| /*************************************************************************** |
| * Copyright (c) 1999-2009, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Tue Nov 17 17:32:36 2009 |
| * MD5 Checksum c5a869a181cd53ce96d34b0e7ab357f3 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7420/rdb/c0/bchp_sun_top_ctrl.h $ |
| * |
| * Hydra_Software_Devel/1 11/17/09 10:13p albertl |
| * SW7420-455: Initial revision. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_SUN_TOP_CTRL_H__ |
| #define BCHP_SUN_TOP_CTRL_H__ |
| |
| /*************************************************************************** |
| *SUN_TOP_CTRL - Top Control registers |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_PROD_REVISION 0x00404000 /* Product Revision ID */ |
| #define BCHP_SUN_TOP_CTRL_SUN_REVISION 0x00404004 /* Sundry Revision ID */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL 0x00404008 /* Reset control */ |
| #define BCHP_SUN_TOP_CTRL_NMI_CTRL 0x00404010 /* Control register for NMI */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET 0x00404014 /* Software reset register */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY 0x00404018 /* Reset history */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0 0x0040401c /* Strapping values */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1 0x00404020 /* Strapping values */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS 0x00404024 /* Bond option value register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0 0x00404028 /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1 0x0040402c /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0 0x00404030 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1 0x00404034 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0 0x00404038 /* Semaphore channel 0 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1 0x0040403c /* Semaphore channel 1 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2 0x00404040 /* Semaphore channel 2 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3 0x00404044 /* Semaphore channel 3 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4 0x00404048 /* Semaphore channel 4 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5 0x0040404c /* Semaphore channel 5 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6 0x00404050 /* Semaphore channel 6 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7 0x00404054 /* Semaphore channel 7 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8 0x00404058 /* Semaphore channel 8 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9 0x0040405c /* Semaphore channel 9 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10 0x00404060 /* Semaphore channel 10 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11 0x00404064 /* Semaphore channel 11 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12 0x00404068 /* Semaphore channel 12 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13 0x0040406c /* Semaphore channel 13 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14 0x00404070 /* Semaphore channel 14 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15 0x00404074 /* Semaphore channel 15 */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0 0x00404078 /* General watchdog timer 0 */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1 0x0040407c /* General watchdog timer 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 0x00404080 /* General control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1 0x00404084 /* General control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2 0x00404088 /* General control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3 0x0040408c /* General control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4 0x00404090 /* General control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5 0x00404094 /* General control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0 0x00404098 /* General status register 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1 0x0040409c /* General status register 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2 0x004040a0 /* General status register 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */ |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH 0x004040bc /* Scratch register */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL 0x004040c0 /* Spare control bits reserved for future use */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x00404100 /* Pinmux control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1 0x00404104 /* Pinmux control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2 0x00404108 /* Pinmux control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3 0x0040410c /* Pinmux control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4 0x00404110 /* Pinmux control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5 0x00404114 /* Pinmux control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6 0x00404118 /* Pinmux control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7 0x0040411c /* Pinmux control register 7 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8 0x00404120 /* Pinmux control register 8 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9 0x00404124 /* Pinmux control register 9 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10 0x00404128 /* Pinmux control register 10 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11 0x0040412c /* Pinmux control register 11 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12 0x00404130 /* Pinmux control register 12 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13 0x00404134 /* Pinmux control register 13 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14 0x00404138 /* Pinmux control register 14 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15 0x0040413c /* Pinmux control register 15 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16 0x00404140 /* Pinmux control register 16 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17 0x00404144 /* Pinmux control register 17 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18 0x00404148 /* Pinmux control register 18 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19 0x0040414c /* Pinmux control register 19 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20 0x00404150 /* Pinmux control register 20 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21 0x00404154 /* Pinmux control register 21 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22 0x00404158 /* Pinmux control register 22 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0 0x00404180 /* Pad pull-up/pull-down control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1 0x00404184 /* Pad pull-up/pull-down control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2 0x00404188 /* Pad pull-up/pull-down control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3 0x0040418c /* Pad pull-up/pull-down control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4 0x00404190 /* Pad pull-up/pull-down control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5 0x00404194 /* Pad pull-up/pull-down control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6 0x00404198 /* Pad pull-up/pull-down control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7 0x0040419c /* Pad pull-up/pull-down control register 7 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8 0x004041a0 /* Pad pull-up/pull-down control register 8 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9 0x004041a4 /* Pad pull-up/pull-down control register 9 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10 0x004041a8 /* Pad pull-up/pull-down control register 10 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11 0x004041ac /* Pad pull-up/pull-down control register 11 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12 0x004041b0 /* Pad pull-up/pull-down control register 12 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13 0x004041b4 /* Pad pull-up/pull-down control register 13 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14 0x004041b8 /* Pad pull-up/pull-down control register 14 */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0 0x004041c0 /* Bypass clock unselect register 0 */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL 0x00404200 /* Test port control */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK 0x00404204 /* Testport peek register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE 0x00404208 /* Testport poke register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK 0x0040420c /* Testport peek register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE 0x00404210 /* Testport poke register */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN 0x00404214 /* EJTAG input bus enables */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL 0x00404218 /* EJTAG output select */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL 0x0040421c /* UART Router select */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG 0x00404300 /* Serial Slave Port configuration register */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV 0x00404320 /* SERS Revision Register */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG 0x00404324 /* SERS Configuration Register */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL 0x00404400 /* Block select for RO testmode */ |
| #define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL 0x00404500 /* Test_mode control register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_MODE 0x00404504 /* Register source for test_mode */ |
| #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE 0x00404508 /* Register source for sub_test_mode */ |
| #define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE 0x0040450c /* Final latched testmode value */ |
| #define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE 0x00404510 /* Final latched sub-testmode value */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL 0x00404600 /* Control register for Power Controller */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS 0x00404604 /* Power Management IRQ input status */ |
| #define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT 0x00404608 /* Power Management Wait counter in place of Wait for MIPS IRQ */ |
| |
| /*************************************************************************** |
| *PROD_REVISION - Product Revision ID |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PROD_REVISION :: product_revision [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_SHIFT 0 |
| |
| /*************************************************************************** |
| *SUN_REVISION - Sundry Revision ID |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SUN_REVISION :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SUN_REVISION :: sundry_revision [15:00] */ |
| #define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_MASK 0x0000ffff |
| #define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_SHIFT 0 |
| |
| /*************************************************************************** |
| *RESET_CTRL - Reset control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_monitor [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_monitor [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_def_val_monitor [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_def_val_monitor_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_def_val_monitor_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: reset_ext_mode_monitor [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_ext_mode_monitor_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_ext_mode_monitor_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: reset_timer_205_monitor [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_205_monitor_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_205_monitor_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: reset_timer_200_monitor [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_200_monitor_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_200_monitor_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [25:12] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK 0x03fff000 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable_lock [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable_lock [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_polarity [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: master_reset_en [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: reserved1 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: sc_insert_reset_en [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_SHIFT 0 |
| |
| /*************************************************************************** |
| *NMI_CTRL - Control register for NMI |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_config_lock_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_config_lock_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: NMI_CTRL :: reserved0 [30:03] */ |
| #define BCHP_SUN_TOP_CTRL_NMI_CTRL_reserved0_MASK 0x7ffffff8 |
| #define BCHP_SUN_TOP_CTRL_NMI_CTRL_reserved0_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_pad_monitor_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_NMI_CTRL_config_nmi_polarity_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_NMI_CTRL_disable_pad_nmi_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_RESET - Software reset register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_RESET :: chip_master_reset [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_1shot [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_1shot [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: pci_rstb_out_sw_reset [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_pci_rstb_out_sw_reset_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_pci_rstb_out_sw_reset_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: top1394_sw_reset [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_top1394_sw_reset_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_top1394_sw_reset_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: avd1_sw_reset [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_avd1_sw_reset_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_avd1_sw_reset_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: avd0_sw_reset [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: aio_sw_reset [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_aio_sw_reset_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_aio_sw_reset_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: rptd_sw_reset [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_rptd_sw_reset_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_rptd_sw_reset_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: spare_sw_reset [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_spare_sw_reset_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_spare_sw_reset_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_level [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: usb_sw_reset [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_usb_sw_reset_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_usb_sw_reset_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: sata_sw_reset [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_sata_sw_reset_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_sata_sw_reset_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: memc_1_sw_reset [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_memc_1_sw_reset_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_memc_1_sw_reset_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: memc_0_sw_reset [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_memc_0_sw_reset_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_memc_0_sw_reset_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: pcie_sw_reset [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_pcie_sw_reset_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_pcie_sw_reset_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: graphics_sw_reset [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_graphics_sw_reset_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_graphics_sw_reset_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: reserved0 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: xpt_sw_reset [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: vec_sw_reset [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_vec_sw_reset_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_vec_sw_reset_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: bvn_sw_reset [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_sw_reset_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_sw_reset_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: hdmi_sw_reset [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_hdmi_sw_reset_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_hdmi_sw_reset_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: moca_sw_reset [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_moca_sw_reset_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_moca_sw_reset_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: ddr1_sw_reset [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_ddr1_sw_reset_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_ddr1_sw_reset_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: ddr0_sw_reset [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_ddr0_sw_reset_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_ddr0_sw_reset_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: rfm_sw_reset [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_rfm_sw_reset_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_rfm_sw_reset_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: jtag_otp_sw_reset [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: enet_sw_reset [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_enet_sw_reset_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_enet_sw_reset_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_level [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: ebi_sw_reset [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_ebi_sw_reset_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_ebi_sw_reset_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: pci_sw_reset [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_pci_sw_reset_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_pci_sw_reset_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SW_RESET :: sundry_sw_reset [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_SHIFT 0 |
| |
| /*************************************************************************** |
| *RESET_HISTORY - Reset history |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:12] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK 0xfffff000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_sft_sft_rst_b [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_hrd_sft_rst_b [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: special_sw_reset [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: reserved1 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0 |
| |
| /*************************************************************************** |
| *STRAP_VALUE_0 - Strapping values |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:12] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK 0xfffff000 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_RSVD_1 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_RSVD_1_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_RSVD_1_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_xtal_adj [10:09] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_adj_MASK 0x00000600 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_adj_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_cpu_freq_0 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_cpu_freq_0_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_cpu_freq_0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_bus_mode [06:05] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_bus_mode_MASK 0x00000060 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_bus_mode_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [04:01] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK 0x0000001e |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 0 |
| |
| /*************************************************************************** |
| *STRAP_VALUE_1 - Strapping values |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:03] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK 0xfffffff8 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *BOND_STATUS - Bond option value register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_0 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pwm_pair_disable [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pwm_pair_disable_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pwm_pair_disable_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_temp_sensor_disable [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_touch_panel_disable [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_touch_panel_disable_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_touch_panel_disable_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rgmii_disable [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rgmii_disable_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rgmii_disable_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_disable [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_3d_gfx_disable [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_3d_gfx_disable_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_3d_gfx_disable_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_uhf_disable [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_uhf_disable_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_pcie_enable [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_pcie_enable_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_pcie_enable_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pcie_disable [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie_disable_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie_disable_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_1394_disable [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_1394_disable_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_1394_disable_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avc1_disable [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc1_disable_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc1_disable_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pwr_ctrl_disable [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pwr_ctrl_disable_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pwr_ctrl_disable_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [12:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK 0x00001800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_pci_ebi [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_pci_ebi_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_pci_ebi_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_hd_display [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_hd_display_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_hd_display_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved1 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_int_daa_disable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_int_daa_disable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_int_daa_disable_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_enable_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_product_id [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_product_id_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_product_id_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_1 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: reserved0 [31:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved0_MASK 0xfe000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved0_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_8 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_8_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_8_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_7 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_7_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_7_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_6 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_6_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_6_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_5 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_5_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_5_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_4 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_4_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_4_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_3 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_3_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_3_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_2 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_2_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_2_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_1 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_1_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_1_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_0 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_0_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: reserved1 [15:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved1_MASK 0x0000fff0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved1_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_2_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_0 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pwm_pair_disable [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pwm_pair_disable_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pwm_pair_disable_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_temp_sensor_disable [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_touch_panel_disable [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_touch_panel_disable_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_touch_panel_disable_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rgmii_disable [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rgmii_disable_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rgmii_disable_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_disable [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_3d_gfx_disable [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_3d_gfx_disable_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_3d_gfx_disable_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_uhf_disable [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_uhf_disable_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_uhf_disable_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_pcie_enable [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_pcie_enable_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_pcie_enable_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pcie_disable [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie_disable_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie_disable_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_1394_disable [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_1394_disable_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_1394_disable_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avc1_disable [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc1_disable_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc1_disable_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pwr_ctrl_disable [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pwr_ctrl_disable_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pwr_ctrl_disable_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [12:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00001800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_pci_ebi [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_pci_ebi_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_pci_ebi_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_hd_display [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_hd_display_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_hd_display_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved1 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_int_daa_disable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_int_daa_disable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_int_daa_disable_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_enable_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_product_id [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_product_id_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_product_id_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_1 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: reserved0 [31:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved0_MASK 0xfe000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved0_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_8 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_8_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_8_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_7 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_7_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_7_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_6 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_6_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_6_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_5 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_5_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_5_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_4 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_4_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_4_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_3 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_3_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_3_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_2 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_2_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_2_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_1 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_1_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_1_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_0 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_0_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: reserved1 [15:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved1_MASK 0x0000fff0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved1_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_2_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_0 - Semaphore channel 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_1 - Semaphore channel 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_2 - Semaphore channel 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_3 - Semaphore channel 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_4 - Semaphore channel 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_5 - Semaphore channel 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_6 - Semaphore channel 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_7 - Semaphore channel 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_8 - Semaphore channel 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_9 - Semaphore channel 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_10 - Semaphore channel 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_11 - Semaphore channel 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_12 - Semaphore channel 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_13 - Semaphore channel 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_14 - Semaphore channel 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_15 - Semaphore channel 15 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT 0 |
| |
| /*************************************************************************** |
| *GEN_WATCHDOG_0 - General watchdog timer 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *GEN_WATCHDOG_1 - General watchdog timer 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_0 - General control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_1 - General control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_10_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: daa_testmode [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_testmode_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_testmode_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: daa_bypass [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_bypass_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_bypass_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_ana_pwrdn [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_ana_pwrdn_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_ana_pwrdn_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_force_sata_mode [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_force_sata_mode_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_force_sata_mode_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_3g_mode [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_3g_mode_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_3g_mode_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_pll_seq_start [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_pll_seq_start_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_pll_seq_start_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_stb_oob [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_stb_oob_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_stb_oob_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_pll_int_ref_clk_sel [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_pll_int_ref_clk_sel_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_pll_int_ref_clk_sel_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_ext_mdio_en [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_ext_mdio_en_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_ext_mdio_en_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved1 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved1_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_2 - General control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_3 - General control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_4 - General control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_5 - General control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_0 - General status register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK 0xfffffff8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_1 - General status register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_2 - General status register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_07 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_07_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_07_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_06 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_06_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_06_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_05 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_05_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_05_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_04 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_04_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_04_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_03 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_03_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_03_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_02 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_02_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_02_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_01 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_01_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_01_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_00 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_00_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_00_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK 0xfff00000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_050 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_050_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_050_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_049 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_049_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_049_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_048 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_048_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_048_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_047 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_047_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_047_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_046 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_046_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_046_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_045 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_045_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_045_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_044 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_044_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_044_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_043 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_043_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_043_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_042 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_042_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_042_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_041 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_041_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_041_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_039 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_039_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_039_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_038 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_038_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_038_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_037 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_037_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_037_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_036 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_036_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_036_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_035 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_035_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_035_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_034 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_034_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_034_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_033 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_033_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_033_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_032 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_032_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_032_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_031 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_031_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_031_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_029 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_029_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_029_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: rgmii_pad_mode [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_rgmii_pad_mode_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_rgmii_pad_mode_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *UNCLEARED_SCRATCH - Scratch register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPARE_CTRL - Spare control bits reserved for future use |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_0 - Pinmux control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad04 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad04_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad04_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad04_PCI_AD04 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad04_ALT_TP_IN_04 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad04_RC_ALT_TP_IN_04 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad03 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad03_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad03_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad03_PCI_AD03 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad03_ALT_TP_IN_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad03_RC_ALT_TP_IN_03 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad02 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad02_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad02_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad02_PCI_AD02 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad02_ALT_TP_IN_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad02_RC_ALT_TP_IN_02 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad01 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad01_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad01_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad01_PCI_AD01 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad01_ALT_TP_IN_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad01_RC_ALT_TP_IN_01 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad00 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad00_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad00_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad00_PCI_AD00 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad00_ALT_TP_IN_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad00_RC_ALT_TP_IN_00 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rmx_sync0 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rmx_sync0_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rmx_sync0_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rmx_sync0_RMX_SYNC0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rmx_sync0_PM_RMX_SYNC0 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rmx_data0 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rmx_data0_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rmx_data0_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rmx_data0_RMX_DATA0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rmx_data0_PM_RMX_DATA0 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: rmx_clk0 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rmx_clk0_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rmx_clk0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rmx_clk0_RMX_CLK0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_rmx_clk0_PM_RMX_CLK0 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_1 - Pinmux control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad12 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad12_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad12_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad12_PCI_AD12 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad12_ALT_TP_IN_12 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad12_RC_ALT_TP_IN_12 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad11 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad11_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad11_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad11_PCI_AD11 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad11_ALT_TP_IN_11 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad11_RC_ALT_TP_IN_11 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad10 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad10_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad10_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad10_PCI_AD10 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad10_ALT_TP_IN_10 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad10_RC_ALT_TP_IN_10 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad09 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad09_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad09_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad09_PCI_AD09 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad09_ALT_TP_IN_09 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad09_RC_ALT_TP_IN_09 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad08 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad08_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad08_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad08_PCI_AD08 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad08_ALT_TP_IN_08 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad08_RC_ALT_TP_IN_08 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad07 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad07_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad07_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad07_PCI_AD07 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad07_ALT_TP_IN_07 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad07_RC_ALT_TP_IN_07 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad06 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad06_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad06_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad06_PCI_AD06 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad06_ALT_TP_IN_06 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad06_RC_ALT_TP_IN_06 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad05 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad05_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad05_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad05_PCI_AD05 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad05_ALT_TP_IN_05 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad05_RC_ALT_TP_IN_05 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_2 - Pinmux control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad20 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad20_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad20_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad20_PCI_AD20 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad20_ALT_TP_IN_20 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad20_RC_ALT_TP_IN_20 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad19 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad19_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad19_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad19_PCI_AD19 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad19_ALT_TP_IN_19 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad19_RC_ALT_TP_IN_19 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad18 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad18_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad18_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad18_PCI_AD18 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad18_ALT_TP_IN_18 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad18_RC_ALT_TP_IN_18 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad17 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad17_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad17_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad17_PCI_AD17 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad17_ALT_TP_IN_17 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad17_RC_ALT_TP_IN_17 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad16 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad16_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad16_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad16_PCI_AD16 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad16_ALT_TP_IN_16 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad16_RC_ALT_TP_IN_16 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad15 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad15_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad15_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad15_PCI_AD15 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad15_ALT_TP_IN_15 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad15_RC_ALT_TP_IN_15 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad14 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad14_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad14_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad14_PCI_AD14 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad14_ALT_TP_IN_14 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad14_RC_ALT_TP_IN_14 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad13 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad13_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad13_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad13_PCI_AD13 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad13_ALT_TP_IN_13 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad13_RC_ALT_TP_IN_13 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_3 - Pinmux control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad28 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad28_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad28_PCI_AD28 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad28_ALT_TP_IN_28 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad28_RC_ALT_TP_IN_28 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad27 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad27_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad27_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad27_PCI_AD27 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad27_ALT_TP_IN_27 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad27_RC_ALT_TP_IN_27 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad26 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad26_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad26_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad26_PCI_AD26 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad26_ALT_TP_OUT_10 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad26_RC_ALT_TP_OUT_10 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad25 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad25_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad25_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad25_PCI_AD25 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad25_ALT_TP_IN_25 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad25_RC_ALT_TP_IN_25 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad24 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad24_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad24_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad24_PCI_AD24 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad24_ALT_TP_IN_24 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad24_RC_ALT_TP_IN_24 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad23 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad23_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad23_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad23_PCI_AD23 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad23_ALT_TP_IN_23 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad23_RC_ALT_TP_IN_23 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad22 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad22_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad22_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad22_PCI_AD22 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad22_ALT_TP_IN_22 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad22_RC_ALT_TP_IN_22 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad21 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad21_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad21_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad21_PCI_AD21 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad21_ALT_TP_IN_21 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad21_RC_ALT_TP_IN_21 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_4 - Pinmux control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr26 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr26_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr26_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr26_EBI_ADDR26 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr26_PM_EBI_ADDR26 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr25 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr25_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr25_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr25_EBI_ADDR25 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr25_PM_EBI_ADDR25 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr24 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr24_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr24_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr24_EBI_ADDR24 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr24_PM_EBI_ADDR24 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_nand_rbb [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_nand_rbb_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_nand_rbb_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_nand_rbb_EBI_NAND_RBB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_nand_rbb_PM_EBI_NAND_RBB 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_ta2b [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_ta2b_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_ta2b_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_ta2b_EBI_TA2B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_ta2b_PM_EBI_TA2B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: pci_ad31 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad31_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad31_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad31_PCI_AD31 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad31_ALT_TP_IN_31 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad31_RC_ALT_TP_IN_31 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: pci_ad30 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad30_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad30_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad30_PCI_AD30 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad30_ALT_TP_OUT_30 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad30_RC_ALT_TP_OUT_30 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: pci_ad29 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad29_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad29_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad29_PCI_AD29 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad29_ALT_TP_IN_29 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad29_RC_ALT_TP_IN_29 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_5 - Pinmux control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_we1b [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_we1b_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_we1b_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_we1b_EBI_WE1B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_we1b_PM_EBI_WE1B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_we0b [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_we0b_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_we0b_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_we0b_EBI_WE0B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_we0b_PM_EBI_WE0B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_rwb [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_rwb_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_rwb_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_rwb_EBI_RWB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_rwb_PM_EBI_RWB 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_cs3b [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs3b_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs3b_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs3b_EBI_CS3B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs3b_PM_EBI_CS3B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_cs2b [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs2b_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs2b_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs2b_EBI_CS2B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs2b_PM_EBI_CS2B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_cs1b [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs1b_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs1b_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs1b_EBI_CS1B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs1b_PM_EBI_CS1B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_cs0b [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs0b_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs0b_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs0b_EBI_CS0B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs0b_PM_EBI_CS0B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr27 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr27_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr27_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr27_EBI_ADDR27 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr27_PM_EBI_ADDR27 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_6 - Pinmux control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ir_in0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ir_in0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ir_in0_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ir_in0_IR_IN0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ir_in0_PM_IR_IN0 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ir_out [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ir_out_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ir_out_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ir_out_IR_OUT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ir_out_PM_IR_OUT 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: daa_aout [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_daa_aout_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_daa_aout_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_daa_aout_DAA_AOUT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_daa_aout_CODEC_SDO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_daa_aout_PM_DAA_AOUT 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_dsb [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_dsb_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_dsb_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_dsb_EBI_DSB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_dsb_PM_EBI_DSB 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_tsb [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsb_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsb_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsb_EBI_TSB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsb_PM_EBI_TSB 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_tsize1b [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsize1b_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsize1b_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsize1b_EBI_TSIZE1B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsize1b_PM_EBI_TSIZE1B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_tsize0b [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsize0b_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsize0b_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsize0b_EBI_TSIZE0B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsize0b_PM_EBI_TSIZE0B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_rdb [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rdb_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rdb_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rdb_EBI_RDB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rdb_PM_EBI_RDB 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_7 - Pinmux control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_007 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_007_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_007_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_007_GPIO_007 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_007_RGMII_RXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_007_UART_RXD_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_007_EXT_IRQB_9 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_007_TP_IN_07 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_007_RC_TP_IN_07 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_006 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_006_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_006_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_006_GPIO_006 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_006_RGMII_RXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_006_UART_RTS_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_006_EXT_IRQB_8 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_006_VEC_HSYNC_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_006_TP_OUT_06 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_006_RC_TP_OUT_06 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_005 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_005_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_005_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_005_GPIO_005 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_005_RGMII_RXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_005_UART_CTS_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_005_EXT_IRQB_7 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_005_VEC_HSYNC_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_005_TP_OUT_05 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_005_RC_TP_OUT_05 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_004 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_GPIO_004 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_RGMII_RXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_UART_TXD_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_EXT_IRQB_6 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_TP_OUT_04 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_004_RC_TP_OUT_04 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_003 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_GPIO_003 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_RGMII_RX_CTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_UART_RXD_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_EXT_IRQB_5 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_TP_IN_03 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_003_RC_TP_IN_03 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_002 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_GPIO_002 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_RGMII_RX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_EXT_IRQB_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_TP_OUT_02 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_002_RC_TP_OUT_02 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_001 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_GPIO_001 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_ENET_LINK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_ENET_ACTIVITY 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_EXT_IRQB_14 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_PM_GPIO_001 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_TP_OUT_01 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_RC_TP_OUT_01 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_000 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_GPIO_000 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_ENET_ACTIVITY 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_ENET_LINK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_EXT_IRQB_13 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_PM_GPIO_000 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_TP_OUT_00 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_RC_TP_OUT_00 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_8 - Pinmux control register 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_015 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_015_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_015_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_015_GPIO_015 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_015_UART_RXD_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_015_UART_RXD_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_015_IR_IN2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_015_UART_RXD_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_015_PM_GPIO_015 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_015_TP_IN_20 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_015_RC_TP_IN_20 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_014 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_014_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_014_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_014_GPIO_014 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_014_RGMII_TXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_014_UART_RTS_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_014_TTX0_DATA 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_014_EXT_IRQB_4 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_014_TP_OUT_14 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_014_RC_TP_OUT_14 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_013 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_013_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_013_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_013_GPIO_013 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_013_RGMII_TXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_013_UART_CTS_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_013_TTX0_REQ 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_013_EXT_IRQB_3 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_013_TP_OUT_13 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_013_RC_TP_OUT_13 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_012 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_GPIO_012 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_RGMII_TXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_UART_TXD_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_EXT_IRQB_12 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_TP_OUT_12 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_012_RC_TP_OUT_12 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_011 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_GPIO_011 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_RGMII_TXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_UART_RXD_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_EXT_IRQB_11 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_TP_IN_11 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_011_RC_TP_IN_11 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_010 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_GPIO_010 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_RGMII_TX_CTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_UART_RTS_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_EXT_IRQB_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_VEC_VSYNC_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_TP_OUT_10 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_010_RC_TP_OUT_10 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_009 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_GPIO_009 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_RGMII_TX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_UART_CTS_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_EXT_IRQB_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_VEC_VSYNC_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_TP_OUT_09 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_RC_TP_OUT_09 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_008 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_GPIO_008 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_UART_TXD_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_UART_TXD_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_EXT_IRQB_10 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_UART_TXD_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_PM_GPIO_008 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_TP_OUT_08 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_RC_TP_OUT_08 7 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_9 - Pinmux control register 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_023 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_023_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_023_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_023_GPIO_023 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_023_IR_IN1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_023_EXT_IRQB_11 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_023_UART_TXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_023_TTX0_DATA 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_023_VEC_VSYNC_1 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_023_PM_GPIO_023 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_023_TP_OUT_23 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_023_RC_TP_OUT_23 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_022 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_022_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_022_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_022_GPIO_022 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_022_IR_INT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_022_NDS_SC_VPP 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_022_UART_RXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_022_TTX0_REQ 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_022_VEC_VSYNC_0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_022_PM_GPIO_022 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_022_TP_IN_22 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_022_RC_TP_IN_22 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_021 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_021_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_021_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_021_GPIO_021 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_021_PWM_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_021_NDS_SC_AUX_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_021_SPI_S_MISO 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_021_VEC_VSYNC_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_021_SC_CLK_OUT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_021_PM_GPIO_021 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_021_TP_OUT_21 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_021_RC_TP_OUT_21 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_020 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_GPIO_020 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_PWM_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_NDS_SC_AUX_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_SPI_S_SS0B 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_VEC_VSYNC_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_SPI_M_SS1B 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_PM_GPIO_020 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_TP_OUT_15 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_020_RC_TP_OUT_15 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_019 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_GPIO_019 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_MOCA_ACTIVITY 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_EXT_IRQB_9 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_SC_CLK_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_PM_GPIO_019 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_TP_OUT_19 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_019_RC_TP_OUT_19 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_018 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_GPIO_018 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_CHIP2POD_MCLKO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_RMXP_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_AUD_FS_CLK1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_EBI_ADDR_15 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_EXT_IRQB_8 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_PM_GPIO_018 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_TP_OUT_18 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_018_RC_TP_OUT_18 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_017 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_GPIO_017 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_MOCA_LINK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_EXT_IRQB_7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_AUD_FS_CLK0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_PM_GPIO_017 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_TP_OUT_17 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_RC_TP_OUT_17 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_016 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_GPIO_016 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_POD2CHIP_MCLKI 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_PPKT_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_IR_IN3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_EBI_ADDR_14 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_EXT_IRQB_6 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_PM_GPIO_016 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_TP_OUT_16 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_RC_TP_OUT_16 8 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_10 - Pinmux control register 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_031 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_031_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_031_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_031_GPIO_031 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_031_POD2CHIP_MDI0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_031_PPKT_DATA0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_031_VO0_656_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_031_LED_LD_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_031_PM_GPIO_031 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_031_TP_OUT_31 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_031_RC_TP_OUT_31 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_030 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_030_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_030_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_030_GPIO_030 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_030_POD2CHIP_MIVAL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_030_PPKT_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_030_VO0_656_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_030_LED_LD_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_030_PM_GPIO_030 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_030_TP_OUT_30 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_030_RC_TP_OUT_30 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_029 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_029_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_029_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_029_GPIO_029 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_029_POD2CHIP_MISTRT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_029_PPKT_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_029_VO0_656_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_029_LED_LD_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_029_PM_GPIO_029 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_029_TP_OUT_29 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_029_RC_TP_OUT_29 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_028 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_GPIO_028 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_CHIP2POD_SCTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_SPI_M_SS0B 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_EBI_ADDR_02 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_PM_GPIO_028 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_TP_OUT_28 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_028_RC_TP_OUT_28 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_027 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_GPIO_027 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_CHIP2POD_SDO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_SPI_M_MISO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_EBI_ADDR_00 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_PM_GPIO_027 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_TP_IN_27 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_027_RC_TP_IN_27 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_026 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_GPIO_026 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_POD2CHIP_SDI 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_SPI_M_MOSI 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_PM_GPIO_026 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_TP_OUT_26 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_026_RC_TP_OUT_26 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_025 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_GPIO_025 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_CHIP2POD_SCLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_SPI_M_SCK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_EBI_ADDR_01 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_PM_GPIO_025 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_TP_OUT_25 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_RC_TP_OUT_25 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_024 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_GPIO_024 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_EXT_IRQB_10 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_BT_CLK_26087 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_PM_GPIO_024 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_TP_IN_24 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_RC_TP_IN_24 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_11 - Pinmux control register 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_039 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_039_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_039_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_039_GPIO_039 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_039_POD2CHIP_MICLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_039_PPKT_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_039_I2S_CLK1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_039_UART_TXD_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_039_EBI_ADDR_13 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_039_PM_GPIO_039 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_039_TP_OUT_07 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_039_RC_TP_OUT_07 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_038 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_038_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_038_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_038_GPIO_038 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_038_POD2CHIP_MDI7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_038_PPKT_DATA7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_038_I2S_LR1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_038_UART_RXD_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_038_PM_GPIO_038 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_038_TP_IN_06 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_038_RC_TP_IN_06 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_037 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_037_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_037_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_037_GPIO_037 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_037_POD2CHIP_MDI6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_037_PPKT_DATA6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_037_I2S_DATA1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_037_VO0_656_CLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_037_PM_GPIO_037 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_037_TP_IN_05 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_037_RC_TP_IN_05 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_036 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_GPIO_036 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_POD2CHIP_MDI5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_PPKT_DATA5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_VO0_656_7 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_LED_LD_7 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_PM_GPIO_036 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_TP_IN_04 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_036_RC_TP_IN_04 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_035 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_GPIO_035 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_POD2CHIP_MDI4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_PPKT_DATA4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_VO0_656_6 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_LED_LD_6 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_PM_GPIO_035 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_TP_OUT_03 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_035_RC_TP_OUT_03 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_034 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_GPIO_034 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_POD2CHIP_MDI3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_PPKT_DATA3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_VO0_656_5 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_LED_LD_5 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_PM_GPIO_034 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_TP_IN_02 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_034_RC_TP_IN_02 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_033 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_GPIO_033 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_POD2CHIP_MDI2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_PPKT_DATA2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_VO0_656_4 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_LED_LD_4 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_PM_GPIO_033 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_TP_IN_01 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_RC_TP_IN_01 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_032 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_GPIO_032 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_POD2CHIP_MDI1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_PPKT_DATA1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_VO0_656_3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_LED_LD_3 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_PM_GPIO_032 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_TP_IN_00 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_RC_TP_IN_00 7 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_12 - Pinmux control register 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_047 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_047_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_047_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_047_GPIO_047 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_047_CHIP2POD_MDO5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_047_RMXP_DATA5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_047_EBI_ADDR_23 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_047_SC_CLK_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_047_CODEC_SCLK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_047_PM_GPIO_047 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_047_TP_IN_15 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_047_RC_TP_IN_15 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_046 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_046_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_046_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_046_GPIO_046 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_046_CHIP2POD_MDO4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_046_RMXP_DATA4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_046_EBI_ADDR_22 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_046_SC_IO_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_046_CODEC_SDI 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_046_PM_GPIO_046 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_046_TP_IN_14 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_046_RC_TP_IN_14 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_045 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_045_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_045_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_045_GPIO_045 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_045_CHIP2POD_MDO3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_045_RMXP_DATA3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_045_EBI_ADDR_21 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_045_NDS_SC_VPP 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_045_PM_GPIO_045 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_045_TP_IN_13 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_045_RC_TP_IN_13 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_044 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_GPIO_044 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_CHIP2POD_MDO2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_RMXP_DATA2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_EBI_ADDR_20 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_NDS_SC_AUX_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_PM_GPIO_044 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_TP_IN_12 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_044_RC_TP_IN_12 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_043 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_GPIO_043 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_CHIP2POD_MDO1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_RMXP_DATA1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_EBI_ADDR_19 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_NDS_SC_AUX_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_PM_GPIO_043 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_TP_OUT_11 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_043_RC_TP_OUT_11 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_042 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_GPIO_042 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_CHIP2POD_MDO0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_RMXP_DATA0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_EBI_ADDR_18 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_PM_GPIO_042 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_TP_IN_10 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_042_RC_TP_IN_10 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_041 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_GPIO_041 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_CHIP2POD_MOSTRT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_RMXP_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_EBI_ADDR_17 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_PM_GPIO_041 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_TP_IN_09 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_RC_TP_IN_09 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_040 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_GPIO_040 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_CHIP2POD_MOVAL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_RMXP_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_EBI_ADDR_16 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_PM_GPIO_040 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_TP_IN_08 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_RC_TP_IN_08 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_13 - Pinmux control register 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_055 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_055_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_055_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_055_GPIO_055 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_055_PKT_ERROR4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_055_VO0_656_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_055_UART_RXD_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_055_HD_DVI0_10 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_055_RMX_PAUSE1 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_055_PM_GPIO_055 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_055_TP_IN_23 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_055_RC_TP_IN_23 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_054 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_054_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_054_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_054_GPIO_054 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_054_PKT_ERROR3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_054_UART_RTS_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_054_EXT_IRQB_3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_054_UHF_LNA_PWRDN 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_054_RMX_PAUSE0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_054_PM_GPIO_054 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_054_TP_OUT_22 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_054_RC_TP_OUT_22 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_053 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_053_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_053_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_053_GPIO_053 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_053_PKT_ERROR2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_053_UART_CTS_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_053_EXT_IRQB_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_053_PM_GPIO_053 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_053_TP_IN_21 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_053_RC_TP_IN_21 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_052 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_GPIO_052 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_PKT_ERROR1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_UART_TXD_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_EXT_IRQB_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_HD_DVI0_CLK_N 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_PM_GPIO_052 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_TP_OUT_20 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_052_RC_TP_OUT_20 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_051 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_GPIO_051 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_PKT_ERROR0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_UART_RXD_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_EXT_IRQB_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_VO0_656_CLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_HD_DVI0_CLK_P 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_051_PM_GPIO_051 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_050 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_GPIO_050 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_CHIP2POD_MOCLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_RMXP_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_EBI_ADDR_12 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_SC_VCC_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_CODEC_MCLK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_PM_GPIO_050 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_TP_IN_18 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_050_RC_TP_IN_18 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_049 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_GPIO_049 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_CHIP2POD_MDO7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_RMXP_DATA7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_EBI_ADDR_25 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_SC_PRES_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_CODEC_SDO 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_PM_GPIO_049 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_TP_IN_17 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_RC_TP_IN_17 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_048 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_GPIO_048 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_CHIP2POD_MDO6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_RMXP_DATA6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_EBI_ADDR_24 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_SC_RST_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_CODEC_FSYNCB 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_PM_GPIO_048 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_TP_IN_16 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_RC_TP_IN_16 8 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_14 - Pinmux control register 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_063 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_063_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_063_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_063_GPIO_063 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_063_PKT_CLK0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_063_PM_GPIO_063 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_063_TP_IN_28 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_063_RC_TP_IN_28 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_062 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_062_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_062_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_062_GPIO_062 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_062_PKT_VALID5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_062_VO0_656_7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_062_UART_TXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_062_HD_DVI0_09 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_062_RMX_CLK1 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_062_UHF_LNA_PWRDN 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_062_PM_GPIO_062 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_062_TP_OUT_27 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_062_RC_TP_OUT_27 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_061 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_061_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_061_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_061_GPIO_061 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_061_PKT_VALID4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_061_VO0_656_6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_061_UART_RXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_061_HD_DVI0_DE 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_061_RMX_DATA1 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_061_PM_GPIO_061 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_061_TP_IN_26 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_061_RC_TP_IN_26 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_060 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_GPIO_060 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_PKT_VALID3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_VO0_656_5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_UART_RTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_HD_DVI0_08 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_VEC_VSYNC_1 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_PM_GPIO_060 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_TP_IN_25 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_060_RC_TP_IN_25 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_059 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_GPIO_059 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_PKT_VALID2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_VO0_656_4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_UART_CTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_HD_DVI0_07 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_VEC_VSYNC_0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_059_PM_GPIO_059 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_058 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_GPIO_058 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_PKT_VALID1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_VO0_656_3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_UART_RTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_HD_DVI0_06 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_TTX0_DATA 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_058_PM_GPIO_058 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_057 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_GPIO_057 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_PKT_VALID0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_VO0_656_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_UART_CTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_HD_DVI0_05 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_TTX0_REQ 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_PM_GPIO_057 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_056 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_GPIO_056 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_PKT_ERROR5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_VO0_656_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_UART_TXD_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_HD_DVI0_04 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_RMX_SYNC1 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_PM_GPIO_056 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_TP_OUT_24 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_RC_TP_OUT_24 8 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_15 - Pinmux control register 15 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_071 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_071_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_071_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_071_GPIO_071 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_071_PKT_DATA2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_071_PM_GPIO_071 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_071_ALT_TP_OUT_04 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_071_RC_ALT_TP_OUT_04 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_070 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_070_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_070_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_070_GPIO_070 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_070_PKT_DATA1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_070_PM_GPIO_070 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_070_ALT_TP_OUT_03 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_070_RC_ALT_TP_OUT_03 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_069 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_069_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_069_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_069_GPIO_069 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_069_PKT_DATA0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_069_PM_GPIO_069 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_069_ALT_TP_OUT_02 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_069_RC_ALT_TP_OUT_02 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_068 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_GPIO_068 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_PKT_CLK5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_HD_DVI0_01 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_EXT_IRQB_6 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_PM_GPIO_068 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_ALT_TP_OUT_01 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_068_RC_ALT_TP_OUT_01 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_067 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_GPIO_067 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_PKT_CLK4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_HD_DVI0_00 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_I2S_CLK0_IN 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_I2S_CLK0_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_EXT_IRQB_5 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_PM_GPIO_067 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_ALT_TP_OUT_00 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_067_RC_ALT_TP_OUT_00 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_066 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_GPIO_066 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_PKT_CLK3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_PM_GPIO_066 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_TP_IN_31 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_066_RC_TP_IN_31 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_065 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_GPIO_065 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_PKT_CLK2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_PM_GPIO_065 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_TP_IN_30 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_RC_TP_IN_30 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_064 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_GPIO_064 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_PKT_CLK1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_PM_GPIO_064 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_TP_IN_29 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_RC_TP_IN_29 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_16 - Pinmux control register 16 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_079 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_079_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_079_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_079_GPIO_079 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_079_PKT_SYNC4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_079_HD_DVI0_VSYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_079_I2S_LR0_IN 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_079_I2S_LR0_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_079_PWM_0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_079_PM_GPIO_079 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_079_ALT_TP_OUT_08 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_079_RC_ALT_TP_OUT_08 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_078 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_078_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_078_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_078_GPIO_078 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_078_PKT_SYNC3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_078_HD_DVI0_11 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_078_PM_GPIO_078 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_078_ALT_TP_OUT_07 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_078_RC_ALT_TP_OUT_07 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_077 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_077_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_077_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_077_GPIO_077 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_077_PKT_SYNC2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_077_PM_GPIO_077 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_076 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_076_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_076_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_076_GPIO_076 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_076_PKT_SYNC1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_076_PM_GPIO_076 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_075 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_075_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_075_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_075_GPIO_075 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_075_PKT_SYNC0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_075_PM_GPIO_075 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_074 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_074_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_074_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_074_GPIO_074 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_074_PKT_DATA5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_074_HD_DVI0_03 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_074_EXT_IRQB_6 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_074_PM_GPIO_074 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_073 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_GPIO_073 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_PKT_DATA4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_HD_DVI0_02 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_I2S_DATA0_IN 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_I2S_DATA0_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_EXT_IRQB_5 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_PM_GPIO_073 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_ALT_TP_OUT_06 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_RC_ALT_TP_OUT_06 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_072 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_GPIO_072 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_PKT_DATA3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_PM_GPIO_072 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_ALT_TP_OUT_05 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_RC_ALT_TP_OUT_05 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_17 - Pinmux control register 17 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_087 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_087_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_087_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_087_GPIO_087 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_087_LED_KD_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_087_I2S_CLK0_IN 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_087_LED_LD_9 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_087_DVO0_VSYNC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_087_I2S_CLK0_OUT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_087_ALT_TP_OUT_16 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_087_RC_ALT_TP_OUT_16 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_086 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_086_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_086_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_086_GPIO_086 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_086_LED_KD_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_086_LED_LD_8 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_086_DVO0_DE 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_086_ALT_TP_OUT_15 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_086_RC_ALT_TP_OUT_15 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_085 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_085_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_085_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_085_GPIO_085 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_085_SC_VCC_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_085_NDS_SC_VCC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_085_EXT_IRQB_4 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_085_PWM_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_085_PM_GPIO_085 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_085_ALT_TP_OUT_14 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_085_RC_ALT_TP_OUT_14 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_084 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_084_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_084_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_084_GPIO_084 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_084_SC_PRES_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_084_NDS_SC_PRES 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_084_EXT_IRQB_3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_084_UART_CTS_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_084_UART_RXD_2 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_084_PM_GPIO_084 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_084_ALT_TP_OUT_13 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_084_RC_ALT_TP_OUT_13 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_083 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_083_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_083_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_083_GPIO_083 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_083_SC_RST_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_083_NDS_SC_RST 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_083_EXT_IRQB_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_083_UART_RTS_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_083_UART_TXD_2 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_083_PM_GPIO_083 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_083_ALT_TP_OUT_12 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_083_RC_ALT_TP_OUT_12 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_082 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_082_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_082_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_082_GPIO_082 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_082_SC_CLK_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_082_NDS_SC_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_082_EXT_IRQB_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_082_UART_TXD_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_082_UART_RTS_2 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_082_PM_GPIO_082 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_082_ALT_TP_OUT_27 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_082_RC_ALT_TP_OUT_27 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_081 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_GPIO_081 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_SC_IO_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_NDS_SC_IO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_EXT_IRQB_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_UART_RXD_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_UART_CTS_2 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_PM_GPIO_081 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_ALT_TP_IN_26 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_RC_ALT_TP_IN_26 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_080 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_GPIO_080 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_PKT_SYNC5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_HD_DVI0_HSYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_PM_GPIO_080 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_ALT_TP_OUT_09 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_RC_ALT_TP_OUT_09 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_18 - Pinmux control register 18 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_095 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_095_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_095_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_095_GPIO_095 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_095_LED_LD_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_095_DVO0_06 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_095_ALT_TP_OUT_24 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_095_RC_ALT_TP_OUT_24 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_094 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_094_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_094_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_094_GPIO_094 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_094_LED_LS_4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_094_DVO0_05 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_094_ALT_TP_OUT_23 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_094_RC_ALT_TP_OUT_23 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_093 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_093_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_093_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_093_GPIO_093 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_093_LED_LS_3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_093_DVO0_04 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_093_ALT_TP_OUT_22 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_093_RC_ALT_TP_OUT_22 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_092 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_092_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_092_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_092_GPIO_092 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_092_LED_LS_2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_092_DVO0_01 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_092_ALT_TP_OUT_21 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_092_RC_ALT_TP_OUT_21 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_091 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_091_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_091_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_091_GPIO_091 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_091_LED_LS_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_091_DVO0_00 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_091_ALT_TP_OUT_20 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_091_RC_ALT_TP_OUT_20 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_090 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_090_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_090_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_090_GPIO_090 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_090_LED_LS_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_090_DVO0_03 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_090_ALT_TP_OUT_19 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_090_RC_ALT_TP_OUT_19 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_089 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_GPIO_089 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_LED_KD_3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_I2S_LR0_IN 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_LED_LD_11 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_DVO0_02 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_I2S_LR0_OUT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_ALT_TP_OUT_18 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_RC_ALT_TP_OUT_18 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_088 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_GPIO_088 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_LED_KD_2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_I2S_DATA0_IN 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_LED_LD_10 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_DVO0_HSYNC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_I2S_DATA0_OUT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_ALT_TP_OUT_17 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_RC_ALT_TP_OUT_17 7 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_19 - Pinmux control register 19 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_103 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_103_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_103_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_103_GPIO_103 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_103_SC_EXT_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_103_EXT_IRQB_4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_103_PM_GPIO_103 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_103_ALT_TP_IN_30 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_103_RC_ALT_TP_IN_30 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_102 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_102_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_102_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_102_GPIO_102 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_102_LED_LD_7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_102_DVO0_CLK_N 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_102_ALT_TP_OUT_31 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_102_RC_ALT_TP_OUT_31 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_101 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_101_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_101_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_101_GPIO_101 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_101_LED_LD_6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_101_DVO0_CLK_P 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_101_TP_IN_19 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_101_RC_TP_IN_19 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_100 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_100_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_100_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_100_GPIO_100 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_100_LED_LD_5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_100_DVO0_11 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_100_ALT_TP_OUT_29 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_100_RC_ALT_TP_OUT_29 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_099 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_099_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_099_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_099_GPIO_099 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_099_LED_LD_4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_099_DVO0_10 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_099_ALT_TP_OUT_28 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_099_RC_ALT_TP_OUT_28 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_098 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_098_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_098_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_098_GPIO_098 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_098_LED_LD_3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_098_DVO0_09 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_098_ALT_TP_OUT_11 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_098_RC_ALT_TP_OUT_11 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_097 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_GPIO_097 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_LED_LD_2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_DVO0_08 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_ALT_TP_OUT_26 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_RC_ALT_TP_OUT_26 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_096 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_GPIO_096 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_LED_LD_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_DVO0_07 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_ALT_TP_OUT_25 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_RC_ALT_TP_OUT_25 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_20 - Pinmux control register 20 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_111 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_111_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_111_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_111_GPIO_111 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_111_CODEC_FSYNCB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_111_NDS_SC_VPP 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_111_MDC_PCIE 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_111_TSPI_RSTB 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_111_EXT_IRQB_13 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_111_PM_GPIO_111 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_110 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_110_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_110_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_110_GPIO_110 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_110_CODEC_SCLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_110_NDS_SC_AUX_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_110_FT_M_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_110_MDIO_PCIE 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_110_TSPI_SCL 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_110_EXT_IRQB_12 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_110_PM_GPIO_110 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_109 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_109_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_109_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_109_GPIO_109 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_109_CODEC_SDI 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_109_NDS_SC_AUX_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_109_FT_M_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_109_MDC_ENET 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_109_TSPI_SSB 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_109_EXT_IRQB_11 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_109_PM_GPIO_109 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_108 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_108_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_108_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_108_GPIO_108 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_108_SC_VCC_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_108_NDS_SC_VCC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_108_MDIO_ENET 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_108_EXT_IRQB_10 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_108_PM_GPIO_108 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_107 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_107_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_107_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_107_GPIO_107 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_107_SC_PRES_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_107_NDS_SC_PRES 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_107_UART_RTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_107_EXT_IRQB_9 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_107_PM_GPIO_107 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_106 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_106_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_106_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_106_GPIO_106 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_106_SC_RST_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_106_NDS_SC_RST 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_106_UART_CTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_106_EXT_IRQB_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_106_PM_GPIO_106 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_105 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_GPIO_105 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_SC_CLK_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_NDS_SC_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_UART_TXD_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_TSPI_MOSI 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_EXT_IRQB_1 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_PM_GPIO_105 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_104 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_GPIO_104 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_SC_IO_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_NDS_SC_IO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_UART_RXD_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_EXT_IRQB_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_PM_GPIO_104 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_21 - Pinmux control register 21 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: sgpio_06 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_06_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_06_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_06_SGPIO_06 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_06_BSC_M3_SCL 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: sgpio_05 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_SGPIO_05 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_BSC_M2_SDA 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: sgpio_04 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_04_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_04_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_04_SGPIO_04 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_04_BSC_M2_SCL 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: sgpio_03 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_03_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_03_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_03_SGPIO_03 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_03_BSC_M1_SDA 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: sgpio_02 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_02_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_02_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_02_SGPIO_02 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_02_BSC_M1_SCL 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: sgpio_01 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_01_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_01_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_01_SGPIO_01 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_01_BSC_M0_SDA 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: sgpio_00 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_00_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_00_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_00_SGPIO_00 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_00_BSC_M0_SCL 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: gpio_112 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_112_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_112_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_112_GPIO_112 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_112_CODEC_MCLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_112_MDIO_SATA 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_112_TSPI_MISO 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_112_EXT_IRQB_14 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_112_PM_GPIO_112 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_22 - Pinmux control register 22 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_22 :: reserved0 [31:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_reserved0_MASK 0xfffff000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_reserved0_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_22 :: sgpio_09 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_09_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_09_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_09_SGPIO_09 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_09_BSC_M4_SDA 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_22 :: sgpio_08 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_08_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_08_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_08_SGPIO_08 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_08_BSC_M4_SCL 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_22 :: sgpio_07 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_07_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_07_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_07_SGPIO_07 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_07_BSC_M3_SDA 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [29:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x3fffffff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK 0x3fffffff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [29:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK 0x3fffffff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_addr26_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr26_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr26_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr26_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr26_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr26_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_addr25_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr25_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr25_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr25_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr25_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr25_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_addr24_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr24_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr24_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr24_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr24_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr24_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved0 [23:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_MASK 0x00ffffff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [29:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK 0x3c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_dsb_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_dsb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_tsb_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_tsize1b_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsize1b_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsize1b_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsize1b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsize1b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsize1b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_tsize0b_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsize0b_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsize0b_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsize0b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsize0b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_tsize0b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_rdb_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_rdb_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_rdb_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_rdb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_rdb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_rdb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_we1b_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_we1b_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_we1b_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_we1b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_we1b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_we1b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_we0b_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_we0b_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_we0b_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_we0b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_we0b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_we0b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_rwb_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_rwb_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_rwb_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_rwb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_rwb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_rwb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_cs3b_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs3b_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs3b_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs3b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs3b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs3b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_cs2b_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs2b_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs2b_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs2b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs2b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs2b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_cs1b_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs1b_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs1b_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs1b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs1b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs1b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_cs0b_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs0b_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs0b_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs0b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs0b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_cs0b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_addr27_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_addr27_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_010_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_010_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_009_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_009_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_008_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_008_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_007_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_007_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_006_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_006_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_005_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_005_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_004_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_004_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_003_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_003_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_002_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_002_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_001_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_000_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_025_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_025_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_024_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_024_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_023_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_023_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_022_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_022_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_021_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_021_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_020_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_020_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_019_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_019_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_018_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_018_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_017_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_017_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_016_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_015_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_014_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_013_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_012_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_011_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_011_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_011_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_011_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_011_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_011_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_040_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_040_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_039_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_039_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_038_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_038_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_037_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_037_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_036_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_036_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_035_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_035_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_034_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_034_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_033_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_033_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_032_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_032_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_031_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_030_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_029_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_028_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_027_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_026_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_055_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_055_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_054_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_054_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_053_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_053_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_052_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_052_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_051_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_051_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_050_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_050_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_049_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_049_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_048_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_048_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_047_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_047_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_046_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_045_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_044_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_043_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_042_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_041_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_070_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_070_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_069_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_069_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_068_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_068_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_067_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_067_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_066_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_066_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_065_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_065_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_064_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_064_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_063_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_063_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_062_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_062_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_061_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_060_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_059_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_058_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_057_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_056_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_085_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_085_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_084_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_084_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_083_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_083_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_082_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_082_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_081_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_081_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_080_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_080_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_079_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_079_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_078_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_078_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_077_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_077_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_076_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_075_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_074_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_073_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_072_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_071_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_100_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_100_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_100_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_100_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_100_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_100_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_099_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_099_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_099_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_099_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_099_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_099_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_098_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_098_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_097_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_097_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_096_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_096_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_095_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_095_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_094_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_094_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_093_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_093_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_092_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_092_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_091_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_090_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_089_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_088_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_087_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_086_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_086_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_086_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_086_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_086_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_086_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_12 - Pad pull-up/pull-down control register 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: spare_pad_ctrl_12 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: reserved0 [29:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_MASK 0x3f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_112_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_112_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_112_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_112_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_112_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_112_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_111_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_111_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_111_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_111_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_111_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_111_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_110_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_110_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_110_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_110_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_110_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_110_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_109_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_109_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_109_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_109_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_109_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_109_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_108_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_108_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_108_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_108_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_108_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_108_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_107_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_107_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_107_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_107_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_107_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_107_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_106_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_106_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_106_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_106_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_106_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_106_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_105_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_105_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_105_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_105_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_105_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_105_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_104_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_104_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_104_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_104_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_104_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_104_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_103_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_103_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_103_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_103_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_103_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_103_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_102_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_102_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_102_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_102_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_102_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_102_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_101_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_101_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_101_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_101_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_101_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_101_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_13 - Pad pull-up/pull-down control register 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: spare_pad_ctrl_13 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: reserved0 [29:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved0_MASK 0x3fffffff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_14 - Pad pull-up/pull-down control register 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_14 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_14 :: spare_pad_ctrl_14 [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_14 :: reserved1 [05:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_reserved1_MASK 0x0000003f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_200_clk [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_200_clk_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_200_clk_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_50_clk [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_50_clk_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_50_clk_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_270_clk [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_270_clk_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_270_clk_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_225_clk [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_225_clk_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_225_clk_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_400_clk [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_400_clk_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_400_clk_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_dsp_clk [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_dsp_clk_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_dsp_clk_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_avd_clk [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_avd_clk_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_avd_clk_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_obsrv_pll [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_obsrv_pll_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_obsrv_pll_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_cpu_clk [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_sys9_clk [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_sys9_clk_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_sys9_clk_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_108 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_108_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_108_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_107 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_107_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_107_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_106 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_106_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_106_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_105 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_105_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_105_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_104 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_104_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_104_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_077 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_077_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_077_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_076 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_076_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_076_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_075 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_075_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_075_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_074 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_074_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_074_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ir_in0 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ir_in0_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ir_in0_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs3b [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs2b [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs2b_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs2b_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_ta2b [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_ta2b_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_ta2b_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pci_gnt2b [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_gnt2b_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_gnt2b_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pci_req2b [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_req2b_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_req2b_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pci_gnt1b [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_gnt1b_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_gnt1b_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pci_req1b [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_req1b_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_req1b_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pci_int_a2 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_int_a2_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_int_a2_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pci_int_a1 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_int_a1_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_int_a1_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_CTRL - Test port control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sundry_local_tp_out_sel [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_0 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_1 1 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_FP_RST_CNT 2 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MISC_TEST 3 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SSP 4 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_OUT_POKE_REG 5 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_IN 6 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UHFR_TP 7 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_DAA_TP 8 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SOFT_MODEM_TP 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_PWR_CTRL_STATUS 10 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_PWR_CTRL_IRQ_IN 11 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UPG_TP_OUT 12 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TOP_AUX_TP_OUT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK 0x0ffffc00 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK 0x00000180 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK 0x0000007f |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_ENET 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU 1 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM 2 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA 3 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF 4 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM 5 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HDMI 6 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE 7 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC 8 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFX 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB 10 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SUN 11 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MAD 12 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT 13 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RPTD 14 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO 15 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0 16 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD1 17 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP 18 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA 19 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCAD 20 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_T1394 21 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0 22 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC1 23 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DDR_APHY0 24 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DDR_APHY1 25 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UNUSED_127 127 |
| |
| /*************************************************************************** |
| *TEST_PORT_OUT_PEEK - Testport peek register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_OUT_POKE - Testport poke register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_IN_PEEK - Testport peek register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_IN_POKE - Testport poke register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *EJTAG_INPUT_EN - EJTAG input bus enables |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AUDIO_ZSP_CPU_ONE_HOT 4 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA_CPU_ONE_HOT 8 |
| |
| /*************************************************************************** |
| *EJTAG_OUTPUT_SEL - EJTAG output select |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK 0xfffffff8 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AUDIO_ZSP_CPU 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA_CPU 3 |
| |
| /*************************************************************************** |
| *UART_ROUTER_SEL - UART Router select |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_ZSP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD1_OL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD1_IL 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_ZSP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD1_OL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD1_IL 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_ZSP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD1_OL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD1_IL 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_ZSP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD1_OL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD1_IL 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_ZSP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD1_OL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD1_IL 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_ZSP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD1_OL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD1_IL 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_ZSP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD1_OL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD1_IL 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_ZSP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD1_OL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD1_IL 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15 |
| |
| /*************************************************************************** |
| *SSP_CONFIG - Serial Slave Port configuration register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK 0xfffff800 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK 0x00000780 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK 0x00000078 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT 0 |
| |
| /*************************************************************************** |
| *SERS_REV - SERS Revision Register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK 0x0000ff00 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT 0 |
| |
| /*************************************************************************** |
| *SERS_CFG - SERS Configuration Register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode 1 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT 27 |
| |
| /* union - case mapped_buffer_mode [26:08] */ |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8 |
| |
| /* union - case cmd_fifo_mode [26:08] */ |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK 0x07c00000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK 0x003e0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK 0x000000fe |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT 0 |
| |
| /*************************************************************************** |
| *SERS_CMD_BUF_%i - Host Serial Write Command Buffer |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE 0x00404328 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END 7 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *SERS_CMD_BUF_%i - Host Serial Write Command Buffer |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT 0 |
| |
| |
| /*************************************************************************** |
| *SERS_STAT_BUF_%i - Host Serial Read Status Buffer |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE 0x00404348 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END 1 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *SERS_STAT_BUF_%i - Host Serial Read Status Buffer |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT 0 |
| |
| |
| /*************************************************************************** |
| *RO_TEST_BLOCK_SEL - Block select for RO testmode |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK 0xffffffe0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [04:03] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x00000018 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_XPT_RO_TEST_ID 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SUN_RO_TEST_ID 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 3 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 4 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_VEC_RO_TEST_ID 5 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_RPTD_RO_TEST_ID 6 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MIPS_RO_TEST_ID 7 |
| |
| /*************************************************************************** |
| *TEST_MODE_CTRL - Test_mode control register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_MODE_CTRL :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: TEST_MODE_CTRL :: use_test_mode_reg_src [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_use_test_mode_reg_src_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_use_test_mode_reg_src_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_MODE - Register source for test_mode |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_MODE :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_MODE :: test_mode [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_SHIFT 0 |
| |
| /*************************************************************************** |
| *SUB_TEST_MODE - Register source for sub_test_mode |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SUB_TEST_MODE :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT 0 |
| |
| /*************************************************************************** |
| *LATCHED_TEST_MODE - Final latched testmode value |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT 0 |
| |
| /*************************************************************************** |
| *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_CTRL - Control register for Power Controller |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_wait_count_upper_bits [31:20] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_count_upper_bits_MASK 0xfff00000 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_count_upper_bits_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_wait_counter_active [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_counter_active_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_counter_active_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_rst_clock_div [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_rst_clock_div_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_rst_clock_div_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_pwrdn_pll_req [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pwrdn_pll_req_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pwrdn_pll_req_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_cml_clocks [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cml_clocks_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cml_clocks_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_all_clocks [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_all_clocks_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_all_clocks_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_cpu_clock [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cpu_clock_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cpu_clock_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_avd_rptd_clock [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_avd_rptd_clock_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_avd_rptd_clock_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_pll_lock [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pll_lock_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pll_lock_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_dram_ready_for_pwrdn [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dram_ready_for_pwrdn_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dram_ready_for_pwrdn_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_bsp_ready_for_pwrdn [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_mips_ready_for_pwrdn [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_mips_ready_for_pwrdn_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_mips_ready_for_pwrdn_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_sec_avd_rptd_clk_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_sec_avd_rptd_clk_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_sec_avd_rptd_clk_disable_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_state [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_ACTIVE 0 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_PWRDN_RDY 1 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_DISABLE_AVD_RPTD 2 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_DISABLE_CPU 3 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_TRANSITION_TO_STANDBY 4 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_STANDBY 5 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_STANDBY_WITH_PLLS_ON 6 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_RESET_216_108_CLKS 7 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_TRANSITION_TO_ACTIVE 8 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_power_ctrl_disable [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_power_ctrl_disable_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_power_ctrl_disable_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_start_pwrdn_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_IRQ_INPUT_STATUS - Power Management IRQ input status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: reserved0 [31:12] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_reserved0_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: spare_wakeup_event_0 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_spare_wakeup_event_0_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_spare_wakeup_event_0_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: ieee_1394_wakeup [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_ieee_1394_wakeup_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_ieee_1394_wakeup_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: cap_wakeup [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_cap_wakeup_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_cap_wakeup_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: wol_enet_wakeup [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_wol_enet_wakeup_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_wol_enet_wakeup_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: wol_moca_wakeup [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_wol_moca_wakeup_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_wol_moca_wakeup_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: uhfr_wakeup [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_uhfr_wakeup_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_uhfr_wakeup_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: gpio_wakeup [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_gpio_wakeup_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_gpio_wakeup_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: nmi_wakeup [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_nmi_wakeup_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_nmi_wakeup_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: timer_wakeup [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_timer_wakeup_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_timer_wakeup_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: kpd_wakeup [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_kpd_wakeup_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_kpd_wakeup_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: irr_wakeup [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_irr_wakeup_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_irr_wakeup_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: cec_wakeup [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_cec_wakeup_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_cec_wakeup_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */ |
| #define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK 0x0000ffff |
| #define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */ |
| |
| /* End of File */ |
