| /*************************************************************************** |
| * Copyright (c) 1999-2009, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Tue Nov 17 18:31:15 2009 |
| * MD5 Checksum c5a869a181cd53ce96d34b0e7ab357f3 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7420/rdb/c0/bchp_memc_ddr23_aphy_ac_1.h $ |
| * |
| * Hydra_Software_Devel/1 11/17/09 9:27p albertl |
| * SW7420-455: Initial revision. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_MEMC_DDR23_APHY_AC_1_H__ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_H__ |
| |
| /*************************************************************************** |
| *MEMC_DDR23_APHY_AC_1 - DDR23 APHY Address Control Registers 1 |
| ***************************************************************************/ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG 0x003c6000 /* DDR23_APHY Config register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_REV_ID 0x003c6004 /* DDR23_APHY Revision ID Register. */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET 0x003c6008 /* DDR soft reset register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_FREQ_CNTL 0x003c600c /* DDR PLL frequency control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG 0x003c6010 /* DDR PLL control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG 0x003c6014 /* DDR PLL control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH1_ADDR_CMD_PHASE_CNTRL 0x003c6018 /* DDR PLL Channel 1 Address phase control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH2_CLOCK_PHASE_CNTRL 0x003c601c /* DDR PLL Channel 2 Clock phase control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH3_WL0_DQ_PHASE_CNTRL 0x003c6020 /* DDR PLL Channel 3 DQ phase control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL 0x003c6024 /* DDR PLL Channel 4 DQS0 phase control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL 0x003c6028 /* DDR PLL Channel 5 DQS1 phase control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH7_WL1_DQ_PHASE_CNTRL 0x003c602c /* DDR PLL Channel 7 DQ phase control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL 0x003c6030 /* DDR PLL Channel 8 DQS0 phase control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL 0x003c6034 /* DDR PLL Channel 9 DQS1 phase control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG 0x003c6038 /* ODT Configuration register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PLL_LOCK_STATUS 0x003c6040 /* DDR PLL lock status register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_POWERDOWN 0x003c6044 /* PLL powerdown register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL 0x003c604c /* Deskew DLL control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_PHASE 0x003c6054 /* Deskew DLL Phase register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_ENABLE 0x003c6058 /* PVT Compensation Controller enable register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_OFFSET_CNTRL 0x003c605c /* PVT Compensation Controller offset control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL 0x003c6060 /* PVT Compensation Controller override control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS 0x003c6064 /* PVT Compensation Controller status register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RX_ODT_CNTRL 0x003c6068 /* "Receive ODT control register" */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_BYPASS_CNTRL 0x003c606c /* Analog macro register bypass control */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PLL_EXT_CLKSEL 0x003c6070 /* DDR PLL external clock select register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_TEST_MODE_CNTRL_REG 0x003c6074 /* DDR23_APHY testport control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_TEST_MODE_CNTRL 0x003c6078 /* Analog test mode control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DISABLE_CHIP_BYPASS_PLL 0x003c607c /* DDR bypass pll mode disable register. */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PAD_SSTL_DDR2_MODE 0x003c6080 /* Pad Mode Control Register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_CLK_DELAY 0x003c6084 /* DDR23_APHY TM1/2 clk delay control */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_VECTOR_MODE_CLK_SEL 0x003c6088 /* DDR vector mode clock select */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL 0x003c608c /* DDR Pad control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_SLEW_CNTRL 0x003c6090 /* DDR Pad slew control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_RX_DRV_CNTRL 0x003c6094 /* DDR Pad Rx power control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_TX_DRV_CNTRL 0x003c6098 /* DDR Pad Tx power control register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_STATUS 0x003c609c /* DDR23_APHY Status Register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DRAM_FIFO_LEVEL 0x003c60a0 /* DRAM FIFO LEVEL register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO 0x003c60a4 /* Command and Data FIFO Status Register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH 0x003c60a8 /* Read Datapath Status Register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_FLAG_BUS 0x003c60ac /* TP_OUT bus value Register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC 0x003c60b0 /* Miscellaneous Register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_SPARE0_RW 0x003c60b4 /* Spare register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_SPARE1_RW 0x003c60b8 /* Spare register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_SPARE0_RO 0x003c60bc /* Spare register */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_SPARE1_RO 0x003c60c0 /* Spare register */ |
| |
| /*************************************************************************** |
| *CONFIG - DDR23_APHY Config register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: CONFIG :: reserved0 [31:26] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_reserved0_MASK 0xfc000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_reserved0_SHIFT 26 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CONFIG :: LRS [25:25] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_LRS_MASK 0x02000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_LRS_SHIFT 25 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CONFIG :: CONFIG_FUNC [24:20] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_CONFIG_FUNC_MASK 0x01f00000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_CONFIG_FUNC_SHIFT 20 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CONFIG :: LAST_READ_LATENCY [19:14] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_LAST_READ_LATENCY_MASK 0x000fc000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_LAST_READ_LATENCY_SHIFT 14 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CONFIG :: READ_LATENCY [13:08] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_READ_LATENCY_MASK 0x00003f00 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_READ_LATENCY_SHIFT 8 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CONFIG :: WRITE_LATENCY [07:03] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_WRITE_LATENCY_MASK 0x000000f8 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_WRITE_LATENCY_SHIFT 3 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CONFIG :: DRAM_WIDTH [02:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_DRAM_WIDTH_MASK 0x00000006 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_DRAM_WIDTH_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CONFIG :: DDR_MODE [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_DDR_MODE_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CONFIG_DDR_MODE_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR23_APHY_REV_ID - DDR23_APHY Revision ID Register. |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DDR23_APHY_REV_ID :: reserved0 [31:16] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_REV_ID_reserved0_MASK 0xffff0000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_REV_ID_reserved0_SHIFT 16 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR23_APHY_REV_ID :: MAJOR_ID [15:08] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_REV_ID_MAJOR_ID_MASK 0x0000ff00 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_REV_ID_MAJOR_ID_SHIFT 8 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR23_APHY_REV_ID :: MINOR_ID [07:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_REV_ID_MINOR_ID_MASK 0x000000ff |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_REV_ID_MINOR_ID_SHIFT 0 |
| |
| /*************************************************************************** |
| *RESET - DDR soft reset register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: RESET :: reserved0 [31:06] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_reserved0_MASK 0xffffffc0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_reserved0_SHIFT 6 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RESET :: RD_DATAPATH_RESET [05:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_RD_DATAPATH_RESET_MASK 0x00000020 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_RD_DATAPATH_RESET_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RESET :: DESKEW_DLL_RESET [04:04] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_DESKEW_DLL_RESET_MASK 0x00000010 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_DESKEW_DLL_RESET_SHIFT 4 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RESET :: FREQ_DIV_RESET [03:03] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_FREQ_DIV_RESET_MASK 0x00000008 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_FREQ_DIV_RESET_SHIFT 3 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RESET :: DATAPATH_216_RESET [02:02] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_DATAPATH_216_RESET_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_DATAPATH_216_RESET_SHIFT 2 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RESET :: DATAPATH_DDR_RESET [01:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_DATAPATH_DDR_RESET_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_DATAPATH_DDR_RESET_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RESET :: VCXO_RESET [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_VCXO_RESET_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RESET_VCXO_RESET_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_FREQ_CNTL - DDR PLL frequency control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_FREQ_CNTL :: reserved0 [31:16] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_FREQ_CNTL_reserved0_MASK 0xffff0000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_FREQ_CNTL_reserved0_SHIFT 16 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_FREQ_CNTL :: NDIV [15:08] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_FREQ_CNTL_NDIV_MASK 0x0000ff00 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_FREQ_CNTL_NDIV_SHIFT 8 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_FREQ_CNTL :: MDIV [07:04] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_FREQ_CNTL_MDIV_MASK 0x000000f0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_FREQ_CNTL_MDIV_SHIFT 4 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_FREQ_CNTL :: PDIV [03:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_FREQ_CNTL_PDIV_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_FREQ_CNTL_PDIV_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CTRL0_REG - DDR PLL control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL0_REG :: PDN_BGR [31:31] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_PDN_BGR_MASK 0x80000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_PDN_BGR_SHIFT 31 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL0_REG :: IBMODE_IBMIN_IBMAX [30:28] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_IBMODE_IBMIN_IBMAX_MASK 0x70000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_IBMODE_IBMIN_IBMAX_SHIFT 28 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL0_REG :: CTATADJ [27:24] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_CTATADJ_MASK 0x0f000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_CTATADJ_SHIFT 24 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL0_REG :: PTATADJ [23:20] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_PTATADJ_MASK 0x00f00000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_PTATADJ_SHIFT 20 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL0_REG :: REFH_REFL [19:18] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_REFH_REFL_MASK 0x000c0000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_REFH_REFL_SHIFT 18 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL0_REG :: VDDR_BGR [17:17] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_VDDR_BGR_MASK 0x00020000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_VDDR_BGR_SHIFT 17 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL0_REG :: WDOG_FREQ_DIS [16:16] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_WDOG_FREQ_DIS_MASK 0x00010000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_WDOG_FREQ_DIS_SHIFT 16 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL0_REG :: KVCO_XS [15:13] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_KVCO_XS_MASK 0x0000e000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_KVCO_XS_SHIFT 13 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL0_REG :: KVCO_XF [12:10] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_KVCO_XF_MASK 0x00001c00 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_KVCO_XF_SHIFT 10 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL0_REG :: LPF_BW [09:08] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_LPF_BW_MASK 0x00000300 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_LPF_BW_SHIFT 8 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL0_REG :: Rz [07:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_Rz_MASK 0x000000e0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_Rz_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL0_REG :: LCPx [04:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_LCPx_MASK 0x0000001f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL0_REG_LCPx_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CTRL1_REG - DDR PLL control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL1_REG :: CTRL1 [31:04] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG_CTRL1_MASK 0xfffffff0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG_CTRL1_SHIFT 4 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL1_REG :: reserved0 [03:03] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG_reserved0_MASK 0x00000008 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG_reserved0_SHIFT 3 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL1_REG :: LDO_PWRDN [02:02] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG_LDO_PWRDN_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG_LDO_PWRDN_SHIFT 2 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CTRL1_REG :: LDO_CTRL [01:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG_LDO_CTRL_MASK 0x00000003 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG_LDO_CTRL_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CH1_ADDR_CMD_PHASE_CNTRL - DDR PLL Channel 1 Address phase control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH1_ADDR_CMD_PHASE_CNTRL :: reserved0 [31:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH1_ADDR_CMD_PHASE_CNTRL_reserved0_MASK 0xffffffe0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH1_ADDR_CMD_PHASE_CNTRL_reserved0_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH1_ADDR_CMD_PHASE_CNTRL :: PHASE_VALUE [04:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH1_ADDR_CMD_PHASE_CNTRL_PHASE_VALUE_MASK 0x0000001f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH1_ADDR_CMD_PHASE_CNTRL_PHASE_VALUE_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CH2_CLOCK_PHASE_CNTRL - DDR PLL Channel 2 Clock phase control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH2_CLOCK_PHASE_CNTRL :: reserved0 [31:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH2_CLOCK_PHASE_CNTRL_reserved0_MASK 0xffffffe0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH2_CLOCK_PHASE_CNTRL_reserved0_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH2_CLOCK_PHASE_CNTRL :: PHASE_VALUE [04:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH2_CLOCK_PHASE_CNTRL_PHASE_VALUE_MASK 0x0000001f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH2_CLOCK_PHASE_CNTRL_PHASE_VALUE_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CH3_WL0_DQ_PHASE_CNTRL - DDR PLL Channel 3 DQ phase control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH3_WL0_DQ_PHASE_CNTRL :: reserved0 [31:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH3_WL0_DQ_PHASE_CNTRL_reserved0_MASK 0xffffffe0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH3_WL0_DQ_PHASE_CNTRL_reserved0_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH3_WL0_DQ_PHASE_CNTRL :: PHASE_VALUE [04:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH3_WL0_DQ_PHASE_CNTRL_PHASE_VALUE_MASK 0x0000001f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH3_WL0_DQ_PHASE_CNTRL_PHASE_VALUE_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CH4_WL0_DQS0_PHASE_CNTRL - DDR PLL Channel 4 DQS0 phase control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH4_WL0_DQS0_PHASE_CNTRL :: reserved0 [31:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL_reserved0_MASK 0xffffffe0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL_reserved0_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH4_WL0_DQS0_PHASE_CNTRL :: PHASE_VALUE [04:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL_PHASE_VALUE_MASK 0x0000001f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL_PHASE_VALUE_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CH5_WL0_DQS1_PHASE_CNTRL - DDR PLL Channel 5 DQS1 phase control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH5_WL0_DQS1_PHASE_CNTRL :: reserved0 [31:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL_reserved0_MASK 0xffffffe0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL_reserved0_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH5_WL0_DQS1_PHASE_CNTRL :: PHASE_VALUE [04:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL_PHASE_VALUE_MASK 0x0000001f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL_PHASE_VALUE_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CH7_WL1_DQ_PHASE_CNTRL - DDR PLL Channel 7 DQ phase control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH7_WL1_DQ_PHASE_CNTRL :: reserved0 [31:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH7_WL1_DQ_PHASE_CNTRL_reserved0_MASK 0xffffffe0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH7_WL1_DQ_PHASE_CNTRL_reserved0_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH7_WL1_DQ_PHASE_CNTRL :: PHASE_VALUE [04:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH7_WL1_DQ_PHASE_CNTRL_PHASE_VALUE_MASK 0x0000001f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH7_WL1_DQ_PHASE_CNTRL_PHASE_VALUE_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CH8_WL1_DQS0_PHASE_CNTRL - DDR PLL Channel 8 DQS0 phase control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH8_WL1_DQS0_PHASE_CNTRL :: reserved0 [31:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL_reserved0_MASK 0xffffffe0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL_reserved0_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH8_WL1_DQS0_PHASE_CNTRL :: PHASE_VALUE [04:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL_PHASE_VALUE_MASK 0x0000001f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL_PHASE_VALUE_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_CH9_WL1_DQS1_PHASE_CNTRL - DDR PLL Channel 9 DQS1 phase control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH9_WL1_DQS1_PHASE_CNTRL :: reserved0 [31:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL_reserved0_MASK 0xffffffe0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL_reserved0_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PLL_CH9_WL1_DQS1_PHASE_CNTRL :: PHASE_VALUE [04:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL_PHASE_VALUE_MASK 0x0000001f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL_PHASE_VALUE_SHIFT 0 |
| |
| /*************************************************************************** |
| *ODT_CONFIG - ODT Configuration register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: ODT_CONFIG :: reserved0 [31:17] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_reserved0_MASK 0xfffe0000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_reserved0_SHIFT 17 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: ODT_CONFIG :: DNP [16:16] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_DNP_MASK 0x00010000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_DNP_SHIFT 16 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: ODT_CONFIG :: DN [15:15] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_DN_MASK 0x00008000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_DN_SHIFT 15 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: ODT_CONFIG :: UP [14:14] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_UP_MASK 0x00004000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_UP_SHIFT 14 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: ODT_CONFIG :: ODT_EST [13:13] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_ODT_EST_MASK 0x00002000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_ODT_EST_SHIFT 13 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: ODT_CONFIG :: STRETCH [12:11] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_STRETCH_MASK 0x00001800 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_STRETCH_SHIFT 11 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: ODT_CONFIG :: EARLY [10:06] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_EARLY_MASK 0x000007c0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_EARLY_SHIFT 6 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: ODT_CONFIG :: DELAY [05:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_DELAY_MASK 0x0000003f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG_DELAY_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR_PLL_LOCK_STATUS - DDR PLL lock status register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PLL_LOCK_STATUS :: LOCK_STATUS [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PLL_LOCK_STATUS_LOCK_STATUS_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PLL_LOCK_STATUS_LOCK_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *POWERDOWN - PLL powerdown register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: POWERDOWN :: reserved0 [31:13] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_POWERDOWN_reserved0_MASK 0xffffe000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_POWERDOWN_reserved0_SHIFT 13 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: POWERDOWN :: FREF_PWRDN [12:12] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_POWERDOWN_FREF_PWRDN_MASK 0x00001000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_POWERDOWN_FREF_PWRDN_SHIFT 12 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: POWERDOWN :: PLLCLKS_OFF_ON_SELFREF [11:11] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_POWERDOWN_PLLCLKS_OFF_ON_SELFREF_MASK 0x00000800 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_POWERDOWN_PLLCLKS_OFF_ON_SELFREF_SHIFT 11 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: POWERDOWN :: LOWPWR_EN [10:10] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_POWERDOWN_LOWPWR_EN_MASK 0x00000400 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_POWERDOWN_LOWPWR_EN_SHIFT 10 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: POWERDOWN :: PWRDN_CML [09:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_POWERDOWN_PWRDN_CML_MASK 0x000003ff |
| #define BCHP_MEMC_DDR23_APHY_AC_1_POWERDOWN_PWRDN_CML_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESKEW_DLL_CNTRL - Deskew DLL control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DESKEW_DLL_CNTRL :: reserved0 [31:17] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL_reserved0_MASK 0xfffe0000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL_reserved0_SHIFT 17 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DESKEW_DLL_CNTRL :: BYPASS_PHASE [16:09] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL_BYPASS_PHASE_MASK 0x0001fe00 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL_BYPASS_PHASE_SHIFT 9 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DESKEW_DLL_CNTRL :: DLL_BYPASS [08:08] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL_DLL_BYPASS_MASK 0x00000100 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL_DLL_BYPASS_SHIFT 8 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DESKEW_DLL_CNTRL :: reserved1 [07:06] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL_reserved1_MASK 0x000000c0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL_reserved1_SHIFT 6 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DESKEW_DLL_CNTRL :: SAMPLE_SEL [05:04] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL_SAMPLE_SEL_MASK 0x00000030 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL_SAMPLE_SEL_SHIFT 4 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DESKEW_DLL_CNTRL :: THRESHOLD [03:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL_THRESHOLD_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL_THRESHOLD_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESKEW_DLL_PHASE - Deskew DLL Phase register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DESKEW_DLL_PHASE :: reserved0 [31:10] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_PHASE_reserved0_MASK 0xfffffc00 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_PHASE_reserved0_SHIFT 10 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DESKEW_DLL_PHASE :: PHASE_DETECTOR_OUTPUT [09:09] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_PHASE_PHASE_DETECTOR_OUTPUT_MASK 0x00000200 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_PHASE_PHASE_DETECTOR_OUTPUT_SHIFT 9 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DESKEW_DLL_PHASE :: PHASE_LOCK_VALUE [08:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_PHASE_PHASE_LOCK_VALUE_MASK 0x000001fe |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_PHASE_PHASE_LOCK_VALUE_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DESKEW_DLL_PHASE :: PHASE_DETECTOR_LOCKED [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_PHASE_PHASE_DETECTOR_LOCKED_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DESKEW_DLL_PHASE_PHASE_DETECTOR_LOCKED_SHIFT 0 |
| |
| /*************************************************************************** |
| *PVT_CONTROLLER_ENABLE - PVT Compensation Controller enable register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_ENABLE_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_ENABLE :: PVT_COMP_EN [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_ENABLE_PVT_COMP_EN_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_ENABLE_PVT_COMP_EN_SHIFT 0 |
| |
| /*************************************************************************** |
| *PVT_CONTROLLER_OFFSET_CNTRL - PVT Compensation Controller offset control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_OFFSET_CNTRL :: reserved0 [31:02] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_OFFSET_CNTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_OFFSET_CNTRL_reserved0_SHIFT 2 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_OFFSET_CNTRL :: PVT_COMP_OFFSET_OP [01:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_OFFSET_CNTRL_PVT_COMP_OFFSET_OP_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_OFFSET_CNTRL_PVT_COMP_OFFSET_OP_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_OFFSET_CNTRL :: PVT_COMP_OFFSET_EN [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_OFFSET_CNTRL_PVT_COMP_OFFSET_EN_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_OFFSET_CNTRL_PVT_COMP_OFFSET_EN_SHIFT 0 |
| |
| /*************************************************************************** |
| *PVT_OVER_RIDE_MODE_CNTRL - PVT Compensation Controller override control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_OVER_RIDE_MODE_CNTRL :: reserved0 [31:12] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL_reserved0_MASK 0xfffff000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL_reserved0_SHIFT 12 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_OVER_RIDE_MODE_CNTRL :: OVER_RIDE_VALUE [11:08] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL_OVER_RIDE_VALUE_MASK 0x00000f00 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL_OVER_RIDE_VALUE_SHIFT 8 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_OVER_RIDE_MODE_CNTRL :: reserved1 [07:07] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL_reserved1_MASK 0x00000080 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL_reserved1_SHIFT 7 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_OVER_RIDE_MODE_CNTRL :: OVER_RIDE_MODE [06:04] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL_OVER_RIDE_MODE_MASK 0x00000070 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL_OVER_RIDE_MODE_SHIFT 4 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_OVER_RIDE_MODE_CNTRL :: reserved2 [03:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL_reserved2_MASK 0x0000000e |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL_reserved2_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_OVER_RIDE_MODE_CNTRL :: OVER_RIDE_EN [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL_OVER_RIDE_EN_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_OVER_RIDE_MODE_CNTRL_OVER_RIDE_EN_SHIFT 0 |
| |
| /*************************************************************************** |
| *PVT_CONTROLLER_STATUS - PVT Compensation Controller status register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: reserved0 [31:26] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_reserved0_MASK 0xfc000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_reserved0_SHIFT 26 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: PVT_CNTRLR_ERROR [25:25] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_CNTRLR_ERROR_MASK 0x02000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_CNTRLR_ERROR_SHIFT 25 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: PVT_CNTRLR_HANG [24:24] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_CNTRLR_HANG_MASK 0x01000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_CNTRLR_HANG_SHIFT 24 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: PVT_CNTRLR_COMP_CODE_INVALID [23:23] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_CNTRLR_COMP_CODE_INVALID_MASK 0x00800000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_CNTRLR_COMP_CODE_INVALID_SHIFT 23 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: PVT_CNTRLR_RCOMP_FILTER_EXPIRED [22:22] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_CNTRLR_RCOMP_FILTER_EXPIRED_MASK 0x00400000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_CNTRLR_RCOMP_FILTER_EXPIRED_SHIFT 22 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: PVT_CNTRLR_NCOMP_FILTER_EXPIRED [21:21] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_CNTRLR_NCOMP_FILTER_EXPIRED_MASK 0x00200000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_CNTRLR_NCOMP_FILTER_EXPIRED_SHIFT 21 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: PVT_CNTRLR_PCOMP_FILTER_EXPIRED [20:20] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_CNTRLR_PCOMP_FILTER_EXPIRED_MASK 0x00100000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_CNTRLR_PCOMP_FILTER_EXPIRED_SHIFT 20 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: PCOMP_CODE [19:16] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PCOMP_CODE_MASK 0x000f0000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PCOMP_CODE_SHIFT 16 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: NCOMP_CODE [15:12] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_NCOMP_CODE_MASK 0x0000f000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_NCOMP_CODE_SHIFT 12 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: reserved1 [11:08] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_reserved1_MASK 0x00000f00 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_reserved1_SHIFT 8 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: PVT_PDONE [07:07] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_PDONE_MASK 0x00000080 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_PDONE_SHIFT 7 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: PVT_NDONE [06:06] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_NDONE_MASK 0x00000040 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_NDONE_SHIFT 6 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: PCOMP_ENB [05:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PCOMP_ENB_MASK 0x00000020 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PCOMP_ENB_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: NCOMP_ENB [04:04] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_NCOMP_ENB_MASK 0x00000010 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_NCOMP_ENB_SHIFT 4 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: reserved2 [03:02] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_reserved2_MASK 0x0000000c |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_reserved2_SHIFT 2 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: PVT_COMP_DONE [01:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_COMP_DONE_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_COMP_DONE_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PVT_CONTROLLER_STATUS :: PVT_COMP_ACK [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_COMP_ACK_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PVT_CONTROLLER_STATUS_PVT_COMP_ACK_SHIFT 0 |
| |
| /*************************************************************************** |
| *RX_ODT_CNTRL - "Receive ODT control register" |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: RX_ODT_CNTRL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RX_ODT_CNTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RX_ODT_CNTRL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RX_ODT_CNTRL :: EXT_CLK_RT60B_OHM [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RX_ODT_CNTRL_EXT_CLK_RT60B_OHM_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RX_ODT_CNTRL_EXT_CLK_RT60B_OHM_SHIFT 0 |
| |
| /*************************************************************************** |
| *ANALOG_BYPASS_CNTRL - Analog macro register bypass control |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: ANALOG_BYPASS_CNTRL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_BYPASS_CNTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_BYPASS_CNTRL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: ANALOG_BYPASS_CNTRL :: BYPASS_PLL [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_BYPASS_CNTRL_BYPASS_PLL_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_BYPASS_CNTRL_BYPASS_PLL_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR_PLL_EXT_CLKSEL - DDR PLL external clock select register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PLL_EXT_CLKSEL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PLL_EXT_CLKSEL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PLL_EXT_CLKSEL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PLL_EXT_CLKSEL :: EXT_CLK_SEL [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_MODE_CNTRL_REG - DDR23_APHY testport control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: TEST_MODE_CNTRL_REG :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_TEST_MODE_CNTRL_REG_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_APHY_AC_1_TEST_MODE_CNTRL_REG_reserved_for_eco0_SHIFT 0 |
| |
| /*************************************************************************** |
| *ANALOG_TEST_MODE_CNTRL - Analog test mode control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: ANALOG_TEST_MODE_CNTRL :: reserved0 [31:16] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_TEST_MODE_CNTRL_reserved0_MASK 0xffff0000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_TEST_MODE_CNTRL_reserved0_SHIFT 16 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: ANALOG_TEST_MODE_CNTRL :: ANALOG_TEST_CNTRL [15:08] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_TEST_MODE_CNTRL_ANALOG_TEST_CNTRL_MASK 0x0000ff00 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_TEST_MODE_CNTRL_ANALOG_TEST_CNTRL_SHIFT 8 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: ANALOG_TEST_MODE_CNTRL :: reserved1 [07:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_TEST_MODE_CNTRL_reserved1_MASK 0x000000fe |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_TEST_MODE_CNTRL_reserved1_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: ANALOG_TEST_MODE_CNTRL :: ANALOG_TEST [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_TEST_MODE_CNTRL_ANALOG_TEST_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_ANALOG_TEST_MODE_CNTRL_ANALOG_TEST_SHIFT 0 |
| |
| /*************************************************************************** |
| *DISABLE_CHIP_BYPASS_PLL - DDR bypass pll mode disable register. |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DISABLE_CHIP_BYPASS_PLL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DISABLE_CHIP_BYPASS_PLL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DISABLE_CHIP_BYPASS_PLL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DISABLE_CHIP_BYPASS_PLL :: DISABLE_BYPASS_PLL [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_SHIFT 0 |
| |
| /*************************************************************************** |
| *PAD_SSTL_DDR2_MODE - Pad Mode Control Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: PAD_SSTL_DDR2_MODE :: reserved0 [31:02] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PAD_SSTL_DDR2_MODE_reserved0_MASK 0xfffffffc |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PAD_SSTL_DDR2_MODE_reserved0_SHIFT 2 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PAD_SSTL_DDR2_MODE :: CMD [01:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PAD_SSTL_DDR2_MODE_CMD_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PAD_SSTL_DDR2_MODE_CMD_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: PAD_SSTL_DDR2_MODE :: CLK [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PAD_SSTL_DDR2_MODE_CLK_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_PAD_SSTL_DDR2_MODE_CLK_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR23_APHY_CLK_DELAY - DDR23_APHY TM1/2 clk delay control |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DDR23_APHY_CLK_DELAY :: reserved0 [31:04] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_CLK_DELAY_reserved0_MASK 0xfffffff0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_CLK_DELAY_reserved0_SHIFT 4 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR23_APHY_CLK_DELAY :: NCDL_CNTRL [03:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_CLK_DELAY_NCDL_CNTRL_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_CLK_DELAY_NCDL_CNTRL_SHIFT 0 |
| |
| /*************************************************************************** |
| *VECTOR_MODE_CLK_SEL - DDR vector mode clock select |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: VECTOR_MODE_CLK_SEL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_VECTOR_MODE_CLK_SEL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_APHY_AC_1_VECTOR_MODE_CLK_SEL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: VECTOR_MODE_CLK_SEL :: SEL [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_VECTOR_MODE_CLK_SEL_SEL_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_VECTOR_MODE_CLK_SEL_SEL_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR_PAD_CNTRL - DDR Pad control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PAD_CNTRL :: reserved0 [31:07] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_reserved0_MASK 0xffffff80 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_reserved0_SHIFT 7 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PAD_CNTRL :: IDDQ_MODE_ON_SELFREF [06:06] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK 0x00000040 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_SHIFT 6 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PAD_CNTRL :: DEVCLK_OFF_ON_SELFREF [05:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_MASK 0x00000020 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PAD_CNTRL :: HIZ_ON_SELFREF [04:04] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_HIZ_ON_SELFREF_MASK 0x00000010 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_HIZ_ON_SELFREF_SHIFT 4 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PAD_CNTRL :: CNTRL [03:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_CNTRL_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_CNTRL_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR_PAD_SLEW_CNTRL - DDR Pad slew control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PAD_SLEW_CNTRL :: reserved0 [31:03] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_SLEW_CNTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_SLEW_CNTRL_reserved0_SHIFT 3 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PAD_SLEW_CNTRL :: SLEW [02:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_SLEW_CNTRL_SLEW_MASK 0x00000007 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_SLEW_CNTRL_SLEW_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR_PAD_RX_DRV_CNTRL - DDR Pad Rx power control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PAD_RX_DRV_CNTRL :: reserved0 [31:03] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_RX_DRV_CNTRL_reserved0_MASK 0xfffffff8 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_RX_DRV_CNTRL_reserved0_SHIFT 3 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PAD_RX_DRV_CNTRL :: RX_DRV [02:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_RX_DRV_CNTRL_RX_DRV_MASK 0x00000007 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_RX_DRV_CNTRL_RX_DRV_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR_PAD_TX_DRV_CNTRL - DDR Pad Tx power control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PAD_TX_DRV_CNTRL :: reserved0 [31:02] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_TX_DRV_CNTRL_reserved0_MASK 0xfffffffc |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_TX_DRV_CNTRL_reserved0_SHIFT 2 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR_PAD_TX_DRV_CNTRL :: TX_DRV [01:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_TX_DRV_CNTRL_TX_DRV_MASK 0x00000003 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_TX_DRV_CNTRL_TX_DRV_SHIFT 0 |
| |
| /*************************************************************************** |
| *DDR23_APHY_STATUS - DDR23_APHY Status Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DDR23_APHY_STATUS :: reserved0 [31:04] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_STATUS_reserved0_SHIFT 4 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR23_APHY_STATUS :: WL0_AND_WL1_RDY_SLIP [03:03] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_STATUS_WL0_AND_WL1_RDY_SLIP_MASK 0x00000008 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_STATUS_WL0_AND_WL1_RDY_SLIP_SHIFT 3 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR23_APHY_STATUS :: WL0_RDY_SLIP [02:02] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_STATUS_WL0_RDY_SLIP_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_STATUS_WL0_RDY_SLIP_SHIFT 2 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR23_APHY_STATUS :: WL1_RDY_SLIP [01:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_STATUS_WL1_RDY_SLIP_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_STATUS_WL1_RDY_SLIP_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DDR23_APHY_STATUS :: READY [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_STATUS_READY_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DDR23_APHY_STATUS_READY_SHIFT 0 |
| |
| /*************************************************************************** |
| *DRAM_FIFO_LEVEL - DRAM FIFO LEVEL register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: DRAM_FIFO_LEVEL :: reserved0 [31:07] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DRAM_FIFO_LEVEL_reserved0_MASK 0xffffff80 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DRAM_FIFO_LEVEL_reserved0_SHIFT 7 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DRAM_FIFO_LEVEL :: VALUE [06:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DRAM_FIFO_LEVEL_VALUE_MASK 0x0000007e |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DRAM_FIFO_LEVEL_VALUE_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: DRAM_FIFO_LEVEL :: ENABLE [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DRAM_FIFO_LEVEL_ENABLE_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_DRAM_FIFO_LEVEL_ENABLE_SHIFT 0 |
| |
| /*************************************************************************** |
| *CMD_DATA_FIFO - Command and Data FIFO Status Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: CMD_DATA_FIFO :: reserved0 [31:27] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_reserved0_MASK 0xf8000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_reserved0_SHIFT 27 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CMD_DATA_FIFO :: CMD_FULL [26:26] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_CMD_FULL_MASK 0x04000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_CMD_FULL_SHIFT 26 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CMD_DATA_FIFO :: FIFO_FULL [25:25] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_FIFO_FULL_MASK 0x02000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_FIFO_FULL_SHIFT 25 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CMD_DATA_FIFO :: FIFO_EMPTY [24:24] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_FIFO_EMPTY_MASK 0x01000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_FIFO_EMPTY_SHIFT 24 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CMD_DATA_FIFO :: CMD_WR_PNTR [23:16] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_CMD_WR_PNTR_MASK 0x00ff0000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_CMD_WR_PNTR_SHIFT 16 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CMD_DATA_FIFO :: CMD_RD_PNTR [15:08] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_CMD_RD_PNTR_MASK 0x0000ff00 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_CMD_RD_PNTR_SHIFT 8 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CMD_DATA_FIFO :: WR_PNTR [07:04] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_WR_PNTR_MASK 0x000000f0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_WR_PNTR_SHIFT 4 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: CMD_DATA_FIFO :: RD_PNTR [03:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_RD_PNTR_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_CMD_DATA_FIFO_RD_PNTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *RD_DATAPATH - Read Datapath Status Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: RD_DATAPATH :: reserved0 [31:28] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_reserved0_MASK 0xf0000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_reserved0_SHIFT 28 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RD_DATAPATH :: F_RDY_3 [27:27] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_F_RDY_3_MASK 0x08000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_F_RDY_3_SHIFT 27 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RD_DATAPATH :: F_RDY_2 [26:26] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_F_RDY_2_MASK 0x04000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_F_RDY_2_SHIFT 26 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RD_DATAPATH :: F_RDY_1 [25:25] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_F_RDY_1_MASK 0x02000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_F_RDY_1_SHIFT 25 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RD_DATAPATH :: F_RDY_0 [24:24] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_F_RDY_0_MASK 0x01000000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_F_RDY_0_SHIFT 24 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RD_DATAPATH :: DWORD3_CNT [23:20] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_DWORD3_CNT_MASK 0x00f00000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_DWORD3_CNT_SHIFT 20 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RD_DATAPATH :: DWORD2_CNT [19:16] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_DWORD2_CNT_MASK 0x000f0000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_DWORD2_CNT_SHIFT 16 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RD_DATAPATH :: DWORD1_CNT [15:12] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_DWORD1_CNT_MASK 0x0000f000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_DWORD1_CNT_SHIFT 12 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RD_DATAPATH :: DWORD0_CNT [11:08] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_DWORD0_CNT_MASK 0x00000f00 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_DWORD0_CNT_SHIFT 8 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RD_DATAPATH :: WR_PNTR [07:04] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_WR_PNTR_MASK 0x000000f0 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_WR_PNTR_SHIFT 4 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: RD_DATAPATH :: RD_PNTR [03:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_RD_PNTR_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_APHY_AC_1_RD_DATAPATH_RD_PNTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *FLAG_BUS - TP_OUT bus value Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: FLAG_BUS :: FLAG_BUS [31:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_FLAG_BUS_FLAG_BUS_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_APHY_AC_1_FLAG_BUS_FLAG_BUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MISC - Miscellaneous Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: reserved_for_eco0 [31:12] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_reserved_for_eco0_MASK 0xfffff000 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_reserved_for_eco0_SHIFT 12 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: WL0_AND_WL1_RDY_SLIP_CLR [11:11] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_WL0_AND_WL1_RDY_SLIP_CLR_MASK 0x00000800 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_WL0_AND_WL1_RDY_SLIP_CLR_SHIFT 11 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: WL0_RDY_SLIP_CLR [10:10] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_WL0_RDY_SLIP_CLR_MASK 0x00000400 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_WL0_RDY_SLIP_CLR_SHIFT 10 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: WL1_RDY_SLIP_CLR [09:09] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_WL1_RDY_SLIP_CLR_MASK 0x00000200 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_WL1_RDY_SLIP_CLR_SHIFT 9 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: FUNC1 [08:08] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_FUNC1_MASK 0x00000100 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_FUNC1_SHIFT 8 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: FUNC0 [07:07] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_FUNC0_MASK 0x00000080 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_FUNC0_SHIFT 7 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: C2IO_INIT_RDY_OVR [06:06] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_C2IO_INIT_RDY_OVR_MASK 0x00000040 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_C2IO_INIT_RDY_OVR_SHIFT 6 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: RD_FIFO_HOLD_CLR [05:05] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_RD_FIFO_HOLD_CLR_MASK 0x00000020 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_RD_FIFO_HOLD_CLR_SHIFT 5 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: CMD_FIFO_HOLD_CLR [04:04] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_CMD_FIFO_HOLD_CLR_MASK 0x00000010 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_CMD_FIFO_HOLD_CLR_SHIFT 4 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: DWORD3_OVERRUN_CLR [03:03] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_DWORD3_OVERRUN_CLR_MASK 0x00000008 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_DWORD3_OVERRUN_CLR_SHIFT 3 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: DWORD2_OVERRUN_CLR [02:02] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_DWORD2_OVERRUN_CLR_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_DWORD2_OVERRUN_CLR_SHIFT 2 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: DWORD1_OVERRUN_CLR [01:01] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_DWORD1_OVERRUN_CLR_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_DWORD1_OVERRUN_CLR_SHIFT 1 |
| |
| /* MEMC_DDR23_APHY_AC_1 :: MISC :: DWORD0_OVERRUN_CLR [00:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_DWORD0_OVERRUN_CLR_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_APHY_AC_1_MISC_DWORD0_OVERRUN_CLR_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPARE0_RW - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: SPARE0_RW :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_SPARE0_RW_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_APHY_AC_1_SPARE0_RW_reserved_for_eco0_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPARE1_RW - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: SPARE1_RW :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_SPARE1_RW_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_APHY_AC_1_SPARE1_RW_reserved_for_eco0_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPARE0_RO - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: SPARE0_RO :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_SPARE0_RO_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_APHY_AC_1_SPARE0_RO_reserved_for_eco0_SHIFT 0 |
| |
| /*************************************************************************** |
| *SPARE1_RO - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_APHY_AC_1 :: SPARE1_RO :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_APHY_AC_1_SPARE1_RO_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_APHY_AC_1_SPARE1_RO_reserved_for_eco0_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_MEMC_DDR23_APHY_AC_1_H__ */ |
| |
| /* End of File */ |
