blob: 62c91044df395bdb54b11671fde2e7bc4d7042f9 [file] [log] [blame]
/***************************************************************************
* Copyright (c) 1999-2009, Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Module Description:
* DO NOT EDIT THIS FILE DIRECTLY
*
* This module was generated magically with RDB from a source description
* file. You must edit the source file for changes to be made to this file.
*
*
* Date: Generated on Tue Nov 17 17:00:30 2009
* MD5 Checksum c5a869a181cd53ce96d34b0e7ab357f3
*
* Compiled with: RDB Utility combo_header.pl
* RDB Parser 3.0
* unknown unknown
* Perl Interpreter 5.008008
* Operating System linux
*
* Revision History:
*
* $brcm_Log: /magnum/basemodules/chp/7420/rdb/c0/bchp_hif_intr2.h $
*
* Hydra_Software_Devel/1 11/17/09 8:56p albertl
* SW7420-455: Initial revision.
*
***************************************************************************/
#ifndef BCHP_HIF_INTR2_H__
#define BCHP_HIF_INTR2_H__
/***************************************************************************
*HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
***************************************************************************/
#define BCHP_HIF_INTR2_CPU_STATUS 0x00441000 /* CPU interrupt Status Register */
#define BCHP_HIF_INTR2_CPU_SET 0x00441004 /* CPU interrupt Set Register */
#define BCHP_HIF_INTR2_CPU_CLEAR 0x00441008 /* CPU interrupt Clear Register */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS 0x0044100c /* CPU interrupt Mask Status Register */
#define BCHP_HIF_INTR2_CPU_MASK_SET 0x00441010 /* CPU interrupt Mask Set Register */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR 0x00441014 /* CPU interrupt Mask Clear Register */
#define BCHP_HIF_INTR2_PCI_STATUS 0x00441018 /* PCI interrupt Status Register */
#define BCHP_HIF_INTR2_PCI_SET 0x0044101c /* PCI interrupt Set Register */
#define BCHP_HIF_INTR2_PCI_CLEAR 0x00441020 /* PCI interrupt Clear Register */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS 0x00441024 /* PCI interrupt Mask Status Register */
#define BCHP_HIF_INTR2_PCI_MASK_SET 0x00441028 /* PCI interrupt Mask Set Register */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR 0x0044102c /* PCI interrupt Mask Clear Register */
/***************************************************************************
*CPU_STATUS - CPU interrupt Status Register
***************************************************************************/
/* HIF_INTR2 :: CPU_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_MASK 0x80000000
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKDOWN_INTR_SHIFT 31
/* HIF_INTR2 :: CPU_STATUS :: PCIE_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_MASK 0x40000000
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_LINKUP_INTR_SHIFT 30
/* HIF_INTR2 :: CPU_STATUS :: EDU_DONE_INTR [29:29] */
#define BCHP_HIF_INTR2_CPU_STATUS_EDU_DONE_INTR_MASK 0x20000000
#define BCHP_HIF_INTR2_CPU_STATUS_EDU_DONE_INTR_SHIFT 29
/* HIF_INTR2 :: CPU_STATUS :: EDU_ERR_INTR [28:28] */
#define BCHP_HIF_INTR2_CPU_STATUS_EDU_ERR_INTR_MASK 0x10000000
#define BCHP_HIF_INTR2_CPU_STATUS_EDU_ERR_INTR_SHIFT 28
/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT 27
/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT 26
/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT 25
/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT 24
/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT 23
/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT 22
/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT 21
/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT 20
/* HIF_INTR2 :: CPU_STATUS :: MICH_INST1_RD_INTR [19:19] */
#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_MASK 0x00080000
#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST1_RD_INTR_SHIFT 19
/* HIF_INTR2 :: CPU_STATUS :: MICH_WR_INTR [18:18] */
#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_MASK 0x00040000
#define BCHP_HIF_INTR2_CPU_STATUS_MICH_WR_INTR_SHIFT 18
/* HIF_INTR2 :: CPU_STATUS :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
/* HIF_INTR2 :: CPU_STATUS :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_CPU_STATUS_EBI_TEA_INTR_SHIFT 16
/* HIF_INTR2 :: CPU_STATUS :: MICH_INST0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_CPU_STATUS_MICH_INST0_RD_INTR_SHIFT 15
/* HIF_INTR2 :: CPU_STATUS :: reserved0 [14:14] */
#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK 0x00004000
#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT 14
/* HIF_INTR2 :: CPU_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT 13
/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR1_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR1_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR1_BRIDGE_INTR_SHIFT 12
/* HIF_INTR2 :: CPU_STATUS :: PCI_RBUS_MSTR_ERR_INTR [11:11] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_RBUS_MSTR_ERR_INTR_MASK 0x00000800
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_RBUS_MSTR_ERR_INTR_SHIFT 11
/* HIF_INTR2 :: CPU_STATUS :: PCI_DMA_DONE [10:10] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_DMA_DONE_MASK 0x00000400
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_DMA_DONE_SHIFT 10
/* HIF_INTR2 :: CPU_STATUS :: PCI_DMA_ERROR [09:09] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_DMA_ERROR_MASK 0x00000200
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_DMA_ERROR_SHIFT 9
/* HIF_INTR2 :: CPU_STATUS :: PCI_SRC_DATA_PERR_INTR [08:08] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_SRC_DATA_PERR_INTR_MASK 0x00000100
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_SRC_DATA_PERR_INTR_SHIFT 8
/* HIF_INTR2 :: CPU_STATUS :: PCI_REC_DATA_PERR_INTR [07:07] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_REC_DATA_PERR_INTR_MASK 0x00000080
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_REC_DATA_PERR_INTR_SHIFT 7
/* HIF_INTR2 :: CPU_STATUS :: PCI_REC_TAR_ABORT_INTR [06:06] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_REC_TAR_ABORT_INTR_MASK 0x00000040
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_REC_TAR_ABORT_INTR_SHIFT 6
/* HIF_INTR2 :: CPU_STATUS :: PCI_REC_MSTR_ABORT_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_REC_MSTR_ABORT_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_REC_MSTR_ABORT_INTR_SHIFT 5
/* HIF_INTR2 :: CPU_STATUS :: PCI_SERR_DET_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_SERR_DET_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_SERR_DET_INTR_SHIFT 4
/* HIF_INTR2 :: CPU_STATUS :: PCI_ADR_PERR_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_ADR_PERR_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_ADR_PERR_INTR_SHIFT 3
/* HIF_INTR2 :: CPU_STATUS :: reserved1 [02:02] */
#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK 0x00000004
#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT 2
/* HIF_INTR2 :: CPU_STATUS :: PCI_RG_BRIDGE_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_RG_BRIDGE_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_CPU_STATUS_PCI_RG_BRIDGE_INTR_SHIFT 1
/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
/***************************************************************************
*CPU_SET - CPU interrupt Set Register
***************************************************************************/
/* HIF_INTR2 :: CPU_SET :: PCIE_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_MASK 0x80000000
#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKDOWN_INTR_SHIFT 31
/* HIF_INTR2 :: CPU_SET :: PCIE_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_MASK 0x40000000
#define BCHP_HIF_INTR2_CPU_SET_PCIE_LINKUP_INTR_SHIFT 30
/* HIF_INTR2 :: CPU_SET :: EDU_DONE_INTR [29:29] */
#define BCHP_HIF_INTR2_CPU_SET_EDU_DONE_INTR_MASK 0x20000000
#define BCHP_HIF_INTR2_CPU_SET_EDU_DONE_INTR_SHIFT 29
/* HIF_INTR2 :: CPU_SET :: EDU_ERR_INTR [28:28] */
#define BCHP_HIF_INTR2_CPU_SET_EDU_ERR_INTR_MASK 0x10000000
#define BCHP_HIF_INTR2_CPU_SET_EDU_ERR_INTR_SHIFT 28
/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT 27
/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT 26
/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT 25
/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT 24
/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT 23
/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT 22
/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT 21
/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT 20
/* HIF_INTR2 :: CPU_SET :: MICH_INST1_RD_INTR [19:19] */
#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_MASK 0x00080000
#define BCHP_HIF_INTR2_CPU_SET_MICH_INST1_RD_INTR_SHIFT 19
/* HIF_INTR2 :: CPU_SET :: MICH_WR_INTR [18:18] */
#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_MASK 0x00040000
#define BCHP_HIF_INTR2_CPU_SET_MICH_WR_INTR_SHIFT 18
/* HIF_INTR2 :: CPU_SET :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_CPU_SET_EBI_TIMEOUT_INTR_SHIFT 17
/* HIF_INTR2 :: CPU_SET :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_CPU_SET_EBI_TEA_INTR_SHIFT 16
/* HIF_INTR2 :: CPU_SET :: MICH_INST0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_CPU_SET_MICH_INST0_RD_INTR_SHIFT 15
/* HIF_INTR2 :: CPU_SET :: reserved0 [14:14] */
#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK 0x00004000
#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT 14
/* HIF_INTR2 :: CPU_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
#define BCHP_HIF_INTR2_CPU_SET_PCIE_RG_BRIDGE_INTR_SHIFT 13
/* HIF_INTR2 :: CPU_SET :: HIF_RGR1_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR1_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR1_BRIDGE_INTR_SHIFT 12
/* HIF_INTR2 :: CPU_SET :: PCI_RBUS_MSTR_ERR_INTR [11:11] */
#define BCHP_HIF_INTR2_CPU_SET_PCI_RBUS_MSTR_ERR_INTR_MASK 0x00000800
#define BCHP_HIF_INTR2_CPU_SET_PCI_RBUS_MSTR_ERR_INTR_SHIFT 11
/* HIF_INTR2 :: CPU_SET :: PCI_DMA_DONE [10:10] */
#define BCHP_HIF_INTR2_CPU_SET_PCI_DMA_DONE_MASK 0x00000400
#define BCHP_HIF_INTR2_CPU_SET_PCI_DMA_DONE_SHIFT 10
/* HIF_INTR2 :: CPU_SET :: PCI_DMA_ERROR [09:09] */
#define BCHP_HIF_INTR2_CPU_SET_PCI_DMA_ERROR_MASK 0x00000200
#define BCHP_HIF_INTR2_CPU_SET_PCI_DMA_ERROR_SHIFT 9
/* HIF_INTR2 :: CPU_SET :: PCI_SRC_DATA_PERR_INTR [08:08] */
#define BCHP_HIF_INTR2_CPU_SET_PCI_SRC_DATA_PERR_INTR_MASK 0x00000100
#define BCHP_HIF_INTR2_CPU_SET_PCI_SRC_DATA_PERR_INTR_SHIFT 8
/* HIF_INTR2 :: CPU_SET :: PCI_REC_DATA_PERR_INTR [07:07] */
#define BCHP_HIF_INTR2_CPU_SET_PCI_REC_DATA_PERR_INTR_MASK 0x00000080
#define BCHP_HIF_INTR2_CPU_SET_PCI_REC_DATA_PERR_INTR_SHIFT 7
/* HIF_INTR2 :: CPU_SET :: PCI_REC_TAR_ABORT_INTR [06:06] */
#define BCHP_HIF_INTR2_CPU_SET_PCI_REC_TAR_ABORT_INTR_MASK 0x00000040
#define BCHP_HIF_INTR2_CPU_SET_PCI_REC_TAR_ABORT_INTR_SHIFT 6
/* HIF_INTR2 :: CPU_SET :: PCI_REC_MSTR_ABORT_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_SET_PCI_REC_MSTR_ABORT_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_CPU_SET_PCI_REC_MSTR_ABORT_INTR_SHIFT 5
/* HIF_INTR2 :: CPU_SET :: PCI_SERR_DET_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_SET_PCI_SERR_DET_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_CPU_SET_PCI_SERR_DET_INTR_SHIFT 4
/* HIF_INTR2 :: CPU_SET :: PCI_ADR_PERR_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_SET_PCI_ADR_PERR_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_SET_PCI_ADR_PERR_INTR_SHIFT 3
/* HIF_INTR2 :: CPU_SET :: reserved1 [02:02] */
#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK 0x00000004
#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT 2
/* HIF_INTR2 :: CPU_SET :: PCI_RG_BRIDGE_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_SET_PCI_RG_BRIDGE_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_CPU_SET_PCI_RG_BRIDGE_INTR_SHIFT 1
/* HIF_INTR2 :: CPU_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
/***************************************************************************
*CPU_CLEAR - CPU interrupt Clear Register
***************************************************************************/
/* HIF_INTR2 :: CPU_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_MASK 0x80000000
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKDOWN_INTR_SHIFT 31
/* HIF_INTR2 :: CPU_CLEAR :: PCIE_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_MASK 0x40000000
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_LINKUP_INTR_SHIFT 30
/* HIF_INTR2 :: CPU_CLEAR :: EDU_DONE_INTR [29:29] */
#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_DONE_INTR_MASK 0x20000000
#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_DONE_INTR_SHIFT 29
/* HIF_INTR2 :: CPU_CLEAR :: EDU_ERR_INTR [28:28] */
#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_ERR_INTR_MASK 0x10000000
#define BCHP_HIF_INTR2_CPU_CLEAR_EDU_ERR_INTR_SHIFT 28
/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT 27
/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT 26
/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT 25
/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT 23
/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT 22
/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT 21
/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT 20
/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST1_RD_INTR [19:19] */
#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_MASK 0x00080000
#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST1_RD_INTR_SHIFT 19
/* HIF_INTR2 :: CPU_CLEAR :: MICH_WR_INTR [18:18] */
#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_MASK 0x00040000
#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_WR_INTR_SHIFT 18
/* HIF_INTR2 :: CPU_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
/* HIF_INTR2 :: CPU_CLEAR :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_CPU_CLEAR_EBI_TEA_INTR_SHIFT 16
/* HIF_INTR2 :: CPU_CLEAR :: MICH_INST0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_CPU_CLEAR_MICH_INST0_RD_INTR_SHIFT 15
/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [14:14] */
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK 0x00004000
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT 14
/* HIF_INTR2 :: CPU_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT 13
/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR1_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR1_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR1_BRIDGE_INTR_SHIFT 12
/* HIF_INTR2 :: CPU_CLEAR :: PCI_RBUS_MSTR_ERR_INTR [11:11] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_RBUS_MSTR_ERR_INTR_MASK 0x00000800
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_RBUS_MSTR_ERR_INTR_SHIFT 11
/* HIF_INTR2 :: CPU_CLEAR :: PCI_DMA_DONE [10:10] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_DMA_DONE_MASK 0x00000400
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_DMA_DONE_SHIFT 10
/* HIF_INTR2 :: CPU_CLEAR :: PCI_DMA_ERROR [09:09] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_DMA_ERROR_MASK 0x00000200
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_DMA_ERROR_SHIFT 9
/* HIF_INTR2 :: CPU_CLEAR :: PCI_SRC_DATA_PERR_INTR [08:08] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_SRC_DATA_PERR_INTR_MASK 0x00000100
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_SRC_DATA_PERR_INTR_SHIFT 8
/* HIF_INTR2 :: CPU_CLEAR :: PCI_REC_DATA_PERR_INTR [07:07] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_REC_DATA_PERR_INTR_MASK 0x00000080
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_REC_DATA_PERR_INTR_SHIFT 7
/* HIF_INTR2 :: CPU_CLEAR :: PCI_REC_TAR_ABORT_INTR [06:06] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_REC_TAR_ABORT_INTR_MASK 0x00000040
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_REC_TAR_ABORT_INTR_SHIFT 6
/* HIF_INTR2 :: CPU_CLEAR :: PCI_REC_MSTR_ABORT_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_REC_MSTR_ABORT_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_REC_MSTR_ABORT_INTR_SHIFT 5
/* HIF_INTR2 :: CPU_CLEAR :: PCI_SERR_DET_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_SERR_DET_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_SERR_DET_INTR_SHIFT 4
/* HIF_INTR2 :: CPU_CLEAR :: PCI_ADR_PERR_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_ADR_PERR_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_ADR_PERR_INTR_SHIFT 3
/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [02:02] */
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK 0x00000004
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT 2
/* HIF_INTR2 :: CPU_CLEAR :: PCI_RG_BRIDGE_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_RG_BRIDGE_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_CPU_CLEAR_PCI_RG_BRIDGE_INTR_SHIFT 1
/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
/***************************************************************************
*CPU_MASK_STATUS - CPU interrupt Mask Status Register
***************************************************************************/
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_MASK 0x80000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKDOWN_INTR_SHIFT 31
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_MASK 0x40000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_LINKUP_INTR_SHIFT 30
/* HIF_INTR2 :: CPU_MASK_STATUS :: EDU_DONE_INTR [29:29] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_DONE_INTR_MASK 0x20000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_DONE_INTR_SHIFT 29
/* HIF_INTR2 :: CPU_MASK_STATUS :: EDU_ERR_INTR [28:28] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_ERR_INTR_MASK 0x10000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EDU_ERR_INTR_SHIFT 28
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT 27
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT 26
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT 25
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT 24
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT 23
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT 22
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT 21
/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT 20
/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_MASK 0x00080000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT 19
/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_WR_INTR [18:18] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_MASK 0x00040000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_WR_INTR_SHIFT 18
/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
/* HIF_INTR2 :: CPU_MASK_STATUS :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_EBI_TEA_INTR_SHIFT 16
/* HIF_INTR2 :: CPU_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT 15
/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [14:14] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK 0x00004000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 14
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT 13
/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR1_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_SHIFT 12
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCI_RBUS_MSTR_ERR_INTR [11:11] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_RBUS_MSTR_ERR_INTR_MASK 0x00000800
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_RBUS_MSTR_ERR_INTR_SHIFT 11
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCI_DMA_DONE [10:10] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_DMA_DONE_MASK 0x00000400
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_DMA_DONE_SHIFT 10
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCI_DMA_ERROR [09:09] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_DMA_ERROR_MASK 0x00000200
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_DMA_ERROR_SHIFT 9
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCI_SRC_DATA_PERR_INTR [08:08] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_SRC_DATA_PERR_INTR_MASK 0x00000100
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_SRC_DATA_PERR_INTR_SHIFT 8
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCI_REC_DATA_PERR_INTR [07:07] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_REC_DATA_PERR_INTR_MASK 0x00000080
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_REC_DATA_PERR_INTR_SHIFT 7
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCI_REC_TAR_ABORT_INTR [06:06] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_REC_TAR_ABORT_INTR_MASK 0x00000040
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_REC_TAR_ABORT_INTR_SHIFT 6
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCI_REC_MSTR_ABORT_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_REC_MSTR_ABORT_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_REC_MSTR_ABORT_INTR_SHIFT 5
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCI_SERR_DET_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_SERR_DET_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_SERR_DET_INTR_SHIFT 4
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCI_ADR_PERR_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_ADR_PERR_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_ADR_PERR_INTR_SHIFT 3
/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [02:02] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK 0x00000004
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT 2
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCI_RG_BRIDGE_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_RG_BRIDGE_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCI_RG_BRIDGE_INTR_SHIFT 1
/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
/***************************************************************************
*CPU_MASK_SET - CPU interrupt Mask Set Register
***************************************************************************/
/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_MASK 0x80000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKDOWN_INTR_SHIFT 31
/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_MASK 0x40000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_LINKUP_INTR_SHIFT 30
/* HIF_INTR2 :: CPU_MASK_SET :: EDU_DONE_INTR [29:29] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_DONE_INTR_MASK 0x20000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_DONE_INTR_SHIFT 29
/* HIF_INTR2 :: CPU_MASK_SET :: EDU_ERR_INTR [28:28] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_ERR_INTR_MASK 0x10000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_EDU_ERR_INTR_SHIFT 28
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT 27
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT 26
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT 25
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT 24
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT 23
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT 22
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT 21
/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT 20
/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_MASK 0x00080000
#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST1_RD_INTR_SHIFT 19
/* HIF_INTR2 :: CPU_MASK_SET :: MICH_WR_INTR [18:18] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_MASK 0x00040000
#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_WR_INTR_SHIFT 18
/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TIMEOUT_INTR_SHIFT 17
/* HIF_INTR2 :: CPU_MASK_SET :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_CPU_MASK_SET_EBI_TEA_INTR_SHIFT 16
/* HIF_INTR2 :: CPU_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_CPU_MASK_SET_MICH_INST0_RD_INTR_SHIFT 15
/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [14:14] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK 0x00004000
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT 14
/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_RG_BRIDGE_INTR_SHIFT 13
/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR1_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR1_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR1_BRIDGE_INTR_SHIFT 12
/* HIF_INTR2 :: CPU_MASK_SET :: PCI_RBUS_MSTR_ERR_INTR [11:11] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_RBUS_MSTR_ERR_INTR_MASK 0x00000800
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_RBUS_MSTR_ERR_INTR_SHIFT 11
/* HIF_INTR2 :: CPU_MASK_SET :: PCI_DMA_DONE [10:10] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_DMA_DONE_MASK 0x00000400
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_DMA_DONE_SHIFT 10
/* HIF_INTR2 :: CPU_MASK_SET :: PCI_DMA_ERROR [09:09] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_DMA_ERROR_MASK 0x00000200
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_DMA_ERROR_SHIFT 9
/* HIF_INTR2 :: CPU_MASK_SET :: PCI_SRC_DATA_PERR_INTR [08:08] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_SRC_DATA_PERR_INTR_MASK 0x00000100
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_SRC_DATA_PERR_INTR_SHIFT 8
/* HIF_INTR2 :: CPU_MASK_SET :: PCI_REC_DATA_PERR_INTR [07:07] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_REC_DATA_PERR_INTR_MASK 0x00000080
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_REC_DATA_PERR_INTR_SHIFT 7
/* HIF_INTR2 :: CPU_MASK_SET :: PCI_REC_TAR_ABORT_INTR [06:06] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_REC_TAR_ABORT_INTR_MASK 0x00000040
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_REC_TAR_ABORT_INTR_SHIFT 6
/* HIF_INTR2 :: CPU_MASK_SET :: PCI_REC_MSTR_ABORT_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_REC_MSTR_ABORT_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_REC_MSTR_ABORT_INTR_SHIFT 5
/* HIF_INTR2 :: CPU_MASK_SET :: PCI_SERR_DET_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_SERR_DET_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_SERR_DET_INTR_SHIFT 4
/* HIF_INTR2 :: CPU_MASK_SET :: PCI_ADR_PERR_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_ADR_PERR_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_ADR_PERR_INTR_SHIFT 3
/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [02:02] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK 0x00000004
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT 2
/* HIF_INTR2 :: CPU_MASK_SET :: PCI_RG_BRIDGE_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_RG_BRIDGE_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCI_RG_BRIDGE_INTR_SHIFT 1
/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
/***************************************************************************
*CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
***************************************************************************/
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_MASK 0x80000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKDOWN_INTR_SHIFT 31
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_MASK 0x40000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_LINKUP_INTR_SHIFT 30
/* HIF_INTR2 :: CPU_MASK_CLEAR :: EDU_DONE_INTR [29:29] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_DONE_INTR_MASK 0x20000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_DONE_INTR_SHIFT 29
/* HIF_INTR2 :: CPU_MASK_CLEAR :: EDU_ERR_INTR [28:28] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_ERR_INTR_MASK 0x10000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EDU_ERR_INTR_SHIFT 28
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT 27
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT 26
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT 25
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT 23
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT 22
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT 21
/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT 20
/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_MASK 0x00080000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT 19
/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_WR_INTR [18:18] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_MASK 0x00040000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_WR_INTR_SHIFT 18
/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
/* HIF_INTR2 :: CPU_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_EBI_TEA_INTR_SHIFT 16
/* HIF_INTR2 :: CPU_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT 15
/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [14:14] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0x00004000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 14
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT 13
/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR1_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_SHIFT 12
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCI_RBUS_MSTR_ERR_INTR [11:11] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_RBUS_MSTR_ERR_INTR_MASK 0x00000800
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_RBUS_MSTR_ERR_INTR_SHIFT 11
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCI_DMA_DONE [10:10] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_DMA_DONE_MASK 0x00000400
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_DMA_DONE_SHIFT 10
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCI_DMA_ERROR [09:09] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_DMA_ERROR_MASK 0x00000200
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_DMA_ERROR_SHIFT 9
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCI_SRC_DATA_PERR_INTR [08:08] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_SRC_DATA_PERR_INTR_MASK 0x00000100
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_SRC_DATA_PERR_INTR_SHIFT 8
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCI_REC_DATA_PERR_INTR [07:07] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_REC_DATA_PERR_INTR_MASK 0x00000080
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_REC_DATA_PERR_INTR_SHIFT 7
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCI_REC_TAR_ABORT_INTR [06:06] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_REC_TAR_ABORT_INTR_MASK 0x00000040
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_REC_TAR_ABORT_INTR_SHIFT 6
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCI_REC_MSTR_ABORT_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_REC_MSTR_ABORT_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_REC_MSTR_ABORT_INTR_SHIFT 5
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCI_SERR_DET_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_SERR_DET_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_SERR_DET_INTR_SHIFT 4
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCI_ADR_PERR_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_ADR_PERR_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_ADR_PERR_INTR_SHIFT 3
/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [02:02] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK 0x00000004
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT 2
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCI_RG_BRIDGE_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_RG_BRIDGE_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCI_RG_BRIDGE_INTR_SHIFT 1
/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
/***************************************************************************
*PCI_STATUS - PCI interrupt Status Register
***************************************************************************/
/* HIF_INTR2 :: PCI_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_MASK 0x80000000
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKDOWN_INTR_SHIFT 31
/* HIF_INTR2 :: PCI_STATUS :: PCIE_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_MASK 0x40000000
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_LINKUP_INTR_SHIFT 30
/* HIF_INTR2 :: PCI_STATUS :: EDU_DONE_INTR [29:29] */
#define BCHP_HIF_INTR2_PCI_STATUS_EDU_DONE_INTR_MASK 0x20000000
#define BCHP_HIF_INTR2_PCI_STATUS_EDU_DONE_INTR_SHIFT 29
/* HIF_INTR2 :: PCI_STATUS :: EDU_ERR_INTR [28:28] */
#define BCHP_HIF_INTR2_PCI_STATUS_EDU_ERR_INTR_MASK 0x10000000
#define BCHP_HIF_INTR2_PCI_STATUS_EDU_ERR_INTR_SHIFT 28
/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT 27
/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT 26
/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT 25
/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT 24
/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT 23
/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT 22
/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT 21
/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT 20
/* HIF_INTR2 :: PCI_STATUS :: MICH_INST1_RD_INTR [19:19] */
#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_MASK 0x00080000
#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST1_RD_INTR_SHIFT 19
/* HIF_INTR2 :: PCI_STATUS :: MICH_WR_INTR [18:18] */
#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_MASK 0x00040000
#define BCHP_HIF_INTR2_PCI_STATUS_MICH_WR_INTR_SHIFT 18
/* HIF_INTR2 :: PCI_STATUS :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
/* HIF_INTR2 :: PCI_STATUS :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_PCI_STATUS_EBI_TEA_INTR_SHIFT 16
/* HIF_INTR2 :: PCI_STATUS :: MICH_INST0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_PCI_STATUS_MICH_INST0_RD_INTR_SHIFT 15
/* HIF_INTR2 :: PCI_STATUS :: reserved0 [14:14] */
#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK 0x00004000
#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT 14
/* HIF_INTR2 :: PCI_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT 13
/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR1_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR1_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR1_BRIDGE_INTR_SHIFT 12
/* HIF_INTR2 :: PCI_STATUS :: PCI_RBUS_MSTR_ERR_INTR [11:11] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_RBUS_MSTR_ERR_INTR_MASK 0x00000800
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_RBUS_MSTR_ERR_INTR_SHIFT 11
/* HIF_INTR2 :: PCI_STATUS :: PCI_DMA_DONE [10:10] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_DMA_DONE_MASK 0x00000400
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_DMA_DONE_SHIFT 10
/* HIF_INTR2 :: PCI_STATUS :: PCI_DMA_ERROR [09:09] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_DMA_ERROR_MASK 0x00000200
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_DMA_ERROR_SHIFT 9
/* HIF_INTR2 :: PCI_STATUS :: PCI_SRC_DATA_PERR_INTR [08:08] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_SRC_DATA_PERR_INTR_MASK 0x00000100
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_SRC_DATA_PERR_INTR_SHIFT 8
/* HIF_INTR2 :: PCI_STATUS :: PCI_REC_DATA_PERR_INTR [07:07] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_REC_DATA_PERR_INTR_MASK 0x00000080
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_REC_DATA_PERR_INTR_SHIFT 7
/* HIF_INTR2 :: PCI_STATUS :: PCI_REC_TAR_ABORT_INTR [06:06] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_REC_TAR_ABORT_INTR_MASK 0x00000040
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_REC_TAR_ABORT_INTR_SHIFT 6
/* HIF_INTR2 :: PCI_STATUS :: PCI_REC_MSTR_ABORT_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_REC_MSTR_ABORT_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_REC_MSTR_ABORT_INTR_SHIFT 5
/* HIF_INTR2 :: PCI_STATUS :: PCI_SERR_DET_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_SERR_DET_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_SERR_DET_INTR_SHIFT 4
/* HIF_INTR2 :: PCI_STATUS :: PCI_ADR_PERR_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_ADR_PERR_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_ADR_PERR_INTR_SHIFT 3
/* HIF_INTR2 :: PCI_STATUS :: reserved1 [02:02] */
#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK 0x00000004
#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT 2
/* HIF_INTR2 :: PCI_STATUS :: PCI_RG_BRIDGE_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_RG_BRIDGE_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_PCI_STATUS_PCI_RG_BRIDGE_INTR_SHIFT 1
/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
/***************************************************************************
*PCI_SET - PCI interrupt Set Register
***************************************************************************/
/* HIF_INTR2 :: PCI_SET :: PCIE_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_MASK 0x80000000
#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKDOWN_INTR_SHIFT 31
/* HIF_INTR2 :: PCI_SET :: PCIE_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_MASK 0x40000000
#define BCHP_HIF_INTR2_PCI_SET_PCIE_LINKUP_INTR_SHIFT 30
/* HIF_INTR2 :: PCI_SET :: EDU_DONE_INTR [29:29] */
#define BCHP_HIF_INTR2_PCI_SET_EDU_DONE_INTR_MASK 0x20000000
#define BCHP_HIF_INTR2_PCI_SET_EDU_DONE_INTR_SHIFT 29
/* HIF_INTR2 :: PCI_SET :: EDU_ERR_INTR [28:28] */
#define BCHP_HIF_INTR2_PCI_SET_EDU_ERR_INTR_MASK 0x10000000
#define BCHP_HIF_INTR2_PCI_SET_EDU_ERR_INTR_SHIFT 28
/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT 27
/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT 26
/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT 25
/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT 24
/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT 23
/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT 22
/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT 21
/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT 20
/* HIF_INTR2 :: PCI_SET :: MICH_INST1_RD_INTR [19:19] */
#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_MASK 0x00080000
#define BCHP_HIF_INTR2_PCI_SET_MICH_INST1_RD_INTR_SHIFT 19
/* HIF_INTR2 :: PCI_SET :: MICH_WR_INTR [18:18] */
#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_MASK 0x00040000
#define BCHP_HIF_INTR2_PCI_SET_MICH_WR_INTR_SHIFT 18
/* HIF_INTR2 :: PCI_SET :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_PCI_SET_EBI_TIMEOUT_INTR_SHIFT 17
/* HIF_INTR2 :: PCI_SET :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_PCI_SET_EBI_TEA_INTR_SHIFT 16
/* HIF_INTR2 :: PCI_SET :: MICH_INST0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_PCI_SET_MICH_INST0_RD_INTR_SHIFT 15
/* HIF_INTR2 :: PCI_SET :: reserved0 [14:14] */
#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK 0x00004000
#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT 14
/* HIF_INTR2 :: PCI_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
#define BCHP_HIF_INTR2_PCI_SET_PCIE_RG_BRIDGE_INTR_SHIFT 13
/* HIF_INTR2 :: PCI_SET :: HIF_RGR1_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR1_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR1_BRIDGE_INTR_SHIFT 12
/* HIF_INTR2 :: PCI_SET :: PCI_RBUS_MSTR_ERR_INTR [11:11] */
#define BCHP_HIF_INTR2_PCI_SET_PCI_RBUS_MSTR_ERR_INTR_MASK 0x00000800
#define BCHP_HIF_INTR2_PCI_SET_PCI_RBUS_MSTR_ERR_INTR_SHIFT 11
/* HIF_INTR2 :: PCI_SET :: PCI_DMA_DONE [10:10] */
#define BCHP_HIF_INTR2_PCI_SET_PCI_DMA_DONE_MASK 0x00000400
#define BCHP_HIF_INTR2_PCI_SET_PCI_DMA_DONE_SHIFT 10
/* HIF_INTR2 :: PCI_SET :: PCI_DMA_ERROR [09:09] */
#define BCHP_HIF_INTR2_PCI_SET_PCI_DMA_ERROR_MASK 0x00000200
#define BCHP_HIF_INTR2_PCI_SET_PCI_DMA_ERROR_SHIFT 9
/* HIF_INTR2 :: PCI_SET :: PCI_SRC_DATA_PERR_INTR [08:08] */
#define BCHP_HIF_INTR2_PCI_SET_PCI_SRC_DATA_PERR_INTR_MASK 0x00000100
#define BCHP_HIF_INTR2_PCI_SET_PCI_SRC_DATA_PERR_INTR_SHIFT 8
/* HIF_INTR2 :: PCI_SET :: PCI_REC_DATA_PERR_INTR [07:07] */
#define BCHP_HIF_INTR2_PCI_SET_PCI_REC_DATA_PERR_INTR_MASK 0x00000080
#define BCHP_HIF_INTR2_PCI_SET_PCI_REC_DATA_PERR_INTR_SHIFT 7
/* HIF_INTR2 :: PCI_SET :: PCI_REC_TAR_ABORT_INTR [06:06] */
#define BCHP_HIF_INTR2_PCI_SET_PCI_REC_TAR_ABORT_INTR_MASK 0x00000040
#define BCHP_HIF_INTR2_PCI_SET_PCI_REC_TAR_ABORT_INTR_SHIFT 6
/* HIF_INTR2 :: PCI_SET :: PCI_REC_MSTR_ABORT_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_SET_PCI_REC_MSTR_ABORT_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_PCI_SET_PCI_REC_MSTR_ABORT_INTR_SHIFT 5
/* HIF_INTR2 :: PCI_SET :: PCI_SERR_DET_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_SET_PCI_SERR_DET_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_PCI_SET_PCI_SERR_DET_INTR_SHIFT 4
/* HIF_INTR2 :: PCI_SET :: PCI_ADR_PERR_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_SET_PCI_ADR_PERR_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_SET_PCI_ADR_PERR_INTR_SHIFT 3
/* HIF_INTR2 :: PCI_SET :: reserved1 [02:02] */
#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK 0x00000004
#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT 2
/* HIF_INTR2 :: PCI_SET :: PCI_RG_BRIDGE_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_SET_PCI_RG_BRIDGE_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_PCI_SET_PCI_RG_BRIDGE_INTR_SHIFT 1
/* HIF_INTR2 :: PCI_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
/***************************************************************************
*PCI_CLEAR - PCI interrupt Clear Register
***************************************************************************/
/* HIF_INTR2 :: PCI_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_MASK 0x80000000
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKDOWN_INTR_SHIFT 31
/* HIF_INTR2 :: PCI_CLEAR :: PCIE_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_MASK 0x40000000
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_LINKUP_INTR_SHIFT 30
/* HIF_INTR2 :: PCI_CLEAR :: EDU_DONE_INTR [29:29] */
#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_DONE_INTR_MASK 0x20000000
#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_DONE_INTR_SHIFT 29
/* HIF_INTR2 :: PCI_CLEAR :: EDU_ERR_INTR [28:28] */
#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_ERR_INTR_MASK 0x10000000
#define BCHP_HIF_INTR2_PCI_CLEAR_EDU_ERR_INTR_SHIFT 28
/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT 27
/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT 26
/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT 25
/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT 23
/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT 22
/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT 21
/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT 20
/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST1_RD_INTR [19:19] */
#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_MASK 0x00080000
#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST1_RD_INTR_SHIFT 19
/* HIF_INTR2 :: PCI_CLEAR :: MICH_WR_INTR [18:18] */
#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_MASK 0x00040000
#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_WR_INTR_SHIFT 18
/* HIF_INTR2 :: PCI_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
/* HIF_INTR2 :: PCI_CLEAR :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_PCI_CLEAR_EBI_TEA_INTR_SHIFT 16
/* HIF_INTR2 :: PCI_CLEAR :: MICH_INST0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_PCI_CLEAR_MICH_INST0_RD_INTR_SHIFT 15
/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [14:14] */
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK 0x00004000
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT 14
/* HIF_INTR2 :: PCI_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT 13
/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR1_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR1_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR1_BRIDGE_INTR_SHIFT 12
/* HIF_INTR2 :: PCI_CLEAR :: PCI_RBUS_MSTR_ERR_INTR [11:11] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_RBUS_MSTR_ERR_INTR_MASK 0x00000800
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_RBUS_MSTR_ERR_INTR_SHIFT 11
/* HIF_INTR2 :: PCI_CLEAR :: PCI_DMA_DONE [10:10] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_DMA_DONE_MASK 0x00000400
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_DMA_DONE_SHIFT 10
/* HIF_INTR2 :: PCI_CLEAR :: PCI_DMA_ERROR [09:09] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_DMA_ERROR_MASK 0x00000200
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_DMA_ERROR_SHIFT 9
/* HIF_INTR2 :: PCI_CLEAR :: PCI_SRC_DATA_PERR_INTR [08:08] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_SRC_DATA_PERR_INTR_MASK 0x00000100
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_SRC_DATA_PERR_INTR_SHIFT 8
/* HIF_INTR2 :: PCI_CLEAR :: PCI_REC_DATA_PERR_INTR [07:07] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_REC_DATA_PERR_INTR_MASK 0x00000080
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_REC_DATA_PERR_INTR_SHIFT 7
/* HIF_INTR2 :: PCI_CLEAR :: PCI_REC_TAR_ABORT_INTR [06:06] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_REC_TAR_ABORT_INTR_MASK 0x00000040
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_REC_TAR_ABORT_INTR_SHIFT 6
/* HIF_INTR2 :: PCI_CLEAR :: PCI_REC_MSTR_ABORT_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_REC_MSTR_ABORT_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_REC_MSTR_ABORT_INTR_SHIFT 5
/* HIF_INTR2 :: PCI_CLEAR :: PCI_SERR_DET_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_SERR_DET_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_SERR_DET_INTR_SHIFT 4
/* HIF_INTR2 :: PCI_CLEAR :: PCI_ADR_PERR_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_ADR_PERR_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_ADR_PERR_INTR_SHIFT 3
/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [02:02] */
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK 0x00000004
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT 2
/* HIF_INTR2 :: PCI_CLEAR :: PCI_RG_BRIDGE_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_RG_BRIDGE_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_PCI_CLEAR_PCI_RG_BRIDGE_INTR_SHIFT 1
/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
/***************************************************************************
*PCI_MASK_STATUS - PCI interrupt Mask Status Register
***************************************************************************/
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_MASK 0x80000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKDOWN_INTR_SHIFT 31
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_MASK 0x40000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_LINKUP_INTR_SHIFT 30
/* HIF_INTR2 :: PCI_MASK_STATUS :: EDU_DONE_INTR [29:29] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_DONE_INTR_MASK 0x20000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_DONE_INTR_SHIFT 29
/* HIF_INTR2 :: PCI_MASK_STATUS :: EDU_ERR_INTR [28:28] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_ERR_INTR_MASK 0x10000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EDU_ERR_INTR_SHIFT 28
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT 27
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT 26
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT 25
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT 24
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT 23
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT 22
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT 21
/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT 20
/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST1_RD_INTR [19:19] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_MASK 0x00080000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST1_RD_INTR_SHIFT 19
/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_WR_INTR [18:18] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_MASK 0x00040000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_WR_INTR_SHIFT 18
/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TIMEOUT_INTR_SHIFT 17
/* HIF_INTR2 :: PCI_MASK_STATUS :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_EBI_TEA_INTR_SHIFT 16
/* HIF_INTR2 :: PCI_MASK_STATUS :: MICH_INST0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_MICH_INST0_RD_INTR_SHIFT 15
/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [14:14] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK 0x00004000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 14
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_RG_BRIDGE_INTR_SHIFT 13
/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR1_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR1_BRIDGE_INTR_SHIFT 12
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCI_RBUS_MSTR_ERR_INTR [11:11] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_RBUS_MSTR_ERR_INTR_MASK 0x00000800
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_RBUS_MSTR_ERR_INTR_SHIFT 11
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCI_DMA_DONE [10:10] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_DMA_DONE_MASK 0x00000400
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_DMA_DONE_SHIFT 10
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCI_DMA_ERROR [09:09] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_DMA_ERROR_MASK 0x00000200
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_DMA_ERROR_SHIFT 9
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCI_SRC_DATA_PERR_INTR [08:08] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_SRC_DATA_PERR_INTR_MASK 0x00000100
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_SRC_DATA_PERR_INTR_SHIFT 8
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCI_REC_DATA_PERR_INTR [07:07] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_REC_DATA_PERR_INTR_MASK 0x00000080
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_REC_DATA_PERR_INTR_SHIFT 7
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCI_REC_TAR_ABORT_INTR [06:06] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_REC_TAR_ABORT_INTR_MASK 0x00000040
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_REC_TAR_ABORT_INTR_SHIFT 6
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCI_REC_MSTR_ABORT_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_REC_MSTR_ABORT_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_REC_MSTR_ABORT_INTR_SHIFT 5
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCI_SERR_DET_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_SERR_DET_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_SERR_DET_INTR_SHIFT 4
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCI_ADR_PERR_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_ADR_PERR_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_ADR_PERR_INTR_SHIFT 3
/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [02:02] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK 0x00000004
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT 2
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCI_RG_BRIDGE_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_RG_BRIDGE_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCI_RG_BRIDGE_INTR_SHIFT 1
/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT 0
/***************************************************************************
*PCI_MASK_SET - PCI interrupt Mask Set Register
***************************************************************************/
/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_MASK 0x80000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKDOWN_INTR_SHIFT 31
/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_MASK 0x40000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_LINKUP_INTR_SHIFT 30
/* HIF_INTR2 :: PCI_MASK_SET :: EDU_DONE_INTR [29:29] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_DONE_INTR_MASK 0x20000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_DONE_INTR_SHIFT 29
/* HIF_INTR2 :: PCI_MASK_SET :: EDU_ERR_INTR [28:28] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_ERR_INTR_MASK 0x10000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_EDU_ERR_INTR_SHIFT 28
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT 27
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT 26
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT 25
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT 24
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT 23
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT 22
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT 21
/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT 20
/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST1_RD_INTR [19:19] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_MASK 0x00080000
#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST1_RD_INTR_SHIFT 19
/* HIF_INTR2 :: PCI_MASK_SET :: MICH_WR_INTR [18:18] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_MASK 0x00040000
#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_WR_INTR_SHIFT 18
/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TIMEOUT_INTR_SHIFT 17
/* HIF_INTR2 :: PCI_MASK_SET :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_PCI_MASK_SET_EBI_TEA_INTR_SHIFT 16
/* HIF_INTR2 :: PCI_MASK_SET :: MICH_INST0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_PCI_MASK_SET_MICH_INST0_RD_INTR_SHIFT 15
/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [14:14] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK 0x00004000
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT 14
/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_RG_BRIDGE_INTR_SHIFT 13
/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR1_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR1_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR1_BRIDGE_INTR_SHIFT 12
/* HIF_INTR2 :: PCI_MASK_SET :: PCI_RBUS_MSTR_ERR_INTR [11:11] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_RBUS_MSTR_ERR_INTR_MASK 0x00000800
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_RBUS_MSTR_ERR_INTR_SHIFT 11
/* HIF_INTR2 :: PCI_MASK_SET :: PCI_DMA_DONE [10:10] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_DMA_DONE_MASK 0x00000400
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_DMA_DONE_SHIFT 10
/* HIF_INTR2 :: PCI_MASK_SET :: PCI_DMA_ERROR [09:09] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_DMA_ERROR_MASK 0x00000200
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_DMA_ERROR_SHIFT 9
/* HIF_INTR2 :: PCI_MASK_SET :: PCI_SRC_DATA_PERR_INTR [08:08] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_SRC_DATA_PERR_INTR_MASK 0x00000100
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_SRC_DATA_PERR_INTR_SHIFT 8
/* HIF_INTR2 :: PCI_MASK_SET :: PCI_REC_DATA_PERR_INTR [07:07] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_REC_DATA_PERR_INTR_MASK 0x00000080
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_REC_DATA_PERR_INTR_SHIFT 7
/* HIF_INTR2 :: PCI_MASK_SET :: PCI_REC_TAR_ABORT_INTR [06:06] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_REC_TAR_ABORT_INTR_MASK 0x00000040
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_REC_TAR_ABORT_INTR_SHIFT 6
/* HIF_INTR2 :: PCI_MASK_SET :: PCI_REC_MSTR_ABORT_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_REC_MSTR_ABORT_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_REC_MSTR_ABORT_INTR_SHIFT 5
/* HIF_INTR2 :: PCI_MASK_SET :: PCI_SERR_DET_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_SERR_DET_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_SERR_DET_INTR_SHIFT 4
/* HIF_INTR2 :: PCI_MASK_SET :: PCI_ADR_PERR_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_ADR_PERR_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_ADR_PERR_INTR_SHIFT 3
/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [02:02] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK 0x00000004
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT 2
/* HIF_INTR2 :: PCI_MASK_SET :: PCI_RG_BRIDGE_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_RG_BRIDGE_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCI_RG_BRIDGE_INTR_SHIFT 1
/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT 0
/***************************************************************************
*PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
***************************************************************************/
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_MASK 0x80000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKDOWN_INTR_SHIFT 31
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_MASK 0x40000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_LINKUP_INTR_SHIFT 30
/* HIF_INTR2 :: PCI_MASK_CLEAR :: EDU_DONE_INTR [29:29] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_DONE_INTR_MASK 0x20000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_DONE_INTR_SHIFT 29
/* HIF_INTR2 :: PCI_MASK_CLEAR :: EDU_ERR_INTR [28:28] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_ERR_INTR_MASK 0x10000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EDU_ERR_INTR_SHIFT 28
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK 0x08000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT 27
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK 0x04000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT 26
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK 0x02000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT 25
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK 0x01000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT 24
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK 0x00800000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT 23
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK 0x00400000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT 22
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK 0x00200000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT 21
/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK 0x00100000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT 20
/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST1_RD_INTR [19:19] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_MASK 0x00080000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST1_RD_INTR_SHIFT 19
/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_WR_INTR [18:18] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_MASK 0x00040000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_WR_INTR_SHIFT 18
/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TIMEOUT_INTR [17:17] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_MASK 0x00020000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TIMEOUT_INTR_SHIFT 17
/* HIF_INTR2 :: PCI_MASK_CLEAR :: EBI_TEA_INTR [16:16] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_MASK 0x00010000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_EBI_TEA_INTR_SHIFT 16
/* HIF_INTR2 :: PCI_MASK_CLEAR :: MICH_INST0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_MASK 0x00008000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_MICH_INST0_RD_INTR_SHIFT 15
/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [14:14] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0x00004000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 14
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_MASK 0x00002000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_RG_BRIDGE_INTR_SHIFT 13
/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR1_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR1_BRIDGE_INTR_SHIFT 12
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCI_RBUS_MSTR_ERR_INTR [11:11] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_RBUS_MSTR_ERR_INTR_MASK 0x00000800
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_RBUS_MSTR_ERR_INTR_SHIFT 11
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCI_DMA_DONE [10:10] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_DMA_DONE_MASK 0x00000400
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_DMA_DONE_SHIFT 10
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCI_DMA_ERROR [09:09] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_DMA_ERROR_MASK 0x00000200
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_DMA_ERROR_SHIFT 9
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCI_SRC_DATA_PERR_INTR [08:08] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_SRC_DATA_PERR_INTR_MASK 0x00000100
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_SRC_DATA_PERR_INTR_SHIFT 8
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCI_REC_DATA_PERR_INTR [07:07] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_REC_DATA_PERR_INTR_MASK 0x00000080
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_REC_DATA_PERR_INTR_SHIFT 7
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCI_REC_TAR_ABORT_INTR [06:06] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_REC_TAR_ABORT_INTR_MASK 0x00000040
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_REC_TAR_ABORT_INTR_SHIFT 6
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCI_REC_MSTR_ABORT_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_REC_MSTR_ABORT_INTR_MASK 0x00000020
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_REC_MSTR_ABORT_INTR_SHIFT 5
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCI_SERR_DET_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_SERR_DET_INTR_MASK 0x00000010
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_SERR_DET_INTR_SHIFT 4
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCI_ADR_PERR_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_ADR_PERR_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_ADR_PERR_INTR_SHIFT 3
/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [02:02] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK 0x00000004
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT 2
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCI_RG_BRIDGE_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_RG_BRIDGE_INTR_MASK 0x00000002
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCI_RG_BRIDGE_INTR_SHIFT 1
/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK 0x00000001
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT 0
#endif /* #ifndef BCHP_HIF_INTR2_H__ */
/* End of File */