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gfiber / kernel / bruno / 4d4d3690f437ffb94a26d3af54ccb7110373dede / . / arch / mips / include / asm / brcmstb / 7420c0 / bchp_clk.h
blob: f6c3b871c1e711fe3a653acdf963031002549941 [file] [log] [blame]
/***************************************************************************
* Copyright (c) 1999-2009, Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Module Description:
* DO NOT EDIT THIS FILE DIRECTLY
*
* This module was generated magically with RDB from a source description
* file. You must edit the source file for changes to be made to this file.
*
*
* Date: Generated on Tue Nov 17 17:30:42 2009
* MD5 Checksum c5a869a181cd53ce96d34b0e7ab357f3
*
* Compiled with: RDB Utility combo_header.pl
* RDB Parser 3.0
* unknown unknown
* Perl Interpreter 5.008008
* Operating System linux
*
* Revision History:
*
* $brcm_Log: /magnum/basemodules/chp/7420/rdb/c0/bchp_clk.h $
*
* Hydra_Software_Devel/1 11/17/09 8:13p albertl
* SW7420-455: Initial revision.
*
***************************************************************************/
#ifndef BCHP_CLK_H__
#define BCHP_CLK_H__
/***************************************************************************
*CLK - CLOCK_GEN Registers
***************************************************************************/
#define BCHP_CLK_REVISION 0x00462000 /* clock_gen Revision register */
#define BCHP_CLK_BVN_EDGE_PM_CTRL 0x00462004 /* Software power management control to turn off BVN_EDGE system 216/108 MHz clocks */
#define BCHP_CLK_BVN_MCVP_PM_CTRL 0x00462008 /* Software power management control to turn off BVN_MCVP system 216/108 MHz clocks */
#define BCHP_CLK_BVN_MIDDLE_PM_CTRL 0x0046200c /* Software power management control to turn off BVN_MIDDLE system 216/108 MHz clocks */
#define BCHP_CLK_DDR23_APHY_0_PM_CTRL 0x00462010 /* Software power management control to turn off DDR23_APHY_0 system 216/108 MHz clocks */
#define BCHP_CLK_DDR23_APHY_1_PM_CTRL 0x00462014 /* Software power management control to turn off DDR23_APHY_1 system 216/108 MHz clocks */
#define BCHP_CLK_GFX_3D_PM_CTRL 0x00462018 /* Software power management control to turn off GFX_3D system 216/108 MHz clocks */
#define BCHP_CLK_GFX_2D_PM_CTRL 0x0046201c /* Software power management control to turn off GFX_2D system 216/108 MHz clocks */
#define BCHP_CLK_MEMC_0_PM_CTRL 0x00462020 /* Software power management control to turn off MEMC_0 system 216/108 MHz clocks */
#define BCHP_CLK_MEMC_1_PM_CTRL 0x00462024 /* Software power management control to turn off MEMC_1 system 216/108 MHz clocks */
#define BCHP_CLK_SECTOP_DMA_PM_CTRL 0x00462028 /* Software power management control to turn off SECTOP DMA 216 MHz clocks */
#define BCHP_CLK_USB_PM_CTRL 0x0046202c /* Software power management control to turn off USB system 216/108 MHz clocks */
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL 0x00462030 /* Software power management control to turn off DVP_HT clocks */
#define BCHP_CLK_TOP1394_CLK_PM_CTRL 0x00462034 /* Software power management control to turn off TOP1394 216/108, 27 MHz clocks */
#define BCHP_CLK_MOCA_CLK_PM_CTRL 0x00462038 /* Software power management control to turn off MOCA clocks */
#define BCHP_CLK_RPT_AIO_CLK_PM_CTRL 0x0046203c /* Software power management control to turn off RPT_AIO clocks */
#define BCHP_CLK_GENET_CLK_PM_CTRL 0x00462040 /* Software power management control to turn off GENET clocks */
#define BCHP_CLK_AVD0_CLK_PM_CTRL 0x00462044 /* Software power management control to turn off AVD0 clocks */
#define BCHP_CLK_AVD1_CLK_PM_CTRL 0x00462048 /* Software power management control to turn off AVD1 clocks */
#define BCHP_CLK_SATA_CLK_PM_CTRL 0x0046204c /* Software power management control to turn off SATA clocks */
#define BCHP_CLK_XPT_CLK_PM_CTRL 0x00462050 /* Software power management control to turn off core_xpt clocks */
#define BCHP_CLK_SUN_UART_CLK_PM_CTRL 0x00462054 /* Software power management control to turn off UART in sundry clocks */
#define BCHP_CLK_SUN_DAA_CLK_PM_CTRL 0x00462058 /* Software power management control to turn off DAA in sundry clocks */
#define BCHP_CLK_SUN_SM_CLK_PM_CTRL 0x0046205c /* Software power management control to turn off soft modem in sundry clocks */
#define BCHP_CLK_SUN_27M_CLK_PM_CTRL 0x00462060 /* Software power management control to turn off 27 MHz in sundry clocks */
#define BCHP_CLK_VEC_CLK_PM_CTRL 0x00462064 /* Software power management control to turn off VEC clocks */
#define BCHP_CLK_TDAC_CLK_PM_CTRL 0x00462068 /* Software power management control to turn off TDAC clocks */
#define BCHP_CLK_QDAC_CLK_PM_CTRL 0x0046206c /* Software power management control to turn off QDAC clocks */
#define BCHP_CLK_RFM_CLK_PM_CTRL 0x00462070 /* Software power management control to turn off RFM clocks */
#define BCHP_CLK_UHFR_CLK_PM_CTRL 0x00462074 /* Software power management control to turn off UHFR clocks */
#define BCHP_CLK_PCIE_CLK_PM_CTRL 0x00462078 /* Software power management control to turn off PCIE clocks */
#define BCHP_CLK_PCI_OUT_CLK_PM_CTRL 0x0046207c /* Software power management control to turn off PCI_OUT clocks */
#define BCHP_CLK_VEC_656_CLK_PM_CTRL 0x00462080 /* Software power management control to turn off VEC_656 clocks */
#define BCHP_CLK_BLUETOOTH_CLK_PM_CTRL 0x00462084 /* Software power management control to turn off Bluetooth clocks */
#define BCHP_CLK_PM_PLL_ALIVE_SEL 0x0046209c /* Software power management control to select certain PLL still alive even in standby mode with all PLLs off */
#define BCHP_CLK_MISC 0x004620a0 /* clock_gen block output clock selection */
#define BCHP_CLK_THIRD_OT_CONTROL_1 0x004620a4 /* Low 3rd Overtone Oscillator Control registers */
#define BCHP_CLK_PLL_TIMER_SELECT 0x004620a8 /* Chip PLL programmable wait time after leaving the standby mode */
#define BCHP_CLK_PLL_LOCK_STATUS 0x004620ac /* current lock status of main PLL */
#define BCHP_CLK_SYS_PLL_1_CTLBUS_HI 0x004620c0 /* SYS 1 PLL control bus higher word */
#define BCHP_CLK_SYS_PLL_1_CTLBUS_LO 0x004620c4 /* SYS 1 PLL control bus lower word */
#define BCHP_CLK_SYS_PLL_1_CTRL 0x004620c8 /* SYS PLL 1 m3div, m4div, reset */
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL 0x004620d0 /* GENET NETWORK PLL reset */
#define BCHP_CLK_SYS_PLL_1_1 0x004620e0 /* SYS_PLL_1 channel 1: 26.087 MHz bluetooth clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable */
#define BCHP_CLK_SYS_PLL_1_2 0x004620e4 /* SYS_PLL_1 channel 2: 100 MHz PCIe differential clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable */
#define BCHP_CLK_SYS_PLL_1_3 0x004620e8 /* SYS_PLL_1 channel 3: 225 MHz MocA PHY differential clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable */
#define BCHP_CLK_SYS_PLL_1_4 0x004620ec /* SYS_PLL_1 channel 4: 225 MHz MocA CPU differential clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable */
#define BCHP_CLK_SYS_PLL_1_5 0x004620f0 /* SYS_PLL_1 channel 5: 50 MHz USDS PLL reference clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable */
#define BCHP_CLK_SYS_PLL_1_6 0x004620f4 /* SYS_PLL_1 channel 6: 100 MHz MocA digital clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable */
#define BCHP_CLK_GENET_NETWORK_PLL_1 0x004620f8 /* GENET_NETWORK_PLL channel 1: 250 MHz RGMII and dvp_ht clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable */
#define BCHP_CLK_GENET_NETWORK_PLL_3 0x004620fc /* GENET_NETWORK_PLL channel 3: 25 MHz internal EPHY clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable */
#define BCHP_CLK_GENET_NETWORK_PLL_4 0x00462100 /* GENET_NETWORK_PLL channel 4: 75 MHz SATA PLL reference clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable */
#define BCHP_CLK_GENET_NETWORK_PLL_5 0x00462104 /* GENET_NETWORK_PLL channel 5: 125 MHz genet_top clockchannel 5: 125 MHz genet_top clock , PLL source post divider powerdown, channel gate on/off and cml buffer enable */
#define BCHP_CLK_GENET_NETWORK_PLL_6 0x00462108 /* GENET_NETWORK_PLL channel 6: 25 MHz clock to external GPHY , PLL source post divider powerdown, channel gate on/off and cml buffer enable */
#define BCHP_CLK_SYS_PLL_0_PLL_3 0x0046210c /* SYS_PLL_0 channel 3: 81 MHz clocks to core_xpt, PLL source post divider powerdown and cml buffer enable */
#define BCHP_CLK_SYS_PLL_0_PLL_4 0x00462110 /* SYS_PLL_0 channel 4: 48 MHz USB PLL reference clocks, PLL source post divider powerdown and cml buffer enable */
#define BCHP_CLK_SYS_PLL_0_PLL_5 0x00462114 /* SYS_PLL_0 channel 5: 33.23 MHz PCI clock, PLL source post divider powerdown and cml buffer enable */
#define BCHP_CLK_SYS_PLL_0_PLL_6 0x00462118 /* SYS_PLL_0 channel 6: 129.6 MHz SATA PCI and DAA clocks, PLL source post divider powerdown and cml buffer enable */
#define BCHP_CLK_SYS_PLL_0_CTRL 0x00462130 /* SYS PLL 0 reset, ch_disable, output_delay and powerdown */
#define BCHP_CLK_MIPS_PLL_CTRL 0x00462134 /* MIPS PLL reset, ch_disable, cpu frequency select, output_delay and powerdown */
#define BCHP_CLK_D2CDIFF_AC_CTRL 0x00462138 /* AC_CTRL for D2CDIFF */
#define BCHP_CLK_SCRATCH 0x0046213c /* clock_gen Scratch register */
/***************************************************************************
*REVISION - clock_gen Revision register
***************************************************************************/
/* CLK :: REVISION :: reserved0 [31:16] */
#define BCHP_CLK_REVISION_reserved0_MASK 0xffff0000
#define BCHP_CLK_REVISION_reserved0_SHIFT 16
/* CLK :: REVISION :: MAJOR [15:08] */
#define BCHP_CLK_REVISION_MAJOR_MASK 0x0000ff00
#define BCHP_CLK_REVISION_MAJOR_SHIFT 8
/* CLK :: REVISION :: MINOR [07:00] */
#define BCHP_CLK_REVISION_MINOR_MASK 0x000000ff
#define BCHP_CLK_REVISION_MINOR_SHIFT 0
/***************************************************************************
*BVN_EDGE_PM_CTRL - Software power management control to turn off BVN_EDGE system 216/108 MHz clocks
***************************************************************************/
/* CLK :: BVN_EDGE_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLK_BVN_EDGE_PM_CTRL_reserved0_MASK 0xfffffffc
#define BCHP_CLK_BVN_EDGE_PM_CTRL_reserved0_SHIFT 2
/* CLK :: BVN_EDGE_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_BVN_EDGE_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_BVN_EDGE_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: BVN_EDGE_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_BVN_EDGE_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_BVN_EDGE_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*BVN_MCVP_PM_CTRL - Software power management control to turn off BVN_MCVP system 216/108 MHz clocks
***************************************************************************/
/* CLK :: BVN_MCVP_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLK_BVN_MCVP_PM_CTRL_reserved0_MASK 0xfffffffc
#define BCHP_CLK_BVN_MCVP_PM_CTRL_reserved0_SHIFT 2
/* CLK :: BVN_MCVP_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_BVN_MCVP_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_BVN_MCVP_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: BVN_MCVP_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_BVN_MCVP_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_BVN_MCVP_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*BVN_MIDDLE_PM_CTRL - Software power management control to turn off BVN_MIDDLE system 216/108 MHz clocks
***************************************************************************/
/* CLK :: BVN_MIDDLE_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLK_BVN_MIDDLE_PM_CTRL_reserved0_MASK 0xfffffffc
#define BCHP_CLK_BVN_MIDDLE_PM_CTRL_reserved0_SHIFT 2
/* CLK :: BVN_MIDDLE_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_BVN_MIDDLE_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_BVN_MIDDLE_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: BVN_MIDDLE_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_BVN_MIDDLE_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_BVN_MIDDLE_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*DDR23_APHY_0_PM_CTRL - Software power management control to turn off DDR23_APHY_0 system 216/108 MHz clocks
***************************************************************************/
/* CLK :: DDR23_APHY_0_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLK_DDR23_APHY_0_PM_CTRL_reserved0_MASK 0xfffffffc
#define BCHP_CLK_DDR23_APHY_0_PM_CTRL_reserved0_SHIFT 2
/* CLK :: DDR23_APHY_0_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_DDR23_APHY_0_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_DDR23_APHY_0_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: DDR23_APHY_0_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_DDR23_APHY_0_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_DDR23_APHY_0_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*DDR23_APHY_1_PM_CTRL - Software power management control to turn off DDR23_APHY_1 system 216/108 MHz clocks
***************************************************************************/
/* CLK :: DDR23_APHY_1_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLK_DDR23_APHY_1_PM_CTRL_reserved0_MASK 0xfffffffc
#define BCHP_CLK_DDR23_APHY_1_PM_CTRL_reserved0_SHIFT 2
/* CLK :: DDR23_APHY_1_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_DDR23_APHY_1_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_DDR23_APHY_1_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: DDR23_APHY_1_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_DDR23_APHY_1_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_DDR23_APHY_1_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*GFX_3D_PM_CTRL - Software power management control to turn off GFX_3D system 216/108 MHz clocks
***************************************************************************/
/* CLK :: GFX_3D_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLK_GFX_3D_PM_CTRL_reserved0_MASK 0xfffffffc
#define BCHP_CLK_GFX_3D_PM_CTRL_reserved0_SHIFT 2
/* CLK :: GFX_3D_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_GFX_3D_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_GFX_3D_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: GFX_3D_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_GFX_3D_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_GFX_3D_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*GFX_2D_PM_CTRL - Software power management control to turn off GFX_2D system 216/108 MHz clocks
***************************************************************************/
/* CLK :: GFX_2D_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLK_GFX_2D_PM_CTRL_reserved0_MASK 0xfffffffc
#define BCHP_CLK_GFX_2D_PM_CTRL_reserved0_SHIFT 2
/* CLK :: GFX_2D_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_GFX_2D_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_GFX_2D_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: GFX_2D_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_GFX_2D_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_GFX_2D_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*MEMC_0_PM_CTRL - Software power management control to turn off MEMC_0 system 216/108 MHz clocks
***************************************************************************/
/* CLK :: MEMC_0_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLK_MEMC_0_PM_CTRL_reserved0_MASK 0xfffffffc
#define BCHP_CLK_MEMC_0_PM_CTRL_reserved0_SHIFT 2
/* CLK :: MEMC_0_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_MEMC_0_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_MEMC_0_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: MEMC_0_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_MEMC_0_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_MEMC_0_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*MEMC_1_PM_CTRL - Software power management control to turn off MEMC_1 system 216/108 MHz clocks
***************************************************************************/
/* CLK :: MEMC_1_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLK_MEMC_1_PM_CTRL_reserved0_MASK 0xfffffffc
#define BCHP_CLK_MEMC_1_PM_CTRL_reserved0_SHIFT 2
/* CLK :: MEMC_1_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_MEMC_1_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_MEMC_1_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: MEMC_1_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_MEMC_1_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_MEMC_1_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*SECTOP_DMA_PM_CTRL - Software power management control to turn off SECTOP DMA 216 MHz clocks
***************************************************************************/
/* CLK :: SECTOP_DMA_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLK_SECTOP_DMA_PM_CTRL_reserved0_MASK 0xfffffffe
#define BCHP_CLK_SECTOP_DMA_PM_CTRL_reserved0_SHIFT 1
/* CLK :: SECTOP_DMA_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_SECTOP_DMA_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_SECTOP_DMA_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*USB_PM_CTRL - Software power management control to turn off USB system 216/108 MHz clocks
***************************************************************************/
/* CLK :: USB_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLK_USB_PM_CTRL_reserved0_MASK 0xfffffffc
#define BCHP_CLK_USB_PM_CTRL_reserved0_SHIFT 2
/* CLK :: USB_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_USB_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_USB_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: USB_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_USB_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_USB_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*DVP_HT_CLK_PM_CTRL - Software power management control to turn off DVP_HT clocks
***************************************************************************/
/* CLK :: DVP_HT_CLK_PM_CTRL :: reserved0 [31:06] */
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_reserved0_MASK 0xffffffc0
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_reserved0_SHIFT 6
/* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_VEC_216M_CLK [05:05] */
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_VEC_216M_CLK_MASK 0x00000020
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_VEC_216M_CLK_SHIFT 5
/* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_HDMI_MAX_250M_CLK [04:04] */
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_MAX_250M_CLK_MASK 0x00000010
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_MAX_250M_CLK_SHIFT 4
/* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_HDMI_27M_CLK [03:03] */
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_27M_CLK_MASK 0x00000008
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_27M_CLK_SHIFT 3
/* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_HDMI_PM_27M_CLK [02:02] */
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_PM_27M_CLK_MASK 0x00000004
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_PM_27M_CLK_SHIFT 2
/* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: DVP_HT_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*TOP1394_CLK_PM_CTRL - Software power management control to turn off TOP1394 216/108, 27 MHz clocks
***************************************************************************/
/* CLK :: TOP1394_CLK_PM_CTRL :: reserved0 [31:03] */
#define BCHP_CLK_TOP1394_CLK_PM_CTRL_reserved0_MASK 0xfffffff8
#define BCHP_CLK_TOP1394_CLK_PM_CTRL_reserved0_SHIFT 3
/* CLK :: TOP1394_CLK_PM_CTRL :: DIS_1394_PM_27M_CLK [02:02] */
#define BCHP_CLK_TOP1394_CLK_PM_CTRL_DIS_1394_PM_27M_CLK_MASK 0x00000004
#define BCHP_CLK_TOP1394_CLK_PM_CTRL_DIS_1394_PM_27M_CLK_SHIFT 2
/* CLK :: TOP1394_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_TOP1394_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_TOP1394_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: TOP1394_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_TOP1394_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_TOP1394_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*MOCA_CLK_PM_CTRL - Software power management control to turn off MOCA clocks
***************************************************************************/
/* CLK :: MOCA_CLK_PM_CTRL :: reserved0 [31:11] */
#define BCHP_CLK_MOCA_CLK_PM_CTRL_reserved0_MASK 0xfffff800
#define BCHP_CLK_MOCA_CLK_PM_CTRL_reserved0_SHIFT 11
/* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_54M_CLK [10:10] */
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_54M_CLK_MASK 0x00000400
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_54M_CLK_SHIFT 10
/* CLK :: MOCA_CLK_PM_CTRL :: DIS_GENET_RGMII_216M_CLK [09:09] */
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_GENET_RGMII_216M_CLK_MASK 0x00000200
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_GENET_RGMII_216M_CLK_SHIFT 9
/* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_ENET_UNIMAC_SYS_RX_27_108M_CLK [08:08] */
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_UNIMAC_SYS_RX_27_108M_CLK_MASK 0x00000100
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_UNIMAC_SYS_RX_27_108M_CLK_SHIFT 8
/* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_ENET_UNIMAC_SYS_TX_27_108M_CLK [07:07] */
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_UNIMAC_SYS_TX_27_108M_CLK_MASK 0x00000080
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_UNIMAC_SYS_TX_27_108M_CLK_SHIFT 7
/* CLK :: MOCA_CLK_PM_CTRL :: reserved1 [06:06] */
#define BCHP_CLK_MOCA_CLK_PM_CTRL_reserved1_MASK 0x00000040
#define BCHP_CLK_MOCA_CLK_PM_CTRL_reserved1_SHIFT 6
/* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_ENET_L2_INTR_27_108M_CLK [05:05] */
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_L2_INTR_27_108M_CLK_MASK 0x00000020
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_L2_INTR_27_108M_CLK_SHIFT 5
/* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_ENET_HFB_27_108M_CLK [04:04] */
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_HFB_27_108M_CLK_MASK 0x00000010
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_HFB_27_108M_CLK_SHIFT 4
/* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_ENET_GMII_TX_27_108M_CLK [03:03] */
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_GMII_TX_27_108M_CLK_MASK 0x00000008
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_ENET_GMII_TX_27_108M_CLK_SHIFT 3
/* CLK :: MOCA_CLK_PM_CTRL :: DIS_MOCA_PM_27M_CLK [02:02] */
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_PM_27M_CLK_MASK 0x00000004
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_MOCA_PM_27M_CLK_SHIFT 2
/* CLK :: MOCA_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: MOCA_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_MOCA_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*RPT_AIO_CLK_PM_CTRL - Software power management control to turn off RPT_AIO clocks
***************************************************************************/
/* CLK :: RPT_AIO_CLK_PM_CTRL :: reserved0 [31:03] */
#define BCHP_CLK_RPT_AIO_CLK_PM_CTRL_reserved0_MASK 0xfffffff8
#define BCHP_CLK_RPT_AIO_CLK_PM_CTRL_reserved0_SHIFT 3
/* CLK :: RPT_AIO_CLK_PM_CTRL :: DIS_RPT_250M_CLK [02:02] */
#define BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_RPT_250M_CLK_MASK 0x00000004
#define BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_RPT_250M_CLK_SHIFT 2
/* CLK :: RPT_AIO_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: RPT_AIO_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*GENET_CLK_PM_CTRL - Software power management control to turn off GENET clocks
***************************************************************************/
/* CLK :: GENET_CLK_PM_CTRL :: reserved0 [31:11] */
#define BCHP_CLK_GENET_CLK_PM_CTRL_reserved0_MASK 0xfffff800
#define BCHP_CLK_GENET_CLK_PM_CTRL_reserved0_SHIFT 11
/* CLK :: GENET_CLK_PM_CTRL :: DIS_GENET_RGMII_250M_CLK [10:10] */
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_RGMII_250M_CLK_MASK 0x00000400
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_RGMII_250M_CLK_SHIFT 10
/* CLK :: GENET_CLK_PM_CTRL :: DIS_GENET_UNIMAC_SYS_RX_27_125M_CLK [09:09] */
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_UNIMAC_SYS_RX_27_125M_CLK_MASK 0x00000200
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_UNIMAC_SYS_RX_27_125M_CLK_SHIFT 9
/* CLK :: GENET_CLK_PM_CTRL :: DIS_GENET_UNIMAC_SYS_TX_27_125M_CLK [08:08] */
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_UNIMAC_SYS_TX_27_125M_CLK_MASK 0x00000100
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_UNIMAC_SYS_TX_27_125M_CLK_SHIFT 8
/* CLK :: GENET_CLK_PM_CTRL :: reserved1 [07:07] */
#define BCHP_CLK_GENET_CLK_PM_CTRL_reserved1_MASK 0x00000080
#define BCHP_CLK_GENET_CLK_PM_CTRL_reserved1_SHIFT 7
/* CLK :: GENET_CLK_PM_CTRL :: DIS_GENET_L2_INTR_27_125M_CLK [06:06] */
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_L2_INTR_27_125M_CLK_MASK 0x00000040
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_L2_INTR_27_125M_CLK_SHIFT 6
/* CLK :: GENET_CLK_PM_CTRL :: DIS_GENET_HFB_27_125M_CLK [05:05] */
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_HFB_27_125M_CLK_MASK 0x00000020
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_HFB_27_125M_CLK_SHIFT 5
/* CLK :: GENET_CLK_PM_CTRL :: DIS_GENET_GMII_TX_27_125M_CLK [04:04] */
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_GMII_TX_27_125M_CLK_MASK 0x00000010
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_GMII_TX_27_125M_CLK_SHIFT 4
/* CLK :: GENET_CLK_PM_CTRL :: DIS_GENET_25M_CLK [03:03] */
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_25M_CLK_MASK 0x00000008
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_25M_CLK_SHIFT 3
/* CLK :: GENET_CLK_PM_CTRL :: DIS_GENET_PM_27M_CLK [02:02] */
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_PM_27M_CLK_MASK 0x00000004
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_PM_27M_CLK_SHIFT 2
/* CLK :: GENET_CLK_PM_CTRL :: DIS_GENET_GISB_108M_CLK [01:01] */
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_GISB_108M_CLK_MASK 0x00000002
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_GENET_GISB_108M_CLK_SHIFT 1
/* CLK :: GENET_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_GENET_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*AVD0_CLK_PM_CTRL - Software power management control to turn off AVD0 clocks
***************************************************************************/
/* CLK :: AVD0_CLK_PM_CTRL :: reserved0 [31:03] */
#define BCHP_CLK_AVD0_CLK_PM_CTRL_reserved0_MASK 0xfffffff8
#define BCHP_CLK_AVD0_CLK_PM_CTRL_reserved0_SHIFT 3
/* CLK :: AVD0_CLK_PM_CTRL :: DIS_250M_CLK [02:02] */
#define BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_250M_CLK_MASK 0x00000004
#define BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_250M_CLK_SHIFT 2
/* CLK :: AVD0_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: AVD0_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*AVD1_CLK_PM_CTRL - Software power management control to turn off AVD1 clocks
***************************************************************************/
/* CLK :: AVD1_CLK_PM_CTRL :: reserved0 [31:03] */
#define BCHP_CLK_AVD1_CLK_PM_CTRL_reserved0_MASK 0xfffffff8
#define BCHP_CLK_AVD1_CLK_PM_CTRL_reserved0_SHIFT 3
/* CLK :: AVD1_CLK_PM_CTRL :: DIS_250M_CLK [02:02] */
#define BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_250M_CLK_MASK 0x00000004
#define BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_250M_CLK_SHIFT 2
/* CLK :: AVD1_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: AVD1_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*SATA_CLK_PM_CTRL - Software power management control to turn off SATA clocks
***************************************************************************/
/* CLK :: SATA_CLK_PM_CTRL :: reserved0 [31:03] */
#define BCHP_CLK_SATA_CLK_PM_CTRL_reserved0_MASK 0xfffffff8
#define BCHP_CLK_SATA_CLK_PM_CTRL_reserved0_SHIFT 3
/* CLK :: SATA_CLK_PM_CTRL :: DIS_SATA_PCI_CLK [02:02] */
#define BCHP_CLK_SATA_CLK_PM_CTRL_DIS_SATA_PCI_CLK_MASK 0x00000004
#define BCHP_CLK_SATA_CLK_PM_CTRL_DIS_SATA_PCI_CLK_SHIFT 2
/* CLK :: SATA_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_SATA_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_SATA_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: SATA_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_SATA_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_SATA_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*XPT_CLK_PM_CTRL - Software power management control to turn off core_xpt clocks
***************************************************************************/
/* CLK :: XPT_CLK_PM_CTRL :: reserved0 [31:07] */
#define BCHP_CLK_XPT_CLK_PM_CTRL_reserved0_MASK 0xffffff80
#define BCHP_CLK_XPT_CLK_PM_CTRL_reserved0_SHIFT 7
/* CLK :: XPT_CLK_PM_CTRL :: DIS_XPT_27M_CLK [06:06] */
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_27M_CLK_MASK 0x00000040
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_27M_CLK_SHIFT 6
/* CLK :: XPT_CLK_PM_CTRL :: DIS_XPT_54M_CLK [05:05] */
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_54M_CLK_MASK 0x00000020
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_54M_CLK_SHIFT 5
/* CLK :: XPT_CLK_PM_CTRL :: DIS_XPT_81M_CLK [04:04] */
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_81M_CLK_MASK 0x00000010
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_81M_CLK_SHIFT 4
/* CLK :: XPT_CLK_PM_CTRL :: DIS_XPT_20P25M_CLK [03:03] */
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_20P25M_CLK_MASK 0x00000008
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_20P25M_CLK_SHIFT 3
/* CLK :: XPT_CLK_PM_CTRL :: DIS_XPT_40P5M_CLK [02:02] */
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_40P5M_CLK_MASK 0x00000004
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_40P5M_CLK_SHIFT 2
/* CLK :: XPT_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: XPT_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_XPT_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*SUN_UART_CLK_PM_CTRL - Software power management control to turn off UART in sundry clocks
***************************************************************************/
/* CLK :: SUN_UART_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLK_SUN_UART_CLK_PM_CTRL_reserved0_MASK 0xfffffffe
#define BCHP_CLK_SUN_UART_CLK_PM_CTRL_reserved0_SHIFT 1
/* CLK :: SUN_UART_CLK_PM_CTRL :: DIS_SUN_UART_108M_CLK [00:00] */
#define BCHP_CLK_SUN_UART_CLK_PM_CTRL_DIS_SUN_UART_108M_CLK_MASK 0x00000001
#define BCHP_CLK_SUN_UART_CLK_PM_CTRL_DIS_SUN_UART_108M_CLK_SHIFT 0
/***************************************************************************
*SUN_DAA_CLK_PM_CTRL - Software power management control to turn off DAA in sundry clocks
***************************************************************************/
/* CLK :: SUN_DAA_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLK_SUN_DAA_CLK_PM_CTRL_reserved0_MASK 0xfffffffe
#define BCHP_CLK_SUN_DAA_CLK_PM_CTRL_reserved0_SHIFT 1
/* CLK :: SUN_DAA_CLK_PM_CTRL :: DIS_SUN_DAA_32P4M_CLK [00:00] */
#define BCHP_CLK_SUN_DAA_CLK_PM_CTRL_DIS_SUN_DAA_32P4M_CLK_MASK 0x00000001
#define BCHP_CLK_SUN_DAA_CLK_PM_CTRL_DIS_SUN_DAA_32P4M_CLK_SHIFT 0
/***************************************************************************
*SUN_SM_CLK_PM_CTRL - Software power management control to turn off soft modem in sundry clocks
***************************************************************************/
/* CLK :: SUN_SM_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLK_SUN_SM_CLK_PM_CTRL_reserved0_MASK 0xfffffffe
#define BCHP_CLK_SUN_SM_CLK_PM_CTRL_reserved0_SHIFT 1
/* CLK :: SUN_SM_CLK_PM_CTRL :: DIS_SUN_SM_27M_CLK [00:00] */
#define BCHP_CLK_SUN_SM_CLK_PM_CTRL_DIS_SUN_SM_27M_CLK_MASK 0x00000001
#define BCHP_CLK_SUN_SM_CLK_PM_CTRL_DIS_SUN_SM_27M_CLK_SHIFT 0
/***************************************************************************
*SUN_27M_CLK_PM_CTRL - Software power management control to turn off 27 MHz in sundry clocks
***************************************************************************/
/* CLK :: SUN_27M_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLK_SUN_27M_CLK_PM_CTRL_reserved0_MASK 0xfffffffe
#define BCHP_CLK_SUN_27M_CLK_PM_CTRL_reserved0_SHIFT 1
/* CLK :: SUN_27M_CLK_PM_CTRL :: DIS_SUN_27M_CLK [00:00] */
#define BCHP_CLK_SUN_27M_CLK_PM_CTRL_DIS_SUN_27M_CLK_MASK 0x00000001
#define BCHP_CLK_SUN_27M_CLK_PM_CTRL_DIS_SUN_27M_CLK_SHIFT 0
/***************************************************************************
*VEC_CLK_PM_CTRL - Software power management control to turn off VEC clocks
***************************************************************************/
/* CLK :: VEC_CLK_PM_CTRL :: reserved0 [31:03] */
#define BCHP_CLK_VEC_CLK_PM_CTRL_reserved0_MASK 0xfffffff8
#define BCHP_CLK_VEC_CLK_PM_CTRL_reserved0_SHIFT 3
/* CLK :: VEC_CLK_PM_CTRL :: DIS_VEC_DAC_216M_CLK [02:02] */
#define BCHP_CLK_VEC_CLK_PM_CTRL_DIS_VEC_DAC_216M_CLK_MASK 0x00000004
#define BCHP_CLK_VEC_CLK_PM_CTRL_DIS_VEC_DAC_216M_CLK_SHIFT 2
/* CLK :: VEC_CLK_PM_CTRL :: DIS_108M_CLK [01:01] */
#define BCHP_CLK_VEC_CLK_PM_CTRL_DIS_108M_CLK_MASK 0x00000002
#define BCHP_CLK_VEC_CLK_PM_CTRL_DIS_108M_CLK_SHIFT 1
/* CLK :: VEC_CLK_PM_CTRL :: DIS_216M_CLK [00:00] */
#define BCHP_CLK_VEC_CLK_PM_CTRL_DIS_216M_CLK_MASK 0x00000001
#define BCHP_CLK_VEC_CLK_PM_CTRL_DIS_216M_CLK_SHIFT 0
/***************************************************************************
*TDAC_CLK_PM_CTRL - Software power management control to turn off TDAC clocks
***************************************************************************/
/* CLK :: TDAC_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLK_TDAC_CLK_PM_CTRL_reserved0_MASK 0xfffffffe
#define BCHP_CLK_TDAC_CLK_PM_CTRL_reserved0_SHIFT 1
/* CLK :: TDAC_CLK_PM_CTRL :: DIS_TDAC_216M_CLK [00:00] */
#define BCHP_CLK_TDAC_CLK_PM_CTRL_DIS_TDAC_216M_CLK_MASK 0x00000001
#define BCHP_CLK_TDAC_CLK_PM_CTRL_DIS_TDAC_216M_CLK_SHIFT 0
/***************************************************************************
*QDAC_CLK_PM_CTRL - Software power management control to turn off QDAC clocks
***************************************************************************/
/* CLK :: QDAC_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLK_QDAC_CLK_PM_CTRL_reserved0_MASK 0xfffffffe
#define BCHP_CLK_QDAC_CLK_PM_CTRL_reserved0_SHIFT 1
/* CLK :: QDAC_CLK_PM_CTRL :: DIS_QDAC_216M_CLK [00:00] */
#define BCHP_CLK_QDAC_CLK_PM_CTRL_DIS_QDAC_216M_CLK_MASK 0x00000001
#define BCHP_CLK_QDAC_CLK_PM_CTRL_DIS_QDAC_216M_CLK_SHIFT 0
/***************************************************************************
*RFM_CLK_PM_CTRL - Software power management control to turn off RFM clocks
***************************************************************************/
/* CLK :: RFM_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLK_RFM_CLK_PM_CTRL_reserved0_MASK 0xfffffffe
#define BCHP_CLK_RFM_CLK_PM_CTRL_reserved0_SHIFT 1
/* CLK :: RFM_CLK_PM_CTRL :: DIS_RFM_108M_CLK [00:00] */
#define BCHP_CLK_RFM_CLK_PM_CTRL_DIS_RFM_108M_CLK_MASK 0x00000001
#define BCHP_CLK_RFM_CLK_PM_CTRL_DIS_RFM_108M_CLK_SHIFT 0
/***************************************************************************
*UHFR_CLK_PM_CTRL - Software power management control to turn off UHFR clocks
***************************************************************************/
/* CLK :: UHFR_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLK_UHFR_CLK_PM_CTRL_reserved0_MASK 0xfffffffc
#define BCHP_CLK_UHFR_CLK_PM_CTRL_reserved0_SHIFT 2
/* CLK :: UHFR_CLK_PM_CTRL :: DIS_ANA_UHFR_CLK [01:01] */
#define BCHP_CLK_UHFR_CLK_PM_CTRL_DIS_ANA_UHFR_CLK_MASK 0x00000002
#define BCHP_CLK_UHFR_CLK_PM_CTRL_DIS_ANA_UHFR_CLK_SHIFT 1
/* CLK :: UHFR_CLK_PM_CTRL :: DIS_DIGI_UHFR_CLK [00:00] */
#define BCHP_CLK_UHFR_CLK_PM_CTRL_DIS_DIGI_UHFR_CLK_MASK 0x00000001
#define BCHP_CLK_UHFR_CLK_PM_CTRL_DIS_DIGI_UHFR_CLK_SHIFT 0
/***************************************************************************
*PCIE_CLK_PM_CTRL - Software power management control to turn off PCIE clocks
***************************************************************************/
/* CLK :: PCIE_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLK_PCIE_CLK_PM_CTRL_reserved0_MASK 0xfffffffe
#define BCHP_CLK_PCIE_CLK_PM_CTRL_reserved0_SHIFT 1
/* CLK :: PCIE_CLK_PM_CTRL :: DIS_PCIE_PM_27M_CLK [00:00] */
#define BCHP_CLK_PCIE_CLK_PM_CTRL_DIS_PCIE_PM_27M_CLK_MASK 0x00000001
#define BCHP_CLK_PCIE_CLK_PM_CTRL_DIS_PCIE_PM_27M_CLK_SHIFT 0
/***************************************************************************
*PCI_OUT_CLK_PM_CTRL - Software power management control to turn off PCI_OUT clocks
***************************************************************************/
/* CLK :: PCI_OUT_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLK_PCI_OUT_CLK_PM_CTRL_reserved0_MASK 0xfffffffe
#define BCHP_CLK_PCI_OUT_CLK_PM_CTRL_reserved0_SHIFT 1
/* CLK :: PCI_OUT_CLK_PM_CTRL :: DIS_PCI_OUT_CLK [00:00] */
#define BCHP_CLK_PCI_OUT_CLK_PM_CTRL_DIS_PCI_OUT_CLK_MASK 0x00000001
#define BCHP_CLK_PCI_OUT_CLK_PM_CTRL_DIS_PCI_OUT_CLK_SHIFT 0
/***************************************************************************
*VEC_656_CLK_PM_CTRL - Software power management control to turn off VEC_656 clocks
***************************************************************************/
/* CLK :: VEC_656_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLK_VEC_656_CLK_PM_CTRL_reserved0_MASK 0xfffffffe
#define BCHP_CLK_VEC_656_CLK_PM_CTRL_reserved0_SHIFT 1
/* CLK :: VEC_656_CLK_PM_CTRL :: DIS_VEC_VCXO_656_CLK [00:00] */
#define BCHP_CLK_VEC_656_CLK_PM_CTRL_DIS_VEC_VCXO_656_CLK_MASK 0x00000001
#define BCHP_CLK_VEC_656_CLK_PM_CTRL_DIS_VEC_VCXO_656_CLK_SHIFT 0
/***************************************************************************
*BLUETOOTH_CLK_PM_CTRL - Software power management control to turn off Bluetooth clocks
***************************************************************************/
/* CLK :: BLUETOOTH_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLK_BLUETOOTH_CLK_PM_CTRL_reserved0_MASK 0xfffffffe
#define BCHP_CLK_BLUETOOTH_CLK_PM_CTRL_reserved0_SHIFT 1
/* CLK :: BLUETOOTH_CLK_PM_CTRL :: DIS_BLUETOOTH_CLK [00:00] */
#define BCHP_CLK_BLUETOOTH_CLK_PM_CTRL_DIS_BLUETOOTH_CLK_MASK 0x00000001
#define BCHP_CLK_BLUETOOTH_CLK_PM_CTRL_DIS_BLUETOOTH_CLK_SHIFT 0
/***************************************************************************
*PM_PLL_ALIVE_SEL - Software power management control to select certain PLL still alive even in standby mode with all PLLs off
***************************************************************************/
/* CLK :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
#define BCHP_CLK_PM_PLL_ALIVE_SEL_reserved0_MASK 0xfffffff8
#define BCHP_CLK_PM_PLL_ALIVE_SEL_reserved0_SHIFT 3
/* CLK :: PM_PLL_ALIVE_SEL :: DDR_PLL [02:02] */
#define BCHP_CLK_PM_PLL_ALIVE_SEL_DDR_PLL_MASK 0x00000004
#define BCHP_CLK_PM_PLL_ALIVE_SEL_DDR_PLL_SHIFT 2
/* CLK :: PM_PLL_ALIVE_SEL :: MIPS_PLL [01:01] */
#define BCHP_CLK_PM_PLL_ALIVE_SEL_MIPS_PLL_MASK 0x00000002
#define BCHP_CLK_PM_PLL_ALIVE_SEL_MIPS_PLL_SHIFT 1
/* CLK :: PM_PLL_ALIVE_SEL :: SYS_PLL_0 [00:00] */
#define BCHP_CLK_PM_PLL_ALIVE_SEL_SYS_PLL_0_MASK 0x00000001
#define BCHP_CLK_PM_PLL_ALIVE_SEL_SYS_PLL_0_SHIFT 0
/***************************************************************************
*MISC - clock_gen block output clock selection
***************************************************************************/
/* CLK :: MISC :: reserved0 [31:21] */
#define BCHP_CLK_MISC_reserved0_MASK 0xffe00000
#define BCHP_CLK_MISC_reserved0_SHIFT 21
/* CLK :: MISC :: GENET_CLK_SEL [20:20] */
#define BCHP_CLK_MISC_GENET_CLK_SEL_MASK 0x00100000
#define BCHP_CLK_MISC_GENET_CLK_SEL_SHIFT 20
/* CLK :: MISC :: GENET_GMII_TX_CLK_SEL [19:19] */
#define BCHP_CLK_MISC_GENET_GMII_TX_CLK_SEL_MASK 0x00080000
#define BCHP_CLK_MISC_GENET_GMII_TX_CLK_SEL_SHIFT 19
/* CLK :: MISC :: SMARTCARD_CLOCK_1_SOURCE_SEL [18:17] */
#define BCHP_CLK_MISC_SMARTCARD_CLOCK_1_SOURCE_SEL_MASK 0x00060000
#define BCHP_CLK_MISC_SMARTCARD_CLOCK_1_SOURCE_SEL_SHIFT 17
/* CLK :: MISC :: SMARTCARD_CLOCK_0_SOURCE_SEL [16:15] */
#define BCHP_CLK_MISC_SMARTCARD_CLOCK_0_SOURCE_SEL_MASK 0x00018000
#define BCHP_CLK_MISC_SMARTCARD_CLOCK_0_SOURCE_SEL_SHIFT 15
/* CLK :: MISC :: SMARTCARD_PLL_REFERENCE_CLK_SEL [14:13] */
#define BCHP_CLK_MISC_SMARTCARD_PLL_REFERENCE_CLK_SEL_MASK 0x00006000
#define BCHP_CLK_MISC_SMARTCARD_PLL_REFERENCE_CLK_SEL_SHIFT 13
/* CLK :: MISC :: VCXOA_OUTCLK_SRC_SEL [12:11] */
#define BCHP_CLK_MISC_VCXOA_OUTCLK_SRC_SEL_MASK 0x00001800
#define BCHP_CLK_MISC_VCXOA_OUTCLK_SRC_SEL_SHIFT 11
/* CLK :: MISC :: OBSRV_PLL_EN [10:10] */
#define BCHP_CLK_MISC_OBSRV_PLL_EN_MASK 0x00000400
#define BCHP_CLK_MISC_OBSRV_PLL_EN_SHIFT 10
/* CLK :: MISC :: FORCE_NO_RAP_PLL_BYPASS [09:09] */
#define BCHP_CLK_MISC_FORCE_NO_RAP_PLL_BYPASS_MASK 0x00000200
#define BCHP_CLK_MISC_FORCE_NO_RAP_PLL_BYPASS_SHIFT 9
/* CLK :: MISC :: VCXO_TEST_IN_SEL [08:08] */
#define BCHP_CLK_MISC_VCXO_TEST_IN_SEL_MASK 0x00000100
#define BCHP_CLK_MISC_VCXO_TEST_IN_SEL_SHIFT 8
/* CLK :: MISC :: INV_VCXO_OUTCLK_SRCA [07:07] */
#define BCHP_CLK_MISC_INV_VCXO_OUTCLK_SRCA_MASK 0x00000080
#define BCHP_CLK_MISC_INV_VCXO_OUTCLK_SRCA_SHIFT 7
/* CLK :: MISC :: MOCA_ENET_CLK_SEL [06:06] */
#define BCHP_CLK_MISC_MOCA_ENET_CLK_SEL_MASK 0x00000040
#define BCHP_CLK_MISC_MOCA_ENET_CLK_SEL_SHIFT 6
/* CLK :: MISC :: MOCA_ENET_GMII_TX_CLK_SEL [05:05] */
#define BCHP_CLK_MISC_MOCA_ENET_GMII_TX_CLK_SEL_MASK 0x00000020
#define BCHP_CLK_MISC_MOCA_ENET_GMII_TX_CLK_SEL_SHIFT 5
/* CLK :: MISC :: INV_VEC656_CLK [04:04] */
#define BCHP_CLK_MISC_INV_VEC656_CLK_MASK 0x00000010
#define BCHP_CLK_MISC_INV_VEC656_CLK_SHIFT 4
/* CLK :: MISC :: VEC656_CLK_SRC_SEL [03:02] */
#define BCHP_CLK_MISC_VEC656_CLK_SRC_SEL_MASK 0x0000000c
#define BCHP_CLK_MISC_VEC656_CLK_SRC_SEL_SHIFT 2
/* CLK :: MISC :: CLK27_OUTCLK_SRC_SEL [01:00] */
#define BCHP_CLK_MISC_CLK27_OUTCLK_SRC_SEL_MASK 0x00000003
#define BCHP_CLK_MISC_CLK27_OUTCLK_SRC_SEL_SHIFT 0
/***************************************************************************
*THIRD_OT_CONTROL_1 - Low 3rd Overtone Oscillator Control registers
***************************************************************************/
/* CLK :: THIRD_OT_CONTROL_1 :: reserved0 [31:16] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_reserved0_MASK 0xffff0000
#define BCHP_CLK_THIRD_OT_CONTROL_1_reserved0_SHIFT 16
/* CLK :: THIRD_OT_CONTROL_1 :: GAIN_AMPLIFIER_CURRENT_CTRL [15:14] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_MASK 0x0000c000
#define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_SHIFT 14
#define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_ONE_HUNDRED_FIFTY_MICRO_AMP 0
#define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_TWO_HUNDRED_MICRO_AMP 1
#define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_TWO_HUNDRED_FIFTY_MICRO_AMP 2
#define BCHP_CLK_THIRD_OT_CONTROL_1_GAIN_AMPLIFIER_CURRENT_CTRL_THREE_HUNDRED_MICRO_AMP 3
/* CLK :: THIRD_OT_CONTROL_1 :: ICBUF_CURRENT_CTRL [13:12] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_MASK 0x00003000
#define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_SHIFT 12
#define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_ONE_HUNDRED_FIFTY_MICRO_AMP 0
#define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_TWO_HUNDRED_MICRO_AMP 1
#define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_TWO_HUNDRED_FIFTY_MICRO_AMP 2
#define BCHP_CLK_THIRD_OT_CONTROL_1_ICBUF_CURRENT_CTRL_THREE_HUNDRED_MICRO_AMP 3
/* CLK :: THIRD_OT_CONTROL_1 :: FREQ_DUBLER_CURRENT_CTRL [11:11] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DUBLER_CURRENT_CTRL_MASK 0x00000800
#define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DUBLER_CURRENT_CTRL_SHIFT 11
#define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DUBLER_CURRENT_CTRL_TWO_HUNDRED_MICRO_AMP 0
#define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DUBLER_CURRENT_CTRL_THREE_HUNDRED_MICRO_AMP 1
/* CLK :: THIRD_OT_CONTROL_1 :: AMPLITUDE_LIMITER_ACTIVE [10:10] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_AMPLITUDE_LIMITER_ACTIVE_MASK 0x00000400
#define BCHP_CLK_THIRD_OT_CONTROL_1_AMPLITUDE_LIMITER_ACTIVE_SHIFT 10
/* CLK :: THIRD_OT_CONTROL_1 :: COMMON_MODE_VOLT_CTRL [09:08] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_MASK 0x00000300
#define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_SHIFT 8
#define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_ONE_POINT_FOUR_FIVE_VOLT 1
#define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_ONE_POINT_FIVE_FOUR_VOLT 0
#define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_ONE_POINT_SIX_TWO_VOLT 2
#define BCHP_CLK_THIRD_OT_CONTROL_1_COMMON_MODE_VOLT_CTRL_ONE_POINT_SIX_SIX_VOLT 3
/* CLK :: THIRD_OT_CONTROL_1 :: FREQ_DOUBLER_BYPASS_EN [07:07] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DOUBLER_BYPASS_EN_MASK 0x00000080
#define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DOUBLER_BYPASS_EN_SHIFT 7
/* CLK :: THIRD_OT_CONTROL_1 :: CML_6_N_P_EN [06:06] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_CML_6_N_P_EN_MASK 0x00000040
#define BCHP_CLK_THIRD_OT_CONTROL_1_CML_6_N_P_EN_SHIFT 6
/* CLK :: THIRD_OT_CONTROL_1 :: CML_5_N_P_EN [05:05] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_CML_5_N_P_EN_MASK 0x00000020
#define BCHP_CLK_THIRD_OT_CONTROL_1_CML_5_N_P_EN_SHIFT 5
/* CLK :: THIRD_OT_CONTROL_1 :: CML_4_N_P_EN [04:04] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_CML_4_N_P_EN_MASK 0x00000010
#define BCHP_CLK_THIRD_OT_CONTROL_1_CML_4_N_P_EN_SHIFT 4
/* CLK :: THIRD_OT_CONTROL_1 :: CML_3_N_P_EN [03:03] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_CML_3_N_P_EN_MASK 0x00000008
#define BCHP_CLK_THIRD_OT_CONTROL_1_CML_3_N_P_EN_SHIFT 3
/* CLK :: THIRD_OT_CONTROL_1 :: CML_2_N_P_EN [02:02] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_CML_2_N_P_EN_MASK 0x00000004
#define BCHP_CLK_THIRD_OT_CONTROL_1_CML_2_N_P_EN_SHIFT 2
/* CLK :: THIRD_OT_CONTROL_1 :: FREQ_MONITOR_OUTPUT_EN [01:01] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_MONITOR_OUTPUT_EN_MASK 0x00000002
#define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_MONITOR_OUTPUT_EN_SHIFT 1
/* CLK :: THIRD_OT_CONTROL_1 :: FREQ_DOUBLER_POWER_DOWN [00:00] */
#define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DOUBLER_POWER_DOWN_MASK 0x00000001
#define BCHP_CLK_THIRD_OT_CONTROL_1_FREQ_DOUBLER_POWER_DOWN_SHIFT 0
/***************************************************************************
*PLL_TIMER_SELECT - Chip PLL programmable wait time after leaving the standby mode
***************************************************************************/
/* CLK :: PLL_TIMER_SELECT :: reserved0 [31:02] */
#define BCHP_CLK_PLL_TIMER_SELECT_reserved0_MASK 0xfffffffc
#define BCHP_CLK_PLL_TIMER_SELECT_reserved0_SHIFT 2
/* CLK :: PLL_TIMER_SELECT :: TIMER [01:00] */
#define BCHP_CLK_PLL_TIMER_SELECT_TIMER_MASK 0x00000003
#define BCHP_CLK_PLL_TIMER_SELECT_TIMER_SHIFT 0
/***************************************************************************
*PLL_LOCK_STATUS - current lock status of main PLL
***************************************************************************/
/* CLK :: PLL_LOCK_STATUS :: reserved0 [31:04] */
#define BCHP_CLK_PLL_LOCK_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLK_PLL_LOCK_STATUS_reserved0_SHIFT 4
/* CLK :: PLL_LOCK_STATUS :: NETWORK_PLL_LOCK [03:03] */
#define BCHP_CLK_PLL_LOCK_STATUS_NETWORK_PLL_LOCK_MASK 0x00000008
#define BCHP_CLK_PLL_LOCK_STATUS_NETWORK_PLL_LOCK_SHIFT 3
/* CLK :: PLL_LOCK_STATUS :: MIPS_PLL_LOCK [02:02] */
#define BCHP_CLK_PLL_LOCK_STATUS_MIPS_PLL_LOCK_MASK 0x00000004
#define BCHP_CLK_PLL_LOCK_STATUS_MIPS_PLL_LOCK_SHIFT 2
/* CLK :: PLL_LOCK_STATUS :: SYSTEM_PLL_0_LOCK [01:01] */
#define BCHP_CLK_PLL_LOCK_STATUS_SYSTEM_PLL_0_LOCK_MASK 0x00000002
#define BCHP_CLK_PLL_LOCK_STATUS_SYSTEM_PLL_0_LOCK_SHIFT 1
/* CLK :: PLL_LOCK_STATUS :: SYSTEM_PLL_1_LOCK [00:00] */
#define BCHP_CLK_PLL_LOCK_STATUS_SYSTEM_PLL_1_LOCK_MASK 0x00000001
#define BCHP_CLK_PLL_LOCK_STATUS_SYSTEM_PLL_1_LOCK_SHIFT 0
/***************************************************************************
*SYS_PLL_1_CTLBUS_HI - SYS 1 PLL control bus higher word
***************************************************************************/
/* CLK :: SYS_PLL_1_CTLBUS_HI :: reserved0 [31:06] */
#define BCHP_CLK_SYS_PLL_1_CTLBUS_HI_reserved0_MASK 0xffffffc0
#define BCHP_CLK_SYS_PLL_1_CTLBUS_HI_reserved0_SHIFT 6
/* CLK :: SYS_PLL_1_CTLBUS_HI :: CTL_BITS_37_32 [05:00] */
#define BCHP_CLK_SYS_PLL_1_CTLBUS_HI_CTL_BITS_37_32_MASK 0x0000003f
#define BCHP_CLK_SYS_PLL_1_CTLBUS_HI_CTL_BITS_37_32_SHIFT 0
/***************************************************************************
*SYS_PLL_1_CTLBUS_LO - SYS 1 PLL control bus lower word
***************************************************************************/
/* CLK :: SYS_PLL_1_CTLBUS_LO :: CTL_BITS_31_0 [31:00] */
#define BCHP_CLK_SYS_PLL_1_CTLBUS_LO_CTL_BITS_31_0_MASK 0xffffffff
#define BCHP_CLK_SYS_PLL_1_CTLBUS_LO_CTL_BITS_31_0_SHIFT 0
/***************************************************************************
*SYS_PLL_1_CTRL - SYS PLL 1 m3div, m4div, reset
***************************************************************************/
/* CLK :: SYS_PLL_1_CTRL :: LDO_CTRL [31:30] */
#define BCHP_CLK_SYS_PLL_1_CTRL_LDO_CTRL_MASK 0xc0000000
#define BCHP_CLK_SYS_PLL_1_CTRL_LDO_CTRL_SHIFT 30
/* CLK :: SYS_PLL_1_CTRL :: reserved0 [29:24] */
#define BCHP_CLK_SYS_PLL_1_CTRL_reserved0_MASK 0x3f000000
#define BCHP_CLK_SYS_PLL_1_CTRL_reserved0_SHIFT 24
/* CLK :: SYS_PLL_1_CTRL :: M4DIV [23:16] */
#define BCHP_CLK_SYS_PLL_1_CTRL_M4DIV_MASK 0x00ff0000
#define BCHP_CLK_SYS_PLL_1_CTRL_M4DIV_SHIFT 16
/* CLK :: SYS_PLL_1_CTRL :: M3DIV [15:08] */
#define BCHP_CLK_SYS_PLL_1_CTRL_M3DIV_MASK 0x0000ff00
#define BCHP_CLK_SYS_PLL_1_CTRL_M3DIV_SHIFT 8
/* CLK :: SYS_PLL_1_CTRL :: POWERDOWN [07:07] */
#define BCHP_CLK_SYS_PLL_1_CTRL_POWERDOWN_MASK 0x00000080
#define BCHP_CLK_SYS_PLL_1_CTRL_POWERDOWN_SHIFT 7
#define BCHP_CLK_SYS_PLL_1_CTRL_POWERDOWN_Powerdown 1
#define BCHP_CLK_SYS_PLL_1_CTRL_POWERDOWN_Normal 0
/* CLK :: SYS_PLL_1_CTRL :: reserved1 [06:01] */
#define BCHP_CLK_SYS_PLL_1_CTRL_reserved1_MASK 0x0000007e
#define BCHP_CLK_SYS_PLL_1_CTRL_reserved1_SHIFT 1
/* CLK :: SYS_PLL_1_CTRL :: RESET [00:00] */
#define BCHP_CLK_SYS_PLL_1_CTRL_RESET_MASK 0x00000001
#define BCHP_CLK_SYS_PLL_1_CTRL_RESET_SHIFT 0
#define BCHP_CLK_SYS_PLL_1_CTRL_RESET_Reset 1
#define BCHP_CLK_SYS_PLL_1_CTRL_RESET_Normal 0
/***************************************************************************
*GENET_NETWORK_PLL_CTRL - GENET NETWORK PLL reset
***************************************************************************/
/* CLK :: GENET_NETWORK_PLL_CTRL :: LDO_CTRL [31:30] */
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_LDO_CTRL_MASK 0xc0000000
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_LDO_CTRL_SHIFT 30
/* CLK :: GENET_NETWORK_PLL_CTRL :: reserved0 [29:09] */
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_reserved0_MASK 0x3ffffe00
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_reserved0_SHIFT 9
/* CLK :: GENET_NETWORK_PLL_CTRL :: INPUTDISABLE [08:08] */
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_INPUTDISABLE_MASK 0x00000100
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_INPUTDISABLE_SHIFT 8
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_INPUTDISABLE_inputdisable 1
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_INPUTDISABLE_Normal 0
/* CLK :: GENET_NETWORK_PLL_CTRL :: POWERDOWN [07:07] */
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_POWERDOWN_MASK 0x00000080
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_POWERDOWN_SHIFT 7
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_POWERDOWN_Powerdown 1
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_POWERDOWN_Normal 0
/* CLK :: GENET_NETWORK_PLL_CTRL :: reserved1 [06:01] */
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_reserved1_MASK 0x0000007e
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_reserved1_SHIFT 1
/* CLK :: GENET_NETWORK_PLL_CTRL :: RESET [00:00] */
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_RESET_MASK 0x00000001
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_RESET_SHIFT 0
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_RESET_Reset 1
#define BCHP_CLK_GENET_NETWORK_PLL_CTRL_RESET_Normal 0
/***************************************************************************
*SYS_PLL_1_1 - SYS_PLL_1 channel 1: 26.087 MHz bluetooth clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable
***************************************************************************/
/* CLK :: SYS_PLL_1_1 :: reserved0 [31:03] */
#define BCHP_CLK_SYS_PLL_1_1_reserved0_MASK 0xfffffff8
#define BCHP_CLK_SYS_PLL_1_1_reserved0_SHIFT 3
/* CLK :: SYS_PLL_1_1 :: DIS_CH [02:02] */
#define BCHP_CLK_SYS_PLL_1_1_DIS_CH_MASK 0x00000004
#define BCHP_CLK_SYS_PLL_1_1_DIS_CH_SHIFT 2
/* CLK :: SYS_PLL_1_1 :: CLOCK_ENA [01:01] */
#define BCHP_CLK_SYS_PLL_1_1_CLOCK_ENA_MASK 0x00000002
#define BCHP_CLK_SYS_PLL_1_1_CLOCK_ENA_SHIFT 1
#define BCHP_CLK_SYS_PLL_1_1_CLOCK_ENA_Enable 1
#define BCHP_CLK_SYS_PLL_1_1_CLOCK_ENA_Disable 0
/* CLK :: SYS_PLL_1_1 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_SYS_PLL_1_1_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_SYS_PLL_1_1_EN_CMLBUF_SHIFT 0
/***************************************************************************
*SYS_PLL_1_2 - SYS_PLL_1 channel 2: 100 MHz PCIe differential clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable
***************************************************************************/
/* CLK :: SYS_PLL_1_2 :: reserved0 [31:03] */
#define BCHP_CLK_SYS_PLL_1_2_reserved0_MASK 0xfffffff8
#define BCHP_CLK_SYS_PLL_1_2_reserved0_SHIFT 3
/* CLK :: SYS_PLL_1_2 :: DIS_CH [02:02] */
#define BCHP_CLK_SYS_PLL_1_2_DIS_CH_MASK 0x00000004
#define BCHP_CLK_SYS_PLL_1_2_DIS_CH_SHIFT 2
/* CLK :: SYS_PLL_1_2 :: CLOCK_ENA [01:01] */
#define BCHP_CLK_SYS_PLL_1_2_CLOCK_ENA_MASK 0x00000002
#define BCHP_CLK_SYS_PLL_1_2_CLOCK_ENA_SHIFT 1
#define BCHP_CLK_SYS_PLL_1_2_CLOCK_ENA_Enable 1
#define BCHP_CLK_SYS_PLL_1_2_CLOCK_ENA_Disable 0
/* CLK :: SYS_PLL_1_2 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_SYS_PLL_1_2_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_SYS_PLL_1_2_EN_CMLBUF_SHIFT 0
/***************************************************************************
*SYS_PLL_1_3 - SYS_PLL_1 channel 3: 225 MHz MocA PHY differential clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable
***************************************************************************/
/* CLK :: SYS_PLL_1_3 :: reserved0 [31:03] */
#define BCHP_CLK_SYS_PLL_1_3_reserved0_MASK 0xfffffff8
#define BCHP_CLK_SYS_PLL_1_3_reserved0_SHIFT 3
/* CLK :: SYS_PLL_1_3 :: DIS_CH [02:02] */
#define BCHP_CLK_SYS_PLL_1_3_DIS_CH_MASK 0x00000004
#define BCHP_CLK_SYS_PLL_1_3_DIS_CH_SHIFT 2
/* CLK :: SYS_PLL_1_3 :: CLOCK_ENA [01:01] */
#define BCHP_CLK_SYS_PLL_1_3_CLOCK_ENA_MASK 0x00000002
#define BCHP_CLK_SYS_PLL_1_3_CLOCK_ENA_SHIFT 1
#define BCHP_CLK_SYS_PLL_1_3_CLOCK_ENA_Enable 1
#define BCHP_CLK_SYS_PLL_1_3_CLOCK_ENA_Disable 0
/* CLK :: SYS_PLL_1_3 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_SYS_PLL_1_3_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_SYS_PLL_1_3_EN_CMLBUF_SHIFT 0
/***************************************************************************
*SYS_PLL_1_4 - SYS_PLL_1 channel 4: 225 MHz MocA CPU differential clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable
***************************************************************************/
/* CLK :: SYS_PLL_1_4 :: reserved0 [31:03] */
#define BCHP_CLK_SYS_PLL_1_4_reserved0_MASK 0xfffffff8
#define BCHP_CLK_SYS_PLL_1_4_reserved0_SHIFT 3
/* CLK :: SYS_PLL_1_4 :: DIS_CH [02:02] */
#define BCHP_CLK_SYS_PLL_1_4_DIS_CH_MASK 0x00000004
#define BCHP_CLK_SYS_PLL_1_4_DIS_CH_SHIFT 2
/* CLK :: SYS_PLL_1_4 :: CLOCK_ENA [01:01] */
#define BCHP_CLK_SYS_PLL_1_4_CLOCK_ENA_MASK 0x00000002
#define BCHP_CLK_SYS_PLL_1_4_CLOCK_ENA_SHIFT 1
#define BCHP_CLK_SYS_PLL_1_4_CLOCK_ENA_Enable 1
#define BCHP_CLK_SYS_PLL_1_4_CLOCK_ENA_Disable 0
/* CLK :: SYS_PLL_1_4 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_SYS_PLL_1_4_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_SYS_PLL_1_4_EN_CMLBUF_SHIFT 0
/***************************************************************************
*SYS_PLL_1_5 - SYS_PLL_1 channel 5: 50 MHz USDS PLL reference clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable
***************************************************************************/
/* CLK :: SYS_PLL_1_5 :: reserved0 [31:03] */
#define BCHP_CLK_SYS_PLL_1_5_reserved0_MASK 0xfffffff8
#define BCHP_CLK_SYS_PLL_1_5_reserved0_SHIFT 3
/* CLK :: SYS_PLL_1_5 :: DIS_CH [02:02] */
#define BCHP_CLK_SYS_PLL_1_5_DIS_CH_MASK 0x00000004
#define BCHP_CLK_SYS_PLL_1_5_DIS_CH_SHIFT 2
/* CLK :: SYS_PLL_1_5 :: CLOCK_ENA [01:01] */
#define BCHP_CLK_SYS_PLL_1_5_CLOCK_ENA_MASK 0x00000002
#define BCHP_CLK_SYS_PLL_1_5_CLOCK_ENA_SHIFT 1
#define BCHP_CLK_SYS_PLL_1_5_CLOCK_ENA_Enable 1
#define BCHP_CLK_SYS_PLL_1_5_CLOCK_ENA_Disable 0
/* CLK :: SYS_PLL_1_5 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_SYS_PLL_1_5_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_SYS_PLL_1_5_EN_CMLBUF_SHIFT 0
/***************************************************************************
*SYS_PLL_1_6 - SYS_PLL_1 channel 6: 100 MHz MocA digital clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable
***************************************************************************/
/* CLK :: SYS_PLL_1_6 :: reserved0 [31:03] */
#define BCHP_CLK_SYS_PLL_1_6_reserved0_MASK 0xfffffff8
#define BCHP_CLK_SYS_PLL_1_6_reserved0_SHIFT 3
/* CLK :: SYS_PLL_1_6 :: DIS_CH [02:02] */
#define BCHP_CLK_SYS_PLL_1_6_DIS_CH_MASK 0x00000004
#define BCHP_CLK_SYS_PLL_1_6_DIS_CH_SHIFT 2
/* CLK :: SYS_PLL_1_6 :: CLOCK_ENA [01:01] */
#define BCHP_CLK_SYS_PLL_1_6_CLOCK_ENA_MASK 0x00000002
#define BCHP_CLK_SYS_PLL_1_6_CLOCK_ENA_SHIFT 1
#define BCHP_CLK_SYS_PLL_1_6_CLOCK_ENA_Enable 1
#define BCHP_CLK_SYS_PLL_1_6_CLOCK_ENA_Disable 0
/* CLK :: SYS_PLL_1_6 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_SYS_PLL_1_6_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_SYS_PLL_1_6_EN_CMLBUF_SHIFT 0
/***************************************************************************
*GENET_NETWORK_PLL_1 - GENET_NETWORK_PLL channel 1: 250 MHz RGMII and dvp_ht clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable
***************************************************************************/
/* CLK :: GENET_NETWORK_PLL_1 :: reserved0 [31:03] */
#define BCHP_CLK_GENET_NETWORK_PLL_1_reserved0_MASK 0xfffffff8
#define BCHP_CLK_GENET_NETWORK_PLL_1_reserved0_SHIFT 3
/* CLK :: GENET_NETWORK_PLL_1 :: DIS_CH [02:02] */
#define BCHP_CLK_GENET_NETWORK_PLL_1_DIS_CH_MASK 0x00000004
#define BCHP_CLK_GENET_NETWORK_PLL_1_DIS_CH_SHIFT 2
/* CLK :: GENET_NETWORK_PLL_1 :: CLOCK_ENA [01:01] */
#define BCHP_CLK_GENET_NETWORK_PLL_1_CLOCK_ENA_MASK 0x00000002
#define BCHP_CLK_GENET_NETWORK_PLL_1_CLOCK_ENA_SHIFT 1
#define BCHP_CLK_GENET_NETWORK_PLL_1_CLOCK_ENA_Enable 1
#define BCHP_CLK_GENET_NETWORK_PLL_1_CLOCK_ENA_Disable 0
/* CLK :: GENET_NETWORK_PLL_1 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_GENET_NETWORK_PLL_1_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_GENET_NETWORK_PLL_1_EN_CMLBUF_SHIFT 0
/***************************************************************************
*GENET_NETWORK_PLL_3 - GENET_NETWORK_PLL channel 3: 25 MHz internal EPHY clock, PLL source post divider powerdown, channel gate on/off and cml buffer enable
***************************************************************************/
/* CLK :: GENET_NETWORK_PLL_3 :: reserved0 [31:03] */
#define BCHP_CLK_GENET_NETWORK_PLL_3_reserved0_MASK 0xfffffff8
#define BCHP_CLK_GENET_NETWORK_PLL_3_reserved0_SHIFT 3
/* CLK :: GENET_NETWORK_PLL_3 :: DIS_CH [02:02] */
#define BCHP_CLK_GENET_NETWORK_PLL_3_DIS_CH_MASK 0x00000004
#define BCHP_CLK_GENET_NETWORK_PLL_3_DIS_CH_SHIFT 2
/* CLK :: GENET_NETWORK_PLL_3 :: CLOCK_ENA [01:01] */
#define BCHP_CLK_GENET_NETWORK_PLL_3_CLOCK_ENA_MASK 0x00000002
#define BCHP_CLK_GENET_NETWORK_PLL_3_CLOCK_ENA_SHIFT 1
#define BCHP_CLK_GENET_NETWORK_PLL_3_CLOCK_ENA_Enable 1
#define BCHP_CLK_GENET_NETWORK_PLL_3_CLOCK_ENA_Disable 0
/* CLK :: GENET_NETWORK_PLL_3 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_GENET_NETWORK_PLL_3_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_GENET_NETWORK_PLL_3_EN_CMLBUF_SHIFT 0
/***************************************************************************
*GENET_NETWORK_PLL_4 - GENET_NETWORK_PLL channel 4: 75 MHz SATA PLL reference clocks, PLL source post divider powerdown, channel gate on/off and cml buffer enable
***************************************************************************/
/* CLK :: GENET_NETWORK_PLL_4 :: reserved0 [31:03] */
#define BCHP_CLK_GENET_NETWORK_PLL_4_reserved0_MASK 0xfffffff8
#define BCHP_CLK_GENET_NETWORK_PLL_4_reserved0_SHIFT 3
/* CLK :: GENET_NETWORK_PLL_4 :: DIS_CH [02:02] */
#define BCHP_CLK_GENET_NETWORK_PLL_4_DIS_CH_MASK 0x00000004
#define BCHP_CLK_GENET_NETWORK_PLL_4_DIS_CH_SHIFT 2
/* CLK :: GENET_NETWORK_PLL_4 :: CLOCK_ENA [01:01] */
#define BCHP_CLK_GENET_NETWORK_PLL_4_CLOCK_ENA_MASK 0x00000002
#define BCHP_CLK_GENET_NETWORK_PLL_4_CLOCK_ENA_SHIFT 1
#define BCHP_CLK_GENET_NETWORK_PLL_4_CLOCK_ENA_Enable 1
#define BCHP_CLK_GENET_NETWORK_PLL_4_CLOCK_ENA_Disable 0
/* CLK :: GENET_NETWORK_PLL_4 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_GENET_NETWORK_PLL_4_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_GENET_NETWORK_PLL_4_EN_CMLBUF_SHIFT 0
/***************************************************************************
*GENET_NETWORK_PLL_5 - GENET_NETWORK_PLL channel 5: 125 MHz genet_top clockchannel 5: 125 MHz genet_top clock , PLL source post divider powerdown, channel gate on/off and cml buffer enable
***************************************************************************/
/* CLK :: GENET_NETWORK_PLL_5 :: reserved0 [31:03] */
#define BCHP_CLK_GENET_NETWORK_PLL_5_reserved0_MASK 0xfffffff8
#define BCHP_CLK_GENET_NETWORK_PLL_5_reserved0_SHIFT 3
/* CLK :: GENET_NETWORK_PLL_5 :: DIS_CH [02:02] */
#define BCHP_CLK_GENET_NETWORK_PLL_5_DIS_CH_MASK 0x00000004
#define BCHP_CLK_GENET_NETWORK_PLL_5_DIS_CH_SHIFT 2
/* CLK :: GENET_NETWORK_PLL_5 :: CLOCK_ENA [01:01] */
#define BCHP_CLK_GENET_NETWORK_PLL_5_CLOCK_ENA_MASK 0x00000002
#define BCHP_CLK_GENET_NETWORK_PLL_5_CLOCK_ENA_SHIFT 1
#define BCHP_CLK_GENET_NETWORK_PLL_5_CLOCK_ENA_Enable 1
#define BCHP_CLK_GENET_NETWORK_PLL_5_CLOCK_ENA_Disable 0
/* CLK :: GENET_NETWORK_PLL_5 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_GENET_NETWORK_PLL_5_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_GENET_NETWORK_PLL_5_EN_CMLBUF_SHIFT 0
/***************************************************************************
*GENET_NETWORK_PLL_6 - GENET_NETWORK_PLL channel 6: 25 MHz clock to external GPHY , PLL source post divider powerdown, channel gate on/off and cml buffer enable
***************************************************************************/
/* CLK :: GENET_NETWORK_PLL_6 :: reserved0 [31:03] */
#define BCHP_CLK_GENET_NETWORK_PLL_6_reserved0_MASK 0xfffffff8
#define BCHP_CLK_GENET_NETWORK_PLL_6_reserved0_SHIFT 3
/* CLK :: GENET_NETWORK_PLL_6 :: DIS_CH [02:02] */
#define BCHP_CLK_GENET_NETWORK_PLL_6_DIS_CH_MASK 0x00000004
#define BCHP_CLK_GENET_NETWORK_PLL_6_DIS_CH_SHIFT 2
/* CLK :: GENET_NETWORK_PLL_6 :: CLOCK_ENA [01:01] */
#define BCHP_CLK_GENET_NETWORK_PLL_6_CLOCK_ENA_MASK 0x00000002
#define BCHP_CLK_GENET_NETWORK_PLL_6_CLOCK_ENA_SHIFT 1
#define BCHP_CLK_GENET_NETWORK_PLL_6_CLOCK_ENA_Enable 1
#define BCHP_CLK_GENET_NETWORK_PLL_6_CLOCK_ENA_Disable 0
/* CLK :: GENET_NETWORK_PLL_6 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_GENET_NETWORK_PLL_6_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_GENET_NETWORK_PLL_6_EN_CMLBUF_SHIFT 0
/***************************************************************************
*SYS_PLL_0_PLL_3 - SYS_PLL_0 channel 3: 81 MHz clocks to core_xpt, PLL source post divider powerdown and cml buffer enable
***************************************************************************/
/* CLK :: SYS_PLL_0_PLL_3 :: reserved0 [31:02] */
#define BCHP_CLK_SYS_PLL_0_PLL_3_reserved0_MASK 0xfffffffc
#define BCHP_CLK_SYS_PLL_0_PLL_3_reserved0_SHIFT 2
/* CLK :: SYS_PLL_0_PLL_3 :: DIS_CH [01:01] */
#define BCHP_CLK_SYS_PLL_0_PLL_3_DIS_CH_MASK 0x00000002
#define BCHP_CLK_SYS_PLL_0_PLL_3_DIS_CH_SHIFT 1
/* CLK :: SYS_PLL_0_PLL_3 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_SYS_PLL_0_PLL_3_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_SYS_PLL_0_PLL_3_EN_CMLBUF_SHIFT 0
/***************************************************************************
*SYS_PLL_0_PLL_4 - SYS_PLL_0 channel 4: 48 MHz USB PLL reference clocks, PLL source post divider powerdown and cml buffer enable
***************************************************************************/
/* CLK :: SYS_PLL_0_PLL_4 :: reserved0 [31:02] */
#define BCHP_CLK_SYS_PLL_0_PLL_4_reserved0_MASK 0xfffffffc
#define BCHP_CLK_SYS_PLL_0_PLL_4_reserved0_SHIFT 2
/* CLK :: SYS_PLL_0_PLL_4 :: DIS_CH [01:01] */
#define BCHP_CLK_SYS_PLL_0_PLL_4_DIS_CH_MASK 0x00000002
#define BCHP_CLK_SYS_PLL_0_PLL_4_DIS_CH_SHIFT 1
/* CLK :: SYS_PLL_0_PLL_4 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_SYS_PLL_0_PLL_4_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_SYS_PLL_0_PLL_4_EN_CMLBUF_SHIFT 0
/***************************************************************************
*SYS_PLL_0_PLL_5 - SYS_PLL_0 channel 5: 33.23 MHz PCI clock, PLL source post divider powerdown and cml buffer enable
***************************************************************************/
/* CLK :: SYS_PLL_0_PLL_5 :: reserved0 [31:02] */
#define BCHP_CLK_SYS_PLL_0_PLL_5_reserved0_MASK 0xfffffffc
#define BCHP_CLK_SYS_PLL_0_PLL_5_reserved0_SHIFT 2
/* CLK :: SYS_PLL_0_PLL_5 :: DIS_CH [01:01] */
#define BCHP_CLK_SYS_PLL_0_PLL_5_DIS_CH_MASK 0x00000002
#define BCHP_CLK_SYS_PLL_0_PLL_5_DIS_CH_SHIFT 1
/* CLK :: SYS_PLL_0_PLL_5 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_SYS_PLL_0_PLL_5_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_SYS_PLL_0_PLL_5_EN_CMLBUF_SHIFT 0
/***************************************************************************
*SYS_PLL_0_PLL_6 - SYS_PLL_0 channel 6: 129.6 MHz SATA PCI and DAA clocks, PLL source post divider powerdown and cml buffer enable
***************************************************************************/
/* CLK :: SYS_PLL_0_PLL_6 :: reserved0 [31:02] */
#define BCHP_CLK_SYS_PLL_0_PLL_6_reserved0_MASK 0xfffffffc
#define BCHP_CLK_SYS_PLL_0_PLL_6_reserved0_SHIFT 2
/* CLK :: SYS_PLL_0_PLL_6 :: DIS_CH [01:01] */
#define BCHP_CLK_SYS_PLL_0_PLL_6_DIS_CH_MASK 0x00000002
#define BCHP_CLK_SYS_PLL_0_PLL_6_DIS_CH_SHIFT 1
/* CLK :: SYS_PLL_0_PLL_6 :: EN_CMLBUF [00:00] */
#define BCHP_CLK_SYS_PLL_0_PLL_6_EN_CMLBUF_MASK 0x00000001
#define BCHP_CLK_SYS_PLL_0_PLL_6_EN_CMLBUF_SHIFT 0
/***************************************************************************
*SYS_PLL_0_CTRL - SYS PLL 0 reset, ch_disable, output_delay and powerdown
***************************************************************************/
/* CLK :: SYS_PLL_0_CTRL :: RST_STATUS [31:31] */
#define BCHP_CLK_SYS_PLL_0_CTRL_RST_STATUS_MASK 0x80000000
#define BCHP_CLK_SYS_PLL_0_CTRL_RST_STATUS_SHIFT 31
/* CLK :: SYS_PLL_0_CTRL :: reserved0 [30:12] */
#define BCHP_CLK_SYS_PLL_0_CTRL_reserved0_MASK 0x7ffff000
#define BCHP_CLK_SYS_PLL_0_CTRL_reserved0_SHIFT 12
/* CLK :: SYS_PLL_0_CTRL :: SYS_PLL_0_DLY_CH6 [11:10] */
#define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH6_MASK 0x00000c00
#define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH6_SHIFT 10
/* CLK :: SYS_PLL_0_CTRL :: SYS_PLL_0_DLY_CH5 [09:08] */
#define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH5_MASK 0x00000300
#define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH5_SHIFT 8
/* CLK :: SYS_PLL_0_CTRL :: SYS_PLL_0_DLY_CH4 [07:06] */
#define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH4_MASK 0x000000c0
#define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH4_SHIFT 6
/* CLK :: SYS_PLL_0_CTRL :: SYS_PLL_0_DLY_CH3 [05:04] */
#define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH3_MASK 0x00000030
#define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH3_SHIFT 4
/* CLK :: SYS_PLL_0_CTRL :: SYS_PLL_0_DLY_CH2 [03:02] */
#define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH2_MASK 0x0000000c
#define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH2_SHIFT 2
/* CLK :: SYS_PLL_0_CTRL :: SYS_PLL_0_DLY_CH1 [01:00] */
#define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH1_MASK 0x00000003
#define BCHP_CLK_SYS_PLL_0_CTRL_SYS_PLL_0_DLY_CH1_SHIFT 0
/***************************************************************************
*MIPS_PLL_CTRL - MIPS PLL reset, ch_disable, cpu frequency select, output_delay and powerdown
***************************************************************************/
/* CLK :: MIPS_PLL_CTRL :: RST_STATUS [31:31] */
#define BCHP_CLK_MIPS_PLL_CTRL_RST_STATUS_MASK 0x80000000
#define BCHP_CLK_MIPS_PLL_CTRL_RST_STATUS_SHIFT 31
/* CLK :: MIPS_PLL_CTRL :: BYPASS_PLL_RQ [30:30] */
#define BCHP_CLK_MIPS_PLL_CTRL_BYPASS_PLL_RQ_MASK 0x40000000
#define BCHP_CLK_MIPS_PLL_CTRL_BYPASS_PLL_RQ_SHIFT 30
/* CLK :: MIPS_PLL_CTRL :: BYPASS_PLL_STATE [29:29] */
#define BCHP_CLK_MIPS_PLL_CTRL_BYPASS_PLL_STATE_MASK 0x20000000
#define BCHP_CLK_MIPS_PLL_CTRL_BYPASS_PLL_STATE_SHIFT 29
#define BCHP_CLK_MIPS_PLL_CTRL_BYPASS_PLL_STATE_normal_PLL_mode 0
#define BCHP_CLK_MIPS_PLL_CTRL_BYPASS_PLL_STATE_bypassed_PLL_mode 1
/* union - case normal_PLL_mode [28:22] */
/* CLK :: MIPS_PLL_CTRL :: normal_PLL_mode :: A_RST_PLL [28:28] */
#define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_A_RST_PLL_MASK 0x10000000
#define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_A_RST_PLL_SHIFT 28
/* CLK :: MIPS_PLL_CTRL :: normal_PLL_mode :: D_RST_PLL [27:27] */
#define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_D_RST_PLL_MASK 0x08000000
#define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_D_RST_PLL_SHIFT 27
/* CLK :: MIPS_PLL_CTRL :: normal_PLL_mode :: CPU_FREQ [26:23] */
#define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_CPU_FREQ_MASK 0x07800000
#define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_CPU_FREQ_SHIFT 23
/* CLK :: MIPS_PLL_CTRL :: normal_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [22:22] */
#define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00400000
#define BCHP_CLK_MIPS_PLL_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 22
/* union - case bypassed_PLL_mode [28:22] */
/* CLK :: MIPS_PLL_CTRL :: bypassed_PLL_mode :: A_RST_PLL [28:28] */
#define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_A_RST_PLL_MASK 0x10000000
#define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_A_RST_PLL_SHIFT 28
/* CLK :: MIPS_PLL_CTRL :: bypassed_PLL_mode :: D_RST_PLL [27:27] */
#define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_D_RST_PLL_MASK 0x08000000
#define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_D_RST_PLL_SHIFT 27
/* CLK :: MIPS_PLL_CTRL :: bypassed_PLL_mode :: CPU_FREQ [26:23] */
#define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_CPU_FREQ_MASK 0x07800000
#define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_CPU_FREQ_SHIFT 23
/* CLK :: MIPS_PLL_CTRL :: bypassed_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [22:22] */
#define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00400000
#define BCHP_CLK_MIPS_PLL_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 22
/* CLK :: MIPS_PLL_CTRL :: reserved0 [21:19] */
#define BCHP_CLK_MIPS_PLL_CTRL_reserved0_MASK 0x00380000
#define BCHP_CLK_MIPS_PLL_CTRL_reserved0_SHIFT 19
/* CLK :: MIPS_PLL_CTRL :: DIS_MIPS_PLL_CH1 [18:18] */
#define BCHP_CLK_MIPS_PLL_CTRL_DIS_MIPS_PLL_CH1_MASK 0x00040000
#define BCHP_CLK_MIPS_PLL_CTRL_DIS_MIPS_PLL_CH1_SHIFT 18
/* CLK :: MIPS_PLL_CTRL :: MIPS_DLY_CH3 [17:16] */
#define BCHP_CLK_MIPS_PLL_CTRL_MIPS_DLY_CH3_MASK 0x00030000
#define BCHP_CLK_MIPS_PLL_CTRL_MIPS_DLY_CH3_SHIFT 16
/* CLK :: MIPS_PLL_CTRL :: MIPS_DLY_CH2 [15:14] */
#define BCHP_CLK_MIPS_PLL_CTRL_MIPS_DLY_CH2_MASK 0x0000c000
#define BCHP_CLK_MIPS_PLL_CTRL_MIPS_DLY_CH2_SHIFT 14
/* CLK :: MIPS_PLL_CTRL :: MIPS_DLY_CH1 [13:12] */
#define BCHP_CLK_MIPS_PLL_CTRL_MIPS_DLY_CH1_MASK 0x00003000
#define BCHP_CLK_MIPS_PLL_CTRL_MIPS_DLY_CH1_SHIFT 12
/* CLK :: MIPS_PLL_CTRL :: LDO_CTRL [11:10] */
#define BCHP_CLK_MIPS_PLL_CTRL_LDO_CTRL_MASK 0x00000c00
#define BCHP_CLK_MIPS_PLL_CTRL_LDO_CTRL_SHIFT 10
/* CLK :: MIPS_PLL_CTRL :: reserved1 [09:00] */
#define BCHP_CLK_MIPS_PLL_CTRL_reserved1_MASK 0x000003ff
#define BCHP_CLK_MIPS_PLL_CTRL_reserved1_SHIFT 0
/***************************************************************************
*D2CDIFF_AC_CTRL - AC_CTRL for D2CDIFF
***************************************************************************/
/* CLK :: D2CDIFF_AC_CTRL :: reserved_for_eco0 [31:25] */
#define C0_BCHP_CLK_D2CDIFF_AC_CTRL_reserved_for_eco0_MASK 0xfe000000
#define C0_BCHP_CLK_D2CDIFF_AC_CTRL_reserved_for_eco0_SHIFT 25
/* CLK :: D2CDIFF_AC_CTRL :: CML_RPTR_2_STATUS [24:24] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_2_STATUS_MASK 0x01000000
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_2_STATUS_SHIFT 24
/* CLK :: D2CDIFF_AC_CTRL :: CML_RPTR_1_STATUS [23:23] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_1_STATUS_MASK 0x00800000
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_1_STATUS_SHIFT 23
/* CLK :: D2CDIFF_AC_CTRL :: CML_RPTR_0_STATUS [22:22] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_0_STATUS_MASK 0x00400000
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_0_STATUS_SHIFT 22
/* CLK :: D2CDIFF_AC_CTRL :: CML_RPTR_USB_STATUS [21:21] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_USB_STATUS_MASK 0x00200000
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_USB_STATUS_SHIFT 21
/* CLK :: D2CDIFF_AC_CTRL :: MOCA_STATUS [20:20] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_MOCA_STATUS_MASK 0x00100000
#define BCHP_CLK_D2CDIFF_AC_CTRL_MOCA_STATUS_SHIFT 20
/* CLK :: D2CDIFF_AC_CTRL :: RPTD_STATUS [19:19] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_RPTD_STATUS_MASK 0x00080000
#define BCHP_CLK_D2CDIFF_AC_CTRL_RPTD_STATUS_SHIFT 19
/* CLK :: D2CDIFF_AC_CTRL :: AVD_STATUS [18:18] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_AVD_STATUS_MASK 0x00040000
#define BCHP_CLK_D2CDIFF_AC_CTRL_AVD_STATUS_SHIFT 18
/* CLK :: D2CDIFF_AC_CTRL :: MIPS_STATUS [17:17] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_MIPS_STATUS_MASK 0x00020000
#define BCHP_CLK_D2CDIFF_AC_CTRL_MIPS_STATUS_SHIFT 17
/* CLK :: D2CDIFF_AC_CTRL :: MAIN_STATUS [16:16] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_MAIN_STATUS_MASK 0x00010000
#define BCHP_CLK_D2CDIFF_AC_CTRL_MAIN_STATUS_SHIFT 16
/* CLK :: D2CDIFF_AC_CTRL :: reserved_for_eco0 [15:09] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_reserved_for_eco0_MASK 0x0000fe00
#define BCHP_CLK_D2CDIFF_AC_CTRL_reserved_for_eco0_SHIFT 9
/* CLK :: D2CDIFF_AC_CTRL :: CML_RPTR_2_XOR [08:08] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_2_XOR_MASK 0x00000100
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_2_XOR_SHIFT 8
/* CLK :: D2CDIFF_AC_CTRL :: CML_RPTR_1_XOR [07:07] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_1_XOR_MASK 0x00000080
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_1_XOR_SHIFT 7
/* CLK :: D2CDIFF_AC_CTRL :: CML_RPTR_0_XOR [06:06] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_0_XOR_MASK 0x00000040
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_0_XOR_SHIFT 6
/* CLK :: D2CDIFF_AC_CTRL :: CML_RPTR_USB_XOR [05:05] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_USB_XOR_MASK 0x00000020
#define BCHP_CLK_D2CDIFF_AC_CTRL_CML_RPTR_USB_XOR_SHIFT 5
/* CLK :: D2CDIFF_AC_CTRL :: MOCA_XOR [04:04] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_MOCA_XOR_MASK 0x00000010
#define BCHP_CLK_D2CDIFF_AC_CTRL_MOCA_XOR_SHIFT 4
/* CLK :: D2CDIFF_AC_CTRL :: RPTD_XOR [03:03] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_RPTD_XOR_MASK 0x00000008
#define BCHP_CLK_D2CDIFF_AC_CTRL_RPTD_XOR_SHIFT 3
/* CLK :: D2CDIFF_AC_CTRL :: AVD_XOR [02:02] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_AVD_XOR_MASK 0x00000004
#define BCHP_CLK_D2CDIFF_AC_CTRL_AVD_XOR_SHIFT 2
/* CLK :: D2CDIFF_AC_CTRL :: MIPS_XOR [01:01] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_MIPS_XOR_MASK 0x00000002
#define BCHP_CLK_D2CDIFF_AC_CTRL_MIPS_XOR_SHIFT 1
/* CLK :: D2CDIFF_AC_CTRL :: MAIN_XOR [00:00] */
#define BCHP_CLK_D2CDIFF_AC_CTRL_MAIN_XOR_MASK 0x00000001
#define BCHP_CLK_D2CDIFF_AC_CTRL_MAIN_XOR_SHIFT 0
/***************************************************************************
*SCRATCH - clock_gen Scratch register
***************************************************************************/
/* CLK :: SCRATCH :: VALUE [31:01] */
#define BCHP_CLK_SCRATCH_VALUE_MASK 0xfffffffe
#define BCHP_CLK_SCRATCH_VALUE_SHIFT 1
/* CLK :: SCRATCH :: CML_REPEATER_2_POWERDOWN [00:00] */
#define BCHP_CLK_SCRATCH_CML_REPEATER_2_POWERDOWN_MASK 0x00000001
#define BCHP_CLK_SCRATCH_CML_REPEATER_2_POWERDOWN_SHIFT 0
#endif /* #ifndef BCHP_CLK_H__ */
/* End of File */