| /* |
| * Device Tree Source for the Porter board |
| * |
| * Copyright (C) 2015 Cogent Embedded, Inc. |
| * |
| * This file is licensed under the terms of the GNU General Public License |
| * version 2. This program is licensed "as is" without any warranty of any |
| * kind, whether express or implied. |
| */ |
| |
| /dts-v1/; |
| #include "r8a7791.dtsi" |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| model = "Porter"; |
| compatible = "renesas,porter", "renesas,r8a7791"; |
| |
| aliases { |
| serial0 = &scif0; |
| }; |
| |
| chosen { |
| bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; |
| stdout-path = &scif0; |
| }; |
| |
| memory@40000000 { |
| device_type = "memory"; |
| reg = <0 0x40000000 0 0x40000000>; |
| }; |
| |
| memory@200000000 { |
| device_type = "memory"; |
| reg = <2 0x00000000 0 0x40000000>; |
| }; |
| |
| vcc_sdhi0: regulator@0 { |
| compatible = "regulator-fixed"; |
| |
| regulator-name = "SDHI0 Vcc"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vccq_sdhi0: regulator@1 { |
| compatible = "regulator-gpio"; |
| |
| regulator-name = "SDHI0 VccQ"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| |
| gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; |
| gpios-states = <1>; |
| states = <3300000 1 |
| 1800000 0>; |
| }; |
| |
| vcc_sdhi2: regulator@2 { |
| compatible = "regulator-fixed"; |
| |
| regulator-name = "SDHI2 Vcc"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vccq_sdhi2: regulator@3 { |
| compatible = "regulator-gpio"; |
| |
| regulator-name = "SDHI2 VccQ"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| |
| gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; |
| gpios-states = <1>; |
| states = <3300000 1 |
| 1800000 0>; |
| }; |
| }; |
| |
| &extal_clk { |
| clock-frequency = <20000000>; |
| }; |
| |
| &pfc { |
| scif0_pins: serial0 { |
| renesas,groups = "scif0_data_d"; |
| renesas,function = "scif0"; |
| }; |
| |
| ether_pins: ether { |
| renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; |
| renesas,function = "eth"; |
| }; |
| |
| phy1_pins: phy1 { |
| renesas,groups = "intc_irq0"; |
| renesas,function = "intc"; |
| }; |
| |
| sdhi0_pins: sd0 { |
| renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; |
| renesas,function = "sdhi0"; |
| }; |
| |
| sdhi2_pins: sd2 { |
| renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; |
| renesas,function = "sdhi2"; |
| }; |
| |
| qspi_pins: spi0 { |
| renesas,groups = "qspi_ctrl", "qspi_data4"; |
| renesas,function = "qspi"; |
| }; |
| |
| i2c2_pins: i2c2 { |
| renesas,groups = "i2c2"; |
| renesas,function = "i2c2"; |
| }; |
| |
| usb0_pins: usb0 { |
| renesas,groups = "usb0"; |
| renesas,function = "usb0"; |
| }; |
| |
| usb1_pins: usb1 { |
| renesas,groups = "usb1"; |
| renesas,function = "usb1"; |
| }; |
| |
| vin0_pins: vin0 { |
| renesas,groups = "vin0_data8", "vin0_clk"; |
| renesas,function = "vin0"; |
| }; |
| }; |
| |
| &scif0 { |
| pinctrl-0 = <&scif0_pins>; |
| pinctrl-names = "default"; |
| |
| status = "okay"; |
| }; |
| |
| ðer { |
| pinctrl-0 = <ðer_pins &phy1_pins>; |
| pinctrl-names = "default"; |
| |
| phy-handle = <&phy1>; |
| renesas,ether-link-active-low; |
| status = "ok"; |
| |
| phy1: ethernet-phy@1 { |
| reg = <1>; |
| interrupt-parent = <&irqc0>; |
| interrupts = <0 IRQ_TYPE_LEVEL_LOW>; |
| micrel,led-mode = <1>; |
| }; |
| }; |
| |
| &sdhi0 { |
| pinctrl-0 = <&sdhi0_pins>; |
| pinctrl-names = "default"; |
| |
| vmmc-supply = <&vcc_sdhi0>; |
| vqmmc-supply = <&vccq_sdhi0>; |
| cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; |
| wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| }; |
| |
| &sdhi2 { |
| pinctrl-0 = <&sdhi2_pins>; |
| pinctrl-names = "default"; |
| |
| vmmc-supply = <&vcc_sdhi2>; |
| vqmmc-supply = <&vccq_sdhi2>; |
| cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &qspi { |
| pinctrl-0 = <&qspi_pins>; |
| pinctrl-names = "default"; |
| |
| status = "okay"; |
| |
| flash@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "spansion,s25fl512s", "jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <30000000>; |
| spi-tx-bus-width = <4>; |
| spi-rx-bus-width = <4>; |
| m25p,fast-read; |
| |
| partition@0 { |
| label = "loader_prg"; |
| reg = <0x00000000 0x00040000>; |
| read-only; |
| }; |
| partition@40000 { |
| label = "user_prg"; |
| reg = <0x00040000 0x00400000>; |
| read-only; |
| }; |
| partition@440000 { |
| label = "flash_fs"; |
| reg = <0x00440000 0x03bc0000>; |
| }; |
| }; |
| }; |
| |
| &i2c2 { |
| pinctrl-0 = <&i2c2_pins>; |
| pinctrl-names = "default"; |
| |
| status = "okay"; |
| clock-frequency = <400000>; |
| |
| composite-in@20 { |
| compatible = "adi,adv7180"; |
| reg = <0x20>; |
| remote = <&vin0>; |
| |
| port { |
| adv7180: endpoint { |
| bus-width = <8>; |
| remote-endpoint = <&vin0ep>; |
| }; |
| }; |
| }; |
| }; |
| |
| &sata0 { |
| status = "okay"; |
| }; |
| |
| /* composite video input */ |
| &vin0 { |
| status = "ok"; |
| pinctrl-0 = <&vin0_pins>; |
| pinctrl-names = "default"; |
| |
| port { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| vin0ep: endpoint { |
| remote-endpoint = <&adv7180>; |
| bus-width = <8>; |
| }; |
| }; |
| }; |
| |
| &pci0 { |
| pinctrl-0 = <&usb0_pins>; |
| pinctrl-names = "default"; |
| |
| status = "okay"; |
| }; |
| |
| &pci1 { |
| pinctrl-0 = <&usb1_pins>; |
| pinctrl-names = "default"; |
| |
| status = "okay"; |
| }; |
| |
| &usbphy { |
| status = "okay"; |
| }; |
| |
| &pcie_bus_clk { |
| status = "okay"; |
| }; |
| |
| &pciec { |
| status = "okay"; |
| }; |