| /* |
| * Copyright (c) 2013-2014 Linaro Ltd. |
| * Copyright (c) 2013-2014 Hisilicon Limited. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * publishhed by the Free Software Foundation. |
| */ |
| |
| #include "skeleton.dtsi" |
| #include <dt-bindings/clock/hix5hd2-clock.h> |
| |
| / { |
| aliases { |
| serial0 = &uart0; |
| }; |
| |
| gic: interrupt-controller@f8a01000 { |
| compatible = "arm,cortex-a9-gic"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| /* gic dist base, gic cpu base */ |
| reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; |
| }; |
| |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| ranges = <0 0xf8000000 0x8000000>; |
| |
| amba { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "arm,amba-bus"; |
| ranges; |
| |
| timer0: timer@00002000 { |
| compatible = "arm,sp804", "arm,primecell"; |
| reg = <0x00002000 0x1000>; |
| /* timer00 & timer01 */ |
| interrupts = <0 24 4>; |
| clocks = <&clock HIX5HD2_FIXED_24M>; |
| status = "disabled"; |
| }; |
| |
| timer1: timer@00a29000 { |
| /* |
| * Only used in NORMAL state, not available ins |
| * SLOW or DOZE state. |
| * The rate is fixed in 24MHz. |
| */ |
| compatible = "arm,sp804", "arm,primecell"; |
| reg = <0x00a29000 0x1000>; |
| /* timer10 & timer11 */ |
| interrupts = <0 25 4>; |
| clocks = <&clock HIX5HD2_FIXED_24M>; |
| status = "disabled"; |
| }; |
| |
| timer2: timer@00a2a000 { |
| compatible = "arm,sp804", "arm,primecell"; |
| reg = <0x00a2a000 0x1000>; |
| /* timer20 & timer21 */ |
| interrupts = <0 26 4>; |
| clocks = <&clock HIX5HD2_FIXED_24M>; |
| status = "disabled"; |
| }; |
| |
| timer3: timer@00a2b000 { |
| compatible = "arm,sp804", "arm,primecell"; |
| reg = <0x00a2b000 0x1000>; |
| /* timer30 & timer31 */ |
| interrupts = <0 27 4>; |
| clocks = <&clock HIX5HD2_FIXED_24M>; |
| status = "disabled"; |
| }; |
| |
| timer4: timer@00a81000 { |
| compatible = "arm,sp804", "arm,primecell"; |
| reg = <0x00a81000 0x1000>; |
| /* timer30 & timer31 */ |
| interrupts = <0 28 4>; |
| clocks = <&clock HIX5HD2_FIXED_24M>; |
| status = "disabled"; |
| }; |
| |
| uart0: uart@00b00000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x00b00000 0x1000>; |
| interrupts = <0 49 4>; |
| clocks = <&clock HIX5HD2_FIXED_83M>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| uart1: uart@00006000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x00006000 0x1000>; |
| interrupts = <0 50 4>; |
| clocks = <&clock HIX5HD2_FIXED_83M>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| uart2: uart@00b02000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x00b02000 0x1000>; |
| interrupts = <0 51 4>; |
| clocks = <&clock HIX5HD2_FIXED_83M>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| uart3: uart@00b03000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x00b03000 0x1000>; |
| interrupts = <0 52 4>; |
| clocks = <&clock HIX5HD2_FIXED_83M>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| uart4: uart@00b04000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0xb04000 0x1000>; |
| interrupts = <0 53 4>; |
| clocks = <&clock HIX5HD2_FIXED_83M>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio0: gpio@b20000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb20000 0x1000>; |
| interrupts = <0 108 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio1: gpio@b21000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb21000 0x1000>; |
| interrupts = <0 109 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio2: gpio@b22000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb22000 0x1000>; |
| interrupts = <0 110 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio3: gpio@b23000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb23000 0x1000>; |
| interrupts = <0 111 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio4: gpio@b24000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb24000 0x1000>; |
| interrupts = <0 112 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio5: gpio@004000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x004000 0x1000>; |
| interrupts = <0 113 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio6: gpio@b26000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb26000 0x1000>; |
| interrupts = <0 114 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio7: gpio@b27000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb27000 0x1000>; |
| interrupts = <0 115 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio8: gpio@b28000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb28000 0x1000>; |
| interrupts = <0 116 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio9: gpio@b29000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb29000 0x1000>; |
| interrupts = <0 117 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio10: gpio@b2a000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb2a000 0x1000>; |
| interrupts = <0 118 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio11: gpio@b2b000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb2b000 0x1000>; |
| interrupts = <0 119 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio12: gpio@b2c000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb2c000 0x1000>; |
| interrupts = <0 120 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio13: gpio@b2d000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb2d000 0x1000>; |
| interrupts = <0 121 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio14: gpio@b2e000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb2e000 0x1000>; |
| interrupts = <0 122 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio15: gpio@b2f000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb2f000 0x1000>; |
| interrupts = <0 123 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio16: gpio@b30000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb30000 0x1000>; |
| interrupts = <0 124 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpio17: gpio@b31000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0xb31000 0x1000>; |
| interrupts = <0 125 0x4>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&clock HIX5HD2_FIXED_100M>; |
| clock-names = "apb_pclk"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| wdt0: watchdog@a2c000 { |
| compatible = "arm,sp805", "arm,primecell"; |
| arm,primecell-periphid = <0x00141805>; |
| reg = <0xa2c000 0x1000>; |
| interrupts = <0 29 4>; |
| clocks = <&clock HIX5HD2_WDG0_RST>; |
| clock-names = "apb_pclk"; |
| }; |
| }; |
| |
| local_timer@00a00600 { |
| compatible = "arm,cortex-a9-twd-timer"; |
| reg = <0x00a00600 0x20>; |
| interrupts = <1 13 0xf01>; |
| }; |
| |
| l2: l2-cache { |
| compatible = "arm,pl310-cache"; |
| reg = <0x00a10000 0x100000>; |
| interrupts = <0 15 4>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| |
| sysctrl: system-controller@00000000 { |
| compatible = "hisilicon,sysctrl", "syscon"; |
| reg = <0x00000000 0x1000>; |
| }; |
| |
| reboot { |
| compatible = "syscon-reboot"; |
| regmap = <&sysctrl>; |
| offset = <0x4>; |
| mask = <0xdeadbeef>; |
| }; |
| |
| cpuctrl@00a22000 { |
| compatible = "hisilicon,cpuctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x00a22000 0x2000>; |
| ranges = <0 0x00a22000 0x2000>; |
| |
| clock: clock@0 { |
| compatible = "hisilicon,hix5hd2-clock"; |
| reg = <0 0x2000>; |
| #clock-cells = <1>; |
| }; |
| }; |
| |
| /* unremovable emmc as mmcblk0 */ |
| mmc: mmc@1830000 { |
| compatible = "snps,dw-mshc"; |
| reg = <0x1830000 0x1000>; |
| interrupts = <0 35 4>; |
| clocks = <&clock HIX5HD2_MMC_CIU_RST>, |
| <&clock HIX5HD2_MMC_BIU_CLK>; |
| clock-names = "ciu", "biu"; |
| }; |
| |
| sd: mmc@1820000 { |
| compatible = "snps,dw-mshc"; |
| reg = <0x1820000 0x1000>; |
| interrupts = <0 34 4>; |
| clocks = <&clock HIX5HD2_SD_CIU_RST>, |
| <&clock HIX5HD2_SD_BIU_CLK>; |
| clock-names = "ciu","biu"; |
| }; |
| |
| gmac0: ethernet@1840000 { |
| compatible = "hisilicon,hix5hd2-gmac"; |
| reg = <0x1840000 0x1000>,<0x184300c 0x4>; |
| interrupts = <0 71 4>; |
| clocks = <&clock HIX5HD2_MAC0_CLK>; |
| status = "disabled"; |
| }; |
| |
| gmac1: ethernet@1841000 { |
| compatible = "hisilicon,hix5hd2-gmac"; |
| reg = <0x1841000 0x1000>,<0x1843010 0x4>; |
| interrupts = <0 72 4>; |
| clocks = <&clock HIX5HD2_MAC1_CLK>; |
| status = "disabled"; |
| }; |
| |
| usb0: ehci@1890000 { |
| compatible = "generic-ehci"; |
| reg = <0x1890000 0x1000>; |
| interrupts = <0 66 4>; |
| clocks = <&clock HIX5HD2_USB_CLK>; |
| }; |
| |
| usb1: ohci@1880000 { |
| compatible = "generic-ohci"; |
| reg = <0x1880000 0x1000>; |
| interrupts = <0 67 4>; |
| clocks = <&clock HIX5HD2_USB_CLK>; |
| }; |
| |
| peripheral_ctrl: syscon@a20000 { |
| compatible = "syscon"; |
| reg = <0xa20000 0x1000>; |
| }; |
| |
| sata_phy: phy@1900000 { |
| compatible = "hisilicon,hix5hd2-sata-phy"; |
| reg = <0x1900000 0x10000>; |
| #phy-cells = <0>; |
| hisilicon,peripheral-syscon = <&peripheral_ctrl>; |
| hisilicon,power-reg = <0x8 10>; |
| }; |
| |
| ahci: sata@1900000 { |
| compatible = "hisilicon,hisi-ahci"; |
| reg = <0x1900000 0x10000>; |
| interrupts = <0 70 4>; |
| clocks = <&clock HIX5HD2_SATA_CLK>; |
| }; |
| |
| ir: ir@001000 { |
| compatible = "hisilicon,hix5hd2-ir"; |
| reg = <0x001000 0x1000>; |
| interrupts = <0 47 4>; |
| clocks = <&clock HIX5HD2_FIXED_24M>; |
| hisilicon,power-syscon = <&sysctrl>; |
| }; |
| |
| i2c0: i2c@b10000 { |
| compatible = "hisilicon,hix5hd2-i2c"; |
| reg = <0xb10000 0x1000>; |
| interrupts = <0 38 4>; |
| clocks = <&clock HIX5HD2_I2C0_RST>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@b11000 { |
| compatible = "hisilicon,hix5hd2-i2c"; |
| reg = <0xb11000 0x1000>; |
| interrupts = <0 39 4>; |
| clocks = <&clock HIX5HD2_I2C1_RST>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@b12000 { |
| compatible = "hisilicon,hix5hd2-i2c"; |
| reg = <0xb12000 0x1000>; |
| interrupts = <0 40 4>; |
| clocks = <&clock HIX5HD2_I2C2_RST>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@b13000 { |
| compatible = "hisilicon,hix5hd2-i2c"; |
| reg = <0xb13000 0x1000>; |
| interrupts = <0 41 4>; |
| clocks = <&clock HIX5HD2_I2C3_RST>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@b16000 { |
| compatible = "hisilicon,hix5hd2-i2c"; |
| reg = <0xb16000 0x1000>; |
| interrupts = <0 43 4>; |
| clocks = <&clock HIX5HD2_I2C4_RST>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@b17000 { |
| compatible = "hisilicon,hix5hd2-i2c"; |
| reg = <0xb17000 0x1000>; |
| interrupts = <0 44 4>; |
| clocks = <&clock HIX5HD2_I2C5_RST>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
