| #include "comcerto-2000.h" | |
| #include "gpio.h" | |
| #include "comcerto_spi.h" | |
| #define COMCERTO_NTG_BASE (COMCERTO_CLKCORE_BASE + 0x280) | |
| // TDM Registers | |
| #define TDM0_VERISON (COMCERTO_TDM_BASE + 0x0000) | |
| #define TDM0_NETWORK (COMCERTO_TDM_BASE + 0x0004) | |
| #define TDM0_TX (COMCERTO_TDM_BASE + 0x0010) | |
| #define TDM0_TX_TSEN_A (COMCERTO_TDM_BASE + 0x0014) | |
| #define TDM0_TX_TSEN_B (COMCERTO_TDM_BASE + 0x0018) | |
| #define TDM0_TX_TSEN_C (COMCERTO_TDM_BASE + 0x001c) | |
| #define TDM0_TX_TSEN_D (COMCERTO_TDM_BASE + 0x0020) | |
| #define TDM0_RX (COMCERTO_TDM_BASE + 0x0030) | |
| #define TDM0_RX_TSEN_A (COMCERTO_TDM_BASE + 0x0034) | |
| #define TDM0_RX_TSEN_B (COMCERTO_TDM_BASE + 0x0038) | |
| #define TDM0_RX_TSEN_C (COMCERTO_TDM_BASE + 0x003c) | |
| #define TDM0_RX_TSEN_D (COMCERTO_TDM_BASE + 0x0040) | |
| #define TDM0_CTSEN_A (COMCERTO_TDM_BASE + 0x0050) | |
| #define TDM0_CTSEN_B (COMCERTO_TDM_BASE + 0x0054) | |
| #define TDM0_CTSEN_C (COMCERTO_TDM_BASE + 0x0058) | |
| #define TDM0_CTSEN_D (COMCERTO_TDM_BASE + 0x005c) | |
| #define TDM1_VERISON (COMCERTO_TDM_BASE + 0x1000) | |
| #define TDM1_NETWORK (COMCERTO_TDM_BASE + 0x1004) | |
| #define TDM1_TX (COMCERTO_TDM_BASE + 0x1010) | |
| #define TDM1_TX_TSEN_A (COMCERTO_TDM_BASE + 0x1014) | |
| #define TDM1_RX (COMCERTO_TDM_BASE + 0x1030) | |
| #define TDM1_RX_TSEN_A (COMCERTO_TDM_BASE + 0x1034) | |
| #define TDM1_CTSEN (COMCERTO_TDM_BASE + 0x1050) | |
| // TDMA Registers | |
| #define TDM_RX_DMA_ENABLE (COMCERTO_TDMA_BASE + 0x0004) | |
| #define TDM_TX_DMA_ENABLE (COMCERTO_TDMA_BASE + 0x0008) | |
| #define IRQ2TDMA_INTERRUPT_ENABLE (COMCERTO_TDMA_BASE + 0x0010) | |
| #define TDMA_BASE_BIST_CTRL (COMCERTO_TDMA_BASE + 0x0014) | |
| #define TDMA_TDM0RX_BIST_CTRL (COMCERTO_TDMA_BASE + 0x0018) | |
| #define TDMA_TDM0TX_BIST_CTRL (COMCERTO_TDMA_BASE + 0x001c) | |
| #define TDM_BLOCK_SIZE (COMCERTO_TDMA_BASE + 0x0020) | |
| #define TDMA_TDM1RX_BIST_CTRL (COMCERTO_TDMA_BASE + 0x2018) | |
| #define TDMA_TDM1TX_BIST_CTRL (COMCERTO_TDMA_BASE + 0x201c) | |
| #define TDMA0_MEMSEG (COMCERTO_TDMA_BASE + 0x0000) | |
| #define TDMA0_RXDMAEN (COMCERTO_TDMA_BASE + 0x0004) | |
| #define TDMA0_TXDMAEN (COMCERTO_TDMA_BASE + 0x0008) | |
| #define TDMA0_BLKSIZE (COMCERTO_TDMA_BASE + 0x0020) | |
| #define TDMA0_INTSIZE (COMCERTO_TDMA_BASE + 0x0024) | |
| #define TDMA0_RXBFPTR (COMCERTO_TDMA_BASE + 0x0028) | |
| #define TDMA0_TXBFPTR (COMCERTO_TDMA_BASE + 0x002c) | |
| #define TDMA0_BACKCOM (COMCERTO_TDMA_BASE + 0x0030) | |
| #define TDMA0_RXCHEN_A (COMCERTO_TDMA_BASE + 0x0060) | |
| #define TDMA0_RXCHEN_B (COMCERTO_TDMA_BASE + 0x0064) | |
| #define TDMA0_RXCHEN_C (COMCERTO_TDMA_BASE + 0x0068) | |
| #define TDMA0_RXCHEN_D (COMCERTO_TDMA_BASE + 0x006c) | |
| #define TDMA0_TXCHEN_A (COMCERTO_TDMA_BASE + 0x0070) | |
| #define TDMA0_TXCHEN_B (COMCERTO_TDMA_BASE + 0x0074) | |
| #define TDMA0_TXCHEN_C (COMCERTO_TDMA_BASE + 0x0078) | |
| #define TDMA0_TXCHEN_D (COMCERTO_TDMA_BASE + 0x007c) | |
| #define TDMA0_RXBASE0 (COMCERTO_TDMA_BASE + 0x1000) | |
| #define TDMA0_TXBASE0 (COMCERTO_TDMA_BASE + 0x1200) | |
| #define TDMA0_RXLKTB0 (COMCERTO_TDMA_BASE + 0x1400) | |
| #define TDMA0_TXLKTB0 (COMCERTO_TDMA_BASE + 0x1600) | |
| #define TDMA0_TXBUF (COMCERTO_TDMA_BASE + 0x1C00) | |
| #define TDMA1_MEMSEG (COMCERTO_TDMA_BASE + 0x2000) | |
| #define TDMA1_RXDMAEN (COMCERTO_TDMA_BASE + 0x2004) | |
| #define TDMA1_TXDMAEN (COMCERTO_TDMA_BASE + 0x2008) | |
| #define TDMA1_BLKSIZE (COMCERTO_TDMA_BASE + 0x2020) | |
| #define TDMA1_INTSIZE (COMCERTO_TDMA_BASE + 0x2024) | |
| #define TDMA1_RXBFPTR (COMCERTO_TDMA_BASE + 0x2028) | |
| #define TDMA1_TXBFPTR (COMCERTO_TDMA_BASE + 0x202c) | |
| #define TDMA1_BACKCOM (COMCERTO_TDMA_BASE + 0x2030) | |
| #define TDMA1_RXCHEN_A (COMCERTO_TDMA_BASE + 0x2060) | |
| #define TDMA1_RXCHEN_B (COMCERTO_TDMA_BASE + 0x2064) | |
| #define TDMA1_RXCHEN_C (COMCERTO_TDMA_BASE + 0x2068) | |
| #define TDMA1_RXCHEN_D (COMCERTO_TDMA_BASE + 0x206c) | |
| #define TDMA1_TXCHEN_A (COMCERTO_TDMA_BASE + 0x2070) | |
| #define TDMA1_TXCHEN_B (COMCERTO_TDMA_BASE + 0x2074) | |
| #define TDMA1_TXCHEN_C (COMCERTO_TDMA_BASE + 0x2078) | |
| #define TDMA1_TXCHEN_D (COMCERTO_TDMA_BASE + 0x207c) | |
| #define TDMA1_RXBASE0 (COMCERTO_TDMA_BASE + 0x3000) | |
| #define TDMA1_TXBASE0 (COMCERTO_TDMA_BASE + 0x3200) | |
| #define TDMA1_RXLKTB0 (COMCERTO_TDMA_BASE + 0x3400) | |
| #define TDMA1_TXLKTB0 (COMCERTO_TDMA_BASE + 0x3600) | |
| #define TDMA1_TXBUF (COMCERTO_TDMA_BASE + 0x3C00) | |
| #define TDMA0_IRQ2STAT (COMCERTO_TDMA_BASE + 0x000c) | |
| #define TDMA1_IRQ2STAT (COMCERTO_TDMA_BASE + 0x200c) | |
| #define NTG_FREQ_SET_INT (COMCERTO_NTG_BASE + 0x00) | |
| #define NTG_FREQ_SET_FRA (COMCERTO_NTG_BASE + 0x04) | |
| #define NTG_PHASE_ADJ_FREQ_INT (COMCERTO_NTG_BASE + 0x10) | |
| #define CLOCK_RESET_SLIC_CONTROL (COMCERTO_APB_CLK_BASE + 0x14C) | |
| #define IRAM_CHKER_SRC_ADDR 0x83000000 | |
| #define IRAM_CHKER_DEST_ADDR 0x83000004 | |
| #define IRAM_CHKER_LENGTH 0x83000008 | |
| #define IRAM_CHKER_CONTROL 0x8300000C | |
| #define IRAM_CHKER_START 31 | |
| #define ENABLE 0x1 | |