Drop support for GPIO44 == POE_ACTIVE
On some old pre-PVT boards, GPIO 44 was connected to the reset line of
the PoE circuit. Drop support for these boards. On newer boards, GPIO 44
is either connected to the QCA8337N interrupt line (Optimus) or
USB_ALARM (Optimus Prime).
Change-Id: Ibf1ed525f255cc9b013e285ba874109b5a603777
diff --git a/arch/arm/boards/optimus/optimus.c b/arch/arm/boards/optimus/optimus.c
index dba5967..eda5f6a 100644
--- a/arch/arm/boards/optimus/optimus.c
+++ b/arch/arm/boards/optimus/optimus.c
@@ -465,7 +465,6 @@
* GPIO 13: system red LED
* GPIO 14: AR8337 reset, active low
* GPIO 15: USB power switch enable, active high
- * GPIO 44: Power Over Ethernet, needs to be set low
* GPIO 48: Power enable for high power wifi 11AC 4.2V PA, needs to be
* set high
*/
@@ -489,10 +488,6 @@
*/
writel(readl(COMCERTO_GPIO_MISC_PIN_SELECT_REG) | 2 << 4, COMCERTO_GPIO_MISC_PIN_SELECT_REG);
- /* GPIO[44] and CORESIGHT_D[0] are muxed on the same pin. Set pin
- * Select Register to select GPIO[44]. Pin Output Register is 0 by
- * default. */
- writel(readl(COMCERTO_GPIO_63_32_PIN_SELECT_REG) | 1<<(44-32), COMCERTO_GPIO_63_32_PIN_SELECT_REG);
/* GPIO[48] and CORESIGHT_D[4] are muxed on the same pin. Set pin
* Select Register to select GPIO[48]. */
writel(readl(COMCERTO_GPIO_63_32_PIN_SELECT_REG) | 1<<(48-32), COMCERTO_GPIO_63_32_PIN_SELECT_REG);
