| //$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$//; |
| //Defining the USB3 PHY CONTROL REGISTER VALUES FOR BER TEST; |
| //$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$//; |
| |
| #define U16 u16 |
| |
| U16 SSP_CR_SUP_DIG_IDCODE_LO_val = 0x04cd; |
| U16 SSP_CR_SUP_DIG_IDCODE_HI_val = 0x3006; |
| U16 SSP_CR_SUP_DIG_DEBUG_val = 0x000a; |
| U16 SSP_CR_SUP_DIG_SS_PHASE_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SS_FREQ_val = 0x3327; |
| U16 SSP_CR_SUP_DIG_ATEOVRD_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_val = 0x004c; |
| U16 SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SSC_OVRD_IN_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_BS_OVRD_IN_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_LEVEL_OVRD_IN_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SUP_OVRD_OUT_val = 0x0101; |
| U16 SSP_CR_SUP_DIG_MPLL_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_BS_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_LEVEL_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SSC_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SUP_ASIC_OUT_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_ATEOVRD_STATUS_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_RTUNE_DEBUG_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_RTUNE_STAT_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SCOPE_ENABLES_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SCOPE_SAMPLES_val = 0x0100; |
| U16 SSP_CR_SUP_DIG_SCOPE_COUNT_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SCOPE_CTL_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_000_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_001_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_010_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_011_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_100_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_101_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_110_val = 0x0000; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_111_val = 0x0000; |
| U16 SSP_CR_SUP_ANA_MPLL_LOOP_CTL_val = 0x00c0; |
| U16 SSP_CR_SUP_ANA_MPLL_ATB_MEAS1_val = 0x0000; |
| U16 SSP_CR_SUP_ANA_MPLL_ATB_MEAS2_val = 0x0000; |
| U16 SSP_CR_SUP_ANA_MPLL_OVRD_val = 0x0000; |
| U16 SSP_CR_SUP_ANA_RTUNE_RTUNE_CTRL_val = 0x0000; |
| U16 SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL_val = 0x0000; |
| U16 SSP_CR_SUP_ANA_SSC_CLK_CNTRL_val = 0x007d; |
| U16 SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_TX_OVRD_IN_HI_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_TX_OVRD_DRV_LO_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_TX_OVRD_DRV_HI_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_TX_OVRD_OUT_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_OVRD_OUT_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_TX_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_TX_ASIC_DRV_LO_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_TX_ASIC_DRV_HI_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_TX_ASIC_OUT_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_ASIC_OUT_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_TX_DEBUG_val = 0x0100; |
| U16 SSP_CR_LANE0_DIG_TX_CM_WAIT_TIME_OVRD_val = 0x009f; |
| U16 SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_0_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_1_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_TX_LBERT_CTL_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_LBERT_CTL_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_LBERT_ERR_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_SCOPE_CTL_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_SCOPE_PHASE_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_DPLL_FREQ_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_CDR_CTL_val = 0x000f; |
| U16 SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_OVRD_val = 0x8000; |
| U16 SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_val = 0x0000; |
| U16 SSP_CR_LANE0_DIG_RX_CDR_ADAP_FSM_val = 0x0000; |
| U16 SSP_CR_LANE0_ANA_RX_ATB0_val = 0x0000; |
| U16 SSP_CR_LANE0_ANA_RX_ATB1_val = 0x0000; |
| U16 SSP_CR_LANE0_ANA_RX_ENPWR0_val = 0x0000; |
| U16 SSP_CR_LANE0_ANA_RX_PMIX_PHASE_val = 0x0000; |
| U16 SSP_CR_LANE0_ANA_RX_ENPWR1_val = 0x0000; |
| U16 SSP_CR_LANE0_ANA_RX_ENPWR2_val = 0x0000; |
| U16 SSP_CR_LANE0_ANA_RX_SCOPE_val = 0x0000; |
| U16 SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL_val = 0x0000; |
| U16 SSP_CR_LANE0_ANA_TX_POWER_CTL_val = 0x0000; |
| U16 SSP_CR_LANE0_ANA_TX_ALT_BLOCK_val = 0x0000; |
| U16 SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK_val = 0x0000; |
| U16 SSP_CR_LANE0_ANA_TX_TX_ATB_REG_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_OVRD_IN_HI_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_OVRD_DRV_LO_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_OVRD_DRV_HI_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_OVRD_OUT_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_OVRD_OUT_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_ASIC_DRV_LO_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_ASIC_DRV_HI_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_ASIC_OUT_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_ASIC_OUT_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_DEBUG_val = 0x0100; |
| U16 SSP_CR_LANE1_DIG_TX_CM_WAIT_TIME_OVRD_val = 0x009f; |
| U16 SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_0_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_1_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_TX_LBERT_CTL_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_LBERT_CTL_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_LBERT_ERR_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_SCOPE_CTL_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_SCOPE_PHASE_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_DPLL_FREQ_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_CDR_CTL_val = 0x000f; |
| U16 SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_OVRD_val = 0x8000; |
| U16 SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_val = 0x0000; |
| U16 SSP_CR_LANE1_DIG_RX_CDR_ADAP_FSM_val = 0x0000; |
| U16 SSP_CR_LANE1_ANA_RX_ATB0_val = 0x0000; |
| U16 SSP_CR_LANE1_ANA_RX_ATB1_val = 0x0000; |
| U16 SSP_CR_LANE1_ANA_RX_ENPWR0_val = 0x0000; |
| U16 SSP_CR_LANE1_ANA_RX_PMIX_PHASE_val = 0x0000; |
| U16 SSP_CR_LANE1_ANA_RX_ENPWR1_val = 0x0000; |
| U16 SSP_CR_LANE1_ANA_RX_ENPWR2_val = 0x0000; |
| U16 SSP_CR_LANE1_ANA_RX_SCOPE_val = 0x0000; |
| U16 SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL_val = 0x0000; |
| U16 SSP_CR_LANE1_ANA_TX_POWER_CTL_val = 0x0000; |
| U16 SSP_CR_LANE1_ANA_TX_ALT_BLOCK_val = 0x0000; |
| U16 SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK_val = 0x0000; |
| U16 SSP_CR_LANE1_ANA_TX_TX_ATB_REG_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_OVRD_IN_HI_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_OVRD_DRV_LO_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_OVRD_DRV_HI_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_OVRD_OUT_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_OVRD_OUT_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_ASIC_DRV_LO_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_ASIC_DRV_HI_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_ASIC_OUT_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_ASIC_OUT_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_DEBUG_val = 0x0100; |
| U16 SSP_CR_LANE2_DIG_TX_CM_WAIT_TIME_OVRD_val = 0x009f; |
| U16 SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_0_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_1_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_TX_LBERT_CTL_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_LBERT_CTL_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_LBERT_ERR_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_SCOPE_CTL_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_SCOPE_PHASE_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_DPLL_FREQ_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_CDR_CTL_val = 0x000f; |
| U16 SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_OVRD_val = 0x8000; |
| U16 SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_val = 0x0000; |
| U16 SSP_CR_LANE2_DIG_RX_CDR_ADAP_FSM_val = 0x0000; |
| U16 SSP_CR_LANE2_ANA_RX_ATB0_val = 0x0000; |
| U16 SSP_CR_LANE2_ANA_RX_ATB1_val = 0x0000; |
| U16 SSP_CR_LANE2_ANA_RX_ENPWR0_val = 0x0000; |
| U16 SSP_CR_LANE2_ANA_RX_PMIX_PHASE_val = 0x0000; |
| U16 SSP_CR_LANE2_ANA_RX_ENPWR1_val = 0x0000; |
| U16 SSP_CR_LANE2_ANA_RX_ENPWR2_val = 0x0000; |
| U16 SSP_CR_LANE2_ANA_RX_SCOPE_val = 0x0000; |
| U16 SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL_val = 0x0000; |
| U16 SSP_CR_LANE2_ANA_TX_POWER_CTL_val = 0x0000; |
| U16 SSP_CR_LANE2_ANA_TX_ALT_BLOCK_val = 0x0000; |
| U16 SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK_val = 0x0000; |
| U16 SSP_CR_LANE2_ANA_TX_TX_ATB_REG_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_OVRD_IN_HI_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_OVRD_DRV_LO_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_OVRD_DRV_HI_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_OVRD_OUT_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_OVRD_OUT_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_ASIC_DRV_LO_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_ASIC_DRV_HI_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_ASIC_OUT_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_ASIC_OUT_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_DEBUG_val = 0x0100; |
| U16 SSP_CR_LANE3_DIG_TX_CM_WAIT_TIME_OVRD_val = 0x009f; |
| U16 SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_0_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_1_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_TX_LBERT_CTL_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_LBERT_CTL_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_LBERT_ERR_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_SCOPE_CTL_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_SCOPE_PHASE_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_DPLL_FREQ_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_CDR_CTL_val = 0x000f; |
| U16 SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_OVRD_val = 0x8000; |
| U16 SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_val = 0x0000; |
| U16 SSP_CR_LANE3_DIG_RX_CDR_ADAP_FSM_val = 0x0000; |
| U16 SSP_CR_LANE3_ANA_RX_ATB0_val = 0x0000; |
| U16 SSP_CR_LANE3_ANA_RX_ATB1_val = 0x0000; |
| U16 SSP_CR_LANE3_ANA_RX_ENPWR0_val = 0x0000; |
| U16 SSP_CR_LANE3_ANA_RX_PMIX_PHASE_val = 0x0000; |
| U16 SSP_CR_LANE3_ANA_RX_ENPWR1_val = 0x0000; |
| U16 SSP_CR_LANE3_ANA_RX_ENPWR2_val = 0x0000; |
| U16 SSP_CR_LANE3_ANA_RX_SCOPE_val = 0x0000; |
| U16 SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL_val = 0x0000; |
| U16 SSP_CR_LANE3_ANA_TX_POWER_CTL_val = 0x0000; |
| U16 SSP_CR_LANE3_ANA_TX_ALT_BLOCK_val = 0x0000; |
| U16 SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK_val = 0x0000; |
| U16 SSP_CR_LANE3_ANA_TX_TX_ATB_REG_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_OVRD_IN_HI_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_OVRD_DRV_LO_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_OVRD_DRV_HI_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_OVRD_OUT_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_OVRD_OUT_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_ASIC_DRV_LO_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_ASIC_DRV_HI_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_ASIC_OUT_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_ASIC_IN_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_ASIC_OUT_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_DEBUG_val = 0x0100; |
| U16 SSP_CR_LANEX_DIG_TX_CM_WAIT_TIME_OVRD_val = 0x009f; |
| U16 SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_0_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_1_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_TX_LBERT_CTL_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_LBERT_CTL_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_LBERT_ERR_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_SCOPE_CTL_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_SCOPE_PHASE_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_DPLL_FREQ_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_CDR_CTL_val = 0x000f; |
| U16 SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_OVRD_val = 0x8000; |
| U16 SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_val = 0x0000; |
| U16 SSP_CR_LANEX_DIG_RX_CDR_ADAP_FSM_val = 0x0000; |
| U16 SSP_CR_LANEX_ANA_RX_ATB0_val = 0x0000; |
| U16 SSP_CR_LANEX_ANA_RX_ATB1_val = 0x0000; |
| U16 SSP_CR_LANEX_ANA_RX_ENPWR0_val = 0x0000; |
| U16 SSP_CR_LANEX_ANA_RX_PMIX_PHASE_val = 0x0000; |
| U16 SSP_CR_LANEX_ANA_RX_ENPWR1_val = 0x0000; |
| U16 SSP_CR_LANEX_ANA_RX_ENPWR2_val = 0x0000; |
| U16 SSP_CR_LANEX_ANA_RX_SCOPE_val = 0x0000; |
| U16 SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL_val = 0x0000; |
| U16 SSP_CR_LANEX_ANA_TX_POWER_CTL_val = 0x0000; |
| U16 SSP_CR_LANEX_ANA_TX_ALT_BLOCK_val = 0x0000; |
| U16 SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK_val = 0x0000; |
| U16 SSP_CR_LANEX_ANA_TX_TX_ATB_REG_val = 0x0000; |
| |
| U16 SSP_CR_SUP_DIG_IDCODE_LO = 0x0000; |
| U16 SSP_CR_SUP_DIG_IDCODE_HI = 0x0001; |
| U16 SSP_CR_SUP_DIG_DEBUG = 0x0002; |
| U16 SSP_CR_SUP_DIG_SS_PHASE = 0x0005; |
| U16 SSP_CR_SUP_DIG_SS_FREQ = 0x0006; |
| U16 SSP_CR_SUP_DIG_ATEOVRD = 0x0010; |
| U16 SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO = 0x0011; |
| U16 SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI = 0x0012; |
| U16 SSP_CR_SUP_DIG_SSC_OVRD_IN = 0x0013; |
| U16 SSP_CR_SUP_DIG_BS_OVRD_IN = 0x0014; |
| U16 SSP_CR_SUP_DIG_LEVEL_OVRD_IN = 0x0015; |
| U16 SSP_CR_SUP_DIG_SUP_OVRD_OUT = 0x0016; |
| U16 SSP_CR_SUP_DIG_MPLL_ASIC_IN = 0x0017; |
| U16 SSP_CR_SUP_DIG_BS_ASIC_IN = 0x0018; |
| U16 SSP_CR_SUP_DIG_LEVEL_ASIC_IN = 0x0019; |
| U16 SSP_CR_SUP_DIG_SSC_ASIC_IN = 0x001A; |
| U16 SSP_CR_SUP_DIG_SUP_ASIC_OUT = 0x001B; |
| U16 SSP_CR_SUP_DIG_ATEOVRD_STATUS = 0x001C; |
| U16 SSP_CR_SUP_DIG_RTUNE_DEBUG = 0x0003; |
| U16 SSP_CR_SUP_DIG_RTUNE_STAT = 0x0004; |
| U16 SSP_CR_SUP_DIG_SCOPE_ENABLES = 0x0020; |
| U16 SSP_CR_SUP_DIG_SCOPE_SAMPLES = 0x0021; |
| U16 SSP_CR_SUP_DIG_SCOPE_COUNT = 0x0022; |
| U16 SSP_CR_SUP_DIG_SCOPE_CTL = 0x0023; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_000 = 0x0024; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_001 = 0x0025; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_010 = 0x0026; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_011 = 0x0027; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_100 = 0x0028; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_101 = 0x0029; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_110 = 0x002A; |
| U16 SSP_CR_SUP_DIG_SCOPE_MASK_111 = 0x002B; |
| U16 SSP_CR_SUP_ANA_MPLL_LOOP_CTL = 0x0030; |
| U16 SSP_CR_SUP_ANA_MPLL_ATB_MEAS1 = 0x0031; |
| U16 SSP_CR_SUP_ANA_MPLL_ATB_MEAS2 = 0x0032; |
| U16 SSP_CR_SUP_ANA_MPLL_OVRD = 0x0033; |
| U16 SSP_CR_SUP_ANA_RTUNE_RTUNE_CTRL = 0x0034; |
| U16 SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL = 0x0035; |
| U16 SSP_CR_SUP_ANA_SSC_CLK_CNTRL = 0x0036; |
| U16 SSP_CR_LANE0_DIG_TX_OVRD_IN_LO = 0x1000; |
| U16 SSP_CR_LANE0_DIG_TX_OVRD_IN_HI = 0x1001; |
| U16 SSP_CR_LANE0_DIG_TX_OVRD_DRV_LO = 0x1002; |
| U16 SSP_CR_LANE0_DIG_TX_OVRD_DRV_HI = 0x1003; |
| U16 SSP_CR_LANE0_DIG_TX_OVRD_OUT = 0x1004; |
| U16 SSP_CR_LANE0_DIG_RX_OVRD_IN_LO = 0x1005; |
| U16 SSP_CR_LANE0_DIG_RX_OVRD_IN_HI = 0x1006; |
| U16 SSP_CR_LANE0_DIG_RX_OVRD_OUT = 0x1007; |
| U16 SSP_CR_LANE0_DIG_TX_ASIC_IN = 0x1008; |
| U16 SSP_CR_LANE0_DIG_TX_ASIC_DRV_LO = 0x1009; |
| U16 SSP_CR_LANE0_DIG_TX_ASIC_DRV_HI = 0x100A; |
| U16 SSP_CR_LANE0_DIG_TX_ASIC_OUT = 0x100B; |
| U16 SSP_CR_LANE0_DIG_RX_ASIC_IN = 0x100C; |
| U16 SSP_CR_LANE0_DIG_RX_ASIC_OUT = 0x100D; |
| U16 SSP_CR_LANE0_DIG_TX_DEBUG = 0x1010; |
| U16 SSP_CR_LANE0_DIG_TX_CM_WAIT_TIME_OVRD = 0x1011; |
| U16 SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_0 = 0x1012; |
| U16 SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_1 = 0x1013; |
| U16 SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN = 0x1014; |
| U16 SSP_CR_LANE0_DIG_TX_LBERT_CTL = 0x1015; |
| U16 SSP_CR_LANE0_DIG_RX_LBERT_CTL = 0x1016; |
| U16 SSP_CR_LANE0_DIG_RX_LBERT_ERR = 0x1017; |
| U16 SSP_CR_LANE0_DIG_RX_SCOPE_CTL = 0x1018; |
| U16 SSP_CR_LANE0_DIG_RX_SCOPE_PHASE = 0x1019; |
| U16 SSP_CR_LANE0_DIG_RX_DPLL_FREQ = 0x101A; |
| U16 SSP_CR_LANE0_DIG_RX_CDR_CTL = 0x101B; |
| U16 SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG = 0x101C; |
| U16 SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_OVRD = 0x101D; |
| U16 SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC = 0x101E; |
| U16 SSP_CR_LANE0_DIG_RX_CDR_ADAP_FSM = 0x101F; |
| U16 SSP_CR_LANE0_ANA_RX_ATB0 = 0x1020; |
| U16 SSP_CR_LANE0_ANA_RX_ATB1 = 0x1021; |
| U16 SSP_CR_LANE0_ANA_RX_ENPWR0 = 0x1022; |
| U16 SSP_CR_LANE0_ANA_RX_PMIX_PHASE = 0x1023; |
| U16 SSP_CR_LANE0_ANA_RX_ENPWR1 = 0x1024; |
| U16 SSP_CR_LANE0_ANA_RX_ENPWR2 = 0x1025; |
| U16 SSP_CR_LANE0_ANA_RX_SCOPE = 0x1026; |
| U16 SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL = 0x102B; |
| U16 SSP_CR_LANE0_ANA_TX_POWER_CTL = 0x102C; |
| U16 SSP_CR_LANE0_ANA_TX_ALT_BLOCK = 0x102D; |
| U16 SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK = 0x102E; |
| U16 SSP_CR_LANE0_ANA_TX_TX_ATB_REG = 0x102F; |
| U16 SSP_CR_LANE1_DIG_TX_OVRD_IN_LO = 0x1100; |
| U16 SSP_CR_LANE1_DIG_TX_OVRD_IN_HI = 0x1101; |
| U16 SSP_CR_LANE1_DIG_TX_OVRD_DRV_LO = 0x1102; |
| U16 SSP_CR_LANE1_DIG_TX_OVRD_DRV_HI = 0x1103; |
| U16 SSP_CR_LANE1_DIG_TX_OVRD_OUT = 0x1104; |
| U16 SSP_CR_LANE1_DIG_RX_OVRD_IN_LO = 0x1105; |
| U16 SSP_CR_LANE1_DIG_RX_OVRD_IN_HI = 0x1106; |
| U16 SSP_CR_LANE1_DIG_RX_OVRD_OUT = 0x1107; |
| U16 SSP_CR_LANE1_DIG_TX_ASIC_IN = 0x1108; |
| U16 SSP_CR_LANE1_DIG_TX_ASIC_DRV_LO = 0x1109; |
| U16 SSP_CR_LANE1_DIG_TX_ASIC_DRV_HI = 0x110A; |
| U16 SSP_CR_LANE1_DIG_TX_ASIC_OUT = 0x110B; |
| U16 SSP_CR_LANE1_DIG_RX_ASIC_IN = 0x110C; |
| U16 SSP_CR_LANE1_DIG_RX_ASIC_OUT = 0x110D; |
| U16 SSP_CR_LANE1_DIG_TX_DEBUG = 0x1110; |
| U16 SSP_CR_LANE1_DIG_TX_CM_WAIT_TIME_OVRD = 0x1111; |
| U16 SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_0 = 0x1112; |
| U16 SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_1 = 0x1113; |
| U16 SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN = 0x1114; |
| U16 SSP_CR_LANE1_DIG_TX_LBERT_CTL = 0x1115; |
| U16 SSP_CR_LANE1_DIG_RX_LBERT_CTL = 0x1116; |
| U16 SSP_CR_LANE1_DIG_RX_LBERT_ERR = 0x1117; |
| U16 SSP_CR_LANE1_DIG_RX_SCOPE_CTL = 0x1118; |
| U16 SSP_CR_LANE1_DIG_RX_SCOPE_PHASE = 0x1119; |
| U16 SSP_CR_LANE1_DIG_RX_DPLL_FREQ = 0x111A; |
| U16 SSP_CR_LANE1_DIG_RX_CDR_CTL = 0x111B; |
| U16 SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG = 0x111C; |
| U16 SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_OVRD = 0x111D; |
| U16 SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC = 0x111E; |
| U16 SSP_CR_LANE1_DIG_RX_CDR_ADAP_FSM = 0x111F; |
| U16 SSP_CR_LANE1_ANA_RX_ATB0 = 0x1120; |
| U16 SSP_CR_LANE1_ANA_RX_ATB1 = 0x1121; |
| U16 SSP_CR_LANE1_ANA_RX_ENPWR0 = 0x1122; |
| U16 SSP_CR_LANE1_ANA_RX_PMIX_PHASE = 0x1123; |
| U16 SSP_CR_LANE1_ANA_RX_ENPWR1 = 0x1124; |
| U16 SSP_CR_LANE1_ANA_RX_ENPWR2 = 0x1125; |
| U16 SSP_CR_LANE1_ANA_RX_SCOPE = 0x1126; |
| U16 SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL = 0x112B; |
| U16 SSP_CR_LANE1_ANA_TX_POWER_CTL = 0x112C; |
| U16 SSP_CR_LANE1_ANA_TX_ALT_BLOCK = 0x112D; |
| U16 SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK = 0x112E; |
| U16 SSP_CR_LANE1_ANA_TX_TX_ATB_REG = 0x112F; |
| U16 SSP_CR_LANE2_DIG_TX_OVRD_IN_LO = 0x1200; |
| U16 SSP_CR_LANE2_DIG_TX_OVRD_IN_HI = 0x1201; |
| U16 SSP_CR_LANE2_DIG_TX_OVRD_DRV_LO = 0x1202; |
| U16 SSP_CR_LANE2_DIG_TX_OVRD_DRV_HI = 0x1203; |
| U16 SSP_CR_LANE2_DIG_TX_OVRD_OUT = 0x1204; |
| U16 SSP_CR_LANE2_DIG_RX_OVRD_IN_LO = 0x1205; |
| U16 SSP_CR_LANE2_DIG_RX_OVRD_IN_HI = 0x1206; |
| U16 SSP_CR_LANE2_DIG_RX_OVRD_OUT = 0x1207; |
| U16 SSP_CR_LANE2_DIG_TX_ASIC_IN = 0x1208; |
| U16 SSP_CR_LANE2_DIG_TX_ASIC_DRV_LO = 0x1209; |
| U16 SSP_CR_LANE2_DIG_TX_ASIC_DRV_HI = 0x120A; |
| U16 SSP_CR_LANE2_DIG_TX_ASIC_OUT = 0x120B; |
| U16 SSP_CR_LANE2_DIG_RX_ASIC_IN = 0x120C; |
| U16 SSP_CR_LANE2_DIG_RX_ASIC_OUT = 0x120D; |
| U16 SSP_CR_LANE2_DIG_TX_DEBUG = 0x1210; |
| U16 SSP_CR_LANE2_DIG_TX_CM_WAIT_TIME_OVRD = 0x1211; |
| U16 SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_0 = 0x1212; |
| U16 SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_1 = 0x1213; |
| U16 SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN = 0x1214; |
| U16 SSP_CR_LANE2_DIG_TX_LBERT_CTL = 0x1215; |
| U16 SSP_CR_LANE2_DIG_RX_LBERT_CTL = 0x1216; |
| U16 SSP_CR_LANE2_DIG_RX_LBERT_ERR = 0x1217; |
| U16 SSP_CR_LANE2_DIG_RX_SCOPE_CTL = 0x1218; |
| U16 SSP_CR_LANE2_DIG_RX_SCOPE_PHASE = 0x1219; |
| U16 SSP_CR_LANE2_DIG_RX_DPLL_FREQ = 0x121A; |
| U16 SSP_CR_LANE2_DIG_RX_CDR_CTL = 0x121B; |
| U16 SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG = 0x121C; |
| U16 SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_OVRD = 0x121D; |
| U16 SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC = 0x121E; |
| U16 SSP_CR_LANE2_DIG_RX_CDR_ADAP_FSM = 0x121F; |
| U16 SSP_CR_LANE2_ANA_RX_ATB0 = 0x1220; |
| U16 SSP_CR_LANE2_ANA_RX_ATB1 = 0x1221; |
| U16 SSP_CR_LANE2_ANA_RX_ENPWR0 = 0x1222; |
| U16 SSP_CR_LANE2_ANA_RX_PMIX_PHASE = 0x1223; |
| U16 SSP_CR_LANE2_ANA_RX_ENPWR1 = 0x1224; |
| U16 SSP_CR_LANE2_ANA_RX_ENPWR2 = 0x1225; |
| U16 SSP_CR_LANE2_ANA_RX_SCOPE = 0x1226; |
| U16 SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL = 0x122B; |
| U16 SSP_CR_LANE2_ANA_TX_POWER_CTL = 0x122C; |
| U16 SSP_CR_LANE2_ANA_TX_ALT_BLOCK = 0x122D; |
| U16 SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK = 0x122E; |
| U16 SSP_CR_LANE2_ANA_TX_TX_ATB_REG = 0x122F; |
| U16 SSP_CR_LANE3_DIG_TX_OVRD_IN_LO = 0x1300; |
| U16 SSP_CR_LANE3_DIG_TX_OVRD_IN_HI = 0x1301; |
| U16 SSP_CR_LANE3_DIG_TX_OVRD_DRV_LO = 0x1302; |
| U16 SSP_CR_LANE3_DIG_TX_OVRD_DRV_HI = 0x1303; |
| U16 SSP_CR_LANE3_DIG_TX_OVRD_OUT = 0x1304; |
| U16 SSP_CR_LANE3_DIG_RX_OVRD_IN_LO = 0x1305; |
| U16 SSP_CR_LANE3_DIG_RX_OVRD_IN_HI = 0x1306; |
| U16 SSP_CR_LANE3_DIG_RX_OVRD_OUT = 0x1307; |
| U16 SSP_CR_LANE3_DIG_TX_ASIC_IN = 0x1308; |
| U16 SSP_CR_LANE3_DIG_TX_ASIC_DRV_LO = 0x1309; |
| U16 SSP_CR_LANE3_DIG_TX_ASIC_DRV_HI = 0x130A; |
| U16 SSP_CR_LANE3_DIG_TX_ASIC_OUT = 0x130B; |
| U16 SSP_CR_LANE3_DIG_RX_ASIC_IN = 0x130C; |
| U16 SSP_CR_LANE3_DIG_RX_ASIC_OUT = 0x130D; |
| U16 SSP_CR_LANE3_DIG_TX_DEBUG = 0x1310; |
| U16 SSP_CR_LANE3_DIG_TX_CM_WAIT_TIME_OVRD = 0x1311; |
| U16 SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_0 = 0x1312; |
| U16 SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_1 = 0x1313; |
| U16 SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN = 0x1314; |
| U16 SSP_CR_LANE3_DIG_TX_LBERT_CTL = 0x1315; |
| U16 SSP_CR_LANE3_DIG_RX_LBERT_CTL = 0x1316; |
| U16 SSP_CR_LANE3_DIG_RX_LBERT_ERR = 0x1317; |
| U16 SSP_CR_LANE3_DIG_RX_SCOPE_CTL = 0x1318; |
| U16 SSP_CR_LANE3_DIG_RX_SCOPE_PHASE = 0x1319; |
| U16 SSP_CR_LANE3_DIG_RX_DPLL_FREQ = 0x131A; |
| U16 SSP_CR_LANE3_DIG_RX_CDR_CTL = 0x131B; |
| U16 SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG = 0x131C; |
| U16 SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_OVRD = 0x131D; |
| U16 SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC = 0x131E; |
| U16 SSP_CR_LANE3_DIG_RX_CDR_ADAP_FSM = 0x131F; |
| U16 SSP_CR_LANE3_ANA_RX_ATB0 = 0x1320; |
| U16 SSP_CR_LANE3_ANA_RX_ATB1 = 0x1321; |
| U16 SSP_CR_LANE3_ANA_RX_ENPWR0 = 0x1322; |
| U16 SSP_CR_LANE3_ANA_RX_PMIX_PHASE = 0x1323; |
| U16 SSP_CR_LANE3_ANA_RX_ENPWR1 = 0x1324; |
| U16 SSP_CR_LANE3_ANA_RX_ENPWR2 = 0x1325; |
| U16 SSP_CR_LANE3_ANA_RX_SCOPE = 0x1326; |
| U16 SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL = 0x132B; |
| U16 SSP_CR_LANE3_ANA_TX_POWER_CTL = 0x132C; |
| U16 SSP_CR_LANE3_ANA_TX_ALT_BLOCK = 0x132D; |
| U16 SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK = 0x132E; |
| U16 SSP_CR_LANE3_ANA_TX_TX_ATB_REG = 0x132F; |
| U16 SSP_CR_LANEX_DIG_TX_OVRD_IN_LO = 0x9000; |
| U16 SSP_CR_LANEX_DIG_TX_OVRD_IN_HI = 0x9001; |
| U16 SSP_CR_LANEX_DIG_TX_OVRD_DRV_LO = 0x9002; |
| U16 SSP_CR_LANEX_DIG_TX_OVRD_DRV_HI = 0x9003; |
| U16 SSP_CR_LANEX_DIG_TX_OVRD_OUT = 0x9004; |
| U16 SSP_CR_LANEX_DIG_RX_OVRD_IN_LO = 0x9005; |
| U16 SSP_CR_LANEX_DIG_RX_OVRD_IN_HI = 0x9006; |
| U16 SSP_CR_LANEX_DIG_RX_OVRD_OUT = 0x9007; |
| U16 SSP_CR_LANEX_DIG_TX_ASIC_IN = 0x9008; |
| U16 SSP_CR_LANEX_DIG_TX_ASIC_DRV_LO = 0x9009; |
| U16 SSP_CR_LANEX_DIG_TX_ASIC_DRV_HI = 0x900A; |
| U16 SSP_CR_LANEX_DIG_TX_ASIC_OUT = 0x900B; |
| U16 SSP_CR_LANEX_DIG_RX_ASIC_IN = 0x900C; |
| U16 SSP_CR_LANEX_DIG_RX_ASIC_OUT = 0x900D; |
| U16 SSP_CR_LANEX_DIG_TX_DEBUG = 0x9010; |
| U16 SSP_CR_LANEX_DIG_TX_CM_WAIT_TIME_OVRD = 0x9011; |
| U16 SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_0 = 0x9012; |
| U16 SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_1 = 0x9013; |
| U16 SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN = 0x9014; |
| U16 SSP_CR_LANEX_DIG_TX_LBERT_CTL = 0x9015; |
| U16 SSP_CR_LANEX_DIG_RX_LBERT_CTL = 0x9016; |
| U16 SSP_CR_LANEX_DIG_RX_LBERT_ERR = 0x9017; |
| U16 SSP_CR_LANEX_DIG_RX_SCOPE_CTL = 0x9018; |
| U16 SSP_CR_LANEX_DIG_RX_SCOPE_PHASE = 0x9019; |
| U16 SSP_CR_LANEX_DIG_RX_DPLL_FREQ = 0x901A; |
| U16 SSP_CR_LANEX_DIG_RX_CDR_CTL = 0x901B; |
| U16 SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG = 0x901C; |
| U16 SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_OVRD = 0x901D; |
| U16 SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC = 0x901E; |
| U16 SSP_CR_LANEX_DIG_RX_CDR_ADAP_FSM = 0x901F; |
| U16 SSP_CR_LANEX_ANA_RX_ATB0 = 0x9020; |
| U16 SSP_CR_LANEX_ANA_RX_ATB1 = 0x9021; |
| U16 SSP_CR_LANEX_ANA_RX_ENPWR0 = 0x9022; |
| U16 SSP_CR_LANEX_ANA_RX_PMIX_PHASE = 0x9023; |
| U16 SSP_CR_LANEX_ANA_RX_ENPWR1 = 0x9024; |
| U16 SSP_CR_LANEX_ANA_RX_ENPWR2 = 0x9025; |
| U16 SSP_CR_LANEX_ANA_RX_SCOPE = 0x9026; |
| U16 SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL = 0x902B; |
| U16 SSP_CR_LANEX_ANA_TX_POWER_CTL = 0x902C; |
| U16 SSP_CR_LANEX_ANA_TX_ALT_BLOCK = 0x902D; |
| U16 SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK = 0x902E; |
| U16 SSP_CR_LANEX_ANA_TX_TX_ATB_REG = 0x902F; |
| U16 HSP0_RO_ADDR0 = 0x2000; |
| U16 HSP0_RO_ADDR1 = 0x2001; |
| U16 HSP0_RO_ADDR2 = 0x2002; |
| U16 HSP0_RO_ADDR3 = 0x2003; |
| U16 HSP0_RO_ADDR4 = 0x2004; |
| U16 HSP0_RO_ADDR5 = 0x2005; |
| U16 HSP0_RO_ADDR6 = 0x2005; |
| U16 HSP0_RO_ADDR7 = 0x2007; |
| U16 HSP0_RO_ADDR8 = 0x2008; |
| U16 HSP0_RO_ADDR9 = 0x2009; |
| U16 HSP0_RO_ADDR10 = 0x200A; |
| U16 HSP0_RO_ADDR11 = 0x200B; |
| U16 HSP0_RO_ADDR12 = 0x200C; |
| U16 HSP0_RO_ADDR13 = 0x200D; |
| U16 HSP0_RO_ADDR14 = 0x200E; |
| U16 HSP0_RO_ADDR15 = 0x200F; |
| U16 HSP0_RW_ADDR0 = 0x2010; |
| U16 HSP0_RW_ADDR1 = 0x2011; |
| U16 HSP0_RW_ADDR2 = 0x2012; |
| U16 HSP0_RW_ADDR3 = 0x2013; |
| U16 HSP0_RW_ADDR4 = 0x2014; |
| U16 HSP0_RW_ADDR5 = 0x2015; |
| U16 HSP0_RW_ADDR6 = 0x2016; |
| U16 HSP0_RW_ADDR7 = 0x2017; |
| U16 HSP0_RW_ADDR8 = 0x2018; |
| U16 HSP0_RW_ADDR9 = 0x2019; |
| U16 HSP0_RW_ADDR10 = 0x201A; |
| U16 HSP0_RW_ADDR11 = 0x201B; |
| U16 HSP0_RW_ADDR12 = 0x201C; |
| U16 HSP0_RW_ADDR13 = 0x201D; |
| U16 HSP0_RW_ADDR14 = 0x201E; |
| U16 HSP0_RW_ADDR15 = 0x201F; |
| U16 HSP1_RO_ADDR0 = 0x2100; |
| U16 HSP1_RO_ADDR1 = 0x2101; |
| U16 HSP1_RO_ADDR2 = 0x2102; |
| U16 HSP1_RO_ADDR3 = 0x2103; |
| U16 HSP1_RO_ADDR4 = 0x2104; |
| U16 HSP1_RO_ADDR5 = 0x2105; |
| U16 HSP1_RO_ADDR6 = 0x2105; |
| U16 HSP1_RO_ADDR7 = 0x2107; |
| U16 HSP1_RO_ADDR8 = 0x2108; |
| U16 HSP1_RO_ADDR9 = 0x2109; |
| U16 HSP1_RO_ADDR10 = 0x210A; |
| U16 HSP1_RO_ADDR11 = 0x210B; |
| U16 HSP1_RO_ADDR12 = 0x210C; |
| U16 HSP1_RO_ADDR13 = 0x210D; |
| U16 HSP1_RO_ADDR14 = 0x210E; |
| U16 HSP1_RO_ADDR15 = 0x210F; |
| U16 HSP1_RW_ADDR0 = 0x2110; |
| U16 HSP1_RW_ADDR1 = 0x2111; |
| U16 HSP1_RW_ADDR2 = 0x2112; |
| U16 HSP1_RW_ADDR3 = 0x2113; |
| U16 HSP1_RW_ADDR4 = 0x2114; |
| U16 HSP1_RW_ADDR5 = 0x2115; |
| U16 HSP1_RW_ADDR6 = 0x2116; |
| U16 HSP1_RW_ADDR7 = 0x2117; |
| U16 HSP1_RW_ADDR8 = 0x2118; |
| U16 HSP1_RW_ADDR9 = 0x2119; |
| U16 HSP1_RW_ADDR10 = 0x211A; |
| U16 HSP1_RW_ADDR11 = 0x211B; |
| U16 HSP1_RW_ADDR12 = 0x211C; |
| U16 HSP1_RW_ADDR13 = 0x211D; |
| U16 HSP1_RW_ADDR14 = 0x211E; |
| U16 HSP1_RW_ADDR15 = 0x211F; |
| U16 HSP2_RO_ADDR0 = 0x2200; |
| U16 HSP2_RO_ADDR1 = 0x2201; |
| U16 HSP2_RO_ADDR2 = 0x2202; |
| U16 HSP2_RO_ADDR3 = 0x2203; |
| U16 HSP2_RO_ADDR4 = 0x2204; |
| U16 HSP2_RO_ADDR5 = 0x2205; |
| U16 HSP2_RO_ADDR6 = 0x2205; |
| U16 HSP2_RO_ADDR7 = 0x2207; |
| U16 HSP2_RO_ADDR8 = 0x2208; |
| U16 HSP2_RO_ADDR9 = 0x2209; |
| U16 HSP2_RO_ADDR10 = 0x220A; |
| U16 HSP2_RO_ADDR11 = 0x220B; |
| U16 HSP2_RO_ADDR12 = 0x220C; |
| U16 HSP2_RO_ADDR13 = 0x220D; |
| U16 HSP2_RO_ADDR14 = 0x220E; |
| U16 HSP2_RO_ADDR15 = 0x220F; |
| U16 HSP2_RW_ADDR0 = 0x2210; |
| U16 HSP2_RW_ADDR1 = 0x2211; |
| U16 HSP2_RW_ADDR2 = 0x2212; |
| U16 HSP2_RW_ADDR3 = 0x2213; |
| U16 HSP2_RW_ADDR4 = 0x2214; |
| U16 HSP2_RW_ADDR5 = 0x2215; |
| U16 HSP2_RW_ADDR6 = 0x2216; |
| U16 HSP2_RW_ADDR7 = 0x2217; |
| U16 HSP2_RW_ADDR8 = 0x2218; |
| U16 HSP2_RW_ADDR9 = 0x2219; |
| U16 HSP2_RW_ADDR10 = 0x221A; |
| U16 HSP2_RW_ADDR11 = 0x221B; |
| U16 HSP2_RW_ADDR12 = 0x221C; |
| U16 HSP2_RW_ADDR13 = 0x221D; |
| U16 HSP2_RW_ADDR14 = 0x221E; |
| U16 HSP2_RW_ADDR15 = 0x221F; |
| U16 HSP3_RO_ADDR0 = 0x2300; |
| U16 HSP3_RO_ADDR1 = 0x2301; |
| U16 HSP3_RO_ADDR2 = 0x2302; |
| U16 HSP3_RO_ADDR3 = 0x2303; |
| U16 HSP3_RO_ADDR4 = 0x2304; |
| U16 HSP3_RO_ADDR5 = 0x2305; |
| U16 HSP3_RO_ADDR6 = 0x2305; |
| U16 HSP3_RO_ADDR7 = 0x2307; |
| U16 HSP3_RO_ADDR8 = 0x2308; |
| U16 HSP3_RO_ADDR9 = 0x2309; |
| U16 HSP3_RO_ADDR10 = 0x230A; |
| U16 HSP3_RO_ADDR11 = 0x230B; |
| U16 HSP3_RO_ADDR12 = 0x230C; |
| U16 HSP3_RO_ADDR13 = 0x230D; |
| U16 HSP3_RO_ADDR14 = 0x230E; |
| U16 HSP3_RO_ADDR15 = 0x230F; |
| U16 HSP3_RW_ADDR0 = 0x2310; |
| U16 HSP3_RW_ADDR1 = 0x2311; |
| U16 HSP3_RW_ADDR2 = 0x2312; |
| U16 HSP3_RW_ADDR3 = 0x2313; |
| U16 HSP3_RW_ADDR4 = 0x2314; |
| U16 HSP3_RW_ADDR5 = 0x2315; |
| U16 HSP3_RW_ADDR6 = 0x2316; |
| U16 HSP3_RW_ADDR7 = 0x2317; |
| U16 HSP3_RW_ADDR8 = 0x2318; |
| U16 HSP3_RW_ADDR9 = 0x2319; |
| U16 HSP3_RW_ADDR10 = 0x231A; |
| U16 HSP3_RW_ADDR11 = 0x231B; |
| U16 HSP3_RW_ADDR12 = 0x231C; |
| U16 HSP3_RW_ADDR13 = 0x231D; |
| U16 HSP3_RW_ADDR14 = 0x231E; |
| U16 HSP3_RW_ADDR15 = 0x231F; |
| U16 HSPX_RW_ADDR0 = 0xA110; |
| U16 HSPX_RW_ADDR1 = 0xA111; |
| U16 HSPX_RW_ADDR2 = 0xA112; |
| U16 HSPX_RW_ADDR3 = 0xA113; |
| U16 HSPX_RW_ADDR4 = 0xA114; |
| U16 HSPX_RW_ADDR5 = 0xA115; |
| U16 HSPX_RW_ADDR6 = 0xA116; |
| U16 HSPX_RW_ADDR7 = 0xA117; |
| U16 HSPX_RW_ADDR8 = 0xA118; |
| U16 HSPX_RW_ADDR9 = 0xA119; |
| U16 HSPX_RW_ADDR10 = 0xA11A; |
| U16 HSPX_RW_ADDR11 = 0xA11B; |
| U16 HSPX_RW_ADDR12 = 0xA11C; |
| U16 HSPX_RW_ADDR13 = 0xA11D; |
| U16 HSPX_RW_ADDR14 = 0xA11E; |
| U16 HSPX_RW_ADDR15 = 0xA11F; |
| |
| //$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$// |
| /*#define SSP_CR_SUP_DIG_IDCODE_LO 0x0000 |
| #define SSP_CR_SUP_DIG_IDCODE_LO_rst 0b0000010011001101 |
| #define SSP_CR_SUP_DIG_IDCODE_LO_size 16 |
| #define SSP_CR_SUP_DIG_IDCODE_LO_IDCODE_LO [15:0] |
| |
| #define SSP_CR_SUP_DIG_IDCODE_HI 0x0001 |
| #define SSP_CR_SUP_DIG_IDCODE_HI_rst 0b0011000000000110 |
| #define SSP_CR_SUP_DIG_IDCODE_HI_size 16 |
| #define SSP_CR_SUP_DIG_IDCODE_HI_IDCODE_HI [15:0] |
| |
| #define SSP_CR_SUP_DIG_DEBUG 0x0002 |
| #define SSP_CR_SUP_DIG_DEBUG_rst 7'b0001010 |
| #define SSP_CR_SUP_DIG_DEBUG_size 7 |
| #define SSP_CR_SUP_DIG_DEBUG_DTB_SEL [6:5] |
| #define SSP_CR_SUP_DIG_DEBUG_TX_VREF_SEL [4:0] |
| |
| #define SSP_CR_SUP_DIG_SS_PHASE 0x0005 |
| #define SSP_CR_SUP_DIG_SS_PHASE_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_SS_PHASE_size 16 |
| #define SSP_CR_SUP_DIG_SS_PHASE_REF_SEL_DIV [15:13] |
| #define SSP_CR_SUP_DIG_SS_PHASE_PH_SEL [12:12] |
| #define SSP_CR_SUP_DIG_SS_PHASE_ZERO_FREQ [11:11] |
| #define SSP_CR_SUP_DIG_SS_PHASE_VAL [10:2] |
| #define SSP_CR_SUP_DIG_SS_PHASE_DTHR [1:0] |
| |
| #define SSP_CR_SUP_DIG_SS_FREQ 0x0006 |
| #define SSP_CR_SUP_DIG_SS_FREQ_rst 15'b011001100100111 |
| #define SSP_CR_SUP_DIG_SS_FREQ_size 15 |
| #define SSP_CR_SUP_DIG_SS_FREQ_FREQ_OVRD [14:14] |
| #define SSP_CR_SUP_DIG_SS_FREQ_FREQ_PK [13:7] |
| #define SSP_CR_SUP_DIG_SS_FREQ_FREQ_CNT_INIT [6:0] |
| |
| #define SSP_CR_SUP_DIG_ATEOVRD 0x0010 |
| #define SSP_CR_SUP_DIG_ATEOVRD_rst 3'b000 |
| #define SSP_CR_SUP_DIG_ATEOVRD_size 3 |
| #define SSP_CR_SUP_DIG_ATEOVRD_ateovrd_en [2:2] |
| #define SSP_CR_SUP_DIG_ATEOVRD_ref_usb2_en [1:1] |
| #define SSP_CR_SUP_DIG_ATEOVRD_ref_clkdiv2 [0:0] |
| |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO 0x0011 |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_rst 0b0000000001001100 |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_size 16 |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_RES_ACK_IN_OVRD [15:15] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_RES_ACK_IN [14:14] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_RES_REQ_IN_OVRD [13:13] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_RES_REQ_IN [12:12] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_RTUNE_REQ_OVRD [11:11] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_RTUNE_REQ [10:10] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_MPLL_MULTIPLIER_OVRD [9:9] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_MPLL_MULTIPLIER [8:2] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_MPLL_EN_OVRD [1:1] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO_MPLL_EN [0:0] |
| |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI 0x0012 |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_size 16 |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_TX_VBOOST_LVL [15:13] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_MPLL_REFSSC_CLK_EN_OVRD [12:12] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_MPLL_REFSSC_CLK_EN [11:11] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_MPLL_RST [10:10] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_FSEL_OVRD [9:9] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_FSEL [8:6] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_MPLL_WORD_CLK_EN_OVRD [5:5] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_MPLL_WORD_CLK_EN [4:4] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_MPLL_DWORD_CLK_EN_OVRD [3:3] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_MPLL_DWORD_CLK_EN [2:2] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_MPLL_QWORD_CLK_EN_OVRD [1:1] |
| #define SSP_CR_SUP_DIG_MPLL_OVRD_IN_HI_MPLL_QWORD_CLK_EN [0:0] |
| |
| #define SSP_CR_SUP_DIG_SSC_OVRD_IN 0x0013 |
| #define SSP_CR_SUP_DIG_SSC_OVRD_IN_rst 14'b00000000000000 |
| #define SSP_CR_SUP_DIG_SSC_OVRD_IN_size 14 |
| #define SSP_CR_SUP_DIG_SSC_OVRD_IN_SSC_OVRD_IN_EN [13:13] |
| #define SSP_CR_SUP_DIG_SSC_OVRD_IN_SSC_EN [12:12] |
| #define SSP_CR_SUP_DIG_SSC_OVRD_IN_SSC_RANGE [11:9] |
| #define SSP_CR_SUP_DIG_SSC_OVRD_IN_SSC_REF_CLK_SEL [8:0] |
| |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN 0x0014 |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_rst 12'b000000000000 |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_size 12 |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_EN [11:11] |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_INVERT [10:10] |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_INIT [9:9] |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_HIGHZ [8:8] |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_CLAMP [7:7] |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_EXTEST_AC [6:6] |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_EXTEST [5:5] |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_PRELOAD [4:4] |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_UPDATE_DR [3:3] |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_CAPTURE_DR [2:2] |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_SHIFT_DR [1:1] |
| #define SSP_CR_SUP_DIG_BS_OVRD_IN_IN [0:0] |
| |
| #define SSP_CR_SUP_DIG_LEVEL_OVRD_IN 0x0015 |
| #define SSP_CR_SUP_DIG_LEVEL_OVRD_IN_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_LEVEL_OVRD_IN_size 16 |
| #define SSP_CR_SUP_DIG_LEVEL_OVRD_IN_LOS_BIAS [15:13] |
| #define SSP_CR_SUP_DIG_LEVEL_OVRD_IN_MPLL_HALF_RATE_OVRD [12:12] |
| #define SSP_CR_SUP_DIG_LEVEL_OVRD_IN_MPLL_HALF_RATE [11:11] |
| #define SSP_CR_SUP_DIG_LEVEL_OVRD_IN_LEVEL_EN [10:10] |
| #define SSP_CR_SUP_DIG_LEVEL_OVRD_IN_ACJT_LEVEL [9:5] |
| #define SSP_CR_SUP_DIG_LEVEL_OVRD_IN_LOS_LEVEL [4:0] |
| |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT 0x0016 |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT_rst 10'b0100000001 |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT_size 10 |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT_MPLL_STATE_OVRD [9:9] |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT_MPLL_STATE [8:8] |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT_BS_OUT_OVRD [7:7] |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT_BS_OUT [6:6] |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT_RTUNE_ACK_OVRD [5:5] |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT_RTUNE_ACK [4:4] |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT_RES_REQ_OUT_OVRD [3:3] |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT_RES_REQ_OUT [2:2] |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT_RES_ACK_OUT_OVRD [1:1] |
| #define SSP_CR_SUP_DIG_SUP_OVRD_OUT_RES_ACK_OUT [0:0] |
| |
| #define SSP_CR_SUP_DIG_MPLL_ASIC_IN 0x0017 |
| #define SSP_CR_SUP_DIG_MPLL_ASIC_IN_rst 15'b000000000000000 |
| #define SSP_CR_SUP_DIG_MPLL_ASIC_IN_size 15 |
| #define SSP_CR_SUP_DIG_MPLL_ASIC_IN_MPLL_REFSSC_CLK_EN [14:14] |
| #define SSP_CR_SUP_DIG_MPLL_ASIC_IN_MPLL_WORD_CLK_EN [13:13] |
| #define SSP_CR_SUP_DIG_MPLL_ASIC_IN_MPLL_DWORD_CLK_EN [12:12] |
| #define SSP_CR_SUP_DIG_MPLL_ASIC_IN_MPLL_QWORD_CLK_EN [11:11] |
| #define SSP_CR_SUP_DIG_MPLL_ASIC_IN_RES_ACK_IN [10:10] |
| #define SSP_CR_SUP_DIG_MPLL_ASIC_IN_RES_REQ_IN [9:9] |
| #define SSP_CR_SUP_DIG_MPLL_ASIC_IN_RTUNE_REQ [8:8] |
| #define SSP_CR_SUP_DIG_MPLL_ASIC_IN_MPLL_MULTIPLIER [7:1] |
| #define SSP_CR_SUP_DIG_MPLL_ASIC_IN_MPLL_EN [0:0] |
| |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN 0x0018 |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_rst 14'b00000000000000 |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_size 14 |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_TX_VBOOST_LVL [13:11] |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_INVERT [10:10] |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_INIT [9:9] |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_HIGHZ [8:8] |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_CLAMP [7:7] |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_EXTEST_AC [6:6] |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_EXTEST [5:5] |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_PRELOAD [4:4] |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_UPDATE_DR [3:3] |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_CAPTURE_DR [2:2] |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_SHIFT_DR [1:1] |
| #define SSP_CR_SUP_DIG_BS_ASIC_IN_IN [0:0] |
| |
| #define SSP_CR_SUP_DIG_LEVEL_ASIC_IN 0x0019 |
| #define SSP_CR_SUP_DIG_LEVEL_ASIC_IN_rst 15'b000000000000000 |
| #define SSP_CR_SUP_DIG_LEVEL_ASIC_IN_size 15 |
| #define SSP_CR_SUP_DIG_LEVEL_ASIC_IN_LOS_BIAS [14:12] |
| #define SSP_CR_SUP_DIG_LEVEL_ASIC_IN_MPLL_HALF_RATE [11:11] |
| #define SSP_CR_SUP_DIG_LEVEL_ASIC_IN_VREG_BYPASS [10:10] |
| #define SSP_CR_SUP_DIG_LEVEL_ASIC_IN_ACJT_LEVEL [9:5] |
| #define SSP_CR_SUP_DIG_LEVEL_ASIC_IN_LOS_LEVEL [4:0] |
| |
| #define SSP_CR_SUP_DIG_SSC_ASIC_IN 0x001A |
| #define SSP_CR_SUP_DIG_SSC_ASIC_IN_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_SSC_ASIC_IN_size 16 |
| #define SSP_CR_SUP_DIG_SSC_ASIC_IN_SS_EN [15:15] |
| #define SSP_CR_SUP_DIG_SSC_ASIC_IN_SSC_RANGE [14:12] |
| #define SSP_CR_SUP_DIG_SSC_ASIC_IN_SSC_REF_CLK_SEL [11:3] |
| #define SSP_CR_SUP_DIG_SSC_ASIC_IN_FSEL [2:0] |
| |
| #define SSP_CR_SUP_DIG_SUP_ASIC_OUT 0x001B |
| #define SSP_CR_SUP_DIG_SUP_ASIC_OUT_rst 5'b00000 |
| #define SSP_CR_SUP_DIG_SUP_ASIC_OUT_size 5 |
| #define SSP_CR_SUP_DIG_SUP_ASIC_OUT_MPLL_STATE [4:4] |
| #define SSP_CR_SUP_DIG_SUP_ASIC_OUT_BS_OUT [3:3] |
| #define SSP_CR_SUP_DIG_SUP_ASIC_OUT_RTUNE_ACK [2:2] |
| #define SSP_CR_SUP_DIG_SUP_ASIC_OUT_RES_REQ_OUT [1:1] |
| #define SSP_CR_SUP_DIG_SUP_ASIC_OUT_RES_ACK_OUT [0:0] |
| |
| #define SSP_CR_SUP_DIG_ATEOVRD_STATUS 0x001C |
| #define SSP_CR_SUP_DIG_ATEOVRD_STATUS_rst 8'b00000000 |
| #define SSP_CR_SUP_DIG_ATEOVRD_STATUS_size 8 |
| #define SSP_CR_SUP_DIG_ATEOVRD_STATUS_REF_SSP_EN [7:7] |
| #define SSP_CR_SUP_DIG_ATEOVRD_STATUS_REF_USE_PAD [6:6] |
| #define SSP_CR_SUP_DIG_ATEOVRD_STATUS_PHY_RESET_IN [5:5] |
| #define SSP_CR_SUP_DIG_ATEOVRD_STATUS_REF_CLKDIV2_IN [4:4] |
| #define SSP_CR_SUP_DIG_ATEOVRD_STATUS_REF_USB2_EN_IN [3:3] |
| #define SSP_CR_SUP_DIG_ATEOVRD_STATUS_ATEOVRD_EN [2:2] |
| #define SSP_CR_SUP_DIG_ATEOVRD_STATUS_REF_CLKDIV2_OUT [1:1] |
| #define SSP_CR_SUP_DIG_ATEOVRD_STATUS_REF_USB2_EN_OUT [0:0] |
| |
| #define SSP_CR_SUP_DIG_RTUNE_DEBUG 0x0003 |
| #define SSP_CR_SUP_DIG_RTUNE_DEBUG_rst 15'b000000000000000 |
| #define SSP_CR_SUP_DIG_RTUNE_DEBUG_size 15 |
| #define SSP_CR_SUP_DIG_RTUNE_DEBUG_VALUE [14:5] |
| #define SSP_CR_SUP_DIG_RTUNE_DEBUG_TYPE [4:3] |
| #define SSP_CR_SUP_DIG_RTUNE_DEBUG_SET_VAL [2:2] |
| #define SSP_CR_SUP_DIG_RTUNE_DEBUG_MAN_TUNE [1:1] |
| #define SSP_CR_SUP_DIG_RTUNE_DEBUG_FLIP_COMP [0:0] |
| |
| #define SSP_CR_SUP_DIG_RTUNE_STAT 0x0004 |
| #define SSP_CR_SUP_DIG_RTUNE_STAT_rst 10'b0000000000 |
| #define SSP_CR_SUP_DIG_RTUNE_STAT_size 10 |
| #define SSP_CR_SUP_DIG_RTUNE_STAT_STAT [9:0] |
| |
| #define SSP_CR_SUP_DIG_SCOPE_ENABLES 0x0020 |
| #define SSP_CR_SUP_DIG_SCOPE_ENABLES_rst 5'b00000 |
| #define SSP_CR_SUP_DIG_SCOPE_ENABLES_size 5 |
| #define SSP_CR_SUP_DIG_SCOPE_ENABLES_LANE_SELECT [4:3] |
| #define SSP_CR_SUP_DIG_SCOPE_ENABLES_MASK_SATURATION_MODE [2:2] |
| #define SSP_CR_SUP_DIG_SCOPE_ENABLES_MASK_EN [1:1] |
| #define SSP_CR_SUP_DIG_SCOPE_ENABLES_XOR_EN [0:0] |
| |
| #define SSP_CR_SUP_DIG_SCOPE_SAMPLES 0x0021 |
| #define SSP_CR_SUP_DIG_SCOPE_SAMPLES_rst 0b0000000100000000 |
| #define SSP_CR_SUP_DIG_SCOPE_SAMPLES_size 16 |
| #define SSP_CR_SUP_DIG_SCOPE_SAMPLES_SAMPLES [15:0] |
| |
| #define SSP_CR_SUP_DIG_SCOPE_COUNT 0x0022 |
| #define SSP_CR_SUP_DIG_SCOPE_COUNT_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_SCOPE_COUNT_size 16 |
| #define SSP_CR_SUP_DIG_SCOPE_COUNT_COUNT [15:0] |
| |
| #define SSP_CR_SUP_DIG_SCOPE_CTL 0x0023 |
| #define SSP_CR_SUP_DIG_SCOPE_CTL_rst 2'b00 |
| #define SSP_CR_SUP_DIG_SCOPE_CTL_size 2 |
| #define SSP_CR_SUP_DIG_SCOPE_CTL_MASK_START [1:1] |
| #define SSP_CR_SUP_DIG_SCOPE_CTL_MASK_SATURATION [0:0] |
| |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_000 0x0024 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_000_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_000_size 16 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_000_MASK_VAL_000 [15:0] |
| |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_001 0x0025 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_001_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_001_size 16 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_001_MASK_VAL_001 [15:0] |
| |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_010 0x0026 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_010_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_010_size 16 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_010_MASK_VAL_010 [15:0] |
| |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_011 0x0027 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_011_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_011_size 16 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_011_MASK_VAL_011 [15:0] |
| |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_100 0x0028 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_100_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_100_size 16 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_100_MASK_VAL_100 [15:0] |
| |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_101 0x0029 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_101_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_101_size 16 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_101_MASK_VAL_101 [15:0] |
| |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_110 0x002A |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_110_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_110_size 16 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_110_MASK_VAL_110 [15:0] |
| |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_111 0x002B |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_111_rst 0b0000000000000000 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_111_size 16 |
| #define SSP_CR_SUP_DIG_SCOPE_MASK_111_MASK_VAL_111 [15:0] |
| |
| #define SSP_CR_SUP_ANA_MPLL_LOOP_CTL 0x0030 |
| #define SSP_CR_SUP_ANA_MPLL_LOOP_CTL_rst 8'b11000000 |
| #define SSP_CR_SUP_ANA_MPLL_LOOP_CTL_size 8 |
| #define SSP_CR_SUP_ANA_MPLL_LOOP_CTL_VMB [0:0] |
| #define SSP_CR_SUP_ANA_MPLL_LOOP_CTL_VBF_SF [1:1] |
| #define SSP_CR_SUP_ANA_MPLL_LOOP_CTL_INT_CNTRL [3:2] |
| #define SSP_CR_SUP_ANA_MPLL_LOOP_CTL_PROP_CNTRL [7:4] |
| |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS1 0x0031 |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS1_rst 8'b00000000 |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS1_size 8 |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS1_VREG_MPLL [0:0] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS1_VP_CP [1:1] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS1_VP [2:2] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS1_IVCO [3:3] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS1_GD [4:4] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS1_VCNTRL [5:5] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS1_VREF [6:6] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS1_VPSF [7:7] |
| |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS2 0x0032 |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS2_rst 8'b00000000 |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS2_size 8 |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS2_EN_MPMIX_TST [0:0] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS2_EN_MPMIX_VPMIX [1:1] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS2_FRC_MPMIX_VPMIX [2:2] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS2_MEAS_TEMP [3:3] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS2_ATB_SENSE_SEL [4:4] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS2_VCNTRL_M [5:5] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS2_VCNTRL_P [6:6] |
| #define SSP_CR_SUP_ANA_MPLL_ATB_MEAS2_IVCO_FILT [7:7] |
| |
| #define SSP_CR_SUP_ANA_MPLL_OVRD 0x0033 |
| #define SSP_CR_SUP_ANA_MPLL_OVRD_rst 8'b00000000 |
| #define SSP_CR_SUP_ANA_MPLL_OVRD_size 8 |
| #define SSP_CR_SUP_ANA_MPLL_OVRD_EN_PMIX_CLK_SEL_LCL [0:0] |
| #define SSP_CR_SUP_ANA_MPLL_OVRD_PMIX_CLK_SEL_LCL [1:1] |
| #define SSP_CR_SUP_ANA_MPLL_OVRD_EN_RST_LCL [2:2] |
| #define SSP_CR_SUP_ANA_MPLL_OVRD_RST_LCL [3:3] |
| #define SSP_CR_SUP_ANA_MPLL_OVRD_EN_GS_LCL [4:4] |
| #define SSP_CR_SUP_ANA_MPLL_OVRD_GS_LCL [5:5] |
| #define SSP_CR_SUP_ANA_MPLL_OVRD_EN_PWRON_LCL [6:6] |
| #define SSP_CR_SUP_ANA_MPLL_OVRD_PWRON_LCL [7:7] |
| |
| #define SSP_CR_SUP_ANA_RTUNE_RTUNE_CTRL 0x0034 |
| #define SSP_CR_SUP_ANA_RTUNE_RTUNE_CTRL_rst 8'b00000000 |
| #define SSP_CR_SUP_ANA_RTUNE_RTUNE_CTRL_size 8 |
| #define SSP_CR_SUP_ANA_RTUNE_RTUNE_CTRL_RT_SEL_ATBF [0:0] |
| #define SSP_CR_SUP_ANA_RTUNE_RTUNE_CTRL_RT_SEL_ATBP [1:1] |
| #define SSP_CR_SUP_ANA_RTUNE_RTUNE_CTRL_RT_ATB [2:2] |
| #define SSP_CR_SUP_ANA_RTUNE_RTUNE_CTRL_RT_DAC_CHOP [3:3] |
| #define SSP_CR_SUP_ANA_RTUNE_RTUNE_CTRL_RT_DAC_MODE [5:4] |
| #define SSP_CR_SUP_ANA_RTUNE_RTUNE_CTRL_X4_FRC_OFF [6:6] |
| #define SSP_CR_SUP_ANA_RTUNE_RTUNE_CTRL_RT_PWRON_FRC_ON [7:7] |
| |
| #define SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL 0x0035 |
| #define SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL_rst 8'b00000000 |
| #define SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL_size 8 |
| #define SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL_ATEST_ASP [0:0] |
| #define SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL_ATEST_ASM [1:1] |
| #define SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL_ATEST_AFP [2:2] |
| #define SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL_ATEST_AFM [3:3] |
| #define SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL_ASP_VPH [4:4] |
| #define SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL_ASP_VHPREG [5:5] |
| #define SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL_ASP_VP [6:6] |
| #define SSP_CR_SUP_ANA_ATB_SWITCHYARD_CTRL_ASM_GD [7:7] |
| |
| #define SSP_CR_SUP_ANA_SSC_CLK_CNTRL 0x0036 |
| #define SSP_CR_SUP_ANA_SSC_CLK_CNTRL_rst 8'b01111101 |
| #define SSP_CR_SUP_ANA_SSC_CLK_CNTRL_size 8 |
| #define SSP_CR_SUP_ANA_SSC_CLK_CNTRL_SSC_CLK_DIV125 [6:0] |
| #define SSP_CR_SUP_ANA_SSC_CLK_CNTRL_NC [7:7] |
| |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO 0x1000 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_size 14 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_DETECT_RX_REQ_OVRD [13:13] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_DETECT_RX_REQ [12:12] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_BEACON_EN_OVRD [11:11] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_BEACON_EN [10:10] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_CM_EN_OVRD [9:9] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_CM_EN [8:8] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_EN_OVRD [7:7] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_EN [6:6] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_DATA_EN_OVRD [5:5] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_DATA_EN [4:4] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_INVERT_OVRD [3:3] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_INVERT [2:2] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_TX_LOOPBK_EN_OVRD [1:1] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_LO_LOOPBK_EN [0:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_HI 0x1001 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_HI_rst 10'b0000000000 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_HI_size 10 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_HI_TX_VBOOST_EN_OVRD [9:9] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_HI_TX_VBOOST_EN [8:8] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_HI_TX_RESET_OVRD [7:7] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_HI_TX_RESET [6:6] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_HI_TX_NYQUIST_DATA [5:5] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_HI_TX_CLK_OUT_EN_OVRD [4:4] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_HI_TX_CLK_OUT_EN [3:3] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_HI_TX_RATE_OVRD [2:2] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_IN_HI_TX_RATE [1:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_OVRD_DRV_LO 0x1002 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_DRV_LO_rst 15'b000000000000000 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_DRV_LO_size 15 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_DRV_LO_EN [14:14] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_DRV_LO_PREEMPH [13:7] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_DRV_LO_AMPLITUDE [6:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_OVRD_DRV_HI 0x1003 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_DRV_HI_rst 6'b000000 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_DRV_HI_size 6 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_DRV_HI_EN [5:5] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_DRV_HI_TERM_OFFSET [4:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_OVRD_OUT 0x1004 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_OUT_rst 8'b00000000 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_OUT_size 8 |
| #define SSP_CR_LANE0_DIG_TX_OVRD_OUT_TX_STATE_OVRD [7:7] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_OUT_TX_STATE [6:6] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_OUT_TX_CM_STATE_OVRD [5:5] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_OUT_TX_CM_STATE [4:4] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_OUT_TX_DETECT_RX_ACK_OVRD [3:3] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_OUT_TX_DETECT_RX_ACK [2:2] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_OUT_DETECT_RX_RES_OVRD [1:1] |
| #define SSP_CR_LANE0_DIG_TX_OVRD_OUT_DETECT_RX_RES [0:0] |
| |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO 0x1005 |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_size 14 |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_LOS_EN_OVRD [13:13] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_LOS_EN [12:12] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_TERM_EN_OVRD [11:11] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_TERM_EN [10:10] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_BIT_SHIFT_OVRD [9:9] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_BIT_SHIFT [8:8] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_ALIGN_EN_OVRD [7:7] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_ALIGN_EN [6:6] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_DATA_EN_OVRD [5:5] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_DATA_EN [4:4] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_PLL_EN_OVRD [3:3] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_PLL_EN [2:2] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_INVERT_OVRD [1:1] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_LO_RX_INVERT [0:0] |
| |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI 0x1006 |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_rst 14'b00000000000000 |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_size 14 |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_RX_RESET_OVRD [13:13] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_RX_RESET [12:12] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_RX_EQ_OVRD [11:11] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_RX_EQ [10:8] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_RX_EQ_EN_OVRD [7:7] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_RX_EQ_EN [6:6] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD [5:5] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_RX_LOS_FILTER [4:3] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_RX_RATE_OVRD [2:2] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_IN_HI_RX_RATE [1:0] |
| |
| #define SSP_CR_LANE0_DIG_RX_OVRD_OUT 0x1007 |
| #define SSP_CR_LANE0_DIG_RX_OVRD_OUT_rst 7'b0000000 |
| #define SSP_CR_LANE0_DIG_RX_OVRD_OUT_size 7 |
| #define SSP_CR_LANE0_DIG_RX_OVRD_OUT_ZERO_DATA [6:6] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_OUT_LOS_OVRD [5:5] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_OUT_LOS [4:4] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_OUT_PLL_STATE_OVRD [3:3] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_OUT_PLL_STATE [2:2] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_OUT_VALID_OVRD [1:1] |
| #define SSP_CR_LANE0_DIG_RX_OVRD_OUT_VALID [0:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN 0x1008 |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_rst 12'b000000000000 |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_size 12 |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_TX_VBOOST_EN [11:11] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_TX_CLK_OUT_EN [10:10] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_DETECT_RX_REQ [9:9] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_BEACON_EN [8:8] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_CM_EN [7:7] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_TX_EN [6:6] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_DATA_EN [5:5] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_TX_RESET [4:4] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_INVERT [3:3] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_LOOPBK_EN [2:2] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_IN_TX_RATE [1:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_ASIC_DRV_LO 0x1009 |
| #define SSP_CR_LANE0_DIG_TX_ASIC_DRV_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANE0_DIG_TX_ASIC_DRV_LO_size 14 |
| #define SSP_CR_LANE0_DIG_TX_ASIC_DRV_LO_PREEMPH [13:7] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_DRV_LO_AMPLITUDE [6:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_ASIC_DRV_HI 0x100A |
| #define SSP_CR_LANE0_DIG_TX_ASIC_DRV_HI_rst 5'b00000 |
| #define SSP_CR_LANE0_DIG_TX_ASIC_DRV_HI_size 5 |
| #define SSP_CR_LANE0_DIG_TX_ASIC_DRV_HI_TERM_OFFSET [4:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_ASIC_OUT 0x100B |
| #define SSP_CR_LANE0_DIG_TX_ASIC_OUT_rst 5'b00000 |
| #define SSP_CR_LANE0_DIG_TX_ASIC_OUT_size 5 |
| #define SSP_CR_LANE0_DIG_TX_ASIC_OUT_STATE [4:4] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_OUT_CM_STATE [3:3] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_OUT_DETECT_RX_ACK [2:2] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_OUT_RESERVED [1:1] |
| #define SSP_CR_LANE0_DIG_TX_ASIC_OUT_DETECT_RX_RES [0:0] |
| |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN 0x100C |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_rst 0b0000000000000000 |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_size 16 |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_RX_EQ_EN [15:15] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_RX_EQ [14:12] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_LOS_FILTER [11:10] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_LOS_EN [9:9] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_TERM_EN [8:8] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_CLK_SHIFT [7:7] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_ALIGN_EN [6:6] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_DATA_EN [5:5] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_PLL_EN [4:4] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_RX_RESET [3:3] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_INVERT [2:2] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_IN_RX_RATE [1:0] |
| |
| #define SSP_CR_LANE0_DIG_RX_ASIC_OUT 0x100D |
| #define SSP_CR_LANE0_DIG_RX_ASIC_OUT_rst 3'b000 |
| #define SSP_CR_LANE0_DIG_RX_ASIC_OUT_size 3 |
| #define SSP_CR_LANE0_DIG_RX_ASIC_OUT_LOS [2:2] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_OUT_PLL_STATE [1:1] |
| #define SSP_CR_LANE0_DIG_RX_ASIC_OUT_VALID [0:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_DEBUG 0x1010 |
| #define SSP_CR_LANE0_DIG_TX_DEBUG_rst 12'b000100000000 |
| #define SSP_CR_LANE0_DIG_TX_DEBUG_size 12 |
| #define SSP_CR_LANE0_DIG_TX_DEBUG_RXDET_MEAS_TIME [11:4] |
| #define SSP_CR_LANE0_DIG_TX_DEBUG_DETECT_RX_ALWAYS [3:3] |
| #define SSP_CR_LANE0_DIG_TX_DEBUG_DTB_SEL [2:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_CM_WAIT_TIME_OVRD 0x1011 |
| #define SSP_CR_LANE0_DIG_TX_CM_WAIT_TIME_OVRD_rst 11'b00010011111 |
| #define SSP_CR_LANE0_DIG_TX_CM_WAIT_TIME_OVRD_size 11 |
| #define SSP_CR_LANE0_DIG_TX_CM_WAIT_TIME_OVRD_CM_TIME_OVRD_EN [10:10] |
| #define SSP_CR_LANE0_DIG_TX_CM_WAIT_TIME_OVRD_CM_TIME_OVRD [9:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_0 0x1012 |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_0_rst 0b0000000000000000 |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_0_size 16 |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_0_SHIFT_OUT [15:15] |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_0_DONE [14:14] |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_0_N_USE [13:7] |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_0_N_TRISTATE [6:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_1 0x1013 |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_1_rst 0b0000000000000000 |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_1_size 16 |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_1_FIXED_DONE [15:15] |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_1_TRA_DONE [14:14] |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_1_N_FIXED [13:7] |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_1_N_TRAILER [6:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN 0x1014 |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_rst 4'b0000 |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_size 4 |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_OVRD [3:3] |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_LOAD [2:2] |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_CLK [1:1] |
| #define SSP_CR_LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_DATA [0:0] |
| |
| #define SSP_CR_LANE0_DIG_TX_LBERT_CTL 0x1015 |
| #define SSP_CR_LANE0_DIG_TX_LBERT_CTL_rst 15'b000000000000000 |
| #define SSP_CR_LANE0_DIG_TX_LBERT_CTL_size 15 |
| #define SSP_CR_LANE0_DIG_TX_LBERT_CTL_MODE [3:0] |
| #define SSP_CR_LANE0_DIG_TX_LBERT_CTL_TRIGGER_ERR [4:4] |
| #define SSP_CR_LANE0_DIG_TX_LBERT_CTL_PAT0 [14:5] |
| |
| #define SSP_CR_LANE0_DIG_RX_LBERT_CTL 0x1016 |
| #define SSP_CR_LANE0_DIG_RX_LBERT_CTL_rst 5'b00000 |
| #define SSP_CR_LANE0_DIG_RX_LBERT_CTL_size 5 |
| #define SSP_CR_LANE0_DIG_RX_LBERT_CTL_MODE [3:0] |
| #define SSP_CR_LANE0_DIG_RX_LBERT_CTL_SYNC [4:4] |
| |
| #define SSP_CR_LANE0_DIG_RX_LBERT_ERR 0x1017 |
| #define SSP_CR_LANE0_DIG_RX_LBERT_ERR_rst 0b0000000000000000 |
| #define SSP_CR_LANE0_DIG_RX_LBERT_ERR_size 16 |
| #define SSP_CR_LANE0_DIG_RX_LBERT_ERR_OV14 [15:15] |
| #define SSP_CR_LANE0_DIG_RX_LBERT_ERR_COUNT [14:0] |
| |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_CTL 0x1018 |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_CTL_rst 14'b00000000000000 |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_CTL_size 14 |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_CTL_RX_VALID_CTL [13:12] |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_CTL_DELAY [11:3] |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_CTL_MODE [2:0] |
| |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_PHASE 0x1019 |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_PHASE_rst 15'b000000000000000 |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_PHASE_size 15 |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_PHASE_BASE [14:10] |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_PHASE_SCOPE_DELAY [9:8] |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_PHASE_SCOPE_SEL [7:7] |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_PHASE_UPDATE [6:6] |
| #define SSP_CR_LANE0_DIG_RX_SCOPE_PHASE_SAMPLE_PHASE [5:0] |
| |
| #define SSP_CR_LANE0_DIG_RX_DPLL_FREQ 0x101A |
| #define SSP_CR_LANE0_DIG_RX_DPLL_FREQ_rst 13'b0000000000000 |
| #define SSP_CR_LANE0_DIG_RX_DPLL_FREQ_size 13 |
| #define SSP_CR_LANE0_DIG_RX_DPLL_FREQ_DTHR [0:0] |
| #define SSP_CR_LANE0_DIG_RX_DPLL_FREQ_VAL [12:1] |
| |
| #define SSP_CR_LANE0_DIG_RX_CDR_CTL 0x101B |
| #define SSP_CR_LANE0_DIG_RX_CDR_CTL_rst 0b0000000000001111 |
| #define SSP_CR_LANE0_DIG_RX_CDR_CTL_size 16 |
| #define SSP_CR_LANE0_DIG_RX_CDR_CTL_PHDET_EN [1:0] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CTL_PHDET_EDGE [3:2] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CTL_PHDET_POL [4:4] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CTL_OVRD_DPLL_GAIN [5:5] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CTL_PHUG_VALUE [7:6] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CTL_FRUG_VALUE [9:8] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CTL_FAST_START [10:10] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CTL_ALWAYS_REALIGN [11:11] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CTL_DTB_SEL [15:12] |
| |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG 0x101C |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_rst 0b0000000000000000 |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_size 16 |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_adap_rx_eq [15:13] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_rx_eq_ctr [12:10] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_rx_ana_eq [9:7] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_adap_rx_valid [6:6] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en_adap [5:5] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en_eq [4:4] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_aligned [3:3] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_rx_valid [2:2] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_timeout [1:1] |
| #define SSP_CR_LANE0_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en [0:0] |
| |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_OVRD 0x101D |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_OVRD_rst 0b1000000000000000 |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_OVRD_size 16 |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_OVRD_adap_ctr_level [15:11] |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_OVRD_adap_polarity [10:10] |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector_ovrd [9:9] |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector_en [8:8] |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector [7:0] |
| |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC 0x101E |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_rst 12'b000000000000 |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_size 12 |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_eq_rx_eq [11:9] |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_eq_locked_vector_en [8:8] |
| #define SSP_CR_LANE0_DIG_RX_CDR_LOCK_VEC_eq_locked_vector [7:0] |
| |
| #define SSP_CR_LANE0_DIG_RX_CDR_ADAP_FSM 0x101F |
| #define SSP_CR_LANE0_DIG_RX_CDR_ADAP_FSM_rst 0b0000000000000000 |
| #define SSP_CR_LANE0_DIG_RX_CDR_ADAP_FSM_size 16 |
| #define SSP_CR_LANE0_DIG_RX_CDR_ADAP_FSM_mstr_ctr [15:11] |
| #define SSP_CR_LANE0_DIG_RX_CDR_ADAP_FSM_loop_ctr [10:7] |
| #define SSP_CR_LANE0_DIG_RX_CDR_ADAP_FSM_adap_ctr [6:3] |
| #define SSP_CR_LANE0_DIG_RX_CDR_ADAP_FSM_adap_state [2:0] |
| |
| #define SSP_CR_LANE0_ANA_RX_ATB0 0x1020 |
| #define SSP_CR_LANE0_ANA_RX_ATB0_rst 8'b00000000 |
| #define SSP_CR_LANE0_ANA_RX_ATB0_size 8 |
| #define SSP_CR_LANE0_ANA_RX_ATB0_EN_ATB_VOFF [0:0] |
| #define SSP_CR_LANE0_ANA_RX_ATB0_EN_ATB_VOS [1:1] |
| #define SSP_CR_LANE0_ANA_RX_ATB0_EN_ATB_RP_S [2:2] |
| #define SSP_CR_LANE0_ANA_RX_ATB0_EN_ATB_RP_F [3:3] |
| #define SSP_CR_LANE0_ANA_RX_ATB0_EN_ATB_RM_S [4:4] |
| #define SSP_CR_LANE0_ANA_RX_ATB0_EN_ATB_RM_F [5:5] |
| #define SSP_CR_LANE0_ANA_RX_ATB0_EN_MARG [6:6] |
| #define SSP_CR_LANE0_ANA_RX_ATB0_EN_ATB [7:7] |
| |
| #define SSP_CR_LANE0_ANA_RX_ATB1 0x1021 |
| #define SSP_CR_LANE0_ANA_RX_ATB1_rst 8'b00000000 |
| #define SSP_CR_LANE0_ANA_RX_ATB1_size 8 |
| #define SSP_CR_LANE0_ANA_RX_ATB1_RX_NC0 [0:0] |
| #define SSP_CR_LANE0_ANA_RX_ATB1_EN_VLOS_USB3 [1:1] |
| #define SSP_CR_LANE0_ANA_RX_ATB1_MEAS_VP [2:2] |
| #define SSP_CR_LANE0_ANA_RX_ATB1_MEAS_GD [3:3] |
| #define SSP_CR_LANE0_ANA_RX_ATB1_EN_ATB_VRF [4:4] |
| #define SSP_CR_LANE0_ANA_RX_ATB1_EN_ATB_VLOS [5:5] |
| #define SSP_CR_LANE0_ANA_RX_ATB1_VLOS_MIN [6:6] |
| #define SSP_CR_LANE0_ANA_RX_ATB1_VLOS_MAX [7:7] |
| |
| #define SSP_CR_LANE0_ANA_RX_ENPWR0 0x1022 |
| #define SSP_CR_LANE0_ANA_RX_ENPWR0_rst 8'b00000000 |
| #define SSP_CR_LANE0_ANA_RX_ENPWR0_size 8 |
| #define SSP_CR_LANE0_ANA_RX_ENPWR0_LCL_ACJT [0:0] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR0_CTL_ACJT [1:1] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR0_LCL_RXCK [2:2] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR0_CTL_RXCK [3:3] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR0_LCL_EN_LOS [4:4] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR0_CTL_EN_LOS [5:5] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR0_LCL_RXPWRON [6:6] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR0_CTL_RXPWRON [7:7] |
| |
| #define SSP_CR_LANE0_ANA_RX_PMIX_PHASE 0x1023 |
| #define SSP_CR_LANE0_ANA_RX_PMIX_PHASE_rst 8'b00000000 |
| #define SSP_CR_LANE0_ANA_RX_PMIX_PHASE_size 8 |
| #define SSP_CR_LANE0_ANA_RX_PMIX_PHASE_PHASE [7:0] |
| |
| #define SSP_CR_LANE0_ANA_RX_ENPWR1 0x1024 |
| #define SSP_CR_LANE0_ANA_RX_ENPWR1_rst 8'b00000000 |
| #define SSP_CR_LANE0_ANA_RX_ENPWR1_size 8 |
| #define SSP_CR_LANE0_ANA_RX_ENPWR1_CTL_PHASE_REG_RST [7:7] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR1_LCL_PHASE_REG_RST [6:6] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR1_CTL_BST [5:5] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR1_LCL_BST [4:2] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR1_CTL_RXTERM [1:1] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR1_LCL_RXTERM [0:0] |
| |
| #define SSP_CR_LANE0_ANA_RX_ENPWR2 0x1025 |
| #define SSP_CR_LANE0_ANA_RX_ENPWR2_rst 8'b00000000 |
| #define SSP_CR_LANE0_ANA_RX_ENPWR2_size 8 |
| #define SSP_CR_LANE0_ANA_RX_ENPWR2_RX_SCOPE_ATB_0 [0:0] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR2_RX_SCOPE_ATB_1 [1:1] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR2_RX_SCOPE_ATB_2 [2:2] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR2_EN_RXPMIX_FRC_VPMIX [3:3] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR2_EN_RXPMIX_VOSC [4:4] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR2_EN_RXPMIX_VRX [5:5] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR2_EN_RXPMIX_VPMIX [6:6] |
| #define SSP_CR_LANE0_ANA_RX_ENPWR2_EN_RXPMIX_TST [7:7] |
| |
| #define SSP_CR_LANE0_ANA_RX_SCOPE 0x1026 |
| #define SSP_CR_LANE0_ANA_RX_SCOPE_rst 8'b00000000 |
| #define SSP_CR_LANE0_ANA_RX_SCOPE_size 8 |
| #define SSP_CR_LANE0_ANA_RX_SCOPE_RX_NC1 [2:0] |
| #define SSP_CR_LANE0_ANA_RX_SCOPE_RX_SCOPE_FDIV20 [3:3] |
| #define SSP_CR_LANE0_ANA_RX_SCOPE_RX_SCOPE_SLEW [4:4] |
| #define SSP_CR_LANE0_ANA_RX_SCOPE_RX_NC2 [7:5] |
| |
| #define SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL 0x102B |
| #define SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL_rst 8'b00000000 |
| #define SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL_size 8 |
| #define SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL_NOCONN_6 [0:0] |
| #define SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL_NOCONN_7 [1:1] |
| #define SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL_NOCONN_8 [2:2] |
| #define SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL_OVRD_VCM_HOLD [3:3] |
| #define SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL_VCM_HOLD_REG [4:4] |
| #define SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL_OVRD_PULL_UP [5:5] |
| #define SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL_PULL_UP_REG [6:6] |
| #define SSP_CR_LANE0_ANA_TX_TXDRV_CNTRL_PULL_DN_REG [7:7] |
| |
| #define SSP_CR_LANE0_ANA_TX_POWER_CTL 0x102C |
| #define SSP_CR_LANE0_ANA_TX_POWER_CTL_rst 8'b00000000 |
| #define SSP_CR_LANE0_ANA_TX_POWER_CTL_size 8 |
| #define SSP_CR_LANE0_ANA_TX_POWER_CTL_LFPS_high_priority [0:0] |
| #define SSP_CR_LANE0_ANA_TX_POWER_CTL_REFGEN_PDN_REG [1:1] |
| #define SSP_CR_LANE0_ANA_TX_POWER_CTL_TX_DIV_CLK_EN [2:2] |
| #define SSP_CR_LANE0_ANA_TX_POWER_CTL_REFGEN_EN_REG [3:3] |
| #define SSP_CR_LANE0_ANA_TX_POWER_CTL_DATA_EN_REG [4:4] |
| #define SSP_CR_LANE0_ANA_TX_POWER_CTL_CLK_EN_REG [5:5] |
| #define SSP_CR_LANE0_ANA_TX_POWER_CTL_SERIAL_EN_REG [6:6] |
| #define SSP_CR_LANE0_ANA_TX_POWER_CTL_OVRD_EN [7:7] |
| |
| #define SSP_CR_LANE0_ANA_TX_ALT_BLOCK 0x102D |
| #define SSP_CR_LANE0_ANA_TX_ALT_BLOCK_rst 8'b00000000 |
| #define SSP_CR_LANE0_ANA_TX_ALT_BLOCK_size 8 |
| #define SSP_CR_LANE0_ANA_TX_ALT_BLOCK_OVRD_ALT_BUS [0:0] |
| #define SSP_CR_LANE0_ANA_TX_ALT_BLOCK_ALT_OSC_VPHREG [1:1] |
| #define SSP_CR_LANE0_ANA_TX_ALT_BLOCK_ALT_OSC_VPH [2:2] |
| #define SSP_CR_LANE0_ANA_TX_ALT_BLOCK_ALT_OSC_VP [3:3] |
| #define SSP_CR_LANE0_ANA_TX_ALT_BLOCK_JTAG_DATA_REG [4:4] |
| #define SSP_CR_LANE0_ANA_TX_ALT_BLOCK_DRV_SOURCE_REG [6:5] |
| #define SSP_CR_LANE0_ANA_TX_ALT_BLOCK_EN_ALT_BUS [7:7] |
| |
| #define SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK 0x102E |
| #define SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK_rst 8'b00000000 |
| #define SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK_size 8 |
| #define SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK_select_pmix_clk [0:0] |
| #define SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK_NOCONN_01 [1:1] |
| #define SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK_ATB_VDCCM [2:2] |
| #define SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK_ATB_VDCCP [3:3] |
| #define SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK_ATB_VREG_TX [4:4] |
| #define SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK_ATB_VPTX [5:5] |
| #define SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK_TX_LB_EN_REG [6:6] |
| #define SSP_CR_LANE0_ANA_TX_ALT_AND_LOOPBACK_OVRD_TX_LB [7:7] |
| |
| #define SSP_CR_LANE0_ANA_TX_TX_ATB_REG 0x102F |
| #define SSP_CR_LANE0_ANA_TX_TX_ATB_REG_rst 8'b00000000 |
| #define SSP_CR_LANE0_ANA_TX_TX_ATB_REG_size 8 |
| #define SSP_CR_LANE0_ANA_TX_TX_ATB_REG_ATB_VCM [0:0] |
| #define SSP_CR_LANE0_ANA_TX_TX_ATB_REG_ATB_TXSM [1:1] |
| #define SSP_CR_LANE0_ANA_TX_TX_ATB_REG_ATB_TXSP [2:2] |
| #define SSP_CR_LANE0_ANA_TX_TX_ATB_REG_ATB_TXFM [3:3] |
| #define SSP_CR_LANE0_ANA_TX_TX_ATB_REG_ATB_TXFP [4:4] |
| #define SSP_CR_LANE0_ANA_TX_TX_ATB_REG_ATB_RXDETREF [5:5] |
| #define SSP_CR_LANE0_ANA_TX_TX_ATB_REG_ATB_VCM_REP [6:6] |
| #define SSP_CR_LANE0_ANA_TX_TX_ATB_REG_ATB_PBIAS [7:7] |
| |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO 0x1100 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_size 14 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_DETECT_RX_REQ_OVRD [13:13] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_DETECT_RX_REQ [12:12] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_BEACON_EN_OVRD [11:11] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_BEACON_EN [10:10] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_CM_EN_OVRD [9:9] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_CM_EN [8:8] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_EN_OVRD [7:7] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_EN [6:6] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_DATA_EN_OVRD [5:5] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_DATA_EN [4:4] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_INVERT_OVRD [3:3] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_INVERT [2:2] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_TX_LOOPBK_EN_OVRD [1:1] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_LO_LOOPBK_EN [0:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_HI 0x1101 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_HI_rst 10'b0000000000 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_HI_size 10 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_HI_TX_VBOOST_EN_OVRD [9:9] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_HI_TX_VBOOST_EN [8:8] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_HI_TX_RESET_OVRD [7:7] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_HI_TX_RESET [6:6] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_HI_TX_NYQUIST_DATA [5:5] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_HI_TX_CLK_OUT_EN_OVRD [4:4] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_HI_TX_CLK_OUT_EN [3:3] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_HI_TX_RATE_OVRD [2:2] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_IN_HI_TX_RATE [1:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_OVRD_DRV_LO 0x1102 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_DRV_LO_rst 15'b000000000000000 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_DRV_LO_size 15 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_DRV_LO_EN [14:14] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_DRV_LO_PREEMPH [13:7] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_DRV_LO_AMPLITUDE [6:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_OVRD_DRV_HI 0x1103 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_DRV_HI_rst 6'b000000 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_DRV_HI_size 6 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_DRV_HI_EN [5:5] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_DRV_HI_TERM_OFFSET [4:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_OVRD_OUT 0x1104 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_OUT_rst 8'b00000000 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_OUT_size 8 |
| #define SSP_CR_LANE1_DIG_TX_OVRD_OUT_TX_STATE_OVRD [7:7] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_OUT_TX_STATE [6:6] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_OUT_TX_CM_STATE_OVRD [5:5] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_OUT_TX_CM_STATE [4:4] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_OUT_TX_DETECT_RX_ACK_OVRD [3:3] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_OUT_TX_DETECT_RX_ACK [2:2] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_OUT_DETECT_RX_RES_OVRD [1:1] |
| #define SSP_CR_LANE1_DIG_TX_OVRD_OUT_DETECT_RX_RES [0:0] |
| |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO 0x1105 |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_size 14 |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_LOS_EN_OVRD [13:13] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_LOS_EN [12:12] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_TERM_EN_OVRD [11:11] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_TERM_EN [10:10] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_BIT_SHIFT_OVRD [9:9] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_BIT_SHIFT [8:8] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_ALIGN_EN_OVRD [7:7] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_ALIGN_EN [6:6] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_DATA_EN_OVRD [5:5] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_DATA_EN [4:4] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_PLL_EN_OVRD [3:3] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_PLL_EN [2:2] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_INVERT_OVRD [1:1] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_LO_RX_INVERT [0:0] |
| |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI 0x1106 |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_rst 14'b00000000000000 |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_size 14 |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_RX_RESET_OVRD [13:13] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_RX_RESET [12:12] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_RX_EQ_OVRD [11:11] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_RX_EQ [10:8] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_RX_EQ_EN_OVRD [7:7] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_RX_EQ_EN [6:6] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD [5:5] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_RX_LOS_FILTER [4:3] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_RX_RATE_OVRD [2:2] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_IN_HI_RX_RATE [1:0] |
| |
| #define SSP_CR_LANE1_DIG_RX_OVRD_OUT 0x1107 |
| #define SSP_CR_LANE1_DIG_RX_OVRD_OUT_rst 7'b0000000 |
| #define SSP_CR_LANE1_DIG_RX_OVRD_OUT_size 7 |
| #define SSP_CR_LANE1_DIG_RX_OVRD_OUT_ZERO_DATA [6:6] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_OUT_LOS_OVRD [5:5] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_OUT_LOS [4:4] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_OUT_PLL_STATE_OVRD [3:3] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_OUT_PLL_STATE [2:2] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_OUT_VALID_OVRD [1:1] |
| #define SSP_CR_LANE1_DIG_RX_OVRD_OUT_VALID [0:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN 0x1108 |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_rst 12'b000000000000 |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_size 12 |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_TX_VBOOST_EN [11:11] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_TX_CLK_OUT_EN [10:10] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_DETECT_RX_REQ [9:9] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_BEACON_EN [8:8] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_CM_EN [7:7] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_TX_EN [6:6] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_DATA_EN [5:5] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_TX_RESET [4:4] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_INVERT [3:3] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_LOOPBK_EN [2:2] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_IN_TX_RATE [1:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_ASIC_DRV_LO 0x1109 |
| #define SSP_CR_LANE1_DIG_TX_ASIC_DRV_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANE1_DIG_TX_ASIC_DRV_LO_size 14 |
| #define SSP_CR_LANE1_DIG_TX_ASIC_DRV_LO_PREEMPH [13:7] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_DRV_LO_AMPLITUDE [6:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_ASIC_DRV_HI 0x110A |
| #define SSP_CR_LANE1_DIG_TX_ASIC_DRV_HI_rst 5'b00000 |
| #define SSP_CR_LANE1_DIG_TX_ASIC_DRV_HI_size 5 |
| #define SSP_CR_LANE1_DIG_TX_ASIC_DRV_HI_TERM_OFFSET [4:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_ASIC_OUT 0x110B |
| #define SSP_CR_LANE1_DIG_TX_ASIC_OUT_rst 5'b00000 |
| #define SSP_CR_LANE1_DIG_TX_ASIC_OUT_size 5 |
| #define SSP_CR_LANE1_DIG_TX_ASIC_OUT_STATE [4:4] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_OUT_CM_STATE [3:3] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_OUT_DETECT_RX_ACK [2:2] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_OUT_RESERVED [1:1] |
| #define SSP_CR_LANE1_DIG_TX_ASIC_OUT_DETECT_RX_RES [0:0] |
| |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN 0x110C |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_rst 0b0000000000000000 |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_size 16 |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_RX_EQ_EN [15:15] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_RX_EQ [14:12] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_LOS_FILTER [11:10] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_LOS_EN [9:9] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_TERM_EN [8:8] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_CLK_SHIFT [7:7] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_ALIGN_EN [6:6] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_DATA_EN [5:5] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_PLL_EN [4:4] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_RX_RESET [3:3] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_INVERT [2:2] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_IN_RX_RATE [1:0] |
| |
| #define SSP_CR_LANE1_DIG_RX_ASIC_OUT 0x110D |
| #define SSP_CR_LANE1_DIG_RX_ASIC_OUT_rst 3'b000 |
| #define SSP_CR_LANE1_DIG_RX_ASIC_OUT_size 3 |
| #define SSP_CR_LANE1_DIG_RX_ASIC_OUT_LOS [2:2] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_OUT_PLL_STATE [1:1] |
| #define SSP_CR_LANE1_DIG_RX_ASIC_OUT_VALID [0:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_DEBUG 0x1110 |
| #define SSP_CR_LANE1_DIG_TX_DEBUG_rst 12'b000100000000 |
| #define SSP_CR_LANE1_DIG_TX_DEBUG_size 12 |
| #define SSP_CR_LANE1_DIG_TX_DEBUG_RXDET_MEAS_TIME [11:4] |
| #define SSP_CR_LANE1_DIG_TX_DEBUG_DETECT_RX_ALWAYS [3:3] |
| #define SSP_CR_LANE1_DIG_TX_DEBUG_DTB_SEL [2:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_CM_WAIT_TIME_OVRD 0x1111 |
| #define SSP_CR_LANE1_DIG_TX_CM_WAIT_TIME_OVRD_rst 11'b00010011111 |
| #define SSP_CR_LANE1_DIG_TX_CM_WAIT_TIME_OVRD_size 11 |
| #define SSP_CR_LANE1_DIG_TX_CM_WAIT_TIME_OVRD_CM_TIME_OVRD_EN [10:10] |
| #define SSP_CR_LANE1_DIG_TX_CM_WAIT_TIME_OVRD_CM_TIME_OVRD [9:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_0 0x1112 |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_0_rst 0b0000000000000000 |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_0_size 16 |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_0_SHIFT_OUT [15:15] |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_0_DONE [14:14] |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_0_N_USE [13:7] |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_0_N_TRISTATE [6:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_1 0x1113 |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_1_rst 0b0000000000000000 |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_1_size 16 |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_1_FIXED_DONE [15:15] |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_1_TRA_DONE [14:14] |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_1_N_FIXED [13:7] |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_1_N_TRAILER [6:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN 0x1114 |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_rst 4'b0000 |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_size 4 |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_OVRD [3:3] |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_LOAD [2:2] |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_CLK [1:1] |
| #define SSP_CR_LANE1_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_DATA [0:0] |
| |
| #define SSP_CR_LANE1_DIG_TX_LBERT_CTL 0x1115 |
| #define SSP_CR_LANE1_DIG_TX_LBERT_CTL_rst 15'b000000000000000 |
| #define SSP_CR_LANE1_DIG_TX_LBERT_CTL_size 15 |
| #define SSP_CR_LANE1_DIG_TX_LBERT_CTL_MODE [3:0] |
| #define SSP_CR_LANE1_DIG_TX_LBERT_CTL_TRIGGER_ERR [4:4] |
| #define SSP_CR_LANE1_DIG_TX_LBERT_CTL_PAT0 [14:5] |
| |
| #define SSP_CR_LANE1_DIG_RX_LBERT_CTL 0x1116 |
| #define SSP_CR_LANE1_DIG_RX_LBERT_CTL_rst 5'b00000 |
| #define SSP_CR_LANE1_DIG_RX_LBERT_CTL_size 5 |
| #define SSP_CR_LANE1_DIG_RX_LBERT_CTL_MODE [3:0] |
| #define SSP_CR_LANE1_DIG_RX_LBERT_CTL_SYNC [4:4] |
| |
| #define SSP_CR_LANE1_DIG_RX_LBERT_ERR 0x1117 |
| #define SSP_CR_LANE1_DIG_RX_LBERT_ERR_rst 0b0000000000000000 |
| #define SSP_CR_LANE1_DIG_RX_LBERT_ERR_size 16 |
| #define SSP_CR_LANE1_DIG_RX_LBERT_ERR_OV14 [15:15] |
| #define SSP_CR_LANE1_DIG_RX_LBERT_ERR_COUNT [14:0] |
| |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_CTL 0x1118 |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_CTL_rst 14'b00000000000000 |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_CTL_size 14 |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_CTL_RX_VALID_CTL [13:12] |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_CTL_DELAY [11:3] |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_CTL_MODE [2:0] |
| |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_PHASE 0x1119 |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_PHASE_rst 15'b000000000000000 |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_PHASE_size 15 |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_PHASE_BASE [14:10] |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_PHASE_SCOPE_DELAY [9:8] |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_PHASE_SCOPE_SEL [7:7] |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_PHASE_UPDATE [6:6] |
| #define SSP_CR_LANE1_DIG_RX_SCOPE_PHASE_SAMPLE_PHASE [5:0] |
| |
| #define SSP_CR_LANE1_DIG_RX_DPLL_FREQ 0x111A |
| #define SSP_CR_LANE1_DIG_RX_DPLL_FREQ_rst 13'b0000000000000 |
| #define SSP_CR_LANE1_DIG_RX_DPLL_FREQ_size 13 |
| #define SSP_CR_LANE1_DIG_RX_DPLL_FREQ_DTHR [0:0] |
| #define SSP_CR_LANE1_DIG_RX_DPLL_FREQ_VAL [12:1] |
| |
| #define SSP_CR_LANE1_DIG_RX_CDR_CTL 0x111B |
| #define SSP_CR_LANE1_DIG_RX_CDR_CTL_rst 0b0000000000001111 |
| #define SSP_CR_LANE1_DIG_RX_CDR_CTL_size 16 |
| #define SSP_CR_LANE1_DIG_RX_CDR_CTL_PHDET_EN [1:0] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CTL_PHDET_EDGE [3:2] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CTL_PHDET_POL [4:4] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CTL_OVRD_DPLL_GAIN [5:5] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CTL_PHUG_VALUE [7:6] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CTL_FRUG_VALUE [9:8] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CTL_FAST_START [10:10] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CTL_ALWAYS_REALIGN [11:11] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CTL_DTB_SEL [15:12] |
| |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG 0x111C |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_rst 0b0000000000000000 |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_size 16 |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_adap_rx_eq [15:13] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_rx_eq_ctr [12:10] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_rx_ana_eq [9:7] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_adap_rx_valid [6:6] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en_adap [5:5] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en_eq [4:4] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_aligned [3:3] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_rx_valid [2:2] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_timeout [1:1] |
| #define SSP_CR_LANE1_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en [0:0] |
| |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_OVRD 0x111D |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_OVRD_rst 0b1000000000000000 |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_OVRD_size 16 |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_OVRD_adap_ctr_level [15:11] |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_OVRD_adap_polarity [10:10] |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector_ovrd [9:9] |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector_en [8:8] |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector [7:0] |
| |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC 0x111E |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_rst 12'b000000000000 |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_size 12 |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_eq_rx_eq [11:9] |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_eq_locked_vector_en [8:8] |
| #define SSP_CR_LANE1_DIG_RX_CDR_LOCK_VEC_eq_locked_vector [7:0] |
| |
| #define SSP_CR_LANE1_DIG_RX_CDR_ADAP_FSM 0x111F |
| #define SSP_CR_LANE1_DIG_RX_CDR_ADAP_FSM_rst 0b0000000000000000 |
| #define SSP_CR_LANE1_DIG_RX_CDR_ADAP_FSM_size 16 |
| #define SSP_CR_LANE1_DIG_RX_CDR_ADAP_FSM_mstr_ctr [15:11] |
| #define SSP_CR_LANE1_DIG_RX_CDR_ADAP_FSM_loop_ctr [10:7] |
| #define SSP_CR_LANE1_DIG_RX_CDR_ADAP_FSM_adap_ctr [6:3] |
| #define SSP_CR_LANE1_DIG_RX_CDR_ADAP_FSM_adap_state [2:0] |
| |
| #define SSP_CR_LANE1_ANA_RX_ATB0 0x1120 |
| #define SSP_CR_LANE1_ANA_RX_ATB0_rst 8'b00000000 |
| #define SSP_CR_LANE1_ANA_RX_ATB0_size 8 |
| #define SSP_CR_LANE1_ANA_RX_ATB0_EN_ATB_VOFF [0:0] |
| #define SSP_CR_LANE1_ANA_RX_ATB0_EN_ATB_VOS [1:1] |
| #define SSP_CR_LANE1_ANA_RX_ATB0_EN_ATB_RP_S [2:2] |
| #define SSP_CR_LANE1_ANA_RX_ATB0_EN_ATB_RP_F [3:3] |
| #define SSP_CR_LANE1_ANA_RX_ATB0_EN_ATB_RM_S [4:4] |
| #define SSP_CR_LANE1_ANA_RX_ATB0_EN_ATB_RM_F [5:5] |
| #define SSP_CR_LANE1_ANA_RX_ATB0_EN_MARG [6:6] |
| #define SSP_CR_LANE1_ANA_RX_ATB0_EN_ATB [7:7] |
| |
| #define SSP_CR_LANE1_ANA_RX_ATB1 0x1121 |
| #define SSP_CR_LANE1_ANA_RX_ATB1_rst 8'b00000000 |
| #define SSP_CR_LANE1_ANA_RX_ATB1_size 8 |
| #define SSP_CR_LANE1_ANA_RX_ATB1_RX_NC0 [0:0] |
| #define SSP_CR_LANE1_ANA_RX_ATB1_EN_VLOS_USB3 [1:1] |
| #define SSP_CR_LANE1_ANA_RX_ATB1_MEAS_VP [2:2] |
| #define SSP_CR_LANE1_ANA_RX_ATB1_MEAS_GD [3:3] |
| #define SSP_CR_LANE1_ANA_RX_ATB1_EN_ATB_VRF [4:4] |
| #define SSP_CR_LANE1_ANA_RX_ATB1_EN_ATB_VLOS [5:5] |
| #define SSP_CR_LANE1_ANA_RX_ATB1_VLOS_MIN [6:6] |
| #define SSP_CR_LANE1_ANA_RX_ATB1_VLOS_MAX [7:7] |
| |
| #define SSP_CR_LANE1_ANA_RX_ENPWR0 0x1122 |
| #define SSP_CR_LANE1_ANA_RX_ENPWR0_rst 8'b00000000 |
| #define SSP_CR_LANE1_ANA_RX_ENPWR0_size 8 |
| #define SSP_CR_LANE1_ANA_RX_ENPWR0_LCL_ACJT [0:0] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR0_CTL_ACJT [1:1] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR0_LCL_RXCK [2:2] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR0_CTL_RXCK [3:3] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR0_LCL_EN_LOS [4:4] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR0_CTL_EN_LOS [5:5] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR0_LCL_RXPWRON [6:6] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR0_CTL_RXPWRON [7:7] |
| |
| #define SSP_CR_LANE1_ANA_RX_PMIX_PHASE 0x1123 |
| #define SSP_CR_LANE1_ANA_RX_PMIX_PHASE_rst 8'b00000000 |
| #define SSP_CR_LANE1_ANA_RX_PMIX_PHASE_size 8 |
| #define SSP_CR_LANE1_ANA_RX_PMIX_PHASE_PHASE [7:0] |
| |
| #define SSP_CR_LANE1_ANA_RX_ENPWR1 0x1124 |
| #define SSP_CR_LANE1_ANA_RX_ENPWR1_rst 8'b00000000 |
| #define SSP_CR_LANE1_ANA_RX_ENPWR1_size 8 |
| #define SSP_CR_LANE1_ANA_RX_ENPWR1_CTL_PHASE_REG_RST [7:7] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR1_LCL_PHASE_REG_RST [6:6] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR1_CTL_BST [5:5] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR1_LCL_BST [4:2] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR1_CTL_RXTERM [1:1] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR1_LCL_RXTERM [0:0] |
| |
| #define SSP_CR_LANE1_ANA_RX_ENPWR2 0x1125 |
| #define SSP_CR_LANE1_ANA_RX_ENPWR2_rst 8'b00000000 |
| #define SSP_CR_LANE1_ANA_RX_ENPWR2_size 8 |
| #define SSP_CR_LANE1_ANA_RX_ENPWR2_RX_SCOPE_ATB_0 [0:0] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR2_RX_SCOPE_ATB_1 [1:1] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR2_RX_SCOPE_ATB_2 [2:2] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR2_EN_RXPMIX_FRC_VPMIX [3:3] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR2_EN_RXPMIX_VOSC [4:4] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR2_EN_RXPMIX_VRX [5:5] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR2_EN_RXPMIX_VPMIX [6:6] |
| #define SSP_CR_LANE1_ANA_RX_ENPWR2_EN_RXPMIX_TST [7:7] |
| |
| #define SSP_CR_LANE1_ANA_RX_SCOPE 0x1126 |
| #define SSP_CR_LANE1_ANA_RX_SCOPE_rst 8'b00000000 |
| #define SSP_CR_LANE1_ANA_RX_SCOPE_size 8 |
| #define SSP_CR_LANE1_ANA_RX_SCOPE_RX_NC1 [2:0] |
| #define SSP_CR_LANE1_ANA_RX_SCOPE_RX_SCOPE_FDIV20 [3:3] |
| #define SSP_CR_LANE1_ANA_RX_SCOPE_RX_SCOPE_SLEW [4:4] |
| #define SSP_CR_LANE1_ANA_RX_SCOPE_RX_NC2 [7:5] |
| |
| #define SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL 0x112B |
| #define SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL_rst 8'b00000000 |
| #define SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL_size 8 |
| #define SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL_NOCONN_6 [0:0] |
| #define SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL_NOCONN_7 [1:1] |
| #define SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL_NOCONN_8 [2:2] |
| #define SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL_OVRD_VCM_HOLD [3:3] |
| #define SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL_VCM_HOLD_REG [4:4] |
| #define SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL_OVRD_PULL_UP [5:5] |
| #define SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL_PULL_UP_REG [6:6] |
| #define SSP_CR_LANE1_ANA_TX_TXDRV_CNTRL_PULL_DN_REG [7:7] |
| |
| #define SSP_CR_LANE1_ANA_TX_POWER_CTL 0x112C |
| #define SSP_CR_LANE1_ANA_TX_POWER_CTL_rst 8'b00000000 |
| #define SSP_CR_LANE1_ANA_TX_POWER_CTL_size 8 |
| #define SSP_CR_LANE1_ANA_TX_POWER_CTL_LFPS_high_priority [0:0] |
| #define SSP_CR_LANE1_ANA_TX_POWER_CTL_REFGEN_PDN_REG [1:1] |
| #define SSP_CR_LANE1_ANA_TX_POWER_CTL_TX_DIV_CLK_EN [2:2] |
| #define SSP_CR_LANE1_ANA_TX_POWER_CTL_REFGEN_EN_REG [3:3] |
| #define SSP_CR_LANE1_ANA_TX_POWER_CTL_DATA_EN_REG [4:4] |
| #define SSP_CR_LANE1_ANA_TX_POWER_CTL_CLK_EN_REG [5:5] |
| #define SSP_CR_LANE1_ANA_TX_POWER_CTL_SERIAL_EN_REG [6:6] |
| #define SSP_CR_LANE1_ANA_TX_POWER_CTL_OVRD_EN [7:7] |
| |
| #define SSP_CR_LANE1_ANA_TX_ALT_BLOCK 0x112D |
| #define SSP_CR_LANE1_ANA_TX_ALT_BLOCK_rst 8'b00000000 |
| #define SSP_CR_LANE1_ANA_TX_ALT_BLOCK_size 8 |
| #define SSP_CR_LANE1_ANA_TX_ALT_BLOCK_OVRD_ALT_BUS [0:0] |
| #define SSP_CR_LANE1_ANA_TX_ALT_BLOCK_ALT_OSC_VPHREG [1:1] |
| #define SSP_CR_LANE1_ANA_TX_ALT_BLOCK_ALT_OSC_VPH [2:2] |
| #define SSP_CR_LANE1_ANA_TX_ALT_BLOCK_ALT_OSC_VP [3:3] |
| #define SSP_CR_LANE1_ANA_TX_ALT_BLOCK_JTAG_DATA_REG [4:4] |
| #define SSP_CR_LANE1_ANA_TX_ALT_BLOCK_DRV_SOURCE_REG [6:5] |
| #define SSP_CR_LANE1_ANA_TX_ALT_BLOCK_EN_ALT_BUS [7:7] |
| |
| #define SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK 0x112E |
| #define SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK_rst 8'b00000000 |
| #define SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK_size 8 |
| #define SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK_select_pmix_clk [0:0] |
| #define SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK_NOCONN_01 [1:1] |
| #define SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK_ATB_VDCCM [2:2] |
| #define SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK_ATB_VDCCP [3:3] |
| #define SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK_ATB_VREG_TX [4:4] |
| #define SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK_ATB_VPTX [5:5] |
| #define SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK_TX_LB_EN_REG [6:6] |
| #define SSP_CR_LANE1_ANA_TX_ALT_AND_LOOPBACK_OVRD_TX_LB [7:7] |
| |
| #define SSP_CR_LANE1_ANA_TX_TX_ATB_REG 0x112F |
| #define SSP_CR_LANE1_ANA_TX_TX_ATB_REG_rst 8'b00000000 |
| #define SSP_CR_LANE1_ANA_TX_TX_ATB_REG_size 8 |
| #define SSP_CR_LANE1_ANA_TX_TX_ATB_REG_ATB_VCM [0:0] |
| #define SSP_CR_LANE1_ANA_TX_TX_ATB_REG_ATB_TXSM [1:1] |
| #define SSP_CR_LANE1_ANA_TX_TX_ATB_REG_ATB_TXSP [2:2] |
| #define SSP_CR_LANE1_ANA_TX_TX_ATB_REG_ATB_TXFM [3:3] |
| #define SSP_CR_LANE1_ANA_TX_TX_ATB_REG_ATB_TXFP [4:4] |
| #define SSP_CR_LANE1_ANA_TX_TX_ATB_REG_ATB_RXDETREF [5:5] |
| #define SSP_CR_LANE1_ANA_TX_TX_ATB_REG_ATB_VCM_REP [6:6] |
| #define SSP_CR_LANE1_ANA_TX_TX_ATB_REG_ATB_PBIAS [7:7] |
| |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO 0x1200 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_size 14 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_DETECT_RX_REQ_OVRD [13:13] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_DETECT_RX_REQ [12:12] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_BEACON_EN_OVRD [11:11] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_BEACON_EN [10:10] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_CM_EN_OVRD [9:9] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_CM_EN [8:8] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_EN_OVRD [7:7] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_EN [6:6] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_DATA_EN_OVRD [5:5] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_DATA_EN [4:4] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_INVERT_OVRD [3:3] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_INVERT [2:2] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_TX_LOOPBK_EN_OVRD [1:1] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_LO_LOOPBK_EN [0:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_HI 0x1201 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_HI_rst 10'b0000000000 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_HI_size 10 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_HI_TX_VBOOST_EN_OVRD [9:9] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_HI_TX_VBOOST_EN [8:8] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_HI_TX_RESET_OVRD [7:7] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_HI_TX_RESET [6:6] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_HI_TX_NYQUIST_DATA [5:5] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_HI_TX_CLK_OUT_EN_OVRD [4:4] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_HI_TX_CLK_OUT_EN [3:3] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_HI_TX_RATE_OVRD [2:2] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_IN_HI_TX_RATE [1:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_OVRD_DRV_LO 0x1202 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_DRV_LO_rst 15'b000000000000000 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_DRV_LO_size 15 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_DRV_LO_EN [14:14] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_DRV_LO_PREEMPH [13:7] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_DRV_LO_AMPLITUDE [6:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_OVRD_DRV_HI 0x1203 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_DRV_HI_rst 6'b000000 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_DRV_HI_size 6 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_DRV_HI_EN [5:5] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_DRV_HI_TERM_OFFSET [4:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_OVRD_OUT 0x1204 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_OUT_rst 8'b00000000 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_OUT_size 8 |
| #define SSP_CR_LANE2_DIG_TX_OVRD_OUT_TX_STATE_OVRD [7:7] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_OUT_TX_STATE [6:6] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_OUT_TX_CM_STATE_OVRD [5:5] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_OUT_TX_CM_STATE [4:4] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_OUT_TX_DETECT_RX_ACK_OVRD [3:3] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_OUT_TX_DETECT_RX_ACK [2:2] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_OUT_DETECT_RX_RES_OVRD [1:1] |
| #define SSP_CR_LANE2_DIG_TX_OVRD_OUT_DETECT_RX_RES [0:0] |
| |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO 0x1205 |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_size 14 |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_LOS_EN_OVRD [13:13] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_LOS_EN [12:12] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_TERM_EN_OVRD [11:11] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_TERM_EN [10:10] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_BIT_SHIFT_OVRD [9:9] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_BIT_SHIFT [8:8] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_ALIGN_EN_OVRD [7:7] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_ALIGN_EN [6:6] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_DATA_EN_OVRD [5:5] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_DATA_EN [4:4] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_PLL_EN_OVRD [3:3] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_PLL_EN [2:2] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_INVERT_OVRD [1:1] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_LO_RX_INVERT [0:0] |
| |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI 0x1206 |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_rst 14'b00000000000000 |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_size 14 |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_RX_RESET_OVRD [13:13] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_RX_RESET [12:12] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_RX_EQ_OVRD [11:11] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_RX_EQ [10:8] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_RX_EQ_EN_OVRD [7:7] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_RX_EQ_EN [6:6] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD [5:5] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_RX_LOS_FILTER [4:3] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_RX_RATE_OVRD [2:2] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_IN_HI_RX_RATE [1:0] |
| |
| #define SSP_CR_LANE2_DIG_RX_OVRD_OUT 0x1207 |
| #define SSP_CR_LANE2_DIG_RX_OVRD_OUT_rst 7'b0000000 |
| #define SSP_CR_LANE2_DIG_RX_OVRD_OUT_size 7 |
| #define SSP_CR_LANE2_DIG_RX_OVRD_OUT_ZERO_DATA [6:6] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_OUT_LOS_OVRD [5:5] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_OUT_LOS [4:4] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_OUT_PLL_STATE_OVRD [3:3] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_OUT_PLL_STATE [2:2] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_OUT_VALID_OVRD [1:1] |
| #define SSP_CR_LANE2_DIG_RX_OVRD_OUT_VALID [0:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN 0x1208 |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_rst 12'b000000000000 |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_size 12 |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_TX_VBOOST_EN [11:11] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_TX_CLK_OUT_EN [10:10] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_DETECT_RX_REQ [9:9] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_BEACON_EN [8:8] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_CM_EN [7:7] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_TX_EN [6:6] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_DATA_EN [5:5] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_TX_RESET [4:4] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_INVERT [3:3] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_LOOPBK_EN [2:2] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_IN_TX_RATE [1:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_ASIC_DRV_LO 0x1209 |
| #define SSP_CR_LANE2_DIG_TX_ASIC_DRV_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANE2_DIG_TX_ASIC_DRV_LO_size 14 |
| #define SSP_CR_LANE2_DIG_TX_ASIC_DRV_LO_PREEMPH [13:7] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_DRV_LO_AMPLITUDE [6:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_ASIC_DRV_HI 0x120A |
| #define SSP_CR_LANE2_DIG_TX_ASIC_DRV_HI_rst 5'b00000 |
| #define SSP_CR_LANE2_DIG_TX_ASIC_DRV_HI_size 5 |
| #define SSP_CR_LANE2_DIG_TX_ASIC_DRV_HI_TERM_OFFSET [4:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_ASIC_OUT 0x120B |
| #define SSP_CR_LANE2_DIG_TX_ASIC_OUT_rst 5'b00000 |
| #define SSP_CR_LANE2_DIG_TX_ASIC_OUT_size 5 |
| #define SSP_CR_LANE2_DIG_TX_ASIC_OUT_STATE [4:4] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_OUT_CM_STATE [3:3] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_OUT_DETECT_RX_ACK [2:2] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_OUT_RESERVED [1:1] |
| #define SSP_CR_LANE2_DIG_TX_ASIC_OUT_DETECT_RX_RES [0:0] |
| |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN 0x120C |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_rst 0b0000000000000000 |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_size 16 |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_RX_EQ_EN [15:15] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_RX_EQ [14:12] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_LOS_FILTER [11:10] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_LOS_EN [9:9] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_TERM_EN [8:8] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_CLK_SHIFT [7:7] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_ALIGN_EN [6:6] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_DATA_EN [5:5] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_PLL_EN [4:4] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_RX_RESET [3:3] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_INVERT [2:2] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_IN_RX_RATE [1:0] |
| |
| #define SSP_CR_LANE2_DIG_RX_ASIC_OUT 0x120D |
| #define SSP_CR_LANE2_DIG_RX_ASIC_OUT_rst 3'b000 |
| #define SSP_CR_LANE2_DIG_RX_ASIC_OUT_size 3 |
| #define SSP_CR_LANE2_DIG_RX_ASIC_OUT_LOS [2:2] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_OUT_PLL_STATE [1:1] |
| #define SSP_CR_LANE2_DIG_RX_ASIC_OUT_VALID [0:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_DEBUG 0x1210 |
| #define SSP_CR_LANE2_DIG_TX_DEBUG_rst 12'b000100000000 |
| #define SSP_CR_LANE2_DIG_TX_DEBUG_size 12 |
| #define SSP_CR_LANE2_DIG_TX_DEBUG_RXDET_MEAS_TIME [11:4] |
| #define SSP_CR_LANE2_DIG_TX_DEBUG_DETECT_RX_ALWAYS [3:3] |
| #define SSP_CR_LANE2_DIG_TX_DEBUG_DTB_SEL [2:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_CM_WAIT_TIME_OVRD 0x1211 |
| #define SSP_CR_LANE2_DIG_TX_CM_WAIT_TIME_OVRD_rst 11'b00010011111 |
| #define SSP_CR_LANE2_DIG_TX_CM_WAIT_TIME_OVRD_size 11 |
| #define SSP_CR_LANE2_DIG_TX_CM_WAIT_TIME_OVRD_CM_TIME_OVRD_EN [10:10] |
| #define SSP_CR_LANE2_DIG_TX_CM_WAIT_TIME_OVRD_CM_TIME_OVRD [9:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_0 0x1212 |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_0_rst 0b0000000000000000 |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_0_size 16 |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_0_SHIFT_OUT [15:15] |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_0_DONE [14:14] |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_0_N_USE [13:7] |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_0_N_TRISTATE [6:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_1 0x1213 |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_1_rst 0b0000000000000000 |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_1_size 16 |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_1_FIXED_DONE [15:15] |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_1_TRA_DONE [14:14] |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_1_N_FIXED [13:7] |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_1_N_TRAILER [6:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN 0x1214 |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_rst 4'b0000 |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_size 4 |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_OVRD [3:3] |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_LOAD [2:2] |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_CLK [1:1] |
| #define SSP_CR_LANE2_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_DATA [0:0] |
| |
| #define SSP_CR_LANE2_DIG_TX_LBERT_CTL 0x1215 |
| #define SSP_CR_LANE2_DIG_TX_LBERT_CTL_rst 15'b000000000000000 |
| #define SSP_CR_LANE2_DIG_TX_LBERT_CTL_size 15 |
| #define SSP_CR_LANE2_DIG_TX_LBERT_CTL_MODE [3:0] |
| #define SSP_CR_LANE2_DIG_TX_LBERT_CTL_TRIGGER_ERR [4:4] |
| #define SSP_CR_LANE2_DIG_TX_LBERT_CTL_PAT0 [14:5] |
| |
| #define SSP_CR_LANE2_DIG_RX_LBERT_CTL 0x1216 |
| #define SSP_CR_LANE2_DIG_RX_LBERT_CTL_rst 5'b00000 |
| #define SSP_CR_LANE2_DIG_RX_LBERT_CTL_size 5 |
| #define SSP_CR_LANE2_DIG_RX_LBERT_CTL_MODE [3:0] |
| #define SSP_CR_LANE2_DIG_RX_LBERT_CTL_SYNC [4:4] |
| |
| #define SSP_CR_LANE2_DIG_RX_LBERT_ERR 0x1217 |
| #define SSP_CR_LANE2_DIG_RX_LBERT_ERR_rst 0b0000000000000000 |
| #define SSP_CR_LANE2_DIG_RX_LBERT_ERR_size 16 |
| #define SSP_CR_LANE2_DIG_RX_LBERT_ERR_OV14 [15:15] |
| #define SSP_CR_LANE2_DIG_RX_LBERT_ERR_COUNT [14:0] |
| |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_CTL 0x1218 |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_CTL_rst 14'b00000000000000 |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_CTL_size 14 |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_CTL_RX_VALID_CTL [13:12] |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_CTL_DELAY [11:3] |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_CTL_MODE [2:0] |
| |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_PHASE 0x1219 |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_PHASE_rst 15'b000000000000000 |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_PHASE_size 15 |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_PHASE_BASE [14:10] |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_PHASE_SCOPE_DELAY [9:8] |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_PHASE_SCOPE_SEL [7:7] |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_PHASE_UPDATE [6:6] |
| #define SSP_CR_LANE2_DIG_RX_SCOPE_PHASE_SAMPLE_PHASE [5:0] |
| |
| #define SSP_CR_LANE2_DIG_RX_DPLL_FREQ 0x121A |
| #define SSP_CR_LANE2_DIG_RX_DPLL_FREQ_rst 13'b0000000000000 |
| #define SSP_CR_LANE2_DIG_RX_DPLL_FREQ_size 13 |
| #define SSP_CR_LANE2_DIG_RX_DPLL_FREQ_DTHR [0:0] |
| #define SSP_CR_LANE2_DIG_RX_DPLL_FREQ_VAL [12:1] |
| |
| #define SSP_CR_LANE2_DIG_RX_CDR_CTL 0x121B |
| #define SSP_CR_LANE2_DIG_RX_CDR_CTL_rst 0b0000000000001111 |
| #define SSP_CR_LANE2_DIG_RX_CDR_CTL_size 16 |
| #define SSP_CR_LANE2_DIG_RX_CDR_CTL_PHDET_EN [1:0] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CTL_PHDET_EDGE [3:2] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CTL_PHDET_POL [4:4] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CTL_OVRD_DPLL_GAIN [5:5] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CTL_PHUG_VALUE [7:6] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CTL_FRUG_VALUE [9:8] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CTL_FAST_START [10:10] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CTL_ALWAYS_REALIGN [11:11] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CTL_DTB_SEL [15:12] |
| |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG 0x121C |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_rst 0b0000000000000000 |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_size 16 |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_adap_rx_eq [15:13] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_rx_eq_ctr [12:10] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_rx_ana_eq [9:7] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_adap_rx_valid [6:6] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en_adap [5:5] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en_eq [4:4] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_aligned [3:3] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_rx_valid [2:2] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_timeout [1:1] |
| #define SSP_CR_LANE2_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en [0:0] |
| |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_OVRD 0x121D |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_OVRD_rst 0b1000000000000000 |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_OVRD_size 16 |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_OVRD_adap_ctr_level [15:11] |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_OVRD_adap_polarity [10:10] |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector_ovrd [9:9] |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector_en [8:8] |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector [7:0] |
| |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC 0x121E |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_rst 12'b000000000000 |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_size 12 |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_eq_rx_eq [11:9] |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_eq_locked_vector_en [8:8] |
| #define SSP_CR_LANE2_DIG_RX_CDR_LOCK_VEC_eq_locked_vector [7:0] |
| |
| #define SSP_CR_LANE2_DIG_RX_CDR_ADAP_FSM 0x121F |
| #define SSP_CR_LANE2_DIG_RX_CDR_ADAP_FSM_rst 0b0000000000000000 |
| #define SSP_CR_LANE2_DIG_RX_CDR_ADAP_FSM_size 16 |
| #define SSP_CR_LANE2_DIG_RX_CDR_ADAP_FSM_mstr_ctr [15:11] |
| #define SSP_CR_LANE2_DIG_RX_CDR_ADAP_FSM_loop_ctr [10:7] |
| #define SSP_CR_LANE2_DIG_RX_CDR_ADAP_FSM_adap_ctr [6:3] |
| #define SSP_CR_LANE2_DIG_RX_CDR_ADAP_FSM_adap_state [2:0] |
| |
| #define SSP_CR_LANE2_ANA_RX_ATB0 0x1220 |
| #define SSP_CR_LANE2_ANA_RX_ATB0_rst 8'b00000000 |
| #define SSP_CR_LANE2_ANA_RX_ATB0_size 8 |
| #define SSP_CR_LANE2_ANA_RX_ATB0_EN_ATB_VOFF [0:0] |
| #define SSP_CR_LANE2_ANA_RX_ATB0_EN_ATB_VOS [1:1] |
| #define SSP_CR_LANE2_ANA_RX_ATB0_EN_ATB_RP_S [2:2] |
| #define SSP_CR_LANE2_ANA_RX_ATB0_EN_ATB_RP_F [3:3] |
| #define SSP_CR_LANE2_ANA_RX_ATB0_EN_ATB_RM_S [4:4] |
| #define SSP_CR_LANE2_ANA_RX_ATB0_EN_ATB_RM_F [5:5] |
| #define SSP_CR_LANE2_ANA_RX_ATB0_EN_MARG [6:6] |
| #define SSP_CR_LANE2_ANA_RX_ATB0_EN_ATB [7:7] |
| |
| #define SSP_CR_LANE2_ANA_RX_ATB1 0x1221 |
| #define SSP_CR_LANE2_ANA_RX_ATB1_rst 8'b00000000 |
| #define SSP_CR_LANE2_ANA_RX_ATB1_size 8 |
| #define SSP_CR_LANE2_ANA_RX_ATB1_RX_NC0 [0:0] |
| #define SSP_CR_LANE2_ANA_RX_ATB1_EN_VLOS_USB3 [1:1] |
| #define SSP_CR_LANE2_ANA_RX_ATB1_MEAS_VP [2:2] |
| #define SSP_CR_LANE2_ANA_RX_ATB1_MEAS_GD [3:3] |
| #define SSP_CR_LANE2_ANA_RX_ATB1_EN_ATB_VRF [4:4] |
| #define SSP_CR_LANE2_ANA_RX_ATB1_EN_ATB_VLOS [5:5] |
| #define SSP_CR_LANE2_ANA_RX_ATB1_VLOS_MIN [6:6] |
| #define SSP_CR_LANE2_ANA_RX_ATB1_VLOS_MAX [7:7] |
| |
| #define SSP_CR_LANE2_ANA_RX_ENPWR0 0x1222 |
| #define SSP_CR_LANE2_ANA_RX_ENPWR0_rst 8'b00000000 |
| #define SSP_CR_LANE2_ANA_RX_ENPWR0_size 8 |
| #define SSP_CR_LANE2_ANA_RX_ENPWR0_LCL_ACJT [0:0] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR0_CTL_ACJT [1:1] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR0_LCL_RXCK [2:2] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR0_CTL_RXCK [3:3] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR0_LCL_EN_LOS [4:4] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR0_CTL_EN_LOS [5:5] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR0_LCL_RXPWRON [6:6] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR0_CTL_RXPWRON [7:7] |
| |
| #define SSP_CR_LANE2_ANA_RX_PMIX_PHASE 0x1223 |
| #define SSP_CR_LANE2_ANA_RX_PMIX_PHASE_rst 8'b00000000 |
| #define SSP_CR_LANE2_ANA_RX_PMIX_PHASE_size 8 |
| #define SSP_CR_LANE2_ANA_RX_PMIX_PHASE_PHASE [7:0] |
| |
| #define SSP_CR_LANE2_ANA_RX_ENPWR1 0x1224 |
| #define SSP_CR_LANE2_ANA_RX_ENPWR1_rst 8'b00000000 |
| #define SSP_CR_LANE2_ANA_RX_ENPWR1_size 8 |
| #define SSP_CR_LANE2_ANA_RX_ENPWR1_CTL_PHASE_REG_RST [7:7] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR1_LCL_PHASE_REG_RST [6:6] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR1_CTL_BST [5:5] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR1_LCL_BST [4:2] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR1_CTL_RXTERM [1:1] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR1_LCL_RXTERM [0:0] |
| |
| #define SSP_CR_LANE2_ANA_RX_ENPWR2 0x1225 |
| #define SSP_CR_LANE2_ANA_RX_ENPWR2_rst 8'b00000000 |
| #define SSP_CR_LANE2_ANA_RX_ENPWR2_size 8 |
| #define SSP_CR_LANE2_ANA_RX_ENPWR2_RX_SCOPE_ATB_0 [0:0] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR2_RX_SCOPE_ATB_1 [1:1] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR2_RX_SCOPE_ATB_2 [2:2] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR2_EN_RXPMIX_FRC_VPMIX [3:3] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR2_EN_RXPMIX_VOSC [4:4] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR2_EN_RXPMIX_VRX [5:5] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR2_EN_RXPMIX_VPMIX [6:6] |
| #define SSP_CR_LANE2_ANA_RX_ENPWR2_EN_RXPMIX_TST [7:7] |
| |
| #define SSP_CR_LANE2_ANA_RX_SCOPE 0x1226 |
| #define SSP_CR_LANE2_ANA_RX_SCOPE_rst 8'b00000000 |
| #define SSP_CR_LANE2_ANA_RX_SCOPE_size 8 |
| #define SSP_CR_LANE2_ANA_RX_SCOPE_RX_NC1 [2:0] |
| #define SSP_CR_LANE2_ANA_RX_SCOPE_RX_SCOPE_FDIV20 [3:3] |
| #define SSP_CR_LANE2_ANA_RX_SCOPE_RX_SCOPE_SLEW [4:4] |
| #define SSP_CR_LANE2_ANA_RX_SCOPE_RX_NC2 [7:5] |
| |
| #define SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL 0x122B |
| #define SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL_rst 8'b00000000 |
| #define SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL_size 8 |
| #define SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL_NOCONN_6 [0:0] |
| #define SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL_NOCONN_7 [1:1] |
| #define SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL_NOCONN_8 [2:2] |
| #define SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL_OVRD_VCM_HOLD [3:3] |
| #define SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL_VCM_HOLD_REG [4:4] |
| #define SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL_OVRD_PULL_UP [5:5] |
| #define SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL_PULL_UP_REG [6:6] |
| #define SSP_CR_LANE2_ANA_TX_TXDRV_CNTRL_PULL_DN_REG [7:7] |
| |
| #define SSP_CR_LANE2_ANA_TX_POWER_CTL 0x122C |
| #define SSP_CR_LANE2_ANA_TX_POWER_CTL_rst 8'b00000000 |
| #define SSP_CR_LANE2_ANA_TX_POWER_CTL_size 8 |
| #define SSP_CR_LANE2_ANA_TX_POWER_CTL_LFPS_high_priority [0:0] |
| #define SSP_CR_LANE2_ANA_TX_POWER_CTL_REFGEN_PDN_REG [1:1] |
| #define SSP_CR_LANE2_ANA_TX_POWER_CTL_TX_DIV_CLK_EN [2:2] |
| #define SSP_CR_LANE2_ANA_TX_POWER_CTL_REFGEN_EN_REG [3:3] |
| #define SSP_CR_LANE2_ANA_TX_POWER_CTL_DATA_EN_REG [4:4] |
| #define SSP_CR_LANE2_ANA_TX_POWER_CTL_CLK_EN_REG [5:5] |
| #define SSP_CR_LANE2_ANA_TX_POWER_CTL_SERIAL_EN_REG [6:6] |
| #define SSP_CR_LANE2_ANA_TX_POWER_CTL_OVRD_EN [7:7] |
| |
| #define SSP_CR_LANE2_ANA_TX_ALT_BLOCK 0x122D |
| #define SSP_CR_LANE2_ANA_TX_ALT_BLOCK_rst 8'b00000000 |
| #define SSP_CR_LANE2_ANA_TX_ALT_BLOCK_size 8 |
| #define SSP_CR_LANE2_ANA_TX_ALT_BLOCK_OVRD_ALT_BUS [0:0] |
| #define SSP_CR_LANE2_ANA_TX_ALT_BLOCK_ALT_OSC_VPHREG [1:1] |
| #define SSP_CR_LANE2_ANA_TX_ALT_BLOCK_ALT_OSC_VPH [2:2] |
| #define SSP_CR_LANE2_ANA_TX_ALT_BLOCK_ALT_OSC_VP [3:3] |
| #define SSP_CR_LANE2_ANA_TX_ALT_BLOCK_JTAG_DATA_REG [4:4] |
| #define SSP_CR_LANE2_ANA_TX_ALT_BLOCK_DRV_SOURCE_REG [6:5] |
| #define SSP_CR_LANE2_ANA_TX_ALT_BLOCK_EN_ALT_BUS [7:7] |
| |
| #define SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK 0x122E |
| #define SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK_rst 8'b00000000 |
| #define SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK_size 8 |
| #define SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK_select_pmix_clk [0:0] |
| #define SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK_NOCONN_01 [1:1] |
| #define SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK_ATB_VDCCM [2:2] |
| #define SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK_ATB_VDCCP [3:3] |
| #define SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK_ATB_VREG_TX [4:4] |
| #define SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK_ATB_VPTX [5:5] |
| #define SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK_TX_LB_EN_REG [6:6] |
| #define SSP_CR_LANE2_ANA_TX_ALT_AND_LOOPBACK_OVRD_TX_LB [7:7] |
| |
| #define SSP_CR_LANE2_ANA_TX_TX_ATB_REG 0x122F |
| #define SSP_CR_LANE2_ANA_TX_TX_ATB_REG_rst 8'b00000000 |
| #define SSP_CR_LANE2_ANA_TX_TX_ATB_REG_size 8 |
| #define SSP_CR_LANE2_ANA_TX_TX_ATB_REG_ATB_VCM [0:0] |
| #define SSP_CR_LANE2_ANA_TX_TX_ATB_REG_ATB_TXSM [1:1] |
| #define SSP_CR_LANE2_ANA_TX_TX_ATB_REG_ATB_TXSP [2:2] |
| #define SSP_CR_LANE2_ANA_TX_TX_ATB_REG_ATB_TXFM [3:3] |
| #define SSP_CR_LANE2_ANA_TX_TX_ATB_REG_ATB_TXFP [4:4] |
| #define SSP_CR_LANE2_ANA_TX_TX_ATB_REG_ATB_RXDETREF [5:5] |
| #define SSP_CR_LANE2_ANA_TX_TX_ATB_REG_ATB_VCM_REP [6:6] |
| #define SSP_CR_LANE2_ANA_TX_TX_ATB_REG_ATB_PBIAS [7:7] |
| |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO 0x1300 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_size 14 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_DETECT_RX_REQ_OVRD [13:13] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_DETECT_RX_REQ [12:12] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_BEACON_EN_OVRD [11:11] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_BEACON_EN [10:10] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_CM_EN_OVRD [9:9] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_CM_EN [8:8] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_EN_OVRD [7:7] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_EN [6:6] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_DATA_EN_OVRD [5:5] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_DATA_EN [4:4] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_INVERT_OVRD [3:3] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_INVERT [2:2] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_TX_LOOPBK_EN_OVRD [1:1] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_LO_LOOPBK_EN [0:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_HI 0x1301 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_HI_rst 10'b0000000000 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_HI_size 10 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_HI_TX_VBOOST_EN_OVRD [9:9] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_HI_TX_VBOOST_EN [8:8] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_HI_TX_RESET_OVRD [7:7] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_HI_TX_RESET [6:6] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_HI_TX_NYQUIST_DATA [5:5] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_HI_TX_CLK_OUT_EN_OVRD [4:4] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_HI_TX_CLK_OUT_EN [3:3] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_HI_TX_RATE_OVRD [2:2] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_IN_HI_TX_RATE [1:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_OVRD_DRV_LO 0x1302 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_DRV_LO_rst 15'b000000000000000 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_DRV_LO_size 15 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_DRV_LO_EN [14:14] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_DRV_LO_PREEMPH [13:7] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_DRV_LO_AMPLITUDE [6:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_OVRD_DRV_HI 0x1303 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_DRV_HI_rst 6'b000000 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_DRV_HI_size 6 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_DRV_HI_EN [5:5] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_DRV_HI_TERM_OFFSET [4:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_OVRD_OUT 0x1304 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_OUT_rst 8'b00000000 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_OUT_size 8 |
| #define SSP_CR_LANE3_DIG_TX_OVRD_OUT_TX_STATE_OVRD [7:7] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_OUT_TX_STATE [6:6] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_OUT_TX_CM_STATE_OVRD [5:5] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_OUT_TX_CM_STATE [4:4] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_OUT_TX_DETECT_RX_ACK_OVRD [3:3] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_OUT_TX_DETECT_RX_ACK [2:2] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_OUT_DETECT_RX_RES_OVRD [1:1] |
| #define SSP_CR_LANE3_DIG_TX_OVRD_OUT_DETECT_RX_RES [0:0] |
| |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO 0x1305 |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_size 14 |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_LOS_EN_OVRD [13:13] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_LOS_EN [12:12] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_TERM_EN_OVRD [11:11] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_TERM_EN [10:10] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_BIT_SHIFT_OVRD [9:9] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_BIT_SHIFT [8:8] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_ALIGN_EN_OVRD [7:7] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_ALIGN_EN [6:6] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_DATA_EN_OVRD [5:5] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_DATA_EN [4:4] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_PLL_EN_OVRD [3:3] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_PLL_EN [2:2] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_INVERT_OVRD [1:1] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_LO_RX_INVERT [0:0] |
| |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI 0x1306 |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_rst 14'b00000000000000 |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_size 14 |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_RX_RESET_OVRD [13:13] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_RX_RESET [12:12] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_RX_EQ_OVRD [11:11] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_RX_EQ [10:8] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_RX_EQ_EN_OVRD [7:7] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_RX_EQ_EN [6:6] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD [5:5] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_RX_LOS_FILTER [4:3] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_RX_RATE_OVRD [2:2] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_IN_HI_RX_RATE [1:0] |
| |
| #define SSP_CR_LANE3_DIG_RX_OVRD_OUT 0x1307 |
| #define SSP_CR_LANE3_DIG_RX_OVRD_OUT_rst 7'b0000000 |
| #define SSP_CR_LANE3_DIG_RX_OVRD_OUT_size 7 |
| #define SSP_CR_LANE3_DIG_RX_OVRD_OUT_ZERO_DATA [6:6] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_OUT_LOS_OVRD [5:5] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_OUT_LOS [4:4] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_OUT_PLL_STATE_OVRD [3:3] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_OUT_PLL_STATE [2:2] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_OUT_VALID_OVRD [1:1] |
| #define SSP_CR_LANE3_DIG_RX_OVRD_OUT_VALID [0:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN 0x1308 |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_rst 12'b000000000000 |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_size 12 |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_TX_VBOOST_EN [11:11] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_TX_CLK_OUT_EN [10:10] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_DETECT_RX_REQ [9:9] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_BEACON_EN [8:8] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_CM_EN [7:7] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_TX_EN [6:6] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_DATA_EN [5:5] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_TX_RESET [4:4] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_INVERT [3:3] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_LOOPBK_EN [2:2] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_IN_TX_RATE [1:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_ASIC_DRV_LO 0x1309 |
| #define SSP_CR_LANE3_DIG_TX_ASIC_DRV_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANE3_DIG_TX_ASIC_DRV_LO_size 14 |
| #define SSP_CR_LANE3_DIG_TX_ASIC_DRV_LO_PREEMPH [13:7] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_DRV_LO_AMPLITUDE [6:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_ASIC_DRV_HI 0x130A |
| #define SSP_CR_LANE3_DIG_TX_ASIC_DRV_HI_rst 5'b00000 |
| #define SSP_CR_LANE3_DIG_TX_ASIC_DRV_HI_size 5 |
| #define SSP_CR_LANE3_DIG_TX_ASIC_DRV_HI_TERM_OFFSET [4:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_ASIC_OUT 0x130B |
| #define SSP_CR_LANE3_DIG_TX_ASIC_OUT_rst 5'b00000 |
| #define SSP_CR_LANE3_DIG_TX_ASIC_OUT_size 5 |
| #define SSP_CR_LANE3_DIG_TX_ASIC_OUT_STATE [4:4] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_OUT_CM_STATE [3:3] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_OUT_DETECT_RX_ACK [2:2] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_OUT_RESERVED [1:1] |
| #define SSP_CR_LANE3_DIG_TX_ASIC_OUT_DETECT_RX_RES [0:0] |
| |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN 0x130C |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_rst 0b0000000000000000 |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_size 16 |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_RX_EQ_EN [15:15] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_RX_EQ [14:12] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_LOS_FILTER [11:10] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_LOS_EN [9:9] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_TERM_EN [8:8] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_CLK_SHIFT [7:7] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_ALIGN_EN [6:6] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_DATA_EN [5:5] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_PLL_EN [4:4] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_RX_RESET [3:3] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_INVERT [2:2] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_IN_RX_RATE [1:0] |
| |
| #define SSP_CR_LANE3_DIG_RX_ASIC_OUT 0x130D |
| #define SSP_CR_LANE3_DIG_RX_ASIC_OUT_rst 3'b000 |
| #define SSP_CR_LANE3_DIG_RX_ASIC_OUT_size 3 |
| #define SSP_CR_LANE3_DIG_RX_ASIC_OUT_LOS [2:2] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_OUT_PLL_STATE [1:1] |
| #define SSP_CR_LANE3_DIG_RX_ASIC_OUT_VALID [0:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_DEBUG 0x1310 |
| #define SSP_CR_LANE3_DIG_TX_DEBUG_rst 12'b000100000000 |
| #define SSP_CR_LANE3_DIG_TX_DEBUG_size 12 |
| #define SSP_CR_LANE3_DIG_TX_DEBUG_RXDET_MEAS_TIME [11:4] |
| #define SSP_CR_LANE3_DIG_TX_DEBUG_DETECT_RX_ALWAYS [3:3] |
| #define SSP_CR_LANE3_DIG_TX_DEBUG_DTB_SEL [2:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_CM_WAIT_TIME_OVRD 0x1311 |
| #define SSP_CR_LANE3_DIG_TX_CM_WAIT_TIME_OVRD_rst 11'b00010011111 |
| #define SSP_CR_LANE3_DIG_TX_CM_WAIT_TIME_OVRD_size 11 |
| #define SSP_CR_LANE3_DIG_TX_CM_WAIT_TIME_OVRD_CM_TIME_OVRD_EN [10:10] |
| #define SSP_CR_LANE3_DIG_TX_CM_WAIT_TIME_OVRD_CM_TIME_OVRD [9:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_0 0x1312 |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_0_rst 0b0000000000000000 |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_0_size 16 |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_0_SHIFT_OUT [15:15] |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_0_DONE [14:14] |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_0_N_USE [13:7] |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_0_N_TRISTATE [6:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_1 0x1313 |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_1_rst 0b0000000000000000 |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_1_size 16 |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_1_FIXED_DONE [15:15] |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_1_TRA_DONE [14:14] |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_1_N_FIXED [13:7] |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_1_N_TRAILER [6:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN 0x1314 |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_rst 4'b0000 |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_size 4 |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_OVRD [3:3] |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_LOAD [2:2] |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_CLK [1:1] |
| #define SSP_CR_LANE3_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_DATA [0:0] |
| |
| #define SSP_CR_LANE3_DIG_TX_LBERT_CTL 0x1315 |
| #define SSP_CR_LANE3_DIG_TX_LBERT_CTL_rst 15'b000000000000000 |
| #define SSP_CR_LANE3_DIG_TX_LBERT_CTL_size 15 |
| #define SSP_CR_LANE3_DIG_TX_LBERT_CTL_MODE [3:0] |
| #define SSP_CR_LANE3_DIG_TX_LBERT_CTL_TRIGGER_ERR [4:4] |
| #define SSP_CR_LANE3_DIG_TX_LBERT_CTL_PAT0 [14:5] |
| |
| #define SSP_CR_LANE3_DIG_RX_LBERT_CTL 0x1316 |
| #define SSP_CR_LANE3_DIG_RX_LBERT_CTL_rst 5'b00000 |
| #define SSP_CR_LANE3_DIG_RX_LBERT_CTL_size 5 |
| #define SSP_CR_LANE3_DIG_RX_LBERT_CTL_MODE [3:0] |
| #define SSP_CR_LANE3_DIG_RX_LBERT_CTL_SYNC [4:4] |
| |
| #define SSP_CR_LANE3_DIG_RX_LBERT_ERR 0x1317 |
| #define SSP_CR_LANE3_DIG_RX_LBERT_ERR_rst 0b0000000000000000 |
| #define SSP_CR_LANE3_DIG_RX_LBERT_ERR_size 16 |
| #define SSP_CR_LANE3_DIG_RX_LBERT_ERR_OV14 [15:15] |
| #define SSP_CR_LANE3_DIG_RX_LBERT_ERR_COUNT [14:0] |
| |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_CTL 0x1318 |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_CTL_rst 14'b00000000000000 |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_CTL_size 14 |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_CTL_RX_VALID_CTL [13:12] |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_CTL_DELAY [11:3] |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_CTL_MODE [2:0] |
| |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_PHASE 0x1319 |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_PHASE_rst 15'b000000000000000 |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_PHASE_size 15 |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_PHASE_BASE [14:10] |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_PHASE_SCOPE_DELAY [9:8] |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_PHASE_SCOPE_SEL [7:7] |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_PHASE_UPDATE [6:6] |
| #define SSP_CR_LANE3_DIG_RX_SCOPE_PHASE_SAMPLE_PHASE [5:0] |
| |
| #define SSP_CR_LANE3_DIG_RX_DPLL_FREQ 0x131A |
| #define SSP_CR_LANE3_DIG_RX_DPLL_FREQ_rst 13'b0000000000000 |
| #define SSP_CR_LANE3_DIG_RX_DPLL_FREQ_size 13 |
| #define SSP_CR_LANE3_DIG_RX_DPLL_FREQ_DTHR [0:0] |
| #define SSP_CR_LANE3_DIG_RX_DPLL_FREQ_VAL [12:1] |
| |
| #define SSP_CR_LANE3_DIG_RX_CDR_CTL 0x131B |
| #define SSP_CR_LANE3_DIG_RX_CDR_CTL_rst 0b0000000000001111 |
| #define SSP_CR_LANE3_DIG_RX_CDR_CTL_size 16 |
| #define SSP_CR_LANE3_DIG_RX_CDR_CTL_PHDET_EN [1:0] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CTL_PHDET_EDGE [3:2] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CTL_PHDET_POL [4:4] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CTL_OVRD_DPLL_GAIN [5:5] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CTL_PHUG_VALUE [7:6] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CTL_FRUG_VALUE [9:8] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CTL_FAST_START [10:10] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CTL_ALWAYS_REALIGN [11:11] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CTL_DTB_SEL [15:12] |
| |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG 0x131C |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_rst 0b0000000000000000 |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_size 16 |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_adap_rx_eq [15:13] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_rx_eq_ctr [12:10] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_rx_ana_eq [9:7] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_adap_rx_valid [6:6] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en_adap [5:5] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en_eq [4:4] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_aligned [3:3] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_rx_valid [2:2] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_timeout [1:1] |
| #define SSP_CR_LANE3_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en [0:0] |
| |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_OVRD 0x131D |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_OVRD_rst 0b1000000000000000 |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_OVRD_size 16 |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_OVRD_adap_ctr_level [15:11] |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_OVRD_adap_polarity [10:10] |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector_ovrd [9:9] |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector_en [8:8] |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector [7:0] |
| |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC 0x131E |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_rst 12'b000000000000 |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_size 12 |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_eq_rx_eq [11:9] |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_eq_locked_vector_en [8:8] |
| #define SSP_CR_LANE3_DIG_RX_CDR_LOCK_VEC_eq_locked_vector [7:0] |
| |
| #define SSP_CR_LANE3_DIG_RX_CDR_ADAP_FSM 0x131F |
| #define SSP_CR_LANE3_DIG_RX_CDR_ADAP_FSM_rst 0b0000000000000000 |
| #define SSP_CR_LANE3_DIG_RX_CDR_ADAP_FSM_size 16 |
| #define SSP_CR_LANE3_DIG_RX_CDR_ADAP_FSM_mstr_ctr [15:11] |
| #define SSP_CR_LANE3_DIG_RX_CDR_ADAP_FSM_loop_ctr [10:7] |
| #define SSP_CR_LANE3_DIG_RX_CDR_ADAP_FSM_adap_ctr [6:3] |
| #define SSP_CR_LANE3_DIG_RX_CDR_ADAP_FSM_adap_state [2:0] |
| |
| #define SSP_CR_LANE3_ANA_RX_ATB0 0x1320 |
| #define SSP_CR_LANE3_ANA_RX_ATB0_rst 8'b00000000 |
| #define SSP_CR_LANE3_ANA_RX_ATB0_size 8 |
| #define SSP_CR_LANE3_ANA_RX_ATB0_EN_ATB_VOFF [0:0] |
| #define SSP_CR_LANE3_ANA_RX_ATB0_EN_ATB_VOS [1:1] |
| #define SSP_CR_LANE3_ANA_RX_ATB0_EN_ATB_RP_S [2:2] |
| #define SSP_CR_LANE3_ANA_RX_ATB0_EN_ATB_RP_F [3:3] |
| #define SSP_CR_LANE3_ANA_RX_ATB0_EN_ATB_RM_S [4:4] |
| #define SSP_CR_LANE3_ANA_RX_ATB0_EN_ATB_RM_F [5:5] |
| #define SSP_CR_LANE3_ANA_RX_ATB0_EN_MARG [6:6] |
| #define SSP_CR_LANE3_ANA_RX_ATB0_EN_ATB [7:7] |
| |
| #define SSP_CR_LANE3_ANA_RX_ATB1 0x1321 |
| #define SSP_CR_LANE3_ANA_RX_ATB1_rst 8'b00000000 |
| #define SSP_CR_LANE3_ANA_RX_ATB1_size 8 |
| #define SSP_CR_LANE3_ANA_RX_ATB1_RX_NC0 [0:0] |
| #define SSP_CR_LANE3_ANA_RX_ATB1_EN_VLOS_USB3 [1:1] |
| #define SSP_CR_LANE3_ANA_RX_ATB1_MEAS_VP [2:2] |
| #define SSP_CR_LANE3_ANA_RX_ATB1_MEAS_GD [3:3] |
| #define SSP_CR_LANE3_ANA_RX_ATB1_EN_ATB_VRF [4:4] |
| #define SSP_CR_LANE3_ANA_RX_ATB1_EN_ATB_VLOS [5:5] |
| #define SSP_CR_LANE3_ANA_RX_ATB1_VLOS_MIN [6:6] |
| #define SSP_CR_LANE3_ANA_RX_ATB1_VLOS_MAX [7:7] |
| |
| #define SSP_CR_LANE3_ANA_RX_ENPWR0 0x1322 |
| #define SSP_CR_LANE3_ANA_RX_ENPWR0_rst 8'b00000000 |
| #define SSP_CR_LANE3_ANA_RX_ENPWR0_size 8 |
| #define SSP_CR_LANE3_ANA_RX_ENPWR0_LCL_ACJT [0:0] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR0_CTL_ACJT [1:1] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR0_LCL_RXCK [2:2] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR0_CTL_RXCK [3:3] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR0_LCL_EN_LOS [4:4] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR0_CTL_EN_LOS [5:5] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR0_LCL_RXPWRON [6:6] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR0_CTL_RXPWRON [7:7] |
| |
| #define SSP_CR_LANE3_ANA_RX_PMIX_PHASE 0x1323 |
| #define SSP_CR_LANE3_ANA_RX_PMIX_PHASE_rst 8'b00000000 |
| #define SSP_CR_LANE3_ANA_RX_PMIX_PHASE_size 8 |
| #define SSP_CR_LANE3_ANA_RX_PMIX_PHASE_PHASE [7:0] |
| |
| #define SSP_CR_LANE3_ANA_RX_ENPWR1 0x1324 |
| #define SSP_CR_LANE3_ANA_RX_ENPWR1_rst 8'b00000000 |
| #define SSP_CR_LANE3_ANA_RX_ENPWR1_size 8 |
| #define SSP_CR_LANE3_ANA_RX_ENPWR1_CTL_PHASE_REG_RST [7:7] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR1_LCL_PHASE_REG_RST [6:6] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR1_CTL_BST [5:5] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR1_LCL_BST [4:2] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR1_CTL_RXTERM [1:1] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR1_LCL_RXTERM [0:0] |
| |
| #define SSP_CR_LANE3_ANA_RX_ENPWR2 0x1325 |
| #define SSP_CR_LANE3_ANA_RX_ENPWR2_rst 8'b00000000 |
| #define SSP_CR_LANE3_ANA_RX_ENPWR2_size 8 |
| #define SSP_CR_LANE3_ANA_RX_ENPWR2_RX_SCOPE_ATB_0 [0:0] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR2_RX_SCOPE_ATB_1 [1:1] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR2_RX_SCOPE_ATB_2 [2:2] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR2_EN_RXPMIX_FRC_VPMIX [3:3] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR2_EN_RXPMIX_VOSC [4:4] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR2_EN_RXPMIX_VRX [5:5] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR2_EN_RXPMIX_VPMIX [6:6] |
| #define SSP_CR_LANE3_ANA_RX_ENPWR2_EN_RXPMIX_TST [7:7] |
| |
| #define SSP_CR_LANE3_ANA_RX_SCOPE 0x1326 |
| #define SSP_CR_LANE3_ANA_RX_SCOPE_rst 8'b00000000 |
| #define SSP_CR_LANE3_ANA_RX_SCOPE_size 8 |
| #define SSP_CR_LANE3_ANA_RX_SCOPE_RX_NC1 [2:0] |
| #define SSP_CR_LANE3_ANA_RX_SCOPE_RX_SCOPE_FDIV20 [3:3] |
| #define SSP_CR_LANE3_ANA_RX_SCOPE_RX_SCOPE_SLEW [4:4] |
| #define SSP_CR_LANE3_ANA_RX_SCOPE_RX_NC2 [7:5] |
| |
| #define SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL 0x132B |
| #define SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL_rst 8'b00000000 |
| #define SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL_size 8 |
| #define SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL_NOCONN_6 [0:0] |
| #define SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL_NOCONN_7 [1:1] |
| #define SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL_NOCONN_8 [2:2] |
| #define SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL_OVRD_VCM_HOLD [3:3] |
| #define SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL_VCM_HOLD_REG [4:4] |
| #define SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL_OVRD_PULL_UP [5:5] |
| #define SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL_PULL_UP_REG [6:6] |
| #define SSP_CR_LANE3_ANA_TX_TXDRV_CNTRL_PULL_DN_REG [7:7] |
| |
| #define SSP_CR_LANE3_ANA_TX_POWER_CTL 0x132C |
| #define SSP_CR_LANE3_ANA_TX_POWER_CTL_rst 8'b00000000 |
| #define SSP_CR_LANE3_ANA_TX_POWER_CTL_size 8 |
| #define SSP_CR_LANE3_ANA_TX_POWER_CTL_LFPS_high_priority [0:0] |
| #define SSP_CR_LANE3_ANA_TX_POWER_CTL_REFGEN_PDN_REG [1:1] |
| #define SSP_CR_LANE3_ANA_TX_POWER_CTL_TX_DIV_CLK_EN [2:2] |
| #define SSP_CR_LANE3_ANA_TX_POWER_CTL_REFGEN_EN_REG [3:3] |
| #define SSP_CR_LANE3_ANA_TX_POWER_CTL_DATA_EN_REG [4:4] |
| #define SSP_CR_LANE3_ANA_TX_POWER_CTL_CLK_EN_REG [5:5] |
| #define SSP_CR_LANE3_ANA_TX_POWER_CTL_SERIAL_EN_REG [6:6] |
| #define SSP_CR_LANE3_ANA_TX_POWER_CTL_OVRD_EN [7:7] |
| |
| #define SSP_CR_LANE3_ANA_TX_ALT_BLOCK 0x132D |
| #define SSP_CR_LANE3_ANA_TX_ALT_BLOCK_rst 8'b00000000 |
| #define SSP_CR_LANE3_ANA_TX_ALT_BLOCK_size 8 |
| #define SSP_CR_LANE3_ANA_TX_ALT_BLOCK_OVRD_ALT_BUS [0:0] |
| #define SSP_CR_LANE3_ANA_TX_ALT_BLOCK_ALT_OSC_VPHREG [1:1] |
| #define SSP_CR_LANE3_ANA_TX_ALT_BLOCK_ALT_OSC_VPH [2:2] |
| #define SSP_CR_LANE3_ANA_TX_ALT_BLOCK_ALT_OSC_VP [3:3] |
| #define SSP_CR_LANE3_ANA_TX_ALT_BLOCK_JTAG_DATA_REG [4:4] |
| #define SSP_CR_LANE3_ANA_TX_ALT_BLOCK_DRV_SOURCE_REG [6:5] |
| #define SSP_CR_LANE3_ANA_TX_ALT_BLOCK_EN_ALT_BUS [7:7] |
| |
| #define SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK 0x132E |
| #define SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK_rst 8'b00000000 |
| #define SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK_size 8 |
| #define SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK_select_pmix_clk [0:0] |
| #define SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK_NOCONN_01 [1:1] |
| #define SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK_ATB_VDCCM [2:2] |
| #define SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK_ATB_VDCCP [3:3] |
| #define SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK_ATB_VREG_TX [4:4] |
| #define SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK_ATB_VPTX [5:5] |
| #define SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK_TX_LB_EN_REG [6:6] |
| #define SSP_CR_LANE3_ANA_TX_ALT_AND_LOOPBACK_OVRD_TX_LB [7:7] |
| |
| #define SSP_CR_LANE3_ANA_TX_TX_ATB_REG 0x132F |
| #define SSP_CR_LANE3_ANA_TX_TX_ATB_REG_rst 8'b00000000 |
| #define SSP_CR_LANE3_ANA_TX_TX_ATB_REG_size 8 |
| #define SSP_CR_LANE3_ANA_TX_TX_ATB_REG_ATB_VCM [0:0] |
| #define SSP_CR_LANE3_ANA_TX_TX_ATB_REG_ATB_TXSM [1:1] |
| #define SSP_CR_LANE3_ANA_TX_TX_ATB_REG_ATB_TXSP [2:2] |
| #define SSP_CR_LANE3_ANA_TX_TX_ATB_REG_ATB_TXFM [3:3] |
| #define SSP_CR_LANE3_ANA_TX_TX_ATB_REG_ATB_TXFP [4:4] |
| #define SSP_CR_LANE3_ANA_TX_TX_ATB_REG_ATB_RXDETREF [5:5] |
| #define SSP_CR_LANE3_ANA_TX_TX_ATB_REG_ATB_VCM_REP [6:6] |
| #define SSP_CR_LANE3_ANA_TX_TX_ATB_REG_ATB_PBIAS [7:7] |
| |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO 0x9000 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_size 14 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_DETECT_RX_REQ_OVRD [13:13] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_DETECT_RX_REQ [12:12] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_BEACON_EN_OVRD [11:11] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_BEACON_EN [10:10] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_CM_EN_OVRD [9:9] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_CM_EN [8:8] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_EN_OVRD [7:7] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_EN [6:6] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_DATA_EN_OVRD [5:5] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_DATA_EN [4:4] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_INVERT_OVRD [3:3] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_INVERT [2:2] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_TX_LOOPBK_EN_OVRD [1:1] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_LO_LOOPBK_EN [0:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_HI 0x9001 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_HI_rst 10'b0000000000 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_HI_size 10 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_HI_TX_VBOOST_EN_OVRD [9:9] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_HI_TX_VBOOST_EN [8:8] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_HI_TX_RESET_OVRD [7:7] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_HI_TX_RESET [6:6] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_HI_TX_NYQUIST_DATA [5:5] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_HI_TX_CLK_OUT_EN_OVRD [4:4] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_HI_TX_CLK_OUT_EN [3:3] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_HI_TX_RATE_OVRD [2:2] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_IN_HI_TX_RATE [1:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_OVRD_DRV_LO 0x9002 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_DRV_LO_rst 15'b000000000000000 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_DRV_LO_size 15 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_DRV_LO_EN [14:14] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_DRV_LO_PREEMPH [13:7] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_DRV_LO_AMPLITUDE [6:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_OVRD_DRV_HI 0x9003 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_DRV_HI_rst 6'b000000 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_DRV_HI_size 6 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_DRV_HI_EN [5:5] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_DRV_HI_TERM_OFFSET [4:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_OVRD_OUT 0x9004 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_OUT_rst 8'b00000000 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_OUT_size 8 |
| #define SSP_CR_LANEX_DIG_TX_OVRD_OUT_TX_STATE_OVRD [7:7] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_OUT_TX_STATE [6:6] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_OUT_TX_CM_STATE_OVRD [5:5] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_OUT_TX_CM_STATE [4:4] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_OUT_TX_DETECT_RX_ACK_OVRD [3:3] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_OUT_TX_DETECT_RX_ACK [2:2] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_OUT_DETECT_RX_RES_OVRD [1:1] |
| #define SSP_CR_LANEX_DIG_TX_OVRD_OUT_DETECT_RX_RES [0:0] |
| |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO 0x9005 |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_size 14 |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_LOS_EN_OVRD [13:13] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_LOS_EN [12:12] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_TERM_EN_OVRD [11:11] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_TERM_EN [10:10] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_BIT_SHIFT_OVRD [9:9] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_BIT_SHIFT [8:8] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_ALIGN_EN_OVRD [7:7] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_ALIGN_EN [6:6] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_DATA_EN_OVRD [5:5] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_DATA_EN [4:4] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_PLL_EN_OVRD [3:3] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_PLL_EN [2:2] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_INVERT_OVRD [1:1] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_LO_RX_INVERT [0:0] |
| |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI 0x9006 |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_rst 14'b00000000000000 |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_size 14 |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_RX_RESET_OVRD [13:13] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_RX_RESET [12:12] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_RX_EQ_OVRD [11:11] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_RX_EQ [10:8] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_RX_EQ_EN_OVRD [7:7] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_RX_EQ_EN [6:6] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD [5:5] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_RX_LOS_FILTER [4:3] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_RX_RATE_OVRD [2:2] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_IN_HI_RX_RATE [1:0] |
| |
| #define SSP_CR_LANEX_DIG_RX_OVRD_OUT 0x9007 |
| #define SSP_CR_LANEX_DIG_RX_OVRD_OUT_rst 7'b0000000 |
| #define SSP_CR_LANEX_DIG_RX_OVRD_OUT_size 7 |
| #define SSP_CR_LANEX_DIG_RX_OVRD_OUT_ZERO_DATA [6:6] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_OUT_LOS_OVRD [5:5] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_OUT_LOS [4:4] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_OUT_PLL_STATE_OVRD [3:3] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_OUT_PLL_STATE [2:2] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_OUT_VALID_OVRD [1:1] |
| #define SSP_CR_LANEX_DIG_RX_OVRD_OUT_VALID [0:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN 0x9008 |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_rst 12'b000000000000 |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_size 12 |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_TX_VBOOST_EN [11:11] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_TX_CLK_OUT_EN [10:10] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_DETECT_RX_REQ [9:9] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_BEACON_EN [8:8] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_CM_EN [7:7] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_TX_EN [6:6] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_DATA_EN [5:5] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_TX_RESET [4:4] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_INVERT [3:3] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_LOOPBK_EN [2:2] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_IN_TX_RATE [1:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_ASIC_DRV_LO 0x9009 |
| #define SSP_CR_LANEX_DIG_TX_ASIC_DRV_LO_rst 14'b00000000000000 |
| #define SSP_CR_LANEX_DIG_TX_ASIC_DRV_LO_size 14 |
| #define SSP_CR_LANEX_DIG_TX_ASIC_DRV_LO_PREEMPH [13:7] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_DRV_LO_AMPLITUDE [6:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_ASIC_DRV_HI 0x900A |
| #define SSP_CR_LANEX_DIG_TX_ASIC_DRV_HI_rst 5'b00000 |
| #define SSP_CR_LANEX_DIG_TX_ASIC_DRV_HI_size 5 |
| #define SSP_CR_LANEX_DIG_TX_ASIC_DRV_HI_TERM_OFFSET [4:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_ASIC_OUT 0x900B |
| #define SSP_CR_LANEX_DIG_TX_ASIC_OUT_rst 5'b00000 |
| #define SSP_CR_LANEX_DIG_TX_ASIC_OUT_size 5 |
| #define SSP_CR_LANEX_DIG_TX_ASIC_OUT_STATE [4:4] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_OUT_CM_STATE [3:3] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_OUT_DETECT_RX_ACK [2:2] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_OUT_RESERVED [1:1] |
| #define SSP_CR_LANEX_DIG_TX_ASIC_OUT_DETECT_RX_RES [0:0] |
| |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN 0x900C |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_rst 0b0000000000000000 |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_size 16 |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_RX_EQ_EN [15:15] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_RX_EQ [14:12] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_LOS_FILTER [11:10] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_LOS_EN [9:9] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_TERM_EN [8:8] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_CLK_SHIFT [7:7] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_ALIGN_EN [6:6] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_DATA_EN [5:5] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_PLL_EN [4:4] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_RX_RESET [3:3] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_INVERT [2:2] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_IN_RX_RATE [1:0] |
| |
| #define SSP_CR_LANEX_DIG_RX_ASIC_OUT 0x900D |
| #define SSP_CR_LANEX_DIG_RX_ASIC_OUT_rst 3'b000 |
| #define SSP_CR_LANEX_DIG_RX_ASIC_OUT_size 3 |
| #define SSP_CR_LANEX_DIG_RX_ASIC_OUT_LOS [2:2] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_OUT_PLL_STATE [1:1] |
| #define SSP_CR_LANEX_DIG_RX_ASIC_OUT_VALID [0:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_DEBUG 0x9010 |
| #define SSP_CR_LANEX_DIG_TX_DEBUG_rst 12'b000100000000 |
| #define SSP_CR_LANEX_DIG_TX_DEBUG_size 12 |
| #define SSP_CR_LANEX_DIG_TX_DEBUG_RXDET_MEAS_TIME [11:4] |
| #define SSP_CR_LANEX_DIG_TX_DEBUG_DETECT_RX_ALWAYS [3:3] |
| #define SSP_CR_LANEX_DIG_TX_DEBUG_DTB_SEL [2:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_CM_WAIT_TIME_OVRD 0x9011 |
| #define SSP_CR_LANEX_DIG_TX_CM_WAIT_TIME_OVRD_rst 11'b00010011111 |
| #define SSP_CR_LANEX_DIG_TX_CM_WAIT_TIME_OVRD_size 11 |
| #define SSP_CR_LANEX_DIG_TX_CM_WAIT_TIME_OVRD_CM_TIME_OVRD_EN [10:10] |
| #define SSP_CR_LANEX_DIG_TX_CM_WAIT_TIME_OVRD_CM_TIME_OVRD [9:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_0 0x9012 |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_0_rst 0b0000000000000000 |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_0_size 16 |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_0_SHIFT_OUT [15:15] |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_0_DONE [14:14] |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_0_N_USE [13:7] |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_0_N_TRISTATE [6:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_1 0x9013 |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_1_rst 0b0000000000000000 |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_1_size 16 |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_1_FIXED_DONE [15:15] |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_1_TRA_DONE [14:14] |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_1_N_FIXED [13:7] |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_1_N_TRAILER [6:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN 0x9014 |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_rst 4'b0000 |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_size 4 |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_OVRD [3:3] |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_LOAD [2:2] |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_CLK [1:1] |
| #define SSP_CR_LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN_CONFIG_DATA [0:0] |
| |
| #define SSP_CR_LANEX_DIG_TX_LBERT_CTL 0x9015 |
| #define SSP_CR_LANEX_DIG_TX_LBERT_CTL_rst 15'b000000000000000 |
| #define SSP_CR_LANEX_DIG_TX_LBERT_CTL_size 15 |
| #define SSP_CR_LANEX_DIG_TX_LBERT_CTL_MODE [3:0] |
| #define SSP_CR_LANEX_DIG_TX_LBERT_CTL_TRIGGER_ERR [4:4] |
| #define SSP_CR_LANEX_DIG_TX_LBERT_CTL_PAT0 [14:5] |
| |
| #define SSP_CR_LANEX_DIG_RX_LBERT_CTL 0x9016 |
| #define SSP_CR_LANEX_DIG_RX_LBERT_CTL_rst 5'b00000 |
| #define SSP_CR_LANEX_DIG_RX_LBERT_CTL_size 5 |
| #define SSP_CR_LANEX_DIG_RX_LBERT_CTL_MODE [3:0] |
| #define SSP_CR_LANEX_DIG_RX_LBERT_CTL_SYNC [4:4] |
| |
| #define SSP_CR_LANEX_DIG_RX_LBERT_ERR 0x9017 |
| #define SSP_CR_LANEX_DIG_RX_LBERT_ERR_rst 0b0000000000000000 |
| #define SSP_CR_LANEX_DIG_RX_LBERT_ERR_size 16 |
| #define SSP_CR_LANEX_DIG_RX_LBERT_ERR_OV14 [15:15] |
| #define SSP_CR_LANEX_DIG_RX_LBERT_ERR_COUNT [14:0] |
| |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_CTL 0x9018 |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_CTL_rst 14'b00000000000000 |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_CTL_size 14 |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_CTL_RX_VALID_CTL [13:12] |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_CTL_DELAY [11:3] |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_CTL_MODE [2:0] |
| |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_PHASE 0x9019 |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_PHASE_rst 15'b000000000000000 |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_PHASE_size 15 |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_PHASE_BASE [14:10] |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_PHASE_SCOPE_DELAY [9:8] |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_PHASE_SCOPE_SEL [7:7] |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_PHASE_UPDATE [6:6] |
| #define SSP_CR_LANEX_DIG_RX_SCOPE_PHASE_SAMPLE_PHASE [5:0] |
| |
| #define SSP_CR_LANEX_DIG_RX_DPLL_FREQ 0x901A |
| #define SSP_CR_LANEX_DIG_RX_DPLL_FREQ_rst 13'b0000000000000 |
| #define SSP_CR_LANEX_DIG_RX_DPLL_FREQ_size 13 |
| #define SSP_CR_LANEX_DIG_RX_DPLL_FREQ_DTHR [0:0] |
| #define SSP_CR_LANEX_DIG_RX_DPLL_FREQ_VAL [12:1] |
| |
| #define SSP_CR_LANEX_DIG_RX_CDR_CTL 0x901B |
| #define SSP_CR_LANEX_DIG_RX_CDR_CTL_rst 0b0000000000001111 |
| #define SSP_CR_LANEX_DIG_RX_CDR_CTL_size 16 |
| #define SSP_CR_LANEX_DIG_RX_CDR_CTL_PHDET_EN [1:0] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CTL_PHDET_EDGE [3:2] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CTL_PHDET_POL [4:4] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CTL_OVRD_DPLL_GAIN [5:5] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CTL_PHUG_VALUE [7:6] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CTL_FRUG_VALUE [9:8] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CTL_FAST_START [10:10] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CTL_ALWAYS_REALIGN [11:11] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CTL_DTB_SEL [15:12] |
| |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG 0x901C |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_rst 0b0000000000000000 |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_size 16 |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_adap_rx_eq [15:13] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_rx_eq_ctr [12:10] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_rx_ana_eq [9:7] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_adap_rx_valid [6:6] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en_adap [5:5] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en_eq [4:4] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_aligned [3:3] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_rx_valid [2:2] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_timeout [1:1] |
| #define SSP_CR_LANEX_DIG_RX_CDR_CDR_FSM_DEBUG_cdr_en [0:0] |
| |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_OVRD 0x901D |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_OVRD_rst 0b1000000000000000 |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_OVRD_size 16 |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_OVRD_adap_ctr_level [15:11] |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_OVRD_adap_polarity [10:10] |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector_ovrd [9:9] |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector_en [8:8] |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_OVRD_lock_vector [7:0] |
| |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC 0x901E |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_rst 12'b000000000000 |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_size 12 |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_eq_rx_eq [11:9] |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_eq_locked_vector_en [8:8] |
| #define SSP_CR_LANEX_DIG_RX_CDR_LOCK_VEC_eq_locked_vector [7:0] |
| |
| #define SSP_CR_LANEX_DIG_RX_CDR_ADAP_FSM 0x901F |
| #define SSP_CR_LANEX_DIG_RX_CDR_ADAP_FSM_rst 0b0000000000000000 |
| #define SSP_CR_LANEX_DIG_RX_CDR_ADAP_FSM_size 16 |
| #define SSP_CR_LANEX_DIG_RX_CDR_ADAP_FSM_mstr_ctr [15:11] |
| #define SSP_CR_LANEX_DIG_RX_CDR_ADAP_FSM_loop_ctr [10:7] |
| #define SSP_CR_LANEX_DIG_RX_CDR_ADAP_FSM_adap_ctr [6:3] |
| #define SSP_CR_LANEX_DIG_RX_CDR_ADAP_FSM_adap_state [2:0] |
| |
| #define SSP_CR_LANEX_ANA_RX_ATB0 0x9020 |
| #define SSP_CR_LANEX_ANA_RX_ATB0_rst 8'b00000000 |
| #define SSP_CR_LANEX_ANA_RX_ATB0_size 8 |
| #define SSP_CR_LANEX_ANA_RX_ATB0_EN_ATB_VOFF [0:0] |
| #define SSP_CR_LANEX_ANA_RX_ATB0_EN_ATB_VOS [1:1] |
| #define SSP_CR_LANEX_ANA_RX_ATB0_EN_ATB_RP_S [2:2] |
| #define SSP_CR_LANEX_ANA_RX_ATB0_EN_ATB_RP_F [3:3] |
| #define SSP_CR_LANEX_ANA_RX_ATB0_EN_ATB_RM_S [4:4] |
| #define SSP_CR_LANEX_ANA_RX_ATB0_EN_ATB_RM_F [5:5] |
| #define SSP_CR_LANEX_ANA_RX_ATB0_EN_MARG [6:6] |
| #define SSP_CR_LANEX_ANA_RX_ATB0_EN_ATB [7:7] |
| |
| #define SSP_CR_LANEX_ANA_RX_ATB1 0x9021 |
| #define SSP_CR_LANEX_ANA_RX_ATB1_rst 8'b00000000 |
| #define SSP_CR_LANEX_ANA_RX_ATB1_size 8 |
| #define SSP_CR_LANEX_ANA_RX_ATB1_RX_NC0 [0:0] |
| #define SSP_CR_LANEX_ANA_RX_ATB1_EN_VLOS_USB3 [1:1] |
| #define SSP_CR_LANEX_ANA_RX_ATB1_MEAS_VP [2:2] |
| #define SSP_CR_LANEX_ANA_RX_ATB1_MEAS_GD [3:3] |
| #define SSP_CR_LANEX_ANA_RX_ATB1_EN_ATB_VRF [4:4] |
| #define SSP_CR_LANEX_ANA_RX_ATB1_EN_ATB_VLOS [5:5] |
| #define SSP_CR_LANEX_ANA_RX_ATB1_VLOS_MIN [6:6] |
| #define SSP_CR_LANEX_ANA_RX_ATB1_VLOS_MAX [7:7] |
| |
| #define SSP_CR_LANEX_ANA_RX_ENPWR0 0x9022 |
| #define SSP_CR_LANEX_ANA_RX_ENPWR0_rst 8'b00000000 |
| #define SSP_CR_LANEX_ANA_RX_ENPWR0_size 8 |
| #define SSP_CR_LANEX_ANA_RX_ENPWR0_LCL_ACJT [0:0] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR0_CTL_ACJT [1:1] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR0_LCL_RXCK [2:2] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR0_CTL_RXCK [3:3] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR0_LCL_EN_LOS [4:4] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR0_CTL_EN_LOS [5:5] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR0_LCL_RXPWRON [6:6] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR0_CTL_RXPWRON [7:7] |
| |
| #define SSP_CR_LANEX_ANA_RX_PMIX_PHASE 0x9023 |
| #define SSP_CR_LANEX_ANA_RX_PMIX_PHASE_rst 8'b00000000 |
| #define SSP_CR_LANEX_ANA_RX_PMIX_PHASE_size 8 |
| #define SSP_CR_LANEX_ANA_RX_PMIX_PHASE_PHASE [7:0] |
| |
| #define SSP_CR_LANEX_ANA_RX_ENPWR1 0x9024 |
| #define SSP_CR_LANEX_ANA_RX_ENPWR1_rst 8'b00000000 |
| #define SSP_CR_LANEX_ANA_RX_ENPWR1_size 8 |
| #define SSP_CR_LANEX_ANA_RX_ENPWR1_CTL_PHASE_REG_RST [7:7] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR1_LCL_PHASE_REG_RST [6:6] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR1_CTL_BST [5:5] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR1_LCL_BST [4:2] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR1_CTL_RXTERM [1:1] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR1_LCL_RXTERM [0:0] |
| |
| #define SSP_CR_LANEX_ANA_RX_ENPWR2 0x9025 |
| #define SSP_CR_LANEX_ANA_RX_ENPWR2_rst 8'b00000000 |
| #define SSP_CR_LANEX_ANA_RX_ENPWR2_size 8 |
| #define SSP_CR_LANEX_ANA_RX_ENPWR2_RX_SCOPE_ATB_0 [0:0] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR2_RX_SCOPE_ATB_1 [1:1] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR2_RX_SCOPE_ATB_2 [2:2] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR2_EN_RXPMIX_FRC_VPMIX [3:3] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR2_EN_RXPMIX_VOSC [4:4] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR2_EN_RXPMIX_VRX [5:5] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR2_EN_RXPMIX_VPMIX [6:6] |
| #define SSP_CR_LANEX_ANA_RX_ENPWR2_EN_RXPMIX_TST [7:7] |
| |
| #define SSP_CR_LANEX_ANA_RX_SCOPE 0x9026 |
| #define SSP_CR_LANEX_ANA_RX_SCOPE_rst 8'b00000000 |
| #define SSP_CR_LANEX_ANA_RX_SCOPE_size 8 |
| #define SSP_CR_LANEX_ANA_RX_SCOPE_RX_NC1 [2:0] |
| #define SSP_CR_LANEX_ANA_RX_SCOPE_RX_SCOPE_FDIV20 [3:3] |
| #define SSP_CR_LANEX_ANA_RX_SCOPE_RX_SCOPE_SLEW [4:4] |
| #define SSP_CR_LANEX_ANA_RX_SCOPE_RX_NC2 [7:5] |
| |
| #define SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL 0x902B |
| #define SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL_rst 8'b00000000 |
| #define SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL_size 8 |
| #define SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL_NOCONN_6 [0:0] |
| #define SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL_NOCONN_7 [1:1] |
| #define SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL_NOCONN_8 [2:2] |
| #define SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL_OVRD_VCM_HOLD [3:3] |
| #define SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL_VCM_HOLD_REG [4:4] |
| #define SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL_OVRD_PULL_UP [5:5] |
| #define SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL_PULL_UP_REG [6:6] |
| #define SSP_CR_LANEX_ANA_TX_TXDRV_CNTRL_PULL_DN_REG [7:7] |
| |
| #define SSP_CR_LANEX_ANA_TX_POWER_CTL 0x902C |
| #define SSP_CR_LANEX_ANA_TX_POWER_CTL_rst 8'b00000000 |
| #define SSP_CR_LANEX_ANA_TX_POWER_CTL_size 8 |
| #define SSP_CR_LANEX_ANA_TX_POWER_CTL_LFPS_high_priority [0:0] |
| #define SSP_CR_LANEX_ANA_TX_POWER_CTL_REFGEN_PDN_REG [1:1] |
| #define SSP_CR_LANEX_ANA_TX_POWER_CTL_TX_DIV_CLK_EN [2:2] |
| #define SSP_CR_LANEX_ANA_TX_POWER_CTL_REFGEN_EN_REG [3:3] |
| #define SSP_CR_LANEX_ANA_TX_POWER_CTL_DATA_EN_REG [4:4] |
| #define SSP_CR_LANEX_ANA_TX_POWER_CTL_CLK_EN_REG [5:5] |
| #define SSP_CR_LANEX_ANA_TX_POWER_CTL_SERIAL_EN_REG [6:6] |
| #define SSP_CR_LANEX_ANA_TX_POWER_CTL_OVRD_EN [7:7] |
| |
| #define SSP_CR_LANEX_ANA_TX_ALT_BLOCK 0x902D |
| #define SSP_CR_LANEX_ANA_TX_ALT_BLOCK_rst 8'b00000000 |
| #define SSP_CR_LANEX_ANA_TX_ALT_BLOCK_size 8 |
| #define SSP_CR_LANEX_ANA_TX_ALT_BLOCK_OVRD_ALT_BUS [0:0] |
| #define SSP_CR_LANEX_ANA_TX_ALT_BLOCK_ALT_OSC_VPHREG [1:1] |
| #define SSP_CR_LANEX_ANA_TX_ALT_BLOCK_ALT_OSC_VPH [2:2] |
| #define SSP_CR_LANEX_ANA_TX_ALT_BLOCK_ALT_OSC_VP [3:3] |
| #define SSP_CR_LANEX_ANA_TX_ALT_BLOCK_JTAG_DATA_REG [4:4] |
| #define SSP_CR_LANEX_ANA_TX_ALT_BLOCK_DRV_SOURCE_REG [6:5] |
| #define SSP_CR_LANEX_ANA_TX_ALT_BLOCK_EN_ALT_BUS [7:7] |
| |
| #define SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK 0x902E |
| #define SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK_rst 8'b00000000 |
| #define SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK_size 8 |
| #define SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK_select_pmix_clk [0:0] |
| #define SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK_NOCONN_01 [1:1] |
| #define SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK_ATB_VDCCM [2:2] |
| #define SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK_ATB_VDCCP [3:3] |
| #define SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK_ATB_VREG_TX [4:4] |
| #define SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK_ATB_VPTX [5:5] |
| #define SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK_TX_LB_EN_REG [6:6] |
| #define SSP_CR_LANEX_ANA_TX_ALT_AND_LOOPBACK_OVRD_TX_LB [7:7] |
| |
| #define SSP_CR_LANEX_ANA_TX_TX_ATB_REG 0x902F |
| #define SSP_CR_LANEX_ANA_TX_TX_ATB_REG_rst 8'b00000000 |
| #define SSP_CR_LANEX_ANA_TX_TX_ATB_REG_size 8 |
| #define SSP_CR_LANEX_ANA_TX_TX_ATB_REG_ATB_VCM [0:0] |
| #define SSP_CR_LANEX_ANA_TX_TX_ATB_REG_ATB_TXSM [1:1] |
| #define SSP_CR_LANEX_ANA_TX_TX_ATB_REG_ATB_TXSP [2:2] |
| #define SSP_CR_LANEX_ANA_TX_TX_ATB_REG_ATB_TXFM [3:3] |
| #define SSP_CR_LANEX_ANA_TX_TX_ATB_REG_ATB_TXFP [4:4] |
| #define SSP_CR_LANEX_ANA_TX_TX_ATB_REG_ATB_RXDETREF [5:5] |
| #define SSP_CR_LANEX_ANA_TX_TX_ATB_REG_ATB_VCM_REP [6:6] |
| #define SSP_CR_LANEX_ANA_TX_TX_ATB_REG_ATB_PBIAS [7:7] |
| |
| #define HSP0_RO_ADDR0 0x2000 |
| // FIELD: ClkUsable_common [3] // pll_lock |
| // FIELD: Squelch_DisN_inv [2] // Squelch Signal |
| |
| #define HSP0_RO_ADDR1 0x2001 |
| // FIELD: vbus_valid_pu_ps [3] // VBUS Valid Comparator Power-Up |
| // FIELD: otg_pu_ps [2] // OTG Power-Up |
| // FIELD: tx_vref_vreg_pu_ps [1] // Tx Voltage Regulator Power-Up |
| // FIELD: sqrx_pu_ps [0] // Squelch/Rx Power-Up |
| |
| #define HSP0_RO_ADDR2 0x2002 |
| // FIELD: comp_pu_ps [3] // Disconnect/Tune Comparator Power-Up |
| // FIELD: bias_pu_ps [2] // Bias Power-Up |
| // FIELD: pll_pu_ps [1] // PLL Power-Up |
| // FIELD: xo_pu_ps [0] // XO Power-Up |
| |
| #define HSP0_RO_ADDR3 0x2003 |
| // FIELD: TxValid [2] // UTMI+ Input, TXVALID |
| // FIELD: TxValidH [1] // UTMI+ Input, TXVALIDH |
| // FIELD: TxReady [0] // UTMI+ Output, TXREADY |
| |
| |
| #define HSP0_RO_ADDR4 0x2004 |
| // FIELD: RxActive [3] // UTMI+ Output, RXACTIVE |
| // FIELD: RxValid [2] // UTMI+ Output, RXVALID |
| // FIELD: RxValidH [1] // UTMI+ Output, RXVALIDH |
| // FIELD: RxError [0] // UTMI+ Output, RXERROR |
| |
| #define HSP0_RO_ADDR5 0x2005 |
| // FIELD: DataOut [3:0] // UTMI+ Output, DATAOUT[3:0] |
| |
| #define HSP0_RO_ADDR6 0x2005 |
| // FIELD: tx_sliver_en_ct [3:0] // Tx Parallel Resistance Circuit[3:0] |
| |
| #define HSP0_RO_ADDR7 0x2007 |
| // FIELD: DataIn_bi [3:0] // UTMI+ Input, DATAIN[3:0] |
| |
| #define HSP0_RO_ADDR8 0x2008 |
| // FIELD: DMinus [3] // Single-Ended Rx DÂ Output |
| // FIELD: DPlus [2] // Single-Ended Rx D+ Output |
| // FIELD: HSDataIn_out [1] // HS Differential Rx Data |
| // FIELD: FSDataIn [0] // FS Differential Rx Data |
| |
| #define HSP0_RO_ADDR9 0x2009 |
| // FIELD: tx_short [2] // HS Tx Short Detect |
| // FIELD: bist_done_int [1] // BIST Done |
| // FIELD: bistError_int [0] // BIST Error |
| |
| #define HSP0_RO_ADDR10 0x200A |
| // FIELD: dataRec_rcv_enDebug [3] // DLL Receive Enable |
| // FIELD: recDataValidDebug [2:1] // DLL Data Valid for Recovered Data [1:0] |
| // FIELD: recDataDebug[4][0] // DLL Recovered Data, Bit 4 |
| |
| #define HSP0_RO_ADDR11 0x200B |
| // FIELD: comp_dis_latch_enb [2] // Disconnect/Tune Comparator Latch Enable |
| // FIELD: comp_dis [1] // Disconnect/Tune Comparator Output |
| // FIELD: ClkUsable_common [0] // pll_lock |
| |
| #define HSP0_RO_ADDR12 0x200C |
| // FIELD: underOverDebug [3] // Elasticity Buffer Underrun/Overrun |
| // FIELD: receive_start [2] // Rx SYNC Detected |
| |
| #define HSP0_RO_ADDR13 0x200D |
| // FIELD: tap_val [3:0] // Tap value, Bit[3:0] |
| |
| #define HSP0_RO_ADDR14 0x200E |
| // FIELD: dirToChangeDebug [3] // dirToChangeDebug |
| // FIELD: changeEnDebug [2] // changeEnDebug |
| // FIELD: ldTransIndDebug [1] // ldTransIndDebug |
| // FIELD: squelchDebug [0] // DLL Squelch Signal |
| |
| #define HSP0_RO_ADDR15 0x200F |
| // FIELD: recDataDebug [3:0] // DLL Recovered Data, Bit[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR00 0x2010 |
| #define HSP0_RW_ADDR0 0x2010 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: overrd_addr [3:0] // Analog Test Control Override Address[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR01 0x2011 |
| #define HSP0_RW_ADDR1 0x2011 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: vbus_valid_pu_tm [3] // VBUS Valid Comparator Power-Up Override |
| // FIELD: otg_pu_tm [2] // OTG Power-Up Override |
| // FIELD: tx_vref_vreg_pu_tm [1] // Tx Voltage Regulator Power-Up Override |
| // FIELD: sqrx_pu_tm [0] // Squelch/Rx Power-Up Override |
| |
| //#define ATE_HSP_TI_RW_ADDR02 0x2012 |
| #define HSP0_RW_ADDR2 0x2012 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: comp_pu_tm [3] // Disconnect/Tune Comparator Power-Up Override |
| // FIELD: bias_pu_tm [2] // Bias Power-Up Override |
| // FIELD: pll_pu_tm [1] // PLL Power-Up Override |
| // FIELD: xo_pu_tm [0] // XO Power-Up Override |
| |
| //#define ATE_HSP_TI_RW_ADDR03 0x2013 |
| #define HSP0_RW_ADDR3 0x2013 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: XO_always_on [2] // XO_Always_On |
| // FIELD: serclk_rx_enb_tm [1] // Rx Clock Gating Enable |
| // FIELD: serclk_tx_enb_tm [0] // Tx Clock Gating Enable |
| |
| //#define ATE_HSP_TI_RW_ADDR04 0x2014 |
| #define HSP0_RW_ADDR4 0x2014 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: LoopbackEnb_int [3] // Loopback Enabled |
| // FIELD: VDPU_EN2 [1] // D+ Pull-Up Override 2 |
| // FIELD: VDPU_EN1 [0] // D+ Pull-up Override 1 |
| |
| //#define ATE_HSP_TI_RW_ADDR05 0x2015 |
| #define HSP0_RW_ADDR5 0x2015 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: xo_clk_div_tm [3:2] // Reference Clock Divider Select [1:0] |
| // FIELD: mstr_overrd_bit [2] // Analog Test Control Master Override Bit |
| // FIELD: overrd_addr[4][1] // Analog Test Control Override Address[4] |
| |
| //#define ATE_HSP_TI_RW_ADDR06 0x2016 |
| #define HSP0_RW_ADDR6 0x2016 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tx_sliver_en [3:0] // Tx Parallel Resistance Circuit[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR07 0x2017 |
| #define HSP0_RW_ADDR7 0x2017 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tx_ls_en [3] // LS Tx Enable |
| |
| //#define ATE_HSP_TI_RW_ADDR08 0x2018 |
| #define HSP0_RW_ADDR8 0x2018 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: bistEn [3] // BIST Enable |
| // FIELD: hs_bist [2] // HS BIST |
| // FIELD: fs_bist [1] // FS BIST |
| // FIELD: ls_bist [0] // LS BIST |
| |
| //#define ATE_HSP_TI_RW_ADDR09 0x2019 |
| #define HSP0_RW_ADDR9 0x2019 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: inst_bist_err [3] // Insert BIST error |
| // FIELD: dm_pulldown_en [1] // D-Â Pull-Down Override |
| // FIELD: dp_pulldown_en [0] // D+ Pull-Down Override |
| |
| //#define ATE_HSP_TI_RW_ADDR10 0x201A |
| #define HSP0_RW_ADDR10 0x201A |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: fs_assert_se0 [2] // FS/LS Tx Assert SE0 |
| // FIELD: fs_output_enb [1] // FS/LS Transmit Output Enable |
| // FIELD: fs_dataout [0] // FS/LS Transmit Data |
| |
| //#define ATE_HSP_TI_RW_ADDR11 0x201B |
| #define HSP0_RW_ADDR11 0x201B |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: res_req_in_tm [3] // Resistor Request Override |
| // FIELD: incr_tune_dis_tm [2] // Disable Incremental Tune |
| // FIELD: comp_sel_analog [1] // Disconnect/Tune Block Comparator Test Mode |
| |
| //#define ATE_HSP_TI_RW_ADDR12 0x201C |
| #define HSP0_RW_ADDR12 0x201C |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: res_ack_out [3] // Resistor Acknowledge Override |
| // FIELD: pll_clk_div_tm [1:0] // PLL Clock Divider[1:0] |
| // FIELD: pll_reset [1] // PLL Reset |
| |
| //#define ATE_HSP_TI_RW_ADDR13 0x201D |
| #define HSP0_RW_ADDR13 0x201D |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: bist_mode_tm [3] // BIST Mode |
| // FIELD: test_pkt_rpt [2] // BIST Test Packet Repeat |
| // FIELD: xo_clk_sel_tm [1:0] // REFCLKSEL[1:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR14 0x201E |
| #define HSP0_RW_ADDR14 0x201E |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tap_sel_ovrd_tm [3] // TAP Select Override |
| // FIELD: tap_shift_enb_tm [2] // TAP Shift Enable |
| // FIELD: tap_shift_dir_tm [1] // TAP Shift Direction |
| // FIELD: Squelch_DisN_async [0] // Squelch Signal |
| |
| //#define ATE_HSP_TI_RW_ADDR15 0x201F |
| #define HSP0_RW_ADDR15 0x201F |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: ClkUsable_tm [3] // Override for Transceiver ClkUsable |
| // FIELD: scale_down_mode [2] // Scale-Down Enable for Disconnect Timers |
| // FIELD: pll_lock_tm [1] // PLL Force Lock |
| #define HSP1_RO_ADDR0 0x2100 |
| // FIELD: ClkUsable_common [3] // pll_lock |
| // FIELD: Squelch_DisN_inv [2] // Squelch Signal |
| |
| #define HSP1_RO_ADDR1 0x2101 |
| // FIELD: vbus_valid_pu_ps [3] // VBUS Valid Comparator Power-Up |
| // FIELD: otg_pu_ps [2] // OTG Power-Up |
| // FIELD: tx_vref_vreg_pu_ps [1] // Tx Voltage Regulator Power-Up |
| // FIELD: sqrx_pu_ps [0] // Squelch/Rx Power-Up |
| |
| #define HSP1_RO_ADDR2 0x2102 |
| // FIELD: comp_pu_ps [3] // Disconnect/Tune Comparator Power-Up |
| // FIELD: bias_pu_ps [2] // Bias Power-Up |
| // FIELD: pll_pu_ps [1] // PLL Power-Up |
| // FIELD: xo_pu_ps [0] // XO Power-Up |
| |
| #define HSP1_RO_ADDR3 0x2103 |
| // FIELD: TxValid [2] // UTMI+ Input, TXVALID |
| // FIELD: TxValidH [1] // UTMI+ Input, TXVALIDH |
| // FIELD: TxReady [0] // UTMI+ Output, TXREADY |
| |
| |
| #define HSP1_RO_ADDR4 0x2104 |
| // FIELD: RxActive [3] // UTMI+ Output, RXACTIVE |
| // FIELD: RxValid [2] // UTMI+ Output, RXVALID |
| // FIELD: RxValidH [1] // UTMI+ Output, RXVALIDH |
| // FIELD: RxError [0] // UTMI+ Output, RXERROR |
| |
| #define HSP1_RO_ADDR5 0x2105 |
| // FIELD: DataOut [3:0] // UTMI+ Output, DATAOUT[3:0] |
| |
| #define HSP1_RO_ADDR6 0x2105 |
| // FIELD: tx_sliver_en_ct [3:0] // Tx Parallel Resistance Circuit[3:0] |
| |
| #define HSP1_RO_ADDR7 0x2107 |
| // FIELD: DataIn_bi [3:0] // UTMI+ Input, DATAIN[3:0] |
| |
| #define HSP1_RO_ADDR8 0x2108 |
| // FIELD: DMinus [3] // Single-Ended Rx DÂ Output |
| // FIELD: DPlus [2] // Single-Ended Rx D+ Output |
| // FIELD: HSDataIn_out [1] // HS Differential Rx Data |
| // FIELD: FSDataIn [0] // FS Differential Rx Data |
| |
| #define HSP1_RO_ADDR9 0x2109 |
| // FIELD: tx_short [2] // HS Tx Short Detect |
| // FIELD: bist_done_int [1] // BIST Done |
| // FIELD: bistError_int [0] // BIST Error |
| |
| #define HSP1_RO_ADDR10 0x210A |
| // FIELD: dataRec_rcv_enDebug [3] // DLL Receive Enable |
| // FIELD: recDataValidDebug [2:1] // DLL Data Valid for Recovered Data [1:0] |
| // FIELD: recDataDebug[4][0] // DLL Recovered Data, Bit 4 |
| |
| #define HSP1_RO_ADDR11 0x210B |
| // FIELD: comp_dis_latch_enb [2] // Disconnect/Tune Comparator Latch Enable |
| // FIELD: comp_dis [1] // Disconnect/Tune Comparator Output |
| // FIELD: ClkUsable_common [0] // pll_lock |
| |
| #define HSP1_RO_ADDR12 0x210C |
| // FIELD: underOverDebug [3] // Elasticity Buffer Underrun/Overrun |
| // FIELD: receive_start [2] // Rx SYNC Detected |
| |
| #define HSP1_RO_ADDR13 0x210D |
| // FIELD: tap_val [3:0] // Tap value, Bit[3:0] |
| |
| #define HSP1_RO_ADDR14 0x210E |
| // FIELD: dirToChangeDebug [3] // dirToChangeDebug |
| // FIELD: changeEnDebug [2] // changeEnDebug |
| // FIELD: ldTransIndDebug [1] // ldTransIndDebug |
| // FIELD: squelchDebug [0] // DLL Squelch Signal |
| |
| #define HSP1_RO_ADDR15 0x210F |
| // FIELD: recDataDebug [3:0] // DLL Recovered Data, Bit[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR00 0x2010 |
| #define HSP1_RW_ADDR0 0x2110 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: overrd_addr [3:0] // Analog Test Control Override Address[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR01 0x2011 |
| #define HSP1_RW_ADDR1 0x2111 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: vbus_valid_pu_tm [3] // VBUS Valid Comparator Power-Up Override |
| // FIELD: otg_pu_tm [2] // OTG Power-Up Override |
| // FIELD: tx_vref_vreg_pu_tm [1] // Tx Voltage Regulator Power-Up Override |
| // FIELD: sqrx_pu_tm [0] // Squelch/Rx Power-Up Override |
| |
| //#define ATE_HSP_TI_RW_ADDR02 0x2012 |
| #define HSP1_RW_ADDR2 0x2112 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: comp_pu_tm [3] // Disconnect/Tune Comparator Power-Up Override |
| // FIELD: bias_pu_tm [2] // Bias Power-Up Override |
| // FIELD: pll_pu_tm [1] // PLL Power-Up Override |
| // FIELD: xo_pu_tm [0] // XO Power-Up Override |
| |
| //#define ATE_HSP_TI_RW_ADDR03 0x2013 |
| #define HSP1_RW_ADDR3 0x2113 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: XO_always_on [2] // XO_Always_On |
| // FIELD: serclk_rx_enb_tm [1] // Rx Clock Gating Enable |
| // FIELD: serclk_tx_enb_tm [0] // Tx Clock Gating Enable |
| |
| //#define ATE_HSP_TI_RW_ADDR04 0x2014 |
| #define HSP1_RW_ADDR4 0x2114 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: LoopbackEnb_int [3] // Loopback Enabled |
| // FIELD: VDPU_EN2 [1] // D+ Pull-Up Override 2 |
| // FIELD: VDPU_EN1 [0] // D+ Pull-up Override 1 |
| |
| //#define ATE_HSP_TI_RW_ADDR05 0x2015 |
| #define HSP1_RW_ADDR5 0x2115 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: xo_clk_div_tm [3:2] // Reference Clock Divider Select [1:0] |
| // FIELD: mstr_overrd_bit [2] // Analog Test Control Master Override Bit |
| // FIELD: overrd_addr[4][1] // Analog Test Control Override Address[4] |
| |
| //#define ATE_HSP_TI_RW_ADDR06 0x2016 |
| #define HSP1_RW_ADDR6 0x2116 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tx_sliver_en [3:0] // Tx Parallel Resistance Circuit[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR07 0x2017 |
| #define HSP1_RW_ADDR7 0x2117 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tx_ls_en [3] // LS Tx Enable |
| |
| //#define ATE_HSP_TI_RW_ADDR08 0x2018 |
| #define HSP1_RW_ADDR8 0x2118 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: bistEn [3] // BIST Enable |
| // FIELD: hs_bist [2] // HS BIST |
| // FIELD: fs_bist [1] // FS BIST |
| // FIELD: ls_bist [0] // LS BIST |
| |
| //#define ATE_HSP_TI_RW_ADDR09 0x2019 |
| #define HSP1_RW_ADDR9 0x2119 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: inst_bist_err [3] // Insert BIST error |
| // FIELD: dm_pulldown_en [1] // D-Â Pull-Down Override |
| // FIELD: dp_pulldown_en [0] // D+ Pull-Down Override |
| |
| //#define ATE_HSP_TI_RW_ADDR10 0x201A |
| #define HSP1_RW_ADDR10 0x211A |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: fs_assert_se0 [2] // FS/LS Tx Assert SE0 |
| // FIELD: fs_output_enb [1] // FS/LS Transmit Output Enable |
| // FIELD: fs_dataout [0] // FS/LS Transmit Data |
| |
| //#define ATE_HSP_TI_RW_ADDR11 0x201B |
| #define HSP1_RW_ADDR11 0x211B |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: res_req_in_tm [3] // Resistor Request Override |
| // FIELD: incr_tune_dis_tm [2] // Disable Incremental Tune |
| // FIELD: comp_sel_analog [1] // Disconnect/Tune Block Comparator Test Mode |
| |
| //#define ATE_HSP_TI_RW_ADDR12 0x201C |
| #define HSP1_RW_ADDR12 0x211C |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: res_ack_out [3] // Resistor Acknowledge Override |
| // FIELD: pll_clk_div_tm [1:0] // PLL Clock Divider[1:0] |
| // FIELD: pll_reset [1] // PLL Reset |
| |
| //#define ATE_HSP_TI_RW_ADDR13 0x201D |
| #define HSP1_RW_ADDR13 0x211D |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: bist_mode_tm [3] // BIST Mode |
| // FIELD: test_pkt_rpt [2] // BIST Test Packet Repeat |
| // FIELD: xo_clk_sel_tm [1:0] // REFCLKSEL[1:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR14 0x201E |
| #define HSP1_RW_ADDR14 0x211E |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tap_sel_ovrd_tm [3] // TAP Select Override |
| // FIELD: tap_shift_enb_tm [2] // TAP Shift Enable |
| // FIELD: tap_shift_dir_tm [1] // TAP Shift Direction |
| // FIELD: Squelch_DisN_async [0] // Squelch Signal |
| |
| //#define ATE_HSP_TI_RW_ADDR15 0x201F |
| #define HSP1_RW_ADDR15 0x211F |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: ClkUsable_tm [3] // Override for Transceiver ClkUsable |
| // FIELD: scale_down_mode [2] // Scale-Down Enable for Disconnect Timers |
| // FIELD: pll_lock_tm [1] // PLL Force Lock |
| #define HSP2_RO_ADDR0 0x2200 |
| // FIELD: ClkUsable_common [3] // pll_lock |
| // FIELD: Squelch_DisN_inv [2] // Squelch Signal |
| |
| #define HSP2_RO_ADDR1 0x2201 |
| // FIELD: vbus_valid_pu_ps [3] // VBUS Valid Comparator Power-Up |
| // FIELD: otg_pu_ps [2] // OTG Power-Up |
| // FIELD: tx_vref_vreg_pu_ps [1] // Tx Voltage Regulator Power-Up |
| // FIELD: sqrx_pu_ps [0] // Squelch/Rx Power-Up |
| |
| #define HSP2_RO_ADDR2 0x2202 |
| // FIELD: comp_pu_ps [3] // Disconnect/Tune Comparator Power-Up |
| // FIELD: bias_pu_ps [2] // Bias Power-Up |
| // FIELD: pll_pu_ps [1] // PLL Power-Up |
| // FIELD: xo_pu_ps [0] // XO Power-Up |
| |
| #define HSP2_RO_ADDR3 0x2203 |
| // FIELD: TxValid [2] // UTMI+ Input, TXVALID |
| // FIELD: TxValidH [1] // UTMI+ Input, TXVALIDH |
| // FIELD: TxReady [0] // UTMI+ Output, TXREADY |
| |
| |
| #define HSP2_RO_ADDR4 0x2204 |
| // FIELD: RxActive [3] // UTMI+ Output, RXACTIVE |
| // FIELD: RxValid [2] // UTMI+ Output, RXVALID |
| // FIELD: RxValidH [1] // UTMI+ Output, RXVALIDH |
| // FIELD: RxError [0] // UTMI+ Output, RXERROR |
| |
| #define HSP2_RO_ADDR5 0x2205 |
| // FIELD: DataOut [3:0] // UTMI+ Output, DATAOUT[3:0] |
| |
| #define HSP2_RO_ADDR6 0x2205 |
| // FIELD: tx_sliver_en_ct [3:0] // Tx Parallel Resistance Circuit[3:0] |
| |
| #define HSP2_RO_ADDR7 0x2207 |
| // FIELD: DataIn_bi [3:0] // UTMI+ Input, DATAIN[3:0] |
| |
| #define HSP2_RO_ADDR8 0x2208 |
| // FIELD: DMinus [3] // Single-Ended Rx DÂ Output |
| // FIELD: DPlus [2] // Single-Ended Rx D+ Output |
| // FIELD: HSDataIn_out [1] // HS Differential Rx Data |
| // FIELD: FSDataIn [0] // FS Differential Rx Data |
| |
| #define HSP2_RO_ADDR9 0x2209 |
| // FIELD: tx_short [2] // HS Tx Short Detect |
| // FIELD: bist_done_int [1] // BIST Done |
| // FIELD: bistError_int [0] // BIST Error |
| |
| #define HSP2_RO_ADDR10 0x220A |
| // FIELD: dataRec_rcv_enDebug [3] // DLL Receive Enable |
| // FIELD: recDataValidDebug [2:1] // DLL Data Valid for Recovered Data [1:0] |
| // FIELD: recDataDebug[4][0] // DLL Recovered Data, Bit 4 |
| |
| #define HSP2_RO_ADDR11 0x220B |
| // FIELD: comp_dis_latch_enb [2] // Disconnect/Tune Comparator Latch Enable |
| // FIELD: comp_dis [1] // Disconnect/Tune Comparator Output |
| // FIELD: ClkUsable_common [0] // pll_lock |
| |
| #define HSP2_RO_ADDR12 0x220C |
| // FIELD: underOverDebug [3] // Elasticity Buffer Underrun/Overrun |
| // FIELD: receive_start [2] // Rx SYNC Detected |
| |
| #define HSP2_RO_ADDR13 0x220D |
| // FIELD: tap_val [3:0] // Tap value, Bit[3:0] |
| |
| #define HSP2_RO_ADDR14 0x220E |
| // FIELD: dirToChangeDebug [3] // dirToChangeDebug |
| // FIELD: changeEnDebug [2] // changeEnDebug |
| // FIELD: ldTransIndDebug [1] // ldTransIndDebug |
| // FIELD: squelchDebug [0] // DLL Squelch Signal |
| |
| #define HSP2_RO_ADDR15 0x220F |
| // FIELD: recDataDebug [3:0] // DLL Recovered Data, Bit[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR00 0x2010 |
| #define HSP2_RW_ADDR0 0x2210 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: overrd_addr [3:0] // Analog Test Control Override Address[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR01 0x2011 |
| #define HSP2_RW_ADDR1 0x2211 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: vbus_valid_pu_tm [3] // VBUS Valid Comparator Power-Up Override |
| // FIELD: otg_pu_tm [2] // OTG Power-Up Override |
| // FIELD: tx_vref_vreg_pu_tm [1] // Tx Voltage Regulator Power-Up Override |
| // FIELD: sqrx_pu_tm [0] // Squelch/Rx Power-Up Override |
| |
| //#define ATE_HSP_TI_RW_ADDR02 0x2012 |
| #define HSP2_RW_ADDR2 0x2212 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: comp_pu_tm [3] // Disconnect/Tune Comparator Power-Up Override |
| // FIELD: bias_pu_tm [2] // Bias Power-Up Override |
| // FIELD: pll_pu_tm [1] // PLL Power-Up Override |
| // FIELD: xo_pu_tm [0] // XO Power-Up Override |
| |
| //#define ATE_HSP_TI_RW_ADDR03 0x2013 |
| #define HSP2_RW_ADDR3 0x2213 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: XO_always_on [2] // XO_Always_On |
| // FIELD: serclk_rx_enb_tm [1] // Rx Clock Gating Enable |
| // FIELD: serclk_tx_enb_tm [0] // Tx Clock Gating Enable |
| |
| //#define ATE_HSP_TI_RW_ADDR04 0x2014 |
| #define HSP2_RW_ADDR4 0x2214 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: LoopbackEnb_int [3] // Loopback Enabled |
| // FIELD: VDPU_EN2 [1] // D+ Pull-Up Override 2 |
| // FIELD: VDPU_EN1 [0] // D+ Pull-up Override 1 |
| |
| //#define ATE_HSP_TI_RW_ADDR05 0x2015 |
| #define HSP2_RW_ADDR5 0x2215 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: xo_clk_div_tm [3:2] // Reference Clock Divider Select [1:0] |
| // FIELD: mstr_overrd_bit [2] // Analog Test Control Master Override Bit |
| // FIELD: overrd_addr[4][1] // Analog Test Control Override Address[4] |
| |
| //#define ATE_HSP_TI_RW_ADDR06 0x2016 |
| #define HSP2_RW_ADDR6 0x2216 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tx_sliver_en [3:0] // Tx Parallel Resistance Circuit[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR07 0x2017 |
| #define HSP2_RW_ADDR7 0x2217 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tx_ls_en [3] // LS Tx Enable |
| |
| //#define ATE_HSP_TI_RW_ADDR08 0x2018 |
| #define HSP2_RW_ADDR8 0x2218 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: bistEn [3] // BIST Enable |
| // FIELD: hs_bist [2] // HS BIST |
| // FIELD: fs_bist [1] // FS BIST |
| // FIELD: ls_bist [0] // LS BIST |
| |
| //#define ATE_HSP_TI_RW_ADDR09 0x2019 |
| #define HSP2_RW_ADDR9 0x2219 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: inst_bist_err [3] // Insert BIST error |
| // FIELD: dm_pulldown_en [1] // D-Â Pull-Down Override |
| // FIELD: dp_pulldown_en [0] // D+ Pull-Down Override |
| |
| //#define ATE_HSP_TI_RW_ADDR10 0x201A |
| #define HSP2_RW_ADDR10 0x221A |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: fs_assert_se0 [2] // FS/LS Tx Assert SE0 |
| // FIELD: fs_output_enb [1] // FS/LS Transmit Output Enable |
| // FIELD: fs_dataout [0] // FS/LS Transmit Data |
| |
| //#define ATE_HSP_TI_RW_ADDR11 0x201B |
| #define HSP2_RW_ADDR11 0x221B |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: res_req_in_tm [3] // Resistor Request Override |
| // FIELD: incr_tune_dis_tm [2] // Disable Incremental Tune |
| // FIELD: comp_sel_analog [1] // Disconnect/Tune Block Comparator Test Mode |
| |
| //#define ATE_HSP_TI_RW_ADDR12 0x201C |
| #define HSP2_RW_ADDR12 0x221C |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: res_ack_out [3] // Resistor Acknowledge Override |
| // FIELD: pll_clk_div_tm [1:0] // PLL Clock Divider[1:0] |
| // FIELD: pll_reset [1] // PLL Reset |
| |
| //#define ATE_HSP_TI_RW_ADDR13 0x201D |
| #define HSP2_RW_ADDR13 0x221D |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: bist_mode_tm [3] // BIST Mode |
| // FIELD: test_pkt_rpt [2] // BIST Test Packet Repeat |
| // FIELD: xo_clk_sel_tm [1:0] // REFCLKSEL[1:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR14 0x201E |
| #define HSP2_RW_ADDR14 0x221E |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tap_sel_ovrd_tm [3] // TAP Select Override |
| // FIELD: tap_shift_enb_tm [2] // TAP Shift Enable |
| // FIELD: tap_shift_dir_tm [1] // TAP Shift Direction |
| // FIELD: Squelch_DisN_async [0] // Squelch Signal |
| |
| //#define ATE_HSP_TI_RW_ADDR15 0x201F |
| #define HSP2_RW_ADDR15 0x221F |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: ClkUsable_tm [3] // Override for Transceiver ClkUsable |
| // FIELD: scale_down_mode [2] // Scale-Down Enable for Disconnect Timers |
| // FIELD: pll_lock_tm [1] // PLL Force Lock |
| #define HSP3_RO_ADDR0 0x2300 |
| // FIELD: ClkUsable_common [3] // pll_lock |
| // FIELD: Squelch_DisN_inv [2] // Squelch Signal |
| |
| #define HSP3_RO_ADDR1 0x2301 |
| // FIELD: vbus_valid_pu_ps [3] // VBUS Valid Comparator Power-Up |
| // FIELD: otg_pu_ps [2] // OTG Power-Up |
| // FIELD: tx_vref_vreg_pu_ps [1] // Tx Voltage Regulator Power-Up |
| // FIELD: sqrx_pu_ps [0] // Squelch/Rx Power-Up |
| |
| #define HSP3_RO_ADDR2 0x2302 |
| // FIELD: comp_pu_ps [3] // Disconnect/Tune Comparator Power-Up |
| // FIELD: bias_pu_ps [2] // Bias Power-Up |
| // FIELD: pll_pu_ps [1] // PLL Power-Up |
| // FIELD: xo_pu_ps [0] // XO Power-Up |
| |
| #define HSP3_RO_ADDR3 0x2303 |
| // FIELD: TxValid [2] // UTMI+ Input, TXVALID |
| // FIELD: TxValidH [1] // UTMI+ Input, TXVALIDH |
| // FIELD: TxReady [0] // UTMI+ Output, TXREADY |
| |
| |
| #define HSP3_RO_ADDR4 0x2304 |
| // FIELD: RxActive [3] // UTMI+ Output, RXACTIVE |
| // FIELD: RxValid [2] // UTMI+ Output, RXVALID |
| // FIELD: RxValidH [1] // UTMI+ Output, RXVALIDH |
| // FIELD: RxError [0] // UTMI+ Output, RXERROR |
| |
| #define HSP3_RO_ADDR5 0x2305 |
| // FIELD: DataOut [3:0] // UTMI+ Output, DATAOUT[3:0] |
| |
| #define HSP3_RO_ADDR6 0x2305 |
| // FIELD: tx_sliver_en_ct [3:0] // Tx Parallel Resistance Circuit[3:0] |
| |
| #define HSP3_RO_ADDR7 0x2307 |
| // FIELD: DataIn_bi [3:0] // UTMI+ Input, DATAIN[3:0] |
| |
| #define HSP3_RO_ADDR8 0x2308 |
| // FIELD: DMinus [3] // Single-Ended Rx DÂ Output |
| // FIELD: DPlus [2] // Single-Ended Rx D+ Output |
| // FIELD: HSDataIn_out [1] // HS Differential Rx Data |
| // FIELD: FSDataIn [0] // FS Differential Rx Data |
| |
| #define HSP3_RO_ADDR9 0x2309 |
| // FIELD: tx_short [2] // HS Tx Short Detect |
| // FIELD: bist_done_int [1] // BIST Done |
| // FIELD: bistError_int [0] // BIST Error |
| |
| #define HSP3_RO_ADDR10 0x230A |
| // FIELD: dataRec_rcv_enDebug [3] // DLL Receive Enable |
| // FIELD: recDataValidDebug [2:1] // DLL Data Valid for Recovered Data [1:0] |
| // FIELD: recDataDebug[4][0] // DLL Recovered Data, Bit 4 |
| |
| #define HSP3_RO_ADDR11 0x230B |
| // FIELD: comp_dis_latch_enb [2] // Disconnect/Tune Comparator Latch Enable |
| // FIELD: comp_dis [1] // Disconnect/Tune Comparator Output |
| // FIELD: ClkUsable_common [0] // pll_lock |
| |
| #define HSP3_RO_ADDR12 0x230C |
| // FIELD: underOverDebug [3] // Elasticity Buffer Underrun/Overrun |
| // FIELD: receive_start [2] // Rx SYNC Detected |
| |
| #define HSP3_RO_ADDR13 0x230D |
| // FIELD: tap_val [3:0] // Tap value, Bit[3:0] |
| |
| #define HSP3_RO_ADDR14 0x230E |
| // FIELD: dirToChangeDebug [3] // dirToChangeDebug |
| // FIELD: changeEnDebug [2] // changeEnDebug |
| // FIELD: ldTransIndDebug [1] // ldTransIndDebug |
| // FIELD: squelchDebug [0] // DLL Squelch Signal |
| |
| #define HSP3_RO_ADDR15 0x230F |
| // FIELD: recDataDebug [3:0] // DLL Recovered Data, Bit[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR00 0x2010 |
| #define HSP3_RW_ADDR0 0x2310 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: overrd_addr [3:0] // Analog Test Control Override Address[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR01 0x2011 |
| #define HSP3_RW_ADDR1 0x2311 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: vbus_valid_pu_tm [3] // VBUS Valid Comparator Power-Up Override |
| // FIELD: otg_pu_tm [2] // OTG Power-Up Override |
| // FIELD: tx_vref_vreg_pu_tm [1] // Tx Voltage Regulator Power-Up Override |
| // FIELD: sqrx_pu_tm [0] // Squelch/Rx Power-Up Override |
| |
| //#define ATE_HSP_TI_RW_ADDR02 0x2012 |
| #define HSP3_RW_ADDR2 0x2312 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: comp_pu_tm [3] // Disconnect/Tune Comparator Power-Up Override |
| // FIELD: bias_pu_tm [2] // Bias Power-Up Override |
| // FIELD: pll_pu_tm [1] // PLL Power-Up Override |
| // FIELD: xo_pu_tm [0] // XO Power-Up Override |
| |
| //#define ATE_HSP_TI_RW_ADDR03 0x2013 |
| #define HSP3_RW_ADDR3 0x2313 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: XO_always_on [2] // XO_Always_On |
| // FIELD: serclk_rx_enb_tm [1] // Rx Clock Gating Enable |
| // FIELD: serclk_tx_enb_tm [0] // Tx Clock Gating Enable |
| |
| //#define ATE_HSP_TI_RW_ADDR04 0x2014 |
| #define HSP3_RW_ADDR4 0x2314 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: LoopbackEnb_int [3] // Loopback Enabled |
| // FIELD: VDPU_EN2 [1] // D+ Pull-Up Override 2 |
| // FIELD: VDPU_EN1 [0] // D+ Pull-up Override 1 |
| |
| //#define ATE_HSP_TI_RW_ADDR05 0x2015 |
| #define HSP3_RW_ADDR5 0x2315 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: xo_clk_div_tm [3:2] // Reference Clock Divider Select [1:0] |
| // FIELD: mstr_overrd_bit [2] // Analog Test Control Master Override Bit |
| // FIELD: overrd_addr[4][1] // Analog Test Control Override Address[4] |
| |
| //#define ATE_HSP_TI_RW_ADDR06 0x2016 |
| #define HSP3_RW_ADDR6 0x2316 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tx_sliver_en [3:0] // Tx Parallel Resistance Circuit[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR07 0x2017 |
| #define HSP3_RW_ADDR7 0x2317 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tx_ls_en [3] // LS Tx Enable |
| |
| //#define ATE_HSP_TI_RW_ADDR08 0x2018 |
| #define HSP3_RW_ADDR8 0x2318 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: bistEn [3] // BIST Enable |
| // FIELD: hs_bist [2] // HS BIST |
| // FIELD: fs_bist [1] // FS BIST |
| // FIELD: ls_bist [0] // LS BIST |
| |
| //#define ATE_HSP_TI_RW_ADDR09 0x2019 |
| #define HSP3_RW_ADDR9 0x2319 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: inst_bist_err [3] // Insert BIST error |
| // FIELD: dm_pulldown_en [1] // D-Â Pull-Down Override |
| // FIELD: dp_pulldown_en [0] // D+ Pull-Down Override |
| |
| //#define ATE_HSP_TI_RW_ADDR10 0x201A |
| #define HSP3_RW_ADDR10 0x231A |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: fs_assert_se0 [2] // FS/LS Tx Assert SE0 |
| // FIELD: fs_output_enb [1] // FS/LS Transmit Output Enable |
| // FIELD: fs_dataout [0] // FS/LS Transmit Data |
| |
| //#define ATE_HSP_TI_RW_ADDR11 0x201B |
| #define HSP3_RW_ADDR11 0x231B |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: res_req_in_tm [3] // Resistor Request Override |
| // FIELD: incr_tune_dis_tm [2] // Disable Incremental Tune |
| // FIELD: comp_sel_analog [1] // Disconnect/Tune Block Comparator Test Mode |
| |
| //#define ATE_HSP_TI_RW_ADDR12 0x201C |
| #define HSP3_RW_ADDR12 0x231C |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: res_ack_out [3] // Resistor Acknowledge Override |
| // FIELD: pll_clk_div_tm [1:0] // PLL Clock Divider[1:0] |
| // FIELD: pll_reset [1] // PLL Reset |
| |
| //#define ATE_HSP_TI_RW_ADDR13 0x201D |
| #define HSP3_RW_ADDR13 0x231D |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: bist_mode_tm [3] // BIST Mode |
| // FIELD: test_pkt_rpt [2] // BIST Test Packet Repeat |
| // FIELD: xo_clk_sel_tm [1:0] // REFCLKSEL[1:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR14 0x201E |
| #define HSP3_RW_ADDR14 0x231E |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tap_sel_ovrd_tm [3] // TAP Select Override |
| // FIELD: tap_shift_enb_tm [2] // TAP Shift Enable |
| // FIELD: tap_shift_dir_tm [1] // TAP Shift Direction |
| // FIELD: Squelch_DisN_async [0] // Squelch Signal |
| |
| //#define ATE_HSP_TI_RW_ADDR15 0x201F |
| #define HSP3_RW_ADDR15 0x231F |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: ClkUsable_tm [3] // Override for Transceiver ClkUsable |
| // FIELD: scale_down_mode [2] // Scale-Down Enable for Disconnect Timers |
| // FIELD: pll_lock_tm [1] // PLL Force Lock |
| //#define ATE_HSP_TI_RW_ADDR00 0xA010 |
| #define HSPX_RW_ADDR0 0xA110 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: overrd_addr [3:0] // Analog Test Control Override Address[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR01 0xA011 |
| #define HSPX_RW_ADDR1 0xA111 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: vbus_valid_pu_tm [3] // VBUS Valid Comparator Power-Up Override |
| // FIELD: otg_pu_tm [2] // OTG Power-Up Override |
| // FIELD: tx_vref_vreg_pu_tm [1] // Tx Voltage Regulator Power-Up Override |
| // FIELD: sqrx_pu_tm [0] // Squelch/Rx Power-Up Override |
| |
| //#define ATE_HSP_TI_RW_ADDR02 0xA012 |
| #define HSPX_RW_ADDR2 0xA112 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: comp_pu_tm [3] // Disconnect/Tune Comparator Power-Up Override |
| // FIELD: bias_pu_tm [2] // Bias Power-Up Override |
| // FIELD: pll_pu_tm [1] // PLL Power-Up Override |
| // FIELD: xo_pu_tm [0] // XO Power-Up Override |
| |
| //#define ATE_HSP_TI_RW_ADDR03 0xA013 |
| #define HSPX_RW_ADDR3 0xA113 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: XO_always_on [2] // XO_Always_On |
| // FIELD: serclk_rx_enb_tm [1] // Rx Clock Gating Enable |
| // FIELD: serclk_tx_enb_tm [0] // Tx Clock Gating Enable |
| |
| //#define ATE_HSP_TI_RW_ADDR04 0xA014 |
| #define HSPX_RW_ADDR4 0xA114 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: LoopbackEnb_int [3] // Loopback Enabled |
| // FIELD: VDPU_EN2 [1] // D+ Pull-Up Override 2 |
| // FIELD: VDPU_EN1 [0] // D+ Pull-up Override 1 |
| |
| //#define ATE_HSP_TI_RW_ADDR05 0xA015 |
| #define HSPX_RW_ADDR5 0xA115 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: xo_clk_div_tm [3:2] // Reference Clock Divider Select [1:0] |
| // FIELD: mstr_overrd_bit [2] // Analog Test Control Master Override Bit |
| // FIELD: overrd_addr[4][1] // Analog Test Control Override Address[4] |
| |
| //#define ATE_HSP_TI_RW_ADDR06 0xA016 |
| #define HSPX_RW_ADDR6 0xA116 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tx_sliver_en [3:0] // Tx Parallel Resistance Circuit[3:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR07 0xA017 |
| #define HSPX_RW_ADDR7 0xA117 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tx_ls_en [3] // LS Tx Enable |
| |
| //#define ATE_HSP_TI_RW_ADDR08 0xA018 |
| #define HSPX_RW_ADDR8 0xA118 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: bistEn [3] // BIST Enable |
| // FIELD: hs_bist [2] // HS BIST |
| // FIELD: fs_bist [1] // FS BIST |
| // FIELD: ls_bist [0] // LS BIST |
| |
| //#define ATE_HSP_TI_RW_ADDR09 0xA019 |
| #define HSPX_RW_ADDR9 0xA119 |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: inst_bist_err [3] // Insert BIST error |
| // FIELD: dm_pulldown_en [1] // D-Â Pull-Down Override |
| // FIELD: dp_pulldown_en [0] // D+ Pull-Down Override |
| |
| //#define ATE_HSP_TI_RW_ADDR10 0xA01A |
| #define HSPX_RW_ADDR10 0xA11A |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: fs_assert_se0 [2] // FS/LS Tx Assert SE0 |
| // FIELD: fs_output_enb [1] // FS/LS Transmit Output Enable |
| // FIELD: fs_dataout [0] // FS/LS Transmit Data |
| |
| //#define ATE_HSP_TI_RW_ADDR11 0xA01B |
| #define HSPX_RW_ADDR11 0xA11B |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: res_req_in_tm [3] // Resistor Request Override |
| // FIELD: incr_tune_dis_tm [2] // Disable Incremental Tune |
| // FIELD: comp_sel_analog [1] // Disconnect/Tune Block Comparator Test Mode |
| |
| //#define ATE_HSP_TI_RW_ADDR12 0xA01C |
| #define HSPX_RW_ADDR12 0xA11C |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: res_ack_out [3] // Resistor Acknowledge Override |
| // FIELD: pll_clk_div_tm [1:0] // PLL Clock Divider[1:0] |
| // FIELD: pll_reset [1] // PLL Reset |
| |
| //#define ATE_HSP_TI_RW_ADDR13 0xA01D |
| #define HSPX_RW_ADDR13 0xA11D |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: bist_mode_tm [3] // BIST Mode |
| // FIELD: test_pkt_rpt [2] // BIST Test Packet Repeat |
| // FIELD: xo_clk_sel_tm [1:0] // REFCLKSEL[1:0] |
| |
| //#define ATE_HSP_TI_RW_ADDR14 0xA01E |
| #define HSPX_RW_ADDR14 0xA11E |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: tap_sel_ovrd_tm [3] // TAP Select Override |
| // FIELD: tap_shift_enb_tm [2] // TAP Shift Enable |
| // FIELD: tap_shift_dir_tm [1] // TAP Shift Direction |
| // FIELD: Squelch_DisN_async [0] // Squelch Signal |
| |
| //#define ATE_HSP_TI_RW_ADDR15 0xA01F |
| #define HSPX_RW_ADDR15 0xA11F |
| // FIELD: [7:4] // Write enable bits for bit field [3:0] |
| // FIELD: ClkUsable_tm [3] // Override for Transceiver ClkUsable |
| // FIELD: scale_down_mode [2] // Scale-Down Enable for Disconnect Timers |
| // FIELD: pll_lock_tm [1] // PLL Force Lock |
| */ |
