Add DDR configuration for spacecast.
- Give USB the highest priority to access the memory.
- Reallocate the quota for CPU, USB and SATA ports.
Change-Id: I2cf17fe04baef183e6e9ef50ab11c75fc1acd4e0
diff --git a/arch/arm/boards/optimus/ddr.c b/arch/arm/boards/optimus/ddr.c
index 10044cd..ec86ce4 100644
--- a/arch/arm/boards/optimus/ddr.c
+++ b/arch/arm/boards/optimus/ddr.c
@@ -6,8 +6,6 @@
#include <mach/gpio.h>
#include <board_id.h>
-/* This array is called optimus_ddrc_cfg for historic reasons. */
-/* It applies to both Optimus and SpaceCast. */
static struct ddr_reg_val optimus_ddrc_cfg[] = {
{DDRC_CTL_00_REG, 0x20410600LL},
{DDRC_CTL_02_REG, 0x00000006LL},
@@ -79,6 +77,77 @@
{0, 0}
};
+static struct ddr_reg_val spacecast_ddrc_cfg[] = {
+ {DDRC_CTL_00_REG, 0x20410600LL},
+ {DDRC_CTL_02_REG, 0x00000006LL},
+ {DDRC_CTL_03_REG, 0x0001A07CLL},
+ {DDRC_CTL_04_REG, 0x00041127LL},
+ {DDRC_CTL_05_REG, 0x04061200LL},
+ {DDRC_CTL_06_REG, 0x141B0404LL},
+ {DDRC_CTL_07_REG, 0x08040804LL},
+ {DDRC_CTL_08_REG, 0x0092190CLL},
+ {DDRC_CTL_09_REG, 0x00000504LL},
+ {DDRC_CTL_10_REG, 0x08080101LL},
+ {DDRC_CTL_11_REG, 0x00020010LL},
+ {DDRC_CTL_12_REG, 0x00011803LL},
+ {DDRC_CTL_13_REG, 0x00000009LL},
+ {DDRC_CTL_14_REG, 0x00BB0100LL},
+ {DDRC_CTL_15_REG, 0x00001034LL},
+ {DDRC_CTL_16_REG, 0x000D0004LL},
+ {DDRC_CTL_17_REG, 0x00060002LL},
+ {DDRC_CTL_18_REG, 0x00C00200LL},
+ {DDRC_CTL_19_REG, 0x00000000LL},
+ {DDRC_CTL_20_REG, 0x00060600LL},
+ {DDRC_CTL_21_REG, 0x00000000LL},
+ {DDRC_CTL_22_REG, 0x00000000LL},
+ {DDRC_CTL_23_REG, 0x00000000LL},
+ {DDRC_CTL_24_REG, 0x00000000LL},
+ {DDRC_CTL_25_REG, 0x00000000LL},
+ {DDRC_CTL_26_REG, 0x00000000LL},
+ {DDRC_CTL_27_REG, 0x00085000LL},
+ {DDRC_CTL_28_REG, 0x00080006LL},
+ {DDRC_CTL_29_REG, 0x00000000LL},
+ {DDRC_CTL_30_REG, 0x00060850LL},
+ {DDRC_CTL_31_REG, 0x00000008LL},
+ {DDRC_CTL_32_REG, 0x00020000LL},
+ {DDRC_CTL_33_REG, 0x00000000LL},
+ {DDRC_CTL_43_REG, 0x01400200LL},
+ {DDRC_CTL_44_REG, 0x02000040LL},
+ {DDRC_CTL_45_REG, 0x01010080LL},
+ {DDRC_CTL_46_REG, 0xFF0A0101LL},
+ {DDRC_CTL_47_REG, 0x010101FFLL},
+ {DDRC_CTL_48_REG, 0x00010001LL},
+ {DDRC_CTL_49_REG, 0x000C0100LL},
+ {DDRC_CTL_50_REG, 0x00010002LL},
+ {DDRC_CTL_52_REG, 0x00000000LL},
+ {DDRC_CTL_53_REG, 0x007FFFFFLL},
+ {DDRC_CTL_59_REG, 0x01000000LL},
+ {DDRC_CTL_60_REG, 0x00020100LL},
+ {DDRC_CTL_61_REG, 0x02010202LL},
+ {DDRC_CTL_62_REG, 0x02000100LL},
+ {DDRC_CTL_63_REG, 0x00000000LL},
+ {DDRC_CTL_91_REG, 0xFFFF0000LL},
+ {DDRC_CTL_92_REG, 0x00000202LL},
+ {DDRC_CTL_93_REG, 0x0303FFFFLL},
+ {DDRC_CTL_94_REG, 0x03FFFF00LL},
+ {DDRC_CTL_95_REG, 0xFFFF0003LL},
+ {DDRC_CTL_96_REG, 0x00000101LL},
+ {DDRC_CTL_97_REG, 0x01000400LL},
+ {DDRC_CTL_98_REG, 0x00012100LL},
+ {DDRC_CTL_99_REG, 0x0500011aLL},
+ {DDRC_CTL_100_REG, 0x00000001LL},
+ {DDRC_CTL_102_REG, 0x00000800LL},
+ {DDRC_CTL_103_REG, 0x00103300LL},
+ {DDRC_CTL_104_REG, 0x02000200LL},
+ {DDRC_CTL_105_REG, 0x02000200LL},
+ {DDRC_CTL_106_REG, 0x00001033LL},
+ {DDRC_CTL_107_REG, 0x000050FFLL},
+ {DDRC_CTL_108_REG, 0x00020610LL},
+ {DDRC_CTL_109_REG, 0x00000003LL},
+ {DDRC_CTL_126_REG, 0x00000000LL},
+ {0, 0}
+};
+
/* This array is called optimus_ddr_phy_cfg for historic reasons. */
/* It applies to both Optimus and SpaceCast. */
static struct ddr_reg_val optimus_ddr_phy_cfg[] = {
@@ -182,7 +251,7 @@
{optimus_ddr_phy_cfg, optimus_ddrc_cfg, SZ_1G, "Optimus"},
/* Nanya NT5CB128M16FP-DI, 533MHz, 32bit, NoECC */
{sideswipe_ddr_phy_cfg, sideswipe_ddrc_cfg, SZ_512M, "Sideswipe"},
- {optimus_ddr_phy_cfg, optimus_ddrc_cfg, SZ_1G, "SpaceCast"},
+ {optimus_ddr_phy_cfg, spacecast_ddrc_cfg, SZ_1G, "SpaceCast"},
};
static struct ddr_config bad_board_id_ddr_config = {0, 0, 0, "Unknown"};
