windcharger: enable gpio4 on reset to maintain poe
GPIO4 is hardwired to output CPU_CLK/4 immediately after reset, and by the time
we set the state in ath_gpio_config the PoE devices have already rebooted.
Instead we configure GPIO4 as early as possible so that PoE devices won't be
interrupted. This way the power interruption is approximately 440uS which can
be safely tolerated by GFLT devices.
PVT boards will use a different GPIO for PoE control, and this fix won't be
needed.
Change-Id: Id96566b86c917a25d45cd295efb6549a955135fd
diff --git a/board/atheros/board953x/board953x.c b/board/atheros/board953x/board953x.c
index 2990dcf..1eee259 100755
--- a/board/atheros/board953x/board953x.c
+++ b/board/atheros/board953x/board953x.c
@@ -95,11 +95,7 @@
void ath_gpio_config(void)
{
- /* disable the CLK_OBS on GPIO_4 and set GPIO4 as input */
- ath_reg_rmw_clear(GPIO_OE_ADDRESS, (1 << 4));
- ath_reg_rmw_clear(GPIO_OUT_FUNCTION1_ADDRESS, GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK);
- ath_reg_rmw_set(GPIO_OUT_FUNCTION1_ADDRESS, GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(0x80));
- ath_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 4));
+ /* GPIO4 configured in cpu/mips/start.S */
/* Set GPIO 13 as input for LED functionality to be OFF during bootup */
ath_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 13));
/* Turn off JUMPST_LED and 5Gz LED during bootup */
diff --git a/board/atheros/common/serial.c b/board/atheros/common/serial.c
index 1afc5f7..e6d8540 100755
--- a/board/atheros/common/serial.c
+++ b/board/atheros/common/serial.c
@@ -38,7 +38,7 @@
#elif defined(CONFIG_MACH_QCA956x)
val = ath_reg_rd(GPIO_OE_ADDRESS) & 0xbbfdf6;
#else
- val = ath_reg_rd(GPIO_OE_ADDRESS) & (~0xcffc10u);
+ val = ath_reg_rd(GPIO_OE_ADDRESS) & (~0xcffc00u);
#endif
ath_reg_wr(GPIO_OE_ADDRESS, val);
@@ -159,7 +159,7 @@
ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS,
GPIO_IN_ENABLE0_UART_SIN_SET(0x9));
- val = ath_reg_rd(GPIO_OUT_ADDRESS) | 0xcffc10u;
+ val = ath_reg_rd(GPIO_OUT_ADDRESS) | 0xcffc00u;
ath_reg_wr(GPIO_OUT_ADDRESS, val);
val = ath_reg_rd(GPIO_SPARE_ADDRESS);
diff --git a/cpu/mips/start.S b/cpu/mips/start.S
index 26ce94e..7b7a96c 100755
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -189,6 +189,17 @@
.align 4
reset:
+ /* TODO(abf): Windcharger PVT will use different GPIO for PoE control. This
+ is only needed for EVT/DVT board testing */
+ /* disable CLK_OBS on GPIO_4 */
+ li t0, 0xb8040030
+ li t1, 0x0c080900
+ sw t1, 0(t0)
+ /* set GPIO4 low (enable PoE) */
+ li t0, 0xb8040010
+ li t1, 0x000000ff
+ sw t1, 0(t0)
+
#if !defined(CONFIG_ATH_NAND_BR)
/*
* Clearing CP0 registers - This is generally required for the MIPS-24k
