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/***************************************************************************
* Copyright (c) 1999-2014, Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Module Description:
* DO NOT EDIT THIS FILE DIRECTLY
*
* This module was generated magically with RDB from a source description
* file. You must edit the source file for changes to be made to this file.
*
*
* Date: Generated on Fri Dec 19 03:17:11 2014
* Full Compile MD5 Checksum 9e27b6ad4c64ff5a28f048a17a7bb056
* (minus title and desc)
* MD5 Checksum a1a4b86f7693c062faaafa50c5ca64ce
*
* Compiled with: RDB Utility combo_header.pl
* RDB Parser 3.0
* unknown unknown
* Perl Interpreter 5.008008
* Operating System linux
*
* Revision History:
*
* $brcm_Log: $
*
***************************************************************************/
#ifndef BCHP_COMMON_H__
#define BCHP_COMMON_H__
/**
* m = memory, c = core, r = register, f = field, d = data.
*/
#if !defined(GET_FIELD) && !defined(SET_FIELD)
#define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK
#define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT
#define GET_FIELD(m,c,r,f) \
((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)))
#define SET_FIELD(m,c,r,f,d) \
((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))))
#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
#endif /* GET & SET */
/***************************************************************************
*BCM7439_B0
***************************************************************************/
#define BCHP_PHYSICAL_OFFSET 0xf0000000
#define BCHP_REGISTER_START 0x00000000 /* HEVD_OL_CPU_REGS_0 is first */
#define BCHP_REGISTER_END 0x01200000 /* MEMC_SENTINEL_0_1 is last */
#define BCHP_REGISTER_SIZE 0x00480000 /* Number of registers */
/****************************************************************************
* Core instance register start address.
***************************************************************************/
#define BCHP_HEVD_OL_CPU_REGS_0_REG_START 0x00000000
#define BCHP_HEVD_OL_CPU_REGS_0_REG_END 0x00000108
#define BCHP_HEVD_OL_CPU_DMA_0_REG_START 0x00000400
#define BCHP_HEVD_OL_CPU_DMA_0_REG_END 0x00000440
#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_START 0x00000800
#define BCHP_HEVD_OL_CPU_DEBUG_0_REG_END 0x00000ffc
#define BCHP_HEVD_OL_SINT_0_REG_START 0x00001000
#define BCHP_HEVD_OL_SINT_0_REG_END 0x00001028
#define BCHP_HEVD_OL_LDST_0_REG_START 0x00008000
#define BCHP_HEVD_OL_LDST_0_REG_END 0x0000fffc
#define BCHP_REG_CABAC2BINS_0_REG_START 0x00010b00
#define BCHP_REG_CABAC2BINS_0_REG_END 0x00010bfc
#define BCHP_REG_CABAC2BINS2_0_REG_START 0x00012400
#define BCHP_REG_CABAC2BINS2_0_REG_END 0x000127fc
#define BCHP_HEVD_CABAC_0_REG_START 0x00013000
#define BCHP_HEVD_CABAC_0_REG_END 0x0001307c
#define BCHP_HEVD_OL_CTL_0_REG_START 0x00014000
#define BCHP_HEVD_OL_CTL_0_REG_END 0x000151fc
#define BCHP_DECODE_MAIN_0_REG_START 0x00020100
#define BCHP_DECODE_MAIN_0_REG_END 0x000201fc
#define BCHP_DECODE_MCOM_0_REG_START 0x00020300
#define BCHP_DECODE_MCOM_0_REG_END 0x0002031c
#define BCHP_DECODE_SPRE_0_REG_START 0x00020320
#define BCHP_DECODE_SPRE_0_REG_END 0x0002033c
#define BCHP_DECODE_WPRD_0_REG_START 0x00020340
#define BCHP_DECODE_WPRD_0_REG_END 0x0002035c
#define BCHP_DECODE_DQNT_0_REG_START 0x00020400
#define BCHP_DECODE_DQNT_0_REG_END 0x0002045c
#define BCHP_DECODE_DQNT_8X8_0_REG_START 0x00020500
#define BCHP_DECODE_DQNT_8X8_0_REG_END 0x0002057c
#define BCHP_DECODE_VP8_XFRM_0_REG_START 0x00020600
#define BCHP_DECODE_VP8_XFRM_0_REG_END 0x0002060c
#define BCHP_DECODE_VP6_DCP_0_REG_START 0x00020620
#define BCHP_DECODE_VP6_DCP_0_REG_END 0x0002062c
#define BCHP_DECODE_XFRM_0_REG_START 0x00020700
#define BCHP_DECODE_XFRM_0_REG_END 0x0002071c
#define BCHP_DECODE_DBLK_0_REG_START 0x00020720
#define BCHP_DECODE_DBLK_0_REG_END 0x0002073c
#define BCHP_DECODE_MB_0_REG_START 0x00020740
#define BCHP_DECODE_MB_0_REG_END 0x0002075c
#define BCHP_DECODE_SINT_0_REG_START 0x00020c00
#define BCHP_DECODE_SINT_0_REG_END 0x00020dfc
#define BCHP_DECODE_WPTBL_0_REG_START 0x00023000
#define BCHP_DECODE_WPTBL_0_REG_END 0x000231fc
#define BCHP_HEVD_BE_GLOBAL_0_REG_START 0x00024000
#define BCHP_HEVD_BE_GLOBAL_0_REG_END 0x00024030
#define BCHP_HEVD_IXFORM_0_REG_START 0x00024100
#define BCHP_HEVD_IXFORM_0_REG_END 0x000241fc
#define BCHP_HEVD_MCOMP_0_REG_START 0x00024200
#define BCHP_HEVD_MCOMP_0_REG_END 0x000242fc
#define BCHP_HEVD_SPRED_0_REG_START 0x00024300
#define BCHP_HEVD_SPRED_0_REG_END 0x000243f0
#define BCHP_HEVD_FILTER_0_REG_START 0x00024400
#define BCHP_HEVD_FILTER_0_REG_END 0x000244fc
#define BCHP_HEVD_OUTPUT_0_REG_START 0x00024500
#define BCHP_HEVD_OUTPUT_0_REG_END 0x000245fc
#define BCHP_HEVD_MARKER_0_REG_START 0x00024f00
#define BCHP_HEVD_MARKER_0_REG_END 0x00024f7c
#define BCHP_HEVD_FE_CTRL_0_REG_START 0x00025000
#define BCHP_HEVD_FE_CTRL_0_REG_END 0x0002507c
#define BCHP_HEVD_STRM_IN_0_REG_START 0x00025100
#define BCHP_HEVD_STRM_IN_0_REG_END 0x00025118
#define BCHP_HEVD_CMDBUS_XMIT_0_REG_START 0x00025200
#define BCHP_HEVD_CMDBUS_XMIT_0_REG_END 0x00025230
#define BCHP_HEVD_VECGEN_0_REG_START 0x00025400
#define BCHP_HEVD_VECGEN_0_REG_END 0x0002568c
#define BCHP_DCD_PIPE_CTL_0_REG_START 0x00026000
#define BCHP_DCD_PIPE_CTL_0_REG_END 0x00026404
#define BCHP_HEVD_PCACHE_0_REG_START 0x00026800
#define BCHP_HEVD_PCACHE_0_REG_END 0x00026838
#define BCHP_HEVD_PFRI_0_REG_START 0x00026a00
#define BCHP_HEVD_PFRI_0_REG_END 0x00026b58
#define BCHP_RVC_0_REG_START 0x00026c00
#define BCHP_RVC_0_REG_END 0x00026c20
#define BCHP_HEVD_IL_CPU_REGS_0_REG_START 0x00030000
#define BCHP_HEVD_IL_CPU_REGS_0_REG_END 0x00030108
#define BCHP_HEVD_IL_CPU_DMA_0_REG_START 0x00030400
#define BCHP_HEVD_IL_CPU_DMA_0_REG_END 0x00030440
#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_START 0x00030800
#define BCHP_HEVD_IL_CPU_DEBUG_0_REG_END 0x00030ffc
#define BCHP_HEVD_IL_SLICE_DMA_0_REG_START 0x00031000
#define BCHP_HEVD_IL_SLICE_DMA_0_REG_END 0x0003100c
#define BCHP_HEVD_IL_LDST_0_REG_START 0x00034000
#define BCHP_HEVD_IL_LDST_0_REG_END 0x00037ffc
#define BCHP_DECODE_MAIN_2_0_REG_START 0x00040100
#define BCHP_DECODE_MAIN_2_0_REG_END 0x000401fc
#define BCHP_DECODE_MCOM_2_0_REG_START 0x00040300
#define BCHP_DECODE_MCOM_2_0_REG_END 0x0004031c
#define BCHP_DECODE_SPRE_2_0_REG_START 0x00040320
#define BCHP_DECODE_SPRE_2_0_REG_END 0x0004033c
#define BCHP_DECODE_WPRD_2_0_REG_START 0x00040340
#define BCHP_DECODE_WPRD_2_0_REG_END 0x0004035c
#define BCHP_DECODE_DQNT_2_0_REG_START 0x00040400
#define BCHP_DECODE_DQNT_2_0_REG_END 0x0004045c
#define BCHP_DECODE_DQNT_8X8_2_0_REG_START 0x00040500
#define BCHP_DECODE_DQNT_8X8_2_0_REG_END 0x0004057c
#define BCHP_DECODE_VP8_XFRM_2_0_REG_START 0x00040600
#define BCHP_DECODE_VP8_XFRM_2_0_REG_END 0x0004060c
#define BCHP_DECODE_VP6_DCP_2_0_REG_START 0x00040620
#define BCHP_DECODE_VP6_DCP_2_0_REG_END 0x0004062c
#define BCHP_DECODE_XFRM_2_0_REG_START 0x00040700
#define BCHP_DECODE_XFRM_2_0_REG_END 0x0004071c
#define BCHP_DECODE_DBLK_2_0_REG_START 0x00040720
#define BCHP_DECODE_DBLK_2_0_REG_END 0x0004073c
#define BCHP_DECODE_MB_2_0_REG_START 0x00040740
#define BCHP_DECODE_MB_2_0_REG_END 0x0004075c
#define BCHP_DECODE_SINT_2_0_REG_START 0x00040c00
#define BCHP_DECODE_SINT_2_0_REG_END 0x00040dfc
#define BCHP_DECODE_WPTBL_2_0_REG_START 0x00043000
#define BCHP_DECODE_WPTBL_2_0_REG_END 0x000431fc
#define BCHP_HEVD_BE_GLOBAL_2_0_REG_START 0x00044000
#define BCHP_HEVD_BE_GLOBAL_2_0_REG_END 0x00044030
#define BCHP_HEVD_IXFORM_2_0_REG_START 0x00044100
#define BCHP_HEVD_IXFORM_2_0_REG_END 0x000441fc
#define BCHP_HEVD_MCOMP_2_0_REG_START 0x00044200
#define BCHP_HEVD_MCOMP_2_0_REG_END 0x000442fc
#define BCHP_HEVD_SPRED_2_0_REG_START 0x00044300
#define BCHP_HEVD_SPRED_2_0_REG_END 0x000443f0
#define BCHP_HEVD_FILTER_2_0_REG_START 0x00044400
#define BCHP_HEVD_FILTER_2_0_REG_END 0x000444fc
#define BCHP_HEVD_OUTPUT_2_0_REG_START 0x00044500
#define BCHP_HEVD_OUTPUT_2_0_REG_END 0x000445fc
#define BCHP_HEVD_MARKER_2_0_REG_START 0x00044f00
#define BCHP_HEVD_MARKER_2_0_REG_END 0x00044f7c
#define BCHP_HEVD_FE_CTRL_2_0_REG_START 0x00045000
#define BCHP_HEVD_FE_CTRL_2_0_REG_END 0x0004507c
#define BCHP_HEVD_STRM_IN_2_0_REG_START 0x00045100
#define BCHP_HEVD_STRM_IN_2_0_REG_END 0x00045118
#define BCHP_HEVD_CMDBUS_XMIT_2_0_REG_START 0x00045200
#define BCHP_HEVD_CMDBUS_XMIT_2_0_REG_END 0x00045230
#define BCHP_HEVD_VECGEN_2_0_REG_START 0x00045400
#define BCHP_HEVD_VECGEN_2_0_REG_END 0x0004568c
#define BCHP_DCD_PIPE_CTL_2_0_REG_START 0x00046000
#define BCHP_DCD_PIPE_CTL_2_0_REG_END 0x00046404
#define BCHP_HEVD_PCACHE_2_0_REG_START 0x00046800
#define BCHP_HEVD_PCACHE_2_0_REG_END 0x00046838
#define BCHP_HEVD_PFRI_2_0_REG_START 0x00046a00
#define BCHP_HEVD_PFRI_2_0_REG_END 0x00046b58
#define BCHP_RVC_2_0_REG_START 0x00046c00
#define BCHP_RVC_2_0_REG_END 0x00046c20
#define BCHP_HEVD_IL_CPU_REGS_2_0_REG_START 0x00050000
#define BCHP_HEVD_IL_CPU_REGS_2_0_REG_END 0x00050108
#define BCHP_HEVD_IL_CPU_DMA_2_0_REG_START 0x00050400
#define BCHP_HEVD_IL_CPU_DMA_2_0_REG_END 0x00050440
#define BCHP_HEVD_IL_CPU_DEBUG_2_0_REG_START 0x00050800
#define BCHP_HEVD_IL_CPU_DEBUG_2_0_REG_END 0x00050ffc
#define BCHP_HEVD_IL_SLICE_DMA_2_0_REG_START 0x00051000
#define BCHP_HEVD_IL_SLICE_DMA_2_0_REG_END 0x0005100c
#define BCHP_HEVD_IL_LDST_2_0_REG_START 0x00054000
#define BCHP_HEVD_IL_LDST_2_0_REG_END 0x00057ffc
#define BCHP_HVD_INTR2_0_REG_START 0x00080000
#define BCHP_HVD_INTR2_0_REG_END 0x0008002c
#define BCHP_HVD_RGR_0_REG_START 0x00080400
#define BCHP_HVD_RGR_0_REG_END 0x00080410
#define BCHP_VICH_0_REG_START 0x000a0000
#define BCHP_VICH_0_REG_END 0x000a008b
#define BCHP_HEVD_OL_CPU_REGS_1_REG_START 0x00100000
#define BCHP_HEVD_OL_CPU_REGS_1_REG_END 0x00100108
#define BCHP_HEVD_OL_CPU_DMA_1_REG_START 0x00100400
#define BCHP_HEVD_OL_CPU_DMA_1_REG_END 0x00100440
#define BCHP_HEVD_OL_CPU_DEBUG_1_REG_START 0x00100800
#define BCHP_HEVD_OL_CPU_DEBUG_1_REG_END 0x00100ffc
#define BCHP_HEVD_OL_SINT_1_REG_START 0x00101000
#define BCHP_HEVD_OL_SINT_1_REG_END 0x00101028
#define BCHP_HEVD_OL_LDST_1_REG_START 0x00108000
#define BCHP_HEVD_OL_LDST_1_REG_END 0x0010fffc
#define BCHP_REG_CABAC2BINS_1_REG_START 0x00110b00
#define BCHP_REG_CABAC2BINS_1_REG_END 0x00110bfc
#define BCHP_REG_CABAC2BINS2_1_REG_START 0x00112400
#define BCHP_REG_CABAC2BINS2_1_REG_END 0x001127fc
#define BCHP_HEVD_CABAC_1_REG_START 0x00113000
#define BCHP_HEVD_CABAC_1_REG_END 0x0011307c
#define BCHP_HEVD_OL_CTL_1_REG_START 0x00114000
#define BCHP_HEVD_OL_CTL_1_REG_END 0x001151fc
#define BCHP_DECODE_MAIN_1_REG_START 0x00120100
#define BCHP_DECODE_MAIN_1_REG_END 0x001201fc
#define BCHP_DECODE_MCOM_1_REG_START 0x00120300
#define BCHP_DECODE_MCOM_1_REG_END 0x0012031c
#define BCHP_DECODE_SPRE_1_REG_START 0x00120320
#define BCHP_DECODE_SPRE_1_REG_END 0x0012033c
#define BCHP_DECODE_WPRD_1_REG_START 0x00120340
#define BCHP_DECODE_WPRD_1_REG_END 0x0012035c
#define BCHP_DECODE_DQNT_1_REG_START 0x00120400
#define BCHP_DECODE_DQNT_1_REG_END 0x0012045c
#define BCHP_DECODE_DQNT_8X8_1_REG_START 0x00120500
#define BCHP_DECODE_DQNT_8X8_1_REG_END 0x0012057c
#define BCHP_DECODE_VP8_XFRM_1_REG_START 0x00120600
#define BCHP_DECODE_VP8_XFRM_1_REG_END 0x0012060c
#define BCHP_DECODE_VP6_DCP_1_REG_START 0x00120620
#define BCHP_DECODE_VP6_DCP_1_REG_END 0x0012062c
#define BCHP_DECODE_XFRM_1_REG_START 0x00120700
#define BCHP_DECODE_XFRM_1_REG_END 0x0012071c
#define BCHP_DECODE_DBLK_1_REG_START 0x00120720
#define BCHP_DECODE_DBLK_1_REG_END 0x0012073c
#define BCHP_DECODE_MB_1_REG_START 0x00120740
#define BCHP_DECODE_MB_1_REG_END 0x0012075c
#define BCHP_DECODE_SINT_1_REG_START 0x00120c00
#define BCHP_DECODE_SINT_1_REG_END 0x00120dfc
#define BCHP_DECODE_WPTBL_1_REG_START 0x00123000
#define BCHP_DECODE_WPTBL_1_REG_END 0x001231fc
#define BCHP_HEVD_BE_GLOBAL_1_REG_START 0x00124000
#define BCHP_HEVD_BE_GLOBAL_1_REG_END 0x00124030
#define BCHP_HEVD_IXFORM_1_REG_START 0x00124100
#define BCHP_HEVD_IXFORM_1_REG_END 0x001241fc
#define BCHP_HEVD_MCOMP_1_REG_START 0x00124200
#define BCHP_HEVD_MCOMP_1_REG_END 0x001242fc
#define BCHP_HEVD_SPRED_1_REG_START 0x00124300
#define BCHP_HEVD_SPRED_1_REG_END 0x001243f0
#define BCHP_HEVD_FILTER_1_REG_START 0x00124400
#define BCHP_HEVD_FILTER_1_REG_END 0x001244fc
#define BCHP_HEVD_OUTPUT_1_REG_START 0x00124500
#define BCHP_HEVD_OUTPUT_1_REG_END 0x001245fc
#define BCHP_HEVD_MARKER_1_REG_START 0x00124f00
#define BCHP_HEVD_MARKER_1_REG_END 0x00124f7c
#define BCHP_HEVD_FE_CTRL_1_REG_START 0x00125000
#define BCHP_HEVD_FE_CTRL_1_REG_END 0x0012507c
#define BCHP_HEVD_STRM_IN_1_REG_START 0x00125100
#define BCHP_HEVD_STRM_IN_1_REG_END 0x00125118
#define BCHP_HEVD_CMDBUS_XMIT_1_REG_START 0x00125200
#define BCHP_HEVD_CMDBUS_XMIT_1_REG_END 0x00125230
#define BCHP_HEVD_VECGEN_1_REG_START 0x00125400
#define BCHP_HEVD_VECGEN_1_REG_END 0x0012568c
#define BCHP_DCD_PIPE_CTL_1_REG_START 0x00126000
#define BCHP_DCD_PIPE_CTL_1_REG_END 0x00126404
#define BCHP_HEVD_PCACHE_1_REG_START 0x00126800
#define BCHP_HEVD_PCACHE_1_REG_END 0x00126838
#define BCHP_HEVD_PFRI_1_REG_START 0x00126a00
#define BCHP_HEVD_PFRI_1_REG_END 0x00126b58
#define BCHP_RVC_1_REG_START 0x00126c00
#define BCHP_RVC_1_REG_END 0x00126c20
#define BCHP_HEVD_IL_CPU_REGS_1_REG_START 0x00130000
#define BCHP_HEVD_IL_CPU_REGS_1_REG_END 0x00130108
#define BCHP_HEVD_IL_CPU_DMA_1_REG_START 0x00130400
#define BCHP_HEVD_IL_CPU_DMA_1_REG_END 0x00130440
#define BCHP_HEVD_IL_CPU_DEBUG_1_REG_START 0x00130800
#define BCHP_HEVD_IL_CPU_DEBUG_1_REG_END 0x00130ffc
#define BCHP_HEVD_IL_SLICE_DMA_1_REG_START 0x00131000
#define BCHP_HEVD_IL_SLICE_DMA_1_REG_END 0x0013100c
#define BCHP_HEVD_IL_LDST_1_REG_START 0x00134000
#define BCHP_HEVD_IL_LDST_1_REG_END 0x00137ffc
#define BCHP_DECODE_MAIN_2_1_REG_START 0x00140100
#define BCHP_DECODE_MAIN_2_1_REG_END 0x001401fc
#define BCHP_DECODE_MCOM_2_1_REG_START 0x00140300
#define BCHP_DECODE_MCOM_2_1_REG_END 0x0014031c
#define BCHP_DECODE_SPRE_2_1_REG_START 0x00140320
#define BCHP_DECODE_SPRE_2_1_REG_END 0x0014033c
#define BCHP_DECODE_WPRD_2_1_REG_START 0x00140340
#define BCHP_DECODE_WPRD_2_1_REG_END 0x0014035c
#define BCHP_DECODE_DQNT_2_1_REG_START 0x00140400
#define BCHP_DECODE_DQNT_2_1_REG_END 0x0014045c
#define BCHP_DECODE_DQNT_8X8_2_1_REG_START 0x00140500
#define BCHP_DECODE_DQNT_8X8_2_1_REG_END 0x0014057c
#define BCHP_DECODE_VP8_XFRM_2_1_REG_START 0x00140600
#define BCHP_DECODE_VP8_XFRM_2_1_REG_END 0x0014060c
#define BCHP_DECODE_VP6_DCP_2_1_REG_START 0x00140620
#define BCHP_DECODE_VP6_DCP_2_1_REG_END 0x0014062c
#define BCHP_DECODE_XFRM_2_1_REG_START 0x00140700
#define BCHP_DECODE_XFRM_2_1_REG_END 0x0014071c
#define BCHP_DECODE_DBLK_2_1_REG_START 0x00140720
#define BCHP_DECODE_DBLK_2_1_REG_END 0x0014073c
#define BCHP_DECODE_MB_2_1_REG_START 0x00140740
#define BCHP_DECODE_MB_2_1_REG_END 0x0014075c
#define BCHP_DECODE_SINT_2_1_REG_START 0x00140c00
#define BCHP_DECODE_SINT_2_1_REG_END 0x00140dfc
#define BCHP_DECODE_WPTBL_2_1_REG_START 0x00143000
#define BCHP_DECODE_WPTBL_2_1_REG_END 0x001431fc
#define BCHP_HEVD_BE_GLOBAL_2_1_REG_START 0x00144000
#define BCHP_HEVD_BE_GLOBAL_2_1_REG_END 0x00144030
#define BCHP_HEVD_IXFORM_2_1_REG_START 0x00144100
#define BCHP_HEVD_IXFORM_2_1_REG_END 0x001441fc
#define BCHP_HEVD_MCOMP_2_1_REG_START 0x00144200
#define BCHP_HEVD_MCOMP_2_1_REG_END 0x001442fc
#define BCHP_HEVD_SPRED_2_1_REG_START 0x00144300
#define BCHP_HEVD_SPRED_2_1_REG_END 0x001443f0
#define BCHP_HEVD_FILTER_2_1_REG_START 0x00144400
#define BCHP_HEVD_FILTER_2_1_REG_END 0x001444fc
#define BCHP_HEVD_OUTPUT_2_1_REG_START 0x00144500
#define BCHP_HEVD_OUTPUT_2_1_REG_END 0x001445fc
#define BCHP_HEVD_MARKER_2_1_REG_START 0x00144f00
#define BCHP_HEVD_MARKER_2_1_REG_END 0x00144f7c
#define BCHP_HEVD_FE_CTRL_2_1_REG_START 0x00145000
#define BCHP_HEVD_FE_CTRL_2_1_REG_END 0x0014507c
#define BCHP_HEVD_STRM_IN_2_1_REG_START 0x00145100
#define BCHP_HEVD_STRM_IN_2_1_REG_END 0x00145118
#define BCHP_HEVD_CMDBUS_XMIT_2_1_REG_START 0x00145200
#define BCHP_HEVD_CMDBUS_XMIT_2_1_REG_END 0x00145230
#define BCHP_HEVD_VECGEN_2_1_REG_START 0x00145400
#define BCHP_HEVD_VECGEN_2_1_REG_END 0x0014568c
#define BCHP_DCD_PIPE_CTL_2_1_REG_START 0x00146000
#define BCHP_DCD_PIPE_CTL_2_1_REG_END 0x00146404
#define BCHP_HEVD_PCACHE_2_1_REG_START 0x00146800
#define BCHP_HEVD_PCACHE_2_1_REG_END 0x00146838
#define BCHP_HEVD_PFRI_2_1_REG_START 0x00146a00
#define BCHP_HEVD_PFRI_2_1_REG_END 0x00146b58
#define BCHP_RVC_2_1_REG_START 0x00146c00
#define BCHP_RVC_2_1_REG_END 0x00146c20
#define BCHP_HEVD_IL_CPU_REGS_2_1_REG_START 0x00150000
#define BCHP_HEVD_IL_CPU_REGS_2_1_REG_END 0x00150108
#define BCHP_HEVD_IL_CPU_DMA_2_1_REG_START 0x00150400
#define BCHP_HEVD_IL_CPU_DMA_2_1_REG_END 0x00150440
#define BCHP_HEVD_IL_CPU_DEBUG_2_1_REG_START 0x00150800
#define BCHP_HEVD_IL_CPU_DEBUG_2_1_REG_END 0x00150ffc
#define BCHP_HEVD_IL_SLICE_DMA_2_1_REG_START 0x00151000
#define BCHP_HEVD_IL_SLICE_DMA_2_1_REG_END 0x0015100c
#define BCHP_HEVD_IL_LDST_2_1_REG_START 0x00154000
#define BCHP_HEVD_IL_LDST_2_1_REG_END 0x00157ffc
#define BCHP_HVD_INTR2_1_REG_START 0x00180000
#define BCHP_HVD_INTR2_1_REG_END 0x0018002c
#define BCHP_HVD_RGR_1_REG_START 0x00180400
#define BCHP_HVD_RGR_1_REG_END 0x00180410
#define BCHP_VICH_1_REG_START 0x001a0000
#define BCHP_VICH_1_REG_END 0x001a008b
#define BCHP_SCPU_LOCALRAM_REG_START 0x00300000
#define BCHP_SCPU_LOCALRAM_REG_END 0x0030fffc
#define BCHP_SCPU_GLOBALRAM_REG_START 0x00310000
#define BCHP_SCPU_GLOBALRAM_REG_END 0x003103fc
#define BCHP_SCPU_MISB_BRIDGE_REG_START 0x00310400
#define BCHP_SCPU_MISB_BRIDGE_REG_END 0x00310450
#define BCHP_SCPU_RGR_BRIDGE_REG_START 0x00310460
#define BCHP_SCPU_RGR_BRIDGE_REG_END 0x00310470
#define BCHP_SCPU_INTR1_REG_START 0x00310480
#define BCHP_SCPU_INTR1_REG_END 0x00310498
#define BCHP_INTERNAL_INTR2_REG_START 0x003104c0
#define BCHP_INTERNAL_INTR2_REG_END 0x003104ec
#define BCHP_BSP_IPI_INTR2_REG_START 0x00310500
#define BCHP_BSP_IPI_INTR2_REG_END 0x0031052c
#define BCHP_SCPU_HW_INTR2_REG_START 0x00310540
#define BCHP_SCPU_HW_INTR2_REG_END 0x0031056c
#define BCHP_CPU_IPI_INTR2_REG_START 0x00311000
#define BCHP_CPU_IPI_INTR2_REG_END 0x0031102c
#define BCHP_SCPU_HOST_INTR2_REG_START 0x00311040
#define BCHP_SCPU_HOST_INTR2_REG_END 0x0031106c
#define BCHP_SCPU_TOP_CTRL_REG_START 0x00312000
#define BCHP_SCPU_TOP_CTRL_REG_END 0x00312008
#define BCHP_SCPU_HDMI_CTRL_REG_START 0x00312080
#define BCHP_SCPU_HDMI_CTRL_REG_END 0x00312084
#define BCHP_SCPU_SEC_TIME_REG_START 0x00312100
#define BCHP_SCPU_SEC_TIME_REG_END 0x00312114
#define BCHP_SAGE_UART_REG_START 0x00312200
#define BCHP_SAGE_UART_REG_END 0x0031221c
#define BCHP_SCPU_PM_REG_START 0x00312980
#define BCHP_SCPU_PM_REG_END 0x00312988
#define BCHP_SCPU_TIMER_REG_START 0x00312e80
#define BCHP_SCPU_TIMER_REG_END 0x00312ebc
#define BCHP_BSP_CMDBUF_REG_START 0x0032c800
#define BCHP_BSP_CMDBUF_REG_END 0x0032cffc
#define BCHP_BSP_GLB_CONTROL_REG_START 0x0032d000
#define BCHP_BSP_GLB_CONTROL_REG_END 0x0032d0b0
#define BCHP_BSP_PKL_REG_START 0x0032d300
#define BCHP_BSP_PKL_REG_END 0x0032d37c
#define BCHP_BSP_CONTROL_INTR2_REG_START 0x0032d800
#define BCHP_BSP_CONTROL_INTR2_REG_END 0x0032d82c
#define BCHP_BSP_VISTA_GENACC_REG_START 0x0032d900
#define BCHP_BSP_VISTA_GENACC_REG_END 0x0032d9fc
#define BCHP_BSP_OTP_SCRATCH_REG_START 0x0032e000
#define BCHP_BSP_OTP_SCRATCH_REG_END 0x0032fffc
#define BCHP_XPT_SECURITY_REG_START 0x00360000
#define BCHP_XPT_SECURITY_REG_END 0x0037fffc
#define BCHP_SECTOP_GRB_REG_START 0x00380000
#define BCHP_SECTOP_GRB_REG_END 0x0038000c
#define BCHP_XPT_SECURITY_NS_INTR2_0_REG_START 0x00380080
#define BCHP_XPT_SECURITY_NS_INTR2_0_REG_END 0x003800ac
#define BCHP_XPT_SECURITY_NS_INTR2_1_REG_START 0x00380100
#define BCHP_XPT_SECURITY_NS_INTR2_1_REG_END 0x0038012c
#define BCHP_XPT_SECURITY_NS_INTR2_2_REG_START 0x00380180
#define BCHP_XPT_SECURITY_NS_INTR2_2_REG_END 0x003801ac
#define BCHP_XPT_SECURITY_NS_REG_START 0x00380200
#define BCHP_XPT_SECURITY_NS_REG_END 0x003802c8
#define BCHP_S_MEMC_0_REG_START 0x003bc000
#define BCHP_S_MEMC_0_REG_END 0x003bc784
#define BCHP_S_MEMC_1_REG_START 0x003cc000
#define BCHP_S_MEMC_1_REG_END 0x003cc784
#define BCHP_SDIO_0_HOST_REG_START 0x003e0000
#define BCHP_SDIO_0_HOST_REG_END 0x003e00fc
#define BCHP_SDIO_0_CFG_REG_START 0x003e0100
#define BCHP_SDIO_0_CFG_REG_END 0x003e01fc
#define BCHP_SDIO_1_HOST_REG_START 0x003e0200
#define BCHP_SDIO_1_HOST_REG_END 0x003e02fc
#define BCHP_SDIO_1_CFG_REG_START 0x003e0300
#define BCHP_SDIO_1_CFG_REG_END 0x003e03fc
#define BCHP_SDIO_1_BOOT_REG_START 0x003e0400
#define BCHP_SDIO_1_BOOT_REG_END 0x003e043c
#define BCHP_EBI_REG_START 0x003e0800
#define BCHP_EBI_REG_END 0x003e0bfc
#define BCHP_HIF_INTR2_REG_START 0x003e1000
#define BCHP_HIF_INTR2_REG_END 0x003e102c
#define BCHP_HIF_CPU_INTR1_REG_START 0x003e1500
#define BCHP_HIF_CPU_INTR1_REG_END 0x003e153c
#define BCHP_PCI_PCIE_INTR1_REG_START 0x003e1600
#define BCHP_PCI_PCIE_INTR1_REG_END 0x003e163c
#define BCHP_HIF_RGR2_REG_START 0x003e1700
#define BCHP_HIF_RGR2_REG_END 0x003e1710
#define BCHP_HIF_SPI_INTR2_REG_START 0x003e1a00
#define BCHP_HIF_SPI_INTR2_REG_END 0x003e1a2c
#define BCHP_HIF_TOP_CTRL_REG_START 0x003e2000
#define BCHP_HIF_TOP_CTRL_REG_END 0x003e203c
#define BCHP_WEBHIF_L1_MASK_REG_START 0x003e2100
#define BCHP_WEBHIF_L1_MASK_REG_END 0x003e210c
#define BCHP_HIF_CPUBIUARCH_REG_START 0x003e2200
#define BCHP_HIF_CPUBIUARCH_REG_END 0x003e23fc
#define BCHP_HIF_CPUBIUCTRL_REG_START 0x003e2400
#define BCHP_HIF_CPUBIUCTRL_REG_END 0x003e27fc
#define BCHP_NAND_REG_START 0x003e2800
#define BCHP_NAND_REG_END 0x003e2dfc
#define BCHP_FLASH_DMA_REG_START 0x003e3000
#define BCHP_FLASH_DMA_REG_END 0x003e3028
#define BCHP_BSPI_REG_START 0x003e3200
#define BCHP_BSPI_REG_END 0x003e324c
#define BCHP_BSPI_RAF_REG_START 0x003e3300
#define BCHP_BSPI_RAF_REG_END 0x003e3320
#define BCHP_HIF_MSPI_REG_START 0x003e3400
#define BCHP_HIF_MSPI_REG_END 0x003e3584
#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_START 0x003e3600
#define BCHP_HIF_CONTINUATION_SECURE_TM_REG_END 0x003e3604
#define BCHP_IPI0_INTR2_REG_START 0x003e4000
#define BCHP_IPI0_INTR2_REG_END 0x003e402c
#define BCHP_IPI1_INTR2_REG_START 0x003e4100
#define BCHP_IPI1_INTR2_REG_END 0x003e412c
#define BCHP_BOOTSRAM_TM_REG_START 0x003f0000
#define BCHP_BOOTSRAM_TM_REG_END 0x003ffffc
#define BCHP_SUN_GISB_ARB_REG_START 0x00400000
#define BCHP_SUN_GISB_ARB_REG_END 0x004007fc
#define BCHP_SUN_GR_REG_START 0x00401000
#define BCHP_SUN_GR_REG_END 0x0040100c
#define BCHP_SSP_RG_REG_START 0x00401200
#define BCHP_SSP_RG_REG_END 0x0040120c
#define BCHP_SUN_RG_REG_START 0x00401400
#define BCHP_SUN_RG_REG_END 0x0040140c
#define BCHP_TPCAP_REG_START 0x00401800
#define BCHP_TPCAP_REG_END 0x0040189c
#define BCHP_SM_L2_REG_START 0x00402000
#define BCHP_SM_L2_REG_END 0x0040202c
#define BCHP_SM_REG_START 0x00402400
#define BCHP_SM_REG_END 0x00402424
#define BCHP_SM_FAST_REG_START 0x00402800
#define BCHP_SM_FAST_REG_END 0x00402818
#define BCHP_SUN_L2_REG_START 0x00403000
#define BCHP_SUN_L2_REG_END 0x00403044
#define BCHP_SUN_TOP_CTRL_REG_START 0x00404000
#define BCHP_SUN_TOP_CTRL_REG_END 0x00404520
#define BCHP_BBSI_RG_REG_START 0x00405c00
#define BCHP_BBSI_RG_REG_END 0x00405c0c
#define BCHP_PWM_REG_START 0x00408000
#define BCHP_PWM_REG_END 0x00408024
#define BCHP_PWMB_REG_START 0x00409000
#define BCHP_PWMB_REG_END 0x00409024
#define BCHP_IRB_REG_START 0x0040a000
#define BCHP_IRB_REG_END 0x0040a138
#define BCHP_PM_REG_START 0x0040a200
#define BCHP_PM_REG_END 0x0040a208
#define BCHP_BSCA_REG_START 0x0040a300
#define BCHP_BSCA_REG_END 0x0040a354
#define BCHP_BSCD_REG_START 0x0040a400
#define BCHP_BSCD_REG_END 0x0040a454
#define BCHP_BSCE_REG_START 0x0040a500
#define BCHP_BSCE_REG_END 0x0040a554
#define BCHP_GIO_REG_START 0x0040a600
#define BCHP_GIO_REG_END 0x0040a69c
#define BCHP_IRQ0_REG_START 0x0040a700
#define BCHP_IRQ0_REG_END 0x0040a704
#define BCHP_IRQ1_REG_START 0x0040a740
#define BCHP_IRQ1_REG_END 0x0040a744
#define BCHP_TIMER_REG_START 0x0040a780
#define BCHP_TIMER_REG_END 0x0040a7bc
#define BCHP_UARTA_REG_START 0x0040a900
#define BCHP_UARTA_REG_END 0x0040a91c
#define BCHP_UARTB_REG_START 0x0040a940
#define BCHP_UARTB_REG_END 0x0040a95c
#define BCHP_UARTC_REG_START 0x0040a980
#define BCHP_UARTC_REG_END 0x0040a99c
#define BCHP_SCA_REG_START 0x0040ac00
#define BCHP_SCA_REG_END 0x0040acbc
#define BCHP_SCB_REG_START 0x0040ad00
#define BCHP_SCB_REG_END 0x0040adbc
#define BCHP_SCIRQ0_REG_START 0x0040ae00
#define BCHP_SCIRQ0_REG_END 0x0040ae04
#define BCHP_SCIRQ1_REG_START 0x0040ae40
#define BCHP_SCIRQ1_REG_END 0x0040ae44
#define BCHP_SCIRQ_SCPU_REG_START 0x0040ae80
#define BCHP_SCIRQ_SCPU_REG_END 0x0040ae84
#define BCHP_MCIF_REG_START 0x0040b000
#define BCHP_MCIF_REG_END 0x0040b028
#define BCHP_MCIF1_REG_START 0x0040b040
#define BCHP_MCIF1_REG_END 0x0040b068
#define BCHP_MCIF_INTR2_REG_START 0x0040b080
#define BCHP_MCIF_INTR2_REG_END 0x0040b0c4
#define BCHP_TMON_REG_START 0x0040b100
#define BCHP_TMON_REG_END 0x0040b154
#define BCHP_UPG_AUX_INTR2_REG_START 0x0040b180
#define BCHP_UPG_AUX_INTR2_REG_END 0x0040b1ac
#define BCHP_CTK_REG_START 0x0040b200
#define BCHP_CTK_REG_END 0x0040b378
#define BCHP_UPG_UART_DMA_REG_START 0x0040b400
#define BCHP_UPG_UART_DMA_REG_END 0x0040b430
#define BCHP_AON_CTRL_REG_START 0x00410000
#define BCHP_AON_CTRL_REG_END 0x004105fc
#define BCHP_AON_L2_REG_START 0x00410600
#define BCHP_AON_L2_REG_END 0x0041062c
#define BCHP_AON_PM_L2_REG_START 0x00410640
#define BCHP_AON_PM_L2_REG_END 0x0041066c
#define BCHP_AON_PIN_CTRL_REG_START 0x00410700
#define BCHP_AON_PIN_CTRL_REG_END 0x00410714
#define BCHP_AON_HDMI_TX_REG_START 0x00410800
#define BCHP_AON_HDMI_TX_REG_END 0x004108ac
#define BCHP_AON_HDMI_RX_REG_START 0x00411200
#define BCHP_AON_HDMI_RX_REG_END 0x004112d4
#define BCHP_CNTControlBase_REG_START 0x00412000
#define BCHP_CNTControlBase_REG_END 0x00412ffc
#define BCHP_CNTReadBase_REG_START 0x00414000
#define BCHP_CNTReadBase_REG_END 0x00414ffc
#define BCHP_MSPI_REG_START 0x00416000
#define BCHP_MSPI_REG_END 0x0041617c
#define BCHP_LDK_REG_START 0x00417000
#define BCHP_LDK_REG_END 0x0041703c
#define BCHP_PM_AON_REG_START 0x00417080
#define BCHP_PM_AON_REG_END 0x00417088
#define BCHP_ICAP_REG_START 0x004170c0
#define BCHP_ICAP_REG_END 0x004170fc
#define BCHP_KBD1_REG_START 0x00417100
#define BCHP_KBD1_REG_END 0x0041713c
#define BCHP_KBD2_REG_START 0x00417180
#define BCHP_KBD2_REG_END 0x004171bc
#define BCHP_KBD3_REG_START 0x00417200
#define BCHP_KBD3_REG_END 0x0041723c
#define BCHP_BSCB_REG_START 0x00417280
#define BCHP_BSCB_REG_END 0x004172d4
#define BCHP_BSCC_REG_START 0x00417300
#define BCHP_BSCC_REG_END 0x00417354
#define BCHP_IRQ0_AON_REG_START 0x00417380
#define BCHP_IRQ0_AON_REG_END 0x00417384
#define BCHP_IRQ1_AON_REG_START 0x004173c0
#define BCHP_IRQ1_AON_REG_END 0x004173c4
#define BCHP_GIO_AON_REG_START 0x00417400
#define BCHP_GIO_AON_REG_END 0x0041743c
#define BCHP_UPG_AUX_AON_INTR2_REG_START 0x00417500
#define BCHP_UPG_AUX_AON_INTR2_REG_END 0x0041752c
#define BCHP_WKTMR_REG_START 0x00417580
#define BCHP_WKTMR_REG_END 0x00417590
#define BCHP_BICAP_REG_START 0x004175c0
#define BCHP_BICAP_REG_END 0x004175f8
#define BCHP_SYS_GISB_ARB_SEC_REG_START 0x0041e000
#define BCHP_SYS_GISB_ARB_SEC_REG_END 0x0041e7fc
#define BCHP_SYS_TOP_CTRL_SEC_REG_START 0x0041e800
#define BCHP_SYS_TOP_CTRL_SEC_REG_END 0x0041e808
#define BCHP_AON_CTRL_SECURE_REG_START 0x0041e900
#define BCHP_AON_CTRL_SECURE_REG_END 0x0041e97c
#define BCHP_BOOTSRAM_SECURE_REG_START 0x00420000
#define BCHP_BOOTSRAM_SECURE_REG_END 0x0042fffc
#define BCHP_ITCH0_REG_START 0x00430000
#define BCHP_ITCH0_REG_END 0x00430000
#define BCHP_HIF_SECURE_CTRL_REG_START 0x00430400
#define BCHP_HIF_SECURE_CTRL_REG_END 0x00430400
#define BCHP_HIF_SECURE_BSPI_REG_START 0x00430500
#define BCHP_HIF_SECURE_BSPI_REG_END 0x00430500
#define BCHP_HIF_SECURE_LR_SPI_REG_START 0x00430600
#define BCHP_HIF_SECURE_LR_SPI_REG_END 0x00430600
#define BCHP_NAND_SECURE_REG_START 0x00430800
#define BCHP_NAND_SECURE_REG_END 0x00430800
#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_START 0x00430c00
#define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_END 0x00430c00
#define BCHP_HIF_CPUBIUARCH_SECURE_REG_START 0x00430e00
#define BCHP_HIF_CPUBIUARCH_SECURE_REG_END 0x00430ffc
#define BCHP_HIF_CONTINUATION_SECURE_REG_START 0x00431000
#define BCHP_HIF_CONTINUATION_SECURE_REG_END 0x00431004
#define BCHP_ITCH1_REG_START 0x00431200
#define BCHP_ITCH1_REG_END 0x00431200
#define BCHP_HIF_CONTINUATION_REG_START 0x00452000
#define BCHP_HIF_CONTINUATION_REG_END 0x004520fc
#define BCHP_WEBHIF_CONTINUATION_REG_START 0x00452800
#define BCHP_WEBHIF_CONTINUATION_REG_END 0x00452804
#define BCHP_WEBHIF_RGR1_REG_START 0x00454000
#define BCHP_WEBHIF_RGR1_REG_END 0x00454010
#define BCHP_WEBHIF_INTR2_REG_START 0x00454100
#define BCHP_WEBHIF_INTR2_REG_END 0x0045412c
#define BCHP_WEBHIF_CPU_INTR1_REG_START 0x00454600
#define BCHP_WEBHIF_CPU_INTR1_REG_END 0x0045463c
#define BCHP_WEBHIF_SCRATCH_REG_START 0x00454800
#define BCHP_WEBHIF_SCRATCH_REG_END 0x0045481c
#define BCHP_WEBHIF_TIMER_REG_START 0x00454900
#define BCHP_WEBHIF_TIMER_REG_END 0x0045493c
#define BCHP_WEBHIF_TOP_CTRL_REG_START 0x00454a00
#define BCHP_WEBHIF_TOP_CTRL_REG_END 0x00454a00
#define BCHP_WEBHIF_IPI0_INTR2_REG_START 0x00455000
#define BCHP_WEBHIF_IPI0_INTR2_REG_END 0x0045502c
#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_START 0x00456000
#define BCHP_WEBHIF_STB_IPI0_INTR2_REG_END 0x0045602c
#define BCHP_SATA_GRB_REG_START 0x00458000
#define BCHP_SATA_GRB_REG_END 0x0045800c
#define BCHP_SATA_TOP_CTRL_REG_START 0x00458040
#define BCHP_SATA_TOP_CTRL_REG_END 0x00458060
#define BCHP_SATA3_INTR2_REG_START 0x00458080
#define BCHP_SATA3_INTR2_REG_END 0x004580ac
#define BCHP_PORT0_SATA3_PCB_REG_START 0x00458100
#define BCHP_PORT0_SATA3_PCB_REG_END 0x00458ffc
#define BCHP_PORT1_SATA3_PCB_REG_START 0x00459100
#define BCHP_PORT1_SATA3_PCB_REG_END 0x00459ffc
#define BCHP_SATA_AHCI_GHC_REG_START 0x0045a000
#define BCHP_SATA_AHCI_GHC_REG_END 0x0045a028
#define BCHP_SATA_GLOBAL_RESERVED_REG_START 0x0045a02c
#define BCHP_SATA_GLOBAL_RESERVED_REG_END 0x0045a09c
#define BCHP_SATA_PORT0_AHCI_S1_REG_START 0x0045a100
#define BCHP_SATA_PORT0_AHCI_S1_REG_END 0x0045a11c
#define BCHP_SATA_PORT0_AHCI_S2_REG_START 0x0045a120
#define BCHP_SATA_PORT0_AHCI_S2_REG_END 0x0045a134
#define BCHP_SATA_PORT0_AHCI_S3_REG_START 0x0045a138
#define BCHP_SATA_PORT0_AHCI_S3_REG_END 0x0045a17c
#define BCHP_SATA_PORT1_AHCI_S1_REG_START 0x0045a180
#define BCHP_SATA_PORT1_AHCI_S1_REG_END 0x0045a19c
#define BCHP_SATA_PORT1_AHCI_S2_REG_START 0x0045a1a0
#define BCHP_SATA_PORT1_AHCI_S2_REG_END 0x0045a1b4
#define BCHP_SATA_PORT1_AHCI_S3_REG_START 0x0045a1b8
#define BCHP_SATA_PORT1_AHCI_S3_REG_END 0x0045a1fc
#define BCHP_SATA_AHCI_PCICFG_REG_START 0x0045a600
#define BCHP_SATA_AHCI_PCICFG_REG_END 0x0045a664
#define BCHP_SATA_PORT0_CTRL_REG_START 0x0045a700
#define BCHP_SATA_PORT0_CTRL_REG_END 0x0045a730
#define BCHP_SATA_PORT0_CJPAT_REG_START 0x0045a740
#define BCHP_SATA_PORT0_CJPAT_REG_END 0x0045a764
#define BCHP_SATA_PORT1_CTRL_REG_START 0x0045a780
#define BCHP_SATA_PORT1_CTRL_REG_END 0x0045a7b0
#define BCHP_SATA_PORT1_CJPAT_REG_START 0x0045a7c0
#define BCHP_SATA_PORT1_CJPAT_REG_END 0x0045a7e4
#define BCHP_SATA_LEG_PCICFG_REG_START 0x0045a800
#define BCHP_SATA_LEG_PCICFG_REG_END 0x0045a880
#define BCHP_SATA_PORT0_LEG_S1_REG_START 0x0045a900
#define BCHP_SATA_PORT0_LEG_S1_REG_END 0x0045a934
#define BCHP_SATA_PORT0_LEG_S2_REG_START 0x0045a940
#define BCHP_SATA_PORT0_LEG_S2_REG_END 0x0045a954
#define BCHP_SATA_PORT0_LEG_S3_REG_START 0x0045a958
#define BCHP_SATA_PORT0_LEG_S3_REG_END 0x0045a998
#define BCHP_SATA_PORT1_LEG_S1_REG_START 0x0045aa00
#define BCHP_SATA_PORT1_LEG_S1_REG_END 0x0045aa34
#define BCHP_SATA_PORT1_LEG_S2_REG_START 0x0045aa40
#define BCHP_SATA_PORT1_LEG_S2_REG_END 0x0045aa54
#define BCHP_SATA_PORT1_LEG_S3_REG_START 0x0045aa58
#define BCHP_SATA_PORT1_LEG_S3_REG_END 0x0045aa98
#define BCHP_RFM_SYSCLK_REG_START 0x0045c000
#define BCHP_RFM_SYSCLK_REG_END 0x0045c124
#define BCHP_RFM_CLK27_REG_START 0x0045c000
#define BCHP_RFM_CLK27_REG_END 0x0045c470
#define BCHP_RFM_L2_REG_START 0x0045cc00
#define BCHP_RFM_L2_REG_END 0x0045cc2c
#define BCHP_RFM_GRB_REG_START 0x0045d000
#define BCHP_RFM_GRB_REG_END 0x0045d00c
#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_START 0x00460000
#define BCHP_PCIE_0_RC_CFG_TYPE1_REG_END 0x0046003c
#define BCHP_PCIE_0_RC_CFG_PM_REG_START 0x00460048
#define BCHP_PCIE_0_RC_CFG_PM_REG_END 0x0046004c
#define BCHP_PCIE_0_RC_CFG_PCIE_REG_START 0x004600ac
#define BCHP_PCIE_0_RC_CFG_PCIE_REG_END 0x004600e4
#define BCHP_PCIE_0_RC_CFG_AER_REG_START 0x00460100
#define BCHP_PCIE_0_RC_CFG_AER_REG_END 0x00460134
#define BCHP_PCIE_0_RC_CFG_VC_REG_START 0x00460160
#define BCHP_PCIE_0_RC_CFG_VC_REG_END 0x00460178
#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_START 0x00460180
#define BCHP_PCIE_0_RC_CFG_VENDOR_REG_END 0x004601a4
#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_START 0x00460404
#define BCHP_PCIE_0_RC_CFG_PRIV0_REG_END 0x00460418
#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_START 0x00460428
#define BCHP_PCIE_0_RC_CFG_PRIV1_REG_END 0x00460630
#define BCHP_PCIE_0_RC_TL_REG_START 0x00460800
#define BCHP_PCIE_0_RC_TL_REG_END 0x00460998
#define BCHP_PCIE_0_RC_DL_REG_START 0x00461000
#define BCHP_PCIE_0_RC_DL_REG_END 0x00461424
#define BCHP_PCIE_0_RC_PL_REG_START 0x00461800
#define BCHP_PCIE_0_RC_PL_REG_END 0x00461e1c
#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_START 0x00462000
#define BCHP_PCIE_0_EP_CFG_TYPE0_REG_END 0x0046203c
#define BCHP_PCIE_0_EP_CFG_PM_REG_START 0x00462048
#define BCHP_PCIE_0_EP_CFG_PM_REG_END 0x0046204c
#define BCHP_PCIE_0_EP_CFG_VPD_REG_START 0x00462050
#define BCHP_PCIE_0_EP_CFG_VPD_REG_END 0x00462054
#define BCHP_PCIE_0_EP_CFG_MSI_REG_START 0x00462058
#define BCHP_PCIE_0_EP_CFG_MSI_REG_END 0x00462064
#define BCHP_PCIE_0_EP_CFG_MSIX_REG_START 0x004620a0
#define BCHP_PCIE_0_EP_CFG_MSIX_REG_END 0x004620a8
#define BCHP_PCIE_0_EP_CFG_PCIE_REG_START 0x004620ac
#define BCHP_PCIE_0_EP_CFG_PCIE_REG_END 0x004620e4
#define BCHP_PCIE_0_EP_CFG_AER_REG_START 0x00462100
#define BCHP_PCIE_0_EP_CFG_AER_REG_END 0x00462134
#define BCHP_PCIE_0_EP_CFG_DEV_REG_START 0x0046213c
#define BCHP_PCIE_0_EP_CFG_DEV_REG_END 0x00462144
#define BCHP_PCIE_0_EP_CFG_PB_REG_START 0x00462150
#define BCHP_PCIE_0_EP_CFG_PB_REG_END 0x0046215c
#define BCHP_PCIE_0_EP_CFG_VC_REG_START 0x00462160
#define BCHP_PCIE_0_EP_CFG_VC_REG_END 0x00462178
#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_START 0x00462180
#define BCHP_PCIE_0_EP_CFG_VENDOR_REG_END 0x004621a4
#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_START 0x00462404
#define BCHP_PCIE_0_EP_CFG_PRIV0_REG_END 0x00462418
#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_START 0x00462428
#define BCHP_PCIE_0_EP_CFG_PRIV1_REG_END 0x00462630
#define BCHP_PCIE_0_EP_TL_REG_START 0x00462800
#define BCHP_PCIE_0_EP_TL_REG_END 0x00462998
#define BCHP_PCIE_0_EP_DL_REG_START 0x00463000
#define BCHP_PCIE_0_EP_DL_REG_END 0x00463424
#define BCHP_PCIE_0_EP_PL_REG_START 0x00463800
#define BCHP_PCIE_0_EP_PL_REG_END 0x00463e1c
#define BCHP_PCIE_0_MISC_REG_START 0x00464000
#define BCHP_PCIE_0_MISC_REG_END 0x004640cc
#define BCHP_PCIE_0_MISC_PERST_REG_START 0x00464100
#define BCHP_PCIE_0_MISC_PERST_REG_END 0x00464104
#define BCHP_PCIE_0_MISC_HARD_REG_START 0x00464200
#define BCHP_PCIE_0_MISC_HARD_REG_END 0x00464204
#define BCHP_PCIE_0_INTR2_REG_START 0x00464300
#define BCHP_PCIE_0_INTR2_REG_END 0x0046432c
#define BCHP_PCIE_0_DMA_REG_START 0x00464400
#define BCHP_PCIE_0_DMA_REG_END 0x0046446c
#define BCHP_PCIE_0_MSI_INTR2_REG_START 0x00464500
#define BCHP_PCIE_0_MSI_INTR2_REG_END 0x0046452c
#define BCHP_PCIE_0_EXT_CFG_REG_START 0x00468000
#define BCHP_PCIE_0_EXT_CFG_REG_END 0x00469008
#define BCHP_PCIE_0_RGR1_REG_START 0x00469200
#define BCHP_PCIE_0_RGR1_REG_END 0x00469210
#define BCHP_PCIE_0_RG_REG_START 0x00469300
#define BCHP_PCIE_0_RG_REG_END 0x0046930c
#define BCHP_USB_CAPS_REG_START 0x00470000
#define BCHP_USB_CAPS_REG_END 0x0047002c
#define BCHP_USB_GR_BRIDGE_REG_START 0x00470100
#define BCHP_USB_GR_BRIDGE_REG_END 0x0047010c
#define BCHP_USB_INTR2_REG_START 0x00470180
#define BCHP_USB_INTR2_REG_END 0x004701ac
#define BCHP_USB_CTRL_REG_START 0x00470200
#define BCHP_USB_CTRL_REG_END 0x004702fc
#define BCHP_USB_EHCI_REG_START 0x00470300
#define BCHP_USB_EHCI_REG_END 0x004703a4
#define BCHP_USB_OHCI_REG_START 0x00470400
#define BCHP_USB_OHCI_REG_END 0x00470454
#define BCHP_USB_EHCI1_REG_START 0x00470500
#define BCHP_USB_EHCI1_REG_END 0x004705a4
#define BCHP_USB_OHCI1_REG_START 0x00470600
#define BCHP_USB_OHCI1_REG_END 0x00470654
#define BCHP_USB_XHCI_REG_START 0x00471000
#define BCHP_USB_XHCI_REG_END 0x00471ffc
#define BCHP_USB_BDC_REG_START 0x00472000
#define BCHP_USB_BDC_REG_END 0x00472fc0
#define BCHP_PCIE_1_RC_CFG_TYPE1_REG_START 0x00490000
#define BCHP_PCIE_1_RC_CFG_TYPE1_REG_END 0x0049003c
#define BCHP_PCIE_1_RC_CFG_PM_REG_START 0x00490048
#define BCHP_PCIE_1_RC_CFG_PM_REG_END 0x0049004c
#define BCHP_PCIE_1_RC_CFG_PCIE_REG_START 0x004900ac
#define BCHP_PCIE_1_RC_CFG_PCIE_REG_END 0x004900e4
#define BCHP_PCIE_1_RC_CFG_AER_REG_START 0x00490100
#define BCHP_PCIE_1_RC_CFG_AER_REG_END 0x00490134
#define BCHP_PCIE_1_RC_CFG_VC_REG_START 0x00490160
#define BCHP_PCIE_1_RC_CFG_VC_REG_END 0x00490178
#define BCHP_PCIE_1_RC_CFG_VENDOR_REG_START 0x00490180
#define BCHP_PCIE_1_RC_CFG_VENDOR_REG_END 0x004901a4
#define BCHP_PCIE_1_RC_CFG_PRIV0_REG_START 0x00490404
#define BCHP_PCIE_1_RC_CFG_PRIV0_REG_END 0x00490418
#define BCHP_PCIE_1_RC_CFG_PRIV1_REG_START 0x00490428
#define BCHP_PCIE_1_RC_CFG_PRIV1_REG_END 0x00490630
#define BCHP_PCIE_1_RC_TL_REG_START 0x00490800
#define BCHP_PCIE_1_RC_TL_REG_END 0x00490998
#define BCHP_PCIE_1_RC_DL_REG_START 0x00491000
#define BCHP_PCIE_1_RC_DL_REG_END 0x00491424
#define BCHP_PCIE_1_RC_PL_REG_START 0x00491800
#define BCHP_PCIE_1_RC_PL_REG_END 0x00491e1c
#define BCHP_PCIE_1_EP_CFG_TYPE0_REG_START 0x00492000
#define BCHP_PCIE_1_EP_CFG_TYPE0_REG_END 0x0049203c
#define BCHP_PCIE_1_EP_CFG_PM_REG_START 0x00492048
#define BCHP_PCIE_1_EP_CFG_PM_REG_END 0x0049204c
#define BCHP_PCIE_1_EP_CFG_VPD_REG_START 0x00492050
#define BCHP_PCIE_1_EP_CFG_VPD_REG_END 0x00492054
#define BCHP_PCIE_1_EP_CFG_MSI_REG_START 0x00492058
#define BCHP_PCIE_1_EP_CFG_MSI_REG_END 0x00492064
#define BCHP_PCIE_1_EP_CFG_MSIX_REG_START 0x004920a0
#define BCHP_PCIE_1_EP_CFG_MSIX_REG_END 0x004920a8
#define BCHP_PCIE_1_EP_CFG_PCIE_REG_START 0x004920ac
#define BCHP_PCIE_1_EP_CFG_PCIE_REG_END 0x004920e4
#define BCHP_PCIE_1_EP_CFG_AER_REG_START 0x00492100
#define BCHP_PCIE_1_EP_CFG_AER_REG_END 0x00492134
#define BCHP_PCIE_1_EP_CFG_DEV_REG_START 0x0049213c
#define BCHP_PCIE_1_EP_CFG_DEV_REG_END 0x00492144
#define BCHP_PCIE_1_EP_CFG_PB_REG_START 0x00492150
#define BCHP_PCIE_1_EP_CFG_PB_REG_END 0x0049215c
#define BCHP_PCIE_1_EP_CFG_VC_REG_START 0x00492160
#define BCHP_PCIE_1_EP_CFG_VC_REG_END 0x00492178
#define BCHP_PCIE_1_EP_CFG_VENDOR_REG_START 0x00492180
#define BCHP_PCIE_1_EP_CFG_VENDOR_REG_END 0x004921a4
#define BCHP_PCIE_1_EP_CFG_PRIV0_REG_START 0x00492404
#define BCHP_PCIE_1_EP_CFG_PRIV0_REG_END 0x00492418
#define BCHP_PCIE_1_EP_CFG_PRIV1_REG_START 0x00492428
#define BCHP_PCIE_1_EP_CFG_PRIV1_REG_END 0x00492630
#define BCHP_PCIE_1_EP_TL_REG_START 0x00492800
#define BCHP_PCIE_1_EP_TL_REG_END 0x00492998
#define BCHP_PCIE_1_EP_DL_REG_START 0x00493000
#define BCHP_PCIE_1_EP_DL_REG_END 0x00493424
#define BCHP_PCIE_1_EP_PL_REG_START 0x00493800
#define BCHP_PCIE_1_EP_PL_REG_END 0x00493e1c
#define BCHP_PCIE_1_MISC_REG_START 0x00494000
#define BCHP_PCIE_1_MISC_REG_END 0x004940cc
#define BCHP_PCIE_1_MISC_PERST_REG_START 0x00494100
#define BCHP_PCIE_1_MISC_PERST_REG_END 0x00494104
#define BCHP_PCIE_1_MISC_HARD_REG_START 0x00494200
#define BCHP_PCIE_1_MISC_HARD_REG_END 0x00494204
#define BCHP_PCIE_1_INTR2_REG_START 0x00494300
#define BCHP_PCIE_1_INTR2_REG_END 0x0049432c
#define BCHP_PCIE_1_DMA_REG_START 0x00494400
#define BCHP_PCIE_1_DMA_REG_END 0x0049446c
#define BCHP_PCIE_1_MSI_INTR2_REG_START 0x00494500
#define BCHP_PCIE_1_MSI_INTR2_REG_END 0x0049452c
#define BCHP_PCIE_1_EXT_CFG_REG_START 0x00498000
#define BCHP_PCIE_1_EXT_CFG_REG_END 0x00499008
#define BCHP_PCIE_1_RGR1_REG_START 0x00499200
#define BCHP_PCIE_1_RGR1_REG_END 0x00499210
#define BCHP_PCIE_1_RG_REG_START 0x00499300
#define BCHP_PCIE_1_RG_REG_END 0x0049930c
#define BCHP_AVS_CPU_PROG_MEM_REG_START 0x004c0000
#define BCHP_AVS_CPU_PROG_MEM_REG_END 0x004c2ffc
#define BCHP_AVS_CPU_DATA_MEM_REG_START 0x004c4000
#define BCHP_AVS_CPU_DATA_MEM_REG_END 0x004c4bfc
#define BCHP_AVS_CPU_CORE_REGS_REG_START 0x004c8000
#define BCHP_AVS_CPU_CORE_REGS_REG_END 0x004c80fc
#define BCHP_AVS_CPU_AUX_REGS_REG_START 0x004ca000
#define BCHP_AVS_CPU_AUX_REGS_REG_END 0x004cb058
#define BCHP_AVS_UART_REG_START 0x004d0000
#define BCHP_AVS_UART_REG_END 0x004d0ffc
#define BCHP_AVS_CPU_L2_REG_START 0x004d1100
#define BCHP_AVS_CPU_L2_REG_END 0x004d112c
#define BCHP_AVS_HOST_L2_REG_START 0x004d1200
#define BCHP_AVS_HOST_L2_REG_END 0x004d1244
#define BCHP_AVS_CPU_CTRL_REG_START 0x004d1300
#define BCHP_AVS_CPU_CTRL_REG_END 0x004d1330
#define BCHP_AVS_BSTI_REG_START 0x004d1400
#define BCHP_AVS_BSTI_REG_END 0x004d1404
#define BCHP_AVS_TMON_REG_START 0x004d1500
#define BCHP_AVS_TMON_REG_END 0x004d1524
#define BCHP_AVS_TOP_CTRL_REG_START 0x004d1800
#define BCHP_AVS_TOP_CTRL_REG_END 0x004d18d8
#define BCHP_AVS_HW_MNTR_REG_START 0x004d2000
#define BCHP_AVS_HW_MNTR_REG_END 0x004d20c8
#define BCHP_AVS_PVT_MNTR_CONFIG_REG_START 0x004d2100
#define BCHP_AVS_PVT_MNTR_CONFIG_REG_END 0x004d2124
#define BCHP_AVS_RO_REGISTERS_0_REG_START 0x004d2200
#define BCHP_AVS_RO_REGISTERS_0_REG_END 0x004d22e0
#define BCHP_AVS_RO_REGISTERS_1_REG_START 0x004d2800
#define BCHP_AVS_RO_REGISTERS_1_REG_END 0x004d2804
#define BCHP_AVS_ROSC_THRESHOLD_1_REG_START 0x004d2d00
#define BCHP_AVS_ROSC_THRESHOLD_1_REG_END 0x004d2dfc
#define BCHP_AVS_ROSC_THRESHOLD_2_REG_START 0x004d2e00
#define BCHP_AVS_ROSC_THRESHOLD_2_REG_END 0x004d2efc
#define BCHP_AVS_WDOG_REG_START 0x004d3000
#define BCHP_AVS_WDOG_REG_END 0x004d3ffc
#define BCHP_AVS_PMB_S_000_REG_START 0x004d4000
#define BCHP_AVS_PMB_S_000_REG_END 0x004d4024
#define BCHP_AVS_PMB_S_001_REG_START 0x004d4040
#define BCHP_AVS_PMB_S_001_REG_END 0x004d4064
#define BCHP_AVS_PMB_S_002_REG_START 0x004d4080
#define BCHP_AVS_PMB_S_002_REG_END 0x004d40a4
#define BCHP_AVS_PMB_S_003_REG_START 0x004d40c0
#define BCHP_AVS_PMB_S_003_REG_END 0x004d40e4
#define BCHP_AVS_PMB_S_004_REG_START 0x004d4100
#define BCHP_AVS_PMB_S_004_REG_END 0x004d4124
#define BCHP_AVS_PMB_S_005_REG_START 0x004d4140
#define BCHP_AVS_PMB_S_005_REG_END 0x004d4164
#define BCHP_AVS_PMB_S_006_REG_START 0x004d4180
#define BCHP_AVS_PMB_S_006_REG_END 0x004d41a4
#define BCHP_AVS_PMB_S_007_REG_START 0x004d41c0
#define BCHP_AVS_PMB_S_007_REG_END 0x004d41e4
#define BCHP_AVS_PMB_S_008_REG_START 0x004d4200
#define BCHP_AVS_PMB_S_008_REG_END 0x004d4224
#define BCHP_AVS_PMB_S_009_REG_START 0x004d4240
#define BCHP_AVS_PMB_S_009_REG_END 0x004d4264
#define BCHP_AVS_PMB_S_010_REG_START 0x004d4280
#define BCHP_AVS_PMB_S_010_REG_END 0x004d42a4
#define BCHP_AVS_PMB_S_011_REG_START 0x004d42c0
#define BCHP_AVS_PMB_S_011_REG_END 0x004d42e4
#define BCHP_AVS_PMB_S_012_REG_START 0x004d4300
#define BCHP_AVS_PMB_S_012_REG_END 0x004d4324
#define BCHP_AVS_PMB_S_013_REG_START 0x004d4340
#define BCHP_AVS_PMB_S_013_REG_END 0x004d4364
#define BCHP_AVS_PMB_S_014_REG_START 0x004d4380
#define BCHP_AVS_PMB_S_014_REG_END 0x004d43a4
#define BCHP_AVS_PMB_S_015_REG_START 0x004d43c0
#define BCHP_AVS_PMB_S_015_REG_END 0x004d43e4
#define BCHP_AVS_PMB_S_016_REG_START 0x004d4400
#define BCHP_AVS_PMB_S_016_REG_END 0x004d4424
#define BCHP_AVS_PMB_S_017_REG_START 0x004d4440
#define BCHP_AVS_PMB_S_017_REG_END 0x004d4464
#define BCHP_AVS_PMB_S_018_REG_START 0x004d4480
#define BCHP_AVS_PMB_S_018_REG_END 0x004d44a4
#define BCHP_AVS_PMB_S_019_REG_START 0x004d44c0
#define BCHP_AVS_PMB_S_019_REG_END 0x004d44e4
#define BCHP_AVS_PMB_S_020_REG_START 0x004d4500
#define BCHP_AVS_PMB_S_020_REG_END 0x004d4524
#define BCHP_AVS_PMB_S_021_REG_START 0x004d4540
#define BCHP_AVS_PMB_S_021_REG_END 0x004d4564
#define BCHP_AVS_PMB_S_022_REG_START 0x004d4580
#define BCHP_AVS_PMB_S_022_REG_END 0x004d45a4
#define BCHP_AVS_PMB_S_023_REG_START 0x004d45c0
#define BCHP_AVS_PMB_S_023_REG_END 0x004d45e4
#define BCHP_AVS_PMB_S_024_REG_START 0x004d4600
#define BCHP_AVS_PMB_S_024_REG_END 0x004d4624
#define BCHP_AVS_PMB_S_025_REG_START 0x004d4640
#define BCHP_AVS_PMB_S_025_REG_END 0x004d4664
#define BCHP_AVS_PMB_REGISTERS_REG_START 0x004d6000
#define BCHP_AVS_PMB_REGISTERS_REG_END 0x004d6008
#define BCHP_CLKGEN_REG_START 0x004e0000
#define BCHP_CLKGEN_REG_END 0x004e0680
#define BCHP_VCXO_0_RM_REG_START 0x004e2800
#define BCHP_VCXO_0_RM_REG_END 0x004e2838
#define BCHP_VCXO_1_RM_REG_START 0x004e2880
#define BCHP_VCXO_1_RM_REG_END 0x004e28b8
#define BCHP_CLKGEN_GR_REG_START 0x004e3000
#define BCHP_CLKGEN_GR_REG_END 0x004e300c
#define BCHP_CLKGEN_INTR2_REG_START 0x004e4800
#define BCHP_CLKGEN_INTR2_REG_END 0x004e4844
#define BCHP_AVS_RANGE_BLOCKER_REG_START 0x004e5000
#define BCHP_AVS_RANGE_BLOCKER_REG_END 0x004e5058
#define BCHP_PROD_OTP_GRB_REG_START 0x004e6000
#define BCHP_PROD_OTP_GRB_REG_END 0x004e600c
#define BCHP_JTAG_OTP_REG_START 0x004e6100
#define BCHP_JTAG_OTP_REG_END 0x004e615c
#define BCHP_BVN_SEC_0_REG_START 0x004f0000
#define BCHP_BVN_SEC_0_REG_END 0x004f0cfc
#define BCHP_BVN_SEC_1_REG_START 0x004f2000
#define BCHP_BVN_SEC_1_REG_END 0x004f2cfc
#define BCHP_BVN_SEC_GR_REG_START 0x004f4000
#define BCHP_BVN_SEC_GR_REG_END 0x004f400c
#define BCHP_MFD_0_REG_START 0x00600000
#define BCHP_MFD_0_REG_END 0x006001fc
#define BCHP_MFD_1_REG_START 0x00600400
#define BCHP_MFD_1_REG_END 0x006005fc
#define BCHP_MFD_2_REG_START 0x00600800
#define BCHP_MFD_2_REG_END 0x006009fc
#define BCHP_MFD_3_REG_START 0x00600c00
#define BCHP_MFD_3_REG_END 0x00600dfc
#define BCHP_VFD_0_REG_START 0x00602000
#define BCHP_VFD_0_REG_END 0x006021fc
#define BCHP_VFD_1_REG_START 0x00602200
#define BCHP_VFD_1_REG_END 0x006023fc
#define BCHP_VFD_2_REG_START 0x00602400
#define BCHP_VFD_2_REG_END 0x006025fc
#define BCHP_VFD_3_REG_START 0x00602600
#define BCHP_VFD_3_REG_END 0x006027fc
#define BCHP_VFD_4_REG_START 0x00602800
#define BCHP_VFD_4_REG_END 0x006029fc
#define BCHP_VFD_5_REG_START 0x00602a00
#define BCHP_VFD_5_REG_END 0x00602bfc
#define BCHP_RDC_REG_START 0x00603000
#define BCHP_RDC_REG_END 0x00603cfc
#define BCHP_BVNF_INTR2_0_REG_START 0x00604000
#define BCHP_BVNF_INTR2_0_REG_END 0x0060402c
#define BCHP_BVNF_INTR2_1_REG_START 0x00604100
#define BCHP_BVNF_INTR2_1_REG_END 0x0060412c
#define BCHP_BVNF_INTR2_3_REG_START 0x00604300
#define BCHP_BVNF_INTR2_3_REG_END 0x0060432c
#define BCHP_BVNF_INTR2_5_REG_START 0x00604500
#define BCHP_BVNF_INTR2_5_REG_END 0x0060452c
#define BCHP_BVNF_INTR2_6_REG_START 0x00604600
#define BCHP_BVNF_INTR2_6_REG_END 0x0060462c
#define BCHP_BVNF_INTR2_7_REG_START 0x00604700
#define BCHP_BVNF_INTR2_7_REG_END 0x0060472c
#define BCHP_BVNF_INTR2_9_REG_START 0x00604900
#define BCHP_BVNF_INTR2_9_REG_END 0x0060492c
#define BCHP_BVNF_INTR2_15_REG_START 0x00604f00
#define BCHP_BVNF_INTR2_15_REG_END 0x00604f2c
#define BCHP_BVNF_INTR2_16_REG_START 0x00605000
#define BCHP_BVNF_INTR2_16_REG_END 0x0060502c
#define BCHP_BVNF_INTR2_18_REG_START 0x00605200
#define BCHP_BVNF_INTR2_18_REG_END 0x0060522c
#define BCHP_FMISC_REG_START 0x00606000
#define BCHP_FMISC_REG_END 0x00606020
#define BCHP_SCL_0_REG_START 0x00620000
#define BCHP_SCL_0_REG_END 0x006203fc
#define BCHP_SCL_1_REG_START 0x00620400
#define BCHP_SCL_1_REG_END 0x006207fc
#define BCHP_SCL_2_REG_START 0x00620800
#define BCHP_SCL_2_REG_END 0x00620bfc
#define BCHP_SCL_3_REG_START 0x00620c00
#define BCHP_SCL_3_REG_END 0x00620ffc
#define BCHP_SCL_4_REG_START 0x00621000
#define BCHP_SCL_4_REG_END 0x006213fc
#define BCHP_SCL_5_REG_START 0x00621400
#define BCHP_SCL_5_REG_END 0x006217fc
#define BCHP_VNET_F_REG_START 0x00622000
#define BCHP_VNET_F_REG_END 0x006221fc
#define BCHP_VNET_B_REG_START 0x00622200
#define BCHP_VNET_B_REG_END 0x006223fc
#define BCHP_MMISC_REG_START 0x00622800
#define BCHP_MMISC_REG_END 0x00622828
#define BCHP_LBOX_0_REG_START 0x00624000
#define BCHP_LBOX_0_REG_END 0x00624070
#define BCHP_XSRC_0_REG_START 0x00624800
#define BCHP_XSRC_0_REG_END 0x00624bfc
#define BCHP_XSRC_1_REG_START 0x00624c00
#define BCHP_XSRC_1_REG_END 0x00624ffc
#define BCHP_DNR_0_REG_START 0x00626000
#define BCHP_DNR_0_REG_END 0x006260a4
#define BCHP_DNR_1_REG_START 0x00626200
#define BCHP_DNR_1_REG_END 0x006262a4
#define BCHP_DNR_2_REG_START 0x00626400
#define BCHP_DNR_2_REG_END 0x006264a4
#define BCHP_DNR_3_REG_START 0x00626600
#define BCHP_DNR_3_REG_END 0x006266a4
#define BCHP_BVNM_INTR2_0_REG_START 0x00627000
#define BCHP_BVNM_INTR2_0_REG_END 0x0062702c
#define BCHP_BVNM_INTR2_1_REG_START 0x00627100
#define BCHP_BVNM_INTR2_1_REG_END 0x0062712c
#define BCHP_CAP_0_REG_START 0x00640000
#define BCHP_CAP_0_REG_END 0x0064010c
#define BCHP_CAP_1_REG_START 0x00640200
#define BCHP_CAP_1_REG_END 0x0064030c
#define BCHP_CAP_2_REG_START 0x00640400
#define BCHP_CAP_2_REG_END 0x0064050c
#define BCHP_CAP_3_REG_START 0x00640600
#define BCHP_CAP_3_REG_END 0x0064070c
#define BCHP_CAP_4_REG_START 0x00640800
#define BCHP_CAP_4_REG_END 0x0064090c
#define BCHP_CAP_5_REG_START 0x00640a00
#define BCHP_CAP_5_REG_END 0x00640b0c
#define BCHP_GFD_0_REG_START 0x00641000
#define BCHP_GFD_0_REG_END 0x0064122c
#define BCHP_GFD_1_REG_START 0x00641400
#define BCHP_GFD_1_REG_END 0x0064162c
#define BCHP_GFD_2_REG_START 0x00641800
#define BCHP_GFD_2_REG_END 0x00641a2c
#define BCHP_GFD_3_REG_START 0x00641c00
#define BCHP_GFD_3_REG_END 0x00641e2c
#define BCHP_CMP_0_REG_START 0x00642000
#define BCHP_CMP_0_REG_END 0x00642b28
#define BCHP_CMP_1_REG_START 0x00643000
#define BCHP_CMP_1_REG_END 0x00643b1c
#define BCHP_CMP_2_REG_START 0x00644000
#define BCHP_CMP_2_REG_END 0x0064461c
#define BCHP_CMP_3_REG_START 0x00645000
#define BCHP_CMP_3_REG_END 0x0064561c
#define BCHP_TNT_CMP_0_V0_REG_START 0x00645800
#define BCHP_TNT_CMP_0_V0_REG_END 0x006458a4
#define BCHP_MASK_0_REG_START 0x00645c00
#define BCHP_MASK_0_REG_END 0x00645c20
#define BCHP_PEP_CMP_0_V0_REG_START 0x00646000
#define BCHP_PEP_CMP_0_V0_REG_END 0x00647284
#define BCHP_BVNB_INTR2_REG_START 0x00648000
#define BCHP_BVNB_INTR2_REG_END 0x0064802c
#define BCHP_BMISC_REG_START 0x00648400
#define BCHP_BMISC_REG_END 0x0064841c
#define BCHP_DMISC_REG_START 0x00680000
#define BCHP_DMISC_REG_END 0x0068001c
#define BCHP_MVP_TOP_0_REG_START 0x00688000
#define BCHP_MVP_TOP_0_REG_END 0x00688038
#define BCHP_SIOB_0_REG_START 0x00688200
#define BCHP_SIOB_0_REG_END 0x006882fc
#define BCHP_HSCL_0_REG_START 0x00688400
#define BCHP_HSCL_0_REG_END 0x006887fc
#define BCHP_HD_ANR_MCTF_0_REG_START 0x00689000
#define BCHP_HD_ANR_MCTF_0_REG_END 0x0068927c
#define BCHP_HD_ANR_AND_0_REG_START 0x00689800
#define BCHP_HD_ANR_AND_0_REG_END 0x00689888
#define BCHP_MDI_TOP_0_REG_START 0x0068a000
#define BCHP_MDI_TOP_0_REG_END 0x0068a0fc
#define BCHP_MDI_FCB_0_REG_START 0x0068a400
#define BCHP_MDI_FCB_0_REG_END 0x0068a7fc
#define BCHP_MDI_PPB_0_REG_START 0x0068a800
#define BCHP_MDI_PPB_0_REG_END 0x0068abfc
#define BCHP_MDI_FCN_0_REG_START 0x0068ac00
#define BCHP_MDI_FCN_0_REG_END 0x0068adfc
#define BCHP_MDI_MEMC_0_REG_START 0x0068ae00
#define BCHP_MDI_MEMC_0_REG_END 0x0068affc
#define BCHP_MVP_TOP_1_REG_START 0x00690000
#define BCHP_MVP_TOP_1_REG_END 0x00690038
#define BCHP_SIOB_1_REG_START 0x00690200
#define BCHP_SIOB_1_REG_END 0x006902fc
#define BCHP_HSCL_1_REG_START 0x00690400
#define BCHP_HSCL_1_REG_END 0x006907fc
#define BCHP_MDI_TOP_1_REG_START 0x00692000
#define BCHP_MDI_TOP_1_REG_END 0x006920fc
#define BCHP_MDI_PPB_1_REG_START 0x00692800
#define BCHP_MDI_PPB_1_REG_END 0x00692bfc
#define BCHP_MDI_FCN_1_REG_START 0x00692c00
#define BCHP_MDI_FCN_1_REG_END 0x00692dfc
#define BCHP_MVP_TOP_2_REG_START 0x00698000
#define BCHP_MVP_TOP_2_REG_END 0x00698038
#define BCHP_SIOB_2_REG_START 0x00698200
#define BCHP_SIOB_2_REG_END 0x006982fc
#define BCHP_HSCL_2_REG_START 0x00698400
#define BCHP_HSCL_2_REG_END 0x006987fc
#define BCHP_MDI_TOP_2_REG_START 0x0069a000
#define BCHP_MDI_TOP_2_REG_END 0x0069a0fc
#define BCHP_MDI_PPB_2_REG_START 0x0069a800
#define BCHP_MDI_PPB_2_REG_END 0x0069abfc
#define BCHP_MDI_FCN_2_REG_START 0x0069ac00
#define BCHP_MDI_FCN_2_REG_END 0x0069adfc
#define BCHP_MVP_TOP_3_REG_START 0x006a0000
#define BCHP_MVP_TOP_3_REG_END 0x006a0038
#define BCHP_SIOB_3_REG_START 0x006a0200
#define BCHP_SIOB_3_REG_END 0x006a02fc
#define BCHP_HSCL_3_REG_START 0x006a0400
#define BCHP_HSCL_3_REG_END 0x006a07fc
#define BCHP_MDI_TOP_3_REG_START 0x006a2000
#define BCHP_MDI_TOP_3_REG_END 0x006a20fc
#define BCHP_MDI_PPB_3_REG_START 0x006a2800
#define BCHP_MDI_PPB_3_REG_END 0x006a2bfc
#define BCHP_MDI_FCN_3_REG_START 0x006a2c00
#define BCHP_MDI_FCN_3_REG_END 0x006a2dfc
#define BCHP_MISC_REG_START 0x006e0000
#define BCHP_MISC_REG_END 0x006e00ac
#define BCHP_IT_0_REG_START 0x006e1000
#define BCHP_IT_0_REG_END 0x006e17fc
#define BCHP_IT_1_REG_START 0x006e2000
#define BCHP_IT_1_REG_END 0x006e27fc
#define BCHP_IT_2_REG_START 0x006e3000
#define BCHP_IT_2_REG_END 0x006e37fc
#define BCHP_VF_0_REG_START 0x006e4000
#define BCHP_VF_0_REG_END 0x006e4134
#define BCHP_VF_1_REG_START 0x006e4200
#define BCHP_VF_1_REG_END 0x006e4334
#define BCHP_SECAM_0_REG_START 0x006e4400
#define BCHP_SECAM_0_REG_END 0x006e4414
#define BCHP_SM_0_REG_START 0x006e4480
#define BCHP_SM_0_REG_END 0x006e44ac
#define BCHP_SDSRC_0_REG_START 0x006e4500
#define BCHP_SDSRC_0_REG_END 0x006e450c
#define BCHP_HDSRC_0_REG_START 0x006e4520
#define BCHP_HDSRC_0_REG_END 0x006e453c
#define BCHP_CSC_0_REG_START 0x006e4580
#define BCHP_CSC_0_REG_END 0x006e45b0
#define BCHP_CSC_1_REG_START 0x006e4600
#define BCHP_CSC_1_REG_END 0x006e4630
#define BCHP_RM_0_REG_START 0x006e4680
#define BCHP_RM_0_REG_END 0x006e46b0
#define BCHP_RM_1_REG_START 0x006e46c0
#define BCHP_RM_1_REG_END 0x006e46f0
#define BCHP_RM_2_REG_START 0x006e4700
#define BCHP_RM_2_REG_END 0x006e4730
#define BCHP_ANA_DEBUG_0_REG_START 0x006e4800
#define BCHP_ANA_DEBUG_0_REG_END 0x006e4844
#define BCHP_DVI_MISC_0_REG_START 0x006e4900
#define BCHP_DVI_MISC_0_REG_END 0x006e4900
#define BCHP_DVI_DTG_0_REG_START 0x006e5000
#define BCHP_DVI_DTG_0_REG_END 0x006e5488
#define BCHP_DVI_DTG_RM_0_REG_START 0x006e5800
#define BCHP_DVI_DTG_RM_0_REG_END 0x006e5830
#define BCHP_DVI_CSC_0_REG_START 0x006e5900
#define BCHP_DVI_CSC_0_REG_END 0x006e5940
#define BCHP_DVI_FC_0_REG_START 0x006e5a00
#define BCHP_DVI_FC_0_REG_END 0x006e5a04
#define BCHP_DVI_DVF_0_REG_START 0x006e5b00
#define BCHP_DVI_DVF_0_REG_END 0x006e5b18
#define BCHP_DVI_DEBUG_0_REG_START 0x006e5c00
#define BCHP_DVI_DEBUG_0_REG_END 0x006e5c44
#define BCHP_ITU656_DTG_0_REG_START 0x006e6000
#define BCHP_ITU656_DTG_0_REG_END 0x006e6488
#define BCHP_ITU656_CSC_0_REG_START 0x006e6600
#define BCHP_ITU656_CSC_0_REG_END 0x006e6630
#define BCHP_ITU656_DVF_0_REG_START 0x006e6700
#define BCHP_ITU656_DVF_0_REG_END 0x006e6718
#define BCHP_ITU656_0_REG_START 0x006e6800
#define BCHP_ITU656_0_REG_END 0x006e6820
#define BCHP_VEC_CFG_REG_START 0x006e6c00
#define BCHP_VEC_CFG_REG_END 0x006e6d78
#define BCHP_VIDEO_ENC_INTR2_REG_START 0x006e7000
#define BCHP_VIDEO_ENC_INTR2_REG_END 0x006e702c
#define BCHP_VIDEO_ENC_TPG_0_REG_START 0x006e7200
#define BCHP_VIDEO_ENC_TPG_0_REG_END 0x006e7320
#define BCHP_VIDEO_ENC_STG_0_REG_START 0x006e7400
#define BCHP_VIDEO_ENC_STG_0_REG_END 0x006e745c
#define BCHP_VIDEO_ENC_STG_1_REG_START 0x006e7500
#define BCHP_VIDEO_ENC_STG_1_REG_END 0x006e755c
#define BCHP_VIDEO_ENC_DECIM_0_REG_START 0x006e7600
#define BCHP_VIDEO_ENC_DECIM_0_REG_END 0x006e7608
#define BCHP_VIDEO_ENC_BP_FIFO_0_REG_START 0x006e7700
#define BCHP_VIDEO_ENC_BP_FIFO_0_REG_END 0x006e772c
#define BCHP_DVP_TVG_0_REG_START 0x006e7800
#define BCHP_DVP_TVG_0_REG_END 0x006e7888
#define BCHP_VBI_ENC_REG_START 0x006e8000
#define BCHP_VBI_ENC_REG_END 0x006e80a0
#define BCHP_CCE_0_REG_START 0x006e8400
#define BCHP_CCE_0_REG_END 0x006e8458
#define BCHP_CCE_1_REG_START 0x006e8500
#define BCHP_CCE_1_REG_END 0x006e8558
#define BCHP_WSE_0_REG_START 0x006e8600
#define BCHP_WSE_0_REG_END 0x006e8614
#define BCHP_WSE_1_REG_START 0x006e8700
#define BCHP_WSE_1_REG_END 0x006e8714
#define BCHP_CGMSAE_0_REG_START 0x006e8800
#define BCHP_CGMSAE_0_REG_END 0x006e8858
#define BCHP_CGMSAE_1_REG_START 0x006e8900
#define BCHP_CGMSAE_1_REG_END 0x006e8958
#define BCHP_TTE_0_REG_START 0x006e8a00
#define BCHP_TTE_0_REG_END 0x006e8a28
#define BCHP_TTE_1_REG_START 0x006e8b00
#define BCHP_TTE_1_REG_END 0x006e8b28
#define BCHP_GSE_0_REG_START 0x006e8c00
#define BCHP_GSE_0_REG_END 0x006e8c80
#define BCHP_GSE_1_REG_START 0x006e8d00
#define BCHP_GSE_1_REG_END 0x006e8d80
#define BCHP_AMOLE_0_REG_START 0x006e8e00
#define BCHP_AMOLE_0_REG_END 0x006e8e8c
#define BCHP_AMOLE_1_REG_START 0x006e8f00
#define BCHP_AMOLE_1_REG_END 0x006e8f8c
#define BCHP_CCE_ANCIL_0_REG_START 0x006e9000
#define BCHP_CCE_ANCIL_0_REG_END 0x006e9054
#define BCHP_WSE_ANCIL_0_REG_START 0x006e9100
#define BCHP_WSE_ANCIL_0_REG_END 0x006e910c
#define BCHP_TTE_ANCIL_0_REG_START 0x006e9200
#define BCHP_TTE_ANCIL_0_REG_END 0x006e9228
#define BCHP_GSE_ANCIL_0_REG_START 0x006e9300
#define BCHP_GSE_ANCIL_0_REG_END 0x006e9380
#define BCHP_AMOLE_ANCIL_0_REG_START 0x006e9400
#define BCHP_AMOLE_ANCIL_0_REG_END 0x006e948c
#define BCHP_ANCI656_ANCIL_0_REG_START 0x006e9500
#define BCHP_ANCI656_ANCIL_0_REG_END 0x006e9524
#define BCHP_DVP_HR_REG_START 0x006f0000
#define BCHP_DVP_HR_REG_END 0x006f03fc
#define BCHP_DVP_HR_INTR2_REG_START 0x006f0400
#define BCHP_DVP_HR_INTR2_REG_END 0x006f042c
#define BCHP_DVP_HR_KEY_RAM_REG_START 0x006f0600
#define BCHP_DVP_HR_KEY_RAM_REG_END 0x006f0614
#define BCHP_HDMI_RX_FE_SHARED_REG_START 0x006f0800
#define BCHP_HDMI_RX_FE_SHARED_REG_END 0x006f090c
#define BCHP_HDMI_RX_SHARED_REG_START 0x006f0c00
#define BCHP_HDMI_RX_SHARED_REG_END 0x006f0c28
#define BCHP_HDMI_RX_FE_0_REG_START 0x006f1000
#define BCHP_HDMI_RX_FE_0_REG_END 0x006f11fc
#define BCHP_HDMI_RX_EQ_0_REG_START 0x006f1200
#define BCHP_HDMI_RX_EQ_0_REG_END 0x006f13fc
#define BCHP_HDMI_RX_0_REG_START 0x006f2000
#define BCHP_HDMI_RX_0_REG_END 0x006f27fc
#define BCHP_HDCP2_RX_0_REG_START 0x006f2800
#define BCHP_HDCP2_RX_0_REG_END 0x006f29fc
#define BCHP_HDMI_RX_INTR2_0_REG_START 0x006f2a00
#define BCHP_HDMI_RX_INTR2_0_REG_END 0x006f2a2c
#define BCHP_HDMI_RX_BANK2_INTR2_0_REG_START 0x006f2a40
#define BCHP_HDMI_RX_BANK2_INTR2_0_REG_END 0x006f2a6c
#define BCHP_HDMI_RX_HAE_INTR2_0_REG_START 0x006f2a80
#define BCHP_HDMI_RX_HAE_INTR2_0_REG_END 0x006f2aac
#define BCHP_HDCP2_RX_HAE_INTR2_0_REG_START 0x006f2ac0
#define BCHP_HDCP2_RX_HAE_INTR2_0_REG_END 0x006f2ad4
#define BCHP_HD_DVI_0_REG_START 0x006f4000
#define BCHP_HD_DVI_0_REG_END 0x006f427c
#define BCHP_DVP_HR_TMR_REG_START 0x006f4cc0
#define BCHP_DVP_HR_TMR_REG_END 0x006f4cfc
#define BCHP_DVP_HT_REG_START 0x006f8000
#define BCHP_DVP_HT_REG_END 0x006f8114
#define BCHP_HDMI_REG_START 0x006f8800
#define BCHP_HDMI_REG_END 0x006f8afc
#define BCHP_HDMI_TX_AUTO_I2C_REG_START 0x006f8b00
#define BCHP_HDMI_TX_AUTO_I2C_REG_END 0x006f8dfc
#define BCHP_HDMI_TX_PHY_REG_START 0x006f8e00
#define BCHP_HDMI_TX_PHY_REG_END 0x006f8e7c
#define BCHP_HDMI_RM_REG_START 0x006f8e80
#define BCHP_HDMI_RM_REG_END 0x006f8eb8
#define BCHP_HDMI_TX_INTR2_REG_START 0x006f8f00
#define BCHP_HDMI_TX_INTR2_REG_END 0x006f8f2c
#define BCHP_HDMI_TX_SCDC_INTR2_0_REG_START 0x006f8f80
#define BCHP_HDMI_TX_SCDC_INTR2_0_REG_END 0x006f8fac
#define BCHP_HDCP2_TX_HAE_INTR2_0_REG_START 0x006f9000
#define BCHP_HDCP2_TX_HAE_INTR2_0_REG_END 0x006f902c
#define BCHP_HDMI_TX_HAE_INTR2_0_REG_START 0x006f9080
#define BCHP_HDMI_TX_HAE_INTR2_0_REG_END 0x006f90ac
#define BCHP_HDMI_RAM_REG_START 0x006f9100
#define BCHP_HDMI_RAM_REG_END 0x006f92fc
#define BCHP_BVN_RGR_REG_START 0x006fe000
#define BCHP_BVN_RGR_REG_END 0x006fe010
#define BCHP_VICE2_CABAC_0_0_REG_START 0x00700000
#define BCHP_VICE2_CABAC_0_0_REG_END 0x007002ec
#define BCHP_VICE2_CME_0_0_REG_START 0x00700400
#define BCHP_VICE2_CME_0_0_REG_END 0x007004a0
#define BCHP_VICE2_DBLK_0_0_REG_START 0x00700800
#define BCHP_VICE2_DBLK_0_0_REG_END 0x0070088c
#define BCHP_VICE2_FME_0_0_REG_START 0x00701000
#define BCHP_VICE2_FME_0_0_REG_END 0x007010c0
#define BCHP_VICE2_HA_0_0_REG_START 0x00701400
#define BCHP_VICE2_HA_0_0_REG_END 0x0070148c
#define BCHP_VICE2_IMD_0_0_REG_START 0x00701800
#define BCHP_VICE2_IMD_0_0_REG_END 0x0070187c
#define BCHP_VICE2_MAU_0_0_REG_START 0x00701c00
#define BCHP_VICE2_MAU_0_0_REG_END 0x00701d28
#define BCHP_VICE2_MC_0_0_REG_START 0x00702000
#define BCHP_VICE2_MC_0_0_REG_END 0x0070208c
#define BCHP_VICE2_SG_0_0_REG_START 0x00702400
#define BCHP_VICE2_SG_0_0_REG_END 0x007025e4
#define BCHP_VICE2_VIP_0_0_REG_START 0x00702800
#define BCHP_VICE2_VIP_0_0_REG_END 0x00702a24
#define BCHP_VICE2_VIP1_0_0_REG_START 0x00702c00
#define BCHP_VICE2_VIP1_0_0_REG_END 0x00702e24
#define BCHP_VICE2_VIP2_0_0_REG_START 0x00703000
#define BCHP_VICE2_VIP2_0_0_REG_END 0x00703224
#define BCHP_VICE2_VIP3_0_0_REG_START 0x00703400
#define BCHP_VICE2_VIP3_0_0_REG_END 0x00703624
#define BCHP_VICE2_XQ_0_0_REG_START 0x00704000
#define BCHP_VICE2_XQ_0_0_REG_END 0x00705338
#define BCHP_VICE2_ARCSS_ESS_ADI_0_0_REG_START 0x00718000
#define BCHP_VICE2_ARCSS_ESS_ADI_0_0_REG_END 0x007182b4
#define BCHP_VICE2_ARCSS_ESS_CTRL_0_0_REG_START 0x00720000
#define BCHP_VICE2_ARCSS_ESS_CTRL_0_0_REG_END 0x007200a4
#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_0_REG_START 0x00720400
#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_0_0_REG_END 0x0072042c
#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_0_REG_START 0x00720600
#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_0_0_REG_END 0x0072062c
#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_0_REG_START 0x00722000
#define BCHP_VICE2_ARCSS_ESS_HOSTIF_0_0_REG_END 0x007233fc
#define BCHP_VICE2_ARCSS_ESS_DCCM_0_0_REG_START 0x00730000
#define BCHP_VICE2_ARCSS_ESS_DCCM_0_0_REG_END 0x0073fffc
#define BCHP_VICE2_ARCSS_ESS_ADI_1_0_REG_START 0x00758000
#define BCHP_VICE2_ARCSS_ESS_ADI_1_0_REG_END 0x007582a8
#define BCHP_VICE2_ARCSS_ESS_CTRL_1_0_REG_START 0x00760000
#define BCHP_VICE2_ARCSS_ESS_CTRL_1_0_REG_END 0x007600a4
#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_0_REG_START 0x00760400
#define BCHP_VICE2_ARCSS_ESS_FLAG_INTR2_1_0_REG_END 0x0076042c
#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_0_REG_START 0x00760600
#define BCHP_VICE2_ARCSS_ESS_P1_INTR2_1_0_REG_END 0x0076062c
#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_0_REG_START 0x00762000
#define BCHP_VICE2_ARCSS_ESS_HOSTIF_1_0_REG_END 0x007633fc
#define BCHP_VICE2_ARCSS_ESS_DCCM_1_0_REG_START 0x00770000
#define BCHP_VICE2_ARCSS_ESS_DCCM_1_0_REG_END 0x0077fffc
#define BCHP_VICE2_RGR_0_REG_START 0x00780000
#define BCHP_VICE2_RGR_0_REG_END 0x0078000c
#define BCHP_VICE2_MISC_0_REG_START 0x00781000
#define BCHP_VICE2_MISC_0_REG_END 0x00781050
#define BCHP_VICE2_L2_0_REG_START 0x00781100
#define BCHP_VICE2_L2_0_REG_END 0x0078112c
#define BCHP_VICE2_ARCSS_MISC_0_REG_START 0x00782000
#define BCHP_VICE2_ARCSS_MISC_0_REG_END 0x007820b8
#define BCHP_VICE2_SEC_CTRL_0_REG_START 0x00900000
#define BCHP_VICE2_SEC_CTRL_0_REG_END 0x00900080
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_START 0x00a00000
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_END 0x00a0002c
#define BCHP_XPT_BUS_IF_REG_START 0x00a00080
#define BCHP_XPT_BUS_IF_REG_END 0x00a000fc
#define BCHP_XPT_XMEMIF_REG_START 0x00a00100
#define BCHP_XPT_XMEMIF_REG_END 0x00a001fc
#define BCHP_XPT_PMU_REG_START 0x00a00200
#define BCHP_XPT_PMU_REG_END 0x00a00270
#define BCHP_XPT_GR_REG_START 0x00a00300
#define BCHP_XPT_GR_REG_END 0x00a0030c
#define BCHP_XPT_RMX0_IO_REG_START 0x00a00400
#define BCHP_XPT_RMX0_IO_REG_END 0x00a00420
#define BCHP_XPT_RMX1_IO_REG_START 0x00a00500
#define BCHP_XPT_RMX1_IO_REG_END 0x00a00520
#define BCHP_XPT_WAKEUP_REG_START 0x00a01000
#define BCHP_XPT_WAKEUP_REG_END 0x00a01fbc
#define BCHP_XPT_DPCR0_REG_START 0x00a02000
#define BCHP_XPT_DPCR0_REG_END 0x00a02078
#define BCHP_XPT_DPCR1_REG_START 0x00a02080
#define BCHP_XPT_DPCR1_REG_END 0x00a020f8
#define BCHP_XPT_DPCR2_REG_START 0x00a02100
#define BCHP_XPT_DPCR2_REG_END 0x00a02178
#define BCHP_XPT_DPCR3_REG_START 0x00a02180
#define BCHP_XPT_DPCR3_REG_END 0x00a021f8
#define BCHP_XPT_DPCR4_REG_START 0x00a02200
#define BCHP_XPT_DPCR4_REG_END 0x00a02278
#define BCHP_XPT_DPCR5_REG_START 0x00a02280
#define BCHP_XPT_DPCR5_REG_END 0x00a022f8
#define BCHP_XPT_DPCR6_REG_START 0x00a02300
#define BCHP_XPT_DPCR6_REG_END 0x00a02378
#define BCHP_XPT_DPCR7_REG_START 0x00a02380
#define BCHP_XPT_DPCR7_REG_END 0x00a023f8
#define BCHP_XPT_DPCR8_REG_START 0x00a02400
#define BCHP_XPT_DPCR8_REG_END 0x00a02478
#define BCHP_XPT_DPCR9_REG_START 0x00a02480
#define BCHP_XPT_DPCR9_REG_END 0x00a024f8
#define BCHP_XPT_DPCR10_REG_START 0x00a02500
#define BCHP_XPT_DPCR10_REG_END 0x00a02578
#define BCHP_XPT_DPCR11_REG_START 0x00a02580
#define BCHP_XPT_DPCR11_REG_END 0x00a025f8
#define BCHP_XPT_DPCR12_REG_START 0x00a02600
#define BCHP_XPT_DPCR12_REG_END 0x00a02678
#define BCHP_XPT_DPCR13_REG_START 0x00a02680
#define BCHP_XPT_DPCR13_REG_END 0x00a026f8
#define BCHP_XPT_DPCR_PP_REG_START 0x00a02800
#define BCHP_XPT_DPCR_PP_REG_END 0x00a02804
#define BCHP_XPT_PSUB_REG_START 0x00a02a00
#define BCHP_XPT_PSUB_REG_END 0x00a02b88
#define BCHP_XPT_MPOD_REG_START 0x00a02c00
#define BCHP_XPT_MPOD_REG_END 0x00a02c20
#define BCHP_XPT_RMX0_REG_START 0x00a02d00
#define BCHP_XPT_RMX0_REG_END 0x00a02d10
#define BCHP_XPT_RMX1_REG_START 0x00a02e00
#define BCHP_XPT_RMX1_REG_END 0x00a02e10
#define BCHP_XPT_RSBUFF_REG_START 0x00a04000
#define BCHP_XPT_RSBUFF_REG_END 0x00a054fc
#define BCHP_XPT_XCBUFF_REG_START 0x00a06000
#define BCHP_XPT_XCBUFF_REG_END 0x00a07e9c
#define BCHP_XPT_PCROFFSET_REG_START 0x00a08000
#define BCHP_XPT_PCROFFSET_REG_END 0x00a0aafc
#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_START 0x00a0c000
#define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_END 0x00a0ea04
#define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_START 0x00a0f000
#define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_END 0x00a0f9fc
#define BCHP_XPT_TSIO_INTR_L2_REG_START 0x00a0fc00
#define BCHP_XPT_TSIO_INTR_L2_REG_END 0x00a0fc2c
#define BCHP_XPT_FULL_PID_PARSER_REG_START 0x00a10000
#define BCHP_XPT_FULL_PID_PARSER_REG_END 0x00a14050
#define BCHP_XPT_FE_REG_START 0x00a20000
#define BCHP_XPT_FE_REG_END 0x00a25ffc
#define BCHP_XPT_MSG_REG_START 0x00a30000
#define BCHP_XPT_MSG_REG_END 0x00a3ca14
#define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_START 0x00a3fb00
#define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_END 0x00a3fb1c
#define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_START 0x00a3fb20
#define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_END 0x00a3fb3c
#define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_START 0x00a3fb40
#define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_END 0x00a3fb5c
#define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_START 0x00a3fb60
#define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_END 0x00a3fb7c
#define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_START 0x00a3fb80
#define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_END 0x00a3fbac
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_START 0x00a3fc00
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_END 0x00a3fc2c
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_START 0x00a3fc40
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_END 0x00a3fc6c
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_START 0x00a3fc80
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_END 0x00a3fcac
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_START 0x00a3fcc0
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_END 0x00a3fcec
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_128_159_L2_REG_START 0x00a3fd00
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_128_159_L2_REG_END 0x00a3fd2c
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_160_191_L2_REG_START 0x00a3fd40
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_160_191_L2_REG_END 0x00a3fd6c
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_192_223_L2_REG_START 0x00a3fd80
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_192_223_L2_REG_END 0x00a3fdac
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_224_255_L2_REG_START 0x00a3fdc0
#define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_224_255_L2_REG_END 0x00a3fdec
#define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_START 0x00a3fe00
#define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_END 0x00a3fe2c
#define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_START 0x00a3fe40
#define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_END 0x00a3fe6c
#define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_START 0x00a3fe80
#define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_END 0x00a3feac
#define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_START 0x00a3fec0
#define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_END 0x00a3feec
#define BCHP_XPT_MSG_BUF_OVFL_INTR_128_159_L2_REG_START 0x00a3ff00
#define BCHP_XPT_MSG_BUF_OVFL_INTR_128_159_L2_REG_END 0x00a3ff2c
#define BCHP_XPT_MSG_BUF_OVFL_INTR_160_191_L2_REG_START 0x00a3ff40
#define BCHP_XPT_MSG_BUF_OVFL_INTR_160_191_L2_REG_END 0x00a3ff6c
#define BCHP_XPT_MSG_BUF_OVFL_INTR_192_223_L2_REG_START 0x00a3ff80
#define BCHP_XPT_MSG_BUF_OVFL_INTR_192_223_L2_REG_END 0x00a3ffac
#define BCHP_XPT_MSG_BUF_OVFL_INTR_224_255_L2_REG_START 0x00a3ffc0
#define BCHP_XPT_MSG_BUF_OVFL_INTR_224_255_L2_REG_END 0x00a3ffec
#define BCHP_XPT_RAVE_REG_START 0x00a40000
#define BCHP_XPT_RAVE_REG_END 0x00a4e178
#define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_START 0x00a4f000
#define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_END 0x00a4f01c
#define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_START 0x00a4f020
#define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_END 0x00a4f03c
#define BCHP_XPT_RAVE_MISC_L2_INTR_REG_START 0x00a4f040
#define BCHP_XPT_RAVE_MISC_L2_INTR_REG_END 0x00a4f06c
#define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f080
#define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_END 0x00a4f0ac
#define BCHP_XPT_RAVE_EMU_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f0c0
#define BCHP_XPT_RAVE_EMU_ERROR_CX32_47_L2_INTR_REG_END 0x00a4f0ec
#define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f100
#define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_END 0x00a4f12c
#define BCHP_XPT_RAVE_PUSI_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f140
#define BCHP_XPT_RAVE_PUSI_ERROR_CX32_47_L2_INTR_REG_END 0x00a4f16c
#define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f180
#define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_END 0x00a4f1ac
#define BCHP_XPT_RAVE_TEI_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f1c0
#define BCHP_XPT_RAVE_TEI_ERROR_CX32_47_L2_INTR_REG_END 0x00a4f1ec
#define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_START 0x00a4f200
#define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_END 0x00a4f22c
#define BCHP_XPT_RAVE_CC_ERROR_CX32_47_L2_INTR_REG_START 0x00a4f240
#define BCHP_XPT_RAVE_CC_ERROR_CX32_47_L2_INTR_REG_END 0x00a4f26c
#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x00a4f280
#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x00a4f2ac
#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX32_47_L2_INTR_REG_START 0x00a4f2c0
#define BCHP_XPT_RAVE_CDB_OVERFLOW_CX32_47_L2_INTR_REG_END 0x00a4f2ec
#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x00a4f300
#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x00a4f32c
#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX32_47_L2_INTR_REG_START 0x00a4f340
#define BCHP_XPT_RAVE_ITB_OVERFLOW_CX32_47_L2_INTR_REG_END 0x00a4f36c
#define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_START 0x00a4f380
#define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_END 0x00a4f3ac
#define BCHP_XPT_RAVE_SPLICE_CX32_47_L2_INTR_REG_START 0x00a4f3c0
#define BCHP_XPT_RAVE_SPLICE_CX32_47_L2_INTR_REG_END 0x00a4f3ec
#define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_START 0x00a4f400
#define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_END 0x00a4f42c
#define BCHP_XPT_RAVE_LAST_CMD_CX32_47_L2_INTR_REG_START 0x00a4f440
#define BCHP_XPT_RAVE_LAST_CMD_CX32_47_L2_INTR_REG_END 0x00a4f46c
#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f480
#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f4ac
#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f4c0
#define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f4ec
#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f500
#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f52c
#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f540
#define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f56c
#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f580
#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f5ac
#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f5c0
#define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f5ec
#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f600
#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f62c
#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f640
#define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f66c
#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f680
#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f6ac
#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f6c0
#define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f6ec
#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x00a4f700
#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x00a4f72c
#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_START 0x00a4f740
#define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX32_47_L2_INTR_REG_END 0x00a4f76c
#define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_START 0x00a4f780
#define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_END 0x00a4f7ac
#define BCHP_XPT_RAVE_TSIO_DMA_END_CX32_47_L2_INTR_REG_START 0x00a4f7c0
#define BCHP_XPT_RAVE_TSIO_DMA_END_CX32_47_L2_INTR_REG_END 0x00a4f7ec
#define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_START 0x00a4f800
#define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_END 0x00a4f82c
#define BCHP_XPT_RAVE_FW_GENERIC_1_CX32_47_L2_INTR_REG_START 0x00a4f840
#define BCHP_XPT_RAVE_FW_GENERIC_1_CX32_47_L2_INTR_REG_END 0x00a4f86c
#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_START 0x00a4ff80
#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_END 0x00a4ffac
#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_START 0x00a4ffc0
#define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_32_47_REG_END 0x00a4ffec
#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x00a60000
#define BCHP_XPT_MEMDMA_MCPB_CPU_INTR_AGGREGATOR_REG_END 0x00a6001c
#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x00a60020
#define BCHP_XPT_MEMDMA_MCPB_PCI_INTR_AGGREGATOR_REG_END 0x00a6003c
#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_START 0x00a60040
#define BCHP_XPT_MEMDMA_MCPB_DESC_DONE_INTR_L2_REG_END 0x00a6006c
#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x00a60080
#define BCHP_XPT_MEMDMA_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x00a600ac
#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_START 0x00a600c0
#define BCHP_XPT_MEMDMA_MCPB_MISC_OOS_INTR_L2_REG_END 0x00a600ec
#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x00a60100
#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x00a6012c
#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_START 0x00a60140
#define BCHP_XPT_MEMDMA_MCPB_MISC_TEI_INTR_L2_REG_END 0x00a6016c
#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x00a60180
#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x00a601ac
#define BCHP_XPT_MEMDMA_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_START 0x00a601c0
#define BCHP_XPT_MEMDMA_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_END 0x00a601ec
#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x00a60200
#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x00a6022c
#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x00a60240
#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x00a6026c
#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x00a60280
#define BCHP_XPT_MEMDMA_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x00a602ac
#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x00a602c0
#define BCHP_XPT_MEMDMA_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x00a602ec
#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x00a60300
#define BCHP_XPT_MEMDMA_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x00a6032c
#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x00a60340
#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x00a6036c
#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x00a60380
#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x00a603ac
#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x00a603c0
#define BCHP_XPT_MEMDMA_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x00a603ec
#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x00a60400
#define BCHP_XPT_MEMDMA_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x00a6042c
#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x00a60440
#define BCHP_XPT_MEMDMA_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x00a6046c
#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x00a60480
#define BCHP_XPT_MEMDMA_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x00a604ac
#define BCHP_XPT_MEMDMA_MCPB_REG_START 0x00a60800
#define BCHP_XPT_MEMDMA_MCPB_REG_END 0x00a60b98
#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_START 0x00a60c00
#define BCHP_XPT_MEMDMA_MCPB_CH0_REG_END 0x00a60d5c
#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_START 0x00a60e00
#define BCHP_XPT_MEMDMA_MCPB_CH1_REG_END 0x00a60f5c
#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_START 0x00a61000
#define BCHP_XPT_MEMDMA_MCPB_CH2_REG_END 0x00a6115c
#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_START 0x00a61200
#define BCHP_XPT_MEMDMA_MCPB_CH3_REG_END 0x00a6135c
#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_START 0x00a61400
#define BCHP_XPT_MEMDMA_MCPB_CH4_REG_END 0x00a6155c
#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_START 0x00a61600
#define BCHP_XPT_MEMDMA_MCPB_CH5_REG_END 0x00a6175c
#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_START 0x00a61800
#define BCHP_XPT_MEMDMA_MCPB_CH6_REG_END 0x00a6195c
#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_START 0x00a61a00
#define BCHP_XPT_MEMDMA_MCPB_CH7_REG_END 0x00a61b5c
#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_START 0x00a61c00
#define BCHP_XPT_MEMDMA_MCPB_CH8_REG_END 0x00a61d5c
#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_START 0x00a61e00
#define BCHP_XPT_MEMDMA_MCPB_CH9_REG_END 0x00a61f5c
#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_START 0x00a62000
#define BCHP_XPT_MEMDMA_MCPB_CH10_REG_END 0x00a6215c
#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_START 0x00a62200
#define BCHP_XPT_MEMDMA_MCPB_CH11_REG_END 0x00a6235c
#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_START 0x00a62400
#define BCHP_XPT_MEMDMA_MCPB_CH12_REG_END 0x00a6255c
#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_START 0x00a62600
#define BCHP_XPT_MEMDMA_MCPB_CH13_REG_END 0x00a6275c
#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_START 0x00a62800
#define BCHP_XPT_MEMDMA_MCPB_CH14_REG_END 0x00a6295c
#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_START 0x00a62a00
#define BCHP_XPT_MEMDMA_MCPB_CH15_REG_END 0x00a62b5c
#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_START 0x00a62c00
#define BCHP_XPT_MEMDMA_MCPB_CH16_REG_END 0x00a62d5c
#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_START 0x00a62e00
#define BCHP_XPT_MEMDMA_MCPB_CH17_REG_END 0x00a62f5c
#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_START 0x00a63000
#define BCHP_XPT_MEMDMA_MCPB_CH18_REG_END 0x00a6315c
#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_START 0x00a63200
#define BCHP_XPT_MEMDMA_MCPB_CH19_REG_END 0x00a6335c
#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_START 0x00a63400
#define BCHP_XPT_MEMDMA_MCPB_CH20_REG_END 0x00a6355c
#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_START 0x00a63600
#define BCHP_XPT_MEMDMA_MCPB_CH21_REG_END 0x00a6375c
#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_START 0x00a63800
#define BCHP_XPT_MEMDMA_MCPB_CH22_REG_END 0x00a6395c
#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_START 0x00a63a00
#define BCHP_XPT_MEMDMA_MCPB_CH23_REG_END 0x00a63b5c
#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_START 0x00a63c00
#define BCHP_XPT_MEMDMA_MCPB_CH24_REG_END 0x00a63d5c
#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_START 0x00a63e00
#define BCHP_XPT_MEMDMA_MCPB_CH25_REG_END 0x00a63f5c
#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_START 0x00a64000
#define BCHP_XPT_MEMDMA_MCPB_CH26_REG_END 0x00a6415c
#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_START 0x00a64200
#define BCHP_XPT_MEMDMA_MCPB_CH27_REG_END 0x00a6435c
#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_START 0x00a64400
#define BCHP_XPT_MEMDMA_MCPB_CH28_REG_END 0x00a6455c
#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_START 0x00a64600
#define BCHP_XPT_MEMDMA_MCPB_CH29_REG_END 0x00a6475c
#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_START 0x00a64800
#define BCHP_XPT_MEMDMA_MCPB_CH30_REG_END 0x00a6495c
#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_START 0x00a64a00
#define BCHP_XPT_MEMDMA_MCPB_CH31_REG_END 0x00a64b5c
#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_START 0x00a68000
#define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_END 0x00a6801c
#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_START 0x00a68020
#define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_END 0x00a6803c
#define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_START 0x00a68040
#define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_END 0x00a6805c
#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_START 0x00a68100
#define BCHP_XPT_WDMA_BTP_INTR_L2_REG_END 0x00a68144
#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_START 0x00a68200
#define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_END 0x00a68244
#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_START 0x00a68300
#define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_END 0x00a68344
#define BCHP_XPT_WDMA_PM_INTR_L2_REG_START 0x00a68400
#define BCHP_XPT_WDMA_PM_INTR_L2_REG_END 0x00a68444
#define BCHP_XPT_WDMA_PM_CONTROL_REG_START 0x00a68500
#define BCHP_XPT_WDMA_PM_CONTROL_REG_END 0x00a68510
#define BCHP_XPT_WDMA_PM_RESULTS_REG_START 0x00a68600
#define BCHP_XPT_WDMA_PM_RESULTS_REG_END 0x00a68658
#define BCHP_XPT_WDMA_REGS_REG_START 0x00a69000
#define BCHP_XPT_WDMA_REGS_REG_END 0x00a69068
#define BCHP_XPT_WDMA_CH0_REG_START 0x00a6a000
#define BCHP_XPT_WDMA_CH0_REG_END 0x00a6a0fc
#define BCHP_XPT_WDMA_CH1_REG_START 0x00a6a100
#define BCHP_XPT_WDMA_CH1_REG_END 0x00a6a1fc
#define BCHP_XPT_WDMA_CH2_REG_START 0x00a6a200
#define BCHP_XPT_WDMA_CH2_REG_END 0x00a6a2fc
#define BCHP_XPT_WDMA_CH3_REG_START 0x00a6a300
#define BCHP_XPT_WDMA_CH3_REG_END 0x00a6a3fc
#define BCHP_XPT_WDMA_CH4_REG_START 0x00a6a400
#define BCHP_XPT_WDMA_CH4_REG_END 0x00a6a4fc
#define BCHP_XPT_WDMA_CH5_REG_START 0x00a6a500
#define BCHP_XPT_WDMA_CH5_REG_END 0x00a6a5fc
#define BCHP_XPT_WDMA_CH6_REG_START 0x00a6a600
#define BCHP_XPT_WDMA_CH6_REG_END 0x00a6a6fc
#define BCHP_XPT_WDMA_CH7_REG_START 0x00a6a700
#define BCHP_XPT_WDMA_CH7_REG_END 0x00a6a7fc
#define BCHP_XPT_WDMA_CH8_REG_START 0x00a6a800
#define BCHP_XPT_WDMA_CH8_REG_END 0x00a6a8fc
#define BCHP_XPT_WDMA_CH9_REG_START 0x00a6a900
#define BCHP_XPT_WDMA_CH9_REG_END 0x00a6a9fc
#define BCHP_XPT_WDMA_CH10_REG_START 0x00a6aa00
#define BCHP_XPT_WDMA_CH10_REG_END 0x00a6aafc
#define BCHP_XPT_WDMA_CH11_REG_START 0x00a6ab00
#define BCHP_XPT_WDMA_CH11_REG_END 0x00a6abfc
#define BCHP_XPT_WDMA_CH12_REG_START 0x00a6ac00
#define BCHP_XPT_WDMA_CH12_REG_END 0x00a6acfc
#define BCHP_XPT_WDMA_CH13_REG_START 0x00a6ad00
#define BCHP_XPT_WDMA_CH13_REG_END 0x00a6adfc
#define BCHP_XPT_WDMA_CH14_REG_START 0x00a6ae00
#define BCHP_XPT_WDMA_CH14_REG_END 0x00a6aefc
#define BCHP_XPT_WDMA_CH15_REG_START 0x00a6af00
#define BCHP_XPT_WDMA_CH15_REG_END 0x00a6affc
#define BCHP_XPT_WDMA_CH16_REG_START 0x00a6b000
#define BCHP_XPT_WDMA_CH16_REG_END 0x00a6b0fc
#define BCHP_XPT_WDMA_CH17_REG_START 0x00a6b100
#define BCHP_XPT_WDMA_CH17_REG_END 0x00a6b1fc
#define BCHP_XPT_WDMA_CH18_REG_START 0x00a6b200
#define BCHP_XPT_WDMA_CH18_REG_END 0x00a6b2fc
#define BCHP_XPT_WDMA_CH19_REG_START 0x00a6b300
#define BCHP_XPT_WDMA_CH19_REG_END 0x00a6b3fc
#define BCHP_XPT_WDMA_CH20_REG_START 0x00a6b400
#define BCHP_XPT_WDMA_CH20_REG_END 0x00a6b4fc
#define BCHP_XPT_WDMA_CH21_REG_START 0x00a6b500
#define BCHP_XPT_WDMA_CH21_REG_END 0x00a6b5fc
#define BCHP_XPT_WDMA_CH22_REG_START 0x00a6b600
#define BCHP_XPT_WDMA_CH22_REG_END 0x00a6b6fc
#define BCHP_XPT_WDMA_CH23_REG_START 0x00a6b700
#define BCHP_XPT_WDMA_CH23_REG_END 0x00a6b7fc
#define BCHP_XPT_WDMA_CH24_REG_START 0x00a6b800
#define BCHP_XPT_WDMA_CH24_REG_END 0x00a6b8fc
#define BCHP_XPT_WDMA_CH25_REG_START 0x00a6b900
#define BCHP_XPT_WDMA_CH25_REG_END 0x00a6b9fc
#define BCHP_XPT_WDMA_CH26_REG_START 0x00a6ba00
#define BCHP_XPT_WDMA_CH26_REG_END 0x00a6bafc
#define BCHP_XPT_WDMA_CH27_REG_START 0x00a6bb00
#define BCHP_XPT_WDMA_CH27_REG_END 0x00a6bbfc
#define BCHP_XPT_WDMA_CH28_REG_START 0x00a6bc00
#define BCHP_XPT_WDMA_CH28_REG_END 0x00a6bcfc
#define BCHP_XPT_WDMA_CH29_REG_START 0x00a6bd00
#define BCHP_XPT_WDMA_CH29_REG_END 0x00a6bdfc
#define BCHP_XPT_WDMA_CH30_REG_START 0x00a6be00
#define BCHP_XPT_WDMA_CH30_REG_END 0x00a6befc
#define BCHP_XPT_WDMA_CH31_REG_START 0x00a6bf00
#define BCHP_XPT_WDMA_CH31_REG_END 0x00a6bffc
#define BCHP_XPT_MEMDMA_XMEMIF_REG_START 0x00a6ff00
#define BCHP_XPT_MEMDMA_XMEMIF_REG_END 0x00a6fffc
#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x00a70000
#define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_END 0x00a7001c
#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x00a70020
#define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_END 0x00a7003c
#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_START 0x00a70040
#define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_END 0x00a7006c
#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x00a70080
#define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x00a700ac
#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_START 0x00a700c0
#define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_END 0x00a700ec
#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x00a70100
#define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x00a7012c
#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_START 0x00a70140
#define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_END 0x00a7016c
#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x00a70180
#define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x00a701ac
#define BCHP_XPT_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_START 0x00a701c0
#define BCHP_XPT_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_END 0x00a701ec
#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x00a70200
#define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x00a7022c
#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x00a70240
#define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x00a7026c
#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x00a70280
#define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x00a702ac
#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x00a702c0
#define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x00a702ec
#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x00a70300
#define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x00a7032c
#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x00a70340
#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x00a7036c
#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x00a70380
#define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x00a703ac
#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x00a703c0
#define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x00a703ec
#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x00a70400
#define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x00a7042c
#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x00a70440
#define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x00a7046c
#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x00a70480
#define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x00a704ac
#define BCHP_XPT_MCPB_REG_START 0x00a70800
#define BCHP_XPT_MCPB_REG_END 0x00a70b98
#define BCHP_XPT_MCPB_CH0_REG_START 0x00a70c00
#define BCHP_XPT_MCPB_CH0_REG_END 0x00a70d5c
#define BCHP_XPT_MCPB_CH1_REG_START 0x00a70e00
#define BCHP_XPT_MCPB_CH1_REG_END 0x00a70f5c
#define BCHP_XPT_MCPB_CH2_REG_START 0x00a71000
#define BCHP_XPT_MCPB_CH2_REG_END 0x00a7115c
#define BCHP_XPT_MCPB_CH3_REG_START 0x00a71200
#define BCHP_XPT_MCPB_CH3_REG_END 0x00a7135c
#define BCHP_XPT_MCPB_CH4_REG_START 0x00a71400
#define BCHP_XPT_MCPB_CH4_REG_END 0x00a7155c
#define BCHP_XPT_MCPB_CH5_REG_START 0x00a71600
#define BCHP_XPT_MCPB_CH5_REG_END 0x00a7175c
#define BCHP_XPT_MCPB_CH6_REG_START 0x00a71800
#define BCHP_XPT_MCPB_CH6_REG_END 0x00a7195c
#define BCHP_XPT_MCPB_CH7_REG_START 0x00a71a00
#define BCHP_XPT_MCPB_CH7_REG_END 0x00a71b5c
#define BCHP_XPT_MCPB_CH8_REG_START 0x00a71c00
#define BCHP_XPT_MCPB_CH8_REG_END 0x00a71d5c
#define BCHP_XPT_MCPB_CH9_REG_START 0x00a71e00
#define BCHP_XPT_MCPB_CH9_REG_END 0x00a71f5c
#define BCHP_XPT_MCPB_CH10_REG_START 0x00a72000
#define BCHP_XPT_MCPB_CH10_REG_END 0x00a7215c
#define BCHP_XPT_MCPB_CH11_REG_START 0x00a72200
#define BCHP_XPT_MCPB_CH11_REG_END 0x00a7235c
#define BCHP_XPT_MCPB_CH12_REG_START 0x00a72400
#define BCHP_XPT_MCPB_CH12_REG_END 0x00a7255c
#define BCHP_XPT_MCPB_CH13_REG_START 0x00a72600
#define BCHP_XPT_MCPB_CH13_REG_END 0x00a7275c
#define BCHP_XPT_MCPB_CH14_REG_START 0x00a72800
#define BCHP_XPT_MCPB_CH14_REG_END 0x00a7295c
#define BCHP_XPT_MCPB_CH15_REG_START 0x00a72a00
#define BCHP_XPT_MCPB_CH15_REG_END 0x00a72b5c
#define BCHP_XPT_MCPB_CH16_REG_START 0x00a72c00
#define BCHP_XPT_MCPB_CH16_REG_END 0x00a72d5c
#define BCHP_XPT_MCPB_CH17_REG_START 0x00a72e00
#define BCHP_XPT_MCPB_CH17_REG_END 0x00a72f5c
#define BCHP_XPT_MCPB_CH18_REG_START 0x00a73000
#define BCHP_XPT_MCPB_CH18_REG_END 0x00a7315c
#define BCHP_XPT_MCPB_CH19_REG_START 0x00a73200
#define BCHP_XPT_MCPB_CH19_REG_END 0x00a7335c
#define BCHP_XPT_MCPB_CH20_REG_START 0x00a73400
#define BCHP_XPT_MCPB_CH20_REG_END 0x00a7355c
#define BCHP_XPT_MCPB_CH21_REG_START 0x00a73600
#define BCHP_XPT_MCPB_CH21_REG_END 0x00a7375c
#define BCHP_XPT_MCPB_CH22_REG_START 0x00a73800
#define BCHP_XPT_MCPB_CH22_REG_END 0x00a7395c
#define BCHP_XPT_MCPB_CH23_REG_START 0x00a73a00
#define BCHP_XPT_MCPB_CH23_REG_END 0x00a73b5c
#define BCHP_XPT_MCPB_CH24_REG_START 0x00a73c00
#define BCHP_XPT_MCPB_CH24_REG_END 0x00a73d5c
#define BCHP_XPT_MCPB_CH25_REG_START 0x00a73e00
#define BCHP_XPT_MCPB_CH25_REG_END 0x00a73f5c
#define BCHP_XPT_MCPB_CH26_REG_START 0x00a74000
#define BCHP_XPT_MCPB_CH26_REG_END 0x00a7415c
#define BCHP_XPT_MCPB_CH27_REG_START 0x00a74200
#define BCHP_XPT_MCPB_CH27_REG_END 0x00a7435c
#define BCHP_XPT_MCPB_CH28_REG_START 0x00a74400
#define BCHP_XPT_MCPB_CH28_REG_END 0x00a7455c
#define BCHP_XPT_MCPB_CH29_REG_START 0x00a74600
#define BCHP_XPT_MCPB_CH29_REG_END 0x00a7475c
#define BCHP_XPT_MCPB_CH30_REG_START 0x00a74800
#define BCHP_XPT_MCPB_CH30_REG_END 0x00a7495c
#define BCHP_XPT_MCPB_CH31_REG_START 0x00a74a00
#define BCHP_XPT_MCPB_CH31_REG_END 0x00a74b5c
#define BCHP_XPT_XPU_REG_START 0x00a78000
#define BCHP_XPT_XPU_REG_END 0x00a7c7fc
#define BCHP_XPT_SECURE_BUS_IF_REG_START 0x00a7f000
#define BCHP_XPT_SECURE_BUS_IF_REG_END 0x00a7f000
#define BCHP_GENET_0_SYS_REG_START 0x00b00000
#define BCHP_GENET_0_SYS_REG_END 0x00b00010
#define BCHP_GENET_0_GR_BRIDGE_REG_START 0x00b00040
#define BCHP_GENET_0_GR_BRIDGE_REG_END 0x00b0004c
#define BCHP_GENET_0_EXT_REG_START 0x00b00080
#define BCHP_GENET_0_EXT_REG_END 0x00b000b4
#define BCHP_GENET_0_INTRL2_0_REG_START 0x00b00200
#define BCHP_GENET_0_INTRL2_0_REG_END 0x00b0022c
#define BCHP_GENET_0_INTRL2_1_REG_START 0x00b00240
#define BCHP_GENET_0_INTRL2_1_REG_END 0x00b0026c
#define BCHP_GENET_0_RBUF_REG_START 0x00b00300
#define BCHP_GENET_0_RBUF_REG_END 0x00b003b4
#define BCHP_GENET_0_TBUF_REG_START 0x00b00600
#define BCHP_GENET_0_TBUF_REG_END 0x00b00628
#define BCHP_GENET_0_UMAC_REG_START 0x00b00800
#define BCHP_GENET_0_UMAC_REG_END 0x00b00ed8
#define BCHP_GENET_0_RDMA_REG_START 0x00b02000
#define BCHP_GENET_0_RDMA_REG_END 0x00b030d4
#define BCHP_GENET_0_TDMA_REG_START 0x00b04000
#define BCHP_GENET_0_TDMA_REG_END 0x00b05084
#define BCHP_GENET_0_HFB_REG_START 0x00b08000
#define BCHP_GENET_0_HFB_REG_END 0x00b0fc48
#define BCHP_GENET_1_SYS_REG_START 0x00b20000
#define BCHP_GENET_1_SYS_REG_END 0x00b20010
#define BCHP_GENET_1_GR_BRIDGE_REG_START 0x00b20040
#define BCHP_GENET_1_GR_BRIDGE_REG_END 0x00b2004c
#define BCHP_GENET_1_EXT_REG_START 0x00b20080
#define BCHP_GENET_1_EXT_REG_END 0x00b200b4
#define BCHP_GENET_1_INTRL2_0_REG_START 0x00b20200
#define BCHP_GENET_1_INTRL2_0_REG_END 0x00b2022c
#define BCHP_GENET_1_INTRL2_1_REG_START 0x00b20240
#define BCHP_GENET_1_INTRL2_1_REG_END 0x00b2026c
#define BCHP_GENET_1_RBUF_REG_START 0x00b20300
#define BCHP_GENET_1_RBUF_REG_END 0x00b203b4
#define BCHP_GENET_1_TBUF_REG_START 0x00b20600
#define BCHP_GENET_1_TBUF_REG_END 0x00b20628
#define BCHP_GENET_1_UMAC_REG_START 0x00b20800
#define BCHP_GENET_1_UMAC_REG_END 0x00b20ed8
#define BCHP_GENET_1_RDMA_REG_START 0x00b22000
#define BCHP_GENET_1_RDMA_REG_END 0x00b230d4
#define BCHP_GENET_1_TDMA_REG_START 0x00b24000
#define BCHP_GENET_1_TDMA_REG_END 0x00b25084
#define BCHP_GENET_1_HFB_REG_START 0x00b28000
#define BCHP_GENET_1_HFB_REG_END 0x00b2fc48
#define BCHP_GENET_2_SYS_REG_START 0x00b40000
#define BCHP_GENET_2_SYS_REG_END 0x00b40010
#define BCHP_GENET_2_GR_BRIDGE_REG_START 0x00b40040
#define BCHP_GENET_2_GR_BRIDGE_REG_END 0x00b4004c
#define BCHP_GENET_2_EXT_REG_START 0x00b40080
#define BCHP_GENET_2_EXT_REG_END 0x00b400b4
#define BCHP_GENET_2_INTRL2_0_REG_START 0x00b40200
#define BCHP_GENET_2_INTRL2_0_REG_END 0x00b4022c
#define BCHP_GENET_2_INTRL2_1_REG_START 0x00b40240
#define BCHP_GENET_2_INTRL2_1_REG_END 0x00b4026c
#define BCHP_GENET_2_RBUF_REG_START 0x00b40300
#define BCHP_GENET_2_RBUF_REG_END 0x00b403b4
#define BCHP_GENET_2_TBUF_REG_START 0x00b40600
#define BCHP_GENET_2_TBUF_REG_END 0x00b40628
#define BCHP_GENET_2_UMAC_REG_START 0x00b40800
#define BCHP_GENET_2_UMAC_REG_END 0x00b40ed8
#define BCHP_GENET_2_RDMA_REG_START 0x00b42000
#define BCHP_GENET_2_RDMA_REG_END 0x00b430d4
#define BCHP_GENET_2_TDMA_REG_START 0x00b44000
#define BCHP_GENET_2_TDMA_REG_END 0x00b45084
#define BCHP_GENET_2_HFB_REG_START 0x00b48000
#define BCHP_GENET_2_HFB_REG_END 0x00b4fc48
#define BCHP_SID_REG_START 0x00bc0100
#define BCHP_SID_REG_END 0x00bc019c
#define BCHP_SID_RLE_REG_START 0x00bc0300
#define BCHP_SID_RLE_REG_END 0x00bc039c
#define BCHP_SID_DQ_REG_START 0x00bc0400
#define BCHP_SID_DQ_REG_END 0x00bc04bc
#define BCHP_SID_STRM_REG_START 0x00bc0800
#define BCHP_SID_STRM_REG_END 0x00bc087c
#define BCHP_SID_OUTPUT_REG_START 0x00bc0c00
#define BCHP_SID_OUTPUT_REG_END 0x00bc0c40
#define BCHP_SID_ARC_REG_START 0x00bc0f00
#define BCHP_SID_ARC_REG_END 0x00bc0f3c
#define BCHP_SID_ARCDMA_REG_START 0x00bc1800
#define BCHP_SID_ARCDMA_REG_END 0x00bc1840
#define BCHP_SID_DMARAM_REG_START 0x00bc1a00
#define BCHP_SID_DMARAM_REG_END 0x00bc1bfc
#define BCHP_SID_PEEK_BITS_REG_START 0x00bc2b00
#define BCHP_SID_PEEK_BITS_REG_END 0x00bc2b3c
#define BCHP_SID_EXTRACT_BITS_REG_START 0x00bc2b40
#define BCHP_SID_EXTRACT_BITS_REG_END 0x00bc2b7c
#define BCHP_SID_HUFF_SYMB_REG_START 0x00bc3000
#define BCHP_SID_HUFF_SYMB_REG_END 0x00bc37fc
#define BCHP_SID_HUFF_CODE_REG_START 0x00bc3900
#define BCHP_SID_HUFF_CODE_REG_END 0x00bc39fc
#define BCHP_SID_SYMB_REG_START 0x00bc3a00
#define BCHP_SID_SYMB_REG_END 0x00bc3a10
#define BCHP_SID_SYMB_JPEG_REG_START 0x00bc3a80
#define BCHP_SID_SYMB_JPEG_REG_END 0x00bc3a8c
#define BCHP_SID_BIGRAM_REG_START 0x00bc8000
#define BCHP_SID_BIGRAM_REG_END 0x00bcfffc
#define BCHP_SID_ARC_DBG_REG_START 0x00bd1000
#define BCHP_SID_ARC_DBG_REG_END 0x00bd1010
#define BCHP_SID_ARC_CORE_REG_START 0x00bd5000
#define BCHP_SID_ARC_CORE_REG_END 0x00bd5014
#define BCHP_SID_GR_REG_START 0x00be0000
#define BCHP_SID_GR_REG_END 0x00be000c
#define BCHP_SID_L2_REG_START 0x00be0100
#define BCHP_SID_L2_REG_END 0x00be012c
#define BCHP_SICH_REG_START 0x00be2000
#define BCHP_SICH_REG_END 0x00be203c
#define BCHP_M2MC_REG_START 0x00be4000
#define BCHP_M2MC_REG_END 0x00be47fc
#define BCHP_M2MC_L2_REG_START 0x00be5000
#define BCHP_M2MC_L2_REG_END 0x00be502c
#define BCHP_M2MC_GR_REG_START 0x00be5800
#define BCHP_M2MC_GR_REG_END 0x00be580c
#define BCHP_M2MC1_REG_START 0x00be6000
#define BCHP_M2MC1_REG_END 0x00be67fc
#define BCHP_M2MC1_L2_REG_START 0x00be7000
#define BCHP_M2MC1_L2_REG_END 0x00be702c
#define BCHP_M2MC1_GR_REG_START 0x00be7800
#define BCHP_M2MC1_GR_REG_END 0x00be780c
#define BCHP_V3D_CTL_REG_START 0x00bea000
#define BCHP_V3D_CTL_REG_END 0x00bea07c
#define BCHP_V3D_CLE_REG_START 0x00bea100
#define BCHP_V3D_CLE_REG_END 0x00bea1a4
#define BCHP_V3D_PTB_REG_START 0x00bea300
#define BCHP_V3D_PTB_REG_END 0x00bea310
#define BCHP_V3D_QPS_REG_START 0x00bea400
#define BCHP_V3D_QPS_REG_END 0x00bea43c
#define BCHP_V3D_VPM_REG_START 0x00bea500
#define BCHP_V3D_VPM_REG_END 0x00bea504
#define BCHP_V3D_PCTR_REG_START 0x00bea600
#define BCHP_V3D_PCTR_REG_END 0x00bea6fc
#define BCHP_V3D_AXM_REG_START 0x00bea700
#define BCHP_V3D_AXM_REG_END 0x00bea714
#define BCHP_V3D_GMP_REG_START 0x00bea800
#define BCHP_V3D_GMP_REG_END 0x00bea820
#define BCHP_V3D_TOP_GR_BRIDGE_REG_START 0x00bea900
#define BCHP_V3D_TOP_GR_BRIDGE_REG_END 0x00bea90c
#define BCHP_V3D_GCA_REG_START 0x00beaa00
#define BCHP_V3D_GCA_REG_END 0x00beaacc
#define BCHP_V3D_ERROR_REG_START 0x00beaf00
#define BCHP_V3D_ERROR_REG_END 0x00beaf20
#define BCHP_V3D_QPUDBG_REG_START 0x00bec000
#define BCHP_V3D_QPUDBG_REG_END 0x00bedffc
#define BCHP_V3D_HUB_CTL_REG_START 0x00bee000
#define BCHP_V3D_HUB_CTL_REG_END 0x00bee07c
#define BCHP_V3D_MSO_REG_START 0x00bee100
#define BCHP_V3D_MSO_REG_END 0x00bee27c
#define BCHP_V3D_TSY_REG_START 0x00bee300
#define BCHP_V3D_TSY_REG_END 0x00bee368
#define BCHP_V3D_TFU_REG_START 0x00bee400
#define BCHP_V3D_TFU_REG_END 0x00bee464
#define BCHP_V3D_MCS_REG_START 0x00bee500
#define BCHP_V3D_MCS_REG_END 0x00bee55c
#define BCHP_RAAGA_DSP_SEC0_REG_START 0x00bf0000
#define BCHP_RAAGA_DSP_SEC0_REG_END 0x00bf0000
#define BCHP_RAAGA_DSP_RGR_REG_START 0x00c00000
#define BCHP_RAAGA_DSP_RGR_REG_END 0x00c00008
#define BCHP_RAAGA_DSP_MISC_REG_START 0x00c20000
#define BCHP_RAAGA_DSP_MISC_REG_END 0x00c2044c
#define BCHP_RAAGA_DSP_TIMERS_REG_START 0x00c21000
#define BCHP_RAAGA_DSP_TIMERS_REG_END 0x00c21058
#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START 0x00c21080
#define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END 0x00c2109c
#define BCHP_RAAGA_DSP_PERI_SW_REG_START 0x00c21100
#define BCHP_RAAGA_DSP_PERI_SW_REG_END 0x00c21154
#define BCHP_RAAGA_DSP_DMA_REG_START 0x00c21400
#define BCHP_RAAGA_DSP_DMA_REG_END 0x00c21664
#define BCHP_RAAGA_DSP_ESR_SI_REG_START 0x00c22000
#define BCHP_RAAGA_DSP_ESR_SI_REG_END 0x00c22014
#define BCHP_RAAGA_DSP_INTH_REG_START 0x00c22200
#define BCHP_RAAGA_DSP_INTH_REG_END 0x00c2222c
#define BCHP_RAAGA_DSP_FW_INTH_REG_START 0x00c22400
#define BCHP_RAAGA_DSP_FW_INTH_REG_END 0x00c2242c
#define BCHP_RAAGA_DSP_FW_CFG_REG_START 0x00c23000
#define BCHP_RAAGA_DSP_FW_CFG_REG_END 0x00c2357c
#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START 0x00c30000
#define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END 0x00c3bffc
#define BCHP_AUD_MISC_REG_START 0x00c80000
#define BCHP_AUD_MISC_REG_END 0x00c80120
#define BCHP_AUD_INTH_REG_START 0x00c80800
#define BCHP_AUD_INTH_REG_END 0x00c8082c
#define BCHP_AUD_FMM_BF_CTRL_REG_START 0x00ca0000
#define BCHP_AUD_FMM_BF_CTRL_REG_END 0x00ca0d3c
#define BCHP_AUD_FMM_BF_ESR_REG_START 0x00ca1000
#define BCHP_AUD_FMM_BF_ESR_REG_END 0x00ca1074
#define BCHP_AUD_FMM_SRC_CTRL0_REG_START 0x00ca2000
#define BCHP_AUD_FMM_SRC_CTRL0_REG_END 0x00ca2bfc
#define BCHP_AUD_FMM_SRC_ESR0_REG_START 0x00ca3000
#define BCHP_AUD_FMM_SRC_ESR0_REG_END 0x00ca3014
#define BCHP_AUD_FMM_DP_CTRL0_REG_START 0x00ca4000
#define BCHP_AUD_FMM_DP_CTRL0_REG_END 0x00ca612c
#define BCHP_AUD_FMM_DP_ESR0_REG_START 0x00ca7c00
#define BCHP_AUD_FMM_DP_ESR0_REG_END 0x00ca7c2c
#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_START 0x00cb0000
#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_0_REG_END 0x00cb0084
#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_1_REG_START 0x00cb0100
#define BCHP_AUD_FMM_IOP_OUT_I2S_STEREO_1_REG_END 0x00cb0184
#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_START 0x00cb0200
#define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_END 0x00cb0284
#define BCHP_AUD_FMM_IOP_OUT_SPDIF_1_REG_START 0x00cb0300
#define BCHP_AUD_FMM_IOP_OUT_SPDIF_1_REG_END 0x00cb0384
#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_START 0x00cb0400
#define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_END 0x00cb04b4
#define BCHP_HIFIDAC_CTRL_0_REG_START 0x00cb0800
#define BCHP_HIFIDAC_CTRL_0_REG_END 0x00cb09fc
#define BCHP_HIFIDAC_RM_0_REG_START 0x00cb0a00
#define BCHP_HIFIDAC_RM_0_REG_END 0x00cb0a30
#define BCHP_HIFIDAC_ESR_0_REG_START 0x00cb0b00
#define BCHP_HIFIDAC_ESR_0_REG_END 0x00cb0b14
#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_START 0x00cb0c00
#define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_END 0x00cb0c98
#define BCHP_AUD_FMM_IOP_PLL_0_REG_START 0x00cb0d00
#define BCHP_AUD_FMM_IOP_PLL_0_REG_END 0x00cb0d88
#define BCHP_AUD_FMM_IOP_PLL_1_REG_START 0x00cb0e00
#define BCHP_AUD_FMM_IOP_PLL_1_REG_END 0x00cb0e88
#define BCHP_AUD_FMM_IOP_PLL_2_REG_START 0x00cb0f00
#define BCHP_AUD_FMM_IOP_PLL_2_REG_END 0x00cb0f88
#define BCHP_AUD_FMM_IOP_NCO_0_REG_START 0x00cb1000
#define BCHP_AUD_FMM_IOP_NCO_0_REG_END 0x00cb1030
#define BCHP_AUD_FMM_IOP_NCO_1_REG_START 0x00cb1100
#define BCHP_AUD_FMM_IOP_NCO_1_REG_END 0x00cb1130
#define BCHP_AUD_FMM_IOP_NCO_2_REG_START 0x00cb1200
#define BCHP_AUD_FMM_IOP_NCO_2_REG_END 0x00cb1230
#define BCHP_AUD_FMM_IOP_NCO_3_REG_START 0x00cb1300
#define BCHP_AUD_FMM_IOP_NCO_3_REG_END 0x00cb1330
#define BCHP_AUD_FMM_IOP_NCO_4_REG_START 0x00cb1400
#define BCHP_AUD_FMM_IOP_NCO_4_REG_END 0x00cb1430
#define BCHP_AUD_FMM_IOP_NCO_5_REG_START 0x00cb1500
#define BCHP_AUD_FMM_IOP_NCO_5_REG_END 0x00cb1530
#define BCHP_AUD_FMM_IOP_NCO_6_REG_START 0x00cb1600
#define BCHP_AUD_FMM_IOP_NCO_6_REG_END 0x00cb1630
#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_START 0x00cb1800
#define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_END 0x00cb1924
#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_START 0x00cb1a00
#define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_END 0x00cb1a5c
#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_START 0x00cb2000
#define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_END 0x00cb20fc
#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_START 0x00cb2800
#define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_END 0x00cb28ac
#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_START 0x00cb3000
#define BCHP_AUD_FMM_IOP_IN_I2S_STEREO_0_REG_END 0x00cb3064
#define BCHP_AUD_FMM_IOP_ATTG_0_REG_START 0x00cb3100
#define BCHP_AUD_FMM_IOP_ATTG_0_REG_END 0x00cb3164
#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_START 0x00cb4000
#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_END 0x00cb41fc
#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_START 0x00cb4400
#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_END 0x00cb4414
#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_START 0x00cb6000
#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_END 0x00cb7bfc
#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_START 0x00cb7d00
#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_END 0x00cb7d14
#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_1_REG_START 0x00cb8000
#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_1_REG_END 0x00cb81fc
#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_1_REG_START 0x00cb8400
#define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_1_REG_END 0x00cb8414
#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_1_REG_START 0x00cba000
#define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_1_REG_END 0x00cbbbfc
#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_1_REG_START 0x00cbbd00
#define BCHP_AUD_FMM_IOP_OUT_MS_ESR_1_REG_END 0x00cbbd14
#define BCHP_AUD_FMM_IOP_MISC_REG_START 0x00cbc100
#define BCHP_AUD_FMM_IOP_MISC_REG_END 0x00cbc154
#define BCHP_DATA_MEM_REG_START 0x00e00000
#define BCHP_DATA_MEM_REG_END 0x00e47ffc
#define BCHP_CNTL_MEM_REG_START 0x00f20000
#define BCHP_CNTL_MEM_REG_END 0x00f67ffc
#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_START 0x00fc0000
#define BCHP_DMA_AHB_ECL_CMD_SCH0_REG_END 0x00fc0000
#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_START 0x00fc0010
#define BCHP_DMA_AHB_ECL_CMD_SCH1_REG_END 0x00fc0010
#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_START 0x00fc0020
#define BCHP_DMA_AHB_ECL_CMD_SCH2_REG_END 0x00fc0020
#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_START 0x00fc0030
#define BCHP_DMA_AHB_ECL_CMD_SCH3_REG_END 0x00fc0030
#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_START 0x00fc0040
#define BCHP_DMA_AHB_ECL_CMD_SCH4_REG_END 0x00fc0040
#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_START 0x00fc0050
#define BCHP_DMA_AHB_ECL_CMD_SCH5_REG_END 0x00fc0050
#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_START 0x00fc0060
#define BCHP_DMA_AHB_ECL_CMD_SCH6_REG_END 0x00fc0060
#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_START 0x00fc0070
#define BCHP_DMA_AHB_ECL_CMD_SCH7_REG_END 0x00fc0070
#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_START 0x00fc0080
#define BCHP_DMA_AHB_ECL_CMD_SCH8_REG_END 0x00fc0080
#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_START 0x00fc0090
#define BCHP_DMA_AHB_ECL_CMD_SCH9_REG_END 0x00fc0090
#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_START 0x00fc00a0
#define BCHP_DMA_AHB_ECL_CMD_SCH10_REG_END 0x00fc00a0
#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_START 0x00fc00b0
#define BCHP_DMA_AHB_ECL_CMD_SCH11_REG_END 0x00fc00b0
#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_START 0x00fc00c0
#define BCHP_DMA_AHB_ECL_CMD_SCH12_REG_END 0x00fc00c0
#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_START 0x00fc00d0
#define BCHP_DMA_AHB_ECL_CMD_SCH13_REG_END 0x00fc00d0
#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_START 0x00fc00e0
#define BCHP_DMA_AHB_ECL_CMD_SCH14_REG_END 0x00fc00e0
#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_START 0x00fc00f0
#define BCHP_DMA_AHB_ECL_CMD_SCH15_REG_END 0x00fc00f0
#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_START 0x00fc0100
#define BCHP_DMA_AHB_ECL_CMD_SCH16_REG_END 0x00fc0100
#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_START 0x00fc0110
#define BCHP_DMA_AHB_ECL_CMD_SCH17_REG_END 0x00fc0110
#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_START 0x00fc0120
#define BCHP_DMA_AHB_ECL_CMD_SCH18_REG_END 0x00fc0120
#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_START 0x00fc0130
#define BCHP_DMA_AHB_ECL_CMD_SCH19_REG_END 0x00fc0130
#define BCHP_DMA_AHB_ECL_CMD_RX_REG_START 0x00fc0800
#define BCHP_DMA_AHB_ECL_CMD_RX_REG_END 0x00fc0800
#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_START 0x00fc4000
#define BCHP_DMA_AHB_CMD_RX_SCH0_REG_END 0x00fc4000
#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_START 0x00fc4010
#define BCHP_DMA_AHB_CMD_RX_SCH1_REG_END 0x00fc4010
#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_START 0x00fc4020
#define BCHP_DMA_AHB_CMD_RX_SCH2_REG_END 0x00fc4020
#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_START 0x00fc4030
#define BCHP_DMA_AHB_CMD_RX_SCH3_REG_END 0x00fc4030
#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_START 0x00fc4040
#define BCHP_DMA_AHB_CMD_RX_SCH4_REG_END 0x00fc4040
#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_START 0x00fc4050
#define BCHP_DMA_AHB_CMD_RX_SCH5_REG_END 0x00fc4050
#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_START 0x00fc4060
#define BCHP_DMA_AHB_CMD_RX_SCH6_REG_END 0x00fc4060
#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_START 0x00fc4070
#define BCHP_DMA_AHB_CMD_RX_SCH7_REG_END 0x00fc4070
#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_START 0x00fc4080
#define BCHP_DMA_AHB_CMD_RX_SCH8_REG_END 0x00fc4080
#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_START 0x00fc4090
#define BCHP_DMA_AHB_CMD_RX_SCH9_REG_END 0x00fc4090
#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_START 0x00fc40a0
#define BCHP_DMA_AHB_CMD_RX_SCH10_REG_END 0x00fc40a0
#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_START 0x00fc40b0
#define BCHP_DMA_AHB_CMD_RX_SCH11_REG_END 0x00fc40b0
#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_START 0x00fc40c0
#define BCHP_DMA_AHB_CMD_RX_SCH12_REG_END 0x00fc40c0
#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_START 0x00fc40d0
#define BCHP_DMA_AHB_CMD_RX_SCH13_REG_END 0x00fc40d0
#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_START 0x00fc40e0
#define BCHP_DMA_AHB_CMD_RX_SCH14_REG_END 0x00fc40e0
#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_START 0x00fc40f0
#define BCHP_DMA_AHB_CMD_RX_SCH15_REG_END 0x00fc40f0
#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_START 0x00fc4100
#define BCHP_DMA_AHB_CMD_RX_SCH16_REG_END 0x00fc4100
#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_START 0x00fc4110
#define BCHP_DMA_AHB_CMD_RX_SCH17_REG_END 0x00fc4110
#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_START 0x00fc4120
#define BCHP_DMA_AHB_CMD_RX_SCH18_REG_END 0x00fc4120
#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_START 0x00fc4130
#define BCHP_DMA_AHB_CMD_RX_SCH19_REG_END 0x00fc4130
#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_START 0x00fc4200
#define BCHP_DMA_AHB_CMD_RES0_SCH0_REG_END 0x00fc4200
#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_START 0x00fc4210
#define BCHP_DMA_AHB_CMD_RES0_SCH1_REG_END 0x00fc4210
#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_START 0x00fc4220
#define BCHP_DMA_AHB_CMD_RES0_SCH2_REG_END 0x00fc4220
#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_START 0x00fc4230
#define BCHP_DMA_AHB_CMD_RES0_SCH3_REG_END 0x00fc4230
#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_START 0x00fc4240
#define BCHP_DMA_AHB_CMD_RES0_SCH4_REG_END 0x00fc4240
#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_START 0x00fc4250
#define BCHP_DMA_AHB_CMD_RES0_SCH5_REG_END 0x00fc4250
#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_START 0x00fc4260
#define BCHP_DMA_AHB_CMD_RES0_SCH6_REG_END 0x00fc4260
#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_START 0x00fc4270
#define BCHP_DMA_AHB_CMD_RES0_SCH7_REG_END 0x00fc4270
#define BCHP_DMA_AHB_CMD_TX0_REG_START 0x00fc4800
#define BCHP_DMA_AHB_CMD_TX0_REG_END 0x00fc4800
#define BCHP_DMA_AHB_CMD_TX1_REG_START 0x00fc4a00
#define BCHP_DMA_AHB_CMD_TX1_REG_END 0x00fc4a00
#define BCHP_DMA_AHB_CMD_CONF0_REG_START 0x00fc4c00
#define BCHP_DMA_AHB_CMD_CONF0_REG_END 0x00fc4c00
#define BCHP_MAC_AHB_REG_START 0x00fc5000
#define BCHP_MAC_AHB_REG_END 0x00fc500c
#define BCHP_LLM_AHB_REG_START 0x00fc8000
#define BCHP_LLM_AHB_REG_END 0x00fc805c
#define BCHP_PHY_REG_START 0x00fe0000
#define BCHP_PHY_REG_END 0x00fe47fc
#define BCHP_ECL_REG_START 0x00fe8000
#define BCHP_ECL_REG_END 0x00fecb20
#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_START 0x00fed000
#define BCHP_DMA_IO2MEM_CH_ECL_TX_Global_REG_END 0x00fed014
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_START 0x00fed040
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH0_REG_END 0x00fed06c
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_START 0x00fed080
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH1_REG_END 0x00fed0ac
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_START 0x00fed0c0
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH2_REG_END 0x00fed0ec
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_START 0x00fed100
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH3_REG_END 0x00fed12c
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_START 0x00fed140
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH4_REG_END 0x00fed16c
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_START 0x00fed180
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH5_REG_END 0x00fed1ac
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_START 0x00fed1c0
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH6_REG_END 0x00fed1ec
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_START 0x00fed200
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH7_REG_END 0x00fed22c
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_START 0x00fed240
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH8_REG_END 0x00fed26c
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_START 0x00fed280
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH9_REG_END 0x00fed2ac
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_START 0x00fed2c0
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH10_REG_END 0x00fed2ec
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_START 0x00fed300
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH11_REG_END 0x00fed32c
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_START 0x00fed340
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH12_REG_END 0x00fed36c
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_START 0x00fed380
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH13_REG_END 0x00fed3ac
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_START 0x00fed3c0
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH14_REG_END 0x00fed3ec
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_START 0x00fed400
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH15_REG_END 0x00fed42c
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_START 0x00fed440
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH16_REG_END 0x00fed46c
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_START 0x00fed480
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH17_REG_END 0x00fed4ac
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_START 0x00fed4c0
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH18_REG_END 0x00fed4ec
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_START 0x00fed500
#define BCHP_DMA_IO2MEM_SUBCH_ECL_TX_SUBCH19_REG_END 0x00fed52c
#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_START 0x00fed800
#define BCHP_DMA_MEM2IO_CH_ECL_RX_REG_END 0x00fed828
#define BCHP_GMII_REG_START 0x00fedc00
#define BCHP_GMII_REG_END 0x00fedc58
#define BCHP_MAC_APB_REG_START 0x00ff0000
#define BCHP_MAC_APB_REG_END 0x00ff14fc
#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_START 0x00ff4000
#define BCHP_DMA_IO2MEM_CH_MAC_RX_Global_REG_END 0x00ff4014
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_START 0x00ff4040
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH0_REG_END 0x00ff406c
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_START 0x00ff4080
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH1_REG_END 0x00ff40ac
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_START 0x00ff40c0
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH2_REG_END 0x00ff40ec
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_START 0x00ff4100
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH3_REG_END 0x00ff412c
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_START 0x00ff4140
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH4_REG_END 0x00ff416c
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_START 0x00ff4180
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH5_REG_END 0x00ff41ac
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_START 0x00ff41c0
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH6_REG_END 0x00ff41ec
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_START 0x00ff4200
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH7_REG_END 0x00ff422c
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_START 0x00ff4240
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH8_REG_END 0x00ff426c
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_START 0x00ff4280
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH9_REG_END 0x00ff42ac
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_START 0x00ff42c0
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH10_REG_END 0x00ff42ec
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_START 0x00ff4300
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH11_REG_END 0x00ff432c
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_START 0x00ff4340
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH12_REG_END 0x00ff436c
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_START 0x00ff4380
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH13_REG_END 0x00ff43ac
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_START 0x00ff43c0
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH14_REG_END 0x00ff43ec
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_START 0x00ff4400
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH15_REG_END 0x00ff442c
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_START 0x00ff4440
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH16_REG_END 0x00ff446c
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_START 0x00ff4480
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH17_REG_END 0x00ff44ac
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_START 0x00ff44c0
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH18_REG_END 0x00ff44ec
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_START 0x00ff4500
#define BCHP_DMA_IO2MEM_SUBCH_MAC_RX_SUBCH19_REG_END 0x00ff452c
#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_START 0x00ff4800
#define BCHP_DMA_IO2MEM_CH_PHY0_Global_REG_END 0x00ff4814
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_START 0x00ff4840
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH0_REG_END 0x00ff486c
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_START 0x00ff4880
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH1_REG_END 0x00ff48ac
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_START 0x00ff48c0
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH2_REG_END 0x00ff48ec
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_START 0x00ff4900
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH3_REG_END 0x00ff492c
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_START 0x00ff4940
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH4_REG_END 0x00ff496c
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_START 0x00ff4980
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH5_REG_END 0x00ff49ac
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_START 0x00ff49c0
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH6_REG_END 0x00ff49ec
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_START 0x00ff4a00
#define BCHP_DMA_IO2MEM_SUBCH_PHY0_SUBCH7_REG_END 0x00ff4a2c
#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_START 0x00ff6000
#define BCHP_DMA_MEM2IO_CH_MAC_TX0_REG_END 0x00ff6028
#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_START 0x00ff6400
#define BCHP_DMA_MEM2IO_CH_MAC_TX1_REG_END 0x00ff6428
#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_START 0x00ff6800
#define BCHP_DMA_MEM2IO_CH_PHY0_CONFIG_REG_END 0x00ff6828
#define BCHP_MOCA_INTC_L2_HI_REG_START 0x00ff8000
#define BCHP_MOCA_INTC_L2_HI_REG_END 0x00ff8584
#define BCHP_MOCA_INTC_L2_LO_REG_START 0x00ff8800
#define BCHP_MOCA_INTC_L2_LO_REG_END 0x00ff8d84
#define BCHP_LLM_APB_REG_START 0x00ffc000
#define BCHP_LLM_APB_REG_END 0x00ffd00c
#define BCHP_TRX_REG_START 0x00ffe000
#define BCHP_TRX_REG_END 0x00ffe1fc
#define BCHP_MOCA_TIMER_REG_START 0x00ffe400
#define BCHP_MOCA_TIMER_REG_END 0x00ffe4ec
#define BCHP_MOCA_GPIO_REG_START 0x00ffe800
#define BCHP_MOCA_GPIO_REG_END 0x00ffe818
#define BCHP_EXTRAS_REG_START 0x00ffec00
#define BCHP_EXTRAS_REG_END 0x00ffed18
#define BCHP_MOCA_BSC_REG_START 0x00fff000
#define BCHP_MOCA_BSC_REG_END 0x00fff058
#define BCHP_MOCA_HOSTM2M_REG_START 0x00fffc00
#define BCHP_MOCA_HOSTM2M_REG_END 0x00fffc14
#define BCHP_AHB_M2M_DMA_REG_START 0x00fffc20
#define BCHP_AHB_M2M_DMA_REG_END 0x00fffc2c
#define BCHP_MOCA_L2_REG_START 0x00fffc40
#define BCHP_MOCA_L2_REG_END 0x00fffc6c
#define BCHP_MOCA_GR_BRIDGE_REG_START 0x00fffc80
#define BCHP_MOCA_GR_BRIDGE_REG_END 0x00fffc8c
#define BCHP_MOCA_HOSTMISC_REG_START 0x00fffd00
#define BCHP_MOCA_HOSTMISC_REG_END 0x00fffd9c
#define BCHP_MEMC_GEN_0_REG_START 0x01100000
#define BCHP_MEMC_GEN_0_REG_END 0x011007fc
#define BCHP_MEMC_EDIS_0_0_REG_START 0x01100800
#define BCHP_MEMC_EDIS_0_0_REG_END 0x011008fc
#define BCHP_MEMC_EDIS_0_1_REG_START 0x01100a00
#define BCHP_MEMC_EDIS_0_1_REG_END 0x01100afc
#define BCHP_MEMC_ARC_0_REG_START 0x01100c00
#define BCHP_MEMC_ARC_0_REG_END 0x01100f74
#define BCHP_MEMC_ARB_0_REG_START 0x01101000
#define BCHP_MEMC_ARB_0_REG_END 0x011014d0
#define BCHP_MEMC_DDR_0_REG_START 0x01102000
#define BCHP_MEMC_DDR_0_REG_END 0x011027fc
#define BCHP_MEMC_L2_0_0_REG_START 0x01103000
#define BCHP_MEMC_L2_0_0_REG_END 0x01103044
#define BCHP_MEMC_L2_0_1_REG_START 0x01103200
#define BCHP_MEMC_L2_0_1_REG_END 0x01103244
#define BCHP_MEMC_L2_0_2_REG_START 0x01103400
#define BCHP_MEMC_L2_0_2_REG_END 0x01103444
#define BCHP_MEMC_TRACELOG_0_0_REG_START 0x01103800
#define BCHP_MEMC_TRACELOG_0_0_REG_END 0x011039fc
#define BCHP_MEMC_RGRB_0_REG_START 0x01104000
#define BCHP_MEMC_RGRB_0_REG_END 0x01104010
#define BCHP_MEMC_MISC_0_REG_START 0x01105000
#define BCHP_MEMC_MISC_0_REG_END 0x01105010
#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_START 0x01108000
#define BCHP_SHIMPHY_ADDR_CNTL_0_REG_END 0x011080e4
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_START 0x01120000
#define BCHP_DDR34_PHY_CONTROL_REGS_0_REG_END 0x01120218
#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_START 0x01120400
#define BCHP_DDR34_PHY_BYTE_LANE_0_0_REG_END 0x01120518
#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_START 0x01120600
#define BCHP_DDR34_PHY_BYTE_LANE_1_0_REG_END 0x01120718
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_REG_START 0x01120800
#define BCHP_DDR34_PHY_BYTE_LANE_2_0_REG_END 0x01120918
#define BCHP_DDR34_PHY_BYTE_LANE_3_0_REG_START 0x01120a00
#define BCHP_DDR34_PHY_BYTE_LANE_3_0_REG_END 0x01120b18
#define BCHP_DDR34_PHY_ECC_LANE_0_REG_START 0x01120c00
#define BCHP_DDR34_PHY_ECC_LANE_0_REG_END 0x01120d18
#define BCHP_DPFE_CONTROLLER_0_REG_START 0x01122000
#define BCHP_DPFE_CONTROLLER_0_REG_END 0x01122050
#define BCHP_DPFE_EDIS_0_0_REG_START 0x01122400
#define BCHP_DPFE_EDIS_0_0_REG_END 0x01122560
#define BCHP_DPFE_EDIS_0_1_REG_START 0x01122800
#define BCHP_DPFE_EDIS_0_1_REG_END 0x01122960
#define BCHP_MEMC_SENTINEL_0_0_REG_START 0x01140000
#define BCHP_MEMC_SENTINEL_0_0_REG_END 0x0117fffc
#define BCHP_MEMC_GEN_1_REG_START 0x01180000
#define BCHP_MEMC_GEN_1_REG_END 0x011807fc
#define BCHP_MEMC_EDIS_1_0_REG_START 0x01180800
#define BCHP_MEMC_EDIS_1_0_REG_END 0x011808fc
#define BCHP_MEMC_EDIS_1_1_REG_START 0x01180a00
#define BCHP_MEMC_EDIS_1_1_REG_END 0x01180afc
#define BCHP_MEMC_ARC_1_REG_START 0x01180c00
#define BCHP_MEMC_ARC_1_REG_END 0x01180f74
#define BCHP_MEMC_ARB_1_REG_START 0x01181000
#define BCHP_MEMC_ARB_1_REG_END 0x011814d0
#define BCHP_MEMC_DDR_1_REG_START 0x01182000
#define BCHP_MEMC_DDR_1_REG_END 0x011827fc
#define BCHP_MEMC_L2_1_0_REG_START 0x01183000
#define BCHP_MEMC_L2_1_0_REG_END 0x01183044
#define BCHP_MEMC_L2_1_1_REG_START 0x01183200
#define BCHP_MEMC_L2_1_1_REG_END 0x01183244
#define BCHP_MEMC_L2_1_2_REG_START 0x01183400
#define BCHP_MEMC_L2_1_2_REG_END 0x01183444
#define BCHP_MEMC_TRACELOG_0_1_REG_START 0x01183800
#define BCHP_MEMC_TRACELOG_0_1_REG_END 0x011839fc
#define BCHP_MEMC_RGRB_1_REG_START 0x01184000
#define BCHP_MEMC_RGRB_1_REG_END 0x01184010
#define BCHP_MEMC_MISC_1_REG_START 0x01185000
#define BCHP_MEMC_MISC_1_REG_END 0x01185010
#define BCHP_SHIMPHY_ADDR_CNTL_1_REG_START 0x01188000
#define BCHP_SHIMPHY_ADDR_CNTL_1_REG_END 0x011880e4
#define BCHP_DDR34_PHY_CONTROL_REGS_1_REG_START 0x011a0000
#define BCHP_DDR34_PHY_CONTROL_REGS_1_REG_END 0x011a0218
#define BCHP_DDR34_PHY_BYTE_LANE_0_1_REG_START 0x011a0400
#define BCHP_DDR34_PHY_BYTE_LANE_0_1_REG_END 0x011a0518
#define BCHP_DDR34_PHY_BYTE_LANE_1_1_REG_START 0x011a0600
#define BCHP_DDR34_PHY_BYTE_LANE_1_1_REG_END 0x011a0718
#define BCHP_DDR34_PHY_BYTE_LANE_2_1_REG_START 0x011a0800
#define BCHP_DDR34_PHY_BYTE_LANE_2_1_REG_END 0x011a0918
#define BCHP_DDR34_PHY_BYTE_LANE_3_1_REG_START 0x011a0a00
#define BCHP_DDR34_PHY_BYTE_LANE_3_1_REG_END 0x011a0b18
#define BCHP_DDR34_PHY_ECC_LANE_1_REG_START 0x011a0c00
#define BCHP_DDR34_PHY_ECC_LANE_1_REG_END 0x011a0d18
#define BCHP_DPFE_CONTROLLER_1_REG_START 0x011a2000
#define BCHP_DPFE_CONTROLLER_1_REG_END 0x011a2050
#define BCHP_DPFE_EDIS_1_0_REG_START 0x011a2400
#define BCHP_DPFE_EDIS_1_0_REG_END 0x011a2560
#define BCHP_DPFE_EDIS_1_1_REG_START 0x011a2800
#define BCHP_DPFE_EDIS_1_1_REG_END 0x011a2960
#define BCHP_MEMC_SENTINEL_0_1_REG_START 0x011c0000
#define BCHP_MEMC_SENTINEL_0_1_REG_END 0x011ffffc
/***************************************************************************
*AUD_FMM_MS_CTRL
***************************************************************************/
/***************************************************************************
*ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer
***************************************************************************/
/* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */
#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff
#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0
/***************************************************************************
*ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits
***************************************************************************/
/* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */
#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK 0xffffffff
#define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0
/***************************************************************************
*AUD_FMM_OP_CTRL
***************************************************************************/
/***************************************************************************
*ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI
***************************************************************************/
/* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */
#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff
#define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0
/***************************************************************************
*BVN_MVFD_MFD
***************************************************************************/
/***************************************************************************
*DRAM_DATA_STRUCTURE - DRAM Data Structure
***************************************************************************/
/* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
#define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
/***************************************************************************
*BVN_MVFD_MFD_8B_HD
***************************************************************************/
/***************************************************************************
*DRAM_DATA_STRUCTURE - DRAM Data Structure
***************************************************************************/
/* BVN_MVFD_MFD_8B_HD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
#define BCHP_BVN_MVFD_MFD_8B_HD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
#define BCHP_BVN_MVFD_MFD_8B_HD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
/***************************************************************************
*BVN_MVFD_MFD_8B_UHD
***************************************************************************/
/***************************************************************************
*DRAM_DATA_STRUCTURE - DRAM Data Structure
***************************************************************************/
/* BVN_MVFD_MFD_8B_UHD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
#define BCHP_BVN_MVFD_MFD_8B_UHD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
#define BCHP_BVN_MVFD_MFD_8B_UHD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
/***************************************************************************
*BVN_MVFD_VFD
***************************************************************************/
/***************************************************************************
*DRAM_DATA_STRUCTURE - DRAM Data Structure
***************************************************************************/
/* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
#define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
/***************************************************************************
*BVN_MVFD_VFD_8B
***************************************************************************/
/***************************************************************************
*DRAM_DATA_STRUCTURE - DRAM Data Structure
***************************************************************************/
/* BVN_MVFD_VFD_8B :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
#define BCHP_BVN_MVFD_VFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
#define BCHP_BVN_MVFD_VFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
/***************************************************************************
*BVN_MVFD_VFD_8B_NODCD
***************************************************************************/
/***************************************************************************
*DRAM_DATA_STRUCTURE - DRAM Data Structure
***************************************************************************/
/* BVN_MVFD_VFD_8B_NODCD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
#define BCHP_BVN_MVFD_VFD_8B_NODCD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
#define BCHP_BVN_MVFD_VFD_8B_NODCD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
/***************************************************************************
*DPFE_CONTROLLER
***************************************************************************/
/***************************************************************************
*Command_Code - DPFE Command Code Format
***************************************************************************/
/* DPFE_CONTROLLER :: Command_Code :: reserved0 [07:05] */
#define BCHP_DPFE_CONTROLLER_Command_Code_reserved0_MASK 0xe0
#define BCHP_DPFE_CONTROLLER_Command_Code_reserved0_SHIFT 5
/* union - case code [04:00] */
/* DPFE_CONTROLLER :: Command_Code :: code :: all [04:00] */
#define BCHP_DPFE_CONTROLLER_Command_Code_code_all_MASK 0x1f
#define BCHP_DPFE_CONTROLLER_Command_Code_code_all_SHIFT 0
/* union - case bits [04:00] */
/* DPFE_CONTROLLER :: Command_Code :: bits :: cs [04:03] */
#define BCHP_DPFE_CONTROLLER_Command_Code_bits_cs_MASK 0x18
#define BCHP_DPFE_CONTROLLER_Command_Code_bits_cs_SHIFT 3
/* DPFE_CONTROLLER :: Command_Code :: bits :: ras [02:02] */
#define BCHP_DPFE_CONTROLLER_Command_Code_bits_ras_MASK 0x04
#define BCHP_DPFE_CONTROLLER_Command_Code_bits_ras_SHIFT 2
/* DPFE_CONTROLLER :: Command_Code :: bits :: cas [01:01] */
#define BCHP_DPFE_CONTROLLER_Command_Code_bits_cas_MASK 0x02
#define BCHP_DPFE_CONTROLLER_Command_Code_bits_cas_SHIFT 1
/* DPFE_CONTROLLER :: Command_Code :: bits :: we [00:00] */
#define BCHP_DPFE_CONTROLLER_Command_Code_bits_we_MASK 0x01
#define BCHP_DPFE_CONTROLLER_Command_Code_bits_we_SHIFT 0
/***************************************************************************
*Row_Addr - DPFE Row Address Format
***************************************************************************/
/* DPFE_CONTROLLER :: Row_Addr :: reserved0 [23:17] */
#define BCHP_DPFE_CONTROLLER_Row_Addr_reserved0_MASK 0xfe0000
#define BCHP_DPFE_CONTROLLER_Row_Addr_reserved0_SHIFT 17
/* DPFE_CONTROLLER :: Row_Addr :: Row_Addr [16:00] */
#define BCHP_DPFE_CONTROLLER_Row_Addr_Row_Addr_MASK 0x01ffff
#define BCHP_DPFE_CONTROLLER_Row_Addr_Row_Addr_SHIFT 0
/***************************************************************************
*Bank_Addr - DPFE Bank Address Format
***************************************************************************/
/* DPFE_CONTROLLER :: Bank_Addr :: reserved0 [07:04] */
#define BCHP_DPFE_CONTROLLER_Bank_Addr_reserved0_MASK 0xf0
#define BCHP_DPFE_CONTROLLER_Bank_Addr_reserved0_SHIFT 4
/* DPFE_CONTROLLER :: Bank_Addr :: Bank_Addr [03:00] */
#define BCHP_DPFE_CONTROLLER_Bank_Addr_Bank_Addr_MASK 0x0f
#define BCHP_DPFE_CONTROLLER_Bank_Addr_Bank_Addr_SHIFT 0
/***************************************************************************
*Post_Command_Delay - DPFE Post Command Delay Format
***************************************************************************/
/* DPFE_CONTROLLER :: Post_Command_Delay :: reserved0 [15:12] */
#define BCHP_DPFE_CONTROLLER_Post_Command_Delay_reserved0_MASK 0xf000
#define BCHP_DPFE_CONTROLLER_Post_Command_Delay_reserved0_SHIFT 12
/* DPFE_CONTROLLER :: Post_Command_Delay :: Post_Command_Delay [11:00] */
#define BCHP_DPFE_CONTROLLER_Post_Command_Delay_Post_Command_Delay_MASK 0x0fff
#define BCHP_DPFE_CONTROLLER_Post_Command_Delay_Post_Command_Delay_SHIFT 0
/***************************************************************************
*GFD
***************************************************************************/
/***************************************************************************
*DRAM_DATA_STRUCTURE - DRAM Data Structure
***************************************************************************/
/* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
#define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
/***************************************************************************
*GFD_HSCL_ONLY
***************************************************************************/
/***************************************************************************
*DRAM_DATA_STRUCTURE - DRAM Data Structure
***************************************************************************/
/* GFD_HSCL_ONLY :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
#define BCHP_GFD_HSCL_ONLY_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
#define BCHP_GFD_HSCL_ONLY_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
/***************************************************************************
*GFD_HSCL_VSCL_ONLY
***************************************************************************/
/***************************************************************************
*DRAM_DATA_STRUCTURE - DRAM Data Structure
***************************************************************************/
/* GFD_HSCL_VSCL_ONLY :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */
#define BCHP_GFD_HSCL_VSCL_ONLY_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff
#define BCHP_GFD_HSCL_VSCL_ONLY_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0
/***************************************************************************
*HIFIDAC_CTRL
***************************************************************************/
/***************************************************************************
*ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset
***************************************************************************/
/* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */
#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff
#define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0
/***************************************************************************
*ABSTRACT_02_MUTE_USAGE - Mute usage
***************************************************************************/
/* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */
#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff
#define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0
/***************************************************************************
*ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change
***************************************************************************/
/* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */
#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff
#define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0
/***************************************************************************
*M2MC
***************************************************************************/
/***************************************************************************
*TYPE_CLUT_COLOR_DATA - color data for color look up table
***************************************************************************/
/* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */
#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK 0xff000000
#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT 24
/* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */
#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK 0x00ff0000
#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT 16
/* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */
#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK 0x0000ff00
#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT 8
/* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */
#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK 0x000000ff
#define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT 0
/***************************************************************************
*LIST_PACKET_ABSTRACT - Linked-List Packet Abstract
***************************************************************************/
/* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */
#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK 0xffffffff
#define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT 0
/***************************************************************************
*LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0
***************************************************************************/
/* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */
#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK 0xf0000000
#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT 28
/* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */
#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK 0x0fffffe0
#define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT 5
/* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */
#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK 0x0000001e
#define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT 1
/* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */
#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK 0x00000001
#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT 0
#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid 0
#define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1
/***************************************************************************
*LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1
***************************************************************************/
/* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK 0xffff8000
#define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT 15
/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK 0x00004000
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT 14
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK 0x00002000
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT 13
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000
#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12
#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK 0x00000800
#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT 11
#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK 0x00000400
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK 0x00000200
#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9
#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK 0x00000100
#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT 8
#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK 0x00000020
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT 5
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004
#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2
#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK 0x00000002
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0
/* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK 0x00000001
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT 0
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1
#define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0
/***************************************************************************
*LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER
***************************************************************************/
/* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */
#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
#define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
/***************************************************************************
*LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER
***************************************************************************/
/* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */
#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
#define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
/***************************************************************************
*LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER
***************************************************************************/
/* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */
#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff
#define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0
/***************************************************************************
*LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT
***************************************************************************/
/* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */
#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK 0xffffffff
#define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT 0
/***************************************************************************
*LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM
***************************************************************************/
/* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */
#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
#define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0
/***************************************************************************
*LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM
***************************************************************************/
/* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */
#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff
#define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0
/***************************************************************************
*LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP
***************************************************************************/
/* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */
#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK 0xffffffff
#define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT 0
/***************************************************************************
*LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY
***************************************************************************/
/* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
#define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
/***************************************************************************
*LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY
***************************************************************************/
/* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */
#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff
#define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0
/***************************************************************************
*LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF
***************************************************************************/
/* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */
#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK 0xffffffff
#define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0
/***************************************************************************
*LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX
***************************************************************************/
/* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */
#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff
#define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0
/***************************************************************************
*LIST_PKT_11_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT
***************************************************************************/
/* M2MC :: LIST_PKT_11_SRC_CLUT :: reserved0 [31:29] */
#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_MASK 0xe0000000
#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_SHIFT 29
/* M2MC :: LIST_PKT_11_SRC_CLUT :: REGISTER_CONTENTS [28:00] */
#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_MASK 0x1fffffff
#define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_SHIFT 0
/***************************************************************************
*PCIE_DMA
***************************************************************************/
/***************************************************************************
*DESC_WORD0 - PCIE DMA Descriptor Word 0
***************************************************************************/
/* PCIE_DMA :: DESC_WORD0 :: MEMORY_ADDRESS [31:00] */
#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_MASK 0xffffffff
#define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_SHIFT 0
/***************************************************************************
*DESC_WORD1 - PCIE DMA Descriptor Word 1
***************************************************************************/
/* PCIE_DMA :: DESC_WORD1 :: PCIE_ADDRESS_LO [31:00] */
#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_MASK 0xffffffff
#define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_SHIFT 0
/***************************************************************************
*DESC_WORD2 - PCIE DMA Descriptor Word 2
***************************************************************************/
/* PCIE_DMA :: DESC_WORD2 :: PCIE_ADDRESS_HI [31:00] */
#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_MASK 0xffffffff
#define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_SHIFT 0
/***************************************************************************
*DESC_WORD3 - PCIE DMA Descriptor Word 3
***************************************************************************/
/* PCIE_DMA :: DESC_WORD3 :: INTERRUPT_ENABLE [31:31] */
#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_MASK 0x80000000
#define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_SHIFT 31
/* PCIE_DMA :: DESC_WORD3 :: reserved0 [30:25] */
#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_MASK 0x7e000000
#define BCHP_PCIE_DMA_DESC_WORD3_reserved0_SHIFT 25
/* PCIE_DMA :: DESC_WORD3 :: DMA_TRANSFER_SIZE [24:00] */
#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_MASK 0x01ffffff
#define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_SHIFT 0
/***************************************************************************
*DESC_WORD4 - PCIE DMA Descriptor Word 4
***************************************************************************/
/* PCIE_DMA :: DESC_WORD4 :: LAST_RECORD_INDICATOR [31:31] */
#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_MASK 0x80000000
#define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_SHIFT 31
/* PCIE_DMA :: DESC_WORD4 :: DMA_DIRECTION [30:30] */
#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MASK 0x40000000
#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_SHIFT 30
#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_PCIE_TO_MEMORY 1
#define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MEMORY_TO_PCIE 0
/* PCIE_DMA :: DESC_WORD4 :: reserved0 [29:03] */
#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_MASK 0x3ffffff8
#define BCHP_PCIE_DMA_DESC_WORD4_reserved0_SHIFT 3
/* PCIE_DMA :: DESC_WORD4 :: DESC_CONTIGUOUS [02:02] */
#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_MASK 0x00000004
#define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_SHIFT 2
/* PCIE_DMA :: DESC_WORD4 :: ENDIAN_XLATE_MODE [01:00] */
#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_MASK 0x00000003
#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SHIFT 0
#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_NO_SWAP 0
#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_16_IN_32 1
#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_32 2
#define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_reserved 3
/***************************************************************************
*DESC_WORD5 - PCIE DMA Descriptor Word 5
***************************************************************************/
/* PCIE_DMA :: DESC_WORD5 :: NEXT_DESC_ADDRESS_LO [31:05] */
#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_MASK 0xffffffe0
#define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_SHIFT 5
/* PCIE_DMA :: DESC_WORD5 :: reserved0 [04:00] */
#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_MASK 0x0000001f
#define BCHP_PCIE_DMA_DESC_WORD5_reserved0_SHIFT 0
/***************************************************************************
*DESC_WORD6 - PCIE DMA Descriptor Word 6
***************************************************************************/
/* PCIE_DMA :: DESC_WORD6 :: NEXT_DESC_ADDRESS_HI [31:00] */
#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_MASK 0xffffffff
#define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_SHIFT 0
/***************************************************************************
*DESC_WORD7 - PCIE DMA Descriptor Word 7
***************************************************************************/
/* PCIE_DMA :: DESC_WORD7 :: reserved0 [31:08] */
#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_MASK 0xffffff00
#define BCHP_PCIE_DMA_DESC_WORD7_reserved0_SHIFT 8
/* PCIE_DMA :: DESC_WORD7 :: MEMORY_ADDRESS_HI [07:00] */
#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_MASK 0x000000ff
#define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_SHIFT 0
/***************************************************************************
*RAAGA_REGSET_DSP_CFG
***************************************************************************/
/***************************************************************************
*AC3_UPS_WORD_00 - AC3 User Parameters Structure Word 0 - DYNRNGSCALEHI
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_00 :: DYNRNGSCALEHI [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_No_compression 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_00_DYNRNGSCALEHI_Full_compression 32767
/***************************************************************************
*AC3_UPS_WORD_01 - AC3 User Parameters Structure Word 1 - DYNRNGSCALELOW
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_01 :: DYNRNGSCALELOW [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_No_compression 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_01_DYNRNGSCALELOW_Full_compression 32767
/***************************************************************************
*AC3_UPS_WORD_02 - AC3 User Parameters Structure Word 2 - PCMSCALEFAC
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_02 :: PCMSCALEFAC [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Full_scale 32767
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_02_PCMSCALEFAC_Mute 0
/***************************************************************************
*AC3_UPS_WORD_03 - AC3 User Parameters Structure Word 3 - COMPMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_03 :: COMPMODE [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_a 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_custom_d 1
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_line 2
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_03_COMPMODE_Comp_rf 3
/***************************************************************************
*AC3_UPS_WORD_04 - AC3 User Parameters Structure Word 4 - DUALMONOMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_04 :: DUALMONOMODE [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Pass_through 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Left_mono 1
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_Right_mono 2
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_04_DUALMONOMODE_True_mono 3
/***************************************************************************
*AC3_UPS_WORD_05 - AC3 User Parameters Structure Word 5 - OUTPUTMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_05 :: OUTPUTMODE [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode11 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode10 1
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode20 2
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode30 3
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode21 4
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode31 5
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode22 6
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_05_OUTPUTMODE_Mode32 7
/***************************************************************************
*AC3_UPS_WORD_06 - AC3 User Parameters Structure Word 6 - OUTLFEON
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_06 :: OUTLFEON [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_Off 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_06_OUTLFEON_On 1
/***************************************************************************
*AC3_UPS_WORD_07 - AC3 User Parameters Structure Word 7 - KCAPABLEMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_07 :: KCAPABLEMODE [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_No_vocal_channels 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V1 1
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Vocal_channel_V2 2
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_07_KCAPABLEMODE_Both_vocal_channels 3
/***************************************************************************
*AC3_UPS_WORD_08 - AC3 User Parameters Structure Word 8 - KARAOKE_PARAMETER_FLAG
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_08 :: KARAOKE_PARAMETER_FLAG [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_Off 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_08_KARAOKE_PARAMETER_FLAG_On 1
/***************************************************************************
*AC3_UPS_WORD_09 - AC3 User Parameters Structure Word 9 - KARAOKE_V1_LEVEL
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_09 :: KARAOKE_V1_LEVEL [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Full_scale 32767
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_09_KARAOKE_V1_LEVEL_Mute 0
/***************************************************************************
*AC3_UPS_WORD_10 - AC3 User Parameters Structure Word 10 - KARAOKE_V1_PAN
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_10 :: KARAOKE_V1_PAN [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_left 32767
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Middle 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_10_KARAOKE_V1_PAN_Hard_right 32768
/***************************************************************************
*AC3_UPS_WORD_11 - AC3 User Parameters Structure Word 11 - KARAOKE_V2_LEVEL
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_11 :: KARAOKE_V2_LEVEL [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Full_scale 32767
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_11_KARAOKE_V2_LEVEL_Mute 0
/***************************************************************************
*AC3_UPS_WORD_12 - AC3 User Parameters Structure Word 12 - KARAOKE_V2_PAN
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_12 :: KARAOKE_V2_PAN [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_left 32767
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Middle 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_12_KARAOKE_V2_PAN_Hard_right 32768
/***************************************************************************
*AC3_UPS_WORD_13 - AC3 User Parameters Structure Word 13 - KARAOKE_GM_LEVEL
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_13 :: KARAOKE_GM_LEVEL [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Full_scale 32767
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_13_KARAOKE_GM_LEVEL_Mute 0
/***************************************************************************
*AC3_UPS_WORD_14 - AC3 User Parameters Structure Word 14 - KARAOKE_GM_PAN
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_14 :: KARAOKE_GM_PAN [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_left 32767
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Middle 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_14_KARAOKE_GM_PAN_Hard_right 32768
/***************************************************************************
*AC3_UPS_WORD_15 - AC3 User Parameters Structure Word 15 - STEREO_MOD
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_15 :: STEREO_MOD [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_Auto 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LtRt 1
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_15_STEREO_MOD_LoRo 2
/***************************************************************************
*AC3_UPS_WORD_16 - AC3 User Parameters Structure Word 16 - USER_DOWNMIX_FLAG
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_16 :: USER_DOWNMIX_FLAG [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_Off 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_16_USER_DOWNMIX_FLAG_On 1
/***************************************************************************
*AC3_UPS_WORD_17_TO_52 - AC3 User Parameters Structure Word 17 to 52 - DRAM_USER_DEFINED_DNMX_COEFFS
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_17_TO_52 :: DRAM_USER_DEFINED_DNMX_COEFFS [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Full_scale 32767
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_17_TO_52_DRAM_USER_DEFINED_DNMX_COEFFS_Mute 0
/***************************************************************************
*AC3_UPS_WORD_53 - AC3 User Parameters Structure Word 53 - DUMMY
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_UPS_WORD_53 :: DUMMY [15:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_MASK 0xffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_UPS_WORD_53_DUMMY_SHIFT 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_00 - AC3 Plus User Parameters Structure Word 0 - COMPMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_00 :: COMPMODE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_00_COMPMODE_SHIFT 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_01 - AC3 Plus User Parameters Structure Word 1 - PCMSCALE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_01 :: PCMSCALE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Full_scale 2147483647
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_01_PCMSCALE_Mute 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_02 - AC3 Plus User Parameters Structure Word 2 - DYNSCALEHIGH
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_02 :: DYNSCALEHIGH [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_02_DYNSCALEHIGH_SHIFT 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_03 - AC3 Plus User Parameters Structure Word 3 - DYNSCALELOW
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_03 :: DYNSCALELOW [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_03_DYNSCALELOW_SHIFT 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_04 - AC3 Plus User Parameters Structure Word 4 - OUTLFE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_04 :: OUTLFE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_04_OUTLFE_SHIFT 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_05 - AC3 Plus User Parameters Structure Word 5 - OUTMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_05 :: OUTMODE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_05_OUTMODE_SHIFT 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_06 - AC3 Plus User Parameters Structure Word 6 - STEREOMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_06 :: STEREOMODE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_06_STEREOMODE_SHIFT 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_07 - AC3 Plus User Parameters Structure Word 7 - DUALMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_07 :: DUALMODE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_07_DUALMODE_SHIFT 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_08 - AC3 Plus User Parameters Structure Word 8 - KMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_08 :: KMODE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_NO_VOCALS 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL1 1
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_VOCAL2 2
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_08_KMODE_GBL_BOTH_VOCALS 3
/***************************************************************************
*AC3_PLUS_UPS_WORD_09 - AC3 Plus User Parameters Structure Word 9 - EXTDNMIX_ENABLED
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_09 :: EXTDNMIX_ENABLED [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_09_EXTDNMIX_ENABLED_SHIFT 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_10_TO_45 - AC3 Plus User Parameters Structure Word 10 to 45 - EXTDNMIXTAB
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_10_TO_45 :: EXTDNMIXTAB [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Full_scale 2147483647
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_10_TO_45_EXTDNMIXTAB_Mute 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_46 - AC3 Plus User Parameters Structure Word 46 - EXTKARAOKE_ENABLED
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_46 :: EXTKARAOKE_ENABLED [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_46_EXTKARAOKE_ENABLED_SHIFT 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_47 - AC3 Plus User Parameters Structure Word 47 - EXT_V1_LEVEL
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_47 :: EXT_V1_LEVEL [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Full_scale 2147483647
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_47_EXT_V1_LEVEL_Mute 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_48 - AC3 Plus User Parameters Structure Word 48 - EXT_V1_PAN
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_48 :: EXT_V1_PAN [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_left 2147483647
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Middle 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_48_EXT_V1_PAN_Hard_right 2147483648
/***************************************************************************
*AC3_PLUS_UPS_WORD_49 - AC3 Plus User Parameters Structure Word 49 - EXT_V2_LEVEL
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_49 :: EXT_V2_LEVEL [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Full_scale 2147483647
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_49_EXT_V2_LEVEL_Mute 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_50 - AC3 Plus User Parameters Structure Word 50 - EXT_V2_PAN
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_50 :: EXT_V2_PAN [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_left 2147483647
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Middle 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_50_EXT_V2_PAN_Hard_right 2147483648
/***************************************************************************
*AC3_PLUS_UPS_WORD_51 - AC3 Plus User Parameters Structure Word 51 - EXT_GM_LEVEL
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_51 :: EXT_GM_LEVEL [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Full_scale 2147483647
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_51_EXT_GM_LEVEL_Mute 0
/***************************************************************************
*AC3_PLUS_UPS_WORD_52 - AC3 Plus User Parameters Structure Word 52 - EXT_GM_PAN
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AC3_PLUS_UPS_WORD_52 :: EXT_GM_PAN [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_left 2147483647
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Middle 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AC3_PLUS_UPS_WORD_52_EXT_GM_PAN_Hard_right 2147483648
/***************************************************************************
*AAC_UPS_WORD_00 - AAC User Parameters Structure Word 0 - XPT_FORMAT
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_00 :: XPT_FORMAT [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_00_XPT_FORMAT_SHIFT 0
/***************************************************************************
*AAC_UPS_WORD_01 - AAC User Parameters Structure Word 1 - DRC_GAIN_CONTROL_COMPRESS
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_01 :: DRC_GAIN_CONTROL_COMPRESS [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_01_DRC_GAIN_CONTROL_COMPRESS_SHIFT 0
/***************************************************************************
*AAC_UPS_WORD_02 - AAC User Parameters Structure Word 2 - DRC_GAIN_CONTROL_BOOST
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_02 :: DRC_GAIN_CONTROL_BOOST [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_02_DRC_GAIN_CONTROL_BOOST_SHIFT 0
/***************************************************************************
*AAC_UPS_WORD_03 - AAC User Parameters Structure Word 3 - DRC_TARGET_LEVEL
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_03 :: DRC_TARGET_LEVEL [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_03_DRC_TARGET_LEVEL_SHIFT 0
/***************************************************************************
*AAC_UPS_WORD_04 - AAC User Parameters Structure Word 4 - DOWNMIX_TYPE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_04 :: DOWNMIX_TYPE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_04_DOWNMIX_TYPE_SHIFT 0
/***************************************************************************
*AAC_UPS_WORD_05 - AAC User Parameters Structure Word 5 - OUTMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_05 :: OUTMODE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Stereo 2
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_05_OUTMODE_Mono 1
/***************************************************************************
*AAC_UPS_WORD_06 - AAC User Parameters Structure Word 6 - DUALMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: AAC_UPS_WORD_06 :: DUALMODE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Left_mono 0
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Right_mono 1
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_stereo 2
#define BCHP_RAAGA_REGSET_DSP_CFG_AAC_UPS_WORD_06_DUALMODE_Dual_mixmono 3
/***************************************************************************
*DTS_CORE_UPS_WORD_00 - DTS Core User Parameters Structure Word 0 - OUTMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_00 :: OUTMODE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Stereo 0
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_00_OUTMODE_Mono 1
/***************************************************************************
*DTS_CORE_UPS_WORD_01 - DTS Core User Parameters Structure Word 1 - OUTLFE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_01 :: OUTLFE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_01_OUTLFE_SHIFT 0
/***************************************************************************
*DTS_CORE_UPS_WORD_02 - DTS Core User Parameters Structure Word 2 - DUALMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_02 :: DUALMODE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_stereo 0
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_leftmono 1
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_rghtmono 2
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_02_DUALMODE_Dual_mixmono 3
/***************************************************************************
*DTS_CORE_UPS_WORD_03 - DTS Core User Parameters Structure Word 3 - STEREOMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_03 :: STEREOMODE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereomode_auto 0
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LTRT 1
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_03_STEREOMODE_Stereodmix_LORO 2
/***************************************************************************
*DTS_CORE_UPS_WORD_04 - DTS Core User Parameters Structure Word 4 - EXTDNMIX_ENABLED
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_04 :: EXTDNMIX_ENABLED [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_04_EXTDNMIX_ENABLED_SHIFT 0
/***************************************************************************
*DTS_CORE_UPS_WORD_05_TO_40 - DTS Core User Parameters Structure Word 5 to 40 - EXTDNMIXTAB
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: DTS_CORE_UPS_WORD_05_TO_40 :: EXTDNMIXTAB [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Full_scale 2147483647
#define BCHP_RAAGA_REGSET_DSP_CFG_DTS_CORE_UPS_WORD_05_TO_40_EXTDNMIXTAB_Mute 0
/***************************************************************************
*LPCM_UPS_WORD_00 - LPCM User Parameters Structure Word 0 - EXTDNMIX_ENABLED
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_00 :: EXTDNMIX_ENABLED [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_00_EXTDNMIX_ENABLED_SHIFT 0
/***************************************************************************
*LPCM_UPS_WORD_01_TO_16 - LPCM User Parameters Structure Word 1 to 16 - EXTDNMIXTAB
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: LPCM_UPS_WORD_01_TO_16 :: EXTDNMIXTAB [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Full_scale 2147483647
#define BCHP_RAAGA_REGSET_DSP_CFG_LPCM_UPS_WORD_01_TO_16_EXTDNMIXTAB_Mute 0
/***************************************************************************
*MPEG_UPS_WORD_00 - MPEG User Parameters Structure Word 0 - OUTMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_00 :: OUTMODE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Stereo 0
#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_00_OUTMODE_Mono 1
/***************************************************************************
*MPEG_UPS_WORD_01 - MPEG User Parameters Structure Word 1 - DUALMODE
***************************************************************************/
/* RAAGA_REGSET_DSP_CFG :: MPEG_UPS_WORD_01 :: DUALMODE [31:00] */
#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_MASK 0xffffffff
#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_SHIFT 0
#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Left_mono 0
#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Right_mono 1
#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_stereo 2
#define BCHP_RAAGA_REGSET_DSP_CFG_MPEG_UPS_WORD_01_DUALMODE_Dual_mixmono 3
/***************************************************************************
*RDC
***************************************************************************/
/***************************************************************************
*RUL - RUL Command.
***************************************************************************/
/* RDC :: RUL :: opcode [31:24] */
#define BCHP_RDC_RUL_opcode_MASK 0xff000000
#define BCHP_RDC_RUL_opcode_SHIFT 24
#define BCHP_RDC_RUL_opcode_NOP 0
#define BCHP_RDC_RUL_opcode_REG_WRITE_IMM 1
#define BCHP_RDC_RUL_opcode_REG_WRITE 2
#define BCHP_RDC_RUL_opcode_REG_READ 3
#define BCHP_RDC_RUL_opcode_LOAD_IMM 4
#define BCHP_RDC_RUL_opcode_WINDOW_WRITE 5
#define BCHP_RDC_RUL_opcode_BLOCK_WRITE 6
#define BCHP_RDC_RUL_opcode_WINDOW_COPY 7
#define BCHP_RDC_RUL_opcode_BLOCK_COPY 8
#define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK 9
#define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW 10
#define BCHP_RDC_RUL_opcode_AND 11
#define BCHP_RDC_RUL_opcode_AND_IMM 12
#define BCHP_RDC_RUL_opcode_OR 13
#define BCHP_RDC_RUL_opcode_OR_IMM 14
#define BCHP_RDC_RUL_opcode_XOR 15
#define BCHP_RDC_RUL_opcode_XOR_IMM 16
#define BCHP_RDC_RUL_opcode_NOT 17
#define BCHP_RDC_RUL_opcode_ROTATE_RIGHT 18
#define BCHP_RDC_RUL_opcode_SUM 19
#define BCHP_RDC_RUL_opcode_SUM_IMM 20
#define BCHP_RDC_RUL_opcode_COND_SKIP 21
#define BCHP_RDC_RUL_opcode_SKIP 22
#define BCHP_RDC_RUL_opcode_EXIT 23
#define BCHP_RDC_RUL_opcode_WAIT_EOP 24
#define BCHP_RDC_RUL_opcode_PLACEHOLDER 255
/* RDC :: RUL :: reserved0 [23:23] */
#define BCHP_RDC_RUL_reserved0_MASK 0x00800000
#define BCHP_RDC_RUL_reserved0_SHIFT 23
/* union - case rdc_args [22:00] */
/* RDC :: RUL :: rdc_args :: rotation [22:18] */
#define BCHP_RDC_RUL_rdc_args_rotation_MASK 0x007c0000
#define BCHP_RDC_RUL_rdc_args_rotation_SHIFT 18
/* RDC :: RUL :: rdc_args :: src1 [17:12] */
#define BCHP_RDC_RUL_rdc_args_src1_MASK 0x0003f000
#define BCHP_RDC_RUL_rdc_args_src1_SHIFT 12
/* RDC :: RUL :: rdc_args :: src2 [11:06] */
#define BCHP_RDC_RUL_rdc_args_src2_MASK 0x00000fc0
#define BCHP_RDC_RUL_rdc_args_src2_SHIFT 6
/* RDC :: RUL :: rdc_args :: dest [05:00] */
#define BCHP_RDC_RUL_rdc_args_dest_MASK 0x0000003f
#define BCHP_RDC_RUL_rdc_args_dest_SHIFT 0
/* union - case reg_args [22:00] */
/* RDC :: RUL :: reg_args :: rotation [22:18] */
#define BCHP_RDC_RUL_reg_args_rotation_MASK 0x007c0000
#define BCHP_RDC_RUL_reg_args_rotation_SHIFT 18
/* RDC :: RUL :: reg_args :: src1 [17:12] */
#define BCHP_RDC_RUL_reg_args_src1_MASK 0x0003f000
#define BCHP_RDC_RUL_reg_args_src1_SHIFT 12
/* RDC :: RUL :: reg_args :: count [11:00] */
#define BCHP_RDC_RUL_reg_args_count_MASK 0x00000fff
#define BCHP_RDC_RUL_reg_args_count_SHIFT 0
/* union - case eop_args [22:00] */
/* RDC :: RUL :: eop_args :: reserved0 [22:08] */
#define BCHP_RDC_RUL_eop_args_reserved0_MASK 0x007fff00
#define BCHP_RDC_RUL_eop_args_reserved0_SHIFT 8
/* RDC :: RUL :: eop_args :: eop [07:00] */
#define BCHP_RDC_RUL_eop_args_eop_MASK 0x000000ff
#define BCHP_RDC_RUL_eop_args_eop_SHIFT 0
/***************************************************************************
*EOP_ID_256 - EOP_ID
***************************************************************************/
/* RDC :: EOP_ID_256 :: eop_id [255:00] */
#define BCHP_RDC_EOP_ID_256_eop_id_MASK 0x0000000000000000000000000000000000000000000000000000000000000000
#define BCHP_RDC_EOP_ID_256_eop_id_SHIFT 0
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_0 0
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_1 1
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_2 2
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_3 3
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_4 4
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_5 5
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_6 6
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_7 7
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_0 8
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_1 9
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_2 10
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_3 11
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_4 12
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_5 13
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_6 14
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_7 15
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_0 16
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_1 17
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_2 18
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_3 19
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_4 20
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_5 21
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_6 22
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_7 23
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_0 24
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_1 25
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_2 26
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_3 27
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_4 28
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_5 29
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_6 30
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_pfa_0 31
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_0 32
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_1 33
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_2 34
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_3 35
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_4 36
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_5 37
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_6 38
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_7 39
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_nvp_0 40
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_s3dh_0 41
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_v0_be 42
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_tntd_0 43
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_xsrc_0 44
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_xsrc_1 45
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_0 46
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_1 47
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_0 48
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_1 49
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_2 50
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_3 51
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_4 52
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_5 53
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_6 54
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_7 55
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_8 56
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_9 57
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_10 58
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_11 59
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_12 60
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_13 61
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_2 62
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_3 63
#define BCHP_RDC_EOP_ID_256_eop_id_mfd_0 64
#define BCHP_RDC_EOP_ID_256_eop_id_mfd_1 65
#define BCHP_RDC_EOP_ID_256_eop_id_mfd_2 66
#define BCHP_RDC_EOP_ID_256_eop_id_mfd_3 67
#define BCHP_RDC_EOP_ID_256_eop_id_mfd_4 68
#define BCHP_RDC_EOP_ID_256_eop_id_mfd_5 69
#define BCHP_RDC_EOP_ID_256_eop_id_mfd_6 70
#define BCHP_RDC_EOP_ID_256_eop_id_mfd_7 71
#define BCHP_RDC_EOP_ID_256_eop_id_vfd_0 72
#define BCHP_RDC_EOP_ID_256_eop_id_vfd_1 73
#define BCHP_RDC_EOP_ID_256_eop_id_vfd_2 74
#define BCHP_RDC_EOP_ID_256_eop_id_vfd_3 75
#define BCHP_RDC_EOP_ID_256_eop_id_vfd_4 76
#define BCHP_RDC_EOP_ID_256_eop_id_vfd_5 77
#define BCHP_RDC_EOP_ID_256_eop_id_vfd_6 78
#define BCHP_RDC_EOP_ID_256_eop_id_vfd_7 79
#define BCHP_RDC_EOP_ID_256_eop_id_cap_0 80
#define BCHP_RDC_EOP_ID_256_eop_id_cap_1 81
#define BCHP_RDC_EOP_ID_256_eop_id_cap_2 82
#define BCHP_RDC_EOP_ID_256_eop_id_cap_3 83
#define BCHP_RDC_EOP_ID_256_eop_id_cap_4 84
#define BCHP_RDC_EOP_ID_256_eop_id_cap_5 85
#define BCHP_RDC_EOP_ID_256_eop_id_cap_6 86
#define BCHP_RDC_EOP_ID_256_eop_id_cap_7 87
#define BCHP_RDC_EOP_ID_256_eop_id_gfd_0 88
#define BCHP_RDC_EOP_ID_256_eop_id_gfd_1 89
#define BCHP_RDC_EOP_ID_256_eop_id_gfd_2 90
#define BCHP_RDC_EOP_ID_256_eop_id_gfd_3 91
#define BCHP_RDC_EOP_ID_256_eop_id_gfd_4 92
#define BCHP_RDC_EOP_ID_256_eop_id_gfd_5 93
#define BCHP_RDC_EOP_ID_256_eop_id_gfd_6 94
#define BCHP_RDC_EOP_ID_256_eop_id_gfd_7 95
#define BCHP_RDC_EOP_ID_256_eop_id_scl_0 96
#define BCHP_RDC_EOP_ID_256_eop_id_scl_1 97
#define BCHP_RDC_EOP_ID_256_eop_id_scl_2 98
#define BCHP_RDC_EOP_ID_256_eop_id_scl_3 99
#define BCHP_RDC_EOP_ID_256_eop_id_scl_4 100
#define BCHP_RDC_EOP_ID_256_eop_id_scl_5 101
#define BCHP_RDC_EOP_ID_256_eop_id_scl_6 102
#define BCHP_RDC_EOP_ID_256_eop_id_scl_7 103
#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_0 104
#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_1 105
#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_2 106
#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_3 107
#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_4 108
#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_5 109
#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_6 110
#define BCHP_RDC_EOP_ID_256_eop_id_xsrc_7 111
#define BCHP_RDC_EOP_ID_256_eop_id_mvp_0 112
#define BCHP_RDC_EOP_ID_256_eop_id_mvp_1 113
#define BCHP_RDC_EOP_ID_256_eop_id_mvp_2 114
#define BCHP_RDC_EOP_ID_256_eop_id_mvp_3 115
#define BCHP_RDC_EOP_ID_256_eop_id_mvp_4 116
#define BCHP_RDC_EOP_ID_256_eop_id_mvp_5 117
#define BCHP_RDC_EOP_ID_256_eop_id_mvp_6 118
#define BCHP_RDC_EOP_ID_256_eop_id_mvp_7 119
#define BCHP_RDC_EOP_ID_256_eop_id_dnr_0 120
#define BCHP_RDC_EOP_ID_256_eop_id_dnr_1 121
#define BCHP_RDC_EOP_ID_256_eop_id_dnr_2 122
#define BCHP_RDC_EOP_ID_256_eop_id_dnr_3 123
#define BCHP_RDC_EOP_ID_256_eop_id_dnr_4 124
#define BCHP_RDC_EOP_ID_256_eop_id_dnr_5 125
#define BCHP_RDC_EOP_ID_256_eop_id_dnr_6 126
#define BCHP_RDC_EOP_ID_256_eop_id_dnr_7 127
#define BCHP_RDC_EOP_ID_256_eop_id_cmp_0 128
#define BCHP_RDC_EOP_ID_256_eop_id_cmp_1 129
#define BCHP_RDC_EOP_ID_256_eop_id_cmp_2 130
#define BCHP_RDC_EOP_ID_256_eop_id_cmp_3 131
#define BCHP_RDC_EOP_ID_256_eop_id_cmp_4 132
#define BCHP_RDC_EOP_ID_256_eop_id_cmp_5 133
#define BCHP_RDC_EOP_ID_256_eop_id_cmp_6 134
#define BCHP_RDC_EOP_ID_256_eop_id_cmp_7 135
#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_0 136
#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_1 137
#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_2 138
#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_3 139
#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_4 140
#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_5 141
#define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_6 142
#define BCHP_RDC_EOP_ID_256_eop_id_tpg_0 143
#define BCHP_RDC_EOP_ID_256_eop_id_vec_0 144
#define BCHP_RDC_EOP_ID_256_eop_id_vec_1 145
#define BCHP_RDC_EOP_ID_256_eop_id_vec_2 146
#define BCHP_RDC_EOP_ID_256_eop_id_vec_3 147
#define BCHP_RDC_EOP_ID_256_eop_id_vec_4 148
#define BCHP_RDC_EOP_ID_256_eop_id_vec_5 149
#define BCHP_RDC_EOP_ID_256_eop_id_vec_6 150
#define BCHP_RDC_EOP_ID_256_eop_id_vec_7 151
#define BCHP_RDC_EOP_ID_256_eop_id_lbox_0 152
#define BCHP_RDC_EOP_ID_256_eop_id_lbox_1 153
#define BCHP_RDC_EOP_ID_256_eop_id_lbox_2 154
#define BCHP_RDC_EOP_ID_256_eop_id_lbox_3 155
#define BCHP_RDC_EOP_ID_256_eop_id_lbox_4 156
#define BCHP_RDC_EOP_ID_256_eop_id_lbox_5 157
#define BCHP_RDC_EOP_ID_256_eop_id_lbox_6 158
#define BCHP_RDC_EOP_ID_256_eop_id_pfa_0 159
#define BCHP_RDC_EOP_ID_256_eop_id_crc_0 160
#define BCHP_RDC_EOP_ID_256_eop_id_crc_1 161
#define BCHP_RDC_EOP_ID_256_eop_id_crc_2 162
#define BCHP_RDC_EOP_ID_256_eop_id_crc_3 163
#define BCHP_RDC_EOP_ID_256_eop_id_hist_0 164
#define BCHP_RDC_EOP_ID_256_eop_id_hist_1 165
#define BCHP_RDC_EOP_ID_256_eop_id_psm_0 166
#define BCHP_RDC_EOP_ID_256_eop_id_plm_0 167
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_0 168
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_1 169
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_2 170
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_3 171
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_4 172
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_5 173
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_6 174
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_7 175
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_0 176
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_1 177
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_2 178
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_3 179
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_0 180
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_1 181
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_psm_0 182
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_plm_0 183
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v0 184
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v0 185
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v0 186
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v0 187
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v0 188
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v0 189
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v0 190
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v0 191
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v1 192
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v1 193
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v1 194
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v1 195
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v1 196
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v1 197
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v1 198
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v1 199
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_0 200
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_1 201
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_2 202
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_3 203
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_4 204
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_5 205
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_6 206
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_7 207
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_b3dc_0 208
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_frc_0 209
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_0 210
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_1 211
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_2 212
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_3 213
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_4 214
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_5 215
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_0 216
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_1 217
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_2 218
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_3 219
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_4 220
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_5 221
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_6 222
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_7 223
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_8 224
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_9 225
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_10 226
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_11 227
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_12 228
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_13 229
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_14 230
#define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_9 231
#define BCHP_RDC_EOP_ID_256_eop_id_nvp_0 232
#define BCHP_RDC_EOP_ID_256_eop_id_s3dh_0 233
#define BCHP_RDC_EOP_ID_256_eop_id_v0_be 234
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_0 235
#define BCHP_RDC_EOP_ID_256_eop_id_gfd_0_1 236
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_2 237
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_3 238
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_4 239
#define BCHP_RDC_EOP_ID_256_eop_id_b3dc_0 240
#define BCHP_RDC_EOP_ID_256_eop_id_frc_0 241
#define BCHP_RDC_EOP_ID_256_eop_id_pdpf_0 242
#define BCHP_RDC_EOP_ID_256_eop_id_pdpb_0 243
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_5 244
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_6 245
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_7 246
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_8 247
#define BCHP_RDC_EOP_ID_256_eop_id_tntd_0 248
#define BCHP_RDC_EOP_ID_256_eop_id_vec_hddvi_0_passthr 249
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_11 250
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_12 251
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_13 252
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_14 253
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_15 254
#define BCHP_RDC_EOP_ID_256_eop_id_reserved_16 255
/***************************************************************************
*SPDIF_RCVR_CTRL
***************************************************************************/
/***************************************************************************
*ABSTRACT_INTERRUPT_HANDLING - Interrupt Handling
***************************************************************************/
/* SPDIF_RCVR_CTRL :: ABSTRACT_INTERRUPT_HANDLING :: MORE_INFORMATION [31:00] */
#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_MASK 0xffffffff
#define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_SHIFT 0
/***************************************************************************
*VICE2_REGSET_MISC
***************************************************************************/
/***************************************************************************
*DCCM - registers interface address offset in DCCM.
***************************************************************************/
/* VICE2_REGSET_MISC :: DCCM :: INTERFACE [31:16] */
#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MASK 0xffff0000
#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_SHIFT 16
#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_HOST2VICE_OFFSET 0
#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_VICE2HOST_OFFSET 4
#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_BVN2VICE_OFFSET 8
#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_0_START 16
#define BCHP_VICE2_REGSET_MISC_DCCM_INTERFACE_MBOX_1_START 40
/* VICE2_REGSET_MISC :: DCCM :: REVISION [15:00] */
#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_MASK 0x0000ffff
#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_SHIFT 0
#define BCHP_VICE2_REGSET_MISC_DCCM_REVISION_ID 1
/***************************************************************************
*MBOX - MBOX registers interface address offset.
***************************************************************************/
/* VICE2_REGSET_MISC :: MBOX :: INTERFACE [31:16] */
#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_MASK 0xffff0000
#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SHIFT 16
#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_00_BVB_PIC_SIZE_OFFSET 0
#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_01_SAMPLE_ASPECT_RATIO_OFFSET 4
#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_02_PIC_INFO_OFFSET 8
#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_03_ORIGINAL_PTS_OFFSET 12
#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_04_STG_PICTURE_ID_OFFSET 16
#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_DWORD_05_BARDATA_INFO_OFFSET 20
#define BCHP_VICE2_REGSET_MISC_MBOX_INTERFACE_SIZE 6
/* VICE2_REGSET_MISC :: MBOX :: MAJORREVISION [15:08] */
#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_MASK 0x0000ff00
#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_SHIFT 8
#define BCHP_VICE2_REGSET_MISC_MBOX_MAJORREVISION_ID 1
/* VICE2_REGSET_MISC :: MBOX :: MINORREVISION [07:00] */
#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_MASK 0x000000ff
#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_SHIFT 0
#define BCHP_VICE2_REGSET_MISC_MBOX_MINORREVISION_ID 0
/***************************************************************************
*DWORD_00_BVB_PIC_SIZE - BVB Picture Size
***************************************************************************/
/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: H_SIZE [31:16] */
#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_MASK 0xffff0000
#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_H_SIZE_SHIFT 16
/* VICE2_REGSET_MISC :: DWORD_00_BVB_PIC_SIZE :: V_SIZE [15:00] */
#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_MASK 0x0000ffff
#define BCHP_VICE2_REGSET_MISC_DWORD_00_BVB_PIC_SIZE_V_SIZE_SHIFT 0
/***************************************************************************
*DWORD_01_SAMPLE_ASPECT_RATIO - Sample Aspect Ratio
***************************************************************************/
/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: H_SIZE [31:16] */
#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_MASK 0xffff0000
#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_H_SIZE_SHIFT 16
/* VICE2_REGSET_MISC :: DWORD_01_SAMPLE_ASPECT_RATIO :: V_SIZE [15:00] */
#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_MASK 0x0000ffff
#define BCHP_VICE2_REGSET_MISC_DWORD_01_SAMPLE_ASPECT_RATIO_V_SIZE_SHIFT 0
/***************************************************************************
*DWORD_02_PIC_INFO - Picture Information
***************************************************************************/
/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: FRAME_RATE [31:16] */
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_MASK 0xffff0000
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_FRAME_RATE_SHIFT 16
/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: SRC_PIC_TYPE [15:12] */
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_MASK 0x0000f000
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_SHIFT 12
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_UNKNOWN 0
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_I 1
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_P 2
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_SRC_PIC_TYPE_B 3
/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: POLARITY [11:10] */
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_MASK 0x00000c00
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_SHIFT 10
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_TOP 0
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_BOT 1
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_POLARITY_FRAME 2
/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: REPEAT [09:09] */
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_MASK 0x00000200
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_SHIFT 9
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_DISABLE 0
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_REPEAT_ENABLE 1
/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: IGNORE [08:08] */
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_MASK 0x00000100
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_SHIFT 8
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_DISABLE 0
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_IGNORE_ENABLE 1
/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: LAST [07:07] */
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_MASK 0x00000080
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_SHIFT 7
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_FALSE 0
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_LAST_TRUE 1
/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: CHANNELCHANGE [06:06] */
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_MASK 0x00000040
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_SHIFT 6
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_FALSE 0
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_CHANNELCHANGE_TRUE 1
/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: reserved0 [05:05] */
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_MASK 0x00000020
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_reserved0_SHIFT 5
/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: ACTIVEFORMATDATA [04:04] */
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_MASK 0x00000010
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_SHIFT 4
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_FALSE 0
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATA_TRUE 1
/* VICE2_REGSET_MISC :: DWORD_02_PIC_INFO :: ACTIVEFORMATDATAMODE [03:00] */
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATAMODE_MASK 0x0000000f
#define BCHP_VICE2_REGSET_MISC_DWORD_02_PIC_INFO_ACTIVEFORMATDATAMODE_SHIFT 0
/***************************************************************************
*DWORD_03_ORIGINAL_PTS - Source PTS Value
***************************************************************************/
/* VICE2_REGSET_MISC :: DWORD_03_ORIGINAL_PTS :: VAL [31:00] */
#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_MASK 0xffffffff
#define BCHP_VICE2_REGSET_MISC_DWORD_03_ORIGINAL_PTS_VAL_SHIFT 0
/***************************************************************************
*DWORD_04_STG_PICTURE_ID - STG Picture ID
***************************************************************************/
/* VICE2_REGSET_MISC :: DWORD_04_STG_PICTURE_ID :: VAL [31:00] */
#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_MASK 0xffffffff
#define BCHP_VICE2_REGSET_MISC_DWORD_04_STG_PICTURE_ID_VAL_SHIFT 0
/***************************************************************************
*DWORD_05_BARDATA_INFO - bar data Information
***************************************************************************/
/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: reserved0 [31:30] */
#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_reserved0_MASK 0xc0000000
#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_reserved0_SHIFT 30
/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: TOPLEFTBARVALUE [29:16] */
#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_TOPLEFTBARVALUE_MASK 0x3fff0000
#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_TOPLEFTBARVALUE_SHIFT 16
/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: BARDATATYPE [15:14] */
#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_MASK 0x0000c000
#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_SHIFT 14
#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_invalidBarData 0
#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_TopBottom 1
#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_LeftRight 2
#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BARDATATYPE_reserved 3
/* VICE2_REGSET_MISC :: DWORD_05_BARDATA_INFO :: BOTRIGHTBARVALUE [13:00] */
#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BOTRIGHTBARVALUE_MASK 0x00003fff
#define BCHP_VICE2_REGSET_MISC_DWORD_05_BARDATA_INFO_BOTRIGHTBARVALUE_SHIFT 0
/***************************************************************************
*XPT_RAVE
***************************************************************************/
/***************************************************************************
*NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples
***************************************************************************/
/* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */
#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff
#define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0
/***************************************************************************
*NOTEB_STREAM_TYPE_SETUP - Stream Type Setup
***************************************************************************/
/* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */
#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff
#define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0
/***************************************************************************
*NOTEC_PES_LAYER_SELECTION - PES Layer Selection
***************************************************************************/
/* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */
#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff
#define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0
/***************************************************************************
*NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general
***************************************************************************/
/* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */
#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff
#define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0
/***************************************************************************
*NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video
***************************************************************************/
/* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */
#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff
#define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0
/***************************************************************************
*NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video
***************************************************************************/
/* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */
#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff
#define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0
/***************************************************************************
*NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio
***************************************************************************/
/* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */
#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff
#define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0
/***************************************************************************
*NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio
***************************************************************************/
/* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */
#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff
#define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0
/***************************************************************************
*NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
***************************************************************************/
/* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */
#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff
#define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0
/***************************************************************************
*NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio
***************************************************************************/
/* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */
#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff
#define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0
/***************************************************************************
*NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio
***************************************************************************/
/* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */
#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff
#define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0
#endif /* #ifndef BCHP_COMMON_H__ */
/* End of File */