| /**************************************************************************** |
| * Copyright (c) 1999-2015, Broadcom Corporation |
| * All Rights Reserved |
| * Confidential Property of Broadcom Corporation |
| * |
| * |
| * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
| * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
| * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Sat Oct 10 03:12:36 2015 |
| * Full Compile MD5 Checksum d9086034aa2cc6f9a99dc8c63a00d9b3 |
| * (minus title and desc) |
| * MD5 Checksum 5b6751e69633ab9bdfaa661db7820c66 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB.pm 360 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * Script Source /projects/stbgit/bin/gen_rdb.pl |
| * DVTSWVER n/a |
| * |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_COMMON_H__ |
| #define BCHP_COMMON_H__ |
| |
| /** |
| * m = memory, c = core, r = register, f = field, d = data. |
| */ |
| #if !defined(GET_FIELD) && !defined(SET_FIELD) |
| #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK |
| #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT |
| |
| #define GET_FIELD(m,c,r,f) \ |
| ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f))) |
| |
| #define SET_FIELD(m,c,r,f,d) \ |
| ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d)) << BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f)))) |
| |
| #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) |
| #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) |
| #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) |
| |
| #endif /* GET & SET */ |
| |
| /*************************************************************************** |
| *BCM7271_A0 |
| ***************************************************************************/ |
| #define BCHP_PHYSICAL_OFFSET 0xd0000000 |
| #define BCHP_REGISTER_START 0x20000000 /* HEVD_OL_CPU_REGS_0 is first */ |
| #define BCHP_REGISTER_END 0x2190ae04 /* WLAN_DOT11_SLAVE is last */ |
| #define BCHP_REGISTER_SIZE 0x00642b81 /* Number of registers */ |
| |
| /**************************************************************************** |
| * Core instance register start address. |
| ***************************************************************************/ |
| #define BCHP_HEVD_OL_CPU_REGS_0_REG_START 0x20000000 |
| #define BCHP_HEVD_OL_CPU_REGS_0_REG_END 0x20000108 |
| #define BCHP_HEVD_OL_CPU_DMA_0_REG_START 0x20000400 |
| #define BCHP_HEVD_OL_CPU_DMA_0_REG_END 0x20000440 |
| #define BCHP_HEVD_OL_CPU_DEBUG_0_REG_START 0x20000800 |
| #define BCHP_HEVD_OL_CPU_DEBUG_0_REG_END 0x20000ffc |
| #define BCHP_HEVD_OL_SINT_0_REG_START 0x20001000 |
| #define BCHP_HEVD_OL_SINT_0_REG_END 0x20001028 |
| #define BCHP_HEVD_OL_LDST_0_REG_START 0x20008000 |
| #define BCHP_HEVD_OL_LDST_0_REG_END 0x2000fffc |
| #define BCHP_REG_CABAC2BINS_0_REG_START 0x20010b00 |
| #define BCHP_REG_CABAC2BINS_0_REG_END 0x20010bfc |
| #define BCHP_REG_CABAC2BINS2_0_REG_START 0x20012400 |
| #define BCHP_REG_CABAC2BINS2_0_REG_END 0x200127fc |
| #define BCHP_HEVD_CABAC_0_REG_START 0x20013000 |
| #define BCHP_HEVD_CABAC_0_REG_END 0x2001307c |
| #define BCHP_HEVD_OL_CTL_0_REG_START 0x20014000 |
| #define BCHP_HEVD_OL_CTL_0_REG_END 0x200153fc |
| #define BCHP_DECODE_MAIN_0_REG_START 0x20020100 |
| #define BCHP_DECODE_MAIN_0_REG_END 0x200201fc |
| #define BCHP_DECODE_MCOM_0_REG_START 0x20020300 |
| #define BCHP_DECODE_MCOM_0_REG_END 0x2002031c |
| #define BCHP_DECODE_SPRE_0_REG_START 0x20020320 |
| #define BCHP_DECODE_SPRE_0_REG_END 0x2002033c |
| #define BCHP_DECODE_WPRD_0_REG_START 0x20020340 |
| #define BCHP_DECODE_WPRD_0_REG_END 0x2002035c |
| #define BCHP_DECODE_DQNT_0_REG_START 0x20020400 |
| #define BCHP_DECODE_DQNT_0_REG_END 0x2002045c |
| #define BCHP_DECODE_DQNT_8X8_0_REG_START 0x20020500 |
| #define BCHP_DECODE_DQNT_8X8_0_REG_END 0x2002057c |
| #define BCHP_DECODE_VP8_XFRM_0_REG_START 0x20020600 |
| #define BCHP_DECODE_VP8_XFRM_0_REG_END 0x2002060c |
| #define BCHP_DECODE_VP6_DCP_0_REG_START 0x20020620 |
| #define BCHP_DECODE_VP6_DCP_0_REG_END 0x2002062c |
| #define BCHP_DECODE_XFRM_0_REG_START 0x20020700 |
| #define BCHP_DECODE_XFRM_0_REG_END 0x2002071c |
| #define BCHP_DECODE_DBLK_0_REG_START 0x20020720 |
| #define BCHP_DECODE_DBLK_0_REG_END 0x2002073c |
| #define BCHP_DECODE_MB_0_REG_START 0x20020740 |
| #define BCHP_DECODE_MB_0_REG_END 0x2002075c |
| #define BCHP_DECODE_SINT_0_REG_START 0x20020c00 |
| #define BCHP_DECODE_SINT_0_REG_END 0x20020dfc |
| #define BCHP_DECODE_WPTBL_0_REG_START 0x20023000 |
| #define BCHP_DECODE_WPTBL_0_REG_END 0x200231fc |
| #define BCHP_HEVD_BE_GLOBAL_0_REG_START 0x20024000 |
| #define BCHP_HEVD_BE_GLOBAL_0_REG_END 0x20024030 |
| #define BCHP_HEVD_IXFORM_0_REG_START 0x20024100 |
| #define BCHP_HEVD_IXFORM_0_REG_END 0x200241fc |
| #define BCHP_HEVD_MCOMP_0_REG_START 0x20024200 |
| #define BCHP_HEVD_MCOMP_0_REG_END 0x200242fc |
| #define BCHP_HEVD_SPRED_0_REG_START 0x20024300 |
| #define BCHP_HEVD_SPRED_0_REG_END 0x200243f0 |
| #define BCHP_HEVD_FILTER_0_REG_START 0x20024400 |
| #define BCHP_HEVD_FILTER_0_REG_END 0x200244fc |
| #define BCHP_HEVD_OUTPUT_0_REG_START 0x20024500 |
| #define BCHP_HEVD_OUTPUT_0_REG_END 0x200245fc |
| #define BCHP_HEVD_MARKER_0_REG_START 0x20024f00 |
| #define BCHP_HEVD_MARKER_0_REG_END 0x20024f7c |
| #define BCHP_HEVD_FE_CTRL_0_REG_START 0x20025000 |
| #define BCHP_HEVD_FE_CTRL_0_REG_END 0x2002507c |
| #define BCHP_HEVD_STRM_IN_0_REG_START 0x20025100 |
| #define BCHP_HEVD_STRM_IN_0_REG_END 0x20025118 |
| #define BCHP_HEVD_CMDBUS_XMIT_0_REG_START 0x20025200 |
| #define BCHP_HEVD_CMDBUS_XMIT_0_REG_END 0x20025230 |
| #define BCHP_HEVD_VECGEN_0_REG_START 0x20025400 |
| #define BCHP_HEVD_VECGEN_0_REG_END 0x2002569c |
| #define BCHP_DCD_PIPE_CTL_0_REG_START 0x20026000 |
| #define BCHP_DCD_PIPE_CTL_0_REG_END 0x20026404 |
| #define BCHP_HEVD_PCACHE_0_REG_START 0x20026800 |
| #define BCHP_HEVD_PCACHE_0_REG_END 0x20026838 |
| #define BCHP_HEVD_PFRI_0_REG_START 0x20026a00 |
| #define BCHP_HEVD_PFRI_0_REG_END 0x20026b58 |
| #define BCHP_RVC_0_REG_START 0x20026c00 |
| #define BCHP_RVC_0_REG_END 0x20026c20 |
| #define BCHP_HEVD_IL_CPU_REGS_0_REG_START 0x20030000 |
| #define BCHP_HEVD_IL_CPU_REGS_0_REG_END 0x20030108 |
| #define BCHP_HEVD_IL_CPU_DMA_0_REG_START 0x20030400 |
| #define BCHP_HEVD_IL_CPU_DMA_0_REG_END 0x20030440 |
| #define BCHP_HEVD_IL_CPU_DEBUG_0_REG_START 0x20030800 |
| #define BCHP_HEVD_IL_CPU_DEBUG_0_REG_END 0x20030ffc |
| #define BCHP_HEVD_IL_SLICE_DMA_0_REG_START 0x20031000 |
| #define BCHP_HEVD_IL_SLICE_DMA_0_REG_END 0x2003100c |
| #define BCHP_HEVD_IL_LDST_0_REG_START 0x20034000 |
| #define BCHP_HEVD_IL_LDST_0_REG_END 0x20037ffc |
| #define BCHP_DECODE_MAIN_2_0_REG_START 0x20040100 |
| #define BCHP_DECODE_MAIN_2_0_REG_END 0x200401fc |
| #define BCHP_DECODE_MCOM_2_0_REG_START 0x20040300 |
| #define BCHP_DECODE_MCOM_2_0_REG_END 0x2004031c |
| #define BCHP_DECODE_SPRE_2_0_REG_START 0x20040320 |
| #define BCHP_DECODE_SPRE_2_0_REG_END 0x2004033c |
| #define BCHP_DECODE_WPRD_2_0_REG_START 0x20040340 |
| #define BCHP_DECODE_WPRD_2_0_REG_END 0x2004035c |
| #define BCHP_DECODE_DQNT_2_0_REG_START 0x20040400 |
| #define BCHP_DECODE_DQNT_2_0_REG_END 0x2004045c |
| #define BCHP_DECODE_DQNT_8X8_2_0_REG_START 0x20040500 |
| #define BCHP_DECODE_DQNT_8X8_2_0_REG_END 0x2004057c |
| #define BCHP_DECODE_VP8_XFRM_2_0_REG_START 0x20040600 |
| #define BCHP_DECODE_VP8_XFRM_2_0_REG_END 0x2004060c |
| #define BCHP_DECODE_VP6_DCP_2_0_REG_START 0x20040620 |
| #define BCHP_DECODE_VP6_DCP_2_0_REG_END 0x2004062c |
| #define BCHP_DECODE_XFRM_2_0_REG_START 0x20040700 |
| #define BCHP_DECODE_XFRM_2_0_REG_END 0x2004071c |
| #define BCHP_DECODE_DBLK_2_0_REG_START 0x20040720 |
| #define BCHP_DECODE_DBLK_2_0_REG_END 0x2004073c |
| #define BCHP_DECODE_MB_2_0_REG_START 0x20040740 |
| #define BCHP_DECODE_MB_2_0_REG_END 0x2004075c |
| #define BCHP_DECODE_SINT_2_0_REG_START 0x20040c00 |
| #define BCHP_DECODE_SINT_2_0_REG_END 0x20040dfc |
| #define BCHP_DECODE_WPTBL_2_0_REG_START 0x20043000 |
| #define BCHP_DECODE_WPTBL_2_0_REG_END 0x200431fc |
| #define BCHP_HEVD_BE_GLOBAL_2_0_REG_START 0x20044000 |
| #define BCHP_HEVD_BE_GLOBAL_2_0_REG_END 0x20044030 |
| #define BCHP_HEVD_IXFORM_2_0_REG_START 0x20044100 |
| #define BCHP_HEVD_IXFORM_2_0_REG_END 0x200441fc |
| #define BCHP_HEVD_MCOMP_2_0_REG_START 0x20044200 |
| #define BCHP_HEVD_MCOMP_2_0_REG_END 0x200442fc |
| #define BCHP_HEVD_SPRED_2_0_REG_START 0x20044300 |
| #define BCHP_HEVD_SPRED_2_0_REG_END 0x200443f0 |
| #define BCHP_HEVD_FILTER_2_0_REG_START 0x20044400 |
| #define BCHP_HEVD_FILTER_2_0_REG_END 0x200444fc |
| #define BCHP_HEVD_OUTPUT_2_0_REG_START 0x20044500 |
| #define BCHP_HEVD_OUTPUT_2_0_REG_END 0x200445fc |
| #define BCHP_HEVD_MARKER_2_0_REG_START 0x20044f00 |
| #define BCHP_HEVD_MARKER_2_0_REG_END 0x20044f7c |
| #define BCHP_HEVD_FE_CTRL_2_0_REG_START 0x20045000 |
| #define BCHP_HEVD_FE_CTRL_2_0_REG_END 0x2004507c |
| #define BCHP_HEVD_STRM_IN_2_0_REG_START 0x20045100 |
| #define BCHP_HEVD_STRM_IN_2_0_REG_END 0x20045118 |
| #define BCHP_HEVD_CMDBUS_XMIT_2_0_REG_START 0x20045200 |
| #define BCHP_HEVD_CMDBUS_XMIT_2_0_REG_END 0x20045230 |
| #define BCHP_HEVD_VECGEN_2_0_REG_START 0x20045400 |
| #define BCHP_HEVD_VECGEN_2_0_REG_END 0x2004569c |
| #define BCHP_DCD_PIPE_CTL_2_0_REG_START 0x20046000 |
| #define BCHP_DCD_PIPE_CTL_2_0_REG_END 0x20046404 |
| #define BCHP_HEVD_PCACHE_2_0_REG_START 0x20046800 |
| #define BCHP_HEVD_PCACHE_2_0_REG_END 0x20046838 |
| #define BCHP_HEVD_PFRI_2_0_REG_START 0x20046a00 |
| #define BCHP_HEVD_PFRI_2_0_REG_END 0x20046b58 |
| #define BCHP_RVC_2_0_REG_START 0x20046c00 |
| #define BCHP_RVC_2_0_REG_END 0x20046c20 |
| #define BCHP_HEVD_IL_CPU_REGS_2_0_REG_START 0x20050000 |
| #define BCHP_HEVD_IL_CPU_REGS_2_0_REG_END 0x20050108 |
| #define BCHP_HEVD_IL_CPU_DMA_2_0_REG_START 0x20050400 |
| #define BCHP_HEVD_IL_CPU_DMA_2_0_REG_END 0x20050440 |
| #define BCHP_HEVD_IL_CPU_DEBUG_2_0_REG_START 0x20050800 |
| #define BCHP_HEVD_IL_CPU_DEBUG_2_0_REG_END 0x20050ffc |
| #define BCHP_HEVD_IL_SLICE_DMA_2_0_REG_START 0x20051000 |
| #define BCHP_HEVD_IL_SLICE_DMA_2_0_REG_END 0x2005100c |
| #define BCHP_HEVD_IL_LDST_2_0_REG_START 0x20054000 |
| #define BCHP_HEVD_IL_LDST_2_0_REG_END 0x20057ffc |
| #define BCHP_HVD_INTR2_0_REG_START 0x20080000 |
| #define BCHP_HVD_INTR2_0_REG_END 0x2008002c |
| #define BCHP_HVD_RGR_0_REG_START 0x20080400 |
| #define BCHP_HVD_RGR_0_REG_END 0x20080410 |
| #define BCHP_VICH_0_REG_START 0x200a0000 |
| #define BCHP_VICH_0_REG_END 0x200a008b |
| #define BCHP_SDIO_0_HOST_REG_START 0x20200000 |
| #define BCHP_SDIO_0_HOST_REG_END 0x202000fc |
| #define BCHP_SDIO_0_CFG_REG_START 0x20200100 |
| #define BCHP_SDIO_0_CFG_REG_END 0x202001fc |
| #define BCHP_SDIO_1_HOST_REG_START 0x20200200 |
| #define BCHP_SDIO_1_HOST_REG_END 0x202002fc |
| #define BCHP_SDIO_1_CFG_REG_START 0x20200300 |
| #define BCHP_SDIO_1_CFG_REG_END 0x202003fc |
| #define BCHP_SDIO_1_BOOT_REG_START 0x20200400 |
| #define BCHP_SDIO_1_BOOT_REG_END 0x2020043c |
| #define BCHP_EBI_REG_START 0x20200800 |
| #define BCHP_EBI_REG_END 0x20200bfc |
| #define BCHP_HIF_INTR2_REG_START 0x20201000 |
| #define BCHP_HIF_INTR2_REG_END 0x2020102c |
| #define BCHP_HIF_CPU_INTR1_REG_START 0x20201500 |
| #define BCHP_HIF_CPU_INTR1_REG_END 0x2020153c |
| #define BCHP_PCI_PCIE_INTR1_REG_START 0x20201600 |
| #define BCHP_PCI_PCIE_INTR1_REG_END 0x2020163c |
| #define BCHP_HIF_RGR2_REG_START 0x20201700 |
| #define BCHP_HIF_RGR2_REG_END 0x20201710 |
| #define BCHP_HIF_SPI_INTR2_REG_START 0x20201a00 |
| #define BCHP_HIF_SPI_INTR2_REG_END 0x20201a2c |
| #define BCHP_HIF_TOP_CTRL_REG_START 0x20201b00 |
| #define BCHP_HIF_TOP_CTRL_REG_END 0x20201b3c |
| #define BCHP_WEBHIF_L1_MASK_REG_START 0x20201c00 |
| #define BCHP_WEBHIF_L1_MASK_REG_END 0x20201c0c |
| #define BCHP_HIF_CPUBIUARCH_REG_START 0x20202200 |
| #define BCHP_HIF_CPUBIUARCH_REG_END 0x202023fc |
| #define BCHP_HIF_CPUBIUCTRL_REG_START 0x20202400 |
| #define BCHP_HIF_CPUBIUCTRL_REG_END 0x202027fc |
| #define BCHP_NAND_REG_START 0x20203000 |
| #define BCHP_NAND_REG_END 0x202037fc |
| #define BCHP_FLASH_DMA_REG_START 0x20203800 |
| #define BCHP_FLASH_DMA_REG_END 0x20203828 |
| #define BCHP_BSPI_REG_START 0x20203a00 |
| #define BCHP_BSPI_REG_END 0x20203a4c |
| #define BCHP_BSPI_RAF_REG_START 0x20203b00 |
| #define BCHP_BSPI_RAF_REG_END 0x20203b20 |
| #define BCHP_HIF_MSPI_REG_START 0x20203c00 |
| #define BCHP_HIF_MSPI_REG_END 0x20203d84 |
| #define BCHP_HIF_CONTINUATION_SECURE_TM_REG_START 0x20203f00 |
| #define BCHP_HIF_CONTINUATION_SECURE_TM_REG_END 0x20203f04 |
| #define BCHP_IPI0_INTR2_REG_START 0x20204000 |
| #define BCHP_IPI0_INTR2_REG_END 0x2020402c |
| #define BCHP_IPI1_INTR2_REG_START 0x20204100 |
| #define BCHP_IPI1_INTR2_REG_END 0x2020412c |
| #define BCHP_IPI2_INTR2_REG_START 0x20204200 |
| #define BCHP_IPI2_INTR2_REG_END 0x2020422c |
| #define BCHP_IPI3_INTR2_REG_START 0x20204300 |
| #define BCHP_IPI3_INTR2_REG_END 0x2020432c |
| #define BCHP_BOOTSRAM_TM_REG_START 0x20220000 |
| #define BCHP_BOOTSRAM_TM_REG_END 0x2023fffc |
| #define BCHP_ITCH0_REG_START 0x20240000 |
| #define BCHP_ITCH0_REG_END 0x20240000 |
| #define BCHP_HIF_SECURE_CTRL_REG_START 0x20240400 |
| #define BCHP_HIF_SECURE_CTRL_REG_END 0x20240400 |
| #define BCHP_HIF_SECURE_BSPI_REG_START 0x20240500 |
| #define BCHP_HIF_SECURE_BSPI_REG_END 0x20240500 |
| #define BCHP_HIF_SECURE_LR_SPI_REG_START 0x20240600 |
| #define BCHP_HIF_SECURE_LR_SPI_REG_END 0x20240600 |
| #define BCHP_NAND_SECURE_REG_START 0x20240800 |
| #define BCHP_NAND_SECURE_REG_END 0x20240800 |
| #define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_START 0x20240c00 |
| #define BCHP_HIF_SECURE_INDIRECT_MSPI_PIPE_REG_END 0x20240c00 |
| #define BCHP_HIF_CPUBIUARCH_SECURE_REG_START 0x20240e00 |
| #define BCHP_HIF_CPUBIUARCH_SECURE_REG_END 0x20240ffc |
| #define BCHP_HIF_CONTINUATION_SECURE_REG_START 0x20241000 |
| #define BCHP_HIF_CONTINUATION_SECURE_REG_END 0x20241004 |
| #define BCHP_ITCH1_REG_START 0x20242000 |
| #define BCHP_ITCH1_REG_END 0x20242000 |
| #define BCHP_BOOTSRAM_SECURE_REG_START 0x20260000 |
| #define BCHP_BOOTSRAM_SECURE_REG_END 0x2027fffc |
| #define BCHP_SCPU_LOCALRAM_REG_START 0x20300000 |
| #define BCHP_SCPU_LOCALRAM_REG_END 0x2030fffc |
| #define BCHP_SCPU_GLOBALRAM_REG_START 0x20310000 |
| #define BCHP_SCPU_GLOBALRAM_REG_END 0x203103fc |
| #define BCHP_SCPU_MISB_BRIDGE_REG_START 0x20310400 |
| #define BCHP_SCPU_MISB_BRIDGE_REG_END 0x20310450 |
| #define BCHP_SCPU_RGR_BRIDGE_REG_START 0x20310460 |
| #define BCHP_SCPU_RGR_BRIDGE_REG_END 0x20310470 |
| #define BCHP_SCPU_INTR1_REG_START 0x20310480 |
| #define BCHP_SCPU_INTR1_REG_END 0x20310498 |
| #define BCHP_INTERNAL_INTR2_REG_START 0x203104c0 |
| #define BCHP_INTERNAL_INTR2_REG_END 0x203104ec |
| #define BCHP_BSP_IPI_INTR2_REG_START 0x20310500 |
| #define BCHP_BSP_IPI_INTR2_REG_END 0x2031052c |
| #define BCHP_SCPU_HW_INTR2_REG_START 0x20310540 |
| #define BCHP_SCPU_HW_INTR2_REG_END 0x2031056c |
| #define BCHP_CPU_IPI_INTR2_REG_START 0x20311000 |
| #define BCHP_CPU_IPI_INTR2_REG_END 0x2031102c |
| #define BCHP_SCPU_HOST_INTR2_REG_START 0x20311040 |
| #define BCHP_SCPU_HOST_INTR2_REG_END 0x2031106c |
| #define BCHP_SCPU_TOP_CTRL_REG_START 0x20312000 |
| #define BCHP_SCPU_TOP_CTRL_REG_END 0x20312008 |
| #define BCHP_SCPU_HDMI_CTRL_REG_START 0x20312080 |
| #define BCHP_SCPU_HDMI_CTRL_REG_END 0x20312084 |
| #define BCHP_SCPU_SEC_TIME_REG_START 0x20312100 |
| #define BCHP_SCPU_SEC_TIME_REG_END 0x20312114 |
| #define BCHP_SAGE_UART_REG_START 0x20312200 |
| #define BCHP_SAGE_UART_REG_END 0x2031221c |
| #define BCHP_SCPU_PM_REG_START 0x20312980 |
| #define BCHP_SCPU_PM_REG_END 0x20312988 |
| #define BCHP_SCPU_TIMER_REG_START 0x20312e80 |
| #define BCHP_SCPU_TIMER_REG_END 0x20312ebc |
| #define BCHP_BSP_CMDBUF_REG_START 0x2032c800 |
| #define BCHP_BSP_CMDBUF_REG_END 0x2032cffc |
| #define BCHP_BSP_GLB_CONTROL_REG_START 0x2032d000 |
| #define BCHP_BSP_GLB_CONTROL_REG_END 0x2032d0b0 |
| #define BCHP_BSP_PKL_REG_START 0x2032d300 |
| #define BCHP_BSP_PKL_REG_END 0x2032d37c |
| #define BCHP_BSP_CONTROL_INTR2_REG_START 0x2032d800 |
| #define BCHP_BSP_CONTROL_INTR2_REG_END 0x2032d82c |
| #define BCHP_BSP_VISTA_GENACC_REG_START 0x2032d900 |
| #define BCHP_BSP_VISTA_GENACC_REG_END 0x2032d9fc |
| #define BCHP_BSP_OTP_SCRATCH_REG_START 0x2032e000 |
| #define BCHP_BSP_OTP_SCRATCH_REG_END 0x2032fffc |
| #define BCHP_XPT_SECURITY_REG_START 0x20360000 |
| #define BCHP_XPT_SECURITY_REG_END 0x2037fffc |
| #define BCHP_SECTOP_GRB_REG_START 0x20380000 |
| #define BCHP_SECTOP_GRB_REG_END 0x2038000c |
| #define BCHP_XPT_SECURITY_NS_INTR2_0_REG_START 0x20380080 |
| #define BCHP_XPT_SECURITY_NS_INTR2_0_REG_END 0x203800ac |
| #define BCHP_XPT_SECURITY_NS_INTR2_1_REG_START 0x20380100 |
| #define BCHP_XPT_SECURITY_NS_INTR2_1_REG_END 0x2038012c |
| #define BCHP_XPT_SECURITY_NS_INTR2_2_REG_START 0x20380180 |
| #define BCHP_XPT_SECURITY_NS_INTR2_2_REG_END 0x203801ac |
| #define BCHP_XPT_SECURITY_NS_REG_START 0x20380200 |
| #define BCHP_XPT_SECURITY_NS_REG_END 0x203802c8 |
| #define BCHP_S_MEMC_0_REG_START 0x203bc000 |
| #define BCHP_S_MEMC_0_REG_END 0x203bc784 |
| #define BCHP_SUN_GISB_ARB_REG_START 0x20400000 |
| #define BCHP_SUN_GISB_ARB_REG_END 0x204007fc |
| #define BCHP_SUN_GR_REG_START 0x20401000 |
| #define BCHP_SUN_GR_REG_END 0x2040100c |
| #define BCHP_SSP_RG_REG_START 0x20401200 |
| #define BCHP_SSP_RG_REG_END 0x2040120c |
| #define BCHP_SUN_RG_REG_START 0x20401400 |
| #define BCHP_SUN_RG_REG_END 0x2040140c |
| #define BCHP_SUN_L2_REG_START 0x20403000 |
| #define BCHP_SUN_L2_REG_END 0x20403044 |
| #define BCHP_SUN_TOP_CTRL_REG_START 0x20404000 |
| #define BCHP_SUN_TOP_CTRL_REG_END 0x2040477c |
| #define BCHP_BBSI_RG_REG_START 0x20405c00 |
| #define BCHP_BBSI_RG_REG_END 0x20405c0c |
| #define BCHP_MPM_TOP_GR_REG_START 0x20406000 |
| #define BCHP_MPM_TOP_GR_REG_END 0x2040600c |
| #define BCHP_PWM_REG_START 0x20408000 |
| #define BCHP_PWM_REG_END 0x20408024 |
| #define BCHP_PWMB_REG_START 0x20409000 |
| #define BCHP_PWMB_REG_END 0x20409024 |
| #define BCHP_IRB_REG_START 0x2040a000 |
| #define BCHP_IRB_REG_END 0x2040a138 |
| #define BCHP_PM_REG_START 0x2040a200 |
| #define BCHP_PM_REG_END 0x2040a208 |
| #define BCHP_BSCA_REG_START 0x2040a300 |
| #define BCHP_BSCA_REG_END 0x2040a354 |
| #define BCHP_BSCE_REG_START 0x2040a400 |
| #define BCHP_BSCE_REG_END 0x2040a454 |
| #define BCHP_GIO_REG_START 0x2040a500 |
| #define BCHP_GIO_REG_END 0x2040a57c |
| #define BCHP_UPG_MAIN_IRQ_REG_START 0x2040a600 |
| #define BCHP_UPG_MAIN_IRQ_REG_END 0x2040a61c |
| #define BCHP_UPG_BSC_IRQ_REG_START 0x2040a640 |
| #define BCHP_UPG_BSC_IRQ_REG_END 0x2040a65c |
| #define BCHP_TIMER_REG_START 0x2040a680 |
| #define BCHP_TIMER_REG_END 0x2040a6bc |
| #define BCHP_SCA_REG_START 0x2040b000 |
| #define BCHP_SCA_REG_END 0x2040b0fc |
| #define BCHP_SCB_REG_START 0x2040b100 |
| #define BCHP_SCB_REG_END 0x2040b1fc |
| #define BCHP_SCIRQ0_REG_START 0x2040b200 |
| #define BCHP_SCIRQ0_REG_END 0x2040b204 |
| #define BCHP_SCIRQ1_REG_START 0x2040b240 |
| #define BCHP_SCIRQ1_REG_END 0x2040b244 |
| #define BCHP_SCIRQ_SCPU_REG_START 0x2040b280 |
| #define BCHP_SCIRQ_SCPU_REG_END 0x2040b284 |
| #define BCHP_MCIF_REG_START 0x2040b400 |
| #define BCHP_MCIF_REG_END 0x2040b428 |
| #define BCHP_MCIF_INTR2_REG_START 0x2040b480 |
| #define BCHP_MCIF_INTR2_REG_END 0x2040b4c4 |
| #define BCHP_UARTA_REG_START 0x2040c000 |
| #define BCHP_UARTA_REG_END 0x2040c01c |
| #define BCHP_UARTA_DMA_ARB_REG_START 0x2040c080 |
| #define BCHP_UARTA_DMA_ARB_REG_END 0x2040c084 |
| #define BCHP_UARTA_DMA_RX_REG_START 0x2040c100 |
| #define BCHP_UARTA_DMA_RX_REG_END 0x2040c1a0 |
| #define BCHP_UARTA_DMA_TX_REG_START 0x2040c200 |
| #define BCHP_UARTA_DMA_TX_REG_END 0x2040c238 |
| #define BCHP_UARTA_DMA_INTR2_REG_START 0x2040c300 |
| #define BCHP_UARTA_DMA_INTR2_REG_END 0x2040c32c |
| #define BCHP_UARTB_REG_START 0x2040d000 |
| #define BCHP_UARTB_REG_END 0x2040d01c |
| #define BCHP_UARTB_DMA_ARB_REG_START 0x2040d080 |
| #define BCHP_UARTB_DMA_ARB_REG_END 0x2040d084 |
| #define BCHP_UARTB_DMA_RX_REG_START 0x2040d100 |
| #define BCHP_UARTB_DMA_RX_REG_END 0x2040d1a0 |
| #define BCHP_UARTB_DMA_TX_REG_START 0x2040d200 |
| #define BCHP_UARTB_DMA_TX_REG_END 0x2040d238 |
| #define BCHP_UARTB_DMA_INTR2_REG_START 0x2040d300 |
| #define BCHP_UARTB_DMA_INTR2_REG_END 0x2040d32c |
| #define BCHP_UARTC_REG_START 0x2040e000 |
| #define BCHP_UARTC_REG_END 0x2040e01c |
| #define BCHP_UARTC_DMA_ARB_REG_START 0x2040e080 |
| #define BCHP_UARTC_DMA_ARB_REG_END 0x2040e084 |
| #define BCHP_UARTC_DMA_RX_REG_START 0x2040e100 |
| #define BCHP_UARTC_DMA_RX_REG_END 0x2040e1a0 |
| #define BCHP_UARTC_DMA_TX_REG_START 0x2040e200 |
| #define BCHP_UARTC_DMA_TX_REG_END 0x2040e238 |
| #define BCHP_UARTC_DMA_INTR2_REG_START 0x2040e300 |
| #define BCHP_UARTC_DMA_INTR2_REG_END 0x2040e32c |
| #define BCHP_DMA_SHARE_REG_START 0x2040f000 |
| #define BCHP_DMA_SHARE_REG_END 0x2040f004 |
| #define BCHP_AON_CTRL_REG_START 0x20410000 |
| #define BCHP_AON_CTRL_REG_END 0x204105fc |
| #define BCHP_AON_L2_REG_START 0x20410600 |
| #define BCHP_AON_L2_REG_END 0x2041062c |
| #define BCHP_AON_PM_L2_REG_START 0x20410640 |
| #define BCHP_AON_PM_L2_REG_END 0x2041066c |
| #define BCHP_AON_PIN_CTRL_REG_START 0x20410700 |
| #define BCHP_AON_PIN_CTRL_REG_END 0x20410720 |
| #define BCHP_AON_HDMI_TX_REG_START 0x20410800 |
| #define BCHP_AON_HDMI_TX_REG_END 0x204108ac |
| #define BCHP_AON_HDMI_RX_REG_START 0x20411200 |
| #define BCHP_AON_HDMI_RX_REG_END 0x204112d4 |
| #define BCHP_CNTControlBase_REG_START 0x20412000 |
| #define BCHP_CNTControlBase_REG_END 0x20412ffc |
| #define BCHP_CNTReadBase_REG_START 0x20414000 |
| #define BCHP_CNTReadBase_REG_END 0x20414ffc |
| #define BCHP_MSPI_REG_START 0x20416000 |
| #define BCHP_MSPI_REG_END 0x2041617c |
| #define BCHP_LDK_REG_START 0x20417000 |
| #define BCHP_LDK_REG_END 0x2041703c |
| #define BCHP_PM_AON_REG_START 0x20417080 |
| #define BCHP_PM_AON_REG_END 0x20417088 |
| #define BCHP_ICAP_REG_START 0x204170c0 |
| #define BCHP_ICAP_REG_END 0x204170fc |
| #define BCHP_KBD1_REG_START 0x20417100 |
| #define BCHP_KBD1_REG_END 0x2041713c |
| #define BCHP_KBD2_REG_START 0x20417180 |
| #define BCHP_KBD2_REG_END 0x204171bc |
| #define BCHP_KBD3_REG_START 0x20417200 |
| #define BCHP_KBD3_REG_END 0x2041723c |
| #define BCHP_BSCB_REG_START 0x20417280 |
| #define BCHP_BSCB_REG_END 0x204172d4 |
| #define BCHP_BSCC_REG_START 0x20417300 |
| #define BCHP_BSCC_REG_END 0x20417354 |
| #define BCHP_BSCD_REG_START 0x20417380 |
| #define BCHP_BSCD_REG_END 0x204173d4 |
| #define BCHP_UPG_MAIN_AON_IRQ_REG_START 0x20417400 |
| #define BCHP_UPG_MAIN_AON_IRQ_REG_END 0x2041741c |
| #define BCHP_UPG_BSC_AON_IRQ_REG_START 0x20417440 |
| #define BCHP_UPG_BSC_AON_IRQ_REG_END 0x2041745c |
| #define BCHP_UPG_SPI_AON_IRQ_REG_START 0x20417480 |
| #define BCHP_UPG_SPI_AON_IRQ_REG_END 0x2041749c |
| #define BCHP_GIO_AON_REG_START 0x204174c0 |
| #define BCHP_GIO_AON_REG_END 0x204174fc |
| #define BCHP_UPG_AUX_AON_INTR2_REG_START 0x20417600 |
| #define BCHP_UPG_AUX_AON_INTR2_REG_END 0x2041762c |
| #define BCHP_WKTMR_REG_START 0x20417680 |
| #define BCHP_WKTMR_REG_END 0x20417690 |
| #define BCHP_BICAP_REG_START 0x204176c0 |
| #define BCHP_BICAP_REG_END 0x204176f8 |
| #define BCHP_CFGCTL_REG_START 0x2041d000 |
| #define BCHP_CFGCTL_REG_END 0x2041d010 |
| #define BCHP_ZONE0_FS_REG_START 0x2041d020 |
| #define BCHP_ZONE0_FS_REG_END 0x2041d034 |
| #define BCHP_SYS_GISB_ARB_SEC_REG_START 0x2041e000 |
| #define BCHP_SYS_GISB_ARB_SEC_REG_END 0x2041e7fc |
| #define BCHP_SYS_TOP_CTRL_SEC_REG_START 0x2041e800 |
| #define BCHP_SYS_TOP_CTRL_SEC_REG_END 0x2041e808 |
| #define BCHP_AON_CTRL_SECURE_REG_START 0x2041e900 |
| #define BCHP_AON_CTRL_SECURE_REG_END 0x2041e97c |
| #define BCHP_HIF_CONTINUATION_REG_START 0x20452000 |
| #define BCHP_HIF_CONTINUATION_REG_END 0x204520fc |
| #define BCHP_WEBHIF_CONTINUATION_REG_START 0x20453000 |
| #define BCHP_WEBHIF_CONTINUATION_REG_END 0x20453014 |
| #define BCHP_WEBHIF_RGR1_REG_START 0x20454000 |
| #define BCHP_WEBHIF_RGR1_REG_END 0x20454010 |
| #define BCHP_WEBHIF_INTR2_REG_START 0x20454100 |
| #define BCHP_WEBHIF_INTR2_REG_END 0x2045412c |
| #define BCHP_WEBHIF_CPU_INTR1_REG_START 0x20454600 |
| #define BCHP_WEBHIF_CPU_INTR1_REG_END 0x2045463c |
| #define BCHP_WEBHIF_SCRATCH_REG_START 0x20454800 |
| #define BCHP_WEBHIF_SCRATCH_REG_END 0x2045481c |
| #define BCHP_WEBHIF_TIMER_REG_START 0x20454900 |
| #define BCHP_WEBHIF_TIMER_REG_END 0x2045493c |
| #define BCHP_WEBHIF_TOP_CTRL_REG_START 0x20454a00 |
| #define BCHP_WEBHIF_TOP_CTRL_REG_END 0x20454a08 |
| #define BCHP_WEBHIF_IPI0_INTR2_REG_START 0x20455000 |
| #define BCHP_WEBHIF_IPI0_INTR2_REG_END 0x2045502c |
| #define BCHP_WEBHIF_IPI1_INTR2_REG_START 0x20455100 |
| #define BCHP_WEBHIF_IPI1_INTR2_REG_END 0x2045512c |
| #define BCHP_WEBHIF_STB_IPI0_INTR2_REG_START 0x20456000 |
| #define BCHP_WEBHIF_STB_IPI0_INTR2_REG_END 0x2045602c |
| #define BCHP_WEBHIF_STB_IPI1_INTR2_REG_START 0x20456100 |
| #define BCHP_WEBHIF_STB_IPI1_INTR2_REG_END 0x2045612c |
| #define BCHP_PCIE_0_RC_CFG_TYPE1_REG_START 0x20460000 |
| #define BCHP_PCIE_0_RC_CFG_TYPE1_REG_END 0x2046003c |
| #define BCHP_PCIE_0_RC_CFG_PM_REG_START 0x20460048 |
| #define BCHP_PCIE_0_RC_CFG_PM_REG_END 0x2046004c |
| #define BCHP_PCIE_0_RC_CFG_PCIE_REG_START 0x204600ac |
| #define BCHP_PCIE_0_RC_CFG_PCIE_REG_END 0x204600e4 |
| #define BCHP_PCIE_0_RC_CFG_AER_REG_START 0x20460100 |
| #define BCHP_PCIE_0_RC_CFG_AER_REG_END 0x20460134 |
| #define BCHP_PCIE_0_RC_CFG_VENDOR_REG_START 0x20460180 |
| #define BCHP_PCIE_0_RC_CFG_VENDOR_REG_END 0x204601a4 |
| #define BCHP_PCIE_0_RC_CFG_L1SUB_REG_START 0x20460240 |
| #define BCHP_PCIE_0_RC_CFG_L1SUB_REG_END 0x2046024c |
| #define BCHP_PCIE_0_RC_CFG_PRIV0_REG_START 0x20460404 |
| #define BCHP_PCIE_0_RC_CFG_PRIV0_REG_END 0x20460418 |
| #define BCHP_PCIE_0_RC_CFG_PRIV1_REG_START 0x20460428 |
| #define BCHP_PCIE_0_RC_CFG_PRIV1_REG_END 0x20460630 |
| #define BCHP_PCIE_0_RC_TL_REG_START 0x20460800 |
| #define BCHP_PCIE_0_RC_TL_REG_END 0x20460a74 |
| #define BCHP_PCIE_0_RC_DL_REG_START 0x20461000 |
| #define BCHP_PCIE_0_RC_DL_REG_END 0x20461424 |
| #define BCHP_PCIE_0_RC_PL_REG_START 0x20461800 |
| #define BCHP_PCIE_0_RC_PL_REG_END 0x20461ffc |
| #define BCHP_PCIE_0_EP_CFG_TYPE0_REG_START 0x20462000 |
| #define BCHP_PCIE_0_EP_CFG_TYPE0_REG_END 0x2046203c |
| #define BCHP_PCIE_0_EP_CFG_PM_REG_START 0x20462048 |
| #define BCHP_PCIE_0_EP_CFG_PM_REG_END 0x2046204c |
| #define BCHP_PCIE_0_EP_CFG_VPD_REG_START 0x20462050 |
| #define BCHP_PCIE_0_EP_CFG_VPD_REG_END 0x20462054 |
| #define BCHP_PCIE_0_EP_CFG_MSI_REG_START 0x20462058 |
| #define BCHP_PCIE_0_EP_CFG_MSI_REG_END 0x20462064 |
| #define BCHP_PCIE_0_EP_CFG_MSIX_REG_START 0x204620a0 |
| #define BCHP_PCIE_0_EP_CFG_MSIX_REG_END 0x204620a8 |
| #define BCHP_PCIE_0_EP_CFG_PCIE_REG_START 0x204620ac |
| #define BCHP_PCIE_0_EP_CFG_PCIE_REG_END 0x204620e4 |
| #define BCHP_PCIE_0_EP_CFG_AER_REG_START 0x20462100 |
| #define BCHP_PCIE_0_EP_CFG_AER_REG_END 0x20462134 |
| #define BCHP_PCIE_0_EP_CFG_DEV_REG_START 0x2046213c |
| #define BCHP_PCIE_0_EP_CFG_DEV_REG_END 0x20462144 |
| #define BCHP_PCIE_0_EP_CFG_PB_REG_START 0x20462150 |
| #define BCHP_PCIE_0_EP_CFG_PB_REG_END 0x2046215c |
| #define BCHP_PCIE_0_EP_CFG_VC_REG_START 0x20462160 |
| #define BCHP_PCIE_0_EP_CFG_VC_REG_END 0x20462178 |
| #define BCHP_PCIE_0_EP_CFG_VENDOR_REG_START 0x20462180 |
| #define BCHP_PCIE_0_EP_CFG_VENDOR_REG_END 0x204621a4 |
| #define BCHP_PCIE_0_EP_CFG_LTR_REG_START 0x204621b0 |
| #define BCHP_PCIE_0_EP_CFG_LTR_REG_END 0x204621b4 |
| #define BCHP_PCIE_0_EP_CFG_L1SUB_REG_START 0x20462240 |
| #define BCHP_PCIE_0_EP_CFG_L1SUB_REG_END 0x2046224c |
| #define BCHP_PCIE_0_EP_CFG_PRIV0_REG_START 0x20462404 |
| #define BCHP_PCIE_0_EP_CFG_PRIV0_REG_END 0x20462418 |
| #define BCHP_PCIE_0_EP_CFG_PRIV1_REG_START 0x20462428 |
| #define BCHP_PCIE_0_EP_CFG_PRIV1_REG_END 0x20462630 |
| #define BCHP_PCIE_0_EP_TL_REG_START 0x20462800 |
| #define BCHP_PCIE_0_EP_TL_REG_END 0x20462a74 |
| #define BCHP_PCIE_0_EP_DL_REG_START 0x20463000 |
| #define BCHP_PCIE_0_EP_DL_REG_END 0x20463424 |
| #define BCHP_PCIE_0_EP_PL_REG_START 0x20463800 |
| #define BCHP_PCIE_0_EP_PL_REG_END 0x20463ffc |
| #define BCHP_PCIE_0_MISC_REG_START 0x20464000 |
| #define BCHP_PCIE_0_MISC_REG_END 0x204640d0 |
| #define BCHP_PCIE_0_MISC_PERST_REG_START 0x20464100 |
| #define BCHP_PCIE_0_MISC_PERST_REG_END 0x20464104 |
| #define BCHP_PCIE_0_MISC_HARD_REG_START 0x20464200 |
| #define BCHP_PCIE_0_MISC_HARD_REG_END 0x20464204 |
| #define BCHP_PCIE_0_INTR2_REG_START 0x20464300 |
| #define BCHP_PCIE_0_INTR2_REG_END 0x2046432c |
| #define BCHP_PCIE_0_DMA_REG_START 0x20464400 |
| #define BCHP_PCIE_0_DMA_REG_END 0x2046446c |
| #define BCHP_PCIE_0_MSI_INTR2_REG_START 0x20464500 |
| #define BCHP_PCIE_0_MSI_INTR2_REG_END 0x2046452c |
| #define BCHP_PCIE_0_EXT_CFG_REG_START 0x20468000 |
| #define BCHP_PCIE_0_EXT_CFG_REG_END 0x20469008 |
| #define BCHP_PCIE_0_RGR1_REG_START 0x20469200 |
| #define BCHP_PCIE_0_RGR1_REG_END 0x20469210 |
| #define BCHP_PCIE_0_RG_REG_START 0x20469300 |
| #define BCHP_PCIE_0_RG_REG_END 0x2046930c |
| #define BCHP_GENET_0_SYS_REG_START 0x20480000 |
| #define BCHP_GENET_0_SYS_REG_END 0x2048002c |
| #define BCHP_GENET_0_GR_BRIDGE_REG_START 0x20480040 |
| #define BCHP_GENET_0_GR_BRIDGE_REG_END 0x2048004c |
| #define BCHP_GENET_0_EXT_REG_START 0x20480080 |
| #define BCHP_GENET_0_EXT_REG_END 0x204800d8 |
| #define BCHP_GENET_0_INTRL2_0_REG_START 0x20480200 |
| #define BCHP_GENET_0_INTRL2_0_REG_END 0x2048022c |
| #define BCHP_GENET_0_INTRL2_1_REG_START 0x20480240 |
| #define BCHP_GENET_0_INTRL2_1_REG_END 0x2048026c |
| #define BCHP_GENET_0_RBUF_REG_START 0x20480300 |
| #define BCHP_GENET_0_RBUF_REG_END 0x204803b4 |
| #define BCHP_GENET_0_TBUF_REG_START 0x20480600 |
| #define BCHP_GENET_0_TBUF_REG_END 0x20480628 |
| #define BCHP_GENET_0_UMAC_REG_START 0x20480800 |
| #define BCHP_GENET_0_UMAC_REG_END 0x20480ed8 |
| #define BCHP_GENET_0_RDMA_REG_START 0x20482000 |
| #define BCHP_GENET_0_RDMA_REG_END 0x204830d4 |
| #define BCHP_GENET_0_TDMA_REG_START 0x20484000 |
| #define BCHP_GENET_0_TDMA_REG_END 0x20485084 |
| #define BCHP_GENET_0_HFB_REG_START 0x20488000 |
| #define BCHP_GENET_0_HFB_REG_END 0x2048fc48 |
| #define BCHP_GENET_1_SYS_REG_START 0x204a0000 |
| #define BCHP_GENET_1_SYS_REG_END 0x204a002c |
| #define BCHP_GENET_1_GR_BRIDGE_REG_START 0x204a0040 |
| #define BCHP_GENET_1_GR_BRIDGE_REG_END 0x204a004c |
| #define BCHP_GENET_1_EXT_REG_START 0x204a0080 |
| #define BCHP_GENET_1_EXT_REG_END 0x204a00d8 |
| #define BCHP_GENET_1_INTRL2_0_REG_START 0x204a0200 |
| #define BCHP_GENET_1_INTRL2_0_REG_END 0x204a022c |
| #define BCHP_GENET_1_INTRL2_1_REG_START 0x204a0240 |
| #define BCHP_GENET_1_INTRL2_1_REG_END 0x204a026c |
| #define BCHP_GENET_1_RBUF_REG_START 0x204a0300 |
| #define BCHP_GENET_1_RBUF_REG_END 0x204a03b4 |
| #define BCHP_GENET_1_TBUF_REG_START 0x204a0600 |
| #define BCHP_GENET_1_TBUF_REG_END 0x204a0628 |
| #define BCHP_GENET_1_UMAC_REG_START 0x204a0800 |
| #define BCHP_GENET_1_UMAC_REG_END 0x204a0ed8 |
| #define BCHP_GENET_1_RDMA_REG_START 0x204a2000 |
| #define BCHP_GENET_1_RDMA_REG_END 0x204a30d4 |
| #define BCHP_GENET_1_TDMA_REG_START 0x204a4000 |
| #define BCHP_GENET_1_TDMA_REG_END 0x204a5084 |
| #define BCHP_GENET_1_HFB_REG_START 0x204a8000 |
| #define BCHP_GENET_1_HFB_REG_END 0x204afc48 |
| #define BCHP_AVS_CPU_PROG_MEM_REG_START 0x204c0000 |
| #define BCHP_AVS_CPU_PROG_MEM_REG_END 0x204c39fc |
| #define BCHP_AVS_CPU_DATA_MEM_REG_START 0x204c4000 |
| #define BCHP_AVS_CPU_DATA_MEM_REG_END 0x204c4e7c |
| #define BCHP_AVS_CPU_CORE_REGS_REG_START 0x204c8000 |
| #define BCHP_AVS_CPU_CORE_REGS_REG_END 0x204c80fc |
| #define BCHP_AVS_CPU_AUX_REGS_REG_START 0x204ca000 |
| #define BCHP_AVS_CPU_AUX_REGS_REG_END 0x204caa08 |
| #define BCHP_AVS_UART_REG_START 0x204d0000 |
| #define BCHP_AVS_UART_REG_END 0x204d0ffc |
| #define BCHP_AVS_CPU_L2_REG_START 0x204d1100 |
| #define BCHP_AVS_CPU_L2_REG_END 0x204d112c |
| #define BCHP_AVS_HOST_L2_REG_START 0x204d1200 |
| #define BCHP_AVS_HOST_L2_REG_END 0x204d1244 |
| #define BCHP_AVS_CPU_CTRL_REG_START 0x204d1300 |
| #define BCHP_AVS_CPU_CTRL_REG_END 0x204d135c |
| #define BCHP_AVS_BSTI_REG_START 0x204d1400 |
| #define BCHP_AVS_BSTI_REG_END 0x204d1404 |
| #define BCHP_AVS_TMON_REG_START 0x204d1500 |
| #define BCHP_AVS_TMON_REG_END 0x204d1524 |
| #define BCHP_AVS_TOP_CTRL_REG_START 0x204d1800 |
| #define BCHP_AVS_TOP_CTRL_REG_END 0x204d18ac |
| #define BCHP_AVS_HW_MNTR_REG_START 0x204d2000 |
| #define BCHP_AVS_HW_MNTR_REG_END 0x204d20c8 |
| #define BCHP_AVS_PVT_MNTR_CONFIG_REG_START 0x204d2100 |
| #define BCHP_AVS_PVT_MNTR_CONFIG_REG_END 0x204d2124 |
| #define BCHP_AVS_RO_REGISTERS_0_REG_START 0x204d2200 |
| #define BCHP_AVS_RO_REGISTERS_0_REG_END 0x204d22e0 |
| #define BCHP_AVS_RO_REGISTERS_1_REG_START 0x204d2800 |
| #define BCHP_AVS_RO_REGISTERS_1_REG_END 0x204d2810 |
| #define BCHP_AVS_ROSC_THRESHOLD_1_REG_START 0x204d2d00 |
| #define BCHP_AVS_ROSC_THRESHOLD_1_REG_END 0x204d2dfc |
| #define BCHP_AVS_ROSC_THRESHOLD_2_REG_START 0x204d2e00 |
| #define BCHP_AVS_ROSC_THRESHOLD_2_REG_END 0x204d2efc |
| #define BCHP_AVS_WDOG_REG_START 0x204d3000 |
| #define BCHP_AVS_WDOG_REG_END 0x204d3ffc |
| #define BCHP_AVS_BSC_REG_START 0x204d4000 |
| #define BCHP_AVS_BSC_REG_END 0x204d4054 |
| #define BCHP_AVS_PMB_S_000_REG_START 0x204d8000 |
| #define BCHP_AVS_PMB_S_000_REG_END 0x204d8024 |
| #define BCHP_AVS_PMB_S_001_REG_START 0x204d8040 |
| #define BCHP_AVS_PMB_S_001_REG_END 0x204d8064 |
| #define BCHP_AVS_PMB_S_002_REG_START 0x204d8080 |
| #define BCHP_AVS_PMB_S_002_REG_END 0x204d80a4 |
| #define BCHP_AVS_PMB_S_003_REG_START 0x204d80c0 |
| #define BCHP_AVS_PMB_S_003_REG_END 0x204d80e4 |
| #define BCHP_AVS_PMB_S_004_REG_START 0x204d8100 |
| #define BCHP_AVS_PMB_S_004_REG_END 0x204d8124 |
| #define BCHP_AVS_PMB_S_005_REG_START 0x204d8140 |
| #define BCHP_AVS_PMB_S_005_REG_END 0x204d8164 |
| #define BCHP_AVS_PMB_S_006_REG_START 0x204d8180 |
| #define BCHP_AVS_PMB_S_006_REG_END 0x204d81a4 |
| #define BCHP_AVS_PMB_S_007_REG_START 0x204d81c0 |
| #define BCHP_AVS_PMB_S_007_REG_END 0x204d81e4 |
| #define BCHP_AVS_PMB_S_008_REG_START 0x204d8200 |
| #define BCHP_AVS_PMB_S_008_REG_END 0x204d8224 |
| #define BCHP_AVS_PMB_S_009_REG_START 0x204d8240 |
| #define BCHP_AVS_PMB_S_009_REG_END 0x204d8264 |
| #define BCHP_AVS_PMB_S_010_REG_START 0x204d8280 |
| #define BCHP_AVS_PMB_S_010_REG_END 0x204d82a4 |
| #define BCHP_AVS_PMB_S_011_REG_START 0x204d82c0 |
| #define BCHP_AVS_PMB_S_011_REG_END 0x204d82e4 |
| #define BCHP_AVS_PMB_S_012_REG_START 0x204d8300 |
| #define BCHP_AVS_PMB_S_012_REG_END 0x204d8324 |
| #define BCHP_AVS_PMB_S_013_REG_START 0x204d8340 |
| #define BCHP_AVS_PMB_S_013_REG_END 0x204d8364 |
| #define BCHP_AVS_PMB_S_014_REG_START 0x204d8380 |
| #define BCHP_AVS_PMB_S_014_REG_END 0x204d83a4 |
| #define BCHP_AVS_PMB_S_015_REG_START 0x204d83c0 |
| #define BCHP_AVS_PMB_S_015_REG_END 0x204d83e4 |
| #define BCHP_AVS_PMB_S_016_REG_START 0x204d8400 |
| #define BCHP_AVS_PMB_S_016_REG_END 0x204d8424 |
| #define BCHP_AVS_PMB_S_017_REG_START 0x204d8440 |
| #define BCHP_AVS_PMB_S_017_REG_END 0x204d8464 |
| #define BCHP_AVS_PMB_S_018_REG_START 0x204d8480 |
| #define BCHP_AVS_PMB_S_018_REG_END 0x204d84a4 |
| #define BCHP_AVS_PMB_S_019_REG_START 0x204d84c0 |
| #define BCHP_AVS_PMB_S_019_REG_END 0x204d84e4 |
| #define BCHP_AVS_PMB_S_020_REG_START 0x204d8500 |
| #define BCHP_AVS_PMB_S_020_REG_END 0x204d8524 |
| #define BCHP_AVS_PMB_S_021_REG_START 0x204d8540 |
| #define BCHP_AVS_PMB_S_021_REG_END 0x204d8564 |
| #define BCHP_AVS_PMB_S_022_REG_START 0x204d8580 |
| #define BCHP_AVS_PMB_S_022_REG_END 0x204d85a4 |
| #define BCHP_AVS_PMB_S_023_REG_START 0x204d85c0 |
| #define BCHP_AVS_PMB_S_023_REG_END 0x204d85e4 |
| #define BCHP_AVS_PMB_S_024_REG_START 0x204d8600 |
| #define BCHP_AVS_PMB_S_024_REG_END 0x204d8624 |
| #define BCHP_AVS_PMB_S_025_REG_START 0x204d8640 |
| #define BCHP_AVS_PMB_S_025_REG_END 0x204d8664 |
| #define BCHP_AVS_PMB_S_026_REG_START 0x204d8680 |
| #define BCHP_AVS_PMB_S_026_REG_END 0x204d86a4 |
| #define BCHP_AVS_PMB_S_027_REG_START 0x204d86c0 |
| #define BCHP_AVS_PMB_S_027_REG_END 0x204d86e4 |
| #define BCHP_AVS_PMB_S_028_REG_START 0x204d8700 |
| #define BCHP_AVS_PMB_S_028_REG_END 0x204d8724 |
| #define BCHP_AVS_PMB_REGISTERS_REG_START 0x204da000 |
| #define BCHP_AVS_PMB_REGISTERS_REG_END 0x204da008 |
| #define BCHP_CLKGEN_REG_START 0x204e0000 |
| #define BCHP_CLKGEN_REG_END 0x204e1018 |
| #define BCHP_VCXO_0_RM_REG_START 0x204e2800 |
| #define BCHP_VCXO_0_RM_REG_END 0x204e2838 |
| #define BCHP_VCXO_1_RM_REG_START 0x204e2880 |
| #define BCHP_VCXO_1_RM_REG_END 0x204e28b8 |
| #define BCHP_CLKGEN_RGR_REG_START 0x204e3000 |
| #define BCHP_CLKGEN_RGR_REG_END 0x204e3010 |
| #define BCHP_CLKGEN_INTR2_REG_START 0x204e4800 |
| #define BCHP_CLKGEN_INTR2_REG_END 0x204e4844 |
| #define BCHP_AVS_RANGE_BLOCKER_REG_START 0x204e5000 |
| #define BCHP_AVS_RANGE_BLOCKER_REG_END 0x204e5058 |
| #define BCHP_PROD_OTP_GRB_REG_START 0x204e6000 |
| #define BCHP_PROD_OTP_GRB_REG_END 0x204e600c |
| #define BCHP_JTAG_OTP_REG_START 0x204e6100 |
| #define BCHP_JTAG_OTP_REG_END 0x204e615c |
| #define BCHP_BVN_SEC_0_REG_START 0x204f0000 |
| #define BCHP_BVN_SEC_0_REG_END 0x204f0cfc |
| #define BCHP_BVN_SEC_1_REG_START 0x204f2000 |
| #define BCHP_BVN_SEC_1_REG_END 0x204f2cfc |
| #define BCHP_BVN_SEC_GR_REG_START 0x204f4000 |
| #define BCHP_BVN_SEC_GR_REG_END 0x204f400c |
| #define BCHP_BOOTROM_REG_START 0x20500000 |
| #define BCHP_BOOTROM_REG_END 0x20500ffc |
| #define BCHP_MFD_0_REG_START 0x20600000 |
| #define BCHP_MFD_0_REG_END 0x206001fc |
| #define BCHP_MFD_1_REG_START 0x20600400 |
| #define BCHP_MFD_1_REG_END 0x206005fc |
| #define BCHP_VFD_0_REG_START 0x20602000 |
| #define BCHP_VFD_0_REG_END 0x206021fc |
| #define BCHP_VFD_1_REG_START 0x20602200 |
| #define BCHP_VFD_1_REG_END 0x206023fc |
| #define BCHP_RDC_REG_START 0x20603000 |
| #define BCHP_RDC_REG_END 0x20603cfc |
| #define BCHP_BVNF_INTR2_0_REG_START 0x20604000 |
| #define BCHP_BVNF_INTR2_0_REG_END 0x2060402c |
| #define BCHP_BVNF_INTR2_1_REG_START 0x20604100 |
| #define BCHP_BVNF_INTR2_1_REG_END 0x2060412c |
| #define BCHP_BVNF_INTR2_3_REG_START 0x20604300 |
| #define BCHP_BVNF_INTR2_3_REG_END 0x2060432c |
| #define BCHP_BVNF_INTR2_5_REG_START 0x20604500 |
| #define BCHP_BVNF_INTR2_5_REG_END 0x2060452c |
| #define BCHP_BVNF_INTR2_6_REG_START 0x20604600 |
| #define BCHP_BVNF_INTR2_6_REG_END 0x2060462c |
| #define BCHP_BVNF_INTR2_7_REG_START 0x20604700 |
| #define BCHP_BVNF_INTR2_7_REG_END 0x2060472c |
| #define BCHP_BVNF_INTR2_9_REG_START 0x20604900 |
| #define BCHP_BVNF_INTR2_9_REG_END 0x2060492c |
| #define BCHP_BVNF_INTR2_15_REG_START 0x20604f00 |
| #define BCHP_BVNF_INTR2_15_REG_END 0x20604f2c |
| #define BCHP_BVNF_INTR2_16_REG_START 0x20605000 |
| #define BCHP_BVNF_INTR2_16_REG_END 0x2060502c |
| #define BCHP_BVNF_INTR2_18_REG_START 0x20605200 |
| #define BCHP_BVNF_INTR2_18_REG_END 0x2060522c |
| #define BCHP_FMISC_REG_START 0x20606000 |
| #define BCHP_FMISC_REG_END 0x20606020 |
| #define BCHP_SCL_0_REG_START 0x20620000 |
| #define BCHP_SCL_0_REG_END 0x206203fc |
| #define BCHP_SCL_1_REG_START 0x20620400 |
| #define BCHP_SCL_1_REG_END 0x206207fc |
| #define BCHP_VNET_F_REG_START 0x20622000 |
| #define BCHP_VNET_F_REG_END 0x206221fc |
| #define BCHP_VNET_B_REG_START 0x20622200 |
| #define BCHP_VNET_B_REG_END 0x206223fc |
| #define BCHP_MMISC_REG_START 0x20622800 |
| #define BCHP_MMISC_REG_END 0x20622828 |
| #define BCHP_LBOX_0_REG_START 0x20624000 |
| #define BCHP_LBOX_0_REG_END 0x20624070 |
| #define BCHP_XSRC_0_REG_START 0x20624800 |
| #define BCHP_XSRC_0_REG_END 0x20624bfc |
| #define BCHP_XSRC_1_REG_START 0x20624c00 |
| #define BCHP_XSRC_1_REG_END 0x20624ffc |
| #define BCHP_DNR_0_REG_START 0x20626000 |
| #define BCHP_DNR_0_REG_END 0x206260a4 |
| #define BCHP_DNR_1_REG_START 0x20626200 |
| #define BCHP_DNR_1_REG_END 0x206262a4 |
| #define BCHP_BVNM_INTR2_0_REG_START 0x20627000 |
| #define BCHP_BVNM_INTR2_0_REG_END 0x2062702c |
| #define BCHP_CAP_0_REG_START 0x20640000 |
| #define BCHP_CAP_0_REG_END 0x2064010c |
| #define BCHP_CAP_1_REG_START 0x20640200 |
| #define BCHP_CAP_1_REG_END 0x2064030c |
| #define BCHP_GFD_0_REG_START 0x20641000 |
| #define BCHP_GFD_0_REG_END 0x206418f4 |
| #define BCHP_GFD_1_REG_START 0x20642000 |
| #define BCHP_GFD_1_REG_END 0x2064222c |
| #define BCHP_CMP_0_REG_START 0x20643800 |
| #define BCHP_CMP_0_REG_END 0x20644328 |
| #define BCHP_CMP_1_REG_START 0x20644800 |
| #define BCHP_CMP_1_REG_END 0x20644e1c |
| #define BCHP_TNT_CMP_0_V0_REG_START 0x20645800 |
| #define BCHP_TNT_CMP_0_V0_REG_END 0x206458a4 |
| #define BCHP_MASK_0_REG_START 0x20645c00 |
| #define BCHP_MASK_0_REG_END 0x20645c20 |
| #define BCHP_PEP_CMP_0_V0_REG_START 0x20646400 |
| #define BCHP_PEP_CMP_0_V0_REG_END 0x20647684 |
| #define BCHP_HDR_CMP_0_REG_START 0x20648400 |
| #define BCHP_HDR_CMP_0_REG_END 0x2064aa9c |
| #define BCHP_BVNB_INTR2_REG_START 0x2064b400 |
| #define BCHP_BVNB_INTR2_REG_END 0x2064b42c |
| #define BCHP_BVNB_INTR2_1_REG_START 0x2064b500 |
| #define BCHP_BVNB_INTR2_1_REG_END 0x2064b52c |
| #define BCHP_BMISC_REG_START 0x2064b800 |
| #define BCHP_BMISC_REG_END 0x2064b81c |
| #define BCHP_DMISC_REG_START 0x20680000 |
| #define BCHP_DMISC_REG_END 0x2068001c |
| #define BCHP_MVP_TOP_0_REG_START 0x20688000 |
| #define BCHP_MVP_TOP_0_REG_END 0x20688038 |
| #define BCHP_SIOB_0_REG_START 0x20688200 |
| #define BCHP_SIOB_0_REG_END 0x206882fc |
| #define BCHP_HSCL_0_REG_START 0x20688400 |
| #define BCHP_HSCL_0_REG_END 0x206887fc |
| #define BCHP_MDI_TOP_0_REG_START 0x2068a000 |
| #define BCHP_MDI_TOP_0_REG_END 0x2068a0fc |
| #define BCHP_MDI_PPB_0_REG_START 0x2068a800 |
| #define BCHP_MDI_PPB_0_REG_END 0x2068abfc |
| #define BCHP_MDI_FCN_0_REG_START 0x2068ac00 |
| #define BCHP_MDI_FCN_0_REG_END 0x2068adfc |
| #define BCHP_MVP_TOP_1_REG_START 0x20690000 |
| #define BCHP_MVP_TOP_1_REG_END 0x20690038 |
| #define BCHP_SIOB_1_REG_START 0x20690200 |
| #define BCHP_SIOB_1_REG_END 0x206902fc |
| #define BCHP_HSCL_1_REG_START 0x20690400 |
| #define BCHP_HSCL_1_REG_END 0x206907fc |
| #define BCHP_MDI_TOP_1_REG_START 0x20692000 |
| #define BCHP_MDI_TOP_1_REG_END 0x206920fc |
| #define BCHP_MDI_PPB_1_REG_START 0x20692800 |
| #define BCHP_MDI_PPB_1_REG_END 0x20692bfc |
| #define BCHP_MDI_FCN_1_REG_START 0x20692c00 |
| #define BCHP_MDI_FCN_1_REG_END 0x20692dfc |
| #define BCHP_MISC_REG_START 0x206e0000 |
| #define BCHP_MISC_REG_END 0x206e0078 |
| #define BCHP_IT_0_REG_START 0x206e1000 |
| #define BCHP_IT_0_REG_END 0x206e17fc |
| #define BCHP_IT_1_REG_START 0x206e2000 |
| #define BCHP_IT_1_REG_END 0x206e27fc |
| #define BCHP_VF_0_REG_START 0x206e3000 |
| #define BCHP_VF_0_REG_END 0x206e3134 |
| #define BCHP_SECAM_0_REG_START 0x206e3200 |
| #define BCHP_SECAM_0_REG_END 0x206e3214 |
| #define BCHP_SM_0_REG_START 0x206e3280 |
| #define BCHP_SM_0_REG_END 0x206e32ac |
| #define BCHP_SDSRC_0_REG_START 0x206e3300 |
| #define BCHP_SDSRC_0_REG_END 0x206e330c |
| #define BCHP_CSC_0_REG_START 0x206e3380 |
| #define BCHP_CSC_0_REG_END 0x206e33b0 |
| #define BCHP_RM_0_REG_START 0x206e3400 |
| #define BCHP_RM_0_REG_END 0x206e3438 |
| #define BCHP_RM_1_REG_START 0x206e3440 |
| #define BCHP_RM_1_REG_END 0x206e3478 |
| #define BCHP_ANA_DEBUG_0_REG_START 0x206e3500 |
| #define BCHP_ANA_DEBUG_0_REG_END 0x206e3544 |
| #define BCHP_DVI_MISC_0_REG_START 0x206e3600 |
| #define BCHP_DVI_MISC_0_REG_END 0x206e3600 |
| #define BCHP_DVI_DTG_0_REG_START 0x206e4000 |
| #define BCHP_DVI_DTG_0_REG_END 0x206e4488 |
| #define BCHP_DVI_DTG_RM_0_REG_START 0x206e4800 |
| #define BCHP_DVI_DTG_RM_0_REG_END 0x206e4838 |
| #define BCHP_DVI_CSC_0_REG_START 0x206e4900 |
| #define BCHP_DVI_CSC_0_REG_END 0x206e4940 |
| #define BCHP_DVI_FC_0_REG_START 0x206e4a00 |
| #define BCHP_DVI_FC_0_REG_END 0x206e4a04 |
| #define BCHP_DVI_DVF_0_REG_START 0x206e4b00 |
| #define BCHP_DVI_DVF_0_REG_END 0x206e4b18 |
| #define BCHP_DVI_DEBUG_0_REG_START 0x206e4c00 |
| #define BCHP_DVI_DEBUG_0_REG_END 0x206e4c44 |
| #define BCHP_ITU656_DTG_0_REG_START 0x206e5000 |
| #define BCHP_ITU656_DTG_0_REG_END 0x206e5488 |
| #define BCHP_ITU656_CSC_0_REG_START 0x206e5600 |
| #define BCHP_ITU656_CSC_0_REG_END 0x206e5630 |
| #define BCHP_ITU656_DVF_0_REG_START 0x206e5700 |
| #define BCHP_ITU656_DVF_0_REG_END 0x206e5718 |
| #define BCHP_ITU656_0_REG_START 0x206e5800 |
| #define BCHP_ITU656_0_REG_END 0x206e5820 |
| #define BCHP_VEC_CFG_REG_START 0x206e5c00 |
| #define BCHP_VEC_CFG_REG_END 0x206e5d48 |
| #define BCHP_VIDEO_ENC_INTR2_REG_START 0x206e6000 |
| #define BCHP_VIDEO_ENC_INTR2_REG_END 0x206e602c |
| #define BCHP_VIDEO_ENC_TPG_0_REG_START 0x206e6200 |
| #define BCHP_VIDEO_ENC_TPG_0_REG_END 0x206e6324 |
| #define BCHP_VIDEO_ENC_STG_0_REG_START 0x206e6400 |
| #define BCHP_VIDEO_ENC_STG_0_REG_END 0x206e645c |
| #define BCHP_VIDEO_ENC_DECIM_0_REG_START 0x206e6500 |
| #define BCHP_VIDEO_ENC_DECIM_0_REG_END 0x206e6508 |
| #define BCHP_VIDEO_ENC_BP_FIFO_0_REG_START 0x206e6600 |
| #define BCHP_VIDEO_ENC_BP_FIFO_0_REG_END 0x206e6644 |
| #define BCHP_VIDEO_ENC_BP_TPG_0_REG_START 0x206e6800 |
| #define BCHP_VIDEO_ENC_BP_TPG_0_REG_END 0x206e6928 |
| #define BCHP_VIDEO_ENC_BP_TPG_RM_0_REG_START 0x206e6a00 |
| #define BCHP_VIDEO_ENC_BP_TPG_RM_0_REG_END 0x206e6a38 |
| #define BCHP_DVP_TVG_0_REG_START 0x206e6b00 |
| #define BCHP_DVP_TVG_0_REG_END 0x206e6b88 |
| #define BCHP_VBI_ENC_REG_START 0x206e8000 |
| #define BCHP_VBI_ENC_REG_END 0x206e8074 |
| #define BCHP_CCE_0_REG_START 0x206e8400 |
| #define BCHP_CCE_0_REG_END 0x206e8458 |
| #define BCHP_WSE_0_REG_START 0x206e8500 |
| #define BCHP_WSE_0_REG_END 0x206e8514 |
| #define BCHP_CGMSAE_0_REG_START 0x206e8600 |
| #define BCHP_CGMSAE_0_REG_END 0x206e8658 |
| #define BCHP_TTE_0_REG_START 0x206e8700 |
| #define BCHP_TTE_0_REG_END 0x206e8728 |
| #define BCHP_GSE_0_REG_START 0x206e8800 |
| #define BCHP_GSE_0_REG_END 0x206e8880 |
| #define BCHP_AMOLE_0_REG_START 0x206e8900 |
| #define BCHP_AMOLE_0_REG_END 0x206e898c |
| #define BCHP_CCE_ANCIL_0_REG_START 0x206e8a00 |
| #define BCHP_CCE_ANCIL_0_REG_END 0x206e8a54 |
| #define BCHP_WSE_ANCIL_0_REG_START 0x206e8b00 |
| #define BCHP_WSE_ANCIL_0_REG_END 0x206e8b0c |
| #define BCHP_TTE_ANCIL_0_REG_START 0x206e8c00 |
| #define BCHP_TTE_ANCIL_0_REG_END 0x206e8c28 |
| #define BCHP_GSE_ANCIL_0_REG_START 0x206e8d00 |
| #define BCHP_GSE_ANCIL_0_REG_END 0x206e8d80 |
| #define BCHP_AMOLE_ANCIL_0_REG_START 0x206e8e00 |
| #define BCHP_AMOLE_ANCIL_0_REG_END 0x206e8e8c |
| #define BCHP_ANCI656_ANCIL_0_REG_START 0x206e8f00 |
| #define BCHP_ANCI656_ANCIL_0_REG_END 0x206e8f24 |
| #define BCHP_VICE2_VIP_0_0_REG_START 0x206ef000 |
| #define BCHP_VICE2_VIP_0_0_REG_END 0x206ef224 |
| #define BCHP_VICE2_VIP_TOP_REG_START 0x206ef800 |
| #define BCHP_VICE2_VIP_TOP_REG_END 0x206ef80c |
| #define BCHP_DVP_HR_REG_START 0x206f0000 |
| #define BCHP_DVP_HR_REG_END 0x206f03fc |
| #define BCHP_DVP_HR_INTR2_REG_START 0x206f0400 |
| #define BCHP_DVP_HR_INTR2_REG_END 0x206f042c |
| #define BCHP_DVP_HR_KEY_RAM_REG_START 0x206f0600 |
| #define BCHP_DVP_HR_KEY_RAM_REG_END 0x206f0614 |
| #define BCHP_HDMI_RX_FE_SHARED_REG_START 0x206f0800 |
| #define BCHP_HDMI_RX_FE_SHARED_REG_END 0x206f090c |
| #define BCHP_HDMI_RX_SHARED_REG_START 0x206f0c00 |
| #define BCHP_HDMI_RX_SHARED_REG_END 0x206f0c28 |
| #define BCHP_HDMI_RX_FE_0_REG_START 0x206f1000 |
| #define BCHP_HDMI_RX_FE_0_REG_END 0x206f11fc |
| #define BCHP_HDMI_RX_EQ_0_REG_START 0x206f1200 |
| #define BCHP_HDMI_RX_EQ_0_REG_END 0x206f13fc |
| #define BCHP_HDMI_RX_0_REG_START 0x206f2000 |
| #define BCHP_HDMI_RX_0_REG_END 0x206f27fc |
| #define BCHP_HDCP2_RX_0_REG_START 0x206f2800 |
| #define BCHP_HDCP2_RX_0_REG_END 0x206f29fc |
| #define BCHP_HDMI_RX_INTR2_0_REG_START 0x206f2a00 |
| #define BCHP_HDMI_RX_INTR2_0_REG_END 0x206f2a2c |
| #define BCHP_HDMI_RX_BANK2_INTR2_0_REG_START 0x206f2a40 |
| #define BCHP_HDMI_RX_BANK2_INTR2_0_REG_END 0x206f2a6c |
| #define BCHP_HDMI_RX_HAE_INTR2_0_REG_START 0x206f2a80 |
| #define BCHP_HDMI_RX_HAE_INTR2_0_REG_END 0x206f2aac |
| #define BCHP_HDCP2_RX_HAE_INTR2_0_REG_START 0x206f2ac0 |
| #define BCHP_HDCP2_RX_HAE_INTR2_0_REG_END 0x206f2ad4 |
| #define BCHP_HD_DVI_0_REG_START 0x206f4000 |
| #define BCHP_HD_DVI_0_REG_END 0x206f427c |
| #define BCHP_DVP_HR_TMR_REG_START 0x206f4cc0 |
| #define BCHP_DVP_HR_TMR_REG_END 0x206f4cfc |
| #define BCHP_DVP_HT_REG_START 0x206f8000 |
| #define BCHP_DVP_HT_REG_END 0x206f8114 |
| #define BCHP_HDMI_REG_START 0x206f8800 |
| #define BCHP_HDMI_REG_END 0x206f8afc |
| #define BCHP_HDMI_TX_AUTO_I2C_REG_START 0x206f8b00 |
| #define BCHP_HDMI_TX_AUTO_I2C_REG_END 0x206f8dfc |
| #define BCHP_HDMI_TX_PHY_REG_START 0x206f8e00 |
| #define BCHP_HDMI_TX_PHY_REG_END 0x206f8e7c |
| #define BCHP_HDMI_RM_REG_START 0x206f8e80 |
| #define BCHP_HDMI_RM_REG_END 0x206f8eb8 |
| #define BCHP_HDMI_TX_INTR2_REG_START 0x206f8f00 |
| #define BCHP_HDMI_TX_INTR2_REG_END 0x206f8f2c |
| #define BCHP_HDMI_TX_SCDC_INTR2_0_REG_START 0x206f8f80 |
| #define BCHP_HDMI_TX_SCDC_INTR2_0_REG_END 0x206f8fac |
| #define BCHP_HDCP2_TX_HAE_INTR2_0_REG_START 0x206f9000 |
| #define BCHP_HDCP2_TX_HAE_INTR2_0_REG_END 0x206f902c |
| #define BCHP_HDMI_TX_HAE_INTR2_0_REG_START 0x206f9080 |
| #define BCHP_HDMI_TX_HAE_INTR2_0_REG_END 0x206f90ac |
| #define BCHP_HDMI_RAM_REG_START 0x206f9100 |
| #define BCHP_HDMI_RAM_REG_END 0x206f92fc |
| #define BCHP_BVN_RGR_REG_START 0x206fe000 |
| #define BCHP_BVN_RGR_REG_END 0x206fe010 |
| #define BCHP_SID_REG_START 0x20980100 |
| #define BCHP_SID_REG_END 0x2098019c |
| #define BCHP_SID_RLE_REG_START 0x20980300 |
| #define BCHP_SID_RLE_REG_END 0x2098039c |
| #define BCHP_SID_DQ_REG_START 0x20980400 |
| #define BCHP_SID_DQ_REG_END 0x209804bc |
| #define BCHP_SID_STRM_REG_START 0x20980800 |
| #define BCHP_SID_STRM_REG_END 0x2098087c |
| #define BCHP_SID_OUTPUT_REG_START 0x20980c00 |
| #define BCHP_SID_OUTPUT_REG_END 0x20980c40 |
| #define BCHP_SID_ARC_REG_START 0x20980f00 |
| #define BCHP_SID_ARC_REG_END 0x20980f3c |
| #define BCHP_SID_ARCDMA_REG_START 0x20981800 |
| #define BCHP_SID_ARCDMA_REG_END 0x20981840 |
| #define BCHP_SID_DMARAM_REG_START 0x20981a00 |
| #define BCHP_SID_DMARAM_REG_END 0x20981bfc |
| #define BCHP_SID_PEEK_BITS_REG_START 0x20982b00 |
| #define BCHP_SID_PEEK_BITS_REG_END 0x20982b3c |
| #define BCHP_SID_EXTRACT_BITS_REG_START 0x20982b40 |
| #define BCHP_SID_EXTRACT_BITS_REG_END 0x20982b7c |
| #define BCHP_SID_HUFF_SYMB_REG_START 0x20983000 |
| #define BCHP_SID_HUFF_SYMB_REG_END 0x209837fc |
| #define BCHP_SID_HUFF_CODE_REG_START 0x20983900 |
| #define BCHP_SID_HUFF_CODE_REG_END 0x209839fc |
| #define BCHP_SID_SYMB_REG_START 0x20983a00 |
| #define BCHP_SID_SYMB_REG_END 0x20983a10 |
| #define BCHP_SID_SYMB_JPEG_REG_START 0x20983a80 |
| #define BCHP_SID_SYMB_JPEG_REG_END 0x20983a8c |
| #define BCHP_SID_BIGRAM_REG_START 0x20988000 |
| #define BCHP_SID_BIGRAM_REG_END 0x2098fffc |
| #define BCHP_SID_ARC_DBG_REG_START 0x20991000 |
| #define BCHP_SID_ARC_DBG_REG_END 0x20991010 |
| #define BCHP_SID_ARC_CORE_REG_START 0x20995000 |
| #define BCHP_SID_ARC_CORE_REG_END 0x20995014 |
| #define BCHP_SID_GR_REG_START 0x209a0000 |
| #define BCHP_SID_GR_REG_END 0x209a000c |
| #define BCHP_SID_L2_REG_START 0x209a0100 |
| #define BCHP_SID_L2_REG_END 0x209a012c |
| #define BCHP_SICH_REG_START 0x209a0200 |
| #define BCHP_SICH_REG_END 0x209a023c |
| #define BCHP_M2MC_REG_START 0x209b0000 |
| #define BCHP_M2MC_REG_END 0x209b07fc |
| #define BCHP_M2MC_L2_REG_START 0x209b1000 |
| #define BCHP_M2MC_L2_REG_END 0x209b102c |
| #define BCHP_M2MC_GR_REG_START 0x209b1800 |
| #define BCHP_M2MC_GR_REG_END 0x209b180c |
| #define BCHP_RAAGA_DSP_SEC0_REG_START 0x209b7000 |
| #define BCHP_RAAGA_DSP_SEC0_REG_END 0x209b7000 |
| #define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_START 0x20a00000 |
| #define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DONE_INTR2_REG_END 0x20a0002c |
| #define BCHP_XPT_BUS_IF_REG_START 0x20a00080 |
| #define BCHP_XPT_BUS_IF_REG_END 0x20a000fc |
| #define BCHP_XPT_XMEMIF_REG_START 0x20a00100 |
| #define BCHP_XPT_XMEMIF_REG_END 0x20a001fc |
| #define BCHP_XPT_PMU_REG_START 0x20a00200 |
| #define BCHP_XPT_PMU_REG_END 0x20a002b8 |
| #define BCHP_XPT_PMU_SCB_REG_START 0x20a00380 |
| #define BCHP_XPT_PMU_SCB_REG_END 0x20a003b8 |
| #define BCHP_XPT_GR_REG_START 0x20a00400 |
| #define BCHP_XPT_GR_REG_END 0x20a0040c |
| #define BCHP_XPT_RMX0_IO_REG_START 0x20a00800 |
| #define BCHP_XPT_RMX0_IO_REG_END 0x20a00820 |
| #define BCHP_XPT_RMX1_IO_REG_START 0x20a00900 |
| #define BCHP_XPT_RMX1_IO_REG_END 0x20a00920 |
| #define BCHP_XPT_WAKEUP_REG_START 0x20a01000 |
| #define BCHP_XPT_WAKEUP_REG_END 0x20a01fbc |
| #define BCHP_XPT_DPCR0_REG_START 0x20a02000 |
| #define BCHP_XPT_DPCR0_REG_END 0x20a02078 |
| #define BCHP_XPT_DPCR1_REG_START 0x20a02080 |
| #define BCHP_XPT_DPCR1_REG_END 0x20a020f8 |
| #define BCHP_XPT_DPCR2_REG_START 0x20a02100 |
| #define BCHP_XPT_DPCR2_REG_END 0x20a02178 |
| #define BCHP_XPT_DPCR3_REG_START 0x20a02180 |
| #define BCHP_XPT_DPCR3_REG_END 0x20a021f8 |
| #define BCHP_XPT_DPCR4_REG_START 0x20a02200 |
| #define BCHP_XPT_DPCR4_REG_END 0x20a02278 |
| #define BCHP_XPT_DPCR5_REG_START 0x20a02280 |
| #define BCHP_XPT_DPCR5_REG_END 0x20a022f8 |
| #define BCHP_XPT_DPCR_PP_REG_START 0x20a02400 |
| #define BCHP_XPT_DPCR_PP_REG_END 0x20a02404 |
| #define BCHP_XPT_PSUB_REG_START 0x20a02a00 |
| #define BCHP_XPT_PSUB_REG_END 0x20a02b88 |
| #define BCHP_XPT_MPOD_REG_START 0x20a02c00 |
| #define BCHP_XPT_MPOD_REG_END 0x20a02c20 |
| #define BCHP_XPT_RMX0_REG_START 0x20a02d00 |
| #define BCHP_XPT_RMX0_REG_END 0x20a02d10 |
| #define BCHP_XPT_RMX1_REG_START 0x20a02e00 |
| #define BCHP_XPT_RMX1_REG_END 0x20a02e10 |
| #define BCHP_XPT_RSBUFF_REG_START 0x20a04000 |
| #define BCHP_XPT_RSBUFF_REG_END 0x20a054fc |
| #define BCHP_XPT_XCBUFF_REG_START 0x20a06000 |
| #define BCHP_XPT_XCBUFF_REG_END 0x20a07e9c |
| #define BCHP_XPT_PCROFFSET_REG_START 0x20a08000 |
| #define BCHP_XPT_PCROFFSET_REG_END 0x20a0aafc |
| #define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_START 0x20a0c000 |
| #define BCHP_XPT_TSIO_CONFIG_REGISTERS_REG_END 0x20a0ea04 |
| #define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_START 0x20a0f000 |
| #define BCHP_XPT_TSIO_CALIB_REGISTERS_REG_END 0x20a0f9fc |
| #define BCHP_XPT_TSIO_INTR_L2_REG_START 0x20a0fc00 |
| #define BCHP_XPT_TSIO_INTR_L2_REG_END 0x20a0fc2c |
| #define BCHP_XPT_FULL_PID_PARSER_REG_START 0x20a10000 |
| #define BCHP_XPT_FULL_PID_PARSER_REG_END 0x20a14050 |
| #define BCHP_XPT_FE_REG_START 0x20a20000 |
| #define BCHP_XPT_FE_REG_END 0x20a257fc |
| #define BCHP_XPT_MSG_REG_START 0x20a30000 |
| #define BCHP_XPT_MSG_REG_END 0x20a3ca14 |
| #define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_START 0x20a3fb00 |
| #define BCHP_XPT_MSG_BUF_DAT_RDY_CPU_INTR_AGGREGATOR_REG_END 0x20a3fb1c |
| #define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_START 0x20a3fb20 |
| #define BCHP_XPT_MSG_BUF_OVFL_CPU_INTR_AGGREGATOR_REG_END 0x20a3fb3c |
| #define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_START 0x20a3fb40 |
| #define BCHP_XPT_MSG_BUF_DAT_RDY_PCI_INTR_AGGREGATOR_REG_END 0x20a3fb5c |
| #define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_START 0x20a3fb60 |
| #define BCHP_XPT_MSG_BUF_OVFL_PCI_INTR_AGGREGATOR_REG_END 0x20a3fb7c |
| #define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_START 0x20a3fb80 |
| #define BCHP_XPT_MSG_DAT_ERR_INTR_L2_REG_END 0x20a3fbac |
| #define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_START 0x20a3fc00 |
| #define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_00_31_L2_REG_END 0x20a3fc2c |
| #define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_START 0x20a3fc40 |
| #define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_32_63_L2_REG_END 0x20a3fc6c |
| #define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_START 0x20a3fc80 |
| #define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_64_95_L2_REG_END 0x20a3fcac |
| #define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_START 0x20a3fcc0 |
| #define BCHP_XPT_MSG_BUF_DAT_RDY_INTR_96_127_L2_REG_END 0x20a3fcec |
| #define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_START 0x20a3fe00 |
| #define BCHP_XPT_MSG_BUF_OVFL_INTR_00_31_L2_REG_END 0x20a3fe2c |
| #define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_START 0x20a3fe40 |
| #define BCHP_XPT_MSG_BUF_OVFL_INTR_32_63_L2_REG_END 0x20a3fe6c |
| #define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_START 0x20a3fe80 |
| #define BCHP_XPT_MSG_BUF_OVFL_INTR_64_95_L2_REG_END 0x20a3feac |
| #define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_START 0x20a3fec0 |
| #define BCHP_XPT_MSG_BUF_OVFL_INTR_96_127_L2_REG_END 0x20a3feec |
| #define BCHP_XPT_RAVE_REG_START 0x20a40000 |
| #define BCHP_XPT_RAVE_REG_END 0x20a49738 |
| #define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_START 0x20a4f000 |
| #define BCHP_XPT_RAVE_CPU_INTR_AGGREGATOR_REG_END 0x20a4f01c |
| #define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_START 0x20a4f020 |
| #define BCHP_XPT_RAVE_PCI_INTR_AGGREGATOR_REG_END 0x20a4f03c |
| #define BCHP_XPT_RAVE_MISC_L2_INTR_REG_START 0x20a4f040 |
| #define BCHP_XPT_RAVE_MISC_L2_INTR_REG_END 0x20a4f06c |
| #define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_START 0x20a4f080 |
| #define BCHP_XPT_RAVE_EMU_ERROR_CX00_31_L2_INTR_REG_END 0x20a4f0ac |
| #define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_START 0x20a4f100 |
| #define BCHP_XPT_RAVE_PUSI_ERROR_CX00_31_L2_INTR_REG_END 0x20a4f12c |
| #define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_START 0x20a4f180 |
| #define BCHP_XPT_RAVE_TEI_ERROR_CX00_31_L2_INTR_REG_END 0x20a4f1ac |
| #define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_START 0x20a4f200 |
| #define BCHP_XPT_RAVE_CC_ERROR_CX00_31_L2_INTR_REG_END 0x20a4f22c |
| #define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x20a4f280 |
| #define BCHP_XPT_RAVE_CDB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x20a4f2ac |
| #define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_START 0x20a4f300 |
| #define BCHP_XPT_RAVE_ITB_OVERFLOW_CX00_31_L2_INTR_REG_END 0x20a4f32c |
| #define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_START 0x20a4f380 |
| #define BCHP_XPT_RAVE_SPLICE_CX00_31_L2_INTR_REG_END 0x20a4f3ac |
| #define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_START 0x20a4f400 |
| #define BCHP_XPT_RAVE_LAST_CMD_CX00_31_L2_INTR_REG_END 0x20a4f42c |
| #define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x20a4f480 |
| #define BCHP_XPT_RAVE_CDB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x20a4f4ac |
| #define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x20a4f500 |
| #define BCHP_XPT_RAVE_CDB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x20a4f52c |
| #define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_START 0x20a4f580 |
| #define BCHP_XPT_RAVE_ITB_LOWER_THRESH_CX00_31_L2_INTR_REG_END 0x20a4f5ac |
| #define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_START 0x20a4f600 |
| #define BCHP_XPT_RAVE_ITB_UPPER_THRESH_CX00_31_L2_INTR_REG_END 0x20a4f62c |
| #define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x20a4f680 |
| #define BCHP_XPT_RAVE_CDB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x20a4f6ac |
| #define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_START 0x20a4f700 |
| #define BCHP_XPT_RAVE_ITB_MIN_DEPTH_THRESH_CX00_31_L2_INTR_REG_END 0x20a4f72c |
| #define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_START 0x20a4f780 |
| #define BCHP_XPT_RAVE_TSIO_DMA_END_CX00_31_L2_INTR_REG_END 0x20a4f7ac |
| #define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_START 0x20a4f800 |
| #define BCHP_XPT_RAVE_FW_GENERIC_1_CX00_31_L2_INTR_REG_END 0x20a4f82c |
| #define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_START 0x20a4ff80 |
| #define BCHP_XPT_RAVE_TO_SCPU_L2_INTR_0_31_REG_END 0x20a4ffac |
| #define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_START 0x20a68000 |
| #define BCHP_XPT_WDMA_PCI_INTR_AGGREGATOR_REG_END 0x20a6801c |
| #define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_START 0x20a68020 |
| #define BCHP_XPT_WDMA_CPU_INTR_AGGREGATOR_REG_END 0x20a6803c |
| #define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_START 0x20a68040 |
| #define BCHP_XPT_WDMA_SCPU_INTR_AGGREGATOR_REG_END 0x20a6805c |
| #define BCHP_XPT_WDMA_BTP_INTR_L2_REG_START 0x20a68100 |
| #define BCHP_XPT_WDMA_BTP_INTR_L2_REG_END 0x20a68144 |
| #define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_START 0x20a68200 |
| #define BCHP_XPT_WDMA_OVERFLOW_INTR_L2_REG_END 0x20a68244 |
| #define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_START 0x20a68300 |
| #define BCHP_XPT_WDMA_DESC_DONE_INTR_L2_REG_END 0x20a68344 |
| #define BCHP_XPT_WDMA_PM_INTR_L2_REG_START 0x20a68400 |
| #define BCHP_XPT_WDMA_PM_INTR_L2_REG_END 0x20a68444 |
| #define BCHP_XPT_WDMA_PM_CONTROL_REG_START 0x20a68500 |
| #define BCHP_XPT_WDMA_PM_CONTROL_REG_END 0x20a68510 |
| #define BCHP_XPT_WDMA_PM_RESULTS_REG_START 0x20a68600 |
| #define BCHP_XPT_WDMA_PM_RESULTS_REG_END 0x20a68658 |
| #define BCHP_XPT_WDMA_REGS_REG_START 0x20a69000 |
| #define BCHP_XPT_WDMA_REGS_REG_END 0x20a69068 |
| #define BCHP_XPT_WDMA_CH0_REG_START 0x20a6a000 |
| #define BCHP_XPT_WDMA_CH0_REG_END 0x20a6a0fc |
| #define BCHP_XPT_WDMA_CH1_REG_START 0x20a6a100 |
| #define BCHP_XPT_WDMA_CH1_REG_END 0x20a6a1fc |
| #define BCHP_XPT_WDMA_CH2_REG_START 0x20a6a200 |
| #define BCHP_XPT_WDMA_CH2_REG_END 0x20a6a2fc |
| #define BCHP_XPT_WDMA_CH3_REG_START 0x20a6a300 |
| #define BCHP_XPT_WDMA_CH3_REG_END 0x20a6a3fc |
| #define BCHP_XPT_WDMA_CH4_REG_START 0x20a6a400 |
| #define BCHP_XPT_WDMA_CH4_REG_END 0x20a6a4fc |
| #define BCHP_XPT_WDMA_CH5_REG_START 0x20a6a500 |
| #define BCHP_XPT_WDMA_CH5_REG_END 0x20a6a5fc |
| #define BCHP_XPT_WDMA_CH6_REG_START 0x20a6a600 |
| #define BCHP_XPT_WDMA_CH6_REG_END 0x20a6a6fc |
| #define BCHP_XPT_WDMA_CH7_REG_START 0x20a6a700 |
| #define BCHP_XPT_WDMA_CH7_REG_END 0x20a6a7fc |
| #define BCHP_XPT_WDMA_CH8_REG_START 0x20a6a800 |
| #define BCHP_XPT_WDMA_CH8_REG_END 0x20a6a8fc |
| #define BCHP_XPT_WDMA_CH9_REG_START 0x20a6a900 |
| #define BCHP_XPT_WDMA_CH9_REG_END 0x20a6a9fc |
| #define BCHP_XPT_WDMA_CH10_REG_START 0x20a6aa00 |
| #define BCHP_XPT_WDMA_CH10_REG_END 0x20a6aafc |
| #define BCHP_XPT_WDMA_CH11_REG_START 0x20a6ab00 |
| #define BCHP_XPT_WDMA_CH11_REG_END 0x20a6abfc |
| #define BCHP_XPT_WDMA_CH12_REG_START 0x20a6ac00 |
| #define BCHP_XPT_WDMA_CH12_REG_END 0x20a6acfc |
| #define BCHP_XPT_WDMA_CH13_REG_START 0x20a6ad00 |
| #define BCHP_XPT_WDMA_CH13_REG_END 0x20a6adfc |
| #define BCHP_XPT_WDMA_CH14_REG_START 0x20a6ae00 |
| #define BCHP_XPT_WDMA_CH14_REG_END 0x20a6aefc |
| #define BCHP_XPT_WDMA_CH15_REG_START 0x20a6af00 |
| #define BCHP_XPT_WDMA_CH15_REG_END 0x20a6affc |
| #define BCHP_XPT_WDMA_CH16_REG_START 0x20a6b000 |
| #define BCHP_XPT_WDMA_CH16_REG_END 0x20a6b0fc |
| #define BCHP_XPT_WDMA_CH17_REG_START 0x20a6b100 |
| #define BCHP_XPT_WDMA_CH17_REG_END 0x20a6b1fc |
| #define BCHP_XPT_WDMA_CH18_REG_START 0x20a6b200 |
| #define BCHP_XPT_WDMA_CH18_REG_END 0x20a6b2fc |
| #define BCHP_XPT_WDMA_CH19_REG_START 0x20a6b300 |
| #define BCHP_XPT_WDMA_CH19_REG_END 0x20a6b3fc |
| #define BCHP_XPT_WDMA_CH20_REG_START 0x20a6b400 |
| #define BCHP_XPT_WDMA_CH20_REG_END 0x20a6b4fc |
| #define BCHP_XPT_WDMA_CH21_REG_START 0x20a6b500 |
| #define BCHP_XPT_WDMA_CH21_REG_END 0x20a6b5fc |
| #define BCHP_XPT_WDMA_CH22_REG_START 0x20a6b600 |
| #define BCHP_XPT_WDMA_CH22_REG_END 0x20a6b6fc |
| #define BCHP_XPT_WDMA_CH23_REG_START 0x20a6b700 |
| #define BCHP_XPT_WDMA_CH23_REG_END 0x20a6b7fc |
| #define BCHP_XPT_WDMA_CH24_REG_START 0x20a6b800 |
| #define BCHP_XPT_WDMA_CH24_REG_END 0x20a6b8fc |
| #define BCHP_XPT_WDMA_CH25_REG_START 0x20a6b900 |
| #define BCHP_XPT_WDMA_CH25_REG_END 0x20a6b9fc |
| #define BCHP_XPT_WDMA_CH26_REG_START 0x20a6ba00 |
| #define BCHP_XPT_WDMA_CH26_REG_END 0x20a6bafc |
| #define BCHP_XPT_WDMA_CH27_REG_START 0x20a6bb00 |
| #define BCHP_XPT_WDMA_CH27_REG_END 0x20a6bbfc |
| #define BCHP_XPT_WDMA_CH28_REG_START 0x20a6bc00 |
| #define BCHP_XPT_WDMA_CH28_REG_END 0x20a6bcfc |
| #define BCHP_XPT_WDMA_CH29_REG_START 0x20a6bd00 |
| #define BCHP_XPT_WDMA_CH29_REG_END 0x20a6bdfc |
| #define BCHP_XPT_WDMA_CH30_REG_START 0x20a6be00 |
| #define BCHP_XPT_WDMA_CH30_REG_END 0x20a6befc |
| #define BCHP_XPT_WDMA_CH31_REG_START 0x20a6bf00 |
| #define BCHP_XPT_WDMA_CH31_REG_END 0x20a6bffc |
| #define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_START 0x20a70000 |
| #define BCHP_XPT_MCPB_CPU_INTR_AGGREGATOR_REG_END 0x20a7001c |
| #define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_START 0x20a70020 |
| #define BCHP_XPT_MCPB_PCI_INTR_AGGREGATOR_REG_END 0x20a7003c |
| #define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_START 0x20a70040 |
| #define BCHP_XPT_MCPB_DESC_DONE_INTR_L2_REG_END 0x20a7006c |
| #define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_START 0x20a70080 |
| #define BCHP_XPT_MCPB_MISC_FALSE_WAKE_INTR_L2_REG_END 0x20a700ac |
| #define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_START 0x20a700c0 |
| #define BCHP_XPT_MCPB_MISC_OOS_INTR_L2_REG_END 0x20a700ec |
| #define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_START 0x20a70100 |
| #define BCHP_XPT_MCPB_MISC_TS_PARITY_ERR_INTR_L2_REG_END 0x20a7012c |
| #define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_START 0x20a70140 |
| #define BCHP_XPT_MCPB_MISC_TEI_INTR_L2_REG_END 0x20a7016c |
| #define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_START 0x20a70180 |
| #define BCHP_XPT_MCPB_MISC_ASF_LEN_ERR_INTR_L2_REG_END 0x20a701ac |
| #define BCHP_XPT_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_START 0x20a701c0 |
| #define BCHP_XPT_MCPB_MISC_WATCHDOG_TIMEOUT_OR_ASF_FATAL_ERR_INTR_L2_REG_END 0x20a701ec |
| #define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_START 0x20a70200 |
| #define BCHP_XPT_MCPB_MISC_ASF_COMPRESSED_DATA_RECEIVED_INTR_L2_REG_END 0x20a7022c |
| #define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_START 0x20a70240 |
| #define BCHP_XPT_MCPB_MISC_ASF_PROTOCOL_ERR_INTR_L2_REG_END 0x20a7026c |
| #define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_START 0x20a70280 |
| #define BCHP_XPT_MCPB_MISC_ASF_PADDING_LEN_ERR_INTR_L2_REG_END 0x20a702ac |
| #define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_START 0x20a702c0 |
| #define BCHP_XPT_MCPB_MISC_TS_RANGE_ERR_INTR_L2_REG_END 0x20a702ec |
| #define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_START 0x20a70300 |
| #define BCHP_XPT_MCPB_MISC_PES_NEXT_TS_RANGE_ERR_INTR_L2_REG_END 0x20a7032c |
| #define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_START 0x20a70340 |
| #define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_READ_INTR_L2_REG_END 0x20a7036c |
| #define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_START 0x20a70380 |
| #define BCHP_XPT_MCPB_MISC_PAUSE_AT_DESC_END_INTR_L2_REG_END 0x20a703ac |
| #define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_START 0x20a703c0 |
| #define BCHP_XPT_MCPB_MISC_PAUSE_AFTER_GROUP_PACKETS_INTR_L2_REG_END 0x20a703ec |
| #define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_START 0x20a70400 |
| #define BCHP_XPT_MCPB_MISC_DESC_TAGID_MISMATCH_INTR_L2_REG_END 0x20a7042c |
| #define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_START 0x20a70440 |
| #define BCHP_XPT_MCPB_MISC_DATA_TAGID_MISMATCH_INTR_L2_REG_END 0x20a7046c |
| #define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_START 0x20a70480 |
| #define BCHP_XPT_MCPB_MISC_CRC_COMPARE_ERROR_INTR_L2_REG_END 0x20a704ac |
| #define BCHP_XPT_MCPB_REG_START 0x20a70800 |
| #define BCHP_XPT_MCPB_REG_END 0x20a70b9c |
| #define BCHP_XPT_MCPB_CH0_REG_START 0x20a70c00 |
| #define BCHP_XPT_MCPB_CH0_REG_END 0x20a70d5c |
| #define BCHP_XPT_MCPB_CH1_REG_START 0x20a70e00 |
| #define BCHP_XPT_MCPB_CH1_REG_END 0x20a70f5c |
| #define BCHP_XPT_MCPB_CH2_REG_START 0x20a71000 |
| #define BCHP_XPT_MCPB_CH2_REG_END 0x20a7115c |
| #define BCHP_XPT_MCPB_CH3_REG_START 0x20a71200 |
| #define BCHP_XPT_MCPB_CH3_REG_END 0x20a7135c |
| #define BCHP_XPT_MCPB_CH4_REG_START 0x20a71400 |
| #define BCHP_XPT_MCPB_CH4_REG_END 0x20a7155c |
| #define BCHP_XPT_MCPB_CH5_REG_START 0x20a71600 |
| #define BCHP_XPT_MCPB_CH5_REG_END 0x20a7175c |
| #define BCHP_XPT_MCPB_CH6_REG_START 0x20a71800 |
| #define BCHP_XPT_MCPB_CH6_REG_END 0x20a7195c |
| #define BCHP_XPT_MCPB_CH7_REG_START 0x20a71a00 |
| #define BCHP_XPT_MCPB_CH7_REG_END 0x20a71b5c |
| #define BCHP_XPT_MCPB_CH8_REG_START 0x20a71c00 |
| #define BCHP_XPT_MCPB_CH8_REG_END 0x20a71d5c |
| #define BCHP_XPT_MCPB_CH9_REG_START 0x20a71e00 |
| #define BCHP_XPT_MCPB_CH9_REG_END 0x20a71f5c |
| #define BCHP_XPT_MCPB_CH10_REG_START 0x20a72000 |
| #define BCHP_XPT_MCPB_CH10_REG_END 0x20a7215c |
| #define BCHP_XPT_MCPB_CH11_REG_START 0x20a72200 |
| #define BCHP_XPT_MCPB_CH11_REG_END 0x20a7235c |
| #define BCHP_XPT_MCPB_CH12_REG_START 0x20a72400 |
| #define BCHP_XPT_MCPB_CH12_REG_END 0x20a7255c |
| #define BCHP_XPT_MCPB_CH13_REG_START 0x20a72600 |
| #define BCHP_XPT_MCPB_CH13_REG_END 0x20a7275c |
| #define BCHP_XPT_MCPB_CH14_REG_START 0x20a72800 |
| #define BCHP_XPT_MCPB_CH14_REG_END 0x20a7295c |
| #define BCHP_XPT_MCPB_CH15_REG_START 0x20a72a00 |
| #define BCHP_XPT_MCPB_CH15_REG_END 0x20a72b5c |
| #define BCHP_XPT_MCPB_CH16_REG_START 0x20a72c00 |
| #define BCHP_XPT_MCPB_CH16_REG_END 0x20a72d5c |
| #define BCHP_XPT_MCPB_CH17_REG_START 0x20a72e00 |
| #define BCHP_XPT_MCPB_CH17_REG_END 0x20a72f5c |
| #define BCHP_XPT_MCPB_CH18_REG_START 0x20a73000 |
| #define BCHP_XPT_MCPB_CH18_REG_END 0x20a7315c |
| #define BCHP_XPT_MCPB_CH19_REG_START 0x20a73200 |
| #define BCHP_XPT_MCPB_CH19_REG_END 0x20a7335c |
| #define BCHP_XPT_MCPB_CH20_REG_START 0x20a73400 |
| #define BCHP_XPT_MCPB_CH20_REG_END 0x20a7355c |
| #define BCHP_XPT_MCPB_CH21_REG_START 0x20a73600 |
| #define BCHP_XPT_MCPB_CH21_REG_END 0x20a7375c |
| #define BCHP_XPT_MCPB_CH22_REG_START 0x20a73800 |
| #define BCHP_XPT_MCPB_CH22_REG_END 0x20a7395c |
| #define BCHP_XPT_MCPB_CH23_REG_START 0x20a73a00 |
| #define BCHP_XPT_MCPB_CH23_REG_END 0x20a73b5c |
| #define BCHP_XPT_MCPB_CH24_REG_START 0x20a73c00 |
| #define BCHP_XPT_MCPB_CH24_REG_END 0x20a73d5c |
| #define BCHP_XPT_MCPB_CH25_REG_START 0x20a73e00 |
| #define BCHP_XPT_MCPB_CH25_REG_END 0x20a73f5c |
| #define BCHP_XPT_MCPB_CH26_REG_START 0x20a74000 |
| #define BCHP_XPT_MCPB_CH26_REG_END 0x20a7415c |
| #define BCHP_XPT_MCPB_CH27_REG_START 0x20a74200 |
| #define BCHP_XPT_MCPB_CH27_REG_END 0x20a7435c |
| #define BCHP_XPT_MCPB_CH28_REG_START 0x20a74400 |
| #define BCHP_XPT_MCPB_CH28_REG_END 0x20a7455c |
| #define BCHP_XPT_MCPB_CH29_REG_START 0x20a74600 |
| #define BCHP_XPT_MCPB_CH29_REG_END 0x20a7475c |
| #define BCHP_XPT_MCPB_CH30_REG_START 0x20a74800 |
| #define BCHP_XPT_MCPB_CH30_REG_END 0x20a7495c |
| #define BCHP_XPT_MCPB_CH31_REG_START 0x20a74a00 |
| #define BCHP_XPT_MCPB_CH31_REG_END 0x20a74b5c |
| #define BCHP_XPT_XPU_REG_START 0x20a78000 |
| #define BCHP_XPT_XPU_REG_END 0x20a7c7fc |
| #define BCHP_XPT_SECURE_BUS_IF_REG_START 0x20a7f000 |
| #define BCHP_XPT_SECURE_BUS_IF_REG_END 0x20a7f000 |
| #define BCHP_USB_CAPS_REG_START 0x20b00000 |
| #define BCHP_USB_CAPS_REG_END 0x20b0002c |
| #define BCHP_USB_GR_BRIDGE_REG_START 0x20b00100 |
| #define BCHP_USB_GR_BRIDGE_REG_END 0x20b0010c |
| #define BCHP_USB_INTR2_REG_START 0x20b00180 |
| #define BCHP_USB_INTR2_REG_END 0x20b001ac |
| #define BCHP_USB_CTRL_REG_START 0x20b00200 |
| #define BCHP_USB_CTRL_REG_END 0x20b002fc |
| #define BCHP_USB_EHCI_REG_START 0x20b00300 |
| #define BCHP_USB_EHCI_REG_END 0x20b003a4 |
| #define BCHP_USB_OHCI_REG_START 0x20b00400 |
| #define BCHP_USB_OHCI_REG_END 0x20b00454 |
| #define BCHP_USB_EHCI1_REG_START 0x20b00500 |
| #define BCHP_USB_EHCI1_REG_END 0x20b005a4 |
| #define BCHP_USB_OHCI1_REG_START 0x20b00600 |
| #define BCHP_USB_OHCI1_REG_END 0x20b00654 |
| #define BCHP_USB_XHCI_REG_START 0x20b01000 |
| #define BCHP_USB_XHCI_REG_END 0x20b018c4 |
| #define BCHP_USB_XHCI_EC_REG_START 0x20b01900 |
| #define BCHP_USB_XHCI_EC_REG_END 0x20b01ffc |
| #define BCHP_USB_BDC_REG_START 0x20b02000 |
| #define BCHP_USB_BDC_REG_END 0x20b023fc |
| #define BCHP_USB_BDC_EC_REG_START 0x20b02c00 |
| #define BCHP_USB_BDC_EC_REG_END 0x20b02fc0 |
| #define BCHP_SATA_GRB_REG_START 0x20b10000 |
| #define BCHP_SATA_GRB_REG_END 0x20b1000c |
| #define BCHP_SATA_TOP_CTRL_REG_START 0x20b10040 |
| #define BCHP_SATA_TOP_CTRL_REG_END 0x20b10060 |
| #define BCHP_SATA3_INTR2_REG_START 0x20b10080 |
| #define BCHP_SATA3_INTR2_REG_END 0x20b100ac |
| #define BCHP_PORT0_SATA3_PCB_REG_START 0x20b10100 |
| #define BCHP_PORT0_SATA3_PCB_REG_END 0x20b10ffc |
| #define BCHP_SATA_AHCI_GHC_REG_START 0x20b12000 |
| #define BCHP_SATA_AHCI_GHC_REG_END 0x20b12028 |
| #define BCHP_SATA_GLOBAL_RESERVED_REG_START 0x20b1202c |
| #define BCHP_SATA_GLOBAL_RESERVED_REG_END 0x20b1209c |
| #define BCHP_SATA_PORT0_AHCI_S1_REG_START 0x20b12100 |
| #define BCHP_SATA_PORT0_AHCI_S1_REG_END 0x20b1211c |
| #define BCHP_SATA_PORT0_AHCI_S2_REG_START 0x20b12120 |
| #define BCHP_SATA_PORT0_AHCI_S2_REG_END 0x20b12134 |
| #define BCHP_SATA_PORT0_AHCI_S3_REG_START 0x20b12138 |
| #define BCHP_SATA_PORT0_AHCI_S3_REG_END 0x20b1217c |
| #define BCHP_SATA_AHCI_PCICFG_REG_START 0x20b12600 |
| #define BCHP_SATA_AHCI_PCICFG_REG_END 0x20b12664 |
| #define BCHP_SATA_PORT0_CTRL_REG_START 0x20b12700 |
| #define BCHP_SATA_PORT0_CTRL_REG_END 0x20b12730 |
| #define BCHP_SATA_PORT0_CJPAT_REG_START 0x20b12740 |
| #define BCHP_SATA_PORT0_CJPAT_REG_END 0x20b12764 |
| #define BCHP_SATA_LEG_PCICFG_REG_START 0x20b12800 |
| #define BCHP_SATA_LEG_PCICFG_REG_END 0x20b12880 |
| #define BCHP_SATA_PORT0_LEG_S1_REG_START 0x20b12900 |
| #define BCHP_SATA_PORT0_LEG_S1_REG_END 0x20b12934 |
| #define BCHP_SATA_PORT0_LEG_S2_REG_START 0x20b12940 |
| #define BCHP_SATA_PORT0_LEG_S2_REG_END 0x20b12954 |
| #define BCHP_SATA_PORT0_LEG_S3_REG_START 0x20b12958 |
| #define BCHP_SATA_PORT0_LEG_S3_REG_END 0x20b12998 |
| #define BCHP_RAAGA_DSP_RGR_REG_START 0x20c00000 |
| #define BCHP_RAAGA_DSP_RGR_REG_END 0x20c00008 |
| #define BCHP_RAAGA_DSP_MISC_REG_START 0x20c20000 |
| #define BCHP_RAAGA_DSP_MISC_REG_END 0x20c2044c |
| #define BCHP_RAAGA_DSP_TIMERS_REG_START 0x20c21000 |
| #define BCHP_RAAGA_DSP_TIMERS_REG_END 0x20c21058 |
| #define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_START 0x20c21080 |
| #define BCHP_RAAGA_DSP_PERI_DBG_CTRL_REG_END 0x20c2108c |
| #define BCHP_RAAGA_DSP_PERI_SW_REG_START 0x20c21100 |
| #define BCHP_RAAGA_DSP_PERI_SW_REG_END 0x20c21154 |
| #define BCHP_RAAGA_DSP_DMA_REG_START 0x20c21400 |
| #define BCHP_RAAGA_DSP_DMA_REG_END 0x20c216b8 |
| #define BCHP_RAAGA_DSP_ESR_SI_REG_START 0x20c22000 |
| #define BCHP_RAAGA_DSP_ESR_SI_REG_END 0x20c22014 |
| #define BCHP_RAAGA_DSP_INTH_REG_START 0x20c22200 |
| #define BCHP_RAAGA_DSP_INTH_REG_END 0x20c2222c |
| #define BCHP_RAAGA_DSP_TIMER_INT_REG_START 0x20c22400 |
| #define BCHP_RAAGA_DSP_TIMER_INT_REG_END 0x20c22414 |
| #define BCHP_RAAGA_DSP_ERROR_INT_REG_START 0x20c22600 |
| #define BCHP_RAAGA_DSP_ERROR_INT_REG_END 0x20c22614 |
| #define BCHP_RAAGA_DSP_DEBUG_INT_REG_START 0x20c22700 |
| #define BCHP_RAAGA_DSP_DEBUG_INT_REG_END 0x20c22714 |
| #define BCHP_RAAGA_DSP_FW_INTH_REG_START 0x20c22800 |
| #define BCHP_RAAGA_DSP_FW_INTH_REG_END 0x20c2282c |
| #define BCHP_RAAGA_DSP_FW_CFG_REG_START 0x20c23000 |
| #define BCHP_RAAGA_DSP_FW_CFG_REG_END 0x20c2357c |
| #define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_START 0x20c30000 |
| #define BCHP_RAAGA_DSP_MEM_SUBSYSTEM_REG_END 0x20c3bffc |
| #define BCHP_RAAGA_AX_MISC_REG_START 0x20c40000 |
| #define BCHP_RAAGA_AX_MISC_REG_END 0x20c40008 |
| #define BCHP_RAAGA_AX_INTR_AGGR_REG_START 0x20c40100 |
| #define BCHP_RAAGA_AX_INTR_AGGR_REG_END 0x20c4014c |
| #define BCHP_RAAGA_AX_RXI_ARB_REG_START 0x20c40200 |
| #define BCHP_RAAGA_AX_RXI_ARB_REG_END 0x20c40248 |
| #define BCHP_RAAGA_AX_DBLK_WATCHDOG_REG_START 0x20c40300 |
| #define BCHP_RAAGA_AX_DBLK_WATCHDOG_REG_END 0x20c40318 |
| #define BCHP_RAAGA_AX_EC_WATCHDOG_REG_START 0x20c40400 |
| #define BCHP_RAAGA_AX_EC_WATCHDOG_REG_END 0x20c40418 |
| #define BCHP_RAAGA_AX_ME_WATCHDOG_REG_START 0x20c40500 |
| #define BCHP_RAAGA_AX_ME_WATCHDOG_REG_END 0x20c40518 |
| #define BCHP_RAAGA_AX_GENAX_WATCHDOG_REG_START 0x20c40600 |
| #define BCHP_RAAGA_AX_GENAX_WATCHDOG_REG_END 0x20c40618 |
| #define BCHP_RAAGA_AX_DBLK_REG_START 0x20c41000 |
| #define BCHP_RAAGA_AX_DBLK_REG_END 0x20c411fc |
| #define BCHP_RAAGA_AX_EC_REG_START 0x20c42000 |
| #define BCHP_RAAGA_AX_EC_REG_END 0x20c42164 |
| #define BCHP_RAAGA_AX_ME_REG_START 0x20c43000 |
| #define BCHP_RAAGA_AX_ME_REG_END 0x20c43348 |
| #define BCHP_RAAGA_AX_GENAX_REG_START 0x20c44000 |
| #define BCHP_RAAGA_AX_GENAX_REG_END 0x20c44618 |
| #define BCHP_AUD_MISC_REG_START 0x20c80000 |
| #define BCHP_AUD_MISC_REG_END 0x20c80120 |
| #define BCHP_AUD_INTH_REG_START 0x20c80800 |
| #define BCHP_AUD_INTH_REG_END 0x20c8082c |
| #define BCHP_AUD_FMM_BF_CTRL_REG_START 0x20ca0000 |
| #define BCHP_AUD_FMM_BF_CTRL_REG_END 0x20ca0d3c |
| #define BCHP_AUD_FMM_BF_ESR_REG_START 0x20ca1000 |
| #define BCHP_AUD_FMM_BF_ESR_REG_END 0x20ca1074 |
| #define BCHP_AUD_FMM_SRC_CTRL0_REG_START 0x20ca2000 |
| #define BCHP_AUD_FMM_SRC_CTRL0_REG_END 0x20ca2bfc |
| #define BCHP_AUD_FMM_SRC_ESR0_REG_START 0x20ca3000 |
| #define BCHP_AUD_FMM_SRC_ESR0_REG_END 0x20ca3014 |
| #define BCHP_AUD_FMM_DP_CTRL0_REG_START 0x20ca4000 |
| #define BCHP_AUD_FMM_DP_CTRL0_REG_END 0x20ca612c |
| #define BCHP_AUD_FMM_DP_ESR0_REG_START 0x20ca7c00 |
| #define BCHP_AUD_FMM_DP_ESR0_REG_END 0x20ca7c2c |
| #define BCHP_AUD_FMM_IOP_OUT_I2S_0_REG_START 0x20cb0000 |
| #define BCHP_AUD_FMM_IOP_OUT_I2S_0_REG_END 0x20cb0034 |
| #define BCHP_AUD_FMM_IOP_OUT_I2S_1_REG_START 0x20cb0100 |
| #define BCHP_AUD_FMM_IOP_OUT_I2S_1_REG_END 0x20cb0134 |
| #define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_START 0x20cb0200 |
| #define BCHP_AUD_FMM_IOP_OUT_SPDIF_0_REG_END 0x20cb0284 |
| #define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_START 0x20cb0300 |
| #define BCHP_AUD_FMM_IOP_OUT_MAI_0_REG_END 0x20cb03b4 |
| #define BCHP_HIFIDAC_CTRL_0_REG_START 0x20cb0800 |
| #define BCHP_HIFIDAC_CTRL_0_REG_END 0x20cb09fc |
| #define BCHP_HIFIDAC_RM_0_REG_START 0x20cb0a00 |
| #define BCHP_HIFIDAC_RM_0_REG_END 0x20cb0a38 |
| #define BCHP_HIFIDAC_ESR_0_REG_START 0x20cb0b00 |
| #define BCHP_HIFIDAC_ESR_0_REG_END 0x20cb0b14 |
| #define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_START 0x20cb0c00 |
| #define BCHP_AUD_FMM_IOP_OUT_DAC_CTRL_0_REG_END 0x20cb0ca0 |
| #define BCHP_AUD_FMM_IOP_PLL_0_REG_START 0x20cb0d00 |
| #define BCHP_AUD_FMM_IOP_PLL_0_REG_END 0x20cb0d90 |
| #define BCHP_AUD_FMM_IOP_PLL_1_REG_START 0x20cb0e00 |
| #define BCHP_AUD_FMM_IOP_PLL_1_REG_END 0x20cb0e90 |
| #define BCHP_AUD_FMM_IOP_NCO_0_REG_START 0x20cb0f00 |
| #define BCHP_AUD_FMM_IOP_NCO_0_REG_END 0x20cb0f38 |
| #define BCHP_AUD_FMM_IOP_NCO_1_REG_START 0x20cb1000 |
| #define BCHP_AUD_FMM_IOP_NCO_1_REG_END 0x20cb1038 |
| #define BCHP_AUD_FMM_IOP_NCO_2_REG_START 0x20cb1100 |
| #define BCHP_AUD_FMM_IOP_NCO_2_REG_END 0x20cb1138 |
| #define BCHP_AUD_FMM_IOP_NCO_3_REG_START 0x20cb1200 |
| #define BCHP_AUD_FMM_IOP_NCO_3_REG_END 0x20cb1238 |
| #define BCHP_AUD_FMM_IOP_NCO_4_REG_START 0x20cb1300 |
| #define BCHP_AUD_FMM_IOP_NCO_4_REG_END 0x20cb1338 |
| #define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_START 0x20cb1400 |
| #define BCHP_AUD_FMM_IOP_LOOPBACK_0_REG_END 0x20cb1524 |
| #define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_START 0x20cb1600 |
| #define BCHP_AUD_FMM_IOP_DUMMYSINK_0_REG_END 0x20cb165c |
| #define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_START 0x20cb1800 |
| #define BCHP_AUD_FMM_IOP_IN_SPDIF_0_REG_END 0x20cb18fc |
| #define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_START 0x20cb2000 |
| #define BCHP_AUD_FMM_IOP_IN_HDMI_0_REG_END 0x20cb20ac |
| #define BCHP_AUD_FMM_IOP_IN_I2S_0_REG_START 0x20cb2800 |
| #define BCHP_AUD_FMM_IOP_IN_I2S_0_REG_END 0x20cb2834 |
| #define BCHP_AUD_FMM_IOP_ATTG_0_REG_START 0x20cb2900 |
| #define BCHP_AUD_FMM_IOP_ATTG_0_REG_END 0x20cb2964 |
| #define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_START 0x20cb4000 |
| #define BCHP_AUD_FMM_IOP_OUT_MS_STRM_CFG_0_REG_END 0x20cb41fc |
| #define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_START 0x20cb4400 |
| #define BCHP_AUD_FMM_IOP_OUT_MS_STRM_ESR_0_REG_END 0x20cb4414 |
| #define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_START 0x20cb6000 |
| #define BCHP_AUD_FMM_IOP_OUT_MS_CTRL_0_REG_END 0x20cb7bfc |
| #define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_START 0x20cb7d00 |
| #define BCHP_AUD_FMM_IOP_OUT_MS_ESR_0_REG_END 0x20cb7d14 |
| #define BCHP_AUD_FMM_IOP_MISC_REG_START 0x20cb8100 |
| #define BCHP_AUD_FMM_IOP_MISC_REG_END 0x20cb8154 |
| #define BCHP_MPM_CPU_PROG_MEM_REG_START 0x20d00000 |
| #define BCHP_MPM_CPU_PROG_MEM_REG_END 0x20d0fffc |
| #define BCHP_MPM_CPU_DATA_MEM_REG_START 0x20d10000 |
| #define BCHP_MPM_CPU_DATA_MEM_REG_END 0x20d13ffc |
| #define BCHP_MPM_CPU_CORE_REGS_REG_START 0x20d20000 |
| #define BCHP_MPM_CPU_CORE_REGS_REG_END 0x20d200fc |
| #define BCHP_MPM_CPU_AUX_REGS_REG_START 0x20d22000 |
| #define BCHP_MPM_CPU_AUX_REGS_REG_END 0x20d23058 |
| #define BCHP_MPM_UART_REG_START 0x20d80000 |
| #define BCHP_MPM_UART_REG_END 0x20d80ffc |
| #define BCHP_MPM_WDOG_REG_START 0x20d81000 |
| #define BCHP_MPM_WDOG_REG_END 0x20d81ffc |
| #define BCHP_MPM_CPU_L1_REG_START 0x20d82000 |
| #define BCHP_MPM_CPU_L1_REG_END 0x20d82018 |
| #define BCHP_MPM_CPU_L2_REG_START 0x20d82100 |
| #define BCHP_MPM_CPU_L2_REG_END 0x20d8212c |
| #define BCHP_MPM_HOST_L2_REG_START 0x20d82200 |
| #define BCHP_MPM_HOST_L2_REG_END 0x20d8222c |
| #define BCHP_MPM_CPU_CTRL_REG_START 0x20d82300 |
| #define BCHP_MPM_CPU_CTRL_REG_END 0x20d82344 |
| #define BCHP_MPM_PM_L2_REG_START 0x20d82400 |
| #define BCHP_MPM_PM_L2_REG_END 0x20d8242c |
| #define BCHP_MPM_RANGE_BLOCKER_REG_START 0x20d82500 |
| #define BCHP_MPM_RANGE_BLOCKER_REG_END 0x20d82554 |
| #define BCHP_MPM_BSPI_REG_START 0x20d82600 |
| #define BCHP_MPM_BSPI_REG_END 0x20d8264c |
| #define BCHP_MPM_MSPI_REG_START 0x20d82800 |
| #define BCHP_MPM_MSPI_REG_END 0x20d82984 |
| #define BCHP_DVP_MT_AON_TOP_REG_START 0x20d83000 |
| #define BCHP_DVP_MT_AON_TOP_REG_END 0x20d8300c |
| #define BCHP_CBUS_INTR2_0_REG_START 0x20d83800 |
| #define BCHP_CBUS_INTR2_0_REG_END 0x20d8382c |
| #define BCHP_CBUS_INTR2_1_REG_START 0x20d83880 |
| #define BCHP_CBUS_INTR2_1_REG_END 0x20d838ac |
| #define BCHP_MT_CBUS_REG_START 0x20d83a00 |
| #define BCHP_MT_CBUS_REG_END 0x20d83afc |
| #define BCHP_MT_MSC_REQ_REG_START 0x20d83b00 |
| #define BCHP_MT_MSC_REQ_REG_END 0x20d83b6c |
| #define BCHP_MT_MSC_RESP_REG_START 0x20d83c00 |
| #define BCHP_MT_MSC_RESP_REG_END 0x20d83cac |
| #define BCHP_MT_DDC_REQ_REG_START 0x20d83d00 |
| #define BCHP_MT_DDC_REQ_REG_END 0x20d83d6c |
| #define BCHP_MPM_FLASH_MEM_REG_START 0x20dc0000 |
| #define BCHP_MPM_FLASH_MEM_REG_END 0x20ddfffc |
| #define BCHP_MEMC_GEN_0_REG_START 0x21100000 |
| #define BCHP_MEMC_GEN_0_REG_END 0x211007fc |
| #define BCHP_MEMC_EDIS_0_0_REG_START 0x21100800 |
| #define BCHP_MEMC_EDIS_0_0_REG_END 0x211008fc |
| #define BCHP_MEMC_EDIS_0_1_REG_START 0x21100a00 |
| #define BCHP_MEMC_EDIS_0_1_REG_END 0x21100afc |
| #define BCHP_MEMC_ARC_0_REG_START 0x21100c00 |
| #define BCHP_MEMC_ARC_0_REG_END 0x21100f74 |
| #define BCHP_MEMC_ARB_0_REG_START 0x21101000 |
| #define BCHP_MEMC_ARB_0_REG_END 0x211014d0 |
| #define BCHP_MEMC_DDR_0_REG_START 0x21102000 |
| #define BCHP_MEMC_DDR_0_REG_END 0x211027fc |
| #define BCHP_MEMC_L2_0_0_REG_START 0x21103000 |
| #define BCHP_MEMC_L2_0_0_REG_END 0x21103044 |
| #define BCHP_MEMC_L2_0_1_REG_START 0x21103200 |
| #define BCHP_MEMC_L2_0_1_REG_END 0x21103244 |
| #define BCHP_MEMC_L2_0_2_REG_START 0x21103400 |
| #define BCHP_MEMC_L2_0_2_REG_END 0x21103444 |
| #define BCHP_MEMC_TRACELOG_0_0_REG_START 0x21103800 |
| #define BCHP_MEMC_TRACELOG_0_0_REG_END 0x211039fc |
| #define BCHP_MEMC_RGRB_0_REG_START 0x21104000 |
| #define BCHP_MEMC_RGRB_0_REG_END 0x21104010 |
| #define BCHP_MEMC_MISC_0_REG_START 0x21105000 |
| #define BCHP_MEMC_MISC_0_REG_END 0x21105014 |
| #define BCHP_SHIMPHY_ADDR_CNTL_0_REG_START 0x21108000 |
| #define BCHP_SHIMPHY_ADDR_CNTL_0_REG_END 0x211080c4 |
| #define BCHP_DDR34_PHY_COMMON_REGS_0_REG_START 0x21120000 |
| #define BCHP_DDR34_PHY_COMMON_REGS_0_REG_END 0x21120060 |
| #define BCHP_DDR34_PHY_CONTROL_REGS_A_0_REG_START 0x21120200 |
| #define BCHP_DDR34_PHY_CONTROL_REGS_A_0_REG_END 0x211202dc |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_A_0_REG_START 0x21120400 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_A_0_REG_END 0x2112057c |
| #define BCHP_DDR34_PHY_BYTE_LANE_1_A_0_REG_START 0x21120600 |
| #define BCHP_DDR34_PHY_BYTE_LANE_1_A_0_REG_END 0x2112077c |
| #define BCHP_DDR34_PHY_CONTROL_REGS_B_0_REG_START 0x21120800 |
| #define BCHP_DDR34_PHY_CONTROL_REGS_B_0_REG_END 0x211208dc |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_B_0_REG_START 0x21120a00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_B_0_REG_END 0x21120b7c |
| #define BCHP_DDR34_PHY_BYTE_LANE_1_B_0_REG_START 0x21120c00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_1_B_0_REG_END 0x21120d7c |
| #define BCHP_DDR34_PHY_PHYBIST_0_REG_START 0x21122000 |
| #define BCHP_DDR34_PHY_PHYBIST_0_REG_END 0x21122030 |
| #define BCHP_DPFE_CONTROLLER_0_REG_START 0x21130000 |
| #define BCHP_DPFE_CONTROLLER_0_REG_END 0x2113006c |
| #define BCHP_DPFE_EDIS_0_0_REG_START 0x21130400 |
| #define BCHP_DPFE_EDIS_0_0_REG_END 0x211305c4 |
| #define BCHP_DPFE_EDIS_0_1_REG_START 0x21130800 |
| #define BCHP_DPFE_EDIS_0_1_REG_END 0x211309c4 |
| #define BCHP_DPFE_CPU_0_REG_START 0x21132000 |
| #define BCHP_DPFE_CPU_0_REG_END 0x2113217c |
| #define BCHP_DPFE_UART_0_REG_START 0x21133000 |
| #define BCHP_DPFE_UART_0_REG_END 0x21133008 |
| #define BCHP_DPFE_DMEM_0_REG_START 0x21134000 |
| #define BCHP_DPFE_DMEM_0_REG_END 0x21134ffc |
| #define BCHP_DPFE_IMEM_0_REG_START 0x21138000 |
| #define BCHP_DPFE_IMEM_0_REG_END 0x2113bffc |
| #define BCHP_MEMC_SENTINEL_0_0_REG_START 0x21140000 |
| #define BCHP_MEMC_SENTINEL_0_0_REG_END 0x2117fffc |
| #define BCHP_V3D_HUB_CTL_REG_START 0x21200000 |
| #define BCHP_V3D_HUB_CTL_REG_END 0x2120007c |
| #define BCHP_V3D_TSY_REG_START 0x21200100 |
| #define BCHP_V3D_TSY_REG_END 0x21200168 |
| #define BCHP_V3D_MSO_REG_START 0x21200200 |
| #define BCHP_V3D_MSO_REG_END 0x2120037c |
| #define BCHP_V3D_TFU_REG_START 0x21200400 |
| #define BCHP_V3D_TFU_REG_END 0x2120048c |
| #define BCHP_V3D_MCS_REG_START 0x21200500 |
| #define BCHP_V3D_MCS_REG_END 0x2120055c |
| #define BCHP_V3D_MMUC_REG_START 0x21201000 |
| #define BCHP_V3D_MMUC_REG_END 0x21201020 |
| #define BCHP_V3D_MMU_T_REG_START 0x21201100 |
| #define BCHP_V3D_MMU_T_REG_END 0x21201134 |
| #define BCHP_V3D_MMU_0_REG_START 0x21201200 |
| #define BCHP_V3D_MMU_0_REG_END 0x21201234 |
| #define BCHP_V3D_TOP_GR_BRIDGE_REG_START 0x21204000 |
| #define BCHP_V3D_TOP_GR_BRIDGE_REG_END 0x2120400c |
| #define BCHP_V3D_GCA_REG_START 0x21204100 |
| #define BCHP_V3D_GCA_REG_END 0x212041d4 |
| #define BCHP_V3D_CTL_0_REG_START 0x21208000 |
| #define BCHP_V3D_CTL_0_REG_END 0x2120807c |
| #define BCHP_V3D_CLE_0_REG_START 0x21208100 |
| #define BCHP_V3D_CLE_0_REG_END 0x212081fc |
| #define BCHP_V3D_PTB_0_REG_START 0x21208300 |
| #define BCHP_V3D_PTB_0_REG_END 0x21208310 |
| #define BCHP_V3D_QPS_0_REG_START 0x21208400 |
| #define BCHP_V3D_QPS_0_REG_END 0x2120843c |
| #define BCHP_V3D_VPM_0_REG_START 0x21208500 |
| #define BCHP_V3D_VPM_0_REG_END 0x21208504 |
| #define BCHP_V3D_PCTR_0_REG_START 0x21208600 |
| #define BCHP_V3D_PCTR_0_REG_END 0x212086fc |
| #define BCHP_V3D_AXM_0_REG_START 0x21208700 |
| #define BCHP_V3D_AXM_0_REG_END 0x21208718 |
| #define BCHP_V3D_GMP_0_REG_START 0x21208800 |
| #define BCHP_V3D_GMP_0_REG_END 0x21208820 |
| #define BCHP_V3D_ERR_0_REG_START 0x21208f00 |
| #define BCHP_V3D_ERR_0_REG_END 0x21208f20 |
| #define BCHP_V3D_QPUDBG_0_REG_START 0x2120a000 |
| #define BCHP_V3D_QPUDBG_0_REG_END 0x2120bffc |
| #define BCHP_WLAN_INTF_RGR_BRIDGE_REG_START 0x217e0000 |
| #define BCHP_WLAN_INTF_RGR_BRIDGE_REG_END 0x217e0010 |
| #define BCHP_WLAN_INTF_D2H_INTR2_REG_START 0x217e0100 |
| #define BCHP_WLAN_INTF_D2H_INTR2_REG_END 0x217e012c |
| #define BCHP_WLAN_INTF_AXI2SCB_REG_START 0x217e0200 |
| #define BCHP_WLAN_INTF_AXI2SCB_REG_END 0x217e0288 |
| #define BCHP_WLAN_INTF_CTRL_REG_START 0x217e0300 |
| #define BCHP_WLAN_INTF_CTRL_REG_END 0x217e0320 |
| #define BCHP_WLAN_CHIPC_BASE_REG_START 0x21800000 |
| #define BCHP_WLAN_CHIPC_BASE_REG_END 0x218000fc |
| #define BCHP_WLAN_MAC_HC_HIN_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_HC_HIN_REG_END 0x218013dc |
| #define BCHP_WLAN_MAC_HC_PHY_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_HC_PHY_REG_END 0x218013fe |
| #define BCHP_WLAN_MAC_HC_RXE_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_HC_RXE_REG_END 0x21801432 |
| #define BCHP_WLAN_MAC_HC_TXE_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_HC_TXE_REG_END 0x2180151a |
| #define BCHP_WLAN_MAC_HC_TSF_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_HC_TSF_REG_END 0x21801672 |
| #define BCHP_WLAN_MAC_HC_IFS_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_HC_IFS_REG_END 0x218016f8 |
| #define BCHP_WLAN_MAC_HC_NAV_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_HC_NAV_REG_END 0x21801712 |
| #define BCHP_WLAN_MAC_WEP_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_WEP_REG_END 0x218017d6 |
| #define BCHP_WLAN_MAC_HC_PMQ_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_HC_PMQ_REG_END 0x218017ee |
| #define BCHP_WLAN_MAC_SHMDMA_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_SHMDMA_REG_END 0x21801870 |
| #define BCHP_WLAN_MAC_RXE_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_RXE_REG_END 0x21801960 |
| #define BCHP_WLAN_MAC_PSMSEL_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_PSMSEL_REG_END 0x21801a0e |
| #define BCHP_WLAN_MAC_SERIAL_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_SERIAL_REG_END 0x21801a56 |
| #define BCHP_WLAN_MAC_FCBS_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_FCBS_REG_END 0x21801a7c |
| #define BCHP_WLAN_MAC_HC_PSM_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_HC_PSM_REG_END 0x21801ace |
| #define BCHP_WLAN_MAC_TXE_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_TXE_REG_END 0x21801b52 |
| #define BCHP_WLAN_MAC_AQM_REG_START 0x21801000 |
| #define BCHP_WLAN_MAC_AQM_REG_END 0x21801bfc |
| #define BCHP_WLAN_PMU_REG_START 0x21802000 |
| #define BCHP_WLAN_PMU_REG_END 0x21802784 |
| #define BCHP_WLAN_GCI_REG_START 0x21804000 |
| #define BCHP_WLAN_GCI_REG_END 0x218043fc |
| #define BCHP_WLAN_RADIO_0_REG_START 0x21806000 |
| #define BCHP_WLAN_RADIO_0_REG_END 0x218067fc |
| #define BCHP_WLAN_RADIO_1_REG_START 0x21807000 |
| #define BCHP_WLAN_RADIO_1_REG_END 0x218077fc |
| #define BCHP_WLAN_RADIO_2_REG_START 0x21808000 |
| #define BCHP_WLAN_RADIO_2_REG_END 0x218087fc |
| #define BCHP_WLAN_RADIO_3_REG_START 0x21809000 |
| #define BCHP_WLAN_RADIO_3_REG_END 0x218097fc |
| #define BCHP_WLAN_RADIO_RFPLL_0_REG_START 0x2180a000 |
| #define BCHP_WLAN_RADIO_RFPLL_0_REG_END 0x2180a7fc |
| #define BCHP_WLAN_CHIPC_MASTER_REG_START 0x21900000 |
| #define BCHP_WLAN_CHIPC_MASTER_REG_END 0x21900e00 |
| #define BCHP_WLAN_DOT11_MASTER_REG_START 0x21901000 |
| #define BCHP_WLAN_DOT11_MASTER_REG_END 0x21901e00 |
| #define BCHP_WLAN_DOT11_I1_MASTER_REG_START 0x21902000 |
| #define BCHP_WLAN_DOT11_I1_MASTER_REG_END 0x21902e00 |
| #define BCHP_WLAN_RBUS_BRIDGE_MASTER_REG_START 0x21903000 |
| #define BCHP_WLAN_RBUS_BRIDGE_MASTER_REG_END 0x21903e00 |
| #define BCHP_WLAN_SCB_BRIDGE_SLAVE_REG_START 0x21904000 |
| #define BCHP_WLAN_SCB_BRIDGE_SLAVE_REG_END 0x21904e00 |
| #define BCHP_WLAN_VASIP_BRIDGE_SLAVE_REG_START 0x21905000 |
| #define BCHP_WLAN_VASIP_BRIDGE_SLAVE_REG_END 0x21905e00 |
| #define BCHP_WLAN_APB_BRIDGE_SLAVE_REG_START 0x21906000 |
| #define BCHP_WLAN_APB_BRIDGE_SLAVE_REG_END 0x21906e00 |
| #define BCHP_WLAN_DEFAULT_SLAVE_REG_START 0x21909000 |
| #define BCHP_WLAN_DEFAULT_SLAVE_REG_END 0x21909e00 |
| #define BCHP_WLAN_DOT11_SLAVE_REG_START 0x2190a000 |
| #define BCHP_WLAN_DOT11_SLAVE_REG_END 0x2190ae00 |
| |
| |
| /*************************************************************************** |
| *AUD_FMM_MS_CTRL |
| ***************************************************************************/ |
| /*************************************************************************** |
| *ABSTRACT_01_MICRO_SEQUENCER_CONTROL - Process to initialize and enable microsequencer |
| ***************************************************************************/ |
| /* AUD_FMM_MS_CTRL :: ABSTRACT_01_MICRO_SEQUENCER_CONTROL :: NULL [31:00] */ |
| #define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_MASK 0xffffffff |
| #define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_01_MICRO_SEQUENCER_CONTROL_NULL_SHIFT 0 |
| |
| /*************************************************************************** |
| *ABSTRACT_02_CHANNEL_STATUS - How to control channel status bits |
| ***************************************************************************/ |
| /* AUD_FMM_MS_CTRL :: ABSTRACT_02_CHANNEL_STATUS :: NULL [31:00] */ |
| #define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_MASK 0xffffffff |
| #define BCHP_AUD_FMM_MS_CTRL_ABSTRACT_02_CHANNEL_STATUS_NULL_SHIFT 0 |
| |
| /*************************************************************************** |
| *AUD_FMM_OP_CTRL |
| ***************************************************************************/ |
| /*************************************************************************** |
| *ABSTRACT_01_MULTICHANNEL_MAI - Transmitting 6- and 8-channel MAI |
| ***************************************************************************/ |
| /* AUD_FMM_OP_CTRL :: ABSTRACT_01_MULTICHANNEL_MAI :: MORE_INFORMATION [31:00] */ |
| #define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_MASK 0xffffffff |
| #define BCHP_AUD_FMM_OP_CTRL_ABSTRACT_01_MULTICHANNEL_MAI_MORE_INFORMATION_SHIFT 0 |
| |
| /*************************************************************************** |
| *BVN_MVFD_MFD |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DRAM_DATA_STRUCTURE - DRAM Data Structure |
| ***************************************************************************/ |
| /* BVN_MVFD_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ |
| #define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff |
| #define BCHP_BVN_MVFD_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 |
| |
| /*************************************************************************** |
| *BVN_MVFD_MFD_8B_UHD |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DRAM_DATA_STRUCTURE - DRAM Data Structure |
| ***************************************************************************/ |
| /* BVN_MVFD_MFD_8B_UHD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ |
| #define BCHP_BVN_MVFD_MFD_8B_UHD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff |
| #define BCHP_BVN_MVFD_MFD_8B_UHD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 |
| |
| /*************************************************************************** |
| *BVN_MVFD_VFD |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DRAM_DATA_STRUCTURE - DRAM Data Structure |
| ***************************************************************************/ |
| /* BVN_MVFD_VFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ |
| #define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff |
| #define BCHP_BVN_MVFD_VFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 |
| |
| /*************************************************************************** |
| *BVN_MVFD_VFD_8B |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DRAM_DATA_STRUCTURE - DRAM Data Structure |
| ***************************************************************************/ |
| /* BVN_MVFD_VFD_8B :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ |
| #define BCHP_BVN_MVFD_VFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff |
| #define BCHP_BVN_MVFD_VFD_8B_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 |
| |
| /*************************************************************************** |
| *DPFE_CONTROLLER |
| ***************************************************************************/ |
| /*************************************************************************** |
| *Command_Code - DPFE Command Code Format |
| ***************************************************************************/ |
| /* DPFE_CONTROLLER :: Command_Code :: reserved0 [07:05] */ |
| #define BCHP_DPFE_CONTROLLER_Command_Code_reserved0_MASK 0xe0 |
| #define BCHP_DPFE_CONTROLLER_Command_Code_reserved0_SHIFT 5 |
| |
| /* union - case code [04:00] */ |
| /* DPFE_CONTROLLER :: Command_Code :: code :: all [04:00] */ |
| #define BCHP_DPFE_CONTROLLER_Command_Code_code_all_MASK 0x1f |
| #define BCHP_DPFE_CONTROLLER_Command_Code_code_all_SHIFT 0 |
| |
| /* union - case bits [04:00] */ |
| /* DPFE_CONTROLLER :: Command_Code :: bits :: cs [04:03] */ |
| #define BCHP_DPFE_CONTROLLER_Command_Code_bits_cs_MASK 0x18 |
| #define BCHP_DPFE_CONTROLLER_Command_Code_bits_cs_SHIFT 3 |
| |
| /* DPFE_CONTROLLER :: Command_Code :: bits :: ras [02:02] */ |
| #define BCHP_DPFE_CONTROLLER_Command_Code_bits_ras_MASK 0x04 |
| #define BCHP_DPFE_CONTROLLER_Command_Code_bits_ras_SHIFT 2 |
| |
| /* DPFE_CONTROLLER :: Command_Code :: bits :: cas [01:01] */ |
| #define BCHP_DPFE_CONTROLLER_Command_Code_bits_cas_MASK 0x02 |
| #define BCHP_DPFE_CONTROLLER_Command_Code_bits_cas_SHIFT 1 |
| |
| /* DPFE_CONTROLLER :: Command_Code :: bits :: we [00:00] */ |
| #define BCHP_DPFE_CONTROLLER_Command_Code_bits_we_MASK 0x01 |
| #define BCHP_DPFE_CONTROLLER_Command_Code_bits_we_SHIFT 0 |
| |
| /*************************************************************************** |
| *Row_Addr - DPFE Row Address Format |
| ***************************************************************************/ |
| /* DPFE_CONTROLLER :: Row_Addr :: reserved0 [23:17] */ |
| #define BCHP_DPFE_CONTROLLER_Row_Addr_reserved0_MASK 0xfe0000 |
| #define BCHP_DPFE_CONTROLLER_Row_Addr_reserved0_SHIFT 17 |
| |
| /* DPFE_CONTROLLER :: Row_Addr :: Row_Addr [16:00] */ |
| #define BCHP_DPFE_CONTROLLER_Row_Addr_Row_Addr_MASK 0x01ffff |
| #define BCHP_DPFE_CONTROLLER_Row_Addr_Row_Addr_SHIFT 0 |
| |
| /*************************************************************************** |
| *Bank_Addr - DPFE Bank Address Format |
| ***************************************************************************/ |
| /* DPFE_CONTROLLER :: Bank_Addr :: reserved0 [07:04] */ |
| #define BCHP_DPFE_CONTROLLER_Bank_Addr_reserved0_MASK 0xf0 |
| #define BCHP_DPFE_CONTROLLER_Bank_Addr_reserved0_SHIFT 4 |
| |
| /* DPFE_CONTROLLER :: Bank_Addr :: Bank_Addr [03:00] */ |
| #define BCHP_DPFE_CONTROLLER_Bank_Addr_Bank_Addr_MASK 0x0f |
| #define BCHP_DPFE_CONTROLLER_Bank_Addr_Bank_Addr_SHIFT 0 |
| |
| /*************************************************************************** |
| *Post_Command_Delay - DPFE Post Command Delay Format |
| ***************************************************************************/ |
| /* DPFE_CONTROLLER :: Post_Command_Delay :: reserved0 [15:12] */ |
| #define BCHP_DPFE_CONTROLLER_Post_Command_Delay_reserved0_MASK 0xf000 |
| #define BCHP_DPFE_CONTROLLER_Post_Command_Delay_reserved0_SHIFT 12 |
| |
| /* DPFE_CONTROLLER :: Post_Command_Delay :: Post_Command_Delay [11:00] */ |
| #define BCHP_DPFE_CONTROLLER_Post_Command_Delay_Post_Command_Delay_MASK 0x0fff |
| #define BCHP_DPFE_CONTROLLER_Post_Command_Delay_Post_Command_Delay_SHIFT 0 |
| |
| /*************************************************************************** |
| *GFD |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DRAM_DATA_STRUCTURE - DRAM Data Structure |
| ***************************************************************************/ |
| /* GFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ |
| #define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff |
| #define BCHP_GFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 |
| |
| /*************************************************************************** |
| *GFD_HSCL_ONLY |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DRAM_DATA_STRUCTURE - DRAM Data Structure |
| ***************************************************************************/ |
| /* GFD_HSCL_ONLY :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ |
| #define BCHP_GFD_HSCL_ONLY_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff |
| #define BCHP_GFD_HSCL_ONLY_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 |
| |
| /*************************************************************************** |
| *HIFIDAC_CTRL |
| ***************************************************************************/ |
| /*************************************************************************** |
| *ABSTRACT_01_COMING_OUT_OF_RESET - Process to come out of reset |
| ***************************************************************************/ |
| /* HIFIDAC_CTRL :: ABSTRACT_01_COMING_OUT_OF_RESET :: MORE_INFORMATION [31:00] */ |
| #define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_MASK 0xffffffff |
| #define BCHP_HIFIDAC_CTRL_ABSTRACT_01_COMING_OUT_OF_RESET_MORE_INFORMATION_SHIFT 0 |
| |
| /*************************************************************************** |
| *ABSTRACT_02_MUTE_USAGE - Mute usage |
| ***************************************************************************/ |
| /* HIFIDAC_CTRL :: ABSTRACT_02_MUTE_USAGE :: MORE_INFORMATION [31:00] */ |
| #define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_MASK 0xffffffff |
| #define BCHP_HIFIDAC_CTRL_ABSTRACT_02_MUTE_USAGE_MORE_INFORMATION_SHIFT 0 |
| |
| /*************************************************************************** |
| *ABSTRACT_03_SAMPLE_RATE_CHANGE - Process to effect a sample rate change |
| ***************************************************************************/ |
| /* HIFIDAC_CTRL :: ABSTRACT_03_SAMPLE_RATE_CHANGE :: MORE_INFORMATION [31:00] */ |
| #define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_MASK 0xffffffff |
| #define BCHP_HIFIDAC_CTRL_ABSTRACT_03_SAMPLE_RATE_CHANGE_MORE_INFORMATION_SHIFT 0 |
| |
| /*************************************************************************** |
| *M2MC |
| ***************************************************************************/ |
| /*************************************************************************** |
| *TYPE_CLUT_COLOR_DATA - color data for color look up table |
| ***************************************************************************/ |
| /* M2MC :: TYPE_CLUT_COLOR_DATA :: ALPHA [31:24] */ |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_MASK 0xff000000 |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_ALPHA_SHIFT 24 |
| |
| /* M2MC :: TYPE_CLUT_COLOR_DATA :: RED [23:16] */ |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_MASK 0x00ff0000 |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_RED_SHIFT 16 |
| |
| /* M2MC :: TYPE_CLUT_COLOR_DATA :: GREEN [15:08] */ |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_MASK 0x0000ff00 |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_GREEN_SHIFT 8 |
| |
| /* M2MC :: TYPE_CLUT_COLOR_DATA :: BLUE [07:00] */ |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_MASK 0x000000ff |
| #define BCHP_M2MC_TYPE_CLUT_COLOR_DATA_BLUE_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PACKET_ABSTRACT - Linked-List Packet Abstract |
| ***************************************************************************/ |
| /* M2MC :: LIST_PACKET_ABSTRACT :: PACKET_FORMAT [31:00] */ |
| #define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PACKET_ABSTRACT_PACKET_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PACKET_HEADER_0 - Linked-List Packet Header Word 0 |
| ***************************************************************************/ |
| /* M2MC :: LIST_PACKET_HEADER_0 :: reserved0 [31:28] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_MASK 0xf0000000 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved0_SHIFT 28 |
| |
| /* M2MC :: LIST_PACKET_HEADER_0 :: NEXT_PKT_ADDR [27:05] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_MASK 0x0fffffe0 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_NEXT_PKT_ADDR_SHIFT 5 |
| |
| /* M2MC :: LIST_PACKET_HEADER_0 :: reserved1 [04:01] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_MASK 0x0000001e |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_reserved1_SHIFT 1 |
| |
| /* M2MC :: LIST_PACKET_HEADER_0 :: LAST_PKT_IND [00:00] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_MASK 0x00000001 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_SHIFT 0 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktValid 0 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_0_LAST_PKT_IND_NextPktInvalid 1 |
| |
| /*************************************************************************** |
| *LIST_PACKET_HEADER_1 - Linked-List Packet Header Word 1 |
| ***************************************************************************/ |
| /* M2MC :: LIST_PACKET_HEADER_1 :: reserved0 [31:15] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_MASK 0xffff8000 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_reserved0_SHIFT 15 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: SRC_FEEDER_GRP_CNTRL [14:14] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_MASK 0x00004000 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_SHIFT 14 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_FEEDER_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: DST_FEEDER_GRP_CNTRL [13:13] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_MASK 0x00002000 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_SHIFT 13 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_FEEDER_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_FEEDER_GRP_CNTRL [12:12] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_MASK 0x00001000 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_SHIFT 12 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_FEEDER_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: BLIT_GRP_CNTRL [11:11] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_MASK 0x00000800 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_SHIFT 11 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLIT_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_PARAM_GRP_CNTRL [10:10] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_MASK 0x00000400 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_SHIFT 10 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_PARAM_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: BLEND_PARAM_GRP_CNTRL [09:09] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_MASK 0x00000200 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_SHIFT 9 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_BLEND_PARAM_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: ROP_GRP_CNTRL [08:08] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_MASK 0x00000100 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_SHIFT 8 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_ROP_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_KEY_GRP_CNTRL [07:07] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_MASK 0x00000080 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_SHIFT 7 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_KEY_GRP_CNTRL [06:06] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_MASK 0x00000040 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_SHIFT 6 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_KEY_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: SCALE_COEF_GRP_CNTRL [05:05] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_MASK 0x00000020 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_SHIFT 5 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SCALE_COEF_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: SRC_COLOR_MATRIX_GRP_CNTRL [04:04] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000010 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_SHIFT 4 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: DST_COLOR_MATRIX_GRP_CNTRL [03:03] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000008 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_SHIFT 3 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: OUTPUT_COLOR_MATRIX_GRP_CNTRL [02:02] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_MASK 0x00000004 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_SHIFT 2 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_OUTPUT_COLOR_MATRIX_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: SRC_CLUT_GRP_CNTRL [01:01] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_MASK 0x00000002 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_SHIFT 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_SRC_CLUT_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /* M2MC :: LIST_PACKET_HEADER_1 :: DST_CLUT_GRP_CNTRL [00:00] */ |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_MASK 0x00000001 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_SHIFT 0 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_ENABLE 1 |
| #define BCHP_M2MC_LIST_PACKET_HEADER_1_DST_CLUT_GRP_CNTRL_GRP_DISABLE 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_00_SRC_FEEDER_N - Linked-List Packet Word N for group SRC_FEEDER |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_00_SRC_FEEDER_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_00_SRC_FEEDER_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_01_DST_FEEDER_N - Linked-List Packet Word N for group DST_FEEDER |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_01_DST_FEEDER_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_01_DST_FEEDER_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_02_OUTPUT_FEEDER_N - Linked-List Packet Word N for group OUTPUT_FEEDER |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_02_OUTPUT_FEEDER_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_02_OUTPUT_FEEDER_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_03_BLIT_N - Linked-List Packet Word N for group BLIT |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_03_BLIT_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_03_BLIT_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_04_SCALE_PARAM_N - Linked-List Packet Word N for group SCALE_PARAM |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_04_SCALE_PARAM_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_04_SCALE_PARAM_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_05_BLEND_PARAM_N - Linked-List Packet Word N for group BLEND_PARAM |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_05_BLEND_PARAM_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_05_BLEND_PARAM_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_06_ROP_N - Linked-List Packet Word N for group ROP |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_06_ROP_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_06_ROP_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_07_SRC_COLOR_KEY_N - Linked-List Packet Word N for group SRC_COLOR_KEY |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_07_SRC_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_07_SRC_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_08_DST_COLOR_KEY_N - Linked-List Packet Word N for group DST_COLOR_KEY |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_08_DST_COLOR_KEY_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_08_DST_COLOR_KEY_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_09_SCALE_COEF_N - Linked-List Packet Word N for group SCALE_COEF |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_09_SCALE_COEF_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_09_SCALE_COEF_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_10_SRC_COLOR_MATRIX_N - Linked-List Packet Word N for group SRC_COLOR_MATRIX |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_10_SRC_COLOR_MATRIX_N :: REGISTER_CONTENTS [31:00] */ |
| #define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_MASK 0xffffffff |
| #define BCHP_M2MC_LIST_PKT_10_SRC_COLOR_MATRIX_N_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *LIST_PKT_11_SRC_CLUT - Linked-List Packet Word for group SRC_CLUT |
| ***************************************************************************/ |
| /* M2MC :: LIST_PKT_11_SRC_CLUT :: reserved0 [31:29] */ |
| #define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_MASK 0xe0000000 |
| #define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_reserved0_SHIFT 29 |
| |
| /* M2MC :: LIST_PKT_11_SRC_CLUT :: REGISTER_CONTENTS [28:00] */ |
| #define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_MASK 0x1fffffff |
| #define BCHP_M2MC_LIST_PKT_11_SRC_CLUT_REGISTER_CONTENTS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PCIE_DMA |
| ***************************************************************************/ |
| /*************************************************************************** |
| *DESC_WORD0 - PCIE DMA Descriptor Word 0 |
| ***************************************************************************/ |
| /* PCIE_DMA :: DESC_WORD0 :: MEMORY_ADDRESS [31:00] */ |
| #define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_MASK 0xffffffff |
| #define BCHP_PCIE_DMA_DESC_WORD0_MEMORY_ADDRESS_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_WORD1 - PCIE DMA Descriptor Word 1 |
| ***************************************************************************/ |
| /* PCIE_DMA :: DESC_WORD1 :: PCIE_ADDRESS_LO [31:00] */ |
| #define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_MASK 0xffffffff |
| #define BCHP_PCIE_DMA_DESC_WORD1_PCIE_ADDRESS_LO_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_WORD2 - PCIE DMA Descriptor Word 2 |
| ***************************************************************************/ |
| /* PCIE_DMA :: DESC_WORD2 :: PCIE_ADDRESS_HI [31:00] */ |
| #define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_MASK 0xffffffff |
| #define BCHP_PCIE_DMA_DESC_WORD2_PCIE_ADDRESS_HI_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_WORD3 - PCIE DMA Descriptor Word 3 |
| ***************************************************************************/ |
| /* PCIE_DMA :: DESC_WORD3 :: INTERRUPT_ENABLE [31:31] */ |
| #define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_MASK 0x80000000 |
| #define BCHP_PCIE_DMA_DESC_WORD3_INTERRUPT_ENABLE_SHIFT 31 |
| |
| /* PCIE_DMA :: DESC_WORD3 :: reserved0 [30:25] */ |
| #define BCHP_PCIE_DMA_DESC_WORD3_reserved0_MASK 0x7e000000 |
| #define BCHP_PCIE_DMA_DESC_WORD3_reserved0_SHIFT 25 |
| |
| /* PCIE_DMA :: DESC_WORD3 :: DMA_TRANSFER_SIZE [24:00] */ |
| #define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_MASK 0x01ffffff |
| #define BCHP_PCIE_DMA_DESC_WORD3_DMA_TRANSFER_SIZE_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_WORD4 - PCIE DMA Descriptor Word 4 |
| ***************************************************************************/ |
| /* PCIE_DMA :: DESC_WORD4 :: LAST_RECORD_INDICATOR [31:31] */ |
| #define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_MASK 0x80000000 |
| #define BCHP_PCIE_DMA_DESC_WORD4_LAST_RECORD_INDICATOR_SHIFT 31 |
| |
| /* PCIE_DMA :: DESC_WORD4 :: DMA_DIRECTION [30:30] */ |
| #define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MASK 0x40000000 |
| #define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_SHIFT 30 |
| #define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_PCIE_TO_MEMORY 1 |
| #define BCHP_PCIE_DMA_DESC_WORD4_DMA_DIRECTION_MEMORY_TO_PCIE 0 |
| |
| /* PCIE_DMA :: DESC_WORD4 :: reserved0 [29:03] */ |
| #define BCHP_PCIE_DMA_DESC_WORD4_reserved0_MASK 0x3ffffff8 |
| #define BCHP_PCIE_DMA_DESC_WORD4_reserved0_SHIFT 3 |
| |
| /* PCIE_DMA :: DESC_WORD4 :: DESC_CONTIGUOUS [02:02] */ |
| #define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_MASK 0x00000004 |
| #define BCHP_PCIE_DMA_DESC_WORD4_DESC_CONTIGUOUS_SHIFT 2 |
| |
| /* PCIE_DMA :: DESC_WORD4 :: ENDIAN_XLATE_MODE [01:00] */ |
| #define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_MASK 0x00000003 |
| #define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SHIFT 0 |
| #define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_NO_SWAP 0 |
| #define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_16_IN_32 1 |
| #define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_SWAP_32 2 |
| #define BCHP_PCIE_DMA_DESC_WORD4_ENDIAN_XLATE_MODE_reserved 3 |
| |
| /*************************************************************************** |
| *DESC_WORD5 - PCIE DMA Descriptor Word 5 |
| ***************************************************************************/ |
| /* PCIE_DMA :: DESC_WORD5 :: NEXT_DESC_ADDRESS_LO [31:05] */ |
| #define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_MASK 0xffffffe0 |
| #define BCHP_PCIE_DMA_DESC_WORD5_NEXT_DESC_ADDRESS_LO_SHIFT 5 |
| |
| /* PCIE_DMA :: DESC_WORD5 :: reserved0 [04:00] */ |
| #define BCHP_PCIE_DMA_DESC_WORD5_reserved0_MASK 0x0000001f |
| #define BCHP_PCIE_DMA_DESC_WORD5_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_WORD6 - PCIE DMA Descriptor Word 6 |
| ***************************************************************************/ |
| /* PCIE_DMA :: DESC_WORD6 :: NEXT_DESC_ADDRESS_HI [31:00] */ |
| #define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_MASK 0xffffffff |
| #define BCHP_PCIE_DMA_DESC_WORD6_NEXT_DESC_ADDRESS_HI_SHIFT 0 |
| |
| /*************************************************************************** |
| *DESC_WORD7 - PCIE DMA Descriptor Word 7 |
| ***************************************************************************/ |
| /* PCIE_DMA :: DESC_WORD7 :: reserved0 [31:08] */ |
| #define BCHP_PCIE_DMA_DESC_WORD7_reserved0_MASK 0xffffff00 |
| #define BCHP_PCIE_DMA_DESC_WORD7_reserved0_SHIFT 8 |
| |
| /* PCIE_DMA :: DESC_WORD7 :: MEMORY_ADDRESS_HI [07:00] */ |
| #define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_MASK 0x000000ff |
| #define BCHP_PCIE_DMA_DESC_WORD7_MEMORY_ADDRESS_HI_SHIFT 0 |
| |
| /*************************************************************************** |
| *RAAGA_REGSET_DSP_ESR_SI |
| ***************************************************************************/ |
| /*************************************************************************** |
| *FIREPATH_INTERRUPTS_STRUCTURE - Firepath Interrupts Structure |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: UNUSED [31:23] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_UNUSED_MASK 0xff800000 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_UNUSED_SHIFT 23 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: RAAGA_AX_DONE_INT [22:22] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_RAAGA_AX_DONE_INT_MASK 0x00400000 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_RAAGA_AX_DONE_INT_SHIFT 22 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: RAAGA_ERROR_INT [21:21] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_RAAGA_ERROR_INT_MASK 0x00200000 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_RAAGA_ERROR_INT_SHIFT 21 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: RAAGA_TIMER_INT [20:20] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_RAAGA_TIMER_INT_MASK 0x00100000 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_RAAGA_TIMER_INT_SHIFT 20 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: PEEK_POKE_INT [19:19] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_PEEK_POKE_INT_MASK 0x00080000 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_PEEK_POKE_INT_SHIFT 19 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: BSP_CMD_INT [18:18] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_BSP_CMD_INT_MASK 0x00040000 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_BSP_CMD_INT_SHIFT 18 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: FMM_INT [17:17] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_FMM_INT_MASK 0x00020000 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_FMM_INT_SHIFT 17 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: VOM_MISS_INT [16:16] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_VOM_MISS_INT_MASK 0x00010000 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_VOM_MISS_INT_SHIFT 16 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: ESR_SI_INT [15:15] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_ESR_SI_INT_MASK 0x00008000 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_ESR_SI_INT_SHIFT 15 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: BVN_DISC_INT [14:14] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_BVN_DISC_INT_MASK 0x00004000 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_BVN_DISC_INT_SHIFT 14 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: BVN_TRIG_INT [13:13] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_BVN_TRIG_INT_MASK 0x00002000 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_BVN_TRIG_INT_SHIFT 13 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: BVN_DISC_1_INT [12:12] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_BVN_DISC_1_INT_MASK 0x00001000 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_BVN_DISC_1_INT_SHIFT 12 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: BVN_TRIG_1_INT [11:11] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_BVN_TRIG_1_INT_MASK 0x00000800 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_BVN_TRIG_1_INT_SHIFT 11 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: BVN_TRIG_2_INT [10:10] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_BVN_TRIG_2_INT_MASK 0x00000400 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_BVN_TRIG_2_INT_SHIFT 10 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: DMA_DONE_5_INT [09:09] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_DMA_DONE_5_INT_MASK 0x00000200 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_DMA_DONE_5_INT_SHIFT 9 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: DMA_DONE_4_INT [08:08] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_DMA_DONE_4_INT_MASK 0x00000100 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_DMA_DONE_4_INT_SHIFT 8 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: DMA_DONE_3_INT [07:07] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_DMA_DONE_3_INT_MASK 0x00000080 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_DMA_DONE_3_INT_SHIFT 7 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: DMA_DONE_2_INT [06:06] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_DMA_DONE_2_INT_MASK 0x00000040 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_DMA_DONE_2_INT_SHIFT 6 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: DMA_DONE_1_INT [05:05] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_DMA_DONE_1_INT_MASK 0x00000020 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_DMA_DONE_1_INT_SHIFT 5 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: DMA_DONE_0_INT [04:04] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_DMA_DONE_0_INT_MASK 0x00000010 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_DMA_DONE_0_INT_SHIFT 4 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: UART_RX_INT [03:03] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_UART_RX_INT_MASK 0x00000008 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_UART_RX_INT_SHIFT 3 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: UART_TX_INT [02:02] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_UART_TX_INT_MASK 0x00000004 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_UART_TX_INT_SHIFT 2 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: PRQ_WATER_MARK_INT [01:01] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_PRQ_WATER_MARK_INT_MASK 0x00000002 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_PRQ_WATER_MARK_INT_SHIFT 1 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_INTERRUPTS_STRUCTURE :: WATCH_DOG_INT [00:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_WATCH_DOG_INT_MASK 0x00000001 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_INTERRUPTS_STRUCTURE_WATCH_DOG_INT_SHIFT 0 |
| |
| /*************************************************************************** |
| *FIREPATH_SUPER_INTERRUPTS_STRUCTURE - Firepath Super Interrupts Structure |
| ***************************************************************************/ |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_SUPER_INTERRUPTS_STRUCTURE :: reserved0 [31:08] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_reserved0_MASK 0xffffff00 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_reserved0_SHIFT 8 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_SUPER_INTERRUPTS_STRUCTURE :: UNUSED1 [07:05] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_UNUSED1_MASK 0x000000e0 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_UNUSED1_SHIFT 5 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_SUPER_INTERRUPTS_STRUCTURE :: DBUG_INT [04:04] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_DBUG_INT_MASK 0x00000010 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_DBUG_INT_SHIFT 4 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_SUPER_INTERRUPTS_STRUCTURE :: UART_RX_INT [03:03] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_UART_RX_INT_MASK 0x00000008 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_UART_RX_INT_SHIFT 3 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_SUPER_INTERRUPTS_STRUCTURE :: UART_TX_INT [02:02] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_UART_TX_INT_MASK 0x00000004 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_UART_TX_INT_SHIFT 2 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_SUPER_INTERRUPTS_STRUCTURE :: UNUSED [01:01] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_UNUSED_MASK 0x00000002 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_UNUSED_SHIFT 1 |
| |
| /* RAAGA_REGSET_DSP_ESR_SI :: FIREPATH_SUPER_INTERRUPTS_STRUCTURE :: WATCH_DOG_INT [00:00] */ |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_WATCH_DOG_INT_MASK 0x00000001 |
| #define BCHP_RAAGA_REGSET_DSP_ESR_SI_FIREPATH_SUPER_INTERRUPTS_STRUCTURE_WATCH_DOG_INT_SHIFT 0 |
| |
| /*************************************************************************** |
| *RDC |
| ***************************************************************************/ |
| /*************************************************************************** |
| *RUL - RUL Command. |
| ***************************************************************************/ |
| /* RDC :: RUL :: opcode [31:24] */ |
| #define BCHP_RDC_RUL_opcode_MASK 0xff000000 |
| #define BCHP_RDC_RUL_opcode_SHIFT 24 |
| #define BCHP_RDC_RUL_opcode_NOP 0 |
| #define BCHP_RDC_RUL_opcode_REG_WRITE_IMM 1 |
| #define BCHP_RDC_RUL_opcode_REG_WRITE 2 |
| #define BCHP_RDC_RUL_opcode_REG_READ 3 |
| #define BCHP_RDC_RUL_opcode_LOAD_IMM 4 |
| #define BCHP_RDC_RUL_opcode_WINDOW_WRITE 5 |
| #define BCHP_RDC_RUL_opcode_BLOCK_WRITE 6 |
| #define BCHP_RDC_RUL_opcode_WINDOW_COPY 7 |
| #define BCHP_RDC_RUL_opcode_BLOCK_COPY 8 |
| #define BCHP_RDC_RUL_opcode_WINDOW_TO_BLOCK 9 |
| #define BCHP_RDC_RUL_opcode_BLOCK_TO_WINDOW 10 |
| #define BCHP_RDC_RUL_opcode_AND 11 |
| #define BCHP_RDC_RUL_opcode_AND_IMM 12 |
| #define BCHP_RDC_RUL_opcode_OR 13 |
| #define BCHP_RDC_RUL_opcode_OR_IMM 14 |
| #define BCHP_RDC_RUL_opcode_XOR 15 |
| #define BCHP_RDC_RUL_opcode_XOR_IMM 16 |
| #define BCHP_RDC_RUL_opcode_NOT 17 |
| #define BCHP_RDC_RUL_opcode_ROTATE_RIGHT 18 |
| #define BCHP_RDC_RUL_opcode_SUM 19 |
| #define BCHP_RDC_RUL_opcode_SUM_IMM 20 |
| #define BCHP_RDC_RUL_opcode_COND_SKIP 21 |
| #define BCHP_RDC_RUL_opcode_SKIP 22 |
| #define BCHP_RDC_RUL_opcode_EXIT 23 |
| #define BCHP_RDC_RUL_opcode_WAIT_EOP 24 |
| #define BCHP_RDC_RUL_opcode_PLACEHOLDER 255 |
| |
| /* RDC :: RUL :: reserved0 [23:23] */ |
| #define BCHP_RDC_RUL_reserved0_MASK 0x00800000 |
| #define BCHP_RDC_RUL_reserved0_SHIFT 23 |
| |
| /* union - case rdc_args [22:00] */ |
| /* RDC :: RUL :: rdc_args :: rotation [22:18] */ |
| #define BCHP_RDC_RUL_rdc_args_rotation_MASK 0x007c0000 |
| #define BCHP_RDC_RUL_rdc_args_rotation_SHIFT 18 |
| |
| /* RDC :: RUL :: rdc_args :: src1 [17:12] */ |
| #define BCHP_RDC_RUL_rdc_args_src1_MASK 0x0003f000 |
| #define BCHP_RDC_RUL_rdc_args_src1_SHIFT 12 |
| |
| /* RDC :: RUL :: rdc_args :: src2 [11:06] */ |
| #define BCHP_RDC_RUL_rdc_args_src2_MASK 0x00000fc0 |
| #define BCHP_RDC_RUL_rdc_args_src2_SHIFT 6 |
| |
| /* RDC :: RUL :: rdc_args :: dest [05:00] */ |
| #define BCHP_RDC_RUL_rdc_args_dest_MASK 0x0000003f |
| #define BCHP_RDC_RUL_rdc_args_dest_SHIFT 0 |
| |
| /* union - case reg_args [22:00] */ |
| /* RDC :: RUL :: reg_args :: rotation [22:18] */ |
| #define BCHP_RDC_RUL_reg_args_rotation_MASK 0x007c0000 |
| #define BCHP_RDC_RUL_reg_args_rotation_SHIFT 18 |
| |
| /* RDC :: RUL :: reg_args :: src1 [17:12] */ |
| #define BCHP_RDC_RUL_reg_args_src1_MASK 0x0003f000 |
| #define BCHP_RDC_RUL_reg_args_src1_SHIFT 12 |
| |
| /* RDC :: RUL :: reg_args :: count [11:00] */ |
| #define BCHP_RDC_RUL_reg_args_count_MASK 0x00000fff |
| #define BCHP_RDC_RUL_reg_args_count_SHIFT 0 |
| |
| /* union - case eop_args [22:00] */ |
| /* RDC :: RUL :: eop_args :: reserved0 [22:08] */ |
| #define BCHP_RDC_RUL_eop_args_reserved0_MASK 0x007fff00 |
| #define BCHP_RDC_RUL_eop_args_reserved0_SHIFT 8 |
| |
| /* RDC :: RUL :: eop_args :: eop [07:00] */ |
| #define BCHP_RDC_RUL_eop_args_eop_MASK 0x000000ff |
| #define BCHP_RDC_RUL_eop_args_eop_SHIFT 0 |
| |
| /*************************************************************************** |
| *EOP_ID_256 - EOP_ID |
| ***************************************************************************/ |
| /* RDC :: EOP_ID_256 :: eop_id [255:00] */ |
| #define BCHP_RDC_EOP_ID_256_eop_id_MASK 0x000000000000000000000000000000000000000000000000ffffffffffffffff |
| #define BCHP_RDC_EOP_ID_256_eop_id_SHIFT 0 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_0 0 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_1 1 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_2 2 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_3 3 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_4 4 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_5 5 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_6 6 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_scl_7 7 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_0 8 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_1 9 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_2 10 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_3 11 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_4 12 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_5 13 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_6 14 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_mvp_7 15 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_0 16 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_1 17 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_2 18 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_3 19 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_4 20 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_5 21 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_6 22 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_dnr_7 23 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_0 24 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_1 25 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_2 26 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_3 27 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_4 28 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_5 29 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_lbox_6 30 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_pfa_0 31 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_0 32 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_1 33 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_2 34 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_3 35 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_4 36 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_5 37 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_6 38 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_null_7 39 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_nvp_0 40 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_s3dh_0 41 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_v0_be 42 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_tntd_0 43 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_xsrc_0 44 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_xsrc_1 45 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_0 46 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_1 47 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_0 48 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_1 49 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_2 50 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_3 51 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_4 52 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_5 53 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_6 54 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_7 55 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_8 56 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_9 57 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_10 58 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_11 59 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_12 60 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_fch_13 61 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_2 62 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_f_reserved_3 63 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mfd_0 64 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mfd_1 65 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mfd_2 66 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mfd_3 67 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mfd_4 68 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mfd_5 69 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mfd_6 70 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mfd_7 71 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vfd_0 72 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vfd_1 73 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vfd_2 74 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vfd_3 75 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vfd_4 76 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vfd_5 77 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vfd_6 78 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vfd_7 79 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cap_0 80 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cap_1 81 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cap_2 82 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cap_3 83 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cap_4 84 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cap_5 85 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cap_6 86 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cap_7 87 |
| #define BCHP_RDC_EOP_ID_256_eop_id_gfd_0 88 |
| #define BCHP_RDC_EOP_ID_256_eop_id_gfd_1 89 |
| #define BCHP_RDC_EOP_ID_256_eop_id_gfd_2 90 |
| #define BCHP_RDC_EOP_ID_256_eop_id_gfd_3 91 |
| #define BCHP_RDC_EOP_ID_256_eop_id_gfd_4 92 |
| #define BCHP_RDC_EOP_ID_256_eop_id_gfd_5 93 |
| #define BCHP_RDC_EOP_ID_256_eop_id_gfd_6 94 |
| #define BCHP_RDC_EOP_ID_256_eop_id_gfd_7 95 |
| #define BCHP_RDC_EOP_ID_256_eop_id_scl_0 96 |
| #define BCHP_RDC_EOP_ID_256_eop_id_scl_1 97 |
| #define BCHP_RDC_EOP_ID_256_eop_id_scl_2 98 |
| #define BCHP_RDC_EOP_ID_256_eop_id_scl_3 99 |
| #define BCHP_RDC_EOP_ID_256_eop_id_scl_4 100 |
| #define BCHP_RDC_EOP_ID_256_eop_id_scl_5 101 |
| #define BCHP_RDC_EOP_ID_256_eop_id_scl_6 102 |
| #define BCHP_RDC_EOP_ID_256_eop_id_scl_7 103 |
| #define BCHP_RDC_EOP_ID_256_eop_id_xsrc_0 104 |
| #define BCHP_RDC_EOP_ID_256_eop_id_xsrc_1 105 |
| #define BCHP_RDC_EOP_ID_256_eop_id_xsrc_2 106 |
| #define BCHP_RDC_EOP_ID_256_eop_id_xsrc_3 107 |
| #define BCHP_RDC_EOP_ID_256_eop_id_xsrc_4 108 |
| #define BCHP_RDC_EOP_ID_256_eop_id_xsrc_5 109 |
| #define BCHP_RDC_EOP_ID_256_eop_id_xsrc_6 110 |
| #define BCHP_RDC_EOP_ID_256_eop_id_xsrc_7 111 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mvp_0 112 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mvp_1 113 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mvp_2 114 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mvp_3 115 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mvp_4 116 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mvp_5 117 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mvp_6 118 |
| #define BCHP_RDC_EOP_ID_256_eop_id_mvp_7 119 |
| #define BCHP_RDC_EOP_ID_256_eop_id_dnr_0 120 |
| #define BCHP_RDC_EOP_ID_256_eop_id_dnr_1 121 |
| #define BCHP_RDC_EOP_ID_256_eop_id_dnr_2 122 |
| #define BCHP_RDC_EOP_ID_256_eop_id_dnr_3 123 |
| #define BCHP_RDC_EOP_ID_256_eop_id_dnr_4 124 |
| #define BCHP_RDC_EOP_ID_256_eop_id_dnr_5 125 |
| #define BCHP_RDC_EOP_ID_256_eop_id_dnr_6 126 |
| #define BCHP_RDC_EOP_ID_256_eop_id_dnr_7 127 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cmp_0 128 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cmp_1 129 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cmp_2 130 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cmp_3 131 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cmp_4 132 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cmp_5 133 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cmp_6 134 |
| #define BCHP_RDC_EOP_ID_256_eop_id_cmp_7 135 |
| #define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_0 136 |
| #define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_1 137 |
| #define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_2 138 |
| #define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_3 139 |
| #define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_4 140 |
| #define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_5 141 |
| #define BCHP_RDC_EOP_ID_256_eop_id_hd_dvi_6 142 |
| #define BCHP_RDC_EOP_ID_256_eop_id_tpg_0 143 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vec_0 144 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vec_1 145 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vec_2 146 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vec_3 147 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vec_4 148 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vec_5 149 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vec_6 150 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vec_7 151 |
| #define BCHP_RDC_EOP_ID_256_eop_id_lbox_0 152 |
| #define BCHP_RDC_EOP_ID_256_eop_id_lbox_1 153 |
| #define BCHP_RDC_EOP_ID_256_eop_id_lbox_2 154 |
| #define BCHP_RDC_EOP_ID_256_eop_id_lbox_3 155 |
| #define BCHP_RDC_EOP_ID_256_eop_id_lbox_4 156 |
| #define BCHP_RDC_EOP_ID_256_eop_id_lbox_5 157 |
| #define BCHP_RDC_EOP_ID_256_eop_id_lbox_6 158 |
| #define BCHP_RDC_EOP_ID_256_eop_id_pfa_0 159 |
| #define BCHP_RDC_EOP_ID_256_eop_id_crc_0 160 |
| #define BCHP_RDC_EOP_ID_256_eop_id_crc_1 161 |
| #define BCHP_RDC_EOP_ID_256_eop_id_crc_2 162 |
| #define BCHP_RDC_EOP_ID_256_eop_id_crc_3 163 |
| #define BCHP_RDC_EOP_ID_256_eop_id_hist_0 164 |
| #define BCHP_RDC_EOP_ID_256_eop_id_hist_1 165 |
| #define BCHP_RDC_EOP_ID_256_eop_id_psm_0 166 |
| #define BCHP_RDC_EOP_ID_256_eop_id_plm_0 167 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_0 168 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_1 169 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_2 170 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_3 171 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_4 172 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_5 173 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_6 174 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cap_7 175 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_0 176 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_1 177 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_2 178 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_crc_3 179 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_0 180 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_hist_1 181 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_psm_0 182 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_plm_0 183 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v0 184 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v0 185 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v0 186 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v0 187 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v0 188 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v0 189 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v0 190 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v0 191 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_0_v1 192 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_1_v1 193 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_2_v1 194 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_3_v1 195 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_4_v1 196 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_5_v1 197 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_6_v1 198 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_cmp_7_v1 199 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_0 200 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_1 201 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_2 202 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_3 203 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_4 204 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_5 205 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_6 206 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_null_7 207 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_b3dc_0 208 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_frc_0 209 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_0 210 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_1 211 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_2 212 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_3 213 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_4 214 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_5 215 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_0 216 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_1 217 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_2 218 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_3 219 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_4 220 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_5 221 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_6 222 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_7 223 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_8 224 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_9 225 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_10 226 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_11 227 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_12 228 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_13 229 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_loopback_14 230 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vnet_b_reserved_9 231 |
| #define BCHP_RDC_EOP_ID_256_eop_id_nvp_0 232 |
| #define BCHP_RDC_EOP_ID_256_eop_id_s3dh_0 233 |
| #define BCHP_RDC_EOP_ID_256_eop_id_v0_be 234 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_0 235 |
| #define BCHP_RDC_EOP_ID_256_eop_id_gfd_0_1 236 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_2 237 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_3 238 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_4 239 |
| #define BCHP_RDC_EOP_ID_256_eop_id_b3dc_0 240 |
| #define BCHP_RDC_EOP_ID_256_eop_id_frc_0 241 |
| #define BCHP_RDC_EOP_ID_256_eop_id_pdpf_0 242 |
| #define BCHP_RDC_EOP_ID_256_eop_id_pdpb_0 243 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_5 244 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_6 245 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_7 246 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_8 247 |
| #define BCHP_RDC_EOP_ID_256_eop_id_tntd_0 248 |
| #define BCHP_RDC_EOP_ID_256_eop_id_vec_hddvi_0_passthr 249 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_11 250 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_12 251 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_13 252 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_14 253 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_15 254 |
| #define BCHP_RDC_EOP_ID_256_eop_id_reserved_16 255 |
| |
| /*************************************************************************** |
| *SPDIF_RCVR_CTRL |
| ***************************************************************************/ |
| /*************************************************************************** |
| *ABSTRACT_INTERRUPT_HANDLING - Interrupt Handling |
| ***************************************************************************/ |
| /* SPDIF_RCVR_CTRL :: ABSTRACT_INTERRUPT_HANDLING :: MORE_INFORMATION [31:00] */ |
| #define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_MASK 0xffffffff |
| #define BCHP_SPDIF_RCVR_CTRL_ABSTRACT_INTERRUPT_HANDLING_MORE_INFORMATION_SHIFT 0 |
| |
| /*************************************************************************** |
| *XPT_RAVE |
| ***************************************************************************/ |
| /*************************************************************************** |
| *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEC_PES_LAYER_SELECTION - PES Layer Selection |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */ |
| #define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0 |
| |
| /*************************************************************************** |
| *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio |
| ***************************************************************************/ |
| /* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */ |
| #define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff |
| #define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0 |
| |
| #endif /* #ifndef BCHP_COMMON_H__ */ |
| |
| /* End of File */ |
