| /**************************************************************************** |
| * Copyright (c) 1999-2014, Broadcom Corporation |
| * All Rights Reserved |
| * Confidential Property of Broadcom Corporation |
| * |
| * |
| * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
| * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
| * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Wed Jun 10 03:09:37 2015 |
| * Full Compile MD5 Checksum e8bde4108283f67d401938287dbb6bde |
| * (minus title and desc) |
| * MD5 Checksum 56f0f944fbd407545cd964e7b4e7f7b0 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB.pm 15517 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_SWITCH_CORE_H__ |
| #define BCHP_SWITCH_CORE_H__ |
| |
| /*************************************************************************** |
| *SWITCH_CORE |
| ***************************************************************************/ |
| #define BCHP_SWITCH_CORE_G_PCTL_P0 0x04e00000 /* [RW] Port 0 Control Register */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P1 0x04e00004 /* [RW] Port 1 Control Register */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P2 0x04e00008 /* [RW] Port 2 Control Register */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P3 0x04e0000c /* [RW] Port 3 Control Register */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P4 0x04e00010 /* [RW] Port 4 Control Register */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P5 0x04e00014 /* [RW] Port 5 Control Register */ |
| #define BCHP_SWITCH_CORE_CTL_P7 0x04e0001c /* [RW] Port 7 Control Register */ |
| #define BCHP_SWITCH_CORE_CTL_IMP 0x04e00020 /* [RW] IMP Port(Port 8) Control Register */ |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL 0x04e00028 /* [RW] RX Global Control register(Not2Release) */ |
| #define BCHP_SWITCH_CORE_SWMODE 0x04e0002c /* [RW] Switch Mode Register */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP 0x04e00038 /* [RW] IMP Port(Port 8) States Override Register */ |
| #define BCHP_SWITCH_CORE_DEBUG_REG 0x04e00078 /* [RW] Debug Control Register(Not2Release) */ |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG 0x04e0007c /* [RW] Removed Pins Debug Register(Not2Release) */ |
| #define BCHP_SWITCH_CORE_NEW_CTRL 0x04e00084 /* [RW] New Control Register */ |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL 0x04e00088 /* [RW] Switch Control Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_PROTECTED_SEL 0x04e00090 /* [RW] Protected Port Select Register */ |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL 0x04e00098 /* [RW] WAN Port select Register */ |
| #define BCHP_SWITCH_CORE_PAUSE_CAP 0x04e000a0 /* [RW] PAUSE Capability Register */ |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL 0x04e000bc /* [RW] Reserved Multicast Register */ |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE 0x04e000c4 /* [RW] TxQ Flush Mode Control Register(Not2Release) */ |
| #define BCHP_SWITCH_CORE_ULF_DROP_MAP 0x04e000c8 /* [RW] Unicast Lookup Failed Forward Map Register */ |
| #define BCHP_SWITCH_CORE_MLF_DROP_MAP 0x04e000d0 /* [RW] Multicast Lookup Failed Forward Map Register */ |
| #define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP 0x04e000d8 /* [RW] IPMC Forward Map Register */ |
| #define BCHP_SWITCH_CORE_RX_PAUSE_PASS 0x04e000e0 /* [RW] Pause pass Through for RX Register */ |
| #define BCHP_SWITCH_CORE_TX_PAUSE_PASS 0x04e000e8 /* [RW] Pause pass Through for TX Register */ |
| #define BCHP_SWITCH_CORE_DIS_LEARN 0x04e000f0 /* [RW] Disable Learning Register */ |
| #define BCHP_SWITCH_CORE_SFT_LRN_CTL 0x04e000f8 /* [RW] Software Learning Control */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1 0x04e00100 /* [RW] Low Power Expansion I Register */ |
| #define BCHP_SWITCH_CORE_CTLREG_REG_SPARE 0x04e00150 /* [RW] Spare Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0 0x04e00160 /* [RW] Port 0 GMII Port States Override Register */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1 0x04e00164 /* [RW] Port 1 GMII Port States Override Register */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2 0x04e00168 /* [RW] Port 2 GMII Port States Override Register */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3 0x04e0016c /* [RW] Port 3 GMII Port States Override Register */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4 0x04e00170 /* [RW] Port 4 GMII Port States Override Register */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5 0x04e00174 /* [RW] Port 5 GMII Port States Override Register */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7 0x04e0017c /* [RW] Port 7 GMII Port States Override Register */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL 0x04e001e4 /* [RW] Watch Dog Control Register */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT1 0x04e001e8 /* [RO] Watch Dog Report 1 Register(Not2Release) */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT2 0x04e001f0 /* [RO] Watch Dog Report 2 Register(Not2Release) */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT3 0x04e001f8 /* [RO] Watch Dog Report 3 Register(Not2Release) */ |
| #define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL 0x04e00200 /* [RW] Pause Frame Detection Control Register */ |
| #define BCHP_SWITCH_CORE_PAUSE_ST_ADDR 0x04e00204 /* [RW] PAUSE Frame DA Address */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL 0x04e00220 /* [RW] Fast Ageing Control Register */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_PORT 0x04e00224 /* [RW] Fast Ageing Port Control Register */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_VID 0x04e00228 /* [RW] Fast Ageing VID Control Register */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL 0x04e00378 /* [RW] LOW Power Control Register */ |
| #define BCHP_SWITCH_CORE_TCAM_CTRL 0x04e003a0 /* [RW] TCAM Control Register */ |
| #define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS 0x04e003a8 /* [RO] TCAM Checksum Status Register */ |
| #define BCHP_SWITCH_CORE_LNKSTS 0x04e00400 /* [RO] Link Status Summary Register */ |
| #define BCHP_SWITCH_CORE_LNKSTSCHG 0x04e00408 /* [RO] Link Status Change Register */ |
| #define BCHP_SWITCH_CORE_SPDSTS 0x04e00410 /* [RO] Port Speed Summary Register */ |
| #define BCHP_SWITCH_CORE_DUPSTS 0x04e00420 /* [RO] Duplex status Summary Register */ |
| #define BCHP_SWITCH_CORE_PAUSESTS 0x04e00428 /* [RO] Pause Status Summary Register */ |
| #define BCHP_SWITCH_CORE_SRCADRCHG 0x04e00438 /* [RO] Source Address Change Register */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P0 0x04e00440 /* [RO] Port 0 Last Source Address */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P1 0x04e00458 /* [RO] Port 1 Last Source Address */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P2 0x04e00470 /* [RO] Port 2 Last Source Address */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P3 0x04e00488 /* [RO] Port 3 Last Source Address */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P4 0x04e004a0 /* [RO] Port 4 Last Source Address */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P5 0x04e004b8 /* [RO] Port 5 Last Source Address */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P7 0x04e004e8 /* [RO] Port 7 Last Source Address */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P8 0x04e00500 /* [RO] Port 8 Last Source Address */ |
| #define BCHP_SWITCH_CORE_BIST_STS0 0x04e00518 /* [RO] BIST Status Register 0 */ |
| #define BCHP_SWITCH_CORE_BIST_STS1 0x04e00530 /* [RO] BIST Status Register 1 */ |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0 0x04e00540 /* [RO] PBPTRFIFO Status Register 0(Not2Release) */ |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1 0x04e00558 /* [RO] PBPTRFIFO Status Register 1(Not2Release) */ |
| #define BCHP_SWITCH_CORE_STRAP_PIN_STATUS 0x04e005c0 /* [RO] Strap Pin Status Register */ |
| #define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE 0x04e00600 /* [RO] Direct Input Control Value Register */ |
| #define BCHP_SWITCH_CORE_RESET_STATUS 0x04e00640 /* [RO] Reset Status Register */ |
| #define BCHP_SWITCH_CORE_ENG_DET_STS 0x04e00648 /* [RO] PHY Energy Detect Status Register */ |
| #define BCHP_SWITCH_CORE_ENG_DET_STS_CHG 0x04e0064c /* [RO] PHY Energy Detect Status Change Register */ |
| #define BCHP_SWITCH_CORE_STREG_REG_SPARE0 0x04e00680 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_STREG_REG_SPARE1 0x04e00690 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_GMNGCFG 0x04e00800 /* [RW] Global Management Configuration Register */ |
| #define BCHP_SWITCH_CORE_IMP0_PRT_ID 0x04e00804 /* [RO] IMP/IMP0 Port ID Register */ |
| #define BCHP_SWITCH_CORE_IMP1_PRT_ID 0x04e00808 /* [RO] IMP1 Port ID Register */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL 0x04e0080c /* [RW] BRCM Header Control Register */ |
| #define BCHP_SWITCH_CORE_SPTAGT 0x04e00818 /* [RW] Aging Time Control Register */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2 0x04e00828 /* [RW] BRCM Header Control 2 Register */ |
| #define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL 0x04e00830 /* [RW] IPG Shrink Control Register */ |
| #define BCHP_SWITCH_CORE_MIRCAPCTL 0x04e00840 /* [RW] Mirror Capture Control Register */ |
| #define BCHP_SWITCH_CORE_IGMIRCTL 0x04e00848 /* [RW] Ingress Mirror Control Register */ |
| #define BCHP_SWITCH_CORE_IGMIRDIV 0x04e00850 /* [RW] Ingress Mirror Divider Register */ |
| #define BCHP_SWITCH_CORE_IGMIRMAC 0x04e00858 /* [RW] Ingress Mirror Mac Address Register */ |
| #define BCHP_SWITCH_CORE_EGMIRCTL 0x04e00870 /* [RW] Egress Mirror Control Register */ |
| #define BCHP_SWITCH_CORE_EGMIRDIV 0x04e00878 /* [RW] Egress Mirror Divider Register */ |
| #define BCHP_SWITCH_CORE_EGMIRMAC 0x04e00880 /* [RW] Egress Mirror MAC Address Register */ |
| #define BCHP_SWITCH_CORE_MODEL_ID 0x04e008c0 /* [RO] Model ID Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_CHIP_REVID 0x04e00900 /* [RO] Chip Version ID Register */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL 0x04e00940 /* [RW] High Level Protocol Control Register */ |
| #define BCHP_SWITCH_CORE_RST_MIB_CNT_EN 0x04e00950 /* [RW] Reset MIB Counter Enable Register */ |
| #define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA 0x04e00960 /* [RW] IPG Shrink 2G Workaround Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS 0x04e00980 /* [RW] Broadcom Header RX Disable Register */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS 0x04e00988 /* [RW] Broadcom Header TX Disable Register */ |
| #define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0 0x04e009c0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1 0x04e009d0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_INT_STS 0x04e00c00 /* [RW] External Host Raw Interrupt Status Register */ |
| #define BCHP_SWITCH_CORE_INT_EN 0x04e00c20 /* [RW] External Host Interrupt Enable Register */ |
| #define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP 0x04e00c40 /* [RW] IMP Port(port 8) Sleep Timer Register */ |
| #define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER 0x04e00c48 /* [RW] Port 7 Sleep Timer Register */ |
| #define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER 0x04e00c50 /* [RW] WAN Port Sleep Timer Register */ |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS 0x04e00c60 /* [RO] Port Sleep Status Register */ |
| #define BCHP_SWITCH_CORE_INT_TRIGGER 0x04e00c80 /* [RW] Interrupt Trigger Register */ |
| #define BCHP_SWITCH_CORE_LINK_STS_INT_EN 0x04e00c90 /* [RW] Link Status Interrupt Enable Register */ |
| #define BCHP_SWITCH_CORE_ENG_DET_INT_EN 0x04e00ca0 /* [RW] Energy Detection Interrupt Enable Register */ |
| #define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN 0x04e00ca8 /* [RW] LPI Status Change Interrupt Enable Register */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS 0x04e00d80 /* [RW] Memory ECC Double-Error-Detection Interrupt Status (Not2Release) */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN 0x04e00d88 /* [RW] Memory ECC Double-Error-Detection Interrupt Enable (Not2Release) */ |
| #define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS 0x04e00d90 /* [RW] Per Port EVT Table ECC Double-Error-Detection Error Status (Not2Release) */ |
| #define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS 0x04e00d98 /* [RW] Per Port MIB Counter ECC Double-Error-Detection Error Status (Not2Release) */ |
| #define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS 0x04e00da0 /* [RW] Per Port TXQ ECC Double-Error-Detection Error Status (Not2Release) */ |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL 0x04e00dc0 /* [RW] Probe Bus Control Registers(Not2Release) */ |
| #define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL 0x04e00dd0 /* [RW] MDC Extend Clock Control Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN 0x04e00e00 /* [RW] PPPoE Session Packet Parsing Enable Register */ |
| #define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0 0x04e00e40 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1 0x04e00e50 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_GARLCFG 0x04e01000 /* [RW] Global ARL Configuration Register */ |
| #define BCHP_SWITCH_CORE_BPDU_MCADDR 0x04e01010 /* [RW] BPDU Multicast Address Register */ |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL 0x04e01038 /* [RW] Multiport Control Register */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR0 0x04e01040 /* [RW] Multiport Address 0 Register (Default for TS) */ |
| #define BCHP_SWITCH_CORE_MPORTVEC0 0x04e01060 /* [RW] Multiport Vector 0 Register */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR1 0x04e01080 /* [RW] Multiport Address 1 Register */ |
| #define BCHP_SWITCH_CORE_MPORTVEC1 0x04e010a0 /* [RW] Multiport Vector 1 Register */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR2 0x04e010c0 /* [RW] Multiport Address 2 Register */ |
| #define BCHP_SWITCH_CORE_MPORTVEC2 0x04e010e0 /* [RW] Multiport Vector 2 Register */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR3 0x04e01100 /* [RW] Multiport Address 3 Register */ |
| #define BCHP_SWITCH_CORE_MPORTVEC3 0x04e01120 /* [RW] Multiport Vector 3 Register */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR4 0x04e01140 /* [RW] Multiport Address 4 Register */ |
| #define BCHP_SWITCH_CORE_MPORTVEC4 0x04e01160 /* [RW] Multiport Vector 4 Register */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR5 0x04e01180 /* [RW] Multiport Address 5 Register */ |
| #define BCHP_SWITCH_CORE_MPORTVEC5 0x04e011a0 /* [RW] Multiport Vector 5 Register */ |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR 0x04e011c0 /* [RW] ARL Bin Full Counter Register */ |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD 0x04e011d0 /* [RW] ARL Biin Full Forward Enable Register */ |
| #define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0 0x04e01200 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1 0x04e01210 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL 0x04e01400 /* [RW] ARL Read/Write Control Register */ |
| #define BCHP_SWITCH_CORE_ARLA_MAC 0x04e01408 /* [RW] MAC Address Index Register */ |
| #define BCHP_SWITCH_CORE_ARLA_VID 0x04e01420 /* [RW] VID Index Register */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0 0x04e01440 /* [RW] ARL MAC/VID Entry 0 Register */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0 0x04e01460 /* [RW] ARL FWD Entry 0 Register */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1 0x04e01480 /* [RW] ARL MAC/VID Entry 1 Register */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1 0x04e014a0 /* [RW] ARL FWD Entry 1 Register */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2 0x04e014c0 /* [RW] ARL MAC/VID Entry 2 Register */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2 0x04e014e0 /* [RW] ARL FWD Entry 2 Register */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3 0x04e01500 /* [RW] ARL MAC/VID Entry 3 Register */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3 0x04e01520 /* [RW] ARL FWD Entry 3 Register */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_CTL 0x04e01540 /* [RW] ARL Search Control Register */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_ADR 0x04e01544 /* [RO] ARL Search Address Register */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID 0x04e01580 /* [RO] ARL Search MAC/VID Result 0 Register */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0 0x04e015a0 /* [RO] ARL Search Result 0 Register */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID 0x04e015c0 /* [RO] ARL Search MAC/VID Result 1 Register */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1 0x04e015e0 /* [RO] ARL Search Result 1 Register */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL 0x04e01600 /* [RW] VTBL Read/Write/Clear Control Register */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR 0x04e01604 /* [RW] VTBL Address Index Register */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY 0x04e0160c /* [RW] VTBL Entry Register */ |
| #define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0 0x04e01640 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1 0x04e01650 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_MEM_CTRL 0x04e02000 /* [RW] Memory Debug Control Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_ADDR 0x04e02004 /* [RW] Memory Debug Address Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0 0x04e02020 /* [RW] Memory Debug Data 0_0 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1 0x04e02040 /* [RW] Memory Debug Data 0_1 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0 0x04e02048 /* [RW] Memory Debug Data 1_0 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1 0x04e02068 /* [RW] Memory Debug Data 1_1 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_ADDR 0x04e02080 /* [RW] Frame Memory Address Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA0 0x04e020c0 /* [RW] Frame Memory Data 1st Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA1 0x04e020e0 /* [RW] Frame Memory Data 2st Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA2 0x04e02100 /* [RW] Frame Memory Data 3st Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA3 0x04e02120 /* [RW] Frame Memory Data 4th Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_BTM_DATA0 0x04e02140 /* [RO] Buffer Tag Memory Register 0Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_BTM_DATA1 0x04e02160 /* [RO] Buffer Tag Memory Register 1Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_BFC_ADDR 0x04e02180 /* [RW] Buffer Control Memory Address Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_BFC_DATA 0x04e02188 /* [RO] Buffer Control Memory Data Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL 0x04e021c0 /* [RW] PRS_FIFO Debug Control Register(Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA 0x04e021c4 /* [RO] PRS_FIFO Debug Data Register(Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_REG_SPARE0 0x04e022a0 /* [RW] Spare 0 Register (Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_REG_SPARE1 0x04e022b0 /* [RW] Spare 1 Register (Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL 0x04e022c0 /* [RW] Memory Misc Control Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0 0x04e022d0 /* [RW] Memory Test Control 0 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1 0x04e022e0 /* [RW] Memory Test Control 1 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2 0x04e022f0 /* [RW] Memory Test Control 2 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3 0x04e02300 /* [RW] Memory Test Control 3 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4 0x04e02310 /* [RW] Memory Test Control 4 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL5 0x04e02320 /* [RW] Memory Test Control 5 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL 0x04e02380 /* [RW] Memory PSM_VDD Pin Control registerNot2Release */ |
| #define BCHP_SWITCH_CORE_PORT0_DEBUG 0x04e02400 /* [RO] PORT0 DEBUGNot2Release */ |
| #define BCHP_SWITCH_CORE_PORT1_DEBUG 0x04e02440 /* [RO] PORT1 DEBUGNot2Release */ |
| #define BCHP_SWITCH_CORE_PORT2_DEBUG 0x04e02480 /* [RO] PORT2 DEBUGNot2Release */ |
| #define BCHP_SWITCH_CORE_PORT3_DEBUG 0x04e024c0 /* [RO] PORT3 DEBUGNot2Release */ |
| #define BCHP_SWITCH_CORE_PORT4_DEBUG 0x04e02500 /* [RO] PORT4 DEBUGNot2Release */ |
| #define BCHP_SWITCH_CORE_PORT5_DEBUG 0x04e02540 /* [RO] PORT5 DEBUGNot2Release */ |
| #define BCHP_SWITCH_CORE_PORT6_DEBUG 0x04e02580 /* [RO] PORT6 DEBUGNot2Release */ |
| #define BCHP_SWITCH_CORE_PORT7_DEBUG 0x04e025c0 /* [RO] PORT7 DEBUGNot2Release */ |
| #define BCHP_SWITCH_CORE_PORT8_DEBUG 0x04e02600 /* [RO] PORT8 DEBUGNot2Release */ |
| #define BCHP_SWITCH_CORE_FC_DIAG_CTRL 0x04e02800 /* [RW] Flowcon Diagnosis Control Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_CTRL_MODE 0x04e02808 /* [RW] Flow Control Mode Selection Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_CTRL_PORT 0x04e0280c /* [RW] Flow Control Port Selection Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN 0x04e02810 /* [RW] OOB Pause Signal Enable Register (Release2Customer)Not2Release */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_MAX 0x04e02840 /* [RW] MAX Quantum Pause Time Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_MIN 0x04e02848 /* [RW] MIN Quantum Pause Time Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD 0x04e02850 /* [RW] Quantum Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD 0x04e02858 /* [RW] Quantum Pause Update Period Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT 0x04e02860 /* [RW] Default Quantum Pause Time Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL 0x04e02868 /* [RW] Multicast Drop Control Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL 0x04e02870 /* [RW] Pause/Drop Control Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF 0x04e02878 /* [RW] TXQ Pause Off Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_RX_RUNOFF 0x04e02880 /* [RW] RX-Based Run-Off Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_RX_RSV_THD 0x04e02888 /* [RW] RX-Based Reserved Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_RX_HYST_THD 0x04e02890 /* [RW] RX-Based Hysteresis Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_RX_MAX_PTR 0x04e02898 /* [RW] RX-Based Maximum Buffer Remap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG 0x04e028a0 /* [RW] Flow Control Spare Zero Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG 0x04e028a8 /* [RW] Flow Control Spare One Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q0 0x04e028c0 /* [RO] Monitored TXQ 0 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q1 0x04e028c8 /* [RO] Monitored TXQ 1 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q2 0x04e028d0 /* [RO] Monitored TXQ 2 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q3 0x04e028d8 /* [RO] Monitored TXQ 3 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q4 0x04e028e0 /* [RO] Monitored TXQ 4 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q5 0x04e028e8 /* [RO] Monitored TXQ 5 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q6 0x04e028f0 /* [RO] Monitored TXQ 6 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q7 0x04e028f8 /* [RO] Monitored TXQ 7 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0 0x04e02900 /* [RO] Peak TXQ 0 Counter Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1 0x04e02908 /* [RO] Peak TXQ 1 Counter Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2 0x04e02910 /* [RO] Peak TXQ 2 Counter Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3 0x04e02918 /* [RO] Peak TXQ 3 Counter Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4 0x04e02920 /* [RO] Peak TXQ 4 Counter Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5 0x04e02928 /* [RO] Peak TXQ 5 Counter Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6 0x04e02930 /* [RO] Peak TXQ 6 Counter Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7 0x04e02938 /* [RO] Peak TXQ 7 Counter Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED 0x04e02940 /* [RO] Peak Total Used Count Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_USED 0x04e02948 /* [RO] Total Used Count Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT 0x04e02950 /* [RO] Peak RX Counter Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LINK_PORTMAP 0x04e02958 /* [RO] PHY Link Information Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP 0x04e02960 /* [RO] Giga Speed Information Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P0 0x04e02980 /* [RO] Port 0 Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P1 0x04e02988 /* [RO] Port 1 Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P2 0x04e02990 /* [RO] Port 2 Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P3 0x04e02998 /* [RO] Port 3 Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P4 0x04e029a0 /* [RO] Port 4 Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P5 0x04e029a8 /* [RO] Port 5 Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7 0x04e029b8 /* [RO] Port 7 Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8 0x04e029c0 /* [RO] Port 8 Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_HIS 0x04e029e0 /* [RO] Pause History Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS 0x04e029e8 /* [RO] TX Quantum Pause History Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS 0x04e029f0 /* [RO] RX Based Pause History Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS 0x04e029f8 /* [RO] RX Buffer Error History Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0 0x04e02a00 /* [RO] Port 0 TXQ Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1 0x04e02a08 /* [RO] Port 1 TXQ Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2 0x04e02a10 /* [RO] Port 2 TXQ Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3 0x04e02a18 /* [RO] Port 3 TXQ Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4 0x04e02a20 /* [RO] Port 4 TXQ Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5 0x04e02a28 /* [RO] Port 5 TXQ Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7 0x04e02a38 /* [RO] Port 7 TXQ Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8 0x04e02a40 /* [RO] Port 8 TXQ Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0 0x04e02a68 /* [RO] Port 0 Total Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1 0x04e02a70 /* [RO] Port 1 Total Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2 0x04e02a78 /* [RO] Port 2 Total Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3 0x04e02a80 /* [RO] Port 3 Total Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4 0x04e02a88 /* [RO] Port 4 Total Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5 0x04e02a90 /* [RO] Port 5 Total Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7 0x04e02aa0 /* [RO] Port 7 Total Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8 0x04e02aa8 /* [RO] Port 8 Total Congested PortMap Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0 0x04e02c00 /* [RW] LAN Port Queue 0 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1 0x04e02c08 /* [RW] LAN Port Queue 1 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2 0x04e02c10 /* [RW] LAN Port Queue 2 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3 0x04e02c18 /* [RW] LAN Port Queue 3 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4 0x04e02c20 /* [RW] LAN Port Queue 4 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5 0x04e02c28 /* [RW] LAN Port Queue 5 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6 0x04e02c30 /* [RW] LAN Port Queue 6 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7 0x04e02c38 /* [RW] LAN Port Queue 7 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0 0x04e02c40 /* [RW] LAN Port Queue 0 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1 0x04e02c48 /* [RW] LAN Port Queue 1 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2 0x04e02c50 /* [RW] LAN Port Queue 2 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3 0x04e02c58 /* [RW] LAN Port Queue 3 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4 0x04e02c60 /* [RW] LAN Port Queue 4 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5 0x04e02c68 /* [RW] LAN Port Queue 5 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6 0x04e02c70 /* [RW] LAN Port Queue 6 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7 0x04e02c78 /* [RW] LAN Port Queue 7 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0 0x04e02c80 /* [RW] LAN Port Queue 0 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1 0x04e02c88 /* [RW] LAN Port Queue 1 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2 0x04e02c90 /* [RW] LAN Port Queue 2 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3 0x04e02c98 /* [RW] LAN Port Queue 3 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4 0x04e02ca0 /* [RW] LAN Port Queue 4 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5 0x04e02ca8 /* [RW] LAN Port Queue 5 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6 0x04e02cb0 /* [RW] LAN Port Queue 6 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7 0x04e02cb8 /* [RW] LAN Port Queue 7 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0 0x04e02cc0 /* [RW] LAN Port Queue 0 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1 0x04e02cc8 /* [RW] LAN Port Queue 1 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2 0x04e02cd0 /* [RW] LAN Port Queue 2 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3 0x04e02cd8 /* [RW] LAN Port Queue 3 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4 0x04e02ce0 /* [RW] LAN Port Queue 4 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5 0x04e02ce8 /* [RW] LAN Port Queue 5 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6 0x04e02cf0 /* [RW] LAN Port Queue 6 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7 0x04e02cf8 /* [RW] LAN Port Queue 7 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0 0x04e02d00 /* [RW] LAN Port Queue 0 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1 0x04e02d08 /* [RW] LAN Port Queue 1 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2 0x04e02d10 /* [RW] LAN Port Queue 2 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3 0x04e02d18 /* [RW] LAN Port Queue 3 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4 0x04e02d20 /* [RW] LAN Port Queue 4 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5 0x04e02d28 /* [RW] LAN Port Queue 5 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6 0x04e02d30 /* [RW] LAN Port Queue 6 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7 0x04e02d38 /* [RW] LAN Port Queue 7 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0 0x04e02d40 /* [RW] LAN Port Queue 0 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1 0x04e02d48 /* [RW] LAN Port Queue 1 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2 0x04e02d50 /* [RW] LAN Port Queue 2 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3 0x04e02d58 /* [RW] LAN Port Queue 3 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4 0x04e02d60 /* [RW] LAN Port Queue 4 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5 0x04e02d68 /* [RW] LAN Port Queue 5 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6 0x04e02d70 /* [RW] LAN Port Queue 6 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7 0x04e02d78 /* [RW] LAN Port Queue 7 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0 0x04e02d80 /* [RW] LAN Port Queue 0 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1 0x04e02d88 /* [RW] LAN Port Queue 1 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2 0x04e02d90 /* [RW] LAN Port Queue 2 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3 0x04e02d98 /* [RW] LAN Port Queue 3 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4 0x04e02da0 /* [RW] LAN Port Queue 4 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5 0x04e02da8 /* [RW] LAN Port Queue 5 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6 0x04e02db0 /* [RW] LAN Port Queue 6 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7 0x04e02db8 /* [RW] LAN Port Queue 7 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_P0_DEBUG_MUX 0x04e03000 /* [RO] P0 DEBUG MUXNot2Release */ |
| #define BCHP_SWITCH_CORE_P1_DEBUG_MUX 0x04e03010 /* [RO] P1 DEBUG MUXNot2Release */ |
| #define BCHP_SWITCH_CORE_P2_DEBUG_MUX 0x04e03020 /* [RO] P2 DEBUG MUXNot2Release */ |
| #define BCHP_SWITCH_CORE_P3_DEBUG_MUX 0x04e03030 /* [RO] P3 DEBUG MUXNot2Release */ |
| #define BCHP_SWITCH_CORE_P4_DEBUG_MUX 0x04e03040 /* [RO] P4 DEBUG MUXNot2Release */ |
| #define BCHP_SWITCH_CORE_P5_DEBUG_MUX 0x04e03050 /* [RO] P5 DEBUG MUXNot2Release */ |
| #define BCHP_SWITCH_CORE_P6_DEBUG_MUX 0x04e03060 /* [RO] P6 DEBUG MUXNot2Release */ |
| #define BCHP_SWITCH_CORE_DEBUG_MUX_P7 0x04e03070 /* [RO] P7 DEBUG MUXNot2Release */ |
| #define BCHP_SWITCH_CORE_DEBUG_MUX_IMP 0x04e03080 /* [RO] IMP DEBUG MUXNot2Release */ |
| #define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0 0x04e03090 /* [RO] CFP DEBUG BUS 0Not2Release */ |
| #define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1 0x04e030a0 /* [RO] CFP DEBUG BUS 1Not2Release */ |
| #define BCHP_SWITCH_CORE_WRED_DEBUG_0 0x04e030b0 /* [RO] WRED DEBUG 0Not2Release */ |
| #define BCHP_SWITCH_CORE_WRED_DEBUG_1 0x04e030c0 /* [RO] WRED DEBUG 1Not2Release */ |
| #define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0 0x04e030d0 /* [RO] TOP MISC DEBUG 0Not2Release */ |
| #define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1 0x04e030e0 /* [RO] TOP MISC DEBUG 1Not2Release */ |
| #define BCHP_SWITCH_CORE_DIAGREG_BUFCON 0x04e030f0 /* [RO] DIAGREG BUFCONNot2Release */ |
| #define BCHP_SWITCH_CORE_TESTBUS_P1588 0x04e03100 /* [RO] TESTBUS P1588Not2Release */ |
| #define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS 0x04e03110 /* [RO] FLOWCON DEBUG BUSNot2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0 0x04e03400 /* [RW] IMP0 Port(Port 8) Queue 0 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1 0x04e03408 /* [RW] IMP0 Port(Port 8) Queue 1 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2 0x04e03410 /* [RW] IMP0 Port(Port 8) Queue 2 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3 0x04e03418 /* [RW] IMP0 Port(Port 8) Queue 3 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4 0x04e03420 /* [RW] IMP0 Port(Port 8) Queue 4 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5 0x04e03428 /* [RW] IMP0 Port(Port 8) Queue 5 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6 0x04e03430 /* [RW] IMP0 Port(Port 8) Queue 6 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7 0x04e03438 /* [RW] IMP0 Port(Port 8) Queue 7 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0 0x04e03440 /* [RW] IMP0 Port(Port 8) Queue 0 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1 0x04e03448 /* [RW] IMP0 Port(Port 8) Queue 1 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2 0x04e03450 /* [RW] IMP0 Port(Port 8) Queue 2 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3 0x04e03458 /* [RW] IMP0 Port(Port 8) Queue 3 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4 0x04e03460 /* [RW] IMP0 Port(Port 8) Queue 4 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5 0x04e03468 /* [RW] IMP0 Port(Port 8) Queue 5 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6 0x04e03470 /* [RW] IMP0 Port(Port 8) Queue 6 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7 0x04e03478 /* [RW] IMP0 Port(Port 8) Queue 7 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0 0x04e03480 /* [RW] IMP0 Port(Port 8) Queue 0 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1 0x04e03488 /* [RW] IMP0 Port(Port 8) Queue 1 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2 0x04e03490 /* [RW] IMP0 Port(Port 8) Queue 2 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3 0x04e03498 /* [RW] IMP0 Port(Port 8) Queue 3 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4 0x04e034a0 /* [RW] IMP0 Port(Port 8) Queue 4 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5 0x04e034a8 /* [RW] IMP0 Port(Port 8) Queue 5 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6 0x04e034b0 /* [RW] IMP0 Port(Port 8) Queue 6 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7 0x04e034b8 /* [RW] IMP0 Port(Port 8) Queue 7 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0 0x04e034c0 /* [RW] IMP0 Port(Port 8) Queue 0 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1 0x04e034c8 /* [RW] IMP0 Port(Port 8) Queue 1 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2 0x04e034d0 /* [RW] IMP0 Port(Port 8) Queue 2 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3 0x04e034d8 /* [RW] IMP0 Port(Port 8) Queue 3 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4 0x04e034e0 /* [RW] IMP0 Port(Port 8) Queue 4 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5 0x04e034e8 /* [RW] IMP0 Port(Port 8) Queue 5 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6 0x04e034f0 /* [RW] IMP0 Port(Port 8) Queue 6 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7 0x04e034f8 /* [RW] IMP0 Port(Port 8) Queue 7 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0 0x04e03500 /* [RW] IMP0 Port(Port 8) Queue 0 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1 0x04e03508 /* [RW] IMP0 Port(Port 8) Queue 1 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2 0x04e03510 /* [RW] IMP0 Port(Port 8) Queue 2 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3 0x04e03518 /* [RW] IMP0 Port(Port 8) Queue 3 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4 0x04e03520 /* [RW] IMP0 Port(Port 8) Queue 4 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5 0x04e03528 /* [RW] IMP0 Port(Port 8) Queue 5 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6 0x04e03530 /* [RW] IMP0 Port(Port 8) Queue 6 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7 0x04e03538 /* [RW] IMP0 Port(Port 8) Queue 7 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0 0x04e03540 /* [RW] IMP0 Port(Port 8) Queue 0 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1 0x04e03548 /* [RW] IMP0 Port(Port 8) Queue 1 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2 0x04e03550 /* [RW] IMP0 Port(Port 8) Queue 2 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3 0x04e03558 /* [RW] IMP0 Port(Port 8) Queue 3 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4 0x04e03560 /* [RW] IMP0 Port(Port 8) Queue 4 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5 0x04e03568 /* [RW] IMP0 Port(Port 8) Queue 5 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6 0x04e03570 /* [RW] IMP0 Port(Port 8) Queue 6 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7 0x04e03578 /* [RW] IMP0 Port(Port 8) Queue 7 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0 0x04e03580 /* [RW] IMP0 Port(Port 8) Queue 0 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1 0x04e03588 /* [RW] IMP0 Port(Port 8) Queue 1 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2 0x04e03590 /* [RW] IMP0 Port(Port 8) Queue 2 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3 0x04e03598 /* [RW] IMP0 Port(Port 8) Queue 3 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4 0x04e035a0 /* [RW] IMP0 Port(Port 8) Queue 4 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5 0x04e035a8 /* [RW] IMP0 Port(Port 8) Queue 5 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6 0x04e035b0 /* [RW] IMP0 Port(Port 8) Queue 6 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7 0x04e035b8 /* [RW] IMP0 Port(Port 8) Queue 7 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0 0x04e035c0 /* [RW] Spare 0 Register (Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1 0x04e035c8 /* [RW] Spare 1 Register (Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0 0x04e03800 /* [RW] WAN/IMP1 Port Queue 0 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1 0x04e03808 /* [RW] WAN/IMP1 Port Queue 1 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2 0x04e03810 /* [RW] WAN/IMP1 Port Queue 2 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3 0x04e03818 /* [RW] WAN/IMP1 Port Queue 3 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4 0x04e03820 /* [RW] WAN/IMP1 Port Queue 4 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5 0x04e03828 /* [RW] WAN/IMP1 Port Queue 5 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6 0x04e03830 /* [RW] WAN/IMP1 Port Queue 6 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7 0x04e03838 /* [RW] WAN/IMP1 Port Queue 7 Reserved Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0 0x04e03840 /* [RW] WAN/IMP1 Port Queue 0 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1 0x04e03848 /* [RW] WAN/IMP1 Port Queue 1 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2 0x04e03850 /* [RW] WAN/IMP1 Port Queue 2 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3 0x04e03858 /* [RW] WAN/IMP1 Port Queue 3 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4 0x04e03860 /* [RW] WAN/IMP1 Port Queue 4 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5 0x04e03868 /* [RW] WAN/IMP1 Port Queue 5 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6 0x04e03870 /* [RW] WAN/IMP1 Port Queue 6 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7 0x04e03878 /* [RW] WAN/IMP1 Port Queue 7 Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 0x04e03880 /* [RW] WAN/IMP1 Port Queue 0 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 0x04e03888 /* [RW] WAN/IMP1 Port Queue 1 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 0x04e03890 /* [RW] WAN/IMP1 Port Queue 2 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 0x04e03898 /* [RW] WAN/IMP1 Port Queue 3 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 0x04e038a0 /* [RW] WAN/IMP1 Port Queue 4 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 0x04e038a8 /* [RW] WAN/IMP1 Port Queue 5 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 0x04e038b0 /* [RW] WAN/IMP1 Port Queue 6 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 0x04e038b8 /* [RW] WAN/IMP1 Port Queue 7 Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0 0x04e038c0 /* [RW] WAN/IMP1 Port Queue 0 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1 0x04e038c8 /* [RW] WAN/IMP1 Port Queue 1 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2 0x04e038d0 /* [RW] WAN/IMP1 Port Queue 2 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3 0x04e038d8 /* [RW] WAN/IMP1 Port Queue 3 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4 0x04e038e0 /* [RW] WAN/IMP1 Port Queue 4 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5 0x04e038e8 /* [RW] WAN/IMP1 Port Queue 5 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6 0x04e038f0 /* [RW] WAN/IMP1 Port Queue 6 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7 0x04e038f8 /* [RW] WAN/IMP1 Port Queue 7 DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0 0x04e03900 /* [RW] WAN/IMP1 Port Queue 0 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1 0x04e03908 /* [RW] WAN/IMP1 Port Queue 1 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2 0x04e03910 /* [RW] WAN/IMP1 Port Queue 2 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3 0x04e03918 /* [RW] WAN/IMP1 Port Queue 3 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4 0x04e03920 /* [RW] WAN/IMP1 Port Queue 4 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5 0x04e03928 /* [RW] WAN/IMP1 Port Queue 5 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6 0x04e03930 /* [RW] WAN/IMP1 Port Queue 6 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7 0x04e03938 /* [RW] WAN/IMP1 Port Queue 7 Total Hysteresis Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 0x04e03940 /* [RW] WAN/IMP1 Port Queue 0 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 0x04e03948 /* [RW] WAN/IMP1 Port Queue 1 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 0x04e03950 /* [RW] WAN/IMP1 Port Queue 2 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 0x04e03958 /* [RW] WAN/IMP1 Port Queue 3 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 0x04e03960 /* [RW] WAN/IMP1 Port Queue 4 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 0x04e03968 /* [RW] WAN/IMP1 Port Queue 5 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 0x04e03970 /* [RW] WAN/IMP1 Port Queue 6 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 0x04e03978 /* [RW] WAN/IMP1 Port Queue 7 Total Pause Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0 0x04e03980 /* [RW] WAN/IMP1 Port Queue 0 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1 0x04e03988 /* [RW] WAN/IMP1 Port Queue 1 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2 0x04e03990 /* [RW] WAN/IMP1 Port Queue 2 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3 0x04e03998 /* [RW] WAN/IMP1 Port Queue 3 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4 0x04e039a0 /* [RW] WAN/IMP1 Port Queue 4 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5 0x04e039a8 /* [RW] WAN/IMP1 Port Queue 5 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6 0x04e039b0 /* [RW] WAN/IMP1 Port Queue 6 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7 0x04e039b8 /* [RW] WAN/IMP1 Port Queue 7 Total DROP Threshold Register Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0 0x04e039c0 /* [RW] Spare 0 Register (Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1 0x04e039c8 /* [RW] Spare 1 Register (Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_CTL 0x04e03c00 /* [RW] Temperature Monitor Control Registers(Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_RESU 0x04e03c08 /* [RW] Temperature Monitor Result Registers(Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU 0x04e03c10 /* [RW] Peak Temperature Monitor Result Registers(Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_CAL 0x04e03c18 /* [RW] Temperature Monitor Calibration Registers(Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL 0x04e03c20 /* [RW] Temperature Monitor Special Control Registers(Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_TxOctets_P0 0x04e08000 /* [RW] Tx Octets */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P0 0x04e08020 /* [RW] Tx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P0 0x04e08030 /* [RW] Tx Q0 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P0 0x04e08040 /* [RW] Tx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P0 0x04e08050 /* [RW] Tx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P0 0x04e08060 /* [RW] Tx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P0 0x04e08070 /* [RW] Tx Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P0 0x04e08080 /* [RW] Tx Single Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P0 0x04e08090 /* [RW] Tx Multiple collsion Counter */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P0 0x04e080a0 /* [RW] Tx Deferred Transmit Counter */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P0 0x04e080b0 /* [RW] Tx Late Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P0 0x04e080c0 /* [RW] Tx Excessive Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P0 0x04e080d0 /* [RW] Tx Fram IN Disc Counter */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P0 0x04e080e0 /* [RW] Tx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P0 0x04e080f0 /* [RW] Tx Q1 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P0 0x04e08100 /* [RW] Tx Q2 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P0 0x04e08110 /* [RW] Tx Q3 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P0 0x04e08120 /* [RW] Tx Q4 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P0 0x04e08130 /* [RW] Tx Q5 Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxOctets_P0 0x04e08140 /* [RW] Rx Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P0 0x04e08160 /* [RW] Rx Under Size Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P0 0x04e08170 /* [RW] Rx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P0 0x04e08180 /* [RW] Rx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0 0x04e08190 /* [RW] Rx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0 0x04e081a0 /* [RW] Rx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0 0x04e081b0 /* [RW] Rx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0 0x04e081c0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0 0x04e081d0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P0 0x04e081e0 /* [RW] Rx Over Size Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P0 0x04e081f0 /* [RW] Rx Jabber Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P0 0x04e08200 /* [RW] Rx Alignment Error Counter */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P0 0x04e08210 /* [RW] Rx FCS Error Counter */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P0 0x04e08220 /* [RW] Rx Good Packet Octet Counter */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P0 0x04e08240 /* [RW] Rx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P0 0x04e08250 /* [RW] Rx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P0 0x04e08260 /* [RW] Rx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P0 0x04e08270 /* [RW] Rx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P0 0x04e08280 /* [RW] Rx SA Change Counter */ |
| #define BCHP_SWITCH_CORE_RxFragments_P0 0x04e08290 /* [RW] Rx Fragment Counter */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P0 0x04e082a0 /* [RW] Jumbo Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P0 0x04e082b0 /* [RW] Rx Symbol Error Counter */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P0 0x04e082c0 /* [RW] InRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P0 0x04e082d0 /* [RW] OutRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0 0x04e082e0 /* [RW] EEE Low-Power Idle Event Registers */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0 0x04e082f0 /* [RW] EEE Low-Power Idle Duration Registers */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P0 0x04e08300 /* [RW] Rx Discard Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P0 0x04e08320 /* [RW] Tx Q6 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P0 0x04e08330 /* [RW] Tx Q7 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P0 0x04e08340 /* [RW] Tx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0 0x04e08350 /* [RW] Tx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0 0x04e08360 /* [RW] Tx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0 0x04e08370 /* [RW] Tx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0 0x04e08380 /* [RW] Tx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0 0x04e08390 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxOctets_P1 0x04e08400 /* [RW] Tx Octets */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P1 0x04e08420 /* [RW] Tx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P1 0x04e08430 /* [RW] Tx Q0 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P1 0x04e08440 /* [RW] Tx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P1 0x04e08450 /* [RW] Tx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P1 0x04e08460 /* [RW] Tx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P1 0x04e08470 /* [RW] Tx Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P1 0x04e08480 /* [RW] Tx Single Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P1 0x04e08490 /* [RW] Tx Multiple collsion Counter */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P1 0x04e084a0 /* [RW] Tx Deferred Transmit Counter */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P1 0x04e084b0 /* [RW] Tx Late Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P1 0x04e084c0 /* [RW] Tx Excessive Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P1 0x04e084d0 /* [RW] Tx Fram IN Disc Counter */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P1 0x04e084e0 /* [RW] Tx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P1 0x04e084f0 /* [RW] Tx Q1 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P1 0x04e08500 /* [RW] Tx Q2 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P1 0x04e08510 /* [RW] Tx Q3 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P1 0x04e08520 /* [RW] Tx Q4 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P1 0x04e08530 /* [RW] Tx Q5 Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxOctets_P1 0x04e08540 /* [RW] Rx Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P1 0x04e08560 /* [RW] Rx Under Size Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P1 0x04e08570 /* [RW] Rx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P1 0x04e08580 /* [RW] Rx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1 0x04e08590 /* [RW] Rx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1 0x04e085a0 /* [RW] Rx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1 0x04e085b0 /* [RW] Rx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1 0x04e085c0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1 0x04e085d0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P1 0x04e085e0 /* [RW] Rx Over Size Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P1 0x04e085f0 /* [RW] Rx Jabber Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P1 0x04e08600 /* [RW] Rx Alignment Error Counter */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P1 0x04e08610 /* [RW] Rx FCS Error Counter */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P1 0x04e08620 /* [RW] Rx Good Packet Octet Counter */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P1 0x04e08640 /* [RW] Rx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P1 0x04e08650 /* [RW] Rx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P1 0x04e08660 /* [RW] Rx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P1 0x04e08670 /* [RW] Rx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P1 0x04e08680 /* [RW] Rx SA Change Counter */ |
| #define BCHP_SWITCH_CORE_RxFragments_P1 0x04e08690 /* [RW] Rx Fragment Counter */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P1 0x04e086a0 /* [RW] Jumbo Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P1 0x04e086b0 /* [RW] Rx Symbol Error Counter */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P1 0x04e086c0 /* [RW] InRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P1 0x04e086d0 /* [RW] OutRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1 0x04e086e0 /* [RW] EEE Low-Power Idle Event Registers */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1 0x04e086f0 /* [RW] EEE Low-Power Idle Duration Registers */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P1 0x04e08700 /* [RW] Rx Discard Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P1 0x04e08720 /* [RW] Tx Q6 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P1 0x04e08730 /* [RW] Tx Q7 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P1 0x04e08740 /* [RW] Tx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1 0x04e08750 /* [RW] Tx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1 0x04e08760 /* [RW] Tx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1 0x04e08770 /* [RW] Tx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1 0x04e08780 /* [RW] Tx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1 0x04e08790 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxOctets_P2 0x04e08800 /* [RW] Tx Octets */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P2 0x04e08820 /* [RW] Tx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P2 0x04e08830 /* [RW] Tx Q0 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P2 0x04e08840 /* [RW] Tx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P2 0x04e08850 /* [RW] Tx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P2 0x04e08860 /* [RW] Tx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P2 0x04e08870 /* [RW] Tx Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P2 0x04e08880 /* [RW] Tx Single Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P2 0x04e08890 /* [RW] Tx Multiple collsion Counter */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P2 0x04e088a0 /* [RW] Tx Deferred Transmit Counter */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P2 0x04e088b0 /* [RW] Tx Late Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P2 0x04e088c0 /* [RW] Tx Excessive Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P2 0x04e088d0 /* [RW] Tx Fram IN Disc Counter */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P2 0x04e088e0 /* [RW] Tx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P2 0x04e088f0 /* [RW] Tx Q1 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P2 0x04e08900 /* [RW] Tx Q2 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P2 0x04e08910 /* [RW] Tx Q3 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P2 0x04e08920 /* [RW] Tx Q4 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P2 0x04e08930 /* [RW] Tx Q5 Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxOctets_P2 0x04e08940 /* [RW] Rx Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P2 0x04e08960 /* [RW] Rx Under Size Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P2 0x04e08970 /* [RW] Rx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P2 0x04e08980 /* [RW] Rx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2 0x04e08990 /* [RW] Rx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2 0x04e089a0 /* [RW] Rx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2 0x04e089b0 /* [RW] Rx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2 0x04e089c0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2 0x04e089d0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P2 0x04e089e0 /* [RW] Rx Over Size Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P2 0x04e089f0 /* [RW] Rx Jabber Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P2 0x04e08a00 /* [RW] Rx Alignment Error Counter */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P2 0x04e08a10 /* [RW] Rx FCS Error Counter */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P2 0x04e08a20 /* [RW] Rx Good Packet Octet Counter */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P2 0x04e08a40 /* [RW] Rx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P2 0x04e08a50 /* [RW] Rx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P2 0x04e08a60 /* [RW] Rx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P2 0x04e08a70 /* [RW] Rx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P2 0x04e08a80 /* [RW] Rx SA Change Counter */ |
| #define BCHP_SWITCH_CORE_RxFragments_P2 0x04e08a90 /* [RW] Rx Fragment Counter */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P2 0x04e08aa0 /* [RW] Jumbo Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P2 0x04e08ab0 /* [RW] Rx Symbol Error Counter */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P2 0x04e08ac0 /* [RW] InRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P2 0x04e08ad0 /* [RW] OutRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2 0x04e08ae0 /* [RW] EEE Low-Power Idle Event Registers */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2 0x04e08af0 /* [RW] EEE Low-Power Idle Duration Registers */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P2 0x04e08b00 /* [RW] Rx Discard Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P2 0x04e08b20 /* [RW] Tx Q6 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P2 0x04e08b30 /* [RW] Tx Q7 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P2 0x04e08b40 /* [RW] Tx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2 0x04e08b50 /* [RW] Tx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2 0x04e08b60 /* [RW] Tx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2 0x04e08b70 /* [RW] Tx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2 0x04e08b80 /* [RW] Tx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2 0x04e08b90 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxOctets_P3 0x04e08c00 /* [RW] Tx Octets */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P3 0x04e08c20 /* [RW] Tx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P3 0x04e08c30 /* [RW] Tx Q0 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P3 0x04e08c40 /* [RW] Tx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P3 0x04e08c50 /* [RW] Tx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P3 0x04e08c60 /* [RW] Tx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P3 0x04e08c70 /* [RW] Tx Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P3 0x04e08c80 /* [RW] Tx Single Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P3 0x04e08c90 /* [RW] Tx Multiple collsion Counter */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P3 0x04e08ca0 /* [RW] Tx Deferred Transmit Counter */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P3 0x04e08cb0 /* [RW] Tx Late Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P3 0x04e08cc0 /* [RW] Tx Excessive Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P3 0x04e08cd0 /* [RW] Tx Fram IN Disc Counter */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P3 0x04e08ce0 /* [RW] Tx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P3 0x04e08cf0 /* [RW] Tx Q1 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P3 0x04e08d00 /* [RW] Tx Q2 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P3 0x04e08d10 /* [RW] Tx Q3 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P3 0x04e08d20 /* [RW] Tx Q4 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P3 0x04e08d30 /* [RW] Tx Q5 Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxOctets_P3 0x04e08d40 /* [RW] Rx Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P3 0x04e08d60 /* [RW] Rx Under Size Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P3 0x04e08d70 /* [RW] Rx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P3 0x04e08d80 /* [RW] Rx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3 0x04e08d90 /* [RW] Rx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3 0x04e08da0 /* [RW] Rx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3 0x04e08db0 /* [RW] Rx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3 0x04e08dc0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3 0x04e08dd0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P3 0x04e08de0 /* [RW] Rx Over Size Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P3 0x04e08df0 /* [RW] Rx Jabber Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P3 0x04e08e00 /* [RW] Rx Alignment Error Counter */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P3 0x04e08e10 /* [RW] Rx FCS Error Counter */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P3 0x04e08e20 /* [RW] Rx Good Packet Octet Counter */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P3 0x04e08e40 /* [RW] Rx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P3 0x04e08e50 /* [RW] Rx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P3 0x04e08e60 /* [RW] Rx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P3 0x04e08e70 /* [RW] Rx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P3 0x04e08e80 /* [RW] Rx SA Change Counter */ |
| #define BCHP_SWITCH_CORE_RxFragments_P3 0x04e08e90 /* [RW] Rx Fragment Counter */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P3 0x04e08ea0 /* [RW] Jumbo Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P3 0x04e08eb0 /* [RW] Rx Symbol Error Counter */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P3 0x04e08ec0 /* [RW] InRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P3 0x04e08ed0 /* [RW] OutRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3 0x04e08ee0 /* [RW] EEE Low-Power Idle Event Registers */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3 0x04e08ef0 /* [RW] EEE Low-Power Idle Duration Registers */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P3 0x04e08f00 /* [RW] Rx Discard Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P3 0x04e08f20 /* [RW] Tx Q6 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P3 0x04e08f30 /* [RW] Tx Q7 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P3 0x04e08f40 /* [RW] Tx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3 0x04e08f50 /* [RW] Tx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3 0x04e08f60 /* [RW] Tx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3 0x04e08f70 /* [RW] Tx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3 0x04e08f80 /* [RW] Tx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3 0x04e08f90 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxOctets_P4 0x04e09000 /* [RW] Tx Octets */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P4 0x04e09020 /* [RW] Tx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P4 0x04e09030 /* [RW] Tx Q0 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P4 0x04e09040 /* [RW] Tx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P4 0x04e09050 /* [RW] Tx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P4 0x04e09060 /* [RW] Tx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P4 0x04e09070 /* [RW] Tx Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P4 0x04e09080 /* [RW] Tx Single Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P4 0x04e09090 /* [RW] Tx Multiple collsion Counter */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P4 0x04e090a0 /* [RW] Tx Deferred Transmit Counter */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P4 0x04e090b0 /* [RW] Tx Late Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P4 0x04e090c0 /* [RW] Tx Excessive Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P4 0x04e090d0 /* [RW] Tx Fram IN Disc Counter */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P4 0x04e090e0 /* [RW] Tx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P4 0x04e090f0 /* [RW] Tx Q1 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P4 0x04e09100 /* [RW] Tx Q2 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P4 0x04e09110 /* [RW] Tx Q3 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P4 0x04e09120 /* [RW] Tx Q4 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P4 0x04e09130 /* [RW] Tx Q5 Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxOctets_P4 0x04e09140 /* [RW] Rx Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P4 0x04e09160 /* [RW] Rx Under Size Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P4 0x04e09170 /* [RW] Rx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P4 0x04e09180 /* [RW] Rx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4 0x04e09190 /* [RW] Rx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4 0x04e091a0 /* [RW] Rx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4 0x04e091b0 /* [RW] Rx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4 0x04e091c0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4 0x04e091d0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P4 0x04e091e0 /* [RW] Rx Over Size Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P4 0x04e091f0 /* [RW] Rx Jabber Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P4 0x04e09200 /* [RW] Rx Alignment Error Counter */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P4 0x04e09210 /* [RW] Rx FCS Error Counter */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P4 0x04e09220 /* [RW] Rx Good Packet Octet Counter */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P4 0x04e09240 /* [RW] Rx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P4 0x04e09250 /* [RW] Rx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P4 0x04e09260 /* [RW] Rx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P4 0x04e09270 /* [RW] Rx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P4 0x04e09280 /* [RW] Rx SA Change Counter */ |
| #define BCHP_SWITCH_CORE_RxFragments_P4 0x04e09290 /* [RW] Rx Fragment Counter */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P4 0x04e092a0 /* [RW] Jumbo Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P4 0x04e092b0 /* [RW] Rx Symbol Error Counter */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P4 0x04e092c0 /* [RW] InRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P4 0x04e092d0 /* [RW] OutRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4 0x04e092e0 /* [RW] EEE Low-Power Idle Event Registers */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4 0x04e092f0 /* [RW] EEE Low-Power Idle Duration Registers */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P4 0x04e09300 /* [RW] Rx Discard Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P4 0x04e09320 /* [RW] Tx Q6 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P4 0x04e09330 /* [RW] Tx Q7 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P4 0x04e09340 /* [RW] Tx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4 0x04e09350 /* [RW] Tx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4 0x04e09360 /* [RW] Tx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4 0x04e09370 /* [RW] Tx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4 0x04e09380 /* [RW] Tx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4 0x04e09390 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxOctets_P5 0x04e09400 /* [RW] Tx Octets */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P5 0x04e09420 /* [RW] Tx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P5 0x04e09430 /* [RW] Tx Q0 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P5 0x04e09440 /* [RW] Tx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P5 0x04e09450 /* [RW] Tx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P5 0x04e09460 /* [RW] Tx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P5 0x04e09470 /* [RW] Tx Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P5 0x04e09480 /* [RW] Tx Single Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P5 0x04e09490 /* [RW] Tx Multiple collsion Counter */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P5 0x04e094a0 /* [RW] Tx Deferred Transmit Counter */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P5 0x04e094b0 /* [RW] Tx Late Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P5 0x04e094c0 /* [RW] Tx Excessive Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P5 0x04e094d0 /* [RW] Tx Fram IN Disc Counter */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P5 0x04e094e0 /* [RW] Tx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P5 0x04e094f0 /* [RW] Tx Q1 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P5 0x04e09500 /* [RW] Tx Q2 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P5 0x04e09510 /* [RW] Tx Q3 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P5 0x04e09520 /* [RW] Tx Q4 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P5 0x04e09530 /* [RW] Tx Q5 Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxOctets_P5 0x04e09540 /* [RW] Rx Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P5 0x04e09560 /* [RW] Rx Under Size Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P5 0x04e09570 /* [RW] Rx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P5 0x04e09580 /* [RW] Rx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5 0x04e09590 /* [RW] Rx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5 0x04e095a0 /* [RW] Rx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5 0x04e095b0 /* [RW] Rx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5 0x04e095c0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5 0x04e095d0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P5 0x04e095e0 /* [RW] Rx Over Size Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P5 0x04e095f0 /* [RW] Rx Jabber Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P5 0x04e09600 /* [RW] Rx Alignment Error Counter */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P5 0x04e09610 /* [RW] Rx FCS Error Counter */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P5 0x04e09620 /* [RW] Rx Good Packet Octet Counter */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P5 0x04e09640 /* [RW] Rx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P5 0x04e09650 /* [RW] Rx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P5 0x04e09660 /* [RW] Rx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P5 0x04e09670 /* [RW] Rx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P5 0x04e09680 /* [RW] Rx SA Change Counter */ |
| #define BCHP_SWITCH_CORE_RxFragments_P5 0x04e09690 /* [RW] Rx Fragment Counter */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P5 0x04e096a0 /* [RW] Jumbo Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P5 0x04e096b0 /* [RW] Rx Symbol Error Counter */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P5 0x04e096c0 /* [RW] InRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P5 0x04e096d0 /* [RW] OutRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5 0x04e096e0 /* [RW] EEE Low-Power Idle Event Registers */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5 0x04e096f0 /* [RW] EEE Low-Power Idle Duration Registers */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P5 0x04e09700 /* [RW] Rx Discard Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P5 0x04e09720 /* [RW] Tx Q6 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P5 0x04e09730 /* [RW] Tx Q7 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P5 0x04e09740 /* [RW] Tx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5 0x04e09750 /* [RW] Tx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5 0x04e09760 /* [RW] Tx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5 0x04e09770 /* [RW] Tx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5 0x04e09780 /* [RW] Tx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5 0x04e09790 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxOctets_P7 0x04e09c00 /* [RW] Tx Octets */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P7 0x04e09c20 /* [RW] Tx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P7 0x04e09c30 /* [RW] Tx Q0 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P7 0x04e09c40 /* [RW] Tx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P7 0x04e09c50 /* [RW] Tx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P7 0x04e09c60 /* [RW] Tx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P7 0x04e09c70 /* [RW] Tx Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P7 0x04e09c80 /* [RW] Tx Single Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P7 0x04e09c90 /* [RW] Tx Multiple collsion Counter */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P7 0x04e09ca0 /* [RW] Tx Deferred Transmit Counter */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P7 0x04e09cb0 /* [RW] Tx Late Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P7 0x04e09cc0 /* [RW] Tx Excessive Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P7 0x04e09cd0 /* [RW] Tx Fram IN Disc Counter */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P7 0x04e09ce0 /* [RW] Tx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P7 0x04e09cf0 /* [RW] Tx Q1 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P7 0x04e09d00 /* [RW] Tx Q2 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P7 0x04e09d10 /* [RW] Tx Q3 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P7 0x04e09d20 /* [RW] Tx Q4 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P7 0x04e09d30 /* [RW] Tx Q5 Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxOctets_P7 0x04e09d40 /* [RW] Rx Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P7 0x04e09d60 /* [RW] Rx Under Size Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P7 0x04e09d70 /* [RW] Rx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P7 0x04e09d80 /* [RW] Rx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7 0x04e09d90 /* [RW] Rx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7 0x04e09da0 /* [RW] Rx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7 0x04e09db0 /* [RW] Rx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7 0x04e09dc0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7 0x04e09dd0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P7 0x04e09de0 /* [RW] Rx Over Size Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P7 0x04e09df0 /* [RW] Rx Jabber Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P7 0x04e09e00 /* [RW] Rx Alignment Error Counter */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P7 0x04e09e10 /* [RW] Rx FCS Error Counter */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P7 0x04e09e20 /* [RW] Rx Good Packet Octet Counter */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P7 0x04e09e40 /* [RW] Rx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P7 0x04e09e50 /* [RW] Rx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P7 0x04e09e60 /* [RW] Rx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P7 0x04e09e70 /* [RW] Rx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P7 0x04e09e80 /* [RW] Rx SA Change Counter */ |
| #define BCHP_SWITCH_CORE_RxFragments_P7 0x04e09e90 /* [RW] Rx Fragment Counter */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P7 0x04e09ea0 /* [RW] Jumbo Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P7 0x04e09eb0 /* [RW] Rx Symbol Error Counter */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P7 0x04e09ec0 /* [RW] InRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P7 0x04e09ed0 /* [RW] OutRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7 0x04e09ee0 /* [RW] EEE Low-Power Idle Event Registers */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7 0x04e09ef0 /* [RW] EEE Low-Power Idle Duration Registers */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P7 0x04e09f00 /* [RW] Rx Discard Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P7 0x04e09f20 /* [RW] Tx Q6 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P7 0x04e09f30 /* [RW] Tx Q7 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P7 0x04e09f40 /* [RW] Tx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7 0x04e09f50 /* [RW] Tx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7 0x04e09f60 /* [RW] Tx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7 0x04e09f70 /* [RW] Tx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7 0x04e09f80 /* [RW] Tx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7 0x04e09f90 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxOctets_IMP 0x04e0a000 /* [RW] Tx Octets */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_IMP 0x04e0a020 /* [RW] Tx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_IMP 0x04e0a030 /* [RW] Tx Q0 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP 0x04e0a040 /* [RW] Tx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_IMP 0x04e0a050 /* [RW] Tx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_IMP 0x04e0a060 /* [RW] Tx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxCollisions_IMP 0x04e0a070 /* [RW] Tx Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_IMP 0x04e0a080 /* [RW] Tx Single Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_IMP 0x04e0a090 /* [RW] Tx Multiple collsion Counter */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP 0x04e0a0a0 /* [RW] Tx Deferred Transmit Counter */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_IMP 0x04e0a0b0 /* [RW] Tx Late Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP 0x04e0a0c0 /* [RW] Tx Excessive Collision Counter */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_IMP 0x04e0a0d0 /* [RW] Tx Fram IN Disc Counter */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_IMP 0x04e0a0e0 /* [RW] Tx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_IMP 0x04e0a0f0 /* [RW] Tx Q1 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_IMP 0x04e0a100 /* [RW] Tx Q2 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_IMP 0x04e0a110 /* [RW] Tx Q3 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_IMP 0x04e0a120 /* [RW] Tx Q4 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_IMP 0x04e0a130 /* [RW] Tx Q5 Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxOctets_IMP 0x04e0a140 /* [RW] Rx Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_IMP 0x04e0a160 /* [RW] Rx Under Size Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_IMP 0x04e0a170 /* [RW] Rx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_IMP 0x04e0a180 /* [RW] Rx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP 0x04e0a190 /* [RW] Rx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP 0x04e0a1a0 /* [RW] Rx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP 0x04e0a1b0 /* [RW] Rx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP 0x04e0a1c0 /* [RW] Rx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP 0x04e0a1d0 /* [RW] Rx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_IMP 0x04e0a1e0 /* [RW] Rx Over Size Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxJabbers_IMP 0x04e0a1f0 /* [RW] Rx Jabber Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP 0x04e0a200 /* [RW] Rx Alignment Error Counter */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_IMP 0x04e0a210 /* [RW] Rx FCS Error Counter */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_IMP 0x04e0a220 /* [RW] Rx Good Packet Octet Counter */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_IMP 0x04e0a240 /* [RW] Rx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_IMP 0x04e0a250 /* [RW] Rx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_IMP 0x04e0a260 /* [RW] Rx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP 0x04e0a270 /* [RW] Rx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_IMP 0x04e0a280 /* [RW] Rx SA Change Counter */ |
| #define BCHP_SWITCH_CORE_RxFragments_IMP 0x04e0a290 /* [RW] Rx Fragment Counter */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_IMP 0x04e0a2a0 /* [RW] Jumbo Packet Counter */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_IMP 0x04e0a2b0 /* [RW] Rx Symbol Error Counter */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_IMP 0x04e0a2c0 /* [RW] InRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_IMP 0x04e0a2d0 /* [RW] OutRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP 0x04e0a2e0 /* [RW] EEE Low-Power Idle Event Registers */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP 0x04e0a2f0 /* [RW] EEE Low-Power Idle Duration Registers */ |
| #define BCHP_SWITCH_CORE_RxDiscard_IMP 0x04e0a300 /* [RW] Rx Discard Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_IMP 0x04e0a320 /* [RW] Tx Q6 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_IMP 0x04e0a330 /* [RW] Tx Q7 Packet Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_IMP 0x04e0a340 /* [RW] Tx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP 0x04e0a350 /* [RW] Tx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP 0x04e0a360 /* [RW] Tx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP 0x04e0a370 /* [RW] Tx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP 0x04e0a380 /* [RW] Tx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP 0x04e0a390 /* [RW] Tx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL 0x04e0c000 /* [RW] QOS Global Control Register */ |
| #define BCHP_SWITCH_CORE_QOS_1P_EN 0x04e0c010 /* [RW] QoS 802.1P Enable Register */ |
| #define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV 0x04e0c018 /* [RW] QOS DiffServ Enable Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0 0x04e0c040 /* [RW] Port 0 PCP to TC Map for DEI 0 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1 0x04e0c050 /* [RW] Port 1 PCP to TC Map for DEI 0 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2 0x04e0c060 /* [RW] Port 2 PCP to TC Map for DEI 0 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3 0x04e0c070 /* [RW] Port 3 PCP to TC Map for DEI 0 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4 0x04e0c080 /* [RW] Port 4 PCP to TC Map for DEI 0 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5 0x04e0c090 /* [RW] Port 5 PCP to TC Map for DEI 0 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7 0x04e0c0a0 /* [RW] Port 7 PCP to TC Map for DEI 0 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP 0x04e0c0b0 /* [RW] Port 8 (IMP) PCP to TC Map for DEI 0 Register */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0 0x04e0c0c0 /* [RW] DiffServ Priority Map 0 Register */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1 0x04e0c0d8 /* [RW] DiffServ Priority Map 1 Register */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2 0x04e0c0f0 /* [RW] DiffServ Priority Map 2 Register */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3 0x04e0c108 /* [RW] DiffServ Priority Map 3 Register */ |
| #define BCHP_SWITCH_CORE_PID2TC 0x04e0c120 /* [RW] Port ID to TC Map Register */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0 0x04e0c140 /* [RW] Port 0 TC Select Table Register */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1 0x04e0c148 /* [RW] Port 1 TC Select Table Register */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2 0x04e0c150 /* [RW] Port 2 TC Select Table Register */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3 0x04e0c158 /* [RW] Port 3 TC Select Table Register */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4 0x04e0c160 /* [RW] Port 4 TC Select Table Register */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5 0x04e0c168 /* [RW] Port 5 TC Select Table Register */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7 0x04e0c178 /* [RW] Port 7 TC Select Table Register */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP 0x04e0c180 /* [RW] Port 8 TC Select Table Register */ |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP 0x04e0c190 /* [RW] CPU to COS Mapping Register */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0 0x04e0c1c0 /* [RW] Port 0 TC to COS Mapping Register */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1 0x04e0c1d0 /* [RW] Port 1 TC to COS Mapping Register */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2 0x04e0c1e0 /* [RW] Port 2 TC to COS Mapping Register */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3 0x04e0c1f0 /* [RW] Port 3 TC to COS Mapping Register */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4 0x04e0c200 /* [RW] Port 4 TC to COS Mapping Register */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5 0x04e0c210 /* [RW] Port 5 TC to COS Mapping Register */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7 0x04e0c230 /* [RW] Port 7 TC to COS Mapping Register */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP 0x04e0c240 /* [RW] Port 8 TC to COS Mapping Register */ |
| #define BCHP_SWITCH_CORE_QOS_REG_SPARE0 0x04e0c2a0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_QOS_REG_SPARE1 0x04e0c2b0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0 0x04e0c2c0 /* [RW] Port 0 PCP to TC Map for DEI 1 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1 0x04e0c2d0 /* [RW] Port 1 PCP to TC Map for DEI 1 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2 0x04e0c2e0 /* [RW] Port 2 PCP to TC Map for DEI 1 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3 0x04e0c2f0 /* [RW] Port 3 PCP to TC Map for DEI 1 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4 0x04e0c300 /* [RW] Port 4 PCP to TC Map for DEI 1 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5 0x04e0c310 /* [RW] Port 5 PCP to TC Map for DEI 1 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7 0x04e0c320 /* [RW] Port 7 PCP to TC Map for DEI 1 Register */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP 0x04e0c330 /* [RW] Port 8 (IMP) PCP to TC Map for DEI 1 Register */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P0 0x04e0c400 /* [RW] PORT 0 VLAN Control Register */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P1 0x04e0c408 /* [RW] PORT 1 VLAN Control Register */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P2 0x04e0c410 /* [RW] PORT 2 VLAN Control Register */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P3 0x04e0c418 /* [RW] PORT 3 VLAN Control Register */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P4 0x04e0c420 /* [RW] PORT 4 VLAN Control Register */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P5 0x04e0c428 /* [RW] PORT 5 VLAN Control Register */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P7 0x04e0c438 /* [RW] PORT 7 VLAN Control Register */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_IMP 0x04e0c440 /* [RW] PORT 8 VLAN Control Register */ |
| #define BCHP_SWITCH_CORE_VLAN_REG_SPARE0 0x04e0c480 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_VLAN_REG_SPARE1 0x04e0c490 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL 0x04e0c800 /* [RW] MAC Trunk Control Register */ |
| #define BCHP_SWITCH_CORE_IMP0_GRP_CTL 0x04e0c808 /* [RW] IMP0 Group Control Register */ |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0 0x04e0c840 /* [RW] Trunk 0 Group Control Register */ |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1 0x04e0c848 /* [RW] Trunk 1 Group Control Register */ |
| #define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0 0x04e0c880 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1 0x04e0c890 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0 0x04e0d000 /* [RW] 802.1Q VLAN Control 0 Registers */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1 0x04e0d004 /* [RW] 802.1Q VLAN Control 1 Registers */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2 0x04e0d008 /* [RW] 802.1Q VLAN Control 2 Registers */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL3 0x04e0d00c /* [RW] 802.1Q VLAN Control 3 Registers */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4 0x04e0d014 /* [RW] 802.1Q VLAN Control 4 Registers */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5 0x04e0d018 /* [RW] 802.1Q VLAN Control 5 Registers */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6 0x04e0d01c /* [RW] 802.1Q VLAN Control 6 Registers */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL 0x04e0d028 /* [RW] VLAN Multiport Address Control Register */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0 0x04e0d040 /* [RW] Port 0 802.1Q Default Tag Registers */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1 0x04e0d048 /* [RW] Port 1 802.1Q Default Tag Registers */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2 0x04e0d050 /* [RW] Port 2 802.1Q Default Tag Registers */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3 0x04e0d058 /* [RW] Port 3 802.1Q Default Tag Registers */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4 0x04e0d060 /* [RW] Port 4 802.1Q Default Tag Registers */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5 0x04e0d068 /* [RW] Port 5 802.1Q Default Tag Registers */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7 0x04e0d078 /* [RW] Port 7 802.1Q Default Tag Registers */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP 0x04e0d080 /* [RW] Port 8 802.1Q Default Tag Registers */ |
| #define BCHP_SWITCH_CORE_DTAG_TPID 0x04e0d0c0 /* [RW] Double Tagging TPID Registers */ |
| #define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP 0x04e0d0c8 /* [RW] ISP Port Selection Portmap Registers */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS 0x04e0d100 /* [RW] Egress VID Remarking Table Access Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA 0x04e0d110 /* [RW] Egress VID Remarking Table Data Register */ |
| #define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN 0x04e0d140 /* [RW] Join All VLAN Enable Register */ |
| #define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL 0x04e0d148 /* [RW] Port IVL or SVL Control Register */ |
| #define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0 0x04e0d180 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1 0x04e0d190 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL 0x04e0d800 /* [RW] DoS Control RegisterRegister */ |
| #define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ 0x04e0d810 /* [RW] Minimum TCP Header Size Register */ |
| #define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG 0x04e0d820 /* [RW] Maximum ICMPv4 Size Register */ |
| #define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG 0x04e0d830 /* [RW] Maximum ICMPv6 Size Register */ |
| #define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG 0x04e0d840 /* [RW] DoS Disable Learn Register */ |
| #define BCHP_SWITCH_CORE_DOS_REG_SPARE0 0x04e0d880 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_DOS_REG_SPARE1 0x04e0d890 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK 0x04e10004 /* [RW] Jumbo Frame Port Mask Registers */ |
| #define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE 0x04e10014 /* [RW] Jumbo MIB Good Frame Max Size Registers */ |
| #define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0 0x04e10040 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1 0x04e10050 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON 0x04e10400 /* [RW] Common Ingress rate Control Configuration Registers */ |
| #define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD 0x04e10410 /* [RW] Ingress Rate Control Virtual Zero Threshold Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_IRC_ALARM_THD 0x04e10418 /* [RW] Ingress Rate Control Alarm Threshold Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0 0x04e10440 /* [RW] Port 0 Receive Rate Control Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1 0x04e10450 /* [RW] Port 1 Receive Rate Control Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2 0x04e10460 /* [RW] Port 2 Receive Rate Control Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3 0x04e10470 /* [RW] Port 3 Receive Rate Control Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4 0x04e10480 /* [RW] Port 4 Receive Rate Control Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5 0x04e10490 /* [RW] Port 5 Receive Rate Control Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7 0x04e104b0 /* [RW] Port 7 Receive Rate Control Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP 0x04e104c0 /* [RW] Port 8 Receive Rate Control Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0 0x04e104d0 /* [RW] Port 0 Receive Rate Control 1 Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1 0x04e104d8 /* [RW] Port 1 Receive Rate Control 1 Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2 0x04e104e0 /* [RW] Port 2 Receive Rate Control 1 Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3 0x04e104e8 /* [RW] Port 3 Receive Rate Control 1 Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4 0x04e104f0 /* [RW] Port 4 Receive Rate Control 1 Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5 0x04e104f8 /* [RW] Port 5 Receive Rate Control 1 Registers */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7 0x04e10508 /* [RW] Port 7 Receive Rate Control 1 Register */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP 0x04e1050c /* [RW] Port 8 Receive Rate Control 1 Register */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P0 0x04e10540 /* [RO] Port 0 Suppressed Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P1 0x04e10550 /* [RO] Port 1 Suppressed Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P2 0x04e10560 /* [RO] Port 2 Suppressed Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P3 0x04e10570 /* [RO] Port 3 Suppressed Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P4 0x04e10580 /* [RO] Port 4 Suppressed Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P5 0x04e10590 /* [RO] Port 5 Suppressed Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7 0x04e105b0 /* [RO] P7 Suppressed Packet DropCounter Register */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP 0x04e105c0 /* [RO] Port 8 Suppressed Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0 0x04e10740 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1 0x04e10750 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON 0x04e10800 /* [RW] EAP Global Configuration Registers */ |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL 0x04e10804 /* [RW] EAP Multiport Address Control Register */ |
| #define BCHP_SWITCH_CORE_EAP_DIP0 0x04e10808 /* [RW] EAP Destination IP Registers */ |
| #define BCHP_SWITCH_CORE_EAP_DIP1 0x04e10828 /* [RW] EAP Destination IP Registers */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P0 0x04e10880 /* [RW] Port 0 EAP Configuration Registers */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P1 0x04e108a0 /* [RW] Port 1 EAP Configuration Registers */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P2 0x04e108c0 /* [RW] Port 2 EAP Configuration Registers */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P3 0x04e108e0 /* [RW] Port 3 EAP Configuration Registers */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P4 0x04e10900 /* [RW] Port 4 EAP Configuration Registers */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P5 0x04e10920 /* [RW] Port 5 EAP Configuration Registers */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P7 0x04e10960 /* [RW] Port 7 EAP Configuration Registers */ |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP 0x04e10980 /* [RW] IMP EAP Configuration Registers */ |
| #define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0 0x04e109c0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1 0x04e109d0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_MST_CON 0x04e10c00 /* [RW] MST Control Registers */ |
| #define BCHP_SWITCH_CORE_MST_AGE 0x04e10c08 /* [RW] MST Ageing Control Register */ |
| #define BCHP_SWITCH_CORE_MST_TAB0 0x04e10c40 /* [RW] MST Table 0 Enable Registers */ |
| #define BCHP_SWITCH_CORE_MST_TAB1 0x04e10c50 /* [RW] MST Table 1 Enable Registers */ |
| #define BCHP_SWITCH_CORE_MST_TAB2 0x04e10c60 /* [RW] MST Table 2 Enable Registers */ |
| #define BCHP_SWITCH_CORE_MST_TAB3 0x04e10c70 /* [RW] MST Table 3 Enable Registers */ |
| #define BCHP_SWITCH_CORE_MST_TAB4 0x04e10c80 /* [RW] MST Table 4 Enable Registers */ |
| #define BCHP_SWITCH_CORE_MST_TAB5 0x04e10c90 /* [RW] MST Table 5 Enable Registers */ |
| #define BCHP_SWITCH_CORE_MST_TAB6 0x04e10ca0 /* [RW] MST Table 6 Enable Registers */ |
| #define BCHP_SWITCH_CORE_MST_TAB7 0x04e10cb0 /* [RW] MST Table 7 Enable Registers */ |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL 0x04e10d40 /* [RW] STP Multiport Address Bypass Control Register */ |
| #define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0 0x04e10d80 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1 0x04e10d90 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE 0x04e11400 /* [RW] SA Limit Enable Register */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST 0x04e11408 /* [RW] SA Learned Counters Reset Register */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST 0x04e11410 /* [RW] SA Over Limit Counters Reset Register */ |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL 0x04e11440 /* [RW] Total SA Limit Control Register */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0 0x04e11448 /* [RW] Port 0 SA Limit Control Register */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1 0x04e11450 /* [RW] Port 1 SA Limit Control Register */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2 0x04e11458 /* [RW] Port 2 SA Limit Control Register */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3 0x04e11460 /* [RW] Port 3 SA Limit Control Register */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4 0x04e11468 /* [RW] Port 4 SA Limit Control Register */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5 0x04e11470 /* [RW] Port 5 SA Limit Control Register */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7 0x04e11480 /* [RW] Port 7 SA Limit Control Register */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8 0x04e11488 /* [RW] Port 8 SA Limit Control Register */ |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR 0x04e114c0 /* [RW] Total SA Learned Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0 0x04e114c8 /* [RW] Port 0 SA Learned Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1 0x04e114d0 /* [RW] Port 1 SA Learned Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2 0x04e114d8 /* [RW] Port 2 SA Learned Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3 0x04e114e0 /* [RW] Port 3 SA Learned Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4 0x04e114e8 /* [RW] Port 4 SA Learned Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5 0x04e114f0 /* [RW] Port 5 SA Learned Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7 0x04e11500 /* [RW] Port 7 SA Learned Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8 0x04e11508 /* [RW] Port 8 SA Learned Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P0 0x04e11540 /* [RW] Port 0 SA Over Limit Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P1 0x04e11550 /* [RW] Port 1 SA Over Limit Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P2 0x04e11560 /* [RW] Port 2 SA Over Limit Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P3 0x04e11570 /* [RW] Port 3 SA Over Limit Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P4 0x04e11580 /* [RW] Port 4 SA Over Limit Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P5 0x04e11590 /* [RW] Port 5 SA Over Limit Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P7 0x04e115b0 /* [RW] Port 7 SA Over Limit Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P8 0x04e115c0 /* [RW] Port 8 SA Over Limit Counter Register */ |
| #define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT 0x04e115d0 /* [RW] SA Over Limit Actions Config Register */ |
| #define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0 0x04e11600 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1 0x04e11610 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0 0x04e11800 /* [RW] Port 0 QOS Priority Control Register */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1 0x04e11804 /* [RW] Port 1 QOS Priority Control Register */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2 0x04e11808 /* [RW] Port 2 QOS Priority Control Register */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3 0x04e1180c /* [RW] Port 3 QOS Priority Control Register */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4 0x04e11810 /* [RW] Port 4 QOS Priority Control Register */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5 0x04e11814 /* [RW] Port 5 QOS Priority Control Register */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7 0x04e1181c /* [RW] Port 7 QOS Priority Control Register */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP 0x04e11820 /* [RW] Port 8 QOS Priority Control Register */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0 0x04e11840 /* [RW] Port 0 QOS Weight Register */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1 0x04e11860 /* [RW] Port 1 QOS Weight Register */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2 0x04e11880 /* [RW] Port 2 QOS Weight Register */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3 0x04e118a0 /* [RW] Port 3 QOS Weight Register */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4 0x04e118c0 /* [RW] Port 4 QOS Weight Register */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5 0x04e118e0 /* [RW] Port 5 QOS Weight Register */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7 0x04e11920 /* [RW] Port 7 QOS Weight Register */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP 0x04e11940 /* [RW] Port 8 QOS Weight Register */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P0 0x04e11980 /* [RO] Port 0 WDRR Weight-Scaling Penalty Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P1 0x04e11988 /* [RO] Port 1 WDRR Weight-Scaling Penalty Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P2 0x04e11990 /* [RO] Port 2 WDRR Weight-Scaling Penalty Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P3 0x04e11998 /* [RO] Port 3 WDRR Weight-Scaling Penalty Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P4 0x04e119a0 /* [RO] Port 4 WDRR Weight-Scaling Penalty Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P5 0x04e119a8 /* [RO] Port 5 WDRR Weight-Scaling Penalty Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P7 0x04e119c0 /* [RO] Port 7 WDRR Weight-Scaling Penalty Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_P8_WDRR_PENALTY 0x04e119c8 /* [RO] Port 8 WDRR Weight-Scaling Penalty Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0 0x04e11a00 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1 0x04e11a10 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0 0x04e11c00 /* [RW] Port 0 Byte-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1 0x04e11c10 /* [RW] Port 1 Byte-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2 0x04e11c20 /* [RW] Port 2 Byte-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3 0x04e11c30 /* [RW] Port 3 Byte-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4 0x04e11c40 /* [RW] Port 4 Byte-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5 0x04e11c50 /* [RW] Port 5 Byte-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7 0x04e11c70 /* [RW] Port 7 Byte-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP 0x04e11c80 /* [RW] Port 8 Byte-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0 0x04e11cc0 /* [RW] Port 0 Byte-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1 0x04e11cd0 /* [RW] Port 1 Byte-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2 0x04e11ce0 /* [RW] Port 2 Byte-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3 0x04e11cf0 /* [RW] Port 3 Byte-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4 0x04e11d00 /* [RW] Port 4 Byte-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5 0x04e11d10 /* [RW] Port 5 Byte-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7 0x04e11d30 /* [RW] Port 7 Byte-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP 0x04e11d40 /* [RW] Port 8 Byte-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0 0x04e11d80 /* [RO] Port 0 PORT Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1 0x04e11d90 /* [RO] Port 1 PORT Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2 0x04e11da0 /* [RO] Port 2 PORT Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3 0x04e11db0 /* [RO] Port 3 PORT Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4 0x04e11dc0 /* [RO] Port 4 PORT Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5 0x04e11dd0 /* [RO] Port 5 PORT Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7 0x04e11df0 /* [RO] Port 7 PORT Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP 0x04e11e00 /* [RO] Port 8 PORT Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0 0x04e11e40 /* [RW] Port 0 Packet-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1 0x04e11e50 /* [RW] Port 1 Packet-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2 0x04e11e60 /* [RW] Port 2 Packet-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3 0x04e11e70 /* [RW] Port 3 Packet-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4 0x04e11e80 /* [RW] Port 4 Packet-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5 0x04e11e90 /* [RW] Port 5 Packet-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7 0x04e11eb0 /* [RW] Port 7 Packet-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP 0x04e11ec0 /* [RW] Port 8 Packet-Based, Port Shaper Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0 0x04e11ee0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1 0x04e11ef0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0 0x04e11f00 /* [RW] Port 0 Packet-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1 0x04e11f10 /* [RW] Port 1 Packet-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2 0x04e11f20 /* [RW] Port 2 Packet-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3 0x04e11f30 /* [RW] Port 3 Packet-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4 0x04e11f40 /* [RW] Port 4 Packet-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5 0x04e11f50 /* [RW] Port 5 Packet-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7 0x04e11f70 /* [RW] Port 7 Packet-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP 0x04e11f80 /* [RW] Port 8 Packet-Based, Port Shaper Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE 0x04e11f90 /* [RW] Port Shaper AVB Shaping Mode Control Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE 0x04e11f98 /* [RW] Port Shaper Enable Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT 0x04e11fa0 /* [RW] Port Shaper Bucket Count Select Register */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING 0x04e11fa8 /* [RW] Port Shaper Blocking Control Register */ |
| #define BCHP_SWITCH_CORE_IFG_BYTES 0x04e11fb8 /* [RW] IFG Correction Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0 0x04e12000 /* [RW] Port 0 Byte-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1 0x04e12010 /* [RW] Port 1 Byte-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2 0x04e12020 /* [RW] Port 2 Byte-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3 0x04e12030 /* [RW] Port 3 Byte-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4 0x04e12040 /* [RW] Port 4 Byte-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5 0x04e12050 /* [RW] Port 5 Byte-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7 0x04e12070 /* [RW] Port 7 Byte-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP 0x04e12080 /* [RW] Port 8 Byte-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0 0x04e120c0 /* [RW] Port 0 Byte-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1 0x04e120d0 /* [RW] Port 1 Byte-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2 0x04e120e0 /* [RW] Port 2 Byte-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3 0x04e120f0 /* [RW] Port 3 Byte-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4 0x04e12100 /* [RW] Port 4 Byte-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5 0x04e12110 /* [RW] Port 5 Byte-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7 0x04e12130 /* [RW] Port 7 Byte-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP 0x04e12140 /* [RW] Port 8 Byte-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0 0x04e12180 /* [RO] Port 0 Queue 0 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1 0x04e12190 /* [RO] Port 1 Queue 0 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2 0x04e121a0 /* [RO] Port 2 Queue 0 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3 0x04e121b0 /* [RO] Port 3 Queue 0 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4 0x04e121c0 /* [RO] Port 4 Queue 0 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5 0x04e121d0 /* [RO] Port 5 Queue 0 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7 0x04e121f0 /* [RO] Port 7 Queue 0 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP 0x04e12200 /* [RO] Port 8 Queue 0 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0 0x04e12240 /* [RW] Port 0 Packet-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1 0x04e12250 /* [RW] Port 1 Packet-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2 0x04e12260 /* [RW] Port 2 Packet-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3 0x04e12270 /* [RW] Port 3 Packet-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4 0x04e12280 /* [RW] Port 4 Packet-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5 0x04e12290 /* [RW] Port 5 Packet-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7 0x04e122b0 /* [RW] Port 7 Packet-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP 0x04e122c0 /* [RW] Port 8 Packet-based Queue 0 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 0x04e122e0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 0x04e122f0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0 0x04e12300 /* [RW] Port 0 Packet-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1 0x04e12310 /* [RW] Port 1 Packet-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2 0x04e12320 /* [RW] Port 2 Packet-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3 0x04e12330 /* [RW] Port 3 Packet-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4 0x04e12340 /* [RW] Port 4 Packet-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5 0x04e12350 /* [RW] Port 5 Packet-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7 0x04e12370 /* [RW] Port 7 Packet-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP 0x04e12380 /* [RW] Port 8 Packet-based Queue 0 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE 0x04e12390 /* [RW] Queue 0 AVB Shaping Mode Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE 0x04e12398 /* [RW] Queue 0 Shaper Enable Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT 0x04e123a0 /* [RW] Queue 0 Bucket Count Select Register */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING 0x04e123a8 /* [RW] Queue 0 Shaper Blocking Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0 0x04e12400 /* [RW] Port 0 Byte-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1 0x04e12410 /* [RW] Port 1 Byte-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2 0x04e12420 /* [RW] Port 2 Byte-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3 0x04e12430 /* [RW] Port 3 Byte-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4 0x04e12440 /* [RW] Port 4 Byte-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5 0x04e12450 /* [RW] Port 5 Byte-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7 0x04e12470 /* [RW] Port 7 Byte-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP 0x04e12480 /* [RW] Port 8 Byte-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0 0x04e124c0 /* [RW] Port 0 Byte-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1 0x04e124d0 /* [RW] Port 1 Byte-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2 0x04e124e0 /* [RW] Port 2 Byte-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3 0x04e124f0 /* [RW] Port 3 Byte-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4 0x04e12500 /* [RW] Port 4 Byte-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5 0x04e12510 /* [RW] Port 5 Byte-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7 0x04e12530 /* [RW] Port 7 Byte-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP 0x04e12540 /* [RW] Port 8 Byte-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0 0x04e12580 /* [RO] Port 0 Queue 1 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1 0x04e12590 /* [RO] Port 1 Queue 1 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2 0x04e125a0 /* [RO] Port 2 Queue 1 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3 0x04e125b0 /* [RO] Port 3 Queue 1 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4 0x04e125c0 /* [RO] Port 4 Queue 1 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5 0x04e125d0 /* [RO] Port 5 Queue 1 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7 0x04e125f0 /* [RO] Port 7 Queue 1 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP 0x04e12600 /* [RO] Port 8 Queue 1 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0 0x04e12640 /* [RW] Port 0 Packet-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1 0x04e12650 /* [RW] Port 1 Packet-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2 0x04e12660 /* [RW] Port 2 Packet-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3 0x04e12670 /* [RW] Port 3 Packet-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4 0x04e12680 /* [RW] Port 4 Packet-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5 0x04e12690 /* [RW] Port 5 Packet-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7 0x04e126b0 /* [RW] Port 7 Packet-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP 0x04e126c0 /* [RW] Port 8 Packet-based Queue 1 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 0x04e126e0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 0x04e126f0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0 0x04e12700 /* [RW] Port 0 Packet-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1 0x04e12710 /* [RW] Port 1 Packet-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2 0x04e12720 /* [RW] Port 2 Packet-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3 0x04e12730 /* [RW] Port 3 Packet-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4 0x04e12740 /* [RW] Port 4 Packet-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5 0x04e12750 /* [RW] Port 5 Packet-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7 0x04e12770 /* [RW] Port 7 Packet-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP 0x04e12780 /* [RW] Port 8 Packet-based Queue 1 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE 0x04e12790 /* [RW] Queue 1 AVB Shaping Mode Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE 0x04e12798 /* [RW] Queue 1 Shaper Enable Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT 0x04e127a0 /* [RW] Queue 1 Bucket Count Select Register */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING 0x04e127a8 /* [RW] Queue 1 Shaper Blocking Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0 0x04e12800 /* [RW] Port 0 Byte-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1 0x04e12810 /* [RW] Port 1 Byte-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2 0x04e12820 /* [RW] Port 2 Byte-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3 0x04e12830 /* [RW] Port 3 Byte-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4 0x04e12840 /* [RW] Port 4 Byte-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5 0x04e12850 /* [RW] Port 5 Byte-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7 0x04e12870 /* [RW] Port 7 Byte-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP 0x04e12880 /* [RW] Port 8 Byte-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0 0x04e128c0 /* [RW] Port 0 Byte-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1 0x04e128d0 /* [RW] Port 1 Byte-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2 0x04e128e0 /* [RW] Port 2 Byte-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3 0x04e128f0 /* [RW] Port 3 Byte-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4 0x04e12900 /* [RW] Port 4 Byte-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5 0x04e12910 /* [RW] Port 5 Byte-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7 0x04e12930 /* [RW] Port 7 Byte-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP 0x04e12940 /* [RW] Port 8 Byte-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0 0x04e12980 /* [RO] Port 0 Queue 2 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1 0x04e12990 /* [RO] Port 1 Queue 2 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2 0x04e129a0 /* [RO] Port 2 Queue 2 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3 0x04e129b0 /* [RO] Port 3 Queue 2 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4 0x04e129c0 /* [RO] Port 4 Queue 2 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5 0x04e129d0 /* [RO] Port 5 Queue 2 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7 0x04e129f0 /* [RO] Port 7 Queue 2 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP 0x04e12a00 /* [RO] Port 8 Queue 2 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0 0x04e12a40 /* [RW] Port 0 Packet-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1 0x04e12a50 /* [RW] Port 1 Packet-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2 0x04e12a60 /* [RW] Port 2 Packet-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3 0x04e12a70 /* [RW] Port 3 Packet-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4 0x04e12a80 /* [RW] Port 4 Packet-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5 0x04e12a90 /* [RW] Port 5 Packet-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7 0x04e12ab0 /* [RW] Port 7 Packet-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP 0x04e12ac0 /* [RW] Port 8 Packet-based Queue 2 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 0x04e12ae0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 0x04e12af0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0 0x04e12b00 /* [RW] Port 0 Packet-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1 0x04e12b10 /* [RW] Port 1 Packet-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2 0x04e12b20 /* [RW] Port 2 Packet-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3 0x04e12b30 /* [RW] Port 3 Packet-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4 0x04e12b40 /* [RW] Port 4 Packet-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5 0x04e12b50 /* [RW] Port 5 Packet-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7 0x04e12b70 /* [RW] Port 7 Packet-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP 0x04e12b80 /* [RW] Port 8 Packet-based Queue 2 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE 0x04e12b90 /* [RW] Queue 2 AVB Shaping Mode Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE 0x04e12b98 /* [RW] Queue 2 Shaper Enable Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT 0x04e12ba0 /* [RW] Queue 2 Bucket Count Select Register */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING 0x04e12ba8 /* [RW] Queue 2 Shaper Blocking Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0 0x04e12c00 /* [RW] Port 0 Byte-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1 0x04e12c10 /* [RW] Port 1 Byte-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2 0x04e12c20 /* [RW] Port 2 Byte-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3 0x04e12c30 /* [RW] Port 3 Byte-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4 0x04e12c40 /* [RW] Port 4 Byte-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5 0x04e12c50 /* [RW] Port 5 Byte-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7 0x04e12c70 /* [RW] Port 7 Byte-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP 0x04e12c80 /* [RW] Port 8 Byte-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0 0x04e12cc0 /* [RW] Port 0 Byte-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1 0x04e12cd0 /* [RW] Port 1 Byte-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2 0x04e12ce0 /* [RW] Port 2 Byte-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3 0x04e12cf0 /* [RW] Port 3 Byte-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4 0x04e12d00 /* [RW] Port 4 Byte-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5 0x04e12d10 /* [RW] Port 5 Byte-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7 0x04e12d30 /* [RW] Port 7 Byte-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP 0x04e12d40 /* [RW] Port 8 Byte-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0 0x04e12d80 /* [RO] Port 0 Queue 3 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1 0x04e12d90 /* [RO] Port 1 Queue 3 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2 0x04e12da0 /* [RO] Port 2 Queue 3 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3 0x04e12db0 /* [RO] Port 3 Queue 3 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4 0x04e12dc0 /* [RO] Port 4 Queue 3 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5 0x04e12dd0 /* [RO] Port 5 Queue 3 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7 0x04e12df0 /* [RO] Port 7 Queue 3 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP 0x04e12e00 /* [RO] Port 8 Queue 3 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0 0x04e12e40 /* [RW] Port 0 Packet-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1 0x04e12e50 /* [RW] Port 1 Packet-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2 0x04e12e60 /* [RW] Port 2 Packet-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3 0x04e12e70 /* [RW] Port 3 Packet-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4 0x04e12e80 /* [RW] Port 4 Packet-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5 0x04e12e90 /* [RW] Port 5 Packet-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7 0x04e12eb0 /* [RW] Port 7 Packet-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP 0x04e12ec0 /* [RW] Port 8 Packet-based Queue 3 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 0x04e12ee0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 0x04e12ef0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0 0x04e12f00 /* [RW] Port 0 Packet-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1 0x04e12f10 /* [RW] Port 1 Packet-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2 0x04e12f20 /* [RW] Port 2 Packet-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3 0x04e12f30 /* [RW] Port 3 Packet-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4 0x04e12f40 /* [RW] Port 4 Packet-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5 0x04e12f50 /* [RW] Port 5 Packet-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7 0x04e12f70 /* [RW] Port 7 Packet-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP 0x04e12f80 /* [RW] Port 8 Packet-based Queue 3 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE 0x04e12f90 /* [RW] Queue 3 AVB Shaping Mode Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE 0x04e12f98 /* [RW] Queue 3 Shaper Enable Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT 0x04e12fa0 /* [RW] Queue 3 Bucket Count Select Register */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING 0x04e12fa8 /* [RW] Queue 3 Shaper Blocking Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0 0x04e13000 /* [RW] Port 0 Byte-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1 0x04e13010 /* [RW] Port 1 Byte-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2 0x04e13020 /* [RW] Port 2 Byte-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3 0x04e13030 /* [RW] Port 3 Byte-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4 0x04e13040 /* [RW] Port 4 Byte-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5 0x04e13050 /* [RW] Port 5 Byte-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7 0x04e13070 /* [RW] Port 7 Byte-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP 0x04e13080 /* [RW] Port 8 Byte-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0 0x04e130c0 /* [RW] Port 0 Byte-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1 0x04e130d0 /* [RW] Port 1 Byte-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2 0x04e130e0 /* [RW] Port 2 Byte-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3 0x04e130f0 /* [RW] Port 3 Byte-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4 0x04e13100 /* [RW] Port 4 Byte-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5 0x04e13110 /* [RW] Port 5 Byte-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7 0x04e13130 /* [RW] Port 7 Byte-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP 0x04e13140 /* [RW] Port 8 Byte-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0 0x04e13180 /* [RO] Port 0 Queue 4 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1 0x04e13190 /* [RO] Port 1 Queue 4 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2 0x04e131a0 /* [RO] Port 2 Queue 4 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3 0x04e131b0 /* [RO] Port 3 Queue 4 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4 0x04e131c0 /* [RO] Port 4 Queue 4 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5 0x04e131d0 /* [RO] Port 5 Queue 4 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7 0x04e131f0 /* [RO] Port 7 Queue 4 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP 0x04e13200 /* [RO] Port 8 Queue 4 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0 0x04e13240 /* [RW] Port 0 Packet-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1 0x04e13250 /* [RW] Port 1 Packet-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2 0x04e13260 /* [RW] Port 2 Packet-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3 0x04e13270 /* [RW] Port 3 Packet-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4 0x04e13280 /* [RW] Port 4 Packet-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5 0x04e13290 /* [RW] Port 5 Packet-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7 0x04e132b0 /* [RW] Port 7 Packet-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP 0x04e132c0 /* [RW] Port 8 Packet-based Queue 4 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 0x04e132e0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 0x04e132f0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0 0x04e13300 /* [RW] Port 0 Packet-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1 0x04e13310 /* [RW] Port 1 Packet-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2 0x04e13320 /* [RW] Port 2 Packet-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3 0x04e13330 /* [RW] Port 3 Packet-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4 0x04e13340 /* [RW] Port 4 Packet-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5 0x04e13350 /* [RW] Port 5 Packet-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7 0x04e13370 /* [RW] Port 7 Packet-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP 0x04e13380 /* [RW] Port 8 Packet-based Queue 4 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE 0x04e13390 /* [RW] Queue 4 AVB Shaping Mode Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE 0x04e13398 /* [RW] Queue 4 Shaper Enable Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT 0x04e133a0 /* [RW] Queue 4 Bucket Count Select Register */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING 0x04e133a8 /* [RW] Queue 4 Shaper Blocking Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0 0x04e13400 /* [RW] Port 0 Byte-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1 0x04e13410 /* [RW] Port 1 Byte-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2 0x04e13420 /* [RW] Port 2 Byte-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3 0x04e13430 /* [RW] Port 3 Byte-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4 0x04e13440 /* [RW] Port 4 Byte-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5 0x04e13450 /* [RW] Port 5 Byte-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7 0x04e13470 /* [RW] Port 7 Byte-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP 0x04e13480 /* [RW] Port 8 Byte-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0 0x04e134c0 /* [RW] Port 0 Byte-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1 0x04e134d0 /* [RW] Port 1 Byte-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2 0x04e134e0 /* [RW] Port 2 Byte-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3 0x04e134f0 /* [RW] Port 3 Byte-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4 0x04e13500 /* [RW] Port 4 Byte-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5 0x04e13510 /* [RW] Port 5 Byte-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7 0x04e13530 /* [RW] Port 7 Byte-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP 0x04e13540 /* [RW] Port 8 Byte-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0 0x04e13580 /* [RO] Port 0 Queue 5 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1 0x04e13590 /* [RO] Port 1 Queue 5 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2 0x04e135a0 /* [RO] Port 2 Queue 5 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3 0x04e135b0 /* [RO] Port 3 Queue 5 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4 0x04e135c0 /* [RO] Port 4 Queue 5 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5 0x04e135d0 /* [RO] Port 5 Queue 5 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7 0x04e135f0 /* [RO] Port 7 Queue 5 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP 0x04e13600 /* [RO] Port 8 Queue 5 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0 0x04e13640 /* [RW] Port 0 Packet-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1 0x04e13650 /* [RW] Port 1 Packet-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2 0x04e13660 /* [RW] Port 2 Packet-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3 0x04e13670 /* [RW] Port 3 Packet-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4 0x04e13680 /* [RW] Port 4 Packet-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5 0x04e13690 /* [RW] Port 5 Packet-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7 0x04e136b0 /* [RW] Port 7 Packet-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP 0x04e136c0 /* [RW] Port 8 Packet-based Queue 5 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 0x04e136e0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 0x04e136f0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0 0x04e13700 /* [RW] Port 0 Packet-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1 0x04e13710 /* [RW] Port 1 Packet-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2 0x04e13720 /* [RW] Port 2 Packet-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3 0x04e13730 /* [RW] Port 3 Packet-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4 0x04e13740 /* [RW] Port 4 Packet-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5 0x04e13750 /* [RW] Port 5 Packet-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7 0x04e13770 /* [RW] Port 7 Packet-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP 0x04e13780 /* [RW] Port 8 Packet-based Queue 5 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE 0x04e13790 /* [RW] Queue 5 AVB Shaping Mode Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE 0x04e13798 /* [RW] Queue 5 Shaper Enable Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT 0x04e137a0 /* [RW] Queue 5 Bucket Count Select Register */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING 0x04e137a8 /* [RW] Queue 5 Shaper Blocking Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0 0x04e13800 /* [RW] Port 0 Byte-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1 0x04e13810 /* [RW] Port 1 Byte-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2 0x04e13820 /* [RW] Port 2 Byte-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3 0x04e13830 /* [RW] Port 3 Byte-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4 0x04e13840 /* [RW] Port 4 Byte-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5 0x04e13850 /* [RW] Port 5 Byte-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7 0x04e13870 /* [RW] Port 7 Byte-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP 0x04e13880 /* [RW] Port 8 Byte-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0 0x04e138c0 /* [RW] Port 0 Byte-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1 0x04e138d0 /* [RW] Port 1 Byte-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2 0x04e138e0 /* [RW] Port 2 Byte-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3 0x04e138f0 /* [RW] Port 3 Byte-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4 0x04e13900 /* [RW] Port 4 Byte-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5 0x04e13910 /* [RW] Port 5 Byte-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7 0x04e13930 /* [RW] Port 7 Byte-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP 0x04e13940 /* [RW] Port 8 Byte-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0 0x04e13980 /* [RO] Port 0 Queue 6 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1 0x04e13990 /* [RO] Port 1 Queue 6 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2 0x04e139a0 /* [RO] Port 2 Queue 6 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3 0x04e139b0 /* [RO] Port 3 Queue 6 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4 0x04e139c0 /* [RO] Port 4 Queue 6 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5 0x04e139d0 /* [RO] Port 5 Queue 6 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7 0x04e139f0 /* [RO] Port 7 Queue 6 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP 0x04e13a00 /* [RO] Port 8 Queue 6 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0 0x04e13a40 /* [RW] Port 0 Packet-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1 0x04e13a50 /* [RW] Port 1 Packet-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2 0x04e13a60 /* [RW] Port 2 Packet-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3 0x04e13a70 /* [RW] Port 3 Packet-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4 0x04e13a80 /* [RW] Port 4 Packet-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5 0x04e13a90 /* [RW] Port 5 Packet-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7 0x04e13ab0 /* [RW] Port 7 Packet-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP 0x04e13ac0 /* [RW] Port 8 Packet-based Queue 6 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 0x04e13ae0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 0x04e13af0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0 0x04e13b00 /* [RW] Port 0 Packet-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1 0x04e13b10 /* [RW] Port 1 Packet-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2 0x04e13b20 /* [RW] Port 2 Packet-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3 0x04e13b30 /* [RW] Port 3 Packet-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4 0x04e13b40 /* [RW] Port 4 Packet-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5 0x04e13b50 /* [RW] Port 5 Packet-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7 0x04e13b70 /* [RW] Port 7 Packet-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP 0x04e13b80 /* [RW] Port 8 Packet-based Queue 6 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE 0x04e13b90 /* [RW] Queue 6 AVB Shaping Mode Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE 0x04e13b98 /* [RW] Queue 6 Shaper Enable Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT 0x04e13ba0 /* [RW] Queue 6 Bucket Count Select Register */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING 0x04e13ba8 /* [RW] Queue 6 Shaper Blocking Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0 0x04e13c00 /* [RW] Port 0 Byte-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1 0x04e13c10 /* [RW] Port 1 Byte-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2 0x04e13c20 /* [RW] Port 2 Byte-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3 0x04e13c30 /* [RW] Port 3 Byte-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4 0x04e13c40 /* [RW] Port 4 Byte-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5 0x04e13c50 /* [RW] Port 5 Byte-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7 0x04e13c70 /* [RW] Port 7 Byte-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP 0x04e13c80 /* [RW] Port 8 Byte-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0 0x04e13cc0 /* [RW] Port 0 Byte-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1 0x04e13cd0 /* [RW] Port 1 Byte-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2 0x04e13ce0 /* [RW] Port 2 Byte-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3 0x04e13cf0 /* [RW] Port 3 Byte-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4 0x04e13d00 /* [RW] Port 4 Byte-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5 0x04e13d10 /* [RW] Port 5 Byte-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7 0x04e13d30 /* [RW] Port 7 Byte-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP 0x04e13d40 /* [RW] Port 8 Byte-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0 0x04e13d80 /* [RO] Port 0 Queue 7 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1 0x04e13d90 /* [RO] Port 1 Queue 7 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2 0x04e13da0 /* [RO] Port 2 Queue 7 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3 0x04e13db0 /* [RO] Port 3 Queue 7 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4 0x04e13dc0 /* [RO] Port 4 Queue 7 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5 0x04e13dd0 /* [RO] Port 5 Queue 7 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7 0x04e13df0 /* [RO] Port 7 Queue 7 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP 0x04e13e00 /* [RO] Port 8 Queue 7 Shaper Status Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0 0x04e13e40 /* [RW] Port 0 Packet-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1 0x04e13e50 /* [RW] Port 1 Packet-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2 0x04e13e60 /* [RW] Port 2 Packet-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3 0x04e13e70 /* [RW] Port 3 Packet-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4 0x04e13e80 /* [RW] Port 4 Packet-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5 0x04e13e90 /* [RW] Port 5 Packet-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7 0x04e13eb0 /* [RW] Port 7 Packet-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP 0x04e13ec0 /* [RW] Port 8 Packet-based Queue 7 Shaping Rate Configure Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 0x04e13ee0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 0x04e13ef0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0 0x04e13f00 /* [RW] Port 0 Packet-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1 0x04e13f10 /* [RW] Port 1 Packet-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2 0x04e13f20 /* [RW] Port 2 Packet-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3 0x04e13f30 /* [RW] Port 3 Packet-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4 0x04e13f40 /* [RW] Port 4 Packet-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5 0x04e13f50 /* [RW] Port 5 Packet-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7 0x04e13f70 /* [RW] Port 7 Packet-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP 0x04e13f80 /* [RW] Port 8 Packet-based Queue 7 Burst Size Configure Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE 0x04e13f90 /* [RW] Queue 7 AVB Shaping Mode Control Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE 0x04e13f98 /* [RW] Queue 7 Shaper Enable Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT 0x04e13fa0 /* [RW] Queue 7 Bucket Count Select Register */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING 0x04e13fa8 /* [RW] Queue 7 Shaper Blocking Control Register */ |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL 0x04e1c000 /* [RW] MIB Snapshot Control Register */ |
| #define BCHP_SWITCH_CORE_S_TxOctets 0x04e1c400 /* [RO] Tx Octets */ |
| #define BCHP_SWITCH_CORE_S_TxDropPkts 0x04e1c420 /* [RO] Tx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ0 0x04e1c430 /* [RO] Tx Q0 Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_TxBroadcastPkts 0x04e1c440 /* [RO] Tx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_TxMulticastPkts 0x04e1c450 /* [RO] Tx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_TxUnicastPkts 0x04e1c460 /* [RO] Tx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_TxCollisions 0x04e1c470 /* [RO] Tx Collision Counter */ |
| #define BCHP_SWITCH_CORE_S_TxSingleCollision 0x04e1c480 /* [RO] Tx Single Collision Counter */ |
| #define BCHP_SWITCH_CORE_S_TxMultipleCollision 0x04e1c490 /* [RO] Tx Multiple collsion Counter */ |
| #define BCHP_SWITCH_CORE_S_TxDeferredTransmit 0x04e1c4a0 /* [RO] Tx Deferred Transmit Counter */ |
| #define BCHP_SWITCH_CORE_S_TxLateCollision 0x04e1c4b0 /* [RO] Tx Late Collision Counter */ |
| #define BCHP_SWITCH_CORE_S_TxExcessiveCollision 0x04e1c4c0 /* [RO] Tx Excessive Collision Counter */ |
| #define BCHP_SWITCH_CORE_S_TxFrameInDisc 0x04e1c4d0 /* [RO] Tx Fram IN Disc Counter */ |
| #define BCHP_SWITCH_CORE_S_TxPausePkts 0x04e1c4e0 /* [RO] Tx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ1 0x04e1c4f0 /* [RO] Tx Q1 Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ2 0x04e1c500 /* [RO] Tx Q2 Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ3 0x04e1c510 /* [RO] Tx Q3 Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ4 0x04e1c520 /* [RO] Tx Q4 Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ5 0x04e1c530 /* [RO] Tx Q5 Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_RxOctets 0x04e1c540 /* [RO] Rx Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_RxUndersizePkts 0x04e1c560 /* [RO] Rx Under Size Packet Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_RxPausePkts 0x04e1c570 /* [RO] Rx Pause Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_RxPkts64Octets 0x04e1c580 /* [RO] Rx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_RxPkts65to127Octets 0x04e1c590 /* [RO] Rx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_RxPkts128to255Octets 0x04e1c5a0 /* [RO] Rx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_RxPkts256to511Octets 0x04e1c5b0 /* [RO] Rx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets 0x04e1c5c0 /* [RO] Rx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets 0x04e1c5d0 /* [RO] Rx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_RxOversizePkts 0x04e1c5e0 /* [RO] Rx Over Size Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_RxJabbers 0x04e1c5f0 /* [RO] Rx Jabber Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_RxAlignmentErrors 0x04e1c600 /* [RO] Rx Alignment Error Counter */ |
| #define BCHP_SWITCH_CORE_S_RxFCSErrors 0x04e1c610 /* [RO] Rx FCS Error Counter */ |
| #define BCHP_SWITCH_CORE_S_RxGoodOctets 0x04e1c620 /* [RO] Rx Good Packet Octet Counter */ |
| #define BCHP_SWITCH_CORE_S_RxDropPkts 0x04e1c640 /* [RO] Rx Drop Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_RxUnicastPkts 0x04e1c650 /* [RO] Rx Unicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_RxMulticastPkts 0x04e1c660 /* [RO] Rx Multicast Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_RxBroadcastPkts 0x04e1c670 /* [RO] Rx Broadcast Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_RxSAChanges 0x04e1c680 /* [RO] Rx SA Change Counter */ |
| #define BCHP_SWITCH_CORE_S_RxFragments 0x04e1c690 /* [RO] Rx Fragment Counter */ |
| #define BCHP_SWITCH_CORE_S_RxJumboPkt 0x04e1c6a0 /* [RO] Jumbo Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_RxSymblErr 0x04e1c6b0 /* [RO] Rx Symbol Error Counter */ |
| #define BCHP_SWITCH_CORE_S_InRangeErrCount 0x04e1c6c0 /* [RO] InRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_S_OutRangeErrCount 0x04e1c6d0 /* [RO] OutRangeErrCount Counter */ |
| #define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT 0x04e1c6e0 /* [RO] EEE Low-Power Idle Event Registers */ |
| #define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION 0x04e1c6f0 /* [RO] EEE Low-Power Idle Duration Registers */ |
| #define BCHP_SWITCH_CORE_S_RxDiscard 0x04e1c700 /* [RO] Rx Discard Counter */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ6 0x04e1c720 /* [RO] Tx Q6 Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ7 0x04e1c730 /* [RO] Tx Q7 Packet Counter */ |
| #define BCHP_SWITCH_CORE_S_TxPkts64Octets 0x04e1c740 /* [RO] Tx 64 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_TxPkts65to127Octets 0x04e1c750 /* [RO] Tx 65 to 127 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_TxPkts128to255Octets 0x04e1c760 /* [RO] Tx 128 to 255 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_TxPkts256to511Octets 0x04e1c770 /* [RO] Tx 256 to 511 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets 0x04e1c780 /* [RO] Tx 512 to 1023 Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets 0x04e1c790 /* [RO] Tx 1024 to MaxPkt Bytes Octets Counter */ |
| #define BCHP_SWITCH_CORE_LPDET_CFG 0x04e1c800 /* [RW] Loop Detection Configuration RegistersNot2Release */ |
| #define BCHP_SWITCH_CORE_DF_TIMER 0x04e1c808 /* [RW] Discovery Frame Timer RegistersNot2Release */ |
| #define BCHP_SWITCH_CORE_LED_PORTMAP 0x04e1c80c /* [RO] LED Waming Portmap RegistersNot2Release */ |
| #define BCHP_SWITCH_CORE_MODULE_ID0 0x04e1c814 /* [RO] Module ID 0 RegistersNot2Release */ |
| #define BCHP_SWITCH_CORE_MODULE_ID1 0x04e1c82c /* [RO] Module ID 1 RegistersNot2Release */ |
| #define BCHP_SWITCH_CORE_LPDET_SA 0x04e1c844 /* [RW] Loop Detect Frame SA RegistersNot2Release */ |
| #define BCHP_SWITCH_CORE_LPDET_REG_SPARE0 0x04e1c880 /* [RW] Spare 0 Register (Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_LPDET_REG_SPARE1 0x04e1c890 /* [RW] Spare 1 Register (Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_BPM_CTRL 0x04e1cc00 /* [RW] BPM Power Switching Control Register Not2Release */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL 0x04e1cc04 /* [RW] BPM Power Switching SW Override Register Not2Release */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG 0x04e1cc08 /* [RW] PSM_VDD Timing Parameter Configuration Register Not2Release */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG 0x04e1cc10 /* [RW] PSM_VDD Switching Threshold Configuration Register Not2Release */ |
| #define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL 0x04e1cc20 /* [RW] BUFCON Row Status Valid Mask SW Override Control Register Not2Release */ |
| #define BCHP_SWITCH_CORE_BPM_STS 0x04e1cc30 /* [RO] BPM Status Register Not2Release */ |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL 0x04e1cc40 /* [RW] BPM PDA Switching SW Override Control Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG 0x04e1cc48 /* [RW] BPM PDA Switching Timeout Counter Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG 0x04e1cc50 /* [RW] BPM PDA Switching Setup Time Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG 0x04e1cc58 /* [RW] BPM PDA Switching Hold Time Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0 0x04e1cc60 /* [RO] Packet Buffer Block 0 Valid Buffer Count Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1 0x04e1cc68 /* [RO] Packet Buffer Block 1 Valid Buffer Count Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2 0x04e1cc70 /* [RO] Packet Buffer Block 2 Valid Buffer Count Register Not2Release */ |
| #define BCHP_SWITCH_CORE_RCY_TIME_CFG 0x04e1cc78 /* [RW] Recycling Check Pulse Period Counter Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL 0x04e1cc80 /* [RW] PBB Powerdown Monitor Control Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON0 0x04e1cca0 /* [RO] PBB Powerdown Time Monitor 0 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON1 0x04e1ccc0 /* [RO] PBB Powerdown Time Monitor 1 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON2 0x04e1cce0 /* [RO] PBB Powerdown Time Monitor 2 Register Not2Release */ |
| #define BCHP_SWITCH_CORE_BPM_REG_SPARE0 0x04e1cd80 /* [RW] Spare 0 Register (Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_BPM_REG_SPARE1 0x04e1cd90 /* [RW] Spare 1 Register (Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0 0x04e24400 /* [RW] Traffic Remarking Control 0 Register */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1 0x04e24410 /* [RW] Traffic Remarking Control 1 Register */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2 0x04e24420 /* [RW] Traffic Remarking Control 2 Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0 0x04e24440 /* [RW] Port 0 Egress TC to PCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1 0x04e24460 /* [RW] Port 1 Egress TC to PCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2 0x04e24480 /* [RW] Port 2 Egress TC to PCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3 0x04e244a0 /* [RW] Port 3 Egress TC to PCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4 0x04e244c0 /* [RW] Port 4 Egress TC to PCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5 0x04e244e0 /* [RW] Port 5 Egress TC to PCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7 0x04e24520 /* [RW] Port 7 Egress TC to PCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP 0x04e24540 /* [RW] Port 8 Egress TC to PCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0 0x04e24580 /* [RW] Port 0 Egress TC to CPCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1 0x04e245a0 /* [RW] Port 1 Egress TC to CPCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2 0x04e245c0 /* [RW] Port 2 Egress TC to CPCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3 0x04e245e0 /* [RW] Port 3 Egress TC to CPCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4 0x04e24600 /* [RW] Port 4 Egress TC to CPCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5 0x04e24620 /* [RW] Port 5 Egress TC to CPCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7 0x04e24660 /* [RW] Port 7 Egress TC to CPCP mapping Register */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP 0x04e24680 /* [RW] Port 8 Egress TC to CPCP mapping Register */ |
| #define BCHP_SWITCH_CORE_TRREG_REG_SPARE0 0x04e246c0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_TRREG_REG_SPARE1 0x04e246d0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EEE_EN_CTRL 0x04e24800 /* [RW] EEE Enable Control Registers */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_ASSERT 0x04e24808 /* [RO] EEE Low Power Assert Status Registers */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_INDICATE 0x04e24810 /* [RO] EEE Low Power Indicate Status Registers */ |
| #define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL 0x04e24818 /* [RO] EEE Receiving Idle Symbols Status Registers */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE 0x04e24820 /* [RW] EEE LPI Symbol Transmit Disable Registers(Not2Release) */ |
| #define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER 0x04e24830 /* [RW] EEE Pipeline Delay Timer Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P0 0x04e24840 /* [RW] EEE Port 0 Sleep Delay Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P1 0x04e24850 /* [RW] EEE Port 1 Sleep Delay Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P2 0x04e24860 /* [RW] EEE Port 2 Sleep Delay Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P3 0x04e24870 /* [RW] EEE Port 3 Sleep Delay Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P4 0x04e24880 /* [RW] EEE Port 4 Sleep Delay Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P5 0x04e24890 /* [RW] EEE Port 5 Sleep Delay Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7 0x04e248b0 /* [RW] EEE Port 7 Sleep Delay Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP 0x04e248c0 /* [RW] EEE Port 8(IMP) Sleep Delay Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P0 0x04e248d0 /* [RW] EEE Port 0 Sleep Delay Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P1 0x04e248e0 /* [RW] EEE Port 1 Sleep Delay Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P2 0x04e248f0 /* [RW] EEE Port 2 Sleep Delay Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P3 0x04e24900 /* [RW] EEE Port 3 Sleep Delay Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P4 0x04e24910 /* [RW] EEE Port 4 Sleep Delay Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P5 0x04e24920 /* [RW] EEE Port 5 Sleep Delay Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7 0x04e24940 /* [RW] EEE Port 7 Sleep Delay Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP 0x04e24950 /* [RW] EEE Port 8(IMP) Sleep Delay Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P0 0x04e24960 /* [RW] EEE Port Minimum Low-Power Duration Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P1 0x04e24970 /* [RW] EEE Port Minimum Low-Power Duration Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P2 0x04e24980 /* [RW] EEE Port Minimum Low-Power Duration Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P3 0x04e24990 /* [RW] EEE Port Minimum Low-Power Duration Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P4 0x04e249a0 /* [RW] EEE Port Minimum Low-Power Duration Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P5 0x04e249b0 /* [RW] EEE Port Minimum Low-Power Duration Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7 0x04e249d0 /* [RW] EEE Port 7 Minimum Low-Power Duration Timer Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP 0x04e249e0 /* [RW] EEE Port 8(IMP) Minimum Low-Power Duration Timer Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P0 0x04e249f0 /* [RW] EEE Port Minimum Low-Power Duration Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P1 0x04e24a00 /* [RW] EEE Port Minimum Low-Power Duration Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P2 0x04e24a10 /* [RW] EEE Port Minimum Low-Power Duration Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P3 0x04e24a20 /* [RW] EEE Port Minimum Low-Power Duration Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P4 0x04e24a30 /* [RW] EEE Port Minimum Low-Power Duration Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P5 0x04e24a40 /* [RW] EEE Port Minimum Low-Power Duration Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7 0x04e24a60 /* [RW] EEE Port 7 Minimum Low-Power Duration Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP 0x04e24a70 /* [RW] EEE Port 8(IMP) Minimum Low-Power Duration Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P0 0x04e24a80 /* [RW] EEE Port 0 Wake Transition Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P1 0x04e24a88 /* [RW] EEE Port 1 Wake Transition Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P2 0x04e24a90 /* [RW] EEE Port 2 Wake Transition Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P3 0x04e24a98 /* [RW] EEE Port 3 Wake Transition Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P4 0x04e24aa0 /* [RW] EEE Port 4 Wake Transition Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P5 0x04e24aa8 /* [RW] EEE Port 5 Wake Transition Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7 0x04e24ab8 /* [RW] EEE Port 7 Wake Transition Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P8 0x04e24ac0 /* [RW] EEE Port 8(IMP) Wake Transition Timer - 1G Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P0 0x04e24ac8 /* [RW] EEE Port 0 Wake Transition Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P1 0x04e24ad0 /* [RW] EEE Port 1 Wake Transition Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P2 0x04e24ad8 /* [RW] EEE Port 2 Wake Transition Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P3 0x04e24ae0 /* [RW] EEE Port 3 Wake Transition Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P4 0x04e24ae8 /* [RW] EEE Port 4 Wake Transition Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P5 0x04e24af0 /* [RW] EEE Port 5 Wake Transition Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7 0x04e24b00 /* [RW] EEE Port 7 Wake Transition Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP 0x04e24b08 /* [RW] EEE Port 8(IMP) Wake Transition Timer - 100M Registers */ |
| #define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH 0x04e24b10 /* [RW] EEE Global Congestion Threshold Registers */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0 0x04e24b18 /* [RW] EEE TXQ 0 Congestion Threshold Registers */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1 0x04e24b20 /* [RW] EEE TXQ 1 Congestion Threshold Registers */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2 0x04e24b28 /* [RW] EEE TXQ 2 Congestion Threshold Registers */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3 0x04e24b30 /* [RW] EEE TXQ 3 Congestion Threshold Registers */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4 0x04e24b38 /* [RW] EEE TXQ 4 Congestion Threshold Registers */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5 0x04e24b40 /* [RW] EEE TXQ 5 Congestion Threshold Registers */ |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL 0x04e24b48 /* [RW] EEE PHY Control Registers(Not2Release) */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6 0x04e24b4c /* [RW] EEE TXQ 6 Congestion Threshold Registers */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7 0x04e24b54 /* [RW] EEE TXQ 7 Congestion Threshold Registers */ |
| #define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0 0x04e24b6c /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1 0x04e24b80 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_EEE_DEBUG 0x04e24b9c /* [RW] EEE Debug Registers(Not2Release) */ |
| #define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER 0x04e24ba0 /* [RW] EEE Link Delay Timer Registers(Not2Release) */ |
| #define BCHP_SWITCH_CORE_EEE_STATE 0x04e24bb0 /* [RO] EEE Control Policy State Registers(Not2Release) */ |
| #define BCHP_SWITCH_CORE_RED_CONTROL 0x04e25400 /* [RW] RED Control Register */ |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE 0x04e25408 /* [RW] RED Table Configuration Register */ |
| #define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS 0x04e25410 /* [RW] RED Egress Bypass Register */ |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL 0x04e25418 /* [RW] RED AQD Control Register */ |
| #define BCHP_SWITCH_CORE_RED_EXPONENT 0x04e25420 /* [RW] RED AQD Weighted Factor Register */ |
| #define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB 0x04e25428 /* [RW] RED Drop Add to MIB Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT 0x04e25440 /* [RW] Default RED profile Register */ |
| #define BCHP_SWITCH_CORE_WRED_REG_SPARE0 0x04e25450 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_WRED_REG_SPARE1 0x04e25460 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE0 0x04e25480 /* [RW] RED profile 0 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE1 0x04e25490 /* [RW] RED profile 1 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE2 0x04e254a0 /* [RW] RED profile 2 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE3 0x04e254b0 /* [RW] RED profile 3 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE4 0x04e254c0 /* [RW] RED profile 4 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE5 0x04e254d0 /* [RW] RED profile 5 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE6 0x04e254e0 /* [RW] RED profile 6 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE7 0x04e254f0 /* [RW] RED profile 7 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE8 0x04e25500 /* [RW] RED profile 8 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE9 0x04e25510 /* [RW] RED profile 9 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE10 0x04e25520 /* [RW] RED profile 10 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE11 0x04e25530 /* [RW] RED profile 11 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE12 0x04e25540 /* [RW] RED profile 12 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE13 0x04e25550 /* [RW] RED profile 13 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE14 0x04e25560 /* [RW] RED profile 14 Register */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE15 0x04e25570 /* [RW] RED profile 15 Register */ |
| #define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST 0x04e255b0 /* [RW] RED Drop Counter Reset Register */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P0 0x04e255c0 /* [RO] PORT 0 RED Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P1 0x04e255d0 /* [RO] PORT 1 RED Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P2 0x04e255e0 /* [RO] PORT 2 RED Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P3 0x04e255f0 /* [RO] PORT 3 RED Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P4 0x04e25600 /* [RO] PORT 4 RED Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P5 0x04e25610 /* [RO] PORT 5 RED Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P7 0x04e25630 /* [RO] PORT 7 RED Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_IMP 0x04e25640 /* [RO] PORT 8 RED Packet Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P0 0x04e25680 /* [RO] PORT 0 RED Byte Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P1 0x04e256a0 /* [RO] PORT 1 RED Byte Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P2 0x04e256c0 /* [RO] PORT 2 RED Byte Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P3 0x04e256e0 /* [RO] PORT 3 RED Byte Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P4 0x04e25700 /* [RO] PORT 4 RED Byte Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P5 0x04e25720 /* [RO] PORT 5 RED Byte Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P7 0x04e25760 /* [RO] PORT 7 RED Byte Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_IMP 0x04e25780 /* [RO] PORT 8 RED Byte Drop Counter Register */ |
| #define BCHP_SWITCH_CORE_CFP_ACC 0x04e28000 /* [RW] CFP Access Registers */ |
| #define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL 0x04e28010 /* [RW] CFP RATE METER Global Control Registers */ |
| #define BCHP_SWITCH_CORE_CFP_DATA0 0x04e28040 /* [RW] CFP TCAM Data 0 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_DATA1 0x04e28050 /* [RW] CFP TCAM Data 1 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_DATA2 0x04e28060 /* [RW] CFP TCAM Data 2 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_DATA3 0x04e28070 /* [RW] CFP TCAM Data 3 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_DATA4 0x04e28080 /* [RW] CFP TCAM Data 4 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_DATA5 0x04e28090 /* [RW] CFP TCAM Data 5 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_DATA6 0x04e280a0 /* [RW] CFP TCAM Data 6 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_DATA7 0x04e280b0 /* [RW] CFP TCAM Data 7 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_MASK0 0x04e280c0 /* [RW] CFP TCAM Mask 0 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_MASK1 0x04e280d0 /* [RW] CFP TCAM Mask 1 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_MASK2 0x04e280e0 /* [RW] CFP TCAM Mask 2 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_MASK3 0x04e280f0 /* [RW] CFP TCAM Mask 3 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_MASK4 0x04e28100 /* [RW] CFP TCAM Mask 4 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_MASK5 0x04e28110 /* [RW] CFP TCAM Mask 5 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_MASK6 0x04e28120 /* [RW] CFP TCAM Mask 6 Registers */ |
| #define BCHP_SWITCH_CORE_CFP_MASK7 0x04e28130 /* [RW] CFP TCAM Mask 7 Registers */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0 0x04e28140 /* [RW] CFP Action/Policy Data 0 Registers */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1 0x04e28150 /* [RW] CFP Action/Policy Data 1 Registers */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2 0x04e28160 /* [RW] CFP Action/Policy Data 2 Registers */ |
| #define BCHP_SWITCH_CORE_RATE_METER0 0x04e28180 /* [RW] CFP RATE METER DATA 0 Registers */ |
| #define BCHP_SWITCH_CORE_RATE_METER1 0x04e28190 /* [RW] CFP RATE METER DATA 1 Registers */ |
| #define BCHP_SWITCH_CORE_RATE_METER2 0x04e281a0 /* [RW] CFP RATE METER DATA 2 Registers */ |
| #define BCHP_SWITCH_CORE_RATE_METER3 0x04e281b0 /* [RW] CFP RATE METER DATA 3 Registers */ |
| #define BCHP_SWITCH_CORE_RATE_METER4 0x04e281c0 /* [RW] CFP RATE METER DATA 4 Registers */ |
| #define BCHP_SWITCH_CORE_RATE_METER5 0x04e281d0 /* [RW] CFP RATE METER DATA 5 Registers */ |
| #define BCHP_SWITCH_CORE_RATE_METER6 0x04e281e0 /* [RW] CFP RATE METER DATA 6 Registers */ |
| #define BCHP_SWITCH_CORE_TC2COLOR 0x04e281f0 /* [RW] TC to COLOR Mapping Registers */ |
| #define BCHP_SWITCH_CORE_STAT_GREEN_CNTR 0x04e28200 /* [RW] Policer Green color statistic counter */ |
| #define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR 0x04e28210 /* [RW] Policer Yellow color statistic counter */ |
| #define BCHP_SWITCH_CORE_STAT_RED_CNTR 0x04e28220 /* [RW] Policer RED color statistic counter */ |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL 0x04e28280 /* [RW] TCAM BIST Control Registers (Not2Release) */ |
| #define BCHP_SWITCH_CORE_TCAM_BIST_STATUS 0x04e28290 /* [RO] TCAM BIST Status Registers (Not2Release) */ |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS 0x04e282a0 /* [RO] TCAM Test Compare Status Registers (Not2Release) */ |
| #define BCHP_SWITCH_CORE_CFP_REG_SPARE0 0x04e282c0 /* [RW] Spare 0 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_CFP_REG_SPARE1 0x04e282d0 /* [RW] Spare 1 Register (Not2Release) */ |
| #define BCHP_SWITCH_CORE_CFP_CTL_REG 0x04e28400 /* [RW] CFP Control Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_0 0x04e28440 /* [RW] UDFs of slice 0 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_1 0x04e28444 /* [RW] UDFs of slice 0 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_2 0x04e28448 /* [RW] UDFs of slice 0 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_3 0x04e2844c /* [RW] UDFs of slice 0 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_4 0x04e28450 /* [RW] UDFs of slice 0 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_5 0x04e28454 /* [RW] UDFs of slice 0 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_6 0x04e28458 /* [RW] UDFs of slice 0 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_7 0x04e2845c /* [RW] UDFs of slice 0 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_8 0x04e28460 /* [RW] UDFs of slice 0 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_0 0x04e28480 /* [RW] UDFs of slice 1 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_1 0x04e28484 /* [RW] UDFs of slice 1 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_2 0x04e28488 /* [RW] UDFs of slice 1 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_3 0x04e2848c /* [RW] UDFs of slice 1 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_4 0x04e28490 /* [RW] UDFs of slice 1 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_5 0x04e28494 /* [RW] UDFs of slice 1 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_6 0x04e28498 /* [RW] UDFs of slice 1 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_7 0x04e2849c /* [RW] UDFs of slice 1 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_8 0x04e284a0 /* [RW] UDFs of slice 1 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_0 0x04e284c0 /* [RW] UDFs of slice 2 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_1 0x04e284c4 /* [RW] UDFs of slice 2 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_2 0x04e284c8 /* [RW] UDFs of slice 2 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_3 0x04e284cc /* [RW] UDFs of slice 2 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_4 0x04e284d0 /* [RW] UDFs of slice 2 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_5 0x04e284d4 /* [RW] UDFs of slice 2 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_6 0x04e284d8 /* [RW] UDFs of slice 2 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_7 0x04e284dc /* [RW] UDFs of slice 2 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_8 0x04e284e0 /* [RW] UDFs of slice 2 for IPv4 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_0 0x04e28500 /* [RW] UDFs of slice 0 for IPv6 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_1 0x04e28504 /* [RW] UDFs of slice 0 for IPv6 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_2 0x04e28508 /* [RW] UDFs of slice 0 for IPv6 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_3 0x04e2850c /* [RW] UDFs of slice 0 for IPv6 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_4 0x04e28510 /* [RW] UDFs of slice 0 for IPv6 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_5 0x04e28514 /* [RW] UDFs of slice 0 for IPv6 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_6 0x04e28518 /* [RW] UDFs of slice 0 for IPv6 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_7 0x04e2851c /* [RW] UDFs of slice 0 for IPv6 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_8 0x04e28520 /* [RW] UDFs of slice 0 for IPv6 packet Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_0 0x04e28540 /* [RW] UDFs of slice 1 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_1 0x04e28544 /* [RW] UDFs of slice 1 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_2 0x04e28548 /* [RW] UDFs of slice 1 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_3 0x04e2854c /* [RW] UDFs of slice 1 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_4 0x04e28550 /* [RW] UDFs of slice 1 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_5 0x04e28554 /* [RW] UDFs of slice 1 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_6 0x04e28558 /* [RW] UDFs of slice 1 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_7 0x04e2855c /* [RW] UDFs of slice 1 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_8 0x04e28560 /* [RW] UDFs of slice 1 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_0 0x04e28580 /* [RW] UDFs of slice 2 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_1 0x04e28584 /* [RW] UDFs of slice 2 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_2 0x04e28588 /* [RW] UDFs of slice 2 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_3 0x04e2858c /* [RW] UDFs of slice 2 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_4 0x04e28590 /* [RW] UDFs of slice 2 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_5 0x04e28594 /* [RW] UDFs of slice 2 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_6 0x04e28598 /* [RW] UDFs of slice 2 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_7 0x04e2859c /* [RW] UDFs of slice 2 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_8 0x04e285a0 /* [RW] UDFs of slice 2 for IPv6 Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_0 0x04e285c0 /* [RW] UDFs of slice 0 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_1 0x04e285c4 /* [RW] UDFs of slice 0 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_2 0x04e285c8 /* [RW] UDFs of slice 0 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_3 0x04e285cc /* [RW] UDFs of slice 0 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_4 0x04e285d0 /* [RW] UDFs of slice 0 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_5 0x04e285d4 /* [RW] UDFs of slice 0 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_6 0x04e285d8 /* [RW] UDFs of slice 0 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_7 0x04e285dc /* [RW] UDFs of slice 0 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_8 0x04e285e0 /* [RW] UDFs of slice 0 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_0 0x04e28600 /* [RW] UDFs of slice 1 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_1 0x04e28604 /* [RW] UDFs of slice 1 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_2 0x04e28608 /* [RW] UDFs of slice 1 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_3 0x04e2860c /* [RW] UDFs of slice 1 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_4 0x04e28610 /* [RW] UDFs of slice 1 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_5 0x04e28614 /* [RW] UDFs of slice 1 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_6 0x04e28618 /* [RW] UDFs of slice 1 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_7 0x04e2861c /* [RW] UDFs of slice 1 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_8 0x04e28620 /* [RW] UDFs of slice 1 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_0 0x04e28640 /* [RW] UDFs of slice 2 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_1 0x04e28644 /* [RW] UDFs of slice 2 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_2 0x04e28648 /* [RW] UDFs of slice 2 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_3 0x04e2864c /* [RW] UDFs of slice 2 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_4 0x04e28650 /* [RW] UDFs of slice 2 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_5 0x04e28654 /* [RW] UDFs of slice 2 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_6 0x04e28658 /* [RW] UDFs of slice 2 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_7 0x04e2865c /* [RW] UDFs of slice 2 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_8 0x04e28660 /* [RW] UDFs of slice 2 for none-IP Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_0 0x04e28680 /* [RW] UDFs for IPv6 Chain Rule Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_1 0x04e28684 /* [RW] UDFs for IPv6 Chain Rule Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_2 0x04e28688 /* [RW] UDFs for IPv6 Chain Rule Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_3 0x04e2868c /* [RW] UDFs for IPv6 Chain Rule Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_4 0x04e28690 /* [RW] UDFs for IPv6 Chain Rule Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_5 0x04e28694 /* [RW] UDFs for IPv6 Chain Rule Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_6 0x04e28698 /* [RW] UDFs for IPv6 Chain Rule Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_7 0x04e2869c /* [RW] UDFs for IPv6 Chain Rule Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_8 0x04e286a0 /* [RW] UDFs for IPv6 Chain Rule Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_9 0x04e286a4 /* [RW] UDFs for IPv6 Chain Rule Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_10 0x04e286a8 /* [RW] UDFs for IPv6 Chain Rule Registers */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_11 0x04e286ac /* [RW] UDFs for IPv6 Chain Rule Registers */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG 0x04e38000 /* [RW] CPU OTP Control RegistersNot2Release */ |
| #define BCHP_SWITCH_CORE_OTP_ADDR_REG 0x04e38010 /* [RW] CPU OTP Address RegistersNot2Release */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG 0x04e38018 /* [RO] CPU OTP Status RegistersNot2Release */ |
| #define BCHP_SWITCH_CORE_OTP_WR_DATA 0x04e38020 /* [RW] CPU OTP Write Data RegistersNot2Release */ |
| #define BCHP_SWITCH_CORE_OTP_RD_DATA 0x04e38030 /* [RO] CPU OTP Read Data RegistersNot2Release */ |
| #define BCHP_SWITCH_CORE_IO_SR_CTL 0x04e38080 /* [RW] I/O Pad Slew Rate Control Register (Engineering use only)Not2Release */ |
| #define BCHP_SWITCH_CORE_IO_DS_SEL0 0x04e38090 /* [RW] I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release */ |
| #define BCHP_SWITCH_CORE_IO_DS_SEL2 0x04e380b0 /* [RW] I/O Pad Drive Strength Select 2 Register (Engineering use only)Not2Release */ |
| #define BCHP_SWITCH_CORE_GMII_IO_SR_CTL 0x04e380c0 /* [RW] GMII I/O Pad Slew Rate Control Register (Engineering use only)Not2Release */ |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0 0x04e380d0 /* [RW] GMII I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release */ |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1 0x04e380e0 /* [RW] GMII I/O Pad Drive Strength Select 1 Register (Engineering use only)Not2Release */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0 0x04e38100 /* [RW] Spare 0 Register (Not2Release)Not2Release */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1 0x04e38110 /* [RW] Spare 1 Register (Not2Release)Not2Release */ |
| |
| /*************************************************************************** |
| *G_PCTL_P0 - Port 0 Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: G_PCTL_P0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: G_PCTL_P0 :: G_MISTP_STATE [07:05] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_G_MISTP_STATE_MASK 0x000000e0 |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_G_MISTP_STATE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_G_MISTP_STATE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: G_PCTL_P0 :: SWITCH_RESV [04:02] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_SWITCH_RESV_MASK 0x0000001c |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_SWITCH_RESV_SHIFT 2 |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: G_PCTL_P0 :: TX_DIS [01:01] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_TX_DIS_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_TX_DIS_SHIFT 1 |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_TX_DIS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: G_PCTL_P0 :: RX_DIS [00:00] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_RX_DIS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_RX_DIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_G_PCTL_P0_RX_DIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *G_PCTL_P1 - Port 1 Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: G_PCTL_P1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: G_PCTL_P1 :: G_MISTP_STATE [07:05] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_G_MISTP_STATE_MASK 0x000000e0 |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_G_MISTP_STATE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_G_MISTP_STATE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: G_PCTL_P1 :: SWITCH_RESV [04:02] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_SWITCH_RESV_MASK 0x0000001c |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_SWITCH_RESV_SHIFT 2 |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: G_PCTL_P1 :: TX_DIS [01:01] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_TX_DIS_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_TX_DIS_SHIFT 1 |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_TX_DIS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: G_PCTL_P1 :: RX_DIS [00:00] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_RX_DIS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_RX_DIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_G_PCTL_P1_RX_DIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *G_PCTL_P2 - Port 2 Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: G_PCTL_P2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: G_PCTL_P2 :: G_MISTP_STATE [07:05] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_G_MISTP_STATE_MASK 0x000000e0 |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_G_MISTP_STATE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_G_MISTP_STATE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: G_PCTL_P2 :: SWITCH_RESV [04:02] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_SWITCH_RESV_MASK 0x0000001c |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_SWITCH_RESV_SHIFT 2 |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: G_PCTL_P2 :: TX_DIS [01:01] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_TX_DIS_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_TX_DIS_SHIFT 1 |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_TX_DIS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: G_PCTL_P2 :: RX_DIS [00:00] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_RX_DIS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_RX_DIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_G_PCTL_P2_RX_DIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *G_PCTL_P3 - Port 3 Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: G_PCTL_P3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: G_PCTL_P3 :: G_MISTP_STATE [07:05] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_G_MISTP_STATE_MASK 0x000000e0 |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_G_MISTP_STATE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_G_MISTP_STATE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: G_PCTL_P3 :: SWITCH_RESV [04:02] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_SWITCH_RESV_MASK 0x0000001c |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_SWITCH_RESV_SHIFT 2 |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: G_PCTL_P3 :: TX_DIS [01:01] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_TX_DIS_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_TX_DIS_SHIFT 1 |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_TX_DIS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: G_PCTL_P3 :: RX_DIS [00:00] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_RX_DIS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_RX_DIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_G_PCTL_P3_RX_DIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *G_PCTL_P4 - Port 4 Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: G_PCTL_P4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: G_PCTL_P4 :: G_MISTP_STATE [07:05] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_G_MISTP_STATE_MASK 0x000000e0 |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_G_MISTP_STATE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_G_MISTP_STATE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: G_PCTL_P4 :: SWITCH_RESV [04:02] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_SWITCH_RESV_MASK 0x0000001c |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_SWITCH_RESV_SHIFT 2 |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: G_PCTL_P4 :: TX_DIS [01:01] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_TX_DIS_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_TX_DIS_SHIFT 1 |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_TX_DIS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: G_PCTL_P4 :: RX_DIS [00:00] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_RX_DIS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_RX_DIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_G_PCTL_P4_RX_DIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *G_PCTL_P5 - Port 5 Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: G_PCTL_P5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: G_PCTL_P5 :: G_MISTP_STATE [07:05] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_G_MISTP_STATE_MASK 0x000000e0 |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_G_MISTP_STATE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_G_MISTP_STATE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: G_PCTL_P5 :: SWITCH_RESV [04:02] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_SWITCH_RESV_MASK 0x0000001c |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_SWITCH_RESV_SHIFT 2 |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: G_PCTL_P5 :: TX_DIS [01:01] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_TX_DIS_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_TX_DIS_SHIFT 1 |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_TX_DIS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: G_PCTL_P5 :: RX_DIS [00:00] */ |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_RX_DIS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_RX_DIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_G_PCTL_P5_RX_DIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CTL_P7 - Port 7 Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CTL_P7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_CTL_P7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_CTL_P7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: CTL_P7 :: G_MISTP_STATE [07:05] */ |
| #define BCHP_SWITCH_CORE_CTL_P7_G_MISTP_STATE_MASK 0x000000e0 |
| #define BCHP_SWITCH_CORE_CTL_P7_G_MISTP_STATE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_CTL_P7_G_MISTP_STATE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: CTL_P7 :: SWITCH_RESV [04:02] */ |
| #define BCHP_SWITCH_CORE_CTL_P7_SWITCH_RESV_MASK 0x0000001c |
| #define BCHP_SWITCH_CORE_CTL_P7_SWITCH_RESV_SHIFT 2 |
| #define BCHP_SWITCH_CORE_CTL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CTL_P7 :: TX_DIS [01:01] */ |
| #define BCHP_SWITCH_CORE_CTL_P7_TX_DIS_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_CTL_P7_TX_DIS_SHIFT 1 |
| #define BCHP_SWITCH_CORE_CTL_P7_TX_DIS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CTL_P7 :: RX_DIS [00:00] */ |
| #define BCHP_SWITCH_CORE_CTL_P7_RX_DIS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_CTL_P7_RX_DIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CTL_P7_RX_DIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CTL_IMP - IMP Port(Port 8) Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CTL_IMP :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_CTL_IMP_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_CTL_IMP_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: CTL_IMP :: SWITCH_RESV [07:05] */ |
| #define BCHP_SWITCH_CORE_CTL_IMP_SWITCH_RESV_MASK 0x000000e0 |
| #define BCHP_SWITCH_CORE_CTL_IMP_SWITCH_RESV_SHIFT 5 |
| #define BCHP_SWITCH_CORE_CTL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CTL_IMP :: RX_UCST_EN [04:04] */ |
| #define BCHP_SWITCH_CORE_CTL_IMP_RX_UCST_EN_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_CTL_IMP_RX_UCST_EN_SHIFT 4 |
| #define BCHP_SWITCH_CORE_CTL_IMP_RX_UCST_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CTL_IMP :: RX_MCST_EN [03:03] */ |
| #define BCHP_SWITCH_CORE_CTL_IMP_RX_MCST_EN_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_CTL_IMP_RX_MCST_EN_SHIFT 3 |
| #define BCHP_SWITCH_CORE_CTL_IMP_RX_MCST_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CTL_IMP :: RX_BCST_EN [02:02] */ |
| #define BCHP_SWITCH_CORE_CTL_IMP_RX_BCST_EN_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_CTL_IMP_RX_BCST_EN_SHIFT 2 |
| #define BCHP_SWITCH_CORE_CTL_IMP_RX_BCST_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CTL_IMP :: TX_DIS [01:01] */ |
| #define BCHP_SWITCH_CORE_CTL_IMP_TX_DIS_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_CTL_IMP_TX_DIS_SHIFT 1 |
| #define BCHP_SWITCH_CORE_CTL_IMP_TX_DIS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CTL_IMP :: RX_DIS [00:00] */ |
| #define BCHP_SWITCH_CORE_CTL_IMP_RX_DIS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_CTL_IMP_RX_DIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CTL_IMP_RX_DIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RX_GLOBAL_CTL - RX Global Control register(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RX_GLOBAL_CTL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: RX_GLOBAL_CTL :: SWITCH_RESV [07:07] */ |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_SWITCH_RESV_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_SWITCH_RESV_SHIFT 7 |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RX_GLOBAL_CTL :: DIS_RX_MASK [06:06] */ |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_RX_MASK_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_RX_MASK_SHIFT 6 |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_RX_MASK_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RX_GLOBAL_CTL :: DIS_ECC_CHK [05:05] */ |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_ECC_CHK_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_ECC_CHK_SHIFT 5 |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_ECC_CHK_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RX_GLOBAL_CTL :: DIS_CRC_CHK [04:04] */ |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_CRC_CHK_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_CRC_CHK_SHIFT 4 |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_DIS_CRC_CHK_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RX_GLOBAL_CTL :: FMOK_LATENCY_CNT [03:00] */ |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SWMODE - Switch Mode Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SWMODE :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_SWMODE_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_SWMODE_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: SWMODE :: SWITCH_RESV [07:05] */ |
| #define BCHP_SWITCH_CORE_SWMODE_SWITCH_RESV_MASK 0x000000e0 |
| #define BCHP_SWITCH_CORE_SWMODE_SWITCH_RESV_SHIFT 5 |
| #define BCHP_SWITCH_CORE_SWMODE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SWMODE :: NOBLKCD [04:04] */ |
| #define BCHP_SWITCH_CORE_SWMODE_NOBLKCD_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_SWMODE_NOBLKCD_SHIFT 4 |
| #define BCHP_SWITCH_CORE_SWMODE_NOBLKCD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SWMODE :: FAST_TXDESC_RERURN [03:03] */ |
| #define BCHP_SWITCH_CORE_SWMODE_FAST_TXDESC_RERURN_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_SWMODE_FAST_TXDESC_RERURN_SHIFT 3 |
| #define BCHP_SWITCH_CORE_SWMODE_FAST_TXDESC_RERURN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SWMODE :: RTRY_LMT_DIS [02:02] */ |
| #define BCHP_SWITCH_CORE_SWMODE_RTRY_LMT_DIS_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_SWMODE_RTRY_LMT_DIS_SHIFT 2 |
| #define BCHP_SWITCH_CORE_SWMODE_RTRY_LMT_DIS_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: SWMODE :: SW_FWDG_EN [01:01] */ |
| #define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_EN_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_EN_SHIFT 1 |
| #define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SWMODE :: SW_FWDG_MODE [00:00] */ |
| #define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_MODE_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_MODE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SWMODE_SW_FWDG_MODE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *STS_OVERRIDE_IMP - IMP Port(Port 8) States Override Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STS_OVERRIDE_IMP :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_IMP :: MII_SW_OR [07:07] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_MII_SW_OR_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_MII_SW_OR_SHIFT 7 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_MII_SW_OR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_IMP :: GMII_SPEED_UP_2G [06:06] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_GMII_SPEED_UP_2G_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_GMII_SPEED_UP_2G_SHIFT 6 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_GMII_SPEED_UP_2G_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_IMP :: TXFLOW_CNTL [05:05] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_TXFLOW_CNTL_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_TXFLOW_CNTL_SHIFT 5 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_TXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_IMP :: RXFLOW_CNTL [04:04] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_RXFLOW_CNTL_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_RXFLOW_CNTL_SHIFT 4 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_RXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_IMP :: SPEED [03:02] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_SPEED_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_SPEED_SHIFT 2 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_SPEED_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_IMP :: DUPLX_MODE [01:01] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_DUPLX_MODE_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_DUPLX_MODE_SHIFT 1 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_DUPLX_MODE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_IMP :: LINK_STS [00:00] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_LINK_STS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_LINK_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_IMP_LINK_STS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DEBUG_REG - Debug Control Register(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DEBUG_REG :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_DEBUG_REG_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_DEBUG_REG_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: DEBUG_REG :: PROBE_SOC_DMU_CLK [07:07] */ |
| #define BCHP_SWITCH_CORE_DEBUG_REG_PROBE_SOC_DMU_CLK_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_DEBUG_REG_PROBE_SOC_DMU_CLK_SHIFT 7 |
| #define BCHP_SWITCH_CORE_DEBUG_REG_PROBE_SOC_DMU_CLK_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEBUG_REG :: DEBUG_SEL [06:01] */ |
| #define BCHP_SWITCH_CORE_DEBUG_REG_DEBUG_SEL_MASK 0x0000007e |
| #define BCHP_SWITCH_CORE_DEBUG_REG_DEBUG_SEL_SHIFT 1 |
| #define BCHP_SWITCH_CORE_DEBUG_REG_DEBUG_SEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEBUG_REG :: EN_DEBUG [00:00] */ |
| #define BCHP_SWITCH_CORE_DEBUG_REG_EN_DEBUG_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_DEBUG_REG_EN_DEBUG_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DEBUG_REG_EN_DEBUG_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RM_PINS_DEBUG - Removed Pins Debug Register(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RM_PINS_DEBUG :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: RM_PINS_DEBUG :: SWITCH_RESV [07:03] */ |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_SWITCH_RESV_MASK 0x000000f8 |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_SWITCH_RESV_SHIFT 3 |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RM_PINS_DEBUG :: DIS_IMP_PIN [02:02] */ |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_DIS_IMP_PIN_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_DIS_IMP_PIN_SHIFT 2 |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_DIS_IMP_PIN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RM_PINS_DEBUG :: ENFDXFLOW_PIN [01:01] */ |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENFDXFLOW_PIN_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENFDXFLOW_PIN_SHIFT 1 |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENFDXFLOW_PIN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: RM_PINS_DEBUG :: ENHDXFLOW_PIN [00:00] */ |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENHDXFLOW_PIN_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENHDXFLOW_PIN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RM_PINS_DEBUG_ENHDXFLOW_PIN_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *NEW_CTRL - New Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: NEW_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_NEW_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: NEW_CTRL :: MC_FWD_EN [07:07] */ |
| #define BCHP_SWITCH_CORE_NEW_CTRL_MC_FWD_EN_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_MC_FWD_EN_SHIFT 7 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_MC_FWD_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: NEW_CTRL :: UC_FWD_EN [06:06] */ |
| #define BCHP_SWITCH_CORE_NEW_CTRL_UC_FWD_EN_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_UC_FWD_EN_SHIFT 6 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_UC_FWD_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: NEW_CTRL :: EN_AUTO_PD_WAR [05:05] */ |
| #define BCHP_SWITCH_CORE_NEW_CTRL_EN_AUTO_PD_WAR_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_EN_AUTO_PD_WAR_SHIFT 5 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_EN_AUTO_PD_WAR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: NEW_CTRL :: OVERRIDE_AUTO_PD_WAR [04:04] */ |
| #define BCHP_SWITCH_CORE_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_SHIFT 4 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: NEW_CTRL :: CABLE_DIAG_LEN [03:03] */ |
| #define BCHP_SWITCH_CORE_NEW_CTRL_CABLE_DIAG_LEN_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_CABLE_DIAG_LEN_SHIFT 3 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_CABLE_DIAG_LEN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: NEW_CTRL :: INRANGEERR_DISCARD [02:02] */ |
| #define BCHP_SWITCH_CORE_NEW_CTRL_INRANGEERR_DISCARD_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_INRANGEERR_DISCARD_SHIFT 2 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_INRANGEERR_DISCARD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: NEW_CTRL :: OUTRANGEERR_DISCARD [01:01] */ |
| #define BCHP_SWITCH_CORE_NEW_CTRL_OUTRANGEERR_DISCARD_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_OUTRANGEERR_DISCARD_SHIFT 1 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_OUTRANGEERR_DISCARD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: NEW_CTRL :: IP_MC [00:00] */ |
| #define BCHP_SWITCH_CORE_NEW_CTRL_IP_MC_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_IP_MC_SHIFT 0 |
| #define BCHP_SWITCH_CORE_NEW_CTRL_IP_MC_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SWITCH_CTRL - Switch Control Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SWITCH_CTRL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SWITCH_CTRL :: SWITCH_RESV_1 [15:07] */ |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_1_MASK 0x0000ff80 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SWITCH_CTRL :: MII_DUMB_FWDG_EN [06:06] */ |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_MII_DUMB_FWDG_EN_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_MII_DUMB_FWDG_EN_SHIFT 6 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_MII_DUMB_FWDG_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SWITCH_CTRL :: SWITCH_RESV_0 [05:04] */ |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_0_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_0_SHIFT 4 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SWITCH_CTRL :: GPHY_PLLBYPASS [03:03] */ |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_GPHY_PLLBYPASS_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_GPHY_PLLBYPASS_SHIFT 3 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_GPHY_PLLBYPASS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SWITCH_CTRL :: MII3_VOL_SEL [02:02] */ |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_MII3_VOL_SEL_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_MII3_VOL_SEL_SHIFT 2 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_MII3_VOL_SEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SWITCH_CTRL :: MII2_VOL_SEL [01:01] */ |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_MII2_VOL_SEL_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_MII2_VOL_SEL_SHIFT 1 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_MII2_VOL_SEL_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: SWITCH_CTRL :: MII1_VOL_SEL [00:00] */ |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_MII1_VOL_SEL_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_MII1_VOL_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SWITCH_CTRL_MII1_VOL_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PROTECTED_SEL - Protected Port Select Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PROTECTED_SEL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PROTECTED_SEL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PROTECTED_SEL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PROTECTED_SEL :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_PROTECTED_SEL_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_PROTECTED_SEL_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PROTECTED_SEL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PROTECTED_SEL :: PORT_SEL [08:00] */ |
| #define BCHP_SWITCH_CORE_PROTECTED_SEL_PORT_SEL_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_PROTECTED_SEL_PORT_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PROTECTED_SEL_PORT_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WAN_PORT_SEL - WAN Port select Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WAN_PORT_SEL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: WAN_PORT_SEL :: SWITCH_RESV_1 [15:10] */ |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_1_MASK 0x0000fc00 |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_1_SHIFT 10 |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WAN_PORT_SEL :: EN_MAN2WAN [09:09] */ |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_EN_MAN2WAN_MASK 0x00000200 |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_EN_MAN2WAN_SHIFT 9 |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_EN_MAN2WAN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WAN_PORT_SEL :: SWITCH_RESV_0 [08:08] */ |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_0_MASK 0x00000100 |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_0_SHIFT 8 |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WAN_PORT_SEL :: WAN_SELECT [07:00] */ |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_WAN_SELECT_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_WAN_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WAN_PORT_SEL_WAN_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAUSE_CAP - PAUSE Capability Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PAUSE_CAP :: SWITCH_RESV_1 [31:24] */ |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_1_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_1_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PAUSE_CAP :: EN_OVERRIDE [23:23] */ |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_EN_OVERRIDE_MASK 0x00800000 |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_EN_OVERRIDE_SHIFT 23 |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_EN_OVERRIDE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PAUSE_CAP :: SWITCH_RESV [22:18] */ |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_MASK 0x007c0000 |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PAUSE_CAP :: RX_PAUSE_CAP [17:09] */ |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_RX_PAUSE_CAP_MASK 0x0003fe00 |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_RX_PAUSE_CAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_RX_PAUSE_CAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PAUSE_CAP :: TX_PAUSE_CAP [08:00] */ |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_TX_PAUSE_CAP_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_TX_PAUSE_CAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PAUSE_CAP_TX_PAUSE_CAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RSV_MCAST_CTRL - Reserved Multicast Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RSV_MCAST_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_RES_MUL_LEARN [07:07] */ |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_SHIFT 7 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RSV_MCAST_CTRL :: SWITCH_RESV [06:05] */ |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_SWITCH_RESV_MASK 0x00000060 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_SWITCH_RESV_SHIFT 5 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_4 [04:04] */ |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_4_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_4_SHIFT 4 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_3 [03:03] */ |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_3_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_3_SHIFT 3 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_2 [02:02] */ |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_2_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_2_SHIFT 2 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_1 [01:01] */ |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_1_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_1_SHIFT 1 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_1_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: RSV_MCAST_CTRL :: EN_MUL_0 [00:00] */ |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_0_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RSV_MCAST_CTRL_EN_MUL_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TXQ_FLUSH_MODE - TxQ Flush Mode Control Register(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TXQ_FLUSH_MODE :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_NEW_BOFF_SEED [07:07] */ |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_SHIFT 7 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_LATECOl65_DROP [06:06] */ |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LATECOl65_DROP_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LATECOl65_DROP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LATECOl65_DROP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_ECOL_TXFM_MASK [05:05] */ |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_SHIFT 5 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_LCOL_TXFM_MASK [04:04] */ |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_SHIFT 4 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_RELOAD_ERR_PATH [03:03] */ |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_SHIFT 3 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TXQ_FLUSH_MODE :: EN_LCOL_FLUSH [02:02] */ |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_SHIFT 2 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TXQ_FLUSH_MODE :: DIS_NEW_TXDIS [01:01] */ |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_SHIFT 1 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TXQ_FLUSH_MODE :: BYPASS_FASTTXDSC_PATH [00:00] */ |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ULF_DROP_MAP - Unicast Lookup Failed Forward Map Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ULF_DROP_MAP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_ULF_DROP_MAP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_ULF_DROP_MAP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: ULF_DROP_MAP :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_ULF_DROP_MAP_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_ULF_DROP_MAP_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_ULF_DROP_MAP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ULF_DROP_MAP :: UNI_LOOKUP_FAIL_FWD_MAP [08:00] */ |
| #define BCHP_SWITCH_CORE_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MLF_DROP_MAP - Multicast Lookup Failed Forward Map Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MLF_DROP_MAP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MLF_DROP_MAP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MLF_DROP_MAP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MLF_DROP_MAP :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_MLF_DROP_MAP_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_MLF_DROP_MAP_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MLF_DROP_MAP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MLF_DROP_MAP :: MUL_LOOKUP_FAIL_FRW_MAP [08:00] */ |
| #define BCHP_SWITCH_CORE_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MLF_IPMC_FWD_MAP - IPMC Forward Map Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MLF_IPMC_FWD_MAP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MLF_IPMC_FWD_MAP :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MLF_IPMC_FWD_MAP :: MLF_IPMC_FWD_MAP [08:00] */ |
| #define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RX_PAUSE_PASS - Pause pass Through for RX Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RX_PAUSE_PASS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_RX_PAUSE_PASS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_RX_PAUSE_PASS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: RX_PAUSE_PASS :: SWITCH_RESV_1 [15:09] */ |
| #define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_1_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_1_SHIFT 9 |
| #define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RX_PAUSE_PASS :: SWITCH_RESV_0 [08:08] */ |
| #define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_0_MASK 0x00000100 |
| #define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_0_SHIFT 8 |
| #define BCHP_SWITCH_CORE_RX_PAUSE_PASS_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RX_PAUSE_PASS :: RX_PAUSE_PASS [07:00] */ |
| #define BCHP_SWITCH_CORE_RX_PAUSE_PASS_RX_PAUSE_PASS_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_RX_PAUSE_PASS_RX_PAUSE_PASS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RX_PAUSE_PASS_RX_PAUSE_PASS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TX_PAUSE_PASS - Pause pass Through for TX Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TX_PAUSE_PASS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TX_PAUSE_PASS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TX_PAUSE_PASS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TX_PAUSE_PASS :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_TX_PAUSE_PASS_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_TX_PAUSE_PASS_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TX_PAUSE_PASS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TX_PAUSE_PASS :: TX_PAUSE_PASS [08:00] */ |
| #define BCHP_SWITCH_CORE_TX_PAUSE_PASS_TX_PAUSE_PASS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_TX_PAUSE_PASS_TX_PAUSE_PASS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TX_PAUSE_PASS_TX_PAUSE_PASS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DIS_LEARN - Disable Learning Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DIS_LEARN :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_DIS_LEARN_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_DIS_LEARN_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: DIS_LEARN :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_DIS_LEARN_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_DIS_LEARN_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_DIS_LEARN_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DIS_LEARN :: DIS_LEARN [08:00] */ |
| #define BCHP_SWITCH_CORE_DIS_LEARN_DIS_LEARN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_DIS_LEARN_DIS_LEARN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DIS_LEARN_DIS_LEARN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SFT_LRN_CTL - Software Learning Control |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SFT_LRN_CTL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SFT_LRN_CTL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SFT_LRN_CTL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SFT_LRN_CTL :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_SFT_LRN_CTL_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_SFT_LRN_CTL_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_SFT_LRN_CTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SFT_LRN_CTL :: SW_LEARN_CNTL [08:00] */ |
| #define BCHP_SWITCH_CORE_SFT_LRN_CTL_SW_LEARN_CNTL_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_SFT_LRN_CTL_SW_LEARN_CNTL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SFT_LRN_CTL_SW_LEARN_CNTL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LOW_POWER_EXP1 - Low Power Expansion I Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LOW_POWER_EXP1 :: SWITCH_RESV_1 [31:25] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_1_MASK 0xfe000000 |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_1_SHIFT 25 |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LOW_POWER_EXP1 :: SLEEP_MACCLK_PORT [24:16] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_MASK 0x01ff0000 |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_SHIFT 16 |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LOW_POWER_EXP1 :: SWITCH_RESV_0 [15:09] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_0_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_0_SHIFT 9 |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LOW_POWER_EXP1 :: SLEEP_SYSCLK_PORT [08:00] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CTLREG_REG_SPARE - Spare Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CTLREG_REG_SPARE :: CTLREG_REG_SPARE [31:00] */ |
| #define BCHP_SWITCH_CORE_CTLREG_REG_SPARE_CTLREG_REG_SPARE_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CTLREG_REG_SPARE_CTLREG_REG_SPARE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CTLREG_REG_SPARE_CTLREG_REG_SPARE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STS_OVERRIDE_GMII_P0 - Port 0 GMII Port States Override Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SWITCH_RESV_1_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: SW_OVERRIDE [06:06] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SW_OVERRIDE_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SW_OVERRIDE_SHIFT 6 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SW_OVERRIDE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: TXFLOW_CNTL [05:05] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_TXFLOW_CNTL_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_TXFLOW_CNTL_SHIFT 5 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_TXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: RXFLOW_CNTL [04:04] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_RXFLOW_CNTL_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_RXFLOW_CNTL_SHIFT 4 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_RXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: SPEED [03:02] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SPEED_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SPEED_SHIFT 2 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_SPEED_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: DUPLX_MODE [01:01] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_DUPLX_MODE_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_DUPLX_MODE_SHIFT 1 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_DUPLX_MODE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P0 :: LINK_STS [00:00] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_LINK_STS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_LINK_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P0_LINK_STS_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *STS_OVERRIDE_GMII_P1 - Port 1 GMII Port States Override Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SWITCH_RESV_1_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: SW_OVERRIDE [06:06] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SW_OVERRIDE_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SW_OVERRIDE_SHIFT 6 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SW_OVERRIDE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: TXFLOW_CNTL [05:05] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_TXFLOW_CNTL_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_TXFLOW_CNTL_SHIFT 5 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_TXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: RXFLOW_CNTL [04:04] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_RXFLOW_CNTL_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_RXFLOW_CNTL_SHIFT 4 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_RXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: SPEED [03:02] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SPEED_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SPEED_SHIFT 2 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_SPEED_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: DUPLX_MODE [01:01] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_DUPLX_MODE_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_DUPLX_MODE_SHIFT 1 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_DUPLX_MODE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P1 :: LINK_STS [00:00] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_LINK_STS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_LINK_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P1_LINK_STS_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *STS_OVERRIDE_GMII_P2 - Port 2 GMII Port States Override Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SWITCH_RESV_1_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: SW_OVERRIDE [06:06] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SW_OVERRIDE_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SW_OVERRIDE_SHIFT 6 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SW_OVERRIDE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: TXFLOW_CNTL [05:05] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_TXFLOW_CNTL_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_TXFLOW_CNTL_SHIFT 5 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_TXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: RXFLOW_CNTL [04:04] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_RXFLOW_CNTL_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_RXFLOW_CNTL_SHIFT 4 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_RXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: SPEED [03:02] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SPEED_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SPEED_SHIFT 2 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_SPEED_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: DUPLX_MODE [01:01] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_DUPLX_MODE_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_DUPLX_MODE_SHIFT 1 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_DUPLX_MODE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P2 :: LINK_STS [00:00] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_LINK_STS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_LINK_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P2_LINK_STS_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *STS_OVERRIDE_GMII_P3 - Port 3 GMII Port States Override Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SWITCH_RESV_1_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: SW_OVERRIDE [06:06] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SW_OVERRIDE_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SW_OVERRIDE_SHIFT 6 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SW_OVERRIDE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: TXFLOW_CNTL [05:05] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_TXFLOW_CNTL_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_TXFLOW_CNTL_SHIFT 5 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_TXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: RXFLOW_CNTL [04:04] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_RXFLOW_CNTL_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_RXFLOW_CNTL_SHIFT 4 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_RXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: SPEED [03:02] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SPEED_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SPEED_SHIFT 2 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_SPEED_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: DUPLX_MODE [01:01] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_DUPLX_MODE_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_DUPLX_MODE_SHIFT 1 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_DUPLX_MODE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P3 :: LINK_STS [00:00] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_LINK_STS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_LINK_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P3_LINK_STS_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *STS_OVERRIDE_GMII_P4 - Port 4 GMII Port States Override Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SWITCH_RESV_1_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: SW_OVERRIDE [06:06] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SW_OVERRIDE_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SW_OVERRIDE_SHIFT 6 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SW_OVERRIDE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: TXFLOW_CNTL [05:05] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_TXFLOW_CNTL_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_TXFLOW_CNTL_SHIFT 5 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_TXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: RXFLOW_CNTL [04:04] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_RXFLOW_CNTL_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_RXFLOW_CNTL_SHIFT 4 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_RXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: SPEED [03:02] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SPEED_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SPEED_SHIFT 2 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_SPEED_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: DUPLX_MODE [01:01] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_DUPLX_MODE_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_DUPLX_MODE_SHIFT 1 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_DUPLX_MODE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P4 :: LINK_STS [00:00] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_LINK_STS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_LINK_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P4_LINK_STS_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *STS_OVERRIDE_GMII_P5 - Port 5 GMII Port States Override Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: GMII_SPEED_UP_2G [07:07] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_GMII_SPEED_UP_2G_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_GMII_SPEED_UP_2G_SHIFT 7 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_GMII_SPEED_UP_2G_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: SW_OVERRIDE [06:06] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_SW_OVERRIDE_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_SW_OVERRIDE_SHIFT 6 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_SW_OVERRIDE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: TXFLOW_CNTL [05:05] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_TXFLOW_CNTL_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_TXFLOW_CNTL_SHIFT 5 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_TXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: RXFLOW_CNTL [04:04] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_RXFLOW_CNTL_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_RXFLOW_CNTL_SHIFT 4 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_RXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: SPEED [03:02] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_SPEED_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_SPEED_SHIFT 2 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_SPEED_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: DUPLX_MODE [01:01] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_DUPLX_MODE_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_DUPLX_MODE_SHIFT 1 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_DUPLX_MODE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P5 :: LINK_STS [00:00] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_LINK_STS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_LINK_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P5_LINK_STS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STS_OVERRIDE_GMII_P7 - Port 7 GMII Port States Override Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: GMII_SPEED_UP_2G [07:07] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_GMII_SPEED_UP_2G_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_GMII_SPEED_UP_2G_SHIFT 7 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_GMII_SPEED_UP_2G_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: SW_OVERRIDE [06:06] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_SW_OVERRIDE_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_SW_OVERRIDE_SHIFT 6 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_SW_OVERRIDE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: TXFLOW_CNTL [05:05] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_TXFLOW_CNTL_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_TXFLOW_CNTL_SHIFT 5 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_TXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: RXFLOW_CNTL [04:04] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_RXFLOW_CNTL_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_RXFLOW_CNTL_SHIFT 4 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_RXFLOW_CNTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: SPEED [03:02] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_SPEED_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_SPEED_SHIFT 2 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_SPEED_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: DUPLX_MODE [01:01] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_DUPLX_MODE_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_DUPLX_MODE_SHIFT 1 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_DUPLX_MODE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: STS_OVERRIDE_GMII_P7 :: LINK_STS [00:00] */ |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_LINK_STS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_LINK_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STS_OVERRIDE_GMII_P7_LINK_STS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WATCH_DOG_CTRL - Watch Dog Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WATCH_DOG_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: WATCH_DOG_CTRL :: SOFTWARE_RESET [07:07] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SOFTWARE_RESET_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SOFTWARE_RESET_SHIFT 7 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SOFTWARE_RESET_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_CHIP_RST [06:06] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_CHIP_RST_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_CHIP_RST_SHIFT 6 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_CHIP_RST_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WATCH_DOG_CTRL :: SWITCH_RESV [05:05] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SWITCH_RESV_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SWITCH_RESV_SHIFT 5 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_SW_RESET [04:04] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_SW_RESET_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_SW_RESET_SHIFT 4 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_SW_RESET_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_AUTO_RST [03:03] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_AUTO_RST_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_AUTO_RST_SHIFT 3 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_AUTO_RST_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_RELOAD_EEPROM [02:02] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RELOAD_EEPROM_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RELOAD_EEPROM_SHIFT 2 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RELOAD_EEPROM_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_RST_REGFILE [01:01] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_REGFILE_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_REGFILE_SHIFT 1 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_REGFILE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WATCH_DOG_CTRL :: EN_RST_SWITCH [00:00] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_SWITCH_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_SWITCH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_CTRL_EN_RST_SWITCH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WATCH_DOG_RPT1 - Watch Dog Report 1 Register(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WATCH_DOG_RPT1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: WATCH_DOG_RPT1 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WATCH_DOG_RPT1 :: TX_PORT_HUNG_INDICATOR [08:00] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WATCH_DOG_RPT2 - Watch Dog Report 2 Register(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WATCH_DOG_RPT2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: WATCH_DOG_RPT2 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WATCH_DOG_RPT2 :: RX_PORT_HUNG_INDICATOR [08:00] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WATCH_DOG_RPT3 - Watch Dog Report 3 Register(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WATCH_DOG_RPT3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: WATCH_DOG_RPT3 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WATCH_DOG_RPT3 :: ARL_HUNG_INDICATOR [08:00] */ |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAUSE_FRM_CTRL - Pause Frame Detection Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PAUSE_FRM_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: PAUSE_FRM_CTRL :: SWITCH_RESV_2 [07:03] */ |
| #define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_2_MASK 0x000000f8 |
| #define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_2_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PAUSE_FRM_CTRL :: SWITCH_RESV_1 [02:01] */ |
| #define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_1_MASK 0x00000006 |
| #define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_1_SHIFT 1 |
| #define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PAUSE_FRM_CTRL :: PAUSE_IGNORE_DA [00:00] */ |
| #define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAUSE_ST_ADDR - PAUSE Frame DA Address |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PAUSE_ST_ADDR :: PAUSE_ST_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_PAUSE_ST_ADDR_PAUSE_ST_ADDR_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_PAUSE_ST_ADDR_PAUSE_ST_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PAUSE_ST_ADDR_PAUSE_ST_ADDR_DEFAULT 0x0180c2000001 |
| |
| /*************************************************************************** |
| *FAST_AGE_CTRL - Fast Ageing Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FAST_AGE_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: FAST_AGE_CTRL :: FAST_AGE_STR_DONE [07:07] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_FAST_AGE_STR_DONE_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_FAST_AGE_STR_DONE_SHIFT 7 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_FAST_AGE_STR_DONE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FAST_AGE_CTRL :: SWITCH_RESV [06:06] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_SWITCH_RESV_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_SWITCH_RESV_SHIFT 6 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_MCAST [05:05] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_MCAST_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_MCAST_SHIFT 5 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_MCAST_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_SPT [04:04] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_SPT_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_SPT_SHIFT 4 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_SPT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_VLAN [03:03] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_VLAN_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_VLAN_SHIFT 3 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_VLAN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_PORT [02:02] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_PORT_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_PORT_SHIFT 2 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_PORT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FAST_AGE_CTRL :: EN_AGE_DYNAMIC [01:01] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_DYNAMIC_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_DYNAMIC_SHIFT 1 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_AGE_DYNAMIC_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: FAST_AGE_CTRL :: EN_FAST_AGE_STATIC [00:00] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FAST_AGE_PORT - Fast Ageing Port Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FAST_AGE_PORT :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_PORT_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_FAST_AGE_PORT_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: FAST_AGE_PORT :: SWITCH_RESV [07:04] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_PORT_SWITCH_RESV_MASK 0x000000f0 |
| #define BCHP_SWITCH_CORE_FAST_AGE_PORT_SWITCH_RESV_SHIFT 4 |
| #define BCHP_SWITCH_CORE_FAST_AGE_PORT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FAST_AGE_PORT :: AGE_PORT [03:00] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_PORT_AGE_PORT_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_FAST_AGE_PORT_AGE_PORT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FAST_AGE_PORT_AGE_PORT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FAST_AGE_VID - Fast Ageing VID Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FAST_AGE_VID :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_VID_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FAST_AGE_VID_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FAST_AGE_VID :: SWITCH_RESV [15:12] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_VID_SWITCH_RESV_MASK 0x0000f000 |
| #define BCHP_SWITCH_CORE_FAST_AGE_VID_SWITCH_RESV_SHIFT 12 |
| #define BCHP_SWITCH_CORE_FAST_AGE_VID_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FAST_AGE_VID :: AGE_VID [11:00] */ |
| #define BCHP_SWITCH_CORE_FAST_AGE_VID_AGE_VID_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_FAST_AGE_VID_AGE_VID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FAST_AGE_VID_AGE_VID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LOW_POWER_CTRL - LOW Power Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LOW_POWER_CTRL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_P8 [15:15] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P8_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P8_SHIFT 15 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P8_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LOW_POWER_CTRL :: SWITCH_RESV_1 [14:13] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_1_MASK 0x00006000 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_1_SHIFT 13 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_P5 [12:12] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P5_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P5_SHIFT 12 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_P4 [11:11] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P4_MASK 0x00000800 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P4_SHIFT 11 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_P4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LOW_POWER_CTRL :: SWITCH_RESV_0 [10:07] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_0_MASK 0x00000780 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_0_SHIFT 7 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LOW_POWER_CTRL :: SLEEP_SYS [06:06] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_SYS_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_SYS_SHIFT 6 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_SLEEP_SYS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LOW_POWER_CTRL :: TIMER_DISABLE [05:05] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_TIMER_DISABLE_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_TIMER_DISABLE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_TIMER_DISABLE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LOW_POWER_CTRL :: EN_LOW_POWER [04:04] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_EN_LOW_POWER_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_EN_LOW_POWER_SHIFT 4 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_EN_LOW_POWER_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LOW_POWER_CTRL :: LOW_POWER_DIVIDER [03:00] */ |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_LOW_POWER_DIVIDER_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_LOW_POWER_DIVIDER_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LOW_POWER_CTRL_LOW_POWER_DIVIDER_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TCAM_CTRL - TCAM Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TCAM_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_TCAM_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_TCAM_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: TCAM_CTRL :: EN_TCAM_CHKSUM [07:07] */ |
| #define BCHP_SWITCH_CORE_TCAM_CTRL_EN_TCAM_CHKSUM_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_TCAM_CTRL_EN_TCAM_CHKSUM_SHIFT 7 |
| #define BCHP_SWITCH_CORE_TCAM_CTRL_EN_TCAM_CHKSUM_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_CTRL :: SWITCH_RESV [06:00] */ |
| #define BCHP_SWITCH_CORE_TCAM_CTRL_SWITCH_RESV_MASK 0x0000007f |
| #define BCHP_SWITCH_CORE_TCAM_CTRL_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TCAM_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TCAM_CHKSUM_STS - TCAM Checksum Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TCAM_CHKSUM_STS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TCAM_CHKSUM_STS :: CFP_TCAM_CHKSUM_ERR [15:15] */ |
| #define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_SHIFT 15 |
| #define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_CHKSUM_STS :: SWITCH_RESV [14:08] */ |
| #define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_SWITCH_RESV_MASK 0x00007f00 |
| #define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_SWITCH_RESV_SHIFT 8 |
| #define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_CHKSUM_STS :: CFP_TCAM_CHKSUM_ADDR [07:00] */ |
| #define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LNKSTS - Link Status Summary Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LNKSTS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_LNKSTS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_LNKSTS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: LNKSTS :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_LNKSTS_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_LNKSTS_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_LNKSTS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LNKSTS :: LNK_STS [08:00] */ |
| #define BCHP_SWITCH_CORE_LNKSTS_LNK_STS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_LNKSTS_LNK_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LNKSTS_LNK_STS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LNKSTSCHG - Link Status Change Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LNKSTSCHG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_LNKSTSCHG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_LNKSTSCHG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: LNKSTSCHG :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_LNKSTSCHG_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_LNKSTSCHG_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_LNKSTSCHG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LNKSTSCHG :: LNK_STS_CHG [08:00] */ |
| #define BCHP_SWITCH_CORE_LNKSTSCHG_LNK_STS_CHG_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_LNKSTSCHG_LNK_STS_CHG_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LNKSTSCHG_LNK_STS_CHG_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *SPDSTS - Port Speed Summary Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SPDSTS :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_SPDSTS_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_SPDSTS_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_SPDSTS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SPDSTS :: PORT_SPD [17:00] */ |
| #define BCHP_SWITCH_CORE_SPDSTS_PORT_SPD_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_SPDSTS_PORT_SPD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SPDSTS_PORT_SPD_DEFAULT 0x0002aaaa |
| |
| /*************************************************************************** |
| *DUPSTS - Duplex status Summary Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DUPSTS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_DUPSTS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_DUPSTS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: DUPSTS :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_DUPSTS_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_DUPSTS_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_DUPSTS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DUPSTS :: DUP_STS [08:00] */ |
| #define BCHP_SWITCH_CORE_DUPSTS_DUP_STS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_DUPSTS_DUP_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DUPSTS_DUP_STS_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *PAUSESTS - Pause Status Summary Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PAUSESTS :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PAUSESTS_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PAUSESTS_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PAUSESTS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PAUSESTS :: PAUSE_STS [17:00] */ |
| #define BCHP_SWITCH_CORE_PAUSESTS_PAUSE_STS_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PAUSESTS_PAUSE_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PAUSESTS_PAUSE_STS_DEFAULT 0x00024120 |
| |
| /*************************************************************************** |
| *SRCADRCHG - Source Address Change Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SRCADRCHG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SRCADRCHG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SRCADRCHG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SRCADRCHG :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_SRCADRCHG_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_SRCADRCHG_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_SRCADRCHG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SRCADRCHG :: SRC_ADDR_CHANGE [08:00] */ |
| #define BCHP_SWITCH_CORE_SRCADRCHG_SRC_ADDR_CHANGE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_SRCADRCHG_SRC_ADDR_CHANGE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SRCADRCHG_SRC_ADDR_CHANGE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LSA_PORT_P0 - Port 0 Last Source Address |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LSA_PORT_P0 :: LST_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P0_LST_ADDR_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P0_LST_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P0_LST_ADDR_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *LSA_PORT_P1 - Port 1 Last Source Address |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LSA_PORT_P1 :: LST_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P1_LST_ADDR_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P1_LST_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P1_LST_ADDR_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *LSA_PORT_P2 - Port 2 Last Source Address |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LSA_PORT_P2 :: LST_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P2_LST_ADDR_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P2_LST_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P2_LST_ADDR_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *LSA_PORT_P3 - Port 3 Last Source Address |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LSA_PORT_P3 :: LST_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P3_LST_ADDR_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P3_LST_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P3_LST_ADDR_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *LSA_PORT_P4 - Port 4 Last Source Address |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LSA_PORT_P4 :: LST_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P4_LST_ADDR_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P4_LST_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P4_LST_ADDR_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *LSA_PORT_P5 - Port 5 Last Source Address |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LSA_PORT_P5 :: LST_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P5_LST_ADDR_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P5_LST_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P5_LST_ADDR_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *LSA_PORT_P7 - Port 7 Last Source Address |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LSA_PORT_P7 :: LST_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P7_LST_ADDR_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P7_LST_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P7_LST_ADDR_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *LSA_PORT_P8 - Port 8 Last Source Address |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LSA_PORT_P8 :: LST_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_LSA_PORT_P8_LST_ADDR_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P8_LST_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LSA_PORT_P8_LST_ADDR_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *BIST_STS0 - BIST Status Register 0 |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BIST_STS0 :: BIST_STS0 [47:00] */ |
| #define BCHP_SWITCH_CORE_BIST_STS0_BIST_STS0_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_BIST_STS0_BIST_STS0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BIST_STS0_BIST_STS0_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *BIST_STS1 - BIST Status Register 1 |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BIST_STS1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BIST_STS1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BIST_STS1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BIST_STS1 :: BIST_STS1 [15:00] */ |
| #define BCHP_SWITCH_CORE_BIST_STS1_BIST_STS1_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_BIST_STS1_BIST_STS1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BIST_STS1_BIST_STS1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PBPTRFIFO_0 - PBPTRFIFO Status Register 0(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P5 [47:40] */ |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P5_MASK 0xff0000000000 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P5_SHIFT 40 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P5_DEFAULT 0x000000000002 |
| |
| /* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P4 [39:32] */ |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P4_MASK 0x00ff00000000 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P4_SHIFT 32 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P4_DEFAULT 0x000000000002 |
| |
| /* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P3 [31:24] */ |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P3_MASK 0x0000ff000000 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P3_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P3_DEFAULT 0x000000000002 |
| |
| /* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P2 [23:16] */ |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P2_MASK 0x000000ff0000 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P2_SHIFT 16 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P2_DEFAULT 0x000000000002 |
| |
| /* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P1 [15:08] */ |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P1_MASK 0x00000000ff00 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P1_SHIFT 8 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P1_DEFAULT 0x000000000002 |
| |
| /* SWITCH_CORE :: PBPTRFIFO_0 :: VALID_CNT_P0 [07:00] */ |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P0_MASK 0x0000000000ff |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_0_VALID_CNT_P0_DEFAULT 0x000000000002 |
| |
| /*************************************************************************** |
| *PBPTRFIFO_1 - PBPTRFIFO Status Register 1(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PBPTRFIFO_1 :: SWITCH_RESV_1 [31:24] */ |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_1_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_1_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PBPTRFIFO_1 :: VALID_CNT_P8 [23:16] */ |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P8_MASK 0x00ff0000 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P8_SHIFT 16 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P8_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PBPTRFIFO_1 :: VALID_CNT_P7 [15:08] */ |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P7_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P7_SHIFT 8 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1_VALID_CNT_P7_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PBPTRFIFO_1 :: SWITCH_RESV_0 [07:00] */ |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_0_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PBPTRFIFO_1_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STRAP_PIN_STATUS - Strap Pin Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STRAP_PIN_STATUS :: STRAP_VALUE_VECTOR [31:00] */ |
| #define BCHP_SWITCH_CORE_STRAP_PIN_STATUS_STRAP_VALUE_VECTOR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_STRAP_PIN_STATUS_STRAP_VALUE_VECTOR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STRAP_PIN_STATUS_STRAP_VALUE_VECTOR_DEFAULT 0x000003f8 |
| |
| /*************************************************************************** |
| *DIRECT_INPUT_CTRL_VALUE - Direct Input Control Value Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DIRECT_INPUT_CTRL_VALUE :: SWITCH_RESV [31:02] */ |
| #define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_SWITCH_RESV_MASK 0xfffffffc |
| #define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_SWITCH_RESV_SHIFT 2 |
| #define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DIRECT_INPUT_CTRL_VALUE :: DIRECT_INPUT_CTRL_VALUE [01:00] */ |
| #define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_DIRECT_INPUT_CTRL_VALUE_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_DIRECT_INPUT_CTRL_VALUE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE_DIRECT_INPUT_CTRL_VALUE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_STATUS - Reset Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RESET_STATUS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_RESET_STATUS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: RESET_STATUS :: SWITCH_RESV_1 [15:11] */ |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_1_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_1_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RESET_STATUS :: SOC_BOOT_DN [10:10] */ |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SOC_BOOT_DN_MASK 0x00000400 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SOC_BOOT_DN_SHIFT 10 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SOC_BOOT_DN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RESET_STATUS :: SW_CORE_RST_STS [09:09] */ |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SW_CORE_RST_STS_MASK 0x00000200 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SW_CORE_RST_STS_SHIFT 9 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SW_CORE_RST_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RESET_STATUS :: SW_REG_RST_STS [08:08] */ |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SW_REG_RST_STS_MASK 0x00000100 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SW_REG_RST_STS_SHIFT 8 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SW_REG_RST_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RESET_STATUS :: SWITCH_RESV_0 [07:06] */ |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_0_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_0_SHIFT 6 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RESET_STATUS :: SD_RST_STS [05:05] */ |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SD_RST_STS_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SD_RST_STS_SHIFT 5 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SD_RST_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RESET_STATUS :: SPHY_RST_STS [04:04] */ |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SPHY_RST_STS_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SPHY_RST_STS_SHIFT 4 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_SPHY_RST_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RESET_STATUS :: QPHY_RST_STS [03:00] */ |
| #define BCHP_SWITCH_CORE_RESET_STATUS_QPHY_RST_STS_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_RESET_STATUS_QPHY_RST_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RESET_STATUS_QPHY_RST_STS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ENG_DET_STS - PHY Energy Detect Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ENG_DET_STS :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_ENG_DET_STS_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_ENG_DET_STS_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: ENG_DET_STS :: ENG_DET_STS [07:00] */ |
| #define BCHP_SWITCH_CORE_ENG_DET_STS_ENG_DET_STS_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_ENG_DET_STS_ENG_DET_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ENG_DET_STS_ENG_DET_STS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ENG_DET_STS_CHG - PHY Energy Detect Status Change Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ENG_DET_STS_CHG :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: ENG_DET_STS_CHG :: ENG_DET_STS_CHG [07:00] */ |
| #define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_ENG_DET_STS_CHG_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_ENG_DET_STS_CHG_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ENG_DET_STS_CHG_ENG_DET_STS_CHG_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STREG_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STREG_REG_SPARE0 :: STREG_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_STREG_REG_SPARE0_STREG_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_STREG_REG_SPARE0_STREG_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STREG_REG_SPARE0_STREG_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STREG_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STREG_REG_SPARE1 :: STREG_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_STREG_REG_SPARE1_STREG_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_STREG_REG_SPARE1_STREG_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STREG_REG_SPARE1_STREG_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GMNGCFG - Global Management Configuration Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: GMNGCFG :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_GMNGCFG_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_GMNGCFG_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: GMNGCFG :: FRM_MNGP [07:06] */ |
| #define BCHP_SWITCH_CORE_GMNGCFG_FRM_MNGP_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_GMNGCFG_FRM_MNGP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_GMNGCFG_FRM_MNGP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: GMNGCFG :: SWITCH_RESV [05:02] */ |
| #define BCHP_SWITCH_CORE_GMNGCFG_SWITCH_RESV_MASK 0x0000003c |
| #define BCHP_SWITCH_CORE_GMNGCFG_SWITCH_RESV_SHIFT 2 |
| #define BCHP_SWITCH_CORE_GMNGCFG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: GMNGCFG :: RXBPDU_EN [01:01] */ |
| #define BCHP_SWITCH_CORE_GMNGCFG_RXBPDU_EN_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_GMNGCFG_RXBPDU_EN_SHIFT 1 |
| #define BCHP_SWITCH_CORE_GMNGCFG_RXBPDU_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: GMNGCFG :: RST_MIB_CNT [00:00] */ |
| #define BCHP_SWITCH_CORE_GMNGCFG_RST_MIB_CNT_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_GMNGCFG_RST_MIB_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_GMNGCFG_RST_MIB_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IMP0_PRT_ID - IMP/IMP0 Port ID Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IMP0_PRT_ID :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_IMP0_PRT_ID_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_IMP0_PRT_ID_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: IMP0_PRT_ID :: SWITCH_RESV [07:04] */ |
| #define BCHP_SWITCH_CORE_IMP0_PRT_ID_SWITCH_RESV_MASK 0x000000f0 |
| #define BCHP_SWITCH_CORE_IMP0_PRT_ID_SWITCH_RESV_SHIFT 4 |
| #define BCHP_SWITCH_CORE_IMP0_PRT_ID_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IMP0_PRT_ID :: IMP0_PRT_ID [03:00] */ |
| #define BCHP_SWITCH_CORE_IMP0_PRT_ID_IMP0_PRT_ID_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_IMP0_PRT_ID_IMP0_PRT_ID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IMP0_PRT_ID_IMP0_PRT_ID_DEFAULT 0x00000008 |
| |
| /*************************************************************************** |
| *IMP1_PRT_ID - IMP1 Port ID Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IMP1_PRT_ID :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_IMP1_PRT_ID_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_IMP1_PRT_ID_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: IMP1_PRT_ID :: SWITCH_RESV [07:04] */ |
| #define BCHP_SWITCH_CORE_IMP1_PRT_ID_SWITCH_RESV_MASK 0x000000f0 |
| #define BCHP_SWITCH_CORE_IMP1_PRT_ID_SWITCH_RESV_SHIFT 4 |
| #define BCHP_SWITCH_CORE_IMP1_PRT_ID_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IMP1_PRT_ID :: IMP1_PRT_ID [03:00] */ |
| #define BCHP_SWITCH_CORE_IMP1_PRT_ID_IMP1_PRT_ID_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_IMP1_PRT_ID_IMP1_PRT_ID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IMP1_PRT_ID_IMP1_PRT_ID_DEFAULT 0x00000005 |
| |
| /*************************************************************************** |
| *BRCM_HDR_CTRL - BRCM Header Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BRCM_HDR_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: BRCM_HDR_CTRL :: SWITCH_RESV [07:03] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_SWITCH_RESV_MASK 0x000000f8 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_SWITCH_RESV_SHIFT 3 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BRCM_HDR_CTRL :: BRCM_HDR_EN [02:00] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_BRCM_HDR_EN_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_BRCM_HDR_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL_BRCM_HDR_EN_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SPTAGT - Aging Time Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SPTAGT :: SWITCH_RESV [31:21] */ |
| #define BCHP_SWITCH_CORE_SPTAGT_SWITCH_RESV_MASK 0xffe00000 |
| #define BCHP_SWITCH_CORE_SPTAGT_SWITCH_RESV_SHIFT 21 |
| #define BCHP_SWITCH_CORE_SPTAGT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SPTAGT :: AGE_CHANGE_EN [20:20] */ |
| #define BCHP_SWITCH_CORE_SPTAGT_AGE_CHANGE_EN_MASK 0x00100000 |
| #define BCHP_SWITCH_CORE_SPTAGT_AGE_CHANGE_EN_SHIFT 20 |
| #define BCHP_SWITCH_CORE_SPTAGT_AGE_CHANGE_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SPTAGT :: AGE_TIME [19:00] */ |
| #define BCHP_SWITCH_CORE_SPTAGT_AGE_TIME_MASK 0x000fffff |
| #define BCHP_SWITCH_CORE_SPTAGT_AGE_TIME_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SPTAGT_AGE_TIME_DEFAULT 0x0000012c |
| |
| /*************************************************************************** |
| *BRCM_HDR_CTRL2 - BRCM Header Control 2 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BRCM_HDR_CTRL2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BRCM_HDR_CTRL2 :: SWITCH_RESV_1 [15:09] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_1_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_1_SHIFT 9 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BRCM_HDR_CTRL2 :: SWITCH_RESV_0 [08:05] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_0_MASK 0x000001e0 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_0_SHIFT 5 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BRCM_HDR_CTRL2 :: BRCM_HDR_EN [04:00] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_BRCM_HDR_EN_MASK 0x0000001f |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_BRCM_HDR_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_CTRL2_BRCM_HDR_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IPG_SHRNK_CTRL - IPG Shrink Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IPG_SHRNK_CTRL :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IPG_SHRNK_CTRL :: IPG_SHKCTRL [17:00] */ |
| #define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_IPG_SHKCTRL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_IPG_SHKCTRL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IPG_SHRNK_CTRL_IPG_SHKCTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MIRCAPCTL - Mirror Capture Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MIRCAPCTL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MIRCAPCTL :: MIR_EN [15:15] */ |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_MIR_EN_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_MIR_EN_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_MIR_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MIRCAPCTL :: BLK_NOT_MIR [14:14] */ |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_BLK_NOT_MIR_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_BLK_NOT_MIR_SHIFT 14 |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_BLK_NOT_MIR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MIRCAPCTL :: SWITCH_RESV_1 [13:06] */ |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_1_MASK 0x00003fc0 |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_1_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MIRCAPCTL :: SWITCH_RESV_0 [05:04] */ |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_0_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_0_SHIFT 4 |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MIRCAPCTL :: SMIR_CAP_PORT [03:00] */ |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_SMIR_CAP_PORT_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_SMIR_CAP_PORT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MIRCAPCTL_SMIR_CAP_PORT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IGMIRCTL - Ingress Mirror Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IGMIRCTL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_IGMIRCTL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_IGMIRCTL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: IGMIRCTL :: IN_MIR_FLTR [15:14] */ |
| #define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_FLTR_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_FLTR_SHIFT 14 |
| #define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_FLTR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IGMIRCTL :: IN_DIV_EN [13:13] */ |
| #define BCHP_SWITCH_CORE_IGMIRCTL_IN_DIV_EN_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_IGMIRCTL_IN_DIV_EN_SHIFT 13 |
| #define BCHP_SWITCH_CORE_IGMIRCTL_IN_DIV_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IGMIRCTL :: SWITCH_RESV [12:09] */ |
| #define BCHP_SWITCH_CORE_IGMIRCTL_SWITCH_RESV_MASK 0x00001e00 |
| #define BCHP_SWITCH_CORE_IGMIRCTL_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_IGMIRCTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IGMIRCTL :: IN_MIR_MSK [08:00] */ |
| #define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_MSK_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_MSK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IGMIRCTL_IN_MIR_MSK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IGMIRDIV - Ingress Mirror Divider Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IGMIRDIV :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_IGMIRDIV_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_IGMIRDIV_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: IGMIRDIV :: SWITCH_RESV [15:10] */ |
| #define BCHP_SWITCH_CORE_IGMIRDIV_SWITCH_RESV_MASK 0x0000fc00 |
| #define BCHP_SWITCH_CORE_IGMIRDIV_SWITCH_RESV_SHIFT 10 |
| #define BCHP_SWITCH_CORE_IGMIRDIV_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IGMIRDIV :: IN_MIR_DIV [09:00] */ |
| #define BCHP_SWITCH_CORE_IGMIRDIV_IN_MIR_DIV_MASK 0x000003ff |
| #define BCHP_SWITCH_CORE_IGMIRDIV_IN_MIR_DIV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IGMIRDIV_IN_MIR_DIV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IGMIRMAC - Ingress Mirror Mac Address Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IGMIRMAC :: IN_MIR_MAC [47:00] */ |
| #define BCHP_SWITCH_CORE_IGMIRMAC_IN_MIR_MAC_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_IGMIRMAC_IN_MIR_MAC_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IGMIRMAC_IN_MIR_MAC_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *EGMIRCTL - Egress Mirror Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGMIRCTL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EGMIRCTL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EGMIRCTL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EGMIRCTL :: OUT_MIR_FLTR [15:14] */ |
| #define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_FLTR_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_FLTR_SHIFT 14 |
| #define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_FLTR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGMIRCTL :: OUT_DIV_EN [13:13] */ |
| #define BCHP_SWITCH_CORE_EGMIRCTL_OUT_DIV_EN_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_EGMIRCTL_OUT_DIV_EN_SHIFT 13 |
| #define BCHP_SWITCH_CORE_EGMIRCTL_OUT_DIV_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGMIRCTL :: SWITCH_RESV [12:09] */ |
| #define BCHP_SWITCH_CORE_EGMIRCTL_SWITCH_RESV_MASK 0x00001e00 |
| #define BCHP_SWITCH_CORE_EGMIRCTL_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_EGMIRCTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGMIRCTL :: OUT_MIR_MSK [08:00] */ |
| #define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_MSK_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_MSK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGMIRCTL_OUT_MIR_MSK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGMIRDIV - Egress Mirror Divider Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGMIRDIV :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EGMIRDIV_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EGMIRDIV_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EGMIRDIV :: SWITCH_RESV [15:10] */ |
| #define BCHP_SWITCH_CORE_EGMIRDIV_SWITCH_RESV_MASK 0x0000fc00 |
| #define BCHP_SWITCH_CORE_EGMIRDIV_SWITCH_RESV_SHIFT 10 |
| #define BCHP_SWITCH_CORE_EGMIRDIV_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGMIRDIV :: OUT_MIR_DIV [09:00] */ |
| #define BCHP_SWITCH_CORE_EGMIRDIV_OUT_MIR_DIV_MASK 0x000003ff |
| #define BCHP_SWITCH_CORE_EGMIRDIV_OUT_MIR_DIV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGMIRDIV_OUT_MIR_DIV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGMIRMAC - Egress Mirror MAC Address Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGMIRMAC :: OUT_MIR_MAC [47:00] */ |
| #define BCHP_SWITCH_CORE_EGMIRMAC_OUT_MIR_MAC_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_EGMIRMAC_OUT_MIR_MAC_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGMIRMAC_OUT_MIR_MAC_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *MODEL_ID - Model ID Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MODEL_ID :: MODELID [31:00] */ |
| #define BCHP_SWITCH_CORE_MODEL_ID_MODELID_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_MODEL_ID_MODELID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MODEL_ID_MODELID_DEFAULT 0x00053012 |
| |
| /*************************************************************************** |
| *CHIP_REVID - Chip Version ID Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CHIP_REVID :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_CHIP_REVID_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_CHIP_REVID_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: CHIP_REVID :: REVID [07:00] */ |
| #define BCHP_SWITCH_CORE_CHIP_REVID_REVID_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_CHIP_REVID_REVID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CHIP_REVID_REVID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HL_PRTC_CTRL - High Level Protocol Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: SWITCH_RESV_1 [31:19] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_1_MASK 0xfff80000 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_1_SHIFT 19 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_QRY_FWD_MODE [18:18] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_MASK 0x00040000 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_SHIFT 18 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_QRY_EN [17:17] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_EN_MASK 0x00020000 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_EN_SHIFT 17 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_QRY_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_RPTDONE_FWD_MODE [16:16] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_MASK 0x00010000 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_SHIFT 16 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: MLD_RPTDONE_EN [15:15] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_EN_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_EN_SHIFT 15 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_MLD_RPTDONE_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_UKN_FWD_MODE [14:14] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_SHIFT 14 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_UKN_EN [13:13] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_EN_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_EN_SHIFT 13 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_UKN_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_QRY_FWD_MODE [12:12] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_SHIFT 12 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_QRY_EN [11:11] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_EN_MASK 0x00000800 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_EN_SHIFT 11 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_QRY_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_RPTLVE_FWD_MODE [10:10] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_MASK 0x00000400 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_SHIFT 10 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_RPTLVE_EN [09:09] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_EN_MASK 0x00000200 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_EN_SHIFT 9 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_RPTLVE_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: IGMP_DIP_EN [08:08] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_DIP_EN_MASK 0x00000100 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_DIP_EN_SHIFT 8 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_IGMP_DIP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: SWITCH_RESV_0 [07:06] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_0_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_0_SHIFT 6 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: ICMPv6_FWD_MODE [05:05] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPv6_FWD_MODE_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPv6_FWD_MODE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPv6_FWD_MODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: ICMPV6_EN [04:04] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV6_EN_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV6_EN_SHIFT 4 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV6_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: ICMPV4_EN [03:03] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV4_EN_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV4_EN_SHIFT 3 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ICMPV4_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: DHCP_EN [02:02] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_DHCP_EN_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_DHCP_EN_SHIFT 2 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_DHCP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: RARP_EN [01:01] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_RARP_EN_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_RARP_EN_SHIFT 1 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_RARP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: HL_PRTC_CTRL :: ARP_EN [00:00] */ |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ARP_EN_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ARP_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_HL_PRTC_CTRL_ARP_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RST_MIB_CNT_EN - Reset MIB Counter Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RST_MIB_CNT_EN :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: RST_MIB_CNT_EN :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RST_MIB_CNT_EN :: RST_MIB_CNT_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_RST_MIB_CNT_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_RST_MIB_CNT_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RST_MIB_CNT_EN_RST_MIB_CNT_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *IPG_SHRINK_2G_WA - IPG Shrink 2G Workaround Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IPG_SHRINK_2G_WA :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: IPG_SHRINK_2G_WA :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IPG_SHRINK_2G_WA :: VLD2_COND_DIS [08:00] */ |
| #define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_VLD2_COND_DIS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_VLD2_COND_DIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IPG_SHRINK_2G_WA_VLD2_COND_DIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BRCM_HDR_RX_DIS - Broadcom Header RX Disable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BRCM_HDR_RX_DIS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BRCM_HDR_RX_DIS :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BRCM_HDR_RX_DIS :: RX_DIS [08:00] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_RX_DIS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_RX_DIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_RX_DIS_RX_DIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BRCM_HDR_TX_DIS - Broadcom Header TX Disable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BRCM_HDR_TX_DIS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BRCM_HDR_TX_DIS :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BRCM_HDR_TX_DIS :: TX_DIS [08:00] */ |
| #define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_TX_DIS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_TX_DIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BRCM_HDR_TX_DIS_TX_DIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MNGMODE_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MNGMODE_REG_SPARE0 :: MNGMODE_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MNGMODE_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MNGMODE_REG_SPARE1 :: MNGMODE_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INT_STS - External Host Raw Interrupt Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: INT_STS :: INT_STS [31:00] */ |
| #define BCHP_SWITCH_CORE_INT_STS_INT_STS_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_INT_STS_INT_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_INT_STS_INT_STS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INT_EN - External Host Interrupt Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: INT_EN :: INT_EN [31:00] */ |
| #define BCHP_SWITCH_CORE_INT_EN_INT_EN_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_INT_EN_INT_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_INT_EN_INT_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SLEEP_TIMER_IMP - IMP Port(port 8) Sleep Timer Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SLEEP_TIMER_IMP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SLEEP_TIMER_IMP :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SLEEP_TIMER_IMP :: IMP_SLEEP_TIMER [12:00] */ |
| #define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_IMP_SLEEP_TIMER_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_IMP_SLEEP_TIMER_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SLEEP_TIMER_IMP_IMP_SLEEP_TIMER_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT7_SLEEP_TIMER - Port 7 Sleep Timer Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT7_SLEEP_TIMER :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PORT7_SLEEP_TIMER :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT7_SLEEP_TIMER :: PORT7_SLEEP_TIMER [12:00] */ |
| #define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WAN_SLEEP_TIMER - WAN Port Sleep Timer Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WAN_SLEEP_TIMER :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: WAN_SLEEP_TIMER :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WAN_SLEEP_TIMER :: WAN_SLEEP_TIMER [12:00] */ |
| #define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SLEEP_STS - Port Sleep Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SLEEP_STS :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: PORT_SLEEP_STS :: SWITCH_RESV [07:03] */ |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_SWITCH_RESV_MASK 0x000000f8 |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_SWITCH_RESV_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SLEEP_STS :: PORT7_SLEEP_STS [02:02] */ |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_PORT7_SLEEP_STS_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_PORT7_SLEEP_STS_SHIFT 2 |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_PORT7_SLEEP_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SLEEP_STS :: WAN_PORT_SLEEP_STS [01:01] */ |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_SHIFT 1 |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SLEEP_STS :: IMP_PORT_SLEEP_STS [00:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INT_TRIGGER - Interrupt Trigger Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: INT_TRIGGER :: SWITCH_RESV [31:03] */ |
| #define BCHP_SWITCH_CORE_INT_TRIGGER_SWITCH_RESV_MASK 0xfffffff8 |
| #define BCHP_SWITCH_CORE_INT_TRIGGER_SWITCH_RESV_SHIFT 3 |
| #define BCHP_SWITCH_CORE_INT_TRIGGER_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: INT_TRIGGER :: INT_CPU_DOORBELL [02:02] */ |
| #define BCHP_SWITCH_CORE_INT_TRIGGER_INT_CPU_DOORBELL_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_INT_TRIGGER_INT_CPU_DOORBELL_SHIFT 2 |
| #define BCHP_SWITCH_CORE_INT_TRIGGER_INT_CPU_DOORBELL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: INT_TRIGGER :: EXT_CPU_DOORBELL [01:01] */ |
| #define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_DOORBELL_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_DOORBELL_SHIFT 1 |
| #define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_DOORBELL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: INT_TRIGGER :: EXT_CPU_INT [00:00] */ |
| #define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_INT_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_INT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_INT_TRIGGER_EXT_CPU_INT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LINK_STS_INT_EN - Link Status Interrupt Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LINK_STS_INT_EN :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_LINK_STS_INT_EN_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_LINK_STS_INT_EN_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: LINK_STS_INT_EN :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_LINK_STS_INT_EN_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_LINK_STS_INT_EN_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_LINK_STS_INT_EN_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LINK_STS_INT_EN :: LINK_STS_INT_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_LINK_STS_INT_EN_LINK_STS_INT_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_LINK_STS_INT_EN_LINK_STS_INT_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LINK_STS_INT_EN_LINK_STS_INT_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *ENG_DET_INT_EN - Energy Detection Interrupt Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ENG_DET_INT_EN :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_ENG_DET_INT_EN_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_ENG_DET_INT_EN_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: ENG_DET_INT_EN :: SWITCH_RESV_1 [15:09] */ |
| #define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_1_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_1_SHIFT 9 |
| #define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ENG_DET_INT_EN :: SWITCH_RESV_0 [08:05] */ |
| #define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_0_MASK 0x000001e0 |
| #define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_0_SHIFT 5 |
| #define BCHP_SWITCH_CORE_ENG_DET_INT_EN_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ENG_DET_INT_EN :: ENG_DET_INT_EN [04:00] */ |
| #define BCHP_SWITCH_CORE_ENG_DET_INT_EN_ENG_DET_INT_EN_MASK 0x0000001f |
| #define BCHP_SWITCH_CORE_ENG_DET_INT_EN_ENG_DET_INT_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ENG_DET_INT_EN_ENG_DET_INT_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LPI_STS_CHG_INT_EN - LPI Status Change Interrupt Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LPI_STS_CHG_INT_EN :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: LPI_STS_CHG_INT_EN :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LPI_STS_CHG_INT_EN :: LPI_STS_CHG_INT_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *MEM_ECC_ERR_INT_STS - Memory ECC Double-Error-Detection Interrupt Status (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: TXQ_ECC_DED_INT_STS [10:10] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_MASK 0x00000400 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_SHIFT 10 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: MIB_ECC_DED_INT_STS [09:09] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_MASK 0x00000200 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: EVT_ECC_DED_INT_STS [08:08] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_MASK 0x00000100 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_SHIFT 8 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: STS_ECC_DED_INT_STS [07:07] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_SHIFT 7 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: ACTRAT_ECC_DED_INT_STS [06:06] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: TCS_ECC_DED_INT_STS [05:05] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_SHIFT 5 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: FM_ECC_DED_INT_STS [04:04] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_SHIFT 4 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: BT_ECC_DED_INT_STS [03:03] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_SHIFT 3 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: VL_ECC_DED_INT_STS [02:02] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_SHIFT 2 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: ARL_SCON_ECC_DED_INT_STS [01:01] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_SHIFT 1 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_STS :: ARL_ATMU_ECC_DED_INT_STS [00:00] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_ECC_ERR_INT_EN - Memory ECC Double-Error-Detection Interrupt Enable (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: TXQ_ECC_DED_INT_EN [10:10] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_MASK 0x00000400 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_SHIFT 10 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: MIB_ECC_DED_INT_EN [09:09] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_MASK 0x00000200 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: EVT_ECC_DED_INT_EN [08:08] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_MASK 0x00000100 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_SHIFT 8 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: STS_ECC_DED_INT_EN [07:07] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_SHIFT 7 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: ACTRAT_ECC_DED_INT_EN [06:06] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: TCS_ECC_DED_INT_EN [05:05] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_SHIFT 5 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: FM_ECC_DED_INT_EN [04:04] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_SHIFT 4 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: BT_ECC_DED_INT_EN [03:03] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_SHIFT 3 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: VL_ECC_DED_INT_EN [02:02] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_SHIFT 2 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: ARL_SCON_ECC_DED_INT_EN [01:01] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_SHIFT 1 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: MEM_ECC_ERR_INT_EN :: ARL_ATMU_ECC_DED_INT_EN [00:00] */ |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PORT_EVT_ECC_ERR_STS - Per Port EVT Table ECC Double-Error-Detection Error Status (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_EVT_ECC_ERR_STS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PORT_EVT_ECC_ERR_STS :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_EVT_ECC_ERR_STS :: EVT_ECC_ERR_STS [08:00] */ |
| #define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_MIB_ECC_ERR_STS - Per Port MIB Counter ECC Double-Error-Detection Error Status (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_MIB_ECC_ERR_STS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PORT_MIB_ECC_ERR_STS :: SWITCH_RESV [15:10] */ |
| #define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_SWITCH_RESV_MASK 0x0000fc00 |
| #define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_SWITCH_RESV_SHIFT 10 |
| #define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_MIB_ECC_ERR_STS :: MIB_ECC_ERR_STS [09:00] */ |
| #define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_MASK 0x000003ff |
| #define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_TXQ_ECC_ERR_STS - Per Port TXQ ECC Double-Error-Detection Error Status (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_TXQ_ECC_ERR_STS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PORT_TXQ_ECC_ERR_STS :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_TXQ_ECC_ERR_STS :: TXQ_ECC_ERR_STS [08:00] */ |
| #define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PROBE_BUS_CTL - Probe Bus Control Registers(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PROBE_BUS_CTL :: PROBE_DEBUG_CTL [31:24] */ |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_DEBUG_CTL_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_DEBUG_CTL_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_DEBUG_CTL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PROBE_BUS_CTL :: PROBE_CLK_SEL [23:16] */ |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_CLK_SEL_MASK 0x00ff0000 |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_CLK_SEL_SHIFT 16 |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PROBE_CLK_SEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PROBE_BUS_CTL :: PER_PORT_DEBUG_SEL [15:08] */ |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_SHIFT 8 |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PROBE_BUS_CTL :: PER_PORT_PROBE_SEL [07:00] */ |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MDC_EXTEND_CTRL - MDC Extend Clock Control Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MDC_EXTEND_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: MDC_EXTEND_CTRL :: SWITCH_RESV [07:01] */ |
| #define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_SWITCH_RESV_MASK 0x000000fe |
| #define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_SWITCH_RESV_SHIFT 1 |
| #define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MDC_EXTEND_CTRL :: EXTENDED_MDC_EN [00:00] */ |
| #define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PPPOE_SESSION_PARSE_EN - PPPoE Session Packet Parsing Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PPPOE_SESSION_PARSE_EN :: SWITCH_RESV [31:25] */ |
| #define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_SWITCH_RESV_MASK 0xfe000000 |
| #define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_SWITCH_RESV_SHIFT 25 |
| #define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PPPOE_SESSION_PARSE_EN :: PPPOE_SESSION_PARSE_EN [24:16] */ |
| #define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_MASK 0x01ff0000 |
| #define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_SHIFT 16 |
| #define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PPPOE_SESSION_PARSE_EN :: PPPOE_SESSION_ETYPE [15:00] */ |
| #define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_DEFAULT 0x00008864 |
| |
| /*************************************************************************** |
| *CTLREG_1_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CTLREG_1_REG_SPARE0 :: CTLREG_1_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CTLREG_1_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CTLREG_1_REG_SPARE1 :: CTLREG_1_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GARLCFG - Global ARL Configuration Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: GARLCFG :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_GARLCFG_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_GARLCFG_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: GARLCFG :: SWITCH_RESV_1 [07:03] */ |
| #define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_1_MASK 0x000000f8 |
| #define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_1_SHIFT 3 |
| #define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: GARLCFG :: AGE_ACC [02:02] */ |
| #define BCHP_SWITCH_CORE_GARLCFG_AGE_ACC_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_GARLCFG_AGE_ACC_SHIFT 2 |
| #define BCHP_SWITCH_CORE_GARLCFG_AGE_ACC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: GARLCFG :: SWITCH_RESV_0 [01:01] */ |
| #define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_0_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_0_SHIFT 1 |
| #define BCHP_SWITCH_CORE_GARLCFG_SWITCH_RESV_0_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: GARLCFG :: HASH_DISABLE [00:00] */ |
| #define BCHP_SWITCH_CORE_GARLCFG_HASH_DISABLE_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_GARLCFG_HASH_DISABLE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_GARLCFG_HASH_DISABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BPDU_MCADDR - BPDU Multicast Address Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BPDU_MCADDR :: BPDU_MC_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_BPDU_MCADDR_BPDU_MC_ADDR_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_BPDU_MCADDR_BPDU_MC_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BPDU_MCADDR_BPDU_MC_ADDR_DEFAULT 0x0180c2000000 |
| |
| /*************************************************************************** |
| *MULTI_PORT_CTL - Multiport Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MULTI_PORT_CTL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT0_TS_EN [15:15] */ |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT0_TS_EN_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT0_TS_EN_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT0_TS_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_DA_HIT_EN [14:14] */ |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_DA_HIT_EN_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_DA_HIT_EN_SHIFT 14 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_DA_HIT_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MULTI_PORT_CTL :: SWITCH_RESV [13:12] */ |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_SWITCH_RESV_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_SWITCH_RESV_SHIFT 12 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL5 [11:10] */ |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL5_MASK 0x00000c00 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL5_SHIFT 10 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL4 [09:08] */ |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL4_MASK 0x00000300 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL4_SHIFT 8 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL3 [07:06] */ |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL3_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL3_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL2 [05:04] */ |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL2_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL2_SHIFT 4 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL1 [03:02] */ |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL1_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL1_SHIFT 2 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MULTI_PORT_CTL :: MPORT_CTRL0 [01:00] */ |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL0_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MULTI_PORT_CTL_MPORT_CTRL0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MULTIPORT_ADDR0 - Multiport Address 0 Register (Default for TS) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MULTIPORT_ADDR0 :: MPORT_E_TYPE [63:48] */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_E_TYPE_MASK 0xffff000000000000 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_E_TYPE_SHIFT 48 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_E_TYPE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: MULTIPORT_ADDR0 :: MPORT_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_ADDR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR0_MPORT_ADDR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MPORTVEC0 - Multiport Vector 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MPORTVEC0 :: SWITCH_RESV [31:09] */ |
| #define BCHP_SWITCH_CORE_MPORTVEC0_SWITCH_RESV_MASK 0xfffffe00 |
| #define BCHP_SWITCH_CORE_MPORTVEC0_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MPORTVEC0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MPORTVEC0 :: PORT_VCTR [08:00] */ |
| #define BCHP_SWITCH_CORE_MPORTVEC0_PORT_VCTR_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_MPORTVEC0_PORT_VCTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MPORTVEC0_PORT_VCTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MULTIPORT_ADDR1 - Multiport Address 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MULTIPORT_ADDR1 :: MPORT_E_TYPE [63:48] */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_E_TYPE_MASK 0xffff000000000000 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_E_TYPE_SHIFT 48 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_E_TYPE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: MULTIPORT_ADDR1 :: MPORT_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_ADDR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR1_MPORT_ADDR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MPORTVEC1 - Multiport Vector 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MPORTVEC1 :: SWITCH_RESV [31:09] */ |
| #define BCHP_SWITCH_CORE_MPORTVEC1_SWITCH_RESV_MASK 0xfffffe00 |
| #define BCHP_SWITCH_CORE_MPORTVEC1_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MPORTVEC1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MPORTVEC1 :: PORT_VCTR [08:00] */ |
| #define BCHP_SWITCH_CORE_MPORTVEC1_PORT_VCTR_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_MPORTVEC1_PORT_VCTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MPORTVEC1_PORT_VCTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MULTIPORT_ADDR2 - Multiport Address 2 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MULTIPORT_ADDR2 :: MPORT_E_TYPE [63:48] */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_E_TYPE_MASK 0xffff000000000000 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_E_TYPE_SHIFT 48 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_E_TYPE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: MULTIPORT_ADDR2 :: MPORT_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_ADDR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR2_MPORT_ADDR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MPORTVEC2 - Multiport Vector 2 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MPORTVEC2 :: SWITCH_RESV [31:09] */ |
| #define BCHP_SWITCH_CORE_MPORTVEC2_SWITCH_RESV_MASK 0xfffffe00 |
| #define BCHP_SWITCH_CORE_MPORTVEC2_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MPORTVEC2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MPORTVEC2 :: PORT_VCTR [08:00] */ |
| #define BCHP_SWITCH_CORE_MPORTVEC2_PORT_VCTR_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_MPORTVEC2_PORT_VCTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MPORTVEC2_PORT_VCTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MULTIPORT_ADDR3 - Multiport Address 3 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MULTIPORT_ADDR3 :: MPORT_E_TYPE [63:48] */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_E_TYPE_MASK 0xffff000000000000 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_E_TYPE_SHIFT 48 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_E_TYPE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: MULTIPORT_ADDR3 :: MPORT_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_ADDR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR3_MPORT_ADDR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MPORTVEC3 - Multiport Vector 3 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MPORTVEC3 :: SWITCH_RESV [31:09] */ |
| #define BCHP_SWITCH_CORE_MPORTVEC3_SWITCH_RESV_MASK 0xfffffe00 |
| #define BCHP_SWITCH_CORE_MPORTVEC3_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MPORTVEC3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MPORTVEC3 :: PORT_VCTR [08:00] */ |
| #define BCHP_SWITCH_CORE_MPORTVEC3_PORT_VCTR_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_MPORTVEC3_PORT_VCTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MPORTVEC3_PORT_VCTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MULTIPORT_ADDR4 - Multiport Address 4 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MULTIPORT_ADDR4 :: MPORT_E_TYPE [63:48] */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_E_TYPE_MASK 0xffff000000000000 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_E_TYPE_SHIFT 48 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_E_TYPE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: MULTIPORT_ADDR4 :: MPORT_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_ADDR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR4_MPORT_ADDR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MPORTVEC4 - Multiport Vector 4 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MPORTVEC4 :: SWITCH_RESV [31:09] */ |
| #define BCHP_SWITCH_CORE_MPORTVEC4_SWITCH_RESV_MASK 0xfffffe00 |
| #define BCHP_SWITCH_CORE_MPORTVEC4_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MPORTVEC4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MPORTVEC4 :: PORT_VCTR [08:00] */ |
| #define BCHP_SWITCH_CORE_MPORTVEC4_PORT_VCTR_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_MPORTVEC4_PORT_VCTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MPORTVEC4_PORT_VCTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MULTIPORT_ADDR5 - Multiport Address 5 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MULTIPORT_ADDR5 :: MPORT_E_TYPE [63:48] */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_E_TYPE_MASK 0xffff000000000000 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_E_TYPE_SHIFT 48 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_E_TYPE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: MULTIPORT_ADDR5 :: MPORT_ADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_ADDR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MULTIPORT_ADDR5_MPORT_ADDR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MPORTVEC5 - Multiport Vector 5 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MPORTVEC5 :: SWITCH_RESV [31:09] */ |
| #define BCHP_SWITCH_CORE_MPORTVEC5_SWITCH_RESV_MASK 0xfffffe00 |
| #define BCHP_SWITCH_CORE_MPORTVEC5_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MPORTVEC5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MPORTVEC5 :: PORT_VCTR [08:00] */ |
| #define BCHP_SWITCH_CORE_MPORTVEC5_PORT_VCTR_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_MPORTVEC5_PORT_VCTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MPORTVEC5_PORT_VCTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARL_BIN_FULL_CNTR - ARL Bin Full Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARL_BIN_FULL_CNTR :: ARL_BIN_FUL_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARL_BIN_FULL_FWD - ARL Biin Full Forward Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARL_BIN_FULL_FWD :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: ARL_BIN_FULL_FWD :: Reserved [15:01] */ |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_Reserved_MASK 0x0000fffe |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_Reserved_SHIFT 1 |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_Reserved_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARL_BIN_FULL_FWD :: ARL_BIN_FULL_FWD_EN [00:00] */ |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLCTL_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLCTL_REG_SPARE0 :: ARLCTL_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLCTL_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLCTL_REG_SPARE1 :: ARLCTL_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_RWCTL - ARL Read/Write Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_RWCTL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: ARLA_RWCTL :: ARL_STRTDN [07:07] */ |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_STRTDN_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_STRTDN_SHIFT 7 |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_STRTDN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_RWCTL :: IVL_SVL_SELECT [06:06] */ |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_IVL_SVL_SELECT_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_IVL_SVL_SELECT_SHIFT 6 |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_IVL_SVL_SELECT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_RWCTL :: SWITCH_RESV [05:01] */ |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_SWITCH_RESV_MASK 0x0000003e |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_SWITCH_RESV_SHIFT 1 |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_RWCTL :: ARL_RW [00:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_RW_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_RW_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_RWCTL_ARL_RW_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_MAC - MAC Address Index Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_MAC :: MAC_ADDR_INDX [47:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_MAC_MAC_ADDR_INDX_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MAC_MAC_ADDR_INDX_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_MAC_MAC_ADDR_INDX_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *ARLA_VID - VID Index Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_VID :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_ARLA_VID_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_ARLA_VID_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: ARLA_VID :: ARLA_VIDTAB_RSRV0 [15:12] */ |
| #define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_RSRV0_MASK 0x0000f000 |
| #define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_RSRV0_SHIFT 12 |
| #define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_RSRV0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_VID :: ARLA_VIDTAB_INDX [11:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_INDX_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_INDX_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_VID_ARLA_VIDTAB_INDX_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_MACVID_ENTRY0 - ARL MAC/VID Entry 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_MACVID_ENTRY0 :: SWITCH_RESV [63:60] */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_SWITCH_RESV_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_SWITCH_RESV_SHIFT 60 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: ARLA_MACVID_ENTRY0 :: VID [59:48] */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_VID_MASK 0x0fff000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_VID_SHIFT 48 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_VID_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: ARLA_MACVID_ENTRY0 :: ARL_MACADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_ARL_MACADDR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_ARL_MACADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY0_ARL_MACADDR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *ARLA_FWD_ENTRY0 - ARL FWD Entry 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: SWITCH_RESV [31:17] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_SWITCH_RESV_MASK 0xfffe0000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_SWITCH_RESV_SHIFT 17 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_VALID [16:16] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_VALID_MASK 0x00010000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_VALID_SHIFT 16 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_VALID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_STATIC [15:15] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_STATIC_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_STATIC_SHIFT 15 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_STATIC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_AGE [14:14] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_AGE_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_AGE_SHIFT 14 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_AGE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_PRI [13:11] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_PRI_MASK 0x00003800 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_PRI_SHIFT 11 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_PRI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: ARL_CON [10:09] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_CON_MASK 0x00000600 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_CON_SHIFT 9 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_ARL_CON_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY0 :: PORTID [08:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_PORTID_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_PORTID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY0_PORTID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_MACVID_ENTRY1 - ARL MAC/VID Entry 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_MACVID_ENTRY1 :: SWITCH_RESV [63:60] */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_SWITCH_RESV_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_SWITCH_RESV_SHIFT 60 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: ARLA_MACVID_ENTRY1 :: VID [59:48] */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_VID_MASK 0x0fff000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_VID_SHIFT 48 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_VID_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: ARLA_MACVID_ENTRY1 :: ARL_MACADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_ARL_MACADDR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_ARL_MACADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY1_ARL_MACADDR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *ARLA_FWD_ENTRY1 - ARL FWD Entry 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: SWITCH_RESV [31:17] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_SWITCH_RESV_MASK 0xfffe0000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_SWITCH_RESV_SHIFT 17 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_VALID [16:16] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_VALID_MASK 0x00010000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_VALID_SHIFT 16 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_VALID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_STATIC [15:15] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_STATIC_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_STATIC_SHIFT 15 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_STATIC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_AGE [14:14] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_AGE_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_AGE_SHIFT 14 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_AGE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_PRI [13:11] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_PRI_MASK 0x00003800 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_PRI_SHIFT 11 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_PRI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: ARL_CON [10:09] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_CON_MASK 0x00000600 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_CON_SHIFT 9 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_ARL_CON_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY1 :: PORTID [08:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_PORTID_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_PORTID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY1_PORTID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_MACVID_ENTRY2 - ARL MAC/VID Entry 2 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_MACVID_ENTRY2 :: SWITCH_RESV [63:60] */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_SWITCH_RESV_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_SWITCH_RESV_SHIFT 60 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: ARLA_MACVID_ENTRY2 :: VID [59:48] */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_VID_MASK 0x0fff000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_VID_SHIFT 48 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_VID_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: ARLA_MACVID_ENTRY2 :: ARL_MACADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_ARL_MACADDR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_ARL_MACADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY2_ARL_MACADDR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *ARLA_FWD_ENTRY2 - ARL FWD Entry 2 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: SWITCH_RESV [31:17] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_SWITCH_RESV_MASK 0xfffe0000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_SWITCH_RESV_SHIFT 17 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_VALID [16:16] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_VALID_MASK 0x00010000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_VALID_SHIFT 16 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_VALID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_STATIC [15:15] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_STATIC_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_STATIC_SHIFT 15 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_STATIC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_AGE [14:14] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_AGE_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_AGE_SHIFT 14 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_AGE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_PRI [13:11] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_PRI_MASK 0x00003800 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_PRI_SHIFT 11 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_PRI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: ARL_CON [10:09] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_CON_MASK 0x00000600 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_CON_SHIFT 9 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_ARL_CON_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY2 :: PORTID [08:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_PORTID_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_PORTID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY2_PORTID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_MACVID_ENTRY3 - ARL MAC/VID Entry 3 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_MACVID_ENTRY3 :: SWITCH_RESV [63:60] */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_SWITCH_RESV_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_SWITCH_RESV_SHIFT 60 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: ARLA_MACVID_ENTRY3 :: VID [59:48] */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_VID_MASK 0x0fff000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_VID_SHIFT 48 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_VID_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: ARLA_MACVID_ENTRY3 :: ARL_MACADDR [47:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_ARL_MACADDR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_ARL_MACADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_MACVID_ENTRY3_ARL_MACADDR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *ARLA_FWD_ENTRY3 - ARL FWD Entry 3 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: SWITCH_RESV [31:17] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_SWITCH_RESV_MASK 0xfffe0000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_SWITCH_RESV_SHIFT 17 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_VALID [16:16] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_VALID_MASK 0x00010000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_VALID_SHIFT 16 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_VALID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_STATIC [15:15] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_STATIC_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_STATIC_SHIFT 15 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_STATIC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_AGE [14:14] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_AGE_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_AGE_SHIFT 14 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_AGE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_PRI [13:11] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_PRI_MASK 0x00003800 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_PRI_SHIFT 11 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_PRI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: ARL_CON [10:09] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_CON_MASK 0x00000600 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_CON_SHIFT 9 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_ARL_CON_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_FWD_ENTRY3 :: PORTID [08:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_PORTID_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_PORTID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_FWD_ENTRY3_PORTID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_SRCH_CTL - ARL Search Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_SRCH_CTL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_CTL :: ARLA_SRCH_STDN [07:07] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_STDN_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_STDN_SHIFT 7 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_STDN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_CTL :: SWITCH_RESV [06:01] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_SWITCH_RESV_MASK 0x0000007e |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_SWITCH_RESV_SHIFT 1 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_CTL :: ARLA_SRCH_VLID [00:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_VLID_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_VLID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_CTL_ARLA_SRCH_VLID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_SRCH_ADR - ARL Search Address Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_SRCH_ADR :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_ADR :: ARLA_SRCH_ADR_VALID [15:15] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_SHIFT 15 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_ADR :: ARLA_SRCH_ADDRESS [14:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_MASK 0x00007fff |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_SRCH_RSLT_0_MACVID - ARL Search MAC/VID Result 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_0_MACVID :: SWITCH_RESV [63:60] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_SWITCH_RESV_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_SWITCH_RESV_SHIFT 60 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_0_MACVID :: ARLA_SRCH_RSLT_VID_0 [59:48] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_MASK 0x0fff000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_SHIFT 48 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_0_MACVID :: ARLA_SRCH_MACADDR_0 [47:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *ARLA_SRCH_RSLT_0 - ARL Search Result 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: SWITCH_RESV [31:17] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_SWITCH_RESV_MASK 0xfffe0000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_SWITCH_RESV_SHIFT 17 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_VLID_0 [16:16] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_MASK 0x00010000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_SHIFT 16 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_STATIC_0 [15:15] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_SHIFT 15 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_AGE_0 [14:14] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_SHIFT 14 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARLA_SRCH_RSLT_PRI_0 [13:11] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_MASK 0x00003800 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_SHIFT 11 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: ARL_CON_0 [10:09] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARL_CON_0_MASK 0x00000600 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARL_CON_0_SHIFT 9 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_ARL_CON_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_0 :: PORTID_0 [08:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_PORTID_0_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_PORTID_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_0_PORTID_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_SRCH_RSLT_1_MACVID - ARL Search MAC/VID Result 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_1_MACVID :: SWITCH_RESV [63:60] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_SWITCH_RESV_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_SWITCH_RESV_SHIFT 60 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_1_MACVID :: ARLA_SRCH_RSLT_VID_1 [59:48] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_MASK 0x0fff000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_SHIFT 48 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_1_MACVID :: ARLA_SRCH_MACADDR_1 [47:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *ARLA_SRCH_RSLT_1 - ARL Search Result 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: SWITCH_RESV [31:17] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_SWITCH_RESV_MASK 0xfffe0000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_SWITCH_RESV_SHIFT 17 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_VLID_1 [16:16] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_MASK 0x00010000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_SHIFT 16 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_STATIC_1 [15:15] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_SHIFT 15 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_AGE_1 [14:14] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_SHIFT 14 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARLA_SRCH_RSLT_PRI_1 [13:11] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_MASK 0x00003800 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_SHIFT 11 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: ARL_CON_1 [10:09] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARL_CON_1_MASK 0x00000600 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARL_CON_1_SHIFT 9 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_ARL_CON_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_SRCH_RSLT_1 :: PORTID_1 [08:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_PORTID_1_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_PORTID_1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_SRCH_RSLT_1_PORTID_1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_VTBL_RWCTRL - VTBL Read/Write/Clear Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: ARLA_VTBL_STDN [07:07] */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_SHIFT 7 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: SWITCH_RESV [06:02] */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_SWITCH_RESV_MASK 0x0000007c |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_SWITCH_RESV_SHIFT 2 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_VTBL_RWCTRL :: ARLA_VTBL_RW_CLR [01:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_VTBL_ADDR - VTBL Address Index Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_VTBL_ADDR :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: ARLA_VTBL_ADDR :: SWITCH_RESV [15:12] */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_SWITCH_RESV_MASK 0x0000f000 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_SWITCH_RESV_SHIFT 12 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_VTBL_ADDR :: VTBL_ADDR_INDEX [11:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLA_VTBL_ENTRY - VTBL Entry Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLA_VTBL_ENTRY :: SWITCH_RESV [31:22] */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_SWITCH_RESV_MASK 0xffc00000 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_SWITCH_RESV_SHIFT 22 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_VTBL_ENTRY :: FWD_MODE [21:21] */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MODE_MASK 0x00200000 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MODE_SHIFT 21 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_VTBL_ENTRY :: MSPT_INDEX [20:18] */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_MSPT_INDEX_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_MSPT_INDEX_SHIFT 18 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_MSPT_INDEX_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_VTBL_ENTRY :: UNTAG_MAP [17:09] */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_UNTAG_MAP_MASK 0x0003fe00 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_UNTAG_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_UNTAG_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ARLA_VTBL_ENTRY :: FWD_MAP [08:00] */ |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MAP_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLA_VTBL_ENTRY_FWD_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLACCS_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLACCS_REG_SPARE0 :: ARLACCS_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ARLACCS_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ARLACCS_REG_SPARE1 :: ARLACCS_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_CTRL - Memory Debug Control Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_MEM_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_MEM_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: MEM_CTRL :: MEM_TYPE [07:06] */ |
| #define BCHP_SWITCH_CORE_MEM_CTRL_MEM_TYPE_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_MEM_CTRL_MEM_TYPE_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MEM_CTRL_MEM_TYPE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_CTRL :: SWITCH_RESV_1 [05:04] */ |
| #define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_1_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_CTRL :: SWITCH_RESV_0 [03:00] */ |
| #define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_0_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_CTRL_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_ADDR - Memory Debug Address Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_ADDR :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MEM_ADDR_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MEM_ADDR_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MEM_ADDR :: MEM_STDN [15:15] */ |
| #define BCHP_SWITCH_CORE_MEM_ADDR_MEM_STDN_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_MEM_ADDR_MEM_STDN_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MEM_ADDR_MEM_STDN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ADDR :: MEM_RW [14:14] */ |
| #define BCHP_SWITCH_CORE_MEM_ADDR_MEM_RW_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_MEM_ADDR_MEM_RW_SHIFT 14 |
| #define BCHP_SWITCH_CORE_MEM_ADDR_MEM_RW_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_ADDR :: MEM_ADR [13:00] */ |
| #define BCHP_SWITCH_CORE_MEM_ADDR_MEM_ADR_MASK 0x00003fff |
| #define BCHP_SWITCH_CORE_MEM_ADDR_MEM_ADR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_ADDR_MEM_ADR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_DEBUG_DATA_0_0 - Memory Debug Data 0_0 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_DEBUG_DATA_0_0 :: MEM_DAT [63:00] */ |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0_MEM_DAT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0_MEM_DAT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_0_MEM_DAT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MEM_DEBUG_DATA_0_1 - Memory Debug Data 0_1 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_DEBUG_DATA_0_1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MEM_DEBUG_DATA_0_1 :: MEM_DAT [15:00] */ |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_MEM_DAT_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_MEM_DAT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_0_1_MEM_DAT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_DEBUG_DATA_1_0 - Memory Debug Data 1_0 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_DEBUG_DATA_1_0 :: MEM_DAT [63:00] */ |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0_MEM_DAT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0_MEM_DAT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_0_MEM_DAT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MEM_DEBUG_DATA_1_1 - Memory Debug Data 1_1 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_DEBUG_DATA_1_1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MEM_DEBUG_DATA_1_1 :: MEM_DAT [15:00] */ |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_MEM_DAT_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_MEM_DAT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_DEBUG_DATA_1_1_MEM_DAT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_FRM_ADDR - Frame Memory Address Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_FRM_ADDR :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_ADDR_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MEM_FRM_ADDR_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MEM_FRM_ADDR :: MEM_STDN [15:15] */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_STDN_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_STDN_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_STDN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_FRM_ADDR :: MEM_RW [14:14] */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_RW_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_RW_SHIFT 14 |
| #define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_RW_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_FRM_ADDR :: MEM_ADR [13:00] */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_ADR_MASK 0x00003fff |
| #define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_ADR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_FRM_ADDR_MEM_ADR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_FRM_DATA0 - Frame Memory Data 1st Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_FRM_DATA0 :: MEM_DATA [63:00] */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA0_MEM_DATA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA0_MEM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA0_MEM_DATA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MEM_FRM_DATA1 - Frame Memory Data 2st Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_FRM_DATA1 :: MEM_DATA [63:00] */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA1_MEM_DATA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA1_MEM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA1_MEM_DATA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MEM_FRM_DATA2 - Frame Memory Data 3st Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_FRM_DATA2 :: MEM_DATA [63:00] */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA2_MEM_DATA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA2_MEM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA2_MEM_DATA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MEM_FRM_DATA3 - Frame Memory Data 4th Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_FRM_DATA3 :: MEM_DATA [63:00] */ |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA3_MEM_DATA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA3_MEM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_FRM_DATA3_MEM_DATA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MEM_BTM_DATA0 - Buffer Tag Memory Register 0Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_BTM_DATA0 :: MEM_DATA [63:00] */ |
| #define BCHP_SWITCH_CORE_MEM_BTM_DATA0_MEM_DATA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MEM_BTM_DATA0_MEM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_BTM_DATA0_MEM_DATA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MEM_BTM_DATA1 - Buffer Tag Memory Register 1Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_BTM_DATA1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MEM_BTM_DATA1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MEM_BTM_DATA1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MEM_BTM_DATA1 :: MEM_DATA [15:00] */ |
| #define BCHP_SWITCH_CORE_MEM_BTM_DATA1_MEM_DATA_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_MEM_BTM_DATA1_MEM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_BTM_DATA1_MEM_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_BFC_ADDR - Buffer Control Memory Address Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_BFC_ADDR :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MEM_BFC_ADDR_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MEM_BFC_ADDR_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MEM_BFC_ADDR :: MEM_REQ [15:15] */ |
| #define BCHP_SWITCH_CORE_MEM_BFC_ADDR_MEM_REQ_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_MEM_BFC_ADDR_MEM_REQ_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MEM_BFC_ADDR_MEM_REQ_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_BFC_ADDR :: RW_CTRL [14:14] */ |
| #define BCHP_SWITCH_CORE_MEM_BFC_ADDR_RW_CTRL_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_MEM_BFC_ADDR_RW_CTRL_SHIFT 14 |
| #define BCHP_SWITCH_CORE_MEM_BFC_ADDR_RW_CTRL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_BFC_ADDR :: BFC_ADDR [13:00] */ |
| #define BCHP_SWITCH_CORE_MEM_BFC_ADDR_BFC_ADDR_MASK 0x00003fff |
| #define BCHP_SWITCH_CORE_MEM_BFC_ADDR_BFC_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_BFC_ADDR_BFC_ADDR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_BFC_DATA - Buffer Control Memory Data Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_BFC_DATA :: BFC_DATA [63:00] */ |
| #define BCHP_SWITCH_CORE_MEM_BFC_DATA_BFC_DATA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_MEM_BFC_DATA_BFC_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_BFC_DATA_BFC_DATA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *PRS_FIFO_DEBUG_CTRL - PRS_FIFO Debug Control Register(Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PRS_FIFO_DEBUG_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: PRS_FIFO_DEBUG_CTRL :: SWITCH_RESV [07:04] */ |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_SWITCH_RESV_MASK 0x000000f0 |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_SWITCH_RESV_SHIFT 4 |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PRS_FIFO_DEBUG_CTRL :: PRS_FIFO_DBG_CTRL [03:00] */ |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PRS_FIFO_DEBUG_DATA - PRS_FIFO Debug Data Register(Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PRS_FIFO_DEBUG_DATA :: PRS_FIFO_DBG_DATA [63:00] */ |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *MEM_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_REG_SPARE0 :: MEM_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_MEM_REG_SPARE0_MEM_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_MEM_REG_SPARE0_MEM_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_REG_SPARE0_MEM_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_REG_SPARE1 :: MEM_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_MEM_REG_SPARE1_MEM_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_MEM_REG_SPARE1_MEM_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_REG_SPARE1_MEM_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_MISC_CTRL - Memory Misc Control Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_MISC_CTRL :: SWITCH_RESV [31:05] */ |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_SWITCH_RESV_MASK 0xffffffe0 |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_SWITCH_RESV_SHIFT 5 |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_MISC_CTRL :: TXQ_DCM [04:04] */ |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_TXQ_DCM_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_TXQ_DCM_SHIFT 4 |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_TXQ_DCM_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_MISC_CTRL :: PB_DCM [03:03] */ |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_PB_DCM_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_PB_DCM_SHIFT 3 |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_PB_DCM_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_MISC_CTRL :: BT_DCM [02:02] */ |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_BT_DCM_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_BT_DCM_SHIFT 2 |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_BT_DCM_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_MISC_CTRL :: ARL_DCM [01:01] */ |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_ARL_DCM_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_ARL_DCM_SHIFT 1 |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_ARL_DCM_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_MISC_CTRL :: CK_AON [00:00] */ |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_CK_AON_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_CK_AON_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_MISC_CTRL_CK_AON_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *MEM_TEST_CTRL0 - Memory Test Control 0 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_TEST_CTRL0 :: SWITCH_RESV_1 [31:30] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_1_MASK 0xc0000000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL0 :: VL_TM [29:20] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_VL_TM_MASK 0x3ff00000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_VL_TM_SHIFT 20 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_VL_TM_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL0 :: SWITCH_RESV_0 [19:17] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_0_MASK 0x000e0000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_0_SHIFT 17 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL0 :: ARL_TM [16:00] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_ARL_TM_MASK 0x0001ffff |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_ARL_TM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL0_ARL_TM_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_TEST_CTRL1 - Memory Test Control 1 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_TEST_CTRL1 :: SWITCH_RESV_1 [31:30] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_1_MASK 0xc0000000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL1 :: ACTRAT_TM [29:20] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_ACTRAT_TM_MASK 0x3ff00000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_ACTRAT_TM_SHIFT 20 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_ACTRAT_TM_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL1 :: SWITCH_RESV_0 [19:17] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_0_MASK 0x000e0000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_0_SHIFT 17 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL1 :: BT_TM [16:00] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_BT_TM_MASK 0x0001ffff |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_BT_TM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL1_BT_TM_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_TEST_CTRL2 - Memory Test Control 2 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_TEST_CTRL2 :: SWITCH_RESV_1 [31:30] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_1_MASK 0xc0000000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL2 :: STS_TM [29:20] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_STS_TM_MASK 0x3ff00000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_STS_TM_SHIFT 20 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_STS_TM_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL2 :: SWITCH_RESV_0 [19:17] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_0_MASK 0x000e0000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_0_SHIFT 17 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL2 :: PB_TM [16:00] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_PB_TM_MASK 0x0001ffff |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_PB_TM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL2_PB_TM_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_TEST_CTRL3 - Memory Test Control 3 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_TEST_CTRL3 :: SWITCH_RESV_1 [31:30] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_1_MASK 0xc0000000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL3 :: EVT_TM [29:20] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_EVT_TM_MASK 0x3ff00000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_EVT_TM_SHIFT 20 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_EVT_TM_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL3 :: SWITCH_RESV_0 [19:17] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_0_MASK 0x000e0000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_0_SHIFT 17 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL3 :: TXQ_TM [16:00] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_TXQ_TM_MASK 0x0001ffff |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_TXQ_TM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL3_TXQ_TM_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_TEST_CTRL4 - Memory Test Control 4 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_TEST_CTRL4 :: SWITCH_RESV_1 [31:26] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_1_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_1_SHIFT 26 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL4 :: TCAM_CHKSUM_TM [25:16] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_CHKSUM_TM_MASK 0x03ff0000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_CHKSUM_TM_SHIFT 16 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_CHKSUM_TM_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL4 :: SWITCH_RESV_0 [15:14] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_0_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_0_SHIFT 14 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL4 :: TCAM_TM [13:00] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_TM_MASK 0x00003fff |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_TM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL4_TCAM_TM_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_TEST_CTRL5 - Memory Test Control 5 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_TEST_CTRL5 :: SWITCH_RESV [31:06] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_SWITCH_RESV_MASK 0xffffffc0 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_SWITCH_RESV_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_TEST_CTRL5 :: MIB_TM [05:00] */ |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_MIB_TM_MASK 0x0000003f |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_MIB_TM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_TEST_CTRL5_MIB_TM_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MEM_PSM_VDD_CTRL - Memory PSM_VDD Pin Control registerNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: SWITCH_RESV [31:22] */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_SWITCH_RESV_MASK 0xffc00000 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_SWITCH_RESV_SHIFT 22 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: STS_PSM_VDD [21:20] */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_STS_PSM_VDD_MASK 0x00300000 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_STS_PSM_VDD_SHIFT 20 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_STS_PSM_VDD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: ACTRAT_PSM_VDD [19:18] */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_ACTRAT_PSM_VDD_MASK 0x000c0000 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_ACTRAT_PSM_VDD_SHIFT 18 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_ACTRAT_PSM_VDD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: IMP_TXQ_PSM_VDD [17:16] */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_IMP_TXQ_PSM_VDD_MASK 0x00030000 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_IMP_TXQ_PSM_VDD_SHIFT 16 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_IMP_TXQ_PSM_VDD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P7_TXQ_PSM_VDD [15:14] */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P7_TXQ_PSM_VDD_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P7_TXQ_PSM_VDD_SHIFT 14 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P7_TXQ_PSM_VDD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P6_TXQ_PSM_VDD [13:12] */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P6_TXQ_PSM_VDD_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P6_TXQ_PSM_VDD_SHIFT 12 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P6_TXQ_PSM_VDD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P5_TXQ_PSM_VDD [11:10] */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P5_TXQ_PSM_VDD_MASK 0x00000c00 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P5_TXQ_PSM_VDD_SHIFT 10 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P5_TXQ_PSM_VDD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P4_TXQ_PSM_VDD [09:08] */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P4_TXQ_PSM_VDD_MASK 0x00000300 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P4_TXQ_PSM_VDD_SHIFT 8 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P4_TXQ_PSM_VDD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P3_TXQ_PSM_VDD [07:06] */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P3_TXQ_PSM_VDD_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P3_TXQ_PSM_VDD_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P3_TXQ_PSM_VDD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P2_TXQ_PSM_VDD [05:04] */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P2_TXQ_PSM_VDD_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P2_TXQ_PSM_VDD_SHIFT 4 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P2_TXQ_PSM_VDD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P1_TXQ_PSM_VDD [03:02] */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P1_TXQ_PSM_VDD_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P1_TXQ_PSM_VDD_SHIFT 2 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P1_TXQ_PSM_VDD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MEM_PSM_VDD_CTRL :: P0_TXQ_PSM_VDD [01:00] */ |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P0_TXQ_PSM_VDD_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P0_TXQ_PSM_VDD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MEM_PSM_VDD_CTRL_P0_TXQ_PSM_VDD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT0_DEBUG - PORT0 DEBUGNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT0_DEBUG :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_PORT0_DEBUG_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_PORT0_DEBUG_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT0_DEBUG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT1_DEBUG - PORT1 DEBUGNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT1_DEBUG :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_PORT1_DEBUG_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_PORT1_DEBUG_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT1_DEBUG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT2_DEBUG - PORT2 DEBUGNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT2_DEBUG :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_PORT2_DEBUG_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_PORT2_DEBUG_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT2_DEBUG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT3_DEBUG - PORT3 DEBUGNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT3_DEBUG :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_PORT3_DEBUG_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_PORT3_DEBUG_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT3_DEBUG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT4_DEBUG - PORT4 DEBUGNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT4_DEBUG :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_PORT4_DEBUG_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_PORT4_DEBUG_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT4_DEBUG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT5_DEBUG - PORT5 DEBUGNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT5_DEBUG :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_PORT5_DEBUG_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_PORT5_DEBUG_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT5_DEBUG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT6_DEBUG - PORT6 DEBUGNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT6_DEBUG :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_PORT6_DEBUG_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_PORT6_DEBUG_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT6_DEBUG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT7_DEBUG - PORT7 DEBUGNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT7_DEBUG :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_PORT7_DEBUG_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_PORT7_DEBUG_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT7_DEBUG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT8_DEBUG - PORT8 DEBUGNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT8_DEBUG :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_PORT8_DEBUG_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_PORT8_DEBUG_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT8_DEBUG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_DIAG_CTRL - Flowcon Diagnosis Control Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_DIAG_CTRL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_DIAG_CTRL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_DIAG_CTRL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_DIAG_CTRL :: SWITCH_RESV [15:04] */ |
| #define BCHP_SWITCH_CORE_FC_DIAG_CTRL_SWITCH_RESV_MASK 0x0000fff0 |
| #define BCHP_SWITCH_CORE_FC_DIAG_CTRL_SWITCH_RESV_SHIFT 4 |
| #define BCHP_SWITCH_CORE_FC_DIAG_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_DIAG_CTRL :: DIAG_FLOWCON_PORT [03:00] */ |
| #define BCHP_SWITCH_CORE_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_CTRL_MODE - Flow Control Mode Selection Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_CTRL_MODE :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_FC_CTRL_MODE_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_FC_CTRL_MODE_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: FC_CTRL_MODE :: SWITCH_RESV [07:01] */ |
| #define BCHP_SWITCH_CORE_FC_CTRL_MODE_SWITCH_RESV_MASK 0x000000fe |
| #define BCHP_SWITCH_CORE_FC_CTRL_MODE_SWITCH_RESV_SHIFT 1 |
| #define BCHP_SWITCH_CORE_FC_CTRL_MODE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_CTRL_MODE :: FC_MODE [00:00] */ |
| #define BCHP_SWITCH_CORE_FC_CTRL_MODE_FC_MODE_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_FC_CTRL_MODE_FC_MODE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_CTRL_MODE_FC_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_CTRL_PORT - Flow Control Port Selection Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_CTRL_PORT :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_FC_CTRL_PORT_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_FC_CTRL_PORT_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: FC_CTRL_PORT :: SWITCH_RESV [07:04] */ |
| #define BCHP_SWITCH_CORE_FC_CTRL_PORT_SWITCH_RESV_MASK 0x000000f0 |
| #define BCHP_SWITCH_CORE_FC_CTRL_PORT_SWITCH_RESV_SHIFT 4 |
| #define BCHP_SWITCH_CORE_FC_CTRL_PORT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_CTRL_PORT :: FC_PORT_SEL [03:00] */ |
| #define BCHP_SWITCH_CORE_FC_CTRL_PORT_FC_PORT_SEL_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_FC_CTRL_PORT_FC_PORT_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_CTRL_PORT_FC_PORT_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_OOB_PAUSE_EN - OOB Pause Signal Enable Register (Release2Customer)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_OOB_PAUSE_EN :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_OOB_PAUSE_EN :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_OOB_PAUSE_EN :: OOB_PAUSE_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PAUSE_TIME_MAX - MAX Quantum Pause Time Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PAUSE_TIME_MAX :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PAUSE_TIME_MAX :: PAUSE_TIME_MAX [15:00] */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_PAUSE_TIME_MAX_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_PAUSE_TIME_MAX_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_MAX_PAUSE_TIME_MAX_DEFAULT 0x00008000 |
| |
| /*************************************************************************** |
| *PAUSE_TIME_MIN - MIN Quantum Pause Time Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PAUSE_TIME_MIN :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PAUSE_TIME_MIN :: PAUSE_TIME_MIN [15:00] */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_PAUSE_TIME_MIN_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_PAUSE_TIME_MIN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_MIN_PAUSE_TIME_MIN_DEFAULT 0x00000400 |
| |
| /*************************************************************************** |
| *PAUSE_TIME_RESET_THD - Quantum Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PAUSE_TIME_RESET_THD :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PAUSE_TIME_RESET_THD :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PAUSE_TIME_RESET_THD :: PAUSE_TIME_RESET_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_DEFAULT 0x00000100 |
| |
| /*************************************************************************** |
| *PAUSE_TIME_UPDATE_PERIOD - Quantum Pause Update Period Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PAUSE_TIME_UPDATE_PERIOD :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PAUSE_TIME_UPDATE_PERIOD :: PAUSE_TIME_UPDATE_PERIOD [15:00] */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_DEFAULT 0x00001000 |
| |
| /*************************************************************************** |
| *PAUSE_TIME_DEFAULT - Default Quantum Pause Time Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PAUSE_TIME_DEFAULT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PAUSE_TIME_DEFAULT :: PAUSE_TIME_DEFAULT [15:00] */ |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_DEFAULT 0x00001000 |
| |
| /*************************************************************************** |
| *FC_MCAST_DROP_CTRL - Multicast Drop Control Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_MCAST_DROP_CTRL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_MCAST_DROP_CTRL :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_MCAST_DROP_CTRL :: MCAST_PARTIAL_DROP_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *FC_PAUSE_DROP_CTRL - Pause/Drop Control Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: QUEUE_BASED_PAUSE_EN [12:12] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_SHIFT 12 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP0_TOTAL_PAUSE_EN [11:11] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_MASK 0x00000800 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP0_TXQ_PAUSE_EN [10:10] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_MASK 0x00000400 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_SHIFT 10 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP1_TOTAL_PAUSE_EN [09:09] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_MASK 0x00000200 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_SHIFT 9 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_IMP1_TXQ_PAUSE_EN [08:08] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_MASK 0x00000100 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_SHIFT 8 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TOTAL_PAUSE_EN [07:07] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_SHIFT 7 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TXQ_PAUSE_EN [06:06] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_SHIFT 6 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: RX_DROP_EN [05:05] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_DROP_EN_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_DROP_EN_SHIFT 5 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TOTAL_DROP_EN [04:04] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_SHIFT 4 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_TXQ_DROP_EN [03:03] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_SHIFT 3 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: RX_BASED_CTRL_EN [02:02] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_SHIFT 2 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_QUANTUM_CTRL_EN [01:01] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_SHIFT 1 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PAUSE_DROP_CTRL :: TX_BASED_CTRL_EN [00:00] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *FC_TXQ_THD_PAUSE_OFF - TXQ Pause Off Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TXQ_THD_PAUSE_OFF :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TXQ_THD_PAUSE_OFF :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_TXQ_THD_PAUSE_OFF :: TXQ_THD_PAUSE_OFF [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_DEFAULT 0x00000008 |
| |
| /*************************************************************************** |
| *FC_RX_RUNOFF - RX-Based Run-Off Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_RX_RUNOFF :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_RX_RUNOFF_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_RX_RUNOFF_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_RX_RUNOFF :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_RX_RUNOFF_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_RX_RUNOFF_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_RX_RUNOFF_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_RX_RUNOFF :: RX_RUN_OFF_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_RX_RUNOFF_RX_RUN_OFF_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_RX_RUNOFF_RX_RUN_OFF_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_RX_RUNOFF_RX_RUN_OFF_THD_DEFAULT 0x00000013 |
| |
| /*************************************************************************** |
| *FC_RX_RSV_THD - RX-Based Reserved Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_RX_RSV_THD :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_RX_RSV_THD_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_RX_RSV_THD_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_RX_RSV_THD :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_RX_RSV_THD_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_RX_RSV_THD_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_RX_RSV_THD_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_RX_RSV_THD :: RX_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_RX_RSV_THD_RX_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_RX_RSV_THD_RX_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_RX_RSV_THD_RX_RSV_THD_DEFAULT 0x0000000a |
| |
| /*************************************************************************** |
| *FC_RX_HYST_THD - RX-Based Hysteresis Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_RX_HYST_THD :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_RX_HYST_THD_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_RX_HYST_THD_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_RX_HYST_THD :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_RX_HYST_THD_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_RX_HYST_THD_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_RX_HYST_THD_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_RX_HYST_THD :: RX_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_RX_HYST_THD_RX_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_RX_HYST_THD_RX_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_RX_HYST_THD_RX_HYST_THD_DEFAULT 0x00000014 |
| |
| /*************************************************************************** |
| *FC_RX_MAX_PTR - RX-Based Maximum Buffer Remap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_RX_MAX_PTR :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_RX_MAX_PTR :: EN_REMAP [15:15] */ |
| #define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_EN_REMAP_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_EN_REMAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_EN_REMAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_RX_MAX_PTR :: SWITCH_RESV [14:11] */ |
| #define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_SWITCH_RESV_MASK 0x00007800 |
| #define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_RX_MAX_PTR :: MAXBUF_REMAP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_DEFAULT 0x000001ea |
| |
| /*************************************************************************** |
| *FC_SPARE_ZERO_REG - Flow Control Spare Zero Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_SPARE_ZERO_REG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_SPARE_ZERO_REG :: SPARE_ZERO [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_SPARE_ZERO_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_SPARE_ZERO_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_SPARE_ZERO_REG_SPARE_ZERO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_SPARE_ONE_REG - Flow Control Spare One Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_SPARE_ONE_REG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_SPARE_ONE_REG :: SPARE_ONE [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_SPARE_ONE_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_SPARE_ONE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_SPARE_ONE_REG_SPARE_ONE_DEFAULT 0x0000ffff |
| |
| /*************************************************************************** |
| *FC_MON_TX_Q0 - Monitored TXQ 0 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_MON_TX_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q0 :: MONITORED_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q0_MONITORED_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q0_MONITORED_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q0_MONITORED_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_MON_TX_Q1 - Monitored TXQ 1 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_MON_TX_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q1 :: MONITORED_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q1_MONITORED_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q1_MONITORED_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q1_MONITORED_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_MON_TX_Q2 - Monitored TXQ 2 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_MON_TX_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q2 :: MONITORED_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q2_MONITORED_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q2_MONITORED_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q2_MONITORED_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_MON_TX_Q3 - Monitored TXQ 3 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_MON_TX_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q3 :: MONITORED_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q3_MONITORED_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q3_MONITORED_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q3_MONITORED_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_MON_TX_Q4 - Monitored TXQ 4 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_MON_TX_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q4 :: MONITORED_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q4_MONITORED_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q4_MONITORED_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q4_MONITORED_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_MON_TX_Q5 - Monitored TXQ 5 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_MON_TX_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q5 :: MONITORED_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q5_MONITORED_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q5_MONITORED_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q5_MONITORED_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_MON_TX_Q6 - Monitored TXQ 6 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_MON_TX_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q6 :: MONITORED_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q6_MONITORED_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q6_MONITORED_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q6_MONITORED_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_MON_TX_Q7 - Monitored TXQ 7 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_MON_TX_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_MON_TX_Q7 :: MONITORED_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q7_MONITORED_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q7_MONITORED_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_MON_TX_Q7_MONITORED_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_PEAK_TX_Q0 - Peak TXQ 0 Counter Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_PEAK_TX_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q0 :: PEAK_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_PEAK_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_PEAK_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q0_PEAK_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_PEAK_TX_Q1 - Peak TXQ 1 Counter Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_PEAK_TX_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q1 :: PEAK_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_PEAK_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_PEAK_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q1_PEAK_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_PEAK_TX_Q2 - Peak TXQ 2 Counter Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_PEAK_TX_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q2 :: PEAK_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_PEAK_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_PEAK_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q2_PEAK_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_PEAK_TX_Q3 - Peak TXQ 3 Counter Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_PEAK_TX_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q3 :: PEAK_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_PEAK_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_PEAK_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q3_PEAK_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_PEAK_TX_Q4 - Peak TXQ 4 Counter Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_PEAK_TX_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q4 :: PEAK_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_PEAK_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_PEAK_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q4_PEAK_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_PEAK_TX_Q5 - Peak TXQ 5 Counter Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_PEAK_TX_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q5 :: PEAK_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_PEAK_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_PEAK_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q5_PEAK_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_PEAK_TX_Q6 - Peak TXQ 6 Counter Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_PEAK_TX_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q6 :: PEAK_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_PEAK_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_PEAK_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q6_PEAK_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_PEAK_TX_Q7 - Peak TXQ 7 Counter Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_PEAK_TX_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PEAK_TX_Q7 :: PEAK_TXQ_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_PEAK_TXQ_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_PEAK_TXQ_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TX_Q7_PEAK_TXQ_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_PEAK_TOTAL_USED - Peak Total Used Count Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_PEAK_TOTAL_USED :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_PEAK_TOTAL_USED :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PEAK_TOTAL_USED :: PEAK_TOTAL_USE_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TOTAL_USED - Total Used Count Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TOTAL_USED :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_USED_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_USED_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TOTAL_USED :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_USED_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_USED_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_USED_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_TOTAL_USED :: TOTAL_USE_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_USED_TOTAL_USE_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_TOTAL_USED_TOTAL_USE_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_USED_TOTAL_USE_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_PEAK_RX_CNT - Peak RX Counter Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_PEAK_RX_CNT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_PEAK_RX_CNT :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PEAK_RX_CNT :: PEAK_RXBUF_CNT [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_LINK_PORTMAP - PHY Link Information Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LINK_PORTMAP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LINK_PORTMAP :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LINK_PORTMAP :: LINK_PORTMAP [08:00] */ |
| #define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_LINK_PORTMAP_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_LINK_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LINK_PORTMAP_LINK_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_GIGA_PORTMAP - Giga Speed Information Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_GIGA_PORTMAP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_GIGA_PORTMAP :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_GIGA_PORTMAP :: GIGA_PORTMAP [08:00] */ |
| #define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_GIGA_PORTMAP_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_GIGA_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_GIGA_PORTMAP_GIGA_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_CONG_PORTMAP_P0 - Port 0 Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P0 :: CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P0_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P0_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P0_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_CONG_PORTMAP_P1 - Port 1 Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P1 :: CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P1_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P1_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P1_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_CONG_PORTMAP_P2 - Port 2 Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P2 :: CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P2_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P2_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P2_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_CONG_PORTMAP_P3 - Port 3 Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P3 :: CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P3_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P3_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P3_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_CONG_PORTMAP_P4 - Port 4 Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P4 :: CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P4_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P4_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P4_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_CONG_PORTMAP_P5 - Port 5 Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P5 :: CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P5_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P5_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P5_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_CONG_PORTMAP_P7 - Port 7 Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P7 :: CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_CONG_PORTMAP_P8 - Port 8 Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P8 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_CONG_PORTMAP_P8 :: CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_PAUSE_HIS - Pause History Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_PAUSE_HIS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_HIS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_HIS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_PAUSE_HIS :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_HIS_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_HIS_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_HIS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_PAUSE_HIS :: PAUSE_HIS [08:00] */ |
| #define BCHP_SWITCH_CORE_FC_PAUSE_HIS_PAUSE_HIS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_FC_PAUSE_HIS_PAUSE_HIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_PAUSE_HIS_PAUSE_HIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TX_QUANTUM_PAUSE_HIS - TX Quantum Pause History Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TX_QUANTUM_PAUSE_HIS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TX_QUANTUM_PAUSE_HIS :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_TX_QUANTUM_PAUSE_HIS :: TX_QUANTUM_PAUSE_HIS [08:00] */ |
| #define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_RX_PAUSE_HIS - RX Based Pause History Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_RX_PAUSE_HIS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_RX_PAUSE_HIS :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_RX_PAUSE_HIS :: RX_PAUSE_HIS [08:00] */ |
| #define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_RXBUF_ERR_HIS - RX Buffer Error History Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_RXBUF_ERR_HIS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_RXBUF_ERR_HIS :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_RXBUF_ERR_HIS :: RXBUF_ERR_HIS [08:00] */ |
| #define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TXQ_CONG_PORTMAP_P0 - Port 0 TXQ Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P0 :: TXQ_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0_TXQ_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TXQ_CONG_PORTMAP_P1 - Port 1 TXQ Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P1 :: TXQ_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1_TXQ_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TXQ_CONG_PORTMAP_P2 - Port 2 TXQ Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P2 :: TXQ_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2_TXQ_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TXQ_CONG_PORTMAP_P3 - Port 3 TXQ Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P3 :: TXQ_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3_TXQ_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TXQ_CONG_PORTMAP_P4 - Port 4 TXQ Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P4 :: TXQ_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4_TXQ_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TXQ_CONG_PORTMAP_P5 - Port 5 TXQ Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P5 :: TXQ_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5_TXQ_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TXQ_CONG_PORTMAP_P7 - Port 7 TXQ Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P7 :: TXQ_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TXQ_CONG_PORTMAP_P8 - Port 8 TXQ Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P8 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TXQ_CONG_PORTMAP_P8 :: TXQ_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TOTAL_CONG_PORTMAP_P0 - Port 0 Total Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P0 :: TOTAL_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0_TOTAL_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TOTAL_CONG_PORTMAP_P1 - Port 1 Total Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P1 :: TOTAL_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1_TOTAL_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TOTAL_CONG_PORTMAP_P2 - Port 2 Total Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P2 :: TOTAL_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2_TOTAL_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TOTAL_CONG_PORTMAP_P3 - Port 3 Total Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P3 :: TOTAL_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3_TOTAL_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TOTAL_CONG_PORTMAP_P4 - Port 4 Total Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P4 :: TOTAL_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4_TOTAL_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TOTAL_CONG_PORTMAP_P5 - Port 5 Total Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P5 :: TOTAL_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5_TOTAL_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TOTAL_CONG_PORTMAP_P7 - Port 7 Total Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P7 :: TOTAL_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_TOTAL_CONG_PORTMAP_P8 - Port 8 Total Congested PortMap Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P8 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_TOTAL_CONG_PORTMAP_P8 :: TOTAL_CONGEST_PORTMAP [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_RSV_Q0 - LAN Port Queue 0 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q0 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_RSV_Q1 - LAN Port Queue 1 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q1 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_RSV_Q2 - LAN Port Queue 2 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q2 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_RSV_Q3 - LAN Port Queue 3 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q3 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_RSV_Q4 - LAN Port Queue 4 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q4 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_RSV_Q5 - LAN Port Queue 5 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q5 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_RSV_Q6 - LAN Port Queue 6 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q6 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_RSV_Q7 - LAN Port Queue 7 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_RSV_Q7 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_HYST_Q0 - LAN Port Queue 0 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q0 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD_DEFAULT 0x0000004b |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_HYST_Q1 - LAN Port Queue 1 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q1 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD_DEFAULT 0x0000004f |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_HYST_Q2 - LAN Port Queue 2 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q2 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD_DEFAULT 0x00000053 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_HYST_Q3 - LAN Port Queue 3 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q3 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD_DEFAULT 0x00000057 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_HYST_Q4 - LAN Port Queue 4 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q4 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD_DEFAULT 0x0000005b |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_HYST_Q5 - LAN Port Queue 5 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q5 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD_DEFAULT 0x0000005f |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_HYST_Q6 - LAN Port Queue 6 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q6 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD_DEFAULT 0x00000063 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_HYST_Q7 - LAN Port Queue 7 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_HYST_Q7 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD_DEFAULT 0x00000067 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_PAUSE_Q0 - LAN Port Queue 0 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q0 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_DEFAULT 0x00000097 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_PAUSE_Q1 - LAN Port Queue 1 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q1 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_DEFAULT 0x0000009f |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_PAUSE_Q2 - LAN Port Queue 2 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q2 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_DEFAULT 0x000000a7 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_PAUSE_Q3 - LAN Port Queue 3 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q3 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_DEFAULT 0x000000af |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_PAUSE_Q4 - LAN Port Queue 4 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q4 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_DEFAULT 0x000000b7 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_PAUSE_Q5 - LAN Port Queue 5 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q5 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_DEFAULT 0x000000bf |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_PAUSE_Q6 - LAN Port Queue 6 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q6 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_DEFAULT 0x000000c7 |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_PAUSE_Q7 - LAN Port Queue 7 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_PAUSE_Q7 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_DEFAULT 0x000000cf |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_DROP_Q0 - LAN Port Queue 0 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q0 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD_DEFAULT 0x000005cf |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_DROP_Q1 - LAN Port Queue 1 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q1 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD_DEFAULT 0x000005cf |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_DROP_Q2 - LAN Port Queue 2 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q2 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD_DEFAULT 0x000005cf |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_DROP_Q3 - LAN Port Queue 3 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q3 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD_DEFAULT 0x000005cf |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_DROP_Q4 - LAN Port Queue 4 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q4 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD_DEFAULT 0x000005cf |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_DROP_Q5 - LAN Port Queue 5 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q5 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD_DEFAULT 0x000005cf |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_DROP_Q6 - LAN Port Queue 6 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q6 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_LAN_TXQ_THD_DROP_Q7 - LAN Port Queue 7 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TXQ_THD_DROP_Q7 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_HYST_Q0 - LAN Port Queue 0 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q0 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_DEFAULT 0x0000038f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_HYST_Q1 - LAN Port Queue 1 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q1 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_DEFAULT 0x0000038f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_HYST_Q2 - LAN Port Queue 2 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q2 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_DEFAULT 0x0000038f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_HYST_Q3 - LAN Port Queue 3 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q3 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_DEFAULT 0x0000038f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_HYST_Q4 - LAN Port Queue 4 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q4 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_DEFAULT 0x0000038f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_HYST_Q5 - LAN Port Queue 5 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q5 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_DEFAULT 0x0000038f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_HYST_Q6 - LAN Port Queue 6 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q6 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_DEFAULT 0x0000038f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_HYST_Q7 - LAN Port Queue 7 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_HYST_Q7 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_DEFAULT 0x0000038f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_PAUSE_Q0 - LAN Port Queue 0 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q0 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_DEFAULT 0x0000040f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_PAUSE_Q1 - LAN Port Queue 1 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q1 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_DEFAULT 0x00000417 |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_PAUSE_Q2 - LAN Port Queue 2 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q2 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_DEFAULT 0x0000041f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_PAUSE_Q3 - LAN Port Queue 3 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q3 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_DEFAULT 0x00000427 |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_PAUSE_Q4 - LAN Port Queue 4 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q4 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_DEFAULT 0x0000042f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_PAUSE_Q5 - LAN Port Queue 5 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q5 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_DEFAULT 0x00000437 |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_PAUSE_Q6 - LAN Port Queue 6 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q6 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_DEFAULT 0x0000043f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_PAUSE_Q7 - LAN Port Queue 7 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_PAUSE_Q7 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_DEFAULT 0x00000447 |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_DROP_Q0 - LAN Port Queue 0 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q0 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_DEFAULT 0x0000058f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_DROP_Q1 - LAN Port Queue 1 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q1 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_DEFAULT 0x00000597 |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_DROP_Q2 - LAN Port Queue 2 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q2 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_DEFAULT 0x0000059f |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_DROP_Q3 - LAN Port Queue 3 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q3 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_DEFAULT 0x000005a7 |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_DROP_Q4 - LAN Port Queue 4 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q4 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_DEFAULT 0x000005af |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_DROP_Q5 - LAN Port Queue 5 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q5 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_DEFAULT 0x000005b7 |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_DROP_Q6 - LAN Port Queue 6 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q6 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_DEFAULT 0x000005bf |
| |
| /*************************************************************************** |
| *FC_LAN_TOTAL_THD_DROP_Q7 - LAN Port Queue 7 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_LAN_TOTAL_THD_DROP_Q7 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_DEFAULT 0x000005c7 |
| |
| /*************************************************************************** |
| *P0_DEBUG_MUX - P0 DEBUG MUXNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: P0_DEBUG_MUX :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_P0_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_P0_DEBUG_MUX_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_P0_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *P1_DEBUG_MUX - P1 DEBUG MUXNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: P1_DEBUG_MUX :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_P1_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_P1_DEBUG_MUX_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_P1_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *P2_DEBUG_MUX - P2 DEBUG MUXNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: P2_DEBUG_MUX :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_P2_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_P2_DEBUG_MUX_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_P2_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *P3_DEBUG_MUX - P3 DEBUG MUXNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: P3_DEBUG_MUX :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_P3_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_P3_DEBUG_MUX_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_P3_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *P4_DEBUG_MUX - P4 DEBUG MUXNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: P4_DEBUG_MUX :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_P4_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_P4_DEBUG_MUX_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_P4_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *P5_DEBUG_MUX - P5 DEBUG MUXNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: P5_DEBUG_MUX :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_P5_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_P5_DEBUG_MUX_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_P5_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *P6_DEBUG_MUX - P6 DEBUG MUXNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: P6_DEBUG_MUX :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_P6_DEBUG_MUX_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_P6_DEBUG_MUX_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_P6_DEBUG_MUX_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DEBUG_MUX_P7 - P7 DEBUG MUXNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DEBUG_MUX_P7 :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_DEBUG_MUX_P7_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_DEBUG_MUX_P7_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DEBUG_MUX_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DEBUG_MUX_IMP - IMP DEBUG MUXNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DEBUG_MUX_IMP :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_DEBUG_MUX_IMP_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_DEBUG_MUX_IMP_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DEBUG_MUX_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_DEBUG_BUS_0 - CFP DEBUG BUS 0Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_DEBUG_BUS_0 :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_0_SWITCH_RESV_DEFAULT 0x00000021 |
| |
| /*************************************************************************** |
| *CFP_DEBUG_BUS_1 - CFP DEBUG BUS 1Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_DEBUG_BUS_1 :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_DEBUG_BUS_1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WRED_DEBUG_0 - WRED DEBUG 0Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WRED_DEBUG_0 :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_WRED_DEBUG_0_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_WRED_DEBUG_0_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WRED_DEBUG_0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WRED_DEBUG_1 - WRED DEBUG 1Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WRED_DEBUG_1 :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_WRED_DEBUG_1_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_WRED_DEBUG_1_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WRED_DEBUG_1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TOP_MISC_DEBUG_0 - TOP MISC DEBUG 0Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TOP_MISC_DEBUG_0 :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_0_SWITCH_RESV_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *TOP_MISC_DEBUG_1 - TOP MISC DEBUG 1Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TOP_MISC_DEBUG_1 :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TOP_MISC_DEBUG_1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DIAGREG_BUFCON - DIAGREG BUFCONNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DIAGREG_BUFCON :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_DIAGREG_BUFCON_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_DIAGREG_BUFCON_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DIAGREG_BUFCON_SWITCH_RESV_DEFAULT 0x0000fffc |
| |
| /*************************************************************************** |
| *TESTBUS_P1588 - TESTBUS P1588Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TESTBUS_P1588 :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_TESTBUS_P1588_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TESTBUS_P1588_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TESTBUS_P1588_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FLOWCON_DEBUG_BUS - FLOWCON DEBUG BUSNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FLOWCON_DEBUG_BUS :: SWITCH_RESV [31:00] */ |
| #define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS_SWITCH_RESV_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FLOWCON_DEBUG_BUS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_RSV_Q0 - IMP0 Port(Port 8) Queue 0 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q0 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_RSV_Q1 - IMP0 Port(Port 8) Queue 1 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q1 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_RSV_Q2 - IMP0 Port(Port 8) Queue 2 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q2 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_RSV_Q3 - IMP0 Port(Port 8) Queue 3 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q3 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_RSV_Q4 - IMP0 Port(Port 8) Queue 4 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q4 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_RSV_Q5 - IMP0 Port(Port 8) Queue 5 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q5 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_RSV_Q6 - IMP0 Port(Port 8) Queue 6 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q6 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_RSV_Q7 - IMP0 Port(Port 8) Queue 7 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_RSV_Q7 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_HYST_Q0 - IMP0 Port(Port 8) Queue 0 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q0 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD_DEFAULT 0x00000063 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_HYST_Q1 - IMP0 Port(Port 8) Queue 1 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q1 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD_DEFAULT 0x00000067 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_HYST_Q2 - IMP0 Port(Port 8) Queue 2 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q2 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD_DEFAULT 0x0000006b |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_HYST_Q3 - IMP0 Port(Port 8) Queue 3 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q3 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD_DEFAULT 0x0000006f |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_HYST_Q4 - IMP0 Port(Port 8) Queue 4 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q4 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD_DEFAULT 0x00000073 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_HYST_Q5 - IMP0 Port(Port 8) Queue 5 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q5 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD_DEFAULT 0x00000077 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_HYST_Q6 - IMP0 Port(Port 8) Queue 6 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q6 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD_DEFAULT 0x0000007b |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_HYST_Q7 - IMP0 Port(Port 8) Queue 7 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_HYST_Q7 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD_DEFAULT 0x0000007f |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_PAUSE_Q0 - IMP0 Port(Port 8) Queue 0 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q0 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_DEFAULT 0x000000c7 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_PAUSE_Q1 - IMP0 Port(Port 8) Queue 1 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q1 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_DEFAULT 0x000000cf |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_PAUSE_Q2 - IMP0 Port(Port 8) Queue 2 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q2 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_DEFAULT 0x000000d7 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_PAUSE_Q3 - IMP0 Port(Port 8) Queue 3 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q3 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_DEFAULT 0x000000df |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_PAUSE_Q4 - IMP0 Port(Port 8) Queue 4 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q4 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_DEFAULT 0x000000e7 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_PAUSE_Q5 - IMP0 Port(Port 8) Queue 5 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q5 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_DEFAULT 0x000000ef |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_PAUSE_Q6 - IMP0 Port(Port 8) Queue 6 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q6 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_DEFAULT 0x000000f7 |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_PAUSE_Q7 - IMP0 Port(Port 8) Queue 7 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_PAUSE_Q7 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_DEFAULT 0x000000ff |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_DROP_Q0 - IMP0 Port(Port 8) Queue 0 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q0 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_DROP_Q1 - IMP0 Port(Port 8) Queue 1 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q1 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_DROP_Q2 - IMP0 Port(Port 8) Queue 2 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q2 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_DROP_Q3 - IMP0 Port(Port 8) Queue 3 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q3 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_DROP_Q4 - IMP0 Port(Port 8) Queue 4 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q4 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_DROP_Q5 - IMP0 Port(Port 8) Queue 5 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q5 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_DROP_Q6 - IMP0 Port(Port 8) Queue 6 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q6 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_IMP0_TXQ_THD_DROP_Q7 - IMP0 Port(Port 8) Queue 7 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TXQ_THD_DROP_Q7 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_HYST_Q0 - IMP0 Port(Port 8) Queue 0 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q0 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_DEFAULT 0x000003bf |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_HYST_Q1 - IMP0 Port(Port 8) Queue 1 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q1 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_DEFAULT 0x000003bf |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_HYST_Q2 - IMP0 Port(Port 8) Queue 2 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q2 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_DEFAULT 0x000003bf |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_HYST_Q3 - IMP0 Port(Port 8) Queue 3 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q3 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_DEFAULT 0x000003bf |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_HYST_Q4 - IMP0 Port(Port 8) Queue 4 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q4 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_DEFAULT 0x000003bf |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_HYST_Q5 - IMP0 Port(Port 8) Queue 5 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q5 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_DEFAULT 0x000003bf |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_HYST_Q6 - IMP0 Port(Port 8) Queue 6 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q6 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_DEFAULT 0x000003bf |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_HYST_Q7 - IMP0 Port(Port 8) Queue 7 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_HYST_Q7 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_DEFAULT 0x000003bf |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_PAUSE_Q0 - IMP0 Port(Port 8) Queue 0 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q0 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_DEFAULT 0x0000043f |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_PAUSE_Q1 - IMP0 Port(Port 8) Queue 1 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q1 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_DEFAULT 0x00000447 |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_PAUSE_Q2 - IMP0 Port(Port 8) Queue 2 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q2 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_DEFAULT 0x0000044f |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_PAUSE_Q3 - IMP0 Port(Port 8) Queue 3 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q3 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_DEFAULT 0x00000457 |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_PAUSE_Q4 - IMP0 Port(Port 8) Queue 4 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q4 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_DEFAULT 0x0000045f |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_PAUSE_Q5 - IMP0 Port(Port 8) Queue 5 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q5 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_DEFAULT 0x00000467 |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_PAUSE_Q6 - IMP0 Port(Port 8) Queue 6 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q6 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_DEFAULT 0x0000046f |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_PAUSE_Q7 - IMP0 Port(Port 8) Queue 7 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_PAUSE_Q7 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_DEFAULT 0x00000477 |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_DROP_Q0 - IMP0 Port(Port 8) Queue 0 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q0 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_DEFAULT 0x000005bf |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_DROP_Q1 - IMP0 Port(Port 8) Queue 1 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q1 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_DEFAULT 0x000005c7 |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_DROP_Q2 - IMP0 Port(Port 8) Queue 2 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q2 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_DEFAULT 0x000005cf |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_DROP_Q3 - IMP0 Port(Port 8) Queue 3 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q3 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_DEFAULT 0x000005d7 |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_DROP_Q4 - IMP0 Port(Port 8) Queue 4 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q4 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_DEFAULT 0x000005df |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_DROP_Q5 - IMP0 Port(Port 8) Queue 5 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q5 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_DEFAULT 0x000005e7 |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_DROP_Q6 - IMP0 Port(Port 8) Queue 6 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q6 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_DEFAULT 0x000005ef |
| |
| /*************************************************************************** |
| *FC_IMP0_TOTAL_THD_DROP_Q7 - IMP0 Port(Port 8) Queue 7 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_IMP0_TOTAL_THD_DROP_Q7 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_DEFAULT 0x000005f7 |
| |
| /*************************************************************************** |
| *FC_IMP0_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_REG_SPARE0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_REG_SPARE0 :: FC_IMP0_REG_SPARE0 [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_IMP0_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_IMP0_REG_SPARE1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_IMP0_REG_SPARE1 :: FC_IMP0_REG_SPARE1 [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_RSV_Q0 - WAN/IMP1 Port Queue 0 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q0 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_RSV_Q1 - WAN/IMP1 Port Queue 1 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q1 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_RSV_Q2 - WAN/IMP1 Port Queue 2 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q2 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_RSV_Q3 - WAN/IMP1 Port Queue 3 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q3 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_RSV_Q4 - WAN/IMP1 Port Queue 4 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q4 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_RSV_Q5 - WAN/IMP1 Port Queue 5 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q5 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_RSV_Q6 - WAN/IMP1 Port Queue 6 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q6 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_RSV_Q7 - WAN/IMP1 Port Queue 7 Reserved Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_RSV_Q7 :: TXQ_RSV_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD_DEFAULT 0x00000018 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_HYST_Q0 - WAN/IMP1 Port Queue 0 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q0 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD_DEFAULT 0x00000067 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_HYST_Q1 - WAN/IMP1 Port Queue 1 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q1 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD_DEFAULT 0x0000006b |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_HYST_Q2 - WAN/IMP1 Port Queue 2 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q2 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD_DEFAULT 0x0000006f |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_HYST_Q3 - WAN/IMP1 Port Queue 3 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q3 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD_DEFAULT 0x00000073 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_HYST_Q4 - WAN/IMP1 Port Queue 4 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q4 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD_DEFAULT 0x00000077 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_HYST_Q5 - WAN/IMP1 Port Queue 5 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q5 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD_DEFAULT 0x0000007b |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_HYST_Q6 - WAN/IMP1 Port Queue 6 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q6 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD_DEFAULT 0x0000007f |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_HYST_Q7 - WAN/IMP1 Port Queue 7 Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_HYST_Q7 :: TXQ_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD_DEFAULT 0x00000083 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 - WAN/IMP1 Port Queue 0 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_DEFAULT 0x000000cf |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 - WAN/IMP1 Port Queue 1 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_DEFAULT 0x000000d7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 - WAN/IMP1 Port Queue 2 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_DEFAULT 0x000000df |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 - WAN/IMP1 Port Queue 3 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_DEFAULT 0x000000e7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 - WAN/IMP1 Port Queue 4 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_DEFAULT 0x000000ef |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 - WAN/IMP1 Port Queue 5 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_DEFAULT 0x000000f7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 - WAN/IMP1 Port Queue 6 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_DEFAULT 0x000000ff |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 - WAN/IMP1 Port Queue 7 Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 :: TXQ_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_DEFAULT 0x00000107 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_DROP_Q0 - WAN/IMP1 Port Queue 0 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q0 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_DROP_Q1 - WAN/IMP1 Port Queue 1 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q1 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_DROP_Q2 - WAN/IMP1 Port Queue 2 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q2 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_DROP_Q3 - WAN/IMP1 Port Queue 3 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q3 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_DROP_Q4 - WAN/IMP1 Port Queue 4 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q4 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_DROP_Q5 - WAN/IMP1 Port Queue 5 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q5 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_DROP_Q6 - WAN/IMP1 Port Queue 6 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q6 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TXQ_THD_DROP_Q7 - WAN/IMP1 Port Queue 7 DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TXQ_THD_DROP_Q7 :: TXQ_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_HYST_Q0 - WAN/IMP1 Port Queue 0 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q0 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_DEFAULT 0x000003c7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_HYST_Q1 - WAN/IMP1 Port Queue 1 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q1 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_DEFAULT 0x000003c7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_HYST_Q2 - WAN/IMP1 Port Queue 2 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q2 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_DEFAULT 0x000003c7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_HYST_Q3 - WAN/IMP1 Port Queue 3 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q3 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_DEFAULT 0x000003c7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_HYST_Q4 - WAN/IMP1 Port Queue 4 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q4 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_DEFAULT 0x000003c7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_HYST_Q5 - WAN/IMP1 Port Queue 5 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q5 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_DEFAULT 0x000003c7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_HYST_Q6 - WAN/IMP1 Port Queue 6 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q6 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_DEFAULT 0x000003c7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_HYST_Q7 - WAN/IMP1 Port Queue 7 Total Hysteresis Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_HYST_Q7 :: TOTAL_HYST_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_DEFAULT 0x000003c7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 - WAN/IMP1 Port Queue 0 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_DEFAULT 0x00000447 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 - WAN/IMP1 Port Queue 1 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_DEFAULT 0x0000044f |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 - WAN/IMP1 Port Queue 2 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_DEFAULT 0x00000457 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 - WAN/IMP1 Port Queue 3 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_DEFAULT 0x0000045f |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 - WAN/IMP1 Port Queue 4 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_DEFAULT 0x00000467 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 - WAN/IMP1 Port Queue 5 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_DEFAULT 0x0000046f |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 - WAN/IMP1 Port Queue 6 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_DEFAULT 0x00000477 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 - WAN/IMP1 Port Queue 7 Total Pause Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 :: TOTAL_PAUSE_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_DEFAULT 0x0000047f |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_DROP_Q0 - WAN/IMP1 Port Queue 0 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q0 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_DEFAULT 0x000005c7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_DROP_Q1 - WAN/IMP1 Port Queue 1 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q1 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_DEFAULT 0x000005cf |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_DROP_Q2 - WAN/IMP1 Port Queue 2 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q2 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_DEFAULT 0x000005d7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_DROP_Q3 - WAN/IMP1 Port Queue 3 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q3 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_DEFAULT 0x000005df |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_DROP_Q4 - WAN/IMP1 Port Queue 4 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q4 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_DEFAULT 0x000005e7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_DROP_Q5 - WAN/IMP1 Port Queue 5 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q5 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_DEFAULT 0x000005ef |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_DROP_Q6 - WAN/IMP1 Port Queue 6 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q6 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_DEFAULT 0x000005f7 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_TOTAL_THD_DROP_Q7 - WAN/IMP1 Port Queue 7 Total DROP Threshold Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_TOTAL_THD_DROP_Q7 :: TOTAL_DROP_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_DEFAULT 0x000005ff |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE0 :: FC_WAN_IMP1_REG_SPARE0 [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *FC_WAN_IMP1_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: FC_WAN_IMP1_REG_SPARE1 :: FC_WAN_IMP1_REG_SPARE1 [15:00] */ |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TEMP_MON_CTL - Temperature Monitor Control Registers(Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TEMP_MON_CTL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_CTL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_TEMP_MON_CTL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: TEMP_MON_CTL :: BIAS_ADJUST [07:01] */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_CTL_BIAS_ADJUST_MASK 0x000000fe |
| #define BCHP_SWITCH_CORE_TEMP_MON_CTL_BIAS_ADJUST_SHIFT 1 |
| #define BCHP_SWITCH_CORE_TEMP_MON_CTL_BIAS_ADJUST_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TEMP_MON_CTL :: ADC_TEST_EN [00:00] */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_CTL_ADC_TEST_EN_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_TEMP_MON_CTL_ADC_TEST_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TEMP_MON_CTL_ADC_TEST_EN_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *TEMP_MON_RESU - Temperature Monitor Result Registers(Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TEMP_MON_RESU :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_RESU_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TEMP_MON_RESU_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TEMP_MON_RESU :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_RESU_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_TEMP_MON_RESU_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TEMP_MON_RESU_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TEMP_MON_RESU :: TEMP_DATA [08:00] */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_RESU_TEMP_DATA_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_TEMP_MON_RESU_TEMP_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TEMP_MON_RESU_TEMP_DATA_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *PEAK_TEMP_MON_RESU - Peak Temperature Monitor Result Registers(Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PEAK_TEMP_MON_RESU :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PEAK_TEMP_MON_RESU :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PEAK_TEMP_MON_RESU :: PEAK_TEMP_DATA [08:00] */ |
| #define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_PEAK_TEMP_DATA_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_PEAK_TEMP_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PEAK_TEMP_MON_RESU_PEAK_TEMP_DATA_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *TEMP_MON_CAL - Temperature Monitor Calibration Registers(Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TEMP_MON_CAL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_CAL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TEMP_MON_CAL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TEMP_MON_CAL :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_CAL_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_TEMP_MON_CAL_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TEMP_MON_CAL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TEMP_MON_CAL :: TEMP_DATA_25C [08:00] */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_CAL_TEMP_DATA_25C_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_TEMP_MON_CAL_TEMP_DATA_25C_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TEMP_MON_CAL_TEMP_DATA_25C_DEFAULT 0x0000015a |
| |
| /*************************************************************************** |
| *TEMP_MON_SPEC_CTL - Temperature Monitor Special Control Registers(Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TEMP_MON_SPEC_CTL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: TEMP_MON_SPEC_CTL :: SWITCH_RESV [07:01] */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_SWITCH_RESV_MASK 0x000000fe |
| #define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_SWITCH_RESV_SHIFT 1 |
| #define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TEMP_MON_SPEC_CTL :: TEMP_PWRDN [00:00] */ |
| #define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_TEMP_PWRDN_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_TEMP_PWRDN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TEMP_MON_SPEC_CTL_TEMP_PWRDN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxOctets_P0 - Tx Octets |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxOctets_P0 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_TxOctets_P0_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_TxOctets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxOctets_P0_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *TxDropPkts_P0 - Tx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDropPkts_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDropPkts_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDropPkts_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ0_P0 - Tx Q0 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ0_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxBroadcastPkts_P0 - Tx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxBroadcastPkts_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMulticastPkts_P0 - Tx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMulticastPkts_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxUnicastPkts_P0 - Tx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxUnicastPkts_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxCollisions_P0 - Tx Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxCollisions_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxCollisions_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxCollisions_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxSingleCollision_P0 - Tx Single Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxSingleCollision_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMultipleCollision_P0 - Tx Multiple collsion Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMultipleCollision_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxDeferredTransmit_P0 - Tx Deferred Transmit Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDeferredTransmit_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxLateCollision_P0 - Tx Late Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxLateCollision_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxLateCollision_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxLateCollision_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxExcessiveCollision_P0 - Tx Excessive Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxExcessiveCollision_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxFrameInDisc_P0 - Tx Fram IN Disc Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxFrameInDisc_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPausePkts_P0 - Tx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPausePkts_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPausePkts_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPausePkts_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ1_P0 - Tx Q1 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ1_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ2_P0 - Tx Q2 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ2_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ3_P0 - Tx Q3 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ3_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ4_P0 - Tx Q4 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ4_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ5_P0 - Tx Q5 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ5_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOctets_P0 - Rx Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOctets_P0 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxOctets_P0_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxOctets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOctets_P0_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxUndersizePkts_P0 - Rx Under Size Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUndersizePkts_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPausePkts_P0 - Rx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPausePkts_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPausePkts_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPausePkts_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts64Octets_P0 - Rx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts64Octets_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts65to127Octets_P0 - Rx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts65to127Octets_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts128to255Octets_P0 - Rx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts128to255Octets_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts256to511Octets_P0 - Rx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts256to511Octets_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts512to1023Octets_P0 - Rx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts512to1023Octets_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts1024toMaxPktOctets_P0 - Rx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOversizePkts_P0 - Rx Over Size Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOversizePkts_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJabbers_P0 - Rx Jabber Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJabbers_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJabbers_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJabbers_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxAlignmentErrors_P0 - Rx Alignment Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxAlignmentErrors_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFCSErrors_P0 - Rx FCS Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFCSErrors_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxGoodOctets_P0 - Rx Good Packet Octet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxGoodOctets_P0 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P0_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P0_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxDropPkts_P0 - Rx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDropPkts_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDropPkts_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDropPkts_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxUnicastPkts_P0 - Rx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUnicastPkts_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxMulticastPkts_P0 - Rx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxMulticastPkts_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxBroadcastPkts_P0 - Rx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxBroadcastPkts_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSAChanges_P0 - Rx SA Change Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSAChanges_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSAChanges_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSAChanges_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFragments_P0 - Rx Fragment Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFragments_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFragments_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFragments_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFragments_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJumboPkt_P0 - Jumbo Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJumboPkt_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSymblErr_P0 - Rx Symbol Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSymblErr_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSymblErr_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSymblErr_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *InRangeErrCount_P0 - InRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: InRangeErrCount_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OutRangeErrCount_P0 - OutRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OutRangeErrCount_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_EVENT_P0 - EEE Low-Power Idle Event Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_EVENT_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_DURATION_P0 - EEE Low-Power Idle Duration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_DURATION_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxDiscard_P0 - Rx Discard Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDiscard_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDiscard_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDiscard_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ6_P0 - Tx Q6 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ6_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ7_P0 - Tx Q7 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ7_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts64Octets_P0 - Tx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts64Octets_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts65to127Octets_P0 - Tx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts65to127Octets_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts128to255Octets_P0 - Tx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts128to255Octets_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts256to511Octets_P0 - Tx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts256to511Octets_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts512to1023Octets_P0 - Tx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts512to1023Octets_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts1024toMaxPktOctets_P0 - Tx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxOctets_P1 - Tx Octets |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxOctets_P1 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_TxOctets_P1_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_TxOctets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxOctets_P1_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *TxDropPkts_P1 - Tx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDropPkts_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDropPkts_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDropPkts_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ0_P1 - Tx Q0 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ0_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxBroadcastPkts_P1 - Tx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxBroadcastPkts_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMulticastPkts_P1 - Tx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMulticastPkts_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxUnicastPkts_P1 - Tx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxUnicastPkts_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxCollisions_P1 - Tx Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxCollisions_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxCollisions_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxCollisions_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxSingleCollision_P1 - Tx Single Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxSingleCollision_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMultipleCollision_P1 - Tx Multiple collsion Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMultipleCollision_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxDeferredTransmit_P1 - Tx Deferred Transmit Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDeferredTransmit_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxLateCollision_P1 - Tx Late Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxLateCollision_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxLateCollision_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxLateCollision_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxExcessiveCollision_P1 - Tx Excessive Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxExcessiveCollision_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxFrameInDisc_P1 - Tx Fram IN Disc Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxFrameInDisc_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPausePkts_P1 - Tx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPausePkts_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPausePkts_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPausePkts_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ1_P1 - Tx Q1 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ1_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ2_P1 - Tx Q2 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ2_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ3_P1 - Tx Q3 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ3_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ4_P1 - Tx Q4 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ4_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ5_P1 - Tx Q5 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ5_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOctets_P1 - Rx Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOctets_P1 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxOctets_P1_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxOctets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOctets_P1_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxUndersizePkts_P1 - Rx Under Size Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUndersizePkts_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPausePkts_P1 - Rx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPausePkts_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPausePkts_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPausePkts_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts64Octets_P1 - Rx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts64Octets_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts65to127Octets_P1 - Rx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts65to127Octets_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts128to255Octets_P1 - Rx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts128to255Octets_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts256to511Octets_P1 - Rx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts256to511Octets_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts512to1023Octets_P1 - Rx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts512to1023Octets_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts1024toMaxPktOctets_P1 - Rx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOversizePkts_P1 - Rx Over Size Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOversizePkts_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJabbers_P1 - Rx Jabber Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJabbers_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJabbers_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJabbers_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxAlignmentErrors_P1 - Rx Alignment Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxAlignmentErrors_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFCSErrors_P1 - Rx FCS Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFCSErrors_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxGoodOctets_P1 - Rx Good Packet Octet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxGoodOctets_P1 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P1_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P1_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxDropPkts_P1 - Rx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDropPkts_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDropPkts_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDropPkts_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxUnicastPkts_P1 - Rx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUnicastPkts_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxMulticastPkts_P1 - Rx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxMulticastPkts_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxBroadcastPkts_P1 - Rx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxBroadcastPkts_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSAChanges_P1 - Rx SA Change Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSAChanges_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSAChanges_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSAChanges_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFragments_P1 - Rx Fragment Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFragments_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFragments_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFragments_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFragments_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJumboPkt_P1 - Jumbo Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJumboPkt_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSymblErr_P1 - Rx Symbol Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSymblErr_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSymblErr_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSymblErr_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *InRangeErrCount_P1 - InRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: InRangeErrCount_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OutRangeErrCount_P1 - OutRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OutRangeErrCount_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_EVENT_P1 - EEE Low-Power Idle Event Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_EVENT_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_DURATION_P1 - EEE Low-Power Idle Duration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_DURATION_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxDiscard_P1 - Rx Discard Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDiscard_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDiscard_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDiscard_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ6_P1 - Tx Q6 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ6_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ7_P1 - Tx Q7 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ7_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts64Octets_P1 - Tx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts64Octets_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts65to127Octets_P1 - Tx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts65to127Octets_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts128to255Octets_P1 - Tx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts128to255Octets_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts256to511Octets_P1 - Tx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts256to511Octets_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts512to1023Octets_P1 - Tx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts512to1023Octets_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts1024toMaxPktOctets_P1 - Tx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxOctets_P2 - Tx Octets |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxOctets_P2 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_TxOctets_P2_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_TxOctets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxOctets_P2_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *TxDropPkts_P2 - Tx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDropPkts_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDropPkts_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDropPkts_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ0_P2 - Tx Q0 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ0_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxBroadcastPkts_P2 - Tx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxBroadcastPkts_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMulticastPkts_P2 - Tx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMulticastPkts_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxUnicastPkts_P2 - Tx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxUnicastPkts_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxCollisions_P2 - Tx Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxCollisions_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxCollisions_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxCollisions_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxSingleCollision_P2 - Tx Single Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxSingleCollision_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMultipleCollision_P2 - Tx Multiple collsion Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMultipleCollision_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxDeferredTransmit_P2 - Tx Deferred Transmit Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDeferredTransmit_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxLateCollision_P2 - Tx Late Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxLateCollision_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxLateCollision_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxLateCollision_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxExcessiveCollision_P2 - Tx Excessive Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxExcessiveCollision_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxFrameInDisc_P2 - Tx Fram IN Disc Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxFrameInDisc_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPausePkts_P2 - Tx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPausePkts_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPausePkts_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPausePkts_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ1_P2 - Tx Q1 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ1_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ2_P2 - Tx Q2 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ2_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ3_P2 - Tx Q3 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ3_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ4_P2 - Tx Q4 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ4_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ5_P2 - Tx Q5 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ5_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOctets_P2 - Rx Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOctets_P2 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxOctets_P2_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxOctets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOctets_P2_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxUndersizePkts_P2 - Rx Under Size Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUndersizePkts_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPausePkts_P2 - Rx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPausePkts_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPausePkts_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPausePkts_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts64Octets_P2 - Rx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts64Octets_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts65to127Octets_P2 - Rx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts65to127Octets_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts128to255Octets_P2 - Rx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts128to255Octets_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts256to511Octets_P2 - Rx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts256to511Octets_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts512to1023Octets_P2 - Rx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts512to1023Octets_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts1024toMaxPktOctets_P2 - Rx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOversizePkts_P2 - Rx Over Size Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOversizePkts_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJabbers_P2 - Rx Jabber Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJabbers_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJabbers_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJabbers_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxAlignmentErrors_P2 - Rx Alignment Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxAlignmentErrors_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFCSErrors_P2 - Rx FCS Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFCSErrors_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxGoodOctets_P2 - Rx Good Packet Octet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxGoodOctets_P2 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P2_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P2_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxDropPkts_P2 - Rx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDropPkts_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDropPkts_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDropPkts_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxUnicastPkts_P2 - Rx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUnicastPkts_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxMulticastPkts_P2 - Rx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxMulticastPkts_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxBroadcastPkts_P2 - Rx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxBroadcastPkts_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSAChanges_P2 - Rx SA Change Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSAChanges_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSAChanges_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSAChanges_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFragments_P2 - Rx Fragment Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFragments_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFragments_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFragments_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFragments_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJumboPkt_P2 - Jumbo Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJumboPkt_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSymblErr_P2 - Rx Symbol Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSymblErr_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSymblErr_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSymblErr_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *InRangeErrCount_P2 - InRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: InRangeErrCount_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OutRangeErrCount_P2 - OutRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OutRangeErrCount_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_EVENT_P2 - EEE Low-Power Idle Event Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_EVENT_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_DURATION_P2 - EEE Low-Power Idle Duration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_DURATION_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxDiscard_P2 - Rx Discard Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDiscard_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDiscard_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDiscard_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ6_P2 - Tx Q6 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ6_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ7_P2 - Tx Q7 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ7_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts64Octets_P2 - Tx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts64Octets_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts65to127Octets_P2 - Tx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts65to127Octets_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts128to255Octets_P2 - Tx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts128to255Octets_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts256to511Octets_P2 - Tx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts256to511Octets_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts512to1023Octets_P2 - Tx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts512to1023Octets_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts1024toMaxPktOctets_P2 - Tx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxOctets_P3 - Tx Octets |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxOctets_P3 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_TxOctets_P3_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_TxOctets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxOctets_P3_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *TxDropPkts_P3 - Tx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDropPkts_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDropPkts_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDropPkts_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ0_P3 - Tx Q0 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ0_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxBroadcastPkts_P3 - Tx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxBroadcastPkts_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMulticastPkts_P3 - Tx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMulticastPkts_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxUnicastPkts_P3 - Tx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxUnicastPkts_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxCollisions_P3 - Tx Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxCollisions_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxCollisions_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxCollisions_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxSingleCollision_P3 - Tx Single Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxSingleCollision_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMultipleCollision_P3 - Tx Multiple collsion Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMultipleCollision_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxDeferredTransmit_P3 - Tx Deferred Transmit Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDeferredTransmit_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxLateCollision_P3 - Tx Late Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxLateCollision_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxLateCollision_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxLateCollision_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxExcessiveCollision_P3 - Tx Excessive Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxExcessiveCollision_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxFrameInDisc_P3 - Tx Fram IN Disc Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxFrameInDisc_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPausePkts_P3 - Tx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPausePkts_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPausePkts_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPausePkts_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ1_P3 - Tx Q1 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ1_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ2_P3 - Tx Q2 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ2_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ3_P3 - Tx Q3 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ3_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ4_P3 - Tx Q4 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ4_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ5_P3 - Tx Q5 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ5_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOctets_P3 - Rx Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOctets_P3 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxOctets_P3_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxOctets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOctets_P3_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxUndersizePkts_P3 - Rx Under Size Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUndersizePkts_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPausePkts_P3 - Rx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPausePkts_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPausePkts_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPausePkts_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts64Octets_P3 - Rx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts64Octets_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts65to127Octets_P3 - Rx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts65to127Octets_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts128to255Octets_P3 - Rx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts128to255Octets_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts256to511Octets_P3 - Rx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts256to511Octets_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts512to1023Octets_P3 - Rx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts512to1023Octets_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts1024toMaxPktOctets_P3 - Rx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOversizePkts_P3 - Rx Over Size Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOversizePkts_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJabbers_P3 - Rx Jabber Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJabbers_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJabbers_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJabbers_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxAlignmentErrors_P3 - Rx Alignment Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxAlignmentErrors_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFCSErrors_P3 - Rx FCS Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFCSErrors_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxGoodOctets_P3 - Rx Good Packet Octet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxGoodOctets_P3 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P3_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P3_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxDropPkts_P3 - Rx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDropPkts_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDropPkts_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDropPkts_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxUnicastPkts_P3 - Rx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUnicastPkts_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxMulticastPkts_P3 - Rx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxMulticastPkts_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxBroadcastPkts_P3 - Rx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxBroadcastPkts_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSAChanges_P3 - Rx SA Change Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSAChanges_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSAChanges_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSAChanges_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFragments_P3 - Rx Fragment Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFragments_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFragments_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFragments_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFragments_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJumboPkt_P3 - Jumbo Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJumboPkt_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSymblErr_P3 - Rx Symbol Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSymblErr_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSymblErr_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSymblErr_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *InRangeErrCount_P3 - InRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: InRangeErrCount_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OutRangeErrCount_P3 - OutRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OutRangeErrCount_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_EVENT_P3 - EEE Low-Power Idle Event Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_EVENT_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_DURATION_P3 - EEE Low-Power Idle Duration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_DURATION_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxDiscard_P3 - Rx Discard Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDiscard_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDiscard_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDiscard_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ6_P3 - Tx Q6 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ6_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ7_P3 - Tx Q7 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ7_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts64Octets_P3 - Tx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts64Octets_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts65to127Octets_P3 - Tx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts65to127Octets_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts128to255Octets_P3 - Tx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts128to255Octets_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts256to511Octets_P3 - Tx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts256to511Octets_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts512to1023Octets_P3 - Tx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts512to1023Octets_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts1024toMaxPktOctets_P3 - Tx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxOctets_P4 - Tx Octets |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxOctets_P4 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_TxOctets_P4_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_TxOctets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxOctets_P4_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *TxDropPkts_P4 - Tx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDropPkts_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDropPkts_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDropPkts_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ0_P4 - Tx Q0 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ0_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxBroadcastPkts_P4 - Tx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxBroadcastPkts_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMulticastPkts_P4 - Tx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMulticastPkts_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxUnicastPkts_P4 - Tx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxUnicastPkts_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxCollisions_P4 - Tx Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxCollisions_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxCollisions_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxCollisions_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxSingleCollision_P4 - Tx Single Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxSingleCollision_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMultipleCollision_P4 - Tx Multiple collsion Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMultipleCollision_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxDeferredTransmit_P4 - Tx Deferred Transmit Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDeferredTransmit_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxLateCollision_P4 - Tx Late Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxLateCollision_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxLateCollision_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxLateCollision_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxExcessiveCollision_P4 - Tx Excessive Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxExcessiveCollision_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxFrameInDisc_P4 - Tx Fram IN Disc Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxFrameInDisc_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPausePkts_P4 - Tx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPausePkts_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPausePkts_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPausePkts_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ1_P4 - Tx Q1 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ1_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ2_P4 - Tx Q2 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ2_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ3_P4 - Tx Q3 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ3_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ4_P4 - Tx Q4 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ4_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ5_P4 - Tx Q5 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ5_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOctets_P4 - Rx Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOctets_P4 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxOctets_P4_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxOctets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOctets_P4_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxUndersizePkts_P4 - Rx Under Size Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUndersizePkts_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPausePkts_P4 - Rx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPausePkts_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPausePkts_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPausePkts_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts64Octets_P4 - Rx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts64Octets_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts65to127Octets_P4 - Rx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts65to127Octets_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts128to255Octets_P4 - Rx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts128to255Octets_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts256to511Octets_P4 - Rx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts256to511Octets_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts512to1023Octets_P4 - Rx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts512to1023Octets_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts1024toMaxPktOctets_P4 - Rx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOversizePkts_P4 - Rx Over Size Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOversizePkts_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJabbers_P4 - Rx Jabber Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJabbers_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJabbers_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJabbers_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxAlignmentErrors_P4 - Rx Alignment Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxAlignmentErrors_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFCSErrors_P4 - Rx FCS Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFCSErrors_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxGoodOctets_P4 - Rx Good Packet Octet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxGoodOctets_P4 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P4_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P4_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxDropPkts_P4 - Rx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDropPkts_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDropPkts_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDropPkts_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxUnicastPkts_P4 - Rx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUnicastPkts_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxMulticastPkts_P4 - Rx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxMulticastPkts_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxBroadcastPkts_P4 - Rx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxBroadcastPkts_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSAChanges_P4 - Rx SA Change Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSAChanges_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSAChanges_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSAChanges_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFragments_P4 - Rx Fragment Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFragments_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFragments_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFragments_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFragments_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJumboPkt_P4 - Jumbo Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJumboPkt_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSymblErr_P4 - Rx Symbol Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSymblErr_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSymblErr_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSymblErr_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *InRangeErrCount_P4 - InRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: InRangeErrCount_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OutRangeErrCount_P4 - OutRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OutRangeErrCount_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_EVENT_P4 - EEE Low-Power Idle Event Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_EVENT_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_DURATION_P4 - EEE Low-Power Idle Duration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_DURATION_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxDiscard_P4 - Rx Discard Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDiscard_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDiscard_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDiscard_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ6_P4 - Tx Q6 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ6_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ7_P4 - Tx Q7 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ7_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts64Octets_P4 - Tx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts64Octets_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts65to127Octets_P4 - Tx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts65to127Octets_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts128to255Octets_P4 - Tx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts128to255Octets_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts256to511Octets_P4 - Tx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts256to511Octets_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts512to1023Octets_P4 - Tx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts512to1023Octets_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts1024toMaxPktOctets_P4 - Tx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxOctets_P5 - Tx Octets |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxOctets_P5 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_TxOctets_P5_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_TxOctets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxOctets_P5_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *TxDropPkts_P5 - Tx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDropPkts_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDropPkts_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDropPkts_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ0_P5 - Tx Q0 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ0_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxBroadcastPkts_P5 - Tx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxBroadcastPkts_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMulticastPkts_P5 - Tx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMulticastPkts_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxUnicastPkts_P5 - Tx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxUnicastPkts_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxCollisions_P5 - Tx Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxCollisions_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxCollisions_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxCollisions_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxSingleCollision_P5 - Tx Single Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxSingleCollision_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMultipleCollision_P5 - Tx Multiple collsion Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMultipleCollision_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxDeferredTransmit_P5 - Tx Deferred Transmit Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDeferredTransmit_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxLateCollision_P5 - Tx Late Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxLateCollision_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxLateCollision_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxLateCollision_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxExcessiveCollision_P5 - Tx Excessive Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxExcessiveCollision_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxFrameInDisc_P5 - Tx Fram IN Disc Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxFrameInDisc_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPausePkts_P5 - Tx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPausePkts_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPausePkts_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPausePkts_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ1_P5 - Tx Q1 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ1_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ2_P5 - Tx Q2 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ2_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ3_P5 - Tx Q3 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ3_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ4_P5 - Tx Q4 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ4_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ5_P5 - Tx Q5 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ5_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOctets_P5 - Rx Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOctets_P5 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxOctets_P5_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxOctets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOctets_P5_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxUndersizePkts_P5 - Rx Under Size Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUndersizePkts_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPausePkts_P5 - Rx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPausePkts_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPausePkts_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPausePkts_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts64Octets_P5 - Rx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts64Octets_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts65to127Octets_P5 - Rx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts65to127Octets_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts128to255Octets_P5 - Rx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts128to255Octets_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts256to511Octets_P5 - Rx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts256to511Octets_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts512to1023Octets_P5 - Rx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts512to1023Octets_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts1024toMaxPktOctets_P5 - Rx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOversizePkts_P5 - Rx Over Size Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOversizePkts_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJabbers_P5 - Rx Jabber Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJabbers_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJabbers_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJabbers_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxAlignmentErrors_P5 - Rx Alignment Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxAlignmentErrors_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFCSErrors_P5 - Rx FCS Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFCSErrors_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxGoodOctets_P5 - Rx Good Packet Octet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxGoodOctets_P5 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P5_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P5_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxDropPkts_P5 - Rx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDropPkts_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDropPkts_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDropPkts_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxUnicastPkts_P5 - Rx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUnicastPkts_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxMulticastPkts_P5 - Rx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxMulticastPkts_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxBroadcastPkts_P5 - Rx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxBroadcastPkts_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSAChanges_P5 - Rx SA Change Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSAChanges_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSAChanges_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSAChanges_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFragments_P5 - Rx Fragment Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFragments_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFragments_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFragments_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFragments_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJumboPkt_P5 - Jumbo Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJumboPkt_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSymblErr_P5 - Rx Symbol Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSymblErr_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSymblErr_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSymblErr_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *InRangeErrCount_P5 - InRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: InRangeErrCount_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OutRangeErrCount_P5 - OutRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OutRangeErrCount_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_EVENT_P5 - EEE Low-Power Idle Event Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_EVENT_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_DURATION_P5 - EEE Low-Power Idle Duration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_DURATION_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxDiscard_P5 - Rx Discard Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDiscard_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDiscard_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDiscard_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ6_P5 - Tx Q6 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ6_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ7_P5 - Tx Q7 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ7_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts64Octets_P5 - Tx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts64Octets_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts65to127Octets_P5 - Tx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts65to127Octets_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts128to255Octets_P5 - Tx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts128to255Octets_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts256to511Octets_P5 - Tx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts256to511Octets_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts512to1023Octets_P5 - Tx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts512to1023Octets_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts1024toMaxPktOctets_P5 - Tx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxOctets_P7 - Tx Octets |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxOctets_P7 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_TxOctets_P7_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_TxOctets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxOctets_P7_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *TxDropPkts_P7 - Tx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDropPkts_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDropPkts_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDropPkts_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ0_P7 - Tx Q0 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ0_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxBroadcastPkts_P7 - Tx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxBroadcastPkts_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMulticastPkts_P7 - Tx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMulticastPkts_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxUnicastPkts_P7 - Tx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxUnicastPkts_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxCollisions_P7 - Tx Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxCollisions_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxCollisions_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxCollisions_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxCollisions_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxSingleCollision_P7 - Tx Single Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxSingleCollision_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxSingleCollision_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMultipleCollision_P7 - Tx Multiple collsion Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMultipleCollision_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxDeferredTransmit_P7 - Tx Deferred Transmit Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDeferredTransmit_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxLateCollision_P7 - Tx Late Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxLateCollision_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxLateCollision_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxLateCollision_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxExcessiveCollision_P7 - Tx Excessive Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxExcessiveCollision_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxFrameInDisc_P7 - Tx Fram IN Disc Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxFrameInDisc_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPausePkts_P7 - Tx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPausePkts_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPausePkts_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPausePkts_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ1_P7 - Tx Q1 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ1_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ2_P7 - Tx Q2 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ2_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ3_P7 - Tx Q3 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ3_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ4_P7 - Tx Q4 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ4_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ5_P7 - Tx Q5 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ5_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOctets_P7 - Rx Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOctets_P7 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxOctets_P7_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxOctets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOctets_P7_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxUndersizePkts_P7 - Rx Under Size Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUndersizePkts_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPausePkts_P7 - Rx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPausePkts_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPausePkts_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPausePkts_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts64Octets_P7 - Rx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts64Octets_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts65to127Octets_P7 - Rx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts65to127Octets_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts128to255Octets_P7 - Rx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts128to255Octets_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts256to511Octets_P7 - Rx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts256to511Octets_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts512to1023Octets_P7 - Rx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts512to1023Octets_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts1024toMaxPktOctets_P7 - Rx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts1024toMaxPktOctets_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOversizePkts_P7 - Rx Over Size Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOversizePkts_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOversizePkts_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJabbers_P7 - Rx Jabber Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJabbers_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJabbers_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJabbers_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJabbers_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxAlignmentErrors_P7 - Rx Alignment Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxAlignmentErrors_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFCSErrors_P7 - Rx FCS Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFCSErrors_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFCSErrors_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxGoodOctets_P7 - Rx Good Packet Octet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxGoodOctets_P7 :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P7_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_P7_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxDropPkts_P7 - Rx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDropPkts_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDropPkts_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDropPkts_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxUnicastPkts_P7 - Rx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUnicastPkts_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxMulticastPkts_P7 - Rx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxMulticastPkts_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxBroadcastPkts_P7 - Rx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxBroadcastPkts_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSAChanges_P7 - Rx SA Change Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSAChanges_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSAChanges_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSAChanges_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFragments_P7 - Rx Fragment Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFragments_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFragments_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFragments_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFragments_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJumboPkt_P7 - Jumbo Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJumboPkt_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJumboPkt_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSymblErr_P7 - Rx Symbol Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSymblErr_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSymblErr_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSymblErr_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *InRangeErrCount_P7 - InRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: InRangeErrCount_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_InRangeErrCount_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OutRangeErrCount_P7 - OutRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OutRangeErrCount_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_EVENT_P7 - EEE Low-Power Idle Event Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_EVENT_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_DURATION_P7 - EEE Low-Power Idle Duration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_DURATION_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxDiscard_P7 - Rx Discard Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDiscard_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDiscard_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDiscard_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDiscard_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ6_P7 - Tx Q6 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ6_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ7_P7 - Tx Q7 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ7_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts64Octets_P7 - Tx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts64Octets_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts65to127Octets_P7 - Tx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts65to127Octets_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts128to255Octets_P7 - Tx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts128to255Octets_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts256to511Octets_P7 - Tx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts256to511Octets_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts512to1023Octets_P7 - Tx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts512to1023Octets_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts1024toMaxPktOctets_P7 - Tx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts1024toMaxPktOctets_P7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_P7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxOctets_IMP - Tx Octets |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxOctets_IMP :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_TxOctets_IMP_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_TxOctets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxOctets_IMP_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *TxDropPkts_IMP - Tx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDropPkts_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDropPkts_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDropPkts_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDropPkts_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ0_IMP - Tx Q0 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ0_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ0_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxBroadcastPkts_IMP - Tx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxBroadcastPkts_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxBroadcastPkts_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMulticastPkts_IMP - Tx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMulticastPkts_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMulticastPkts_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxUnicastPkts_IMP - Tx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxUnicastPkts_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxUnicastPkts_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxCollisions_IMP - Tx Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxCollisions_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxCollisions_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxCollisions_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxCollisions_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxSingleCollision_IMP - Tx Single Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxSingleCollision_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxSingleCollision_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxSingleCollision_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxSingleCollision_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxMultipleCollision_IMP - Tx Multiple collsion Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxMultipleCollision_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxMultipleCollision_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxDeferredTransmit_IMP - Tx Deferred Transmit Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxDeferredTransmit_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxDeferredTransmit_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxLateCollision_IMP - Tx Late Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxLateCollision_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxLateCollision_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxLateCollision_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxLateCollision_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxExcessiveCollision_IMP - Tx Excessive Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxExcessiveCollision_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxExcessiveCollision_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxFrameInDisc_IMP - Tx Fram IN Disc Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxFrameInDisc_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxFrameInDisc_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPausePkts_IMP - Tx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPausePkts_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPausePkts_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPausePkts_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPausePkts_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ1_IMP - Tx Q1 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ1_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ1_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ2_IMP - Tx Q2 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ2_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ2_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ3_IMP - Tx Q3 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ3_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ3_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ4_IMP - Tx Q4 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ4_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ4_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ5_IMP - Tx Q5 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ5_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ5_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOctets_IMP - Rx Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOctets_IMP :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxOctets_IMP_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxOctets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOctets_IMP_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxUndersizePkts_IMP - Rx Under Size Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUndersizePkts_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUndersizePkts_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPausePkts_IMP - Rx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPausePkts_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPausePkts_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPausePkts_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPausePkts_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts64Octets_IMP - Rx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts64Octets_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts64Octets_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts65to127Octets_IMP - Rx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts65to127Octets_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts65to127Octets_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts128to255Octets_IMP - Rx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts128to255Octets_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts128to255Octets_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts256to511Octets_IMP - Rx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts256to511Octets_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts256to511Octets_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts512to1023Octets_IMP - Rx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts512to1023Octets_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts512to1023Octets_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxPkts1024toMaxPktOctets_IMP - Rx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxPkts1024toMaxPktOctets_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxOversizePkts_IMP - Rx Over Size Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxOversizePkts_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxOversizePkts_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxOversizePkts_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxOversizePkts_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJabbers_IMP - Rx Jabber Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJabbers_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJabbers_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJabbers_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJabbers_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxAlignmentErrors_IMP - Rx Alignment Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxAlignmentErrors_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxAlignmentErrors_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFCSErrors_IMP - Rx FCS Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFCSErrors_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFCSErrors_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFCSErrors_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFCSErrors_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxGoodOctets_IMP - Rx Good Packet Octet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxGoodOctets_IMP :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_RxGoodOctets_IMP_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxGoodOctets_IMP_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RxDropPkts_IMP - Rx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDropPkts_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDropPkts_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDropPkts_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDropPkts_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxUnicastPkts_IMP - Rx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxUnicastPkts_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxUnicastPkts_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxMulticastPkts_IMP - Rx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxMulticastPkts_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxMulticastPkts_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxBroadcastPkts_IMP - Rx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxBroadcastPkts_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxBroadcastPkts_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSAChanges_IMP - Rx SA Change Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSAChanges_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSAChanges_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSAChanges_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSAChanges_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxFragments_IMP - Rx Fragment Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxFragments_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxFragments_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxFragments_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxFragments_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxJumboPkt_IMP - Jumbo Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxJumboPkt_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxJumboPkt_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxJumboPkt_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxJumboPkt_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxSymblErr_IMP - Rx Symbol Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxSymblErr_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxSymblErr_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxSymblErr_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxSymblErr_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *InRangeErrCount_IMP - InRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: InRangeErrCount_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_InRangeErrCount_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_InRangeErrCount_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_InRangeErrCount_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OutRangeErrCount_IMP - OutRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OutRangeErrCount_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OutRangeErrCount_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_EVENT_IMP - EEE Low-Power Idle Event Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_EVENT_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_EVENT_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_DURATION_IMP - EEE Low-Power Idle Duration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_DURATION_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_DURATION_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RxDiscard_IMP - Rx Discard Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RxDiscard_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_RxDiscard_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RxDiscard_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RxDiscard_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ6_IMP - Tx Q6 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ6_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ6_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxQPKTQ7_IMP - Tx Q7 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxQPKTQ7_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxQPKTQ7_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts64Octets_IMP - Tx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts64Octets_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts64Octets_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts65to127Octets_IMP - Tx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts65to127Octets_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts65to127Octets_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts128to255Octets_IMP - Tx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts128to255Octets_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts128to255Octets_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts256to511Octets_IMP - Tx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts256to511Octets_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts256to511Octets_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts512to1023Octets_IMP - Tx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts512to1023Octets_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts512to1023Octets_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TxPkts1024toMaxPktOctets_IMP - Tx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TxPkts1024toMaxPktOctets_IMP :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_GLOBAL_CTRL - QOS Global Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_GLOBAL_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: QOS_GLOBAL_CTRL :: P8_AGGREGATION_MODE [07:07] */ |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_SHIFT 7 |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_GLOBAL_CTRL :: SWITCH_RESV_1 [06:05] */ |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_1_MASK 0x00000060 |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_1_SHIFT 5 |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_GLOBAL_CTRL :: P5_AGGREGATION_MODE [04:04] */ |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_SHIFT 4 |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_GLOBAL_CTRL :: SWITCH_RESV_0 [03:00] */ |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_0_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_GLOBAL_CTRL_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_1P_EN - QoS 802.1P Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_1P_EN :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QOS_1P_EN_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QOS_1P_EN_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QOS_1P_EN :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QOS_1P_EN_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QOS_1P_EN_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QOS_1P_EN_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_1P_EN :: QOS_1P_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_QOS_1P_EN_QOS_1P_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QOS_1P_EN_QOS_1P_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_1P_EN_QOS_1P_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_EN_DIFFSERV - QOS DiffServ Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_EN_DIFFSERV :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QOS_EN_DIFFSERV :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_EN_DIFFSERV :: QOS_EN_DIFFSERV [08:00] */ |
| #define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI0_P0 - Port 0 PCP to TC Map for DEI 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI0_P0 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P0 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P0_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI0_P1 - Port 1 PCP to TC Map for DEI 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI0_P1 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P1 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P1_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI0_P2 - Port 2 PCP to TC Map for DEI 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI0_P2 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P2 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P2_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI0_P3 - Port 3 PCP to TC Map for DEI 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI0_P3 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P3 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P3_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI0_P4 - Port 4 PCP to TC Map for DEI 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI0_P4 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P4 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P4_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI0_P5 - Port 5 PCP to TC Map for DEI 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI0_P5 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P5 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P5_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI0_P7 - Port 7 PCP to TC Map for DEI 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI0_P7 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_P7 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_P7_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI0_IMP - Port 8 (IMP) PCP to TC Map for DEI 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI0_IMP :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI0_IMP :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI0_IMP_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_DIFF_DSCP0 - DiffServ Priority Map 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001111 [47:45] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001111_MASK 0xe00000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001111_SHIFT 45 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001111_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001110 [44:42] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001110_MASK 0x1c0000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001110_SHIFT 42 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001110_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001101 [41:39] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001101_MASK 0x038000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001101_SHIFT 39 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001101_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001100 [38:36] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001100_MASK 0x007000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001100_SHIFT 36 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001100_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001011 [35:33] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001011_MASK 0x000e00000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001011_SHIFT 33 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001011_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001010 [32:30] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001010_MASK 0x0001c0000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001010_SHIFT 30 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001010_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001001 [29:27] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001001_MASK 0x000038000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001001_SHIFT 27 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001001_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_001000 [26:24] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001000_MASK 0x000007000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001000_SHIFT 24 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_001000_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000111 [23:21] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000111_MASK 0x000000e00000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000111_SHIFT 21 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000111_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000110 [20:18] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000110_MASK 0x0000001c0000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000110_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000110_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000101 [17:15] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000101_MASK 0x000000038000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000101_SHIFT 15 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000101_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000100 [14:12] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000100_MASK 0x000000007000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000100_SHIFT 12 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000100_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000011 [11:09] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000011_MASK 0x000000000e00 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000011_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000011_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000010 [08:06] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000010_MASK 0x0000000001c0 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000010_SHIFT 6 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000010_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000001 [05:03] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000001_MASK 0x000000000038 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000001_SHIFT 3 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000001_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP0 :: PRI_DSCP_000000 [02:00] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000000_MASK 0x000000000007 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000000_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP0_PRI_DSCP_000000_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *QOS_DIFF_DSCP1 - DiffServ Priority Map 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011111 [47:45] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011111_MASK 0xe00000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011111_SHIFT 45 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011111_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011110 [44:42] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011110_MASK 0x1c0000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011110_SHIFT 42 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011110_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011101 [41:39] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011101_MASK 0x038000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011101_SHIFT 39 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011101_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011100 [38:36] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011100_MASK 0x007000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011100_SHIFT 36 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011100_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011011 [35:33] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011011_MASK 0x000e00000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011011_SHIFT 33 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011011_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011010 [32:30] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011010_MASK 0x0001c0000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011010_SHIFT 30 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011010_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011001 [29:27] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011001_MASK 0x000038000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011001_SHIFT 27 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011001_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_011000 [26:24] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011000_MASK 0x000007000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011000_SHIFT 24 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_011000_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010111 [23:21] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010111_MASK 0x000000e00000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010111_SHIFT 21 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010111_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010110 [20:18] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010110_MASK 0x0000001c0000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010110_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010110_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010101 [17:15] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010101_MASK 0x000000038000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010101_SHIFT 15 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010101_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010100 [14:12] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010100_MASK 0x000000007000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010100_SHIFT 12 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010100_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010011 [11:09] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010011_MASK 0x000000000e00 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010011_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010011_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010010 [08:06] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010010_MASK 0x0000000001c0 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010010_SHIFT 6 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010010_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010001 [05:03] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010001_MASK 0x000000000038 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010001_SHIFT 3 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010001_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP1 :: PRI_DSCP_010000 [02:00] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010000_MASK 0x000000000007 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010000_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP1_PRI_DSCP_010000_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *QOS_DIFF_DSCP2 - DiffServ Priority Map 2 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101111 [47:45] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101111_MASK 0xe00000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101111_SHIFT 45 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101111_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101110 [44:42] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101110_MASK 0x1c0000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101110_SHIFT 42 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101110_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101101 [41:39] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101101_MASK 0x038000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101101_SHIFT 39 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101101_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101100 [38:36] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101100_MASK 0x007000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101100_SHIFT 36 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101100_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101011 [35:33] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101011_MASK 0x000e00000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101011_SHIFT 33 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101011_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101010 [32:30] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101010_MASK 0x0001c0000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101010_SHIFT 30 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101010_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101001 [29:27] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101001_MASK 0x000038000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101001_SHIFT 27 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101001_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_101000 [26:24] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101000_MASK 0x000007000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101000_SHIFT 24 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_101000_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100111 [23:21] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100111_MASK 0x000000e00000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100111_SHIFT 21 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100111_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100110 [20:18] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100110_MASK 0x0000001c0000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100110_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100110_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100101 [17:15] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100101_MASK 0x000000038000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100101_SHIFT 15 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100101_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100100 [14:12] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100100_MASK 0x000000007000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100100_SHIFT 12 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100100_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100011 [11:09] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100011_MASK 0x000000000e00 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100011_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100011_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100010 [08:06] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100010_MASK 0x0000000001c0 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100010_SHIFT 6 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100010_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100001 [05:03] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100001_MASK 0x000000000038 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100001_SHIFT 3 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100001_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP2 :: PRI_DSCP_100000 [02:00] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100000_MASK 0x000000000007 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100000_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP2_PRI_DSCP_100000_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *QOS_DIFF_DSCP3 - DiffServ Priority Map 3 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111111 [47:45] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111111_MASK 0xe00000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111111_SHIFT 45 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111111_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111110 [44:42] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111110_MASK 0x1c0000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111110_SHIFT 42 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111110_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111101 [41:39] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111101_MASK 0x038000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111101_SHIFT 39 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111101_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111100 [38:36] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111100_MASK 0x007000000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111100_SHIFT 36 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111100_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111011 [35:33] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111011_MASK 0x000e00000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111011_SHIFT 33 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111011_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111010 [32:30] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111010_MASK 0x0001c0000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111010_SHIFT 30 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111010_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111001 [29:27] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111001_MASK 0x000038000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111001_SHIFT 27 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111001_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_111000 [26:24] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111000_MASK 0x000007000000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111000_SHIFT 24 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_111000_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110111 [23:21] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110111_MASK 0x000000e00000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110111_SHIFT 21 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110111_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110110 [20:18] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110110_MASK 0x0000001c0000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110110_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110110_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110101 [17:15] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110101_MASK 0x000000038000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110101_SHIFT 15 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110101_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110100 [14:12] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110100_MASK 0x000000007000 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110100_SHIFT 12 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110100_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110011 [11:09] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110011_MASK 0x000000000e00 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110011_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110011_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110010 [08:06] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110010_MASK 0x0000000001c0 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110010_SHIFT 6 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110010_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110001 [05:03] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110001_MASK 0x000000000038 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110001_SHIFT 3 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110001_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: QOS_DIFF_DSCP3 :: PRI_DSCP_110000 [02:00] */ |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110000_MASK 0x000000000007 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110000_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_DIFF_DSCP3_PRI_DSCP_110000_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *PID2TC - Port ID to TC Map Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PID2TC :: SWITCH_RESV [31:27] */ |
| #define BCHP_SWITCH_CORE_PID2TC_SWITCH_RESV_MASK 0xf8000000 |
| #define BCHP_SWITCH_CORE_PID2TC_SWITCH_RESV_SHIFT 27 |
| #define BCHP_SWITCH_CORE_PID2TC_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PID2TC :: PID2TC [26:00] */ |
| #define BCHP_SWITCH_CORE_PID2TC_PID2TC_MASK 0x07ffffff |
| #define BCHP_SWITCH_CORE_PID2TC_PID2TC_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PID2TC_PID2TC_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC_SEL_TABLE_P0 - Port 0 TC Select Table Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC_SEL_TABLE_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_7 [15:14] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_7_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_7_SHIFT 14 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_6 [13:12] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_6_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_6_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_6_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_5 [11:10] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_5_MASK 0x00000c00 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_5_SHIFT 10 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_4 [09:08] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_4_MASK 0x00000300 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_4_SHIFT 8 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_3 [07:06] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_3_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_3_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_2 [05:04] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_2_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_2_SHIFT 4 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_1 [03:02] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_1_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_1_SHIFT 2 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P0 :: TC_SEL_0 [01:00] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_0_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P0_TC_SEL_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC_SEL_TABLE_P1 - Port 1 TC Select Table Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC_SEL_TABLE_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_7 [15:14] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_7_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_7_SHIFT 14 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_6 [13:12] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_6_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_6_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_6_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_5 [11:10] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_5_MASK 0x00000c00 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_5_SHIFT 10 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_4 [09:08] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_4_MASK 0x00000300 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_4_SHIFT 8 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_3 [07:06] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_3_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_3_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_2 [05:04] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_2_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_2_SHIFT 4 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_1 [03:02] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_1_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_1_SHIFT 2 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P1 :: TC_SEL_0 [01:00] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_0_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P1_TC_SEL_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC_SEL_TABLE_P2 - Port 2 TC Select Table Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC_SEL_TABLE_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_7 [15:14] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_7_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_7_SHIFT 14 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_6 [13:12] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_6_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_6_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_6_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_5 [11:10] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_5_MASK 0x00000c00 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_5_SHIFT 10 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_4 [09:08] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_4_MASK 0x00000300 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_4_SHIFT 8 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_3 [07:06] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_3_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_3_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_2 [05:04] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_2_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_2_SHIFT 4 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_1 [03:02] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_1_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_1_SHIFT 2 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P2 :: TC_SEL_0 [01:00] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_0_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P2_TC_SEL_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC_SEL_TABLE_P3 - Port 3 TC Select Table Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC_SEL_TABLE_P3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_7 [15:14] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_7_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_7_SHIFT 14 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_6 [13:12] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_6_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_6_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_6_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_5 [11:10] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_5_MASK 0x00000c00 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_5_SHIFT 10 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_4 [09:08] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_4_MASK 0x00000300 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_4_SHIFT 8 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_3 [07:06] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_3_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_3_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_2 [05:04] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_2_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_2_SHIFT 4 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_1 [03:02] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_1_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_1_SHIFT 2 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P3 :: TC_SEL_0 [01:00] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_0_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P3_TC_SEL_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC_SEL_TABLE_P4 - Port 4 TC Select Table Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC_SEL_TABLE_P4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_7 [15:14] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_7_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_7_SHIFT 14 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_6 [13:12] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_6_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_6_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_6_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_5 [11:10] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_5_MASK 0x00000c00 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_5_SHIFT 10 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_4 [09:08] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_4_MASK 0x00000300 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_4_SHIFT 8 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_3 [07:06] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_3_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_3_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_2 [05:04] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_2_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_2_SHIFT 4 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_1 [03:02] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_1_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_1_SHIFT 2 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P4 :: TC_SEL_0 [01:00] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_0_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P4_TC_SEL_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC_SEL_TABLE_P5 - Port 5 TC Select Table Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC_SEL_TABLE_P5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_7 [15:14] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_7_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_7_SHIFT 14 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_6 [13:12] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_6_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_6_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_6_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_5 [11:10] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_5_MASK 0x00000c00 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_5_SHIFT 10 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_4 [09:08] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_4_MASK 0x00000300 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_4_SHIFT 8 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_3 [07:06] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_3_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_3_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_2 [05:04] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_2_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_2_SHIFT 4 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_1 [03:02] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_1_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_1_SHIFT 2 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P5 :: TC_SEL_0 [01:00] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_0_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P5_TC_SEL_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC_SEL_TABLE_P7 - Port 7 TC Select Table Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC_SEL_TABLE_P7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_7 [15:14] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_7_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_7_SHIFT 14 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_6 [13:12] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_6_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_6_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_6_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_5 [11:10] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_5_MASK 0x00000c00 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_5_SHIFT 10 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_4 [09:08] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_4_MASK 0x00000300 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_4_SHIFT 8 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_3 [07:06] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_3_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_3_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_2 [05:04] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_2_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_2_SHIFT 4 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_1 [03:02] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_1_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_1_SHIFT 2 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_P7 :: TC_SEL_0 [01:00] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_0_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_P7_TC_SEL_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC_SEL_TABLE_IMP - Port 8 TC Select Table Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC_SEL_TABLE_IMP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_7 [15:14] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_7_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_7_SHIFT 14 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_6 [13:12] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_6_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_6_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_6_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_5 [11:10] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_5_MASK 0x00000c00 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_5_SHIFT 10 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_4 [09:08] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_4_MASK 0x00000300 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_4_SHIFT 8 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_3 [07:06] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_3_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_3_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_2 [05:04] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_2_MASK 0x00000030 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_2_SHIFT 4 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_1 [03:02] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_1_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_1_SHIFT 2 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC_SEL_TABLE_IMP :: TC_SEL_0 [01:00] */ |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_0_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC_SEL_TABLE_IMP_TC_SEL_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CPU2COS_MAP - CPU to COS Mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CPU2COS_MAP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CPU2COS_MAP :: EXCPT_PRCS [17:15] */ |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_EXCPT_PRCS_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_EXCPT_PRCS_SHIFT 15 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_EXCPT_PRCS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CPU2COS_MAP :: PRTC_SNOOP [14:12] */ |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_SNOOP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_SNOOP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_SNOOP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CPU2COS_MAP :: PRTC_TRMNT [11:09] */ |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_TRMNT_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_TRMNT_SHIFT 9 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_PRTC_TRMNT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CPU2COS_MAP :: SW_FLD [08:06] */ |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_SW_FLD_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_SW_FLD_SHIFT 6 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_SW_FLD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CPU2COS_MAP :: SA_LRN [05:03] */ |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_SA_LRN_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_SA_LRN_SHIFT 3 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_SA_LRN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CPU2COS_MAP :: MIRROR [02:00] */ |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_MIRROR_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_MIRROR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CPU2COS_MAP_MIRROR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC2COS_MAP_P0 - Port 0 TC to COS Mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC2COS_MAP_P0 :: BCAST_DLF_DROP_TC [31:24] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_BCAST_DLF_DROP_TC_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_BCAST_DLF_DROP_TC_SHIFT 24 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_BCAST_DLF_DROP_TC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT111_TO_QID [23:21] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT111_TO_QID_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT111_TO_QID_SHIFT 21 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT111_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT110_TO_QID [20:18] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT110_TO_QID_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT110_TO_QID_SHIFT 18 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT110_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT101_TO_QID [17:15] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT101_TO_QID_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT101_TO_QID_SHIFT 15 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT101_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT100_TO_QID [14:12] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT100_TO_QID_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT100_TO_QID_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT100_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT011_TO_QID [11:09] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT011_TO_QID_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT011_TO_QID_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT011_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT010_TO_QID [08:06] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT010_TO_QID_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT010_TO_QID_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT010_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT001_TO_QID [05:03] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT001_TO_QID_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT001_TO_QID_SHIFT 3 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT001_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P0 :: PRT000_TO_QID [02:00] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT000_TO_QID_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT000_TO_QID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P0_PRT000_TO_QID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC2COS_MAP_P1 - Port 1 TC to COS Mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC2COS_MAP_P1 :: BCAST_DLF_DROP_TC [31:24] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_BCAST_DLF_DROP_TC_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_BCAST_DLF_DROP_TC_SHIFT 24 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_BCAST_DLF_DROP_TC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT111_TO_QID [23:21] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT111_TO_QID_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT111_TO_QID_SHIFT 21 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT111_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT110_TO_QID [20:18] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT110_TO_QID_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT110_TO_QID_SHIFT 18 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT110_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT101_TO_QID [17:15] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT101_TO_QID_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT101_TO_QID_SHIFT 15 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT101_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT100_TO_QID [14:12] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT100_TO_QID_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT100_TO_QID_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT100_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT011_TO_QID [11:09] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT011_TO_QID_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT011_TO_QID_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT011_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT010_TO_QID [08:06] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT010_TO_QID_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT010_TO_QID_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT010_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT001_TO_QID [05:03] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT001_TO_QID_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT001_TO_QID_SHIFT 3 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT001_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P1 :: PRT000_TO_QID [02:00] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT000_TO_QID_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT000_TO_QID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P1_PRT000_TO_QID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC2COS_MAP_P2 - Port 2 TC to COS Mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC2COS_MAP_P2 :: BCAST_DLF_DROP_TC [31:24] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_BCAST_DLF_DROP_TC_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_BCAST_DLF_DROP_TC_SHIFT 24 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_BCAST_DLF_DROP_TC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT111_TO_QID [23:21] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT111_TO_QID_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT111_TO_QID_SHIFT 21 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT111_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT110_TO_QID [20:18] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT110_TO_QID_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT110_TO_QID_SHIFT 18 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT110_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT101_TO_QID [17:15] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT101_TO_QID_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT101_TO_QID_SHIFT 15 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT101_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT100_TO_QID [14:12] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT100_TO_QID_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT100_TO_QID_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT100_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT011_TO_QID [11:09] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT011_TO_QID_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT011_TO_QID_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT011_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT010_TO_QID [08:06] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT010_TO_QID_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT010_TO_QID_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT010_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT001_TO_QID [05:03] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT001_TO_QID_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT001_TO_QID_SHIFT 3 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT001_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P2 :: PRT000_TO_QID [02:00] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT000_TO_QID_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT000_TO_QID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P2_PRT000_TO_QID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC2COS_MAP_P3 - Port 3 TC to COS Mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC2COS_MAP_P3 :: BCAST_DLF_DROP_TC [31:24] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_BCAST_DLF_DROP_TC_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_BCAST_DLF_DROP_TC_SHIFT 24 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_BCAST_DLF_DROP_TC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT111_TO_QID [23:21] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT111_TO_QID_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT111_TO_QID_SHIFT 21 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT111_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT110_TO_QID [20:18] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT110_TO_QID_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT110_TO_QID_SHIFT 18 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT110_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT101_TO_QID [17:15] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT101_TO_QID_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT101_TO_QID_SHIFT 15 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT101_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT100_TO_QID [14:12] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT100_TO_QID_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT100_TO_QID_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT100_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT011_TO_QID [11:09] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT011_TO_QID_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT011_TO_QID_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT011_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT010_TO_QID [08:06] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT010_TO_QID_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT010_TO_QID_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT010_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT001_TO_QID [05:03] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT001_TO_QID_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT001_TO_QID_SHIFT 3 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT001_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P3 :: PRT000_TO_QID [02:00] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT000_TO_QID_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT000_TO_QID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P3_PRT000_TO_QID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC2COS_MAP_P4 - Port 4 TC to COS Mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC2COS_MAP_P4 :: BCAST_DLF_DROP_TC [31:24] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_BCAST_DLF_DROP_TC_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_BCAST_DLF_DROP_TC_SHIFT 24 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_BCAST_DLF_DROP_TC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT111_TO_QID [23:21] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT111_TO_QID_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT111_TO_QID_SHIFT 21 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT111_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT110_TO_QID [20:18] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT110_TO_QID_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT110_TO_QID_SHIFT 18 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT110_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT101_TO_QID [17:15] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT101_TO_QID_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT101_TO_QID_SHIFT 15 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT101_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT100_TO_QID [14:12] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT100_TO_QID_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT100_TO_QID_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT100_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT011_TO_QID [11:09] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT011_TO_QID_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT011_TO_QID_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT011_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT010_TO_QID [08:06] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT010_TO_QID_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT010_TO_QID_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT010_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT001_TO_QID [05:03] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT001_TO_QID_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT001_TO_QID_SHIFT 3 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT001_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P4 :: PRT000_TO_QID [02:00] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT000_TO_QID_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT000_TO_QID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P4_PRT000_TO_QID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC2COS_MAP_P5 - Port 5 TC to COS Mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC2COS_MAP_P5 :: BCAST_DLF_DROP_TC [31:24] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_BCAST_DLF_DROP_TC_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_BCAST_DLF_DROP_TC_SHIFT 24 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_BCAST_DLF_DROP_TC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT111_TO_QID [23:21] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT111_TO_QID_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT111_TO_QID_SHIFT 21 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT111_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT110_TO_QID [20:18] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT110_TO_QID_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT110_TO_QID_SHIFT 18 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT110_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT101_TO_QID [17:15] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT101_TO_QID_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT101_TO_QID_SHIFT 15 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT101_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT100_TO_QID [14:12] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT100_TO_QID_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT100_TO_QID_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT100_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT011_TO_QID [11:09] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT011_TO_QID_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT011_TO_QID_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT011_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT010_TO_QID [08:06] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT010_TO_QID_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT010_TO_QID_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT010_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT001_TO_QID [05:03] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT001_TO_QID_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT001_TO_QID_SHIFT 3 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT001_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P5 :: PRT000_TO_QID [02:00] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT000_TO_QID_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT000_TO_QID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P5_PRT000_TO_QID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC2COS_MAP_P7 - Port 7 TC to COS Mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC2COS_MAP_P7 :: BCAST_DLF_DROP_TC [31:24] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_BCAST_DLF_DROP_TC_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_BCAST_DLF_DROP_TC_SHIFT 24 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_BCAST_DLF_DROP_TC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT111_TO_QID [23:21] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT111_TO_QID_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT111_TO_QID_SHIFT 21 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT111_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT110_TO_QID [20:18] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT110_TO_QID_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT110_TO_QID_SHIFT 18 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT110_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT101_TO_QID [17:15] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT101_TO_QID_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT101_TO_QID_SHIFT 15 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT101_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT100_TO_QID [14:12] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT100_TO_QID_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT100_TO_QID_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT100_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT011_TO_QID [11:09] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT011_TO_QID_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT011_TO_QID_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT011_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT010_TO_QID [08:06] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT010_TO_QID_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT010_TO_QID_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT010_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT001_TO_QID [05:03] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT001_TO_QID_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT001_TO_QID_SHIFT 3 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT001_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_P7 :: PRT000_TO_QID [02:00] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT000_TO_QID_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT000_TO_QID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_P7_PRT000_TO_QID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC2COS_MAP_IMP - Port 8 TC to COS Mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC2COS_MAP_IMP :: BCAST_DLF_DROP_TC [31:24] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_BCAST_DLF_DROP_TC_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_BCAST_DLF_DROP_TC_SHIFT 24 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_BCAST_DLF_DROP_TC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT111_TO_QID [23:21] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT111_TO_QID_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT111_TO_QID_SHIFT 21 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT111_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT110_TO_QID [20:18] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT110_TO_QID_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT110_TO_QID_SHIFT 18 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT110_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT101_TO_QID [17:15] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT101_TO_QID_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT101_TO_QID_SHIFT 15 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT101_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT100_TO_QID [14:12] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT100_TO_QID_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT100_TO_QID_SHIFT 12 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT100_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT011_TO_QID [11:09] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT011_TO_QID_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT011_TO_QID_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT011_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT010_TO_QID [08:06] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT010_TO_QID_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT010_TO_QID_SHIFT 6 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT010_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT001_TO_QID [05:03] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT001_TO_QID_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT001_TO_QID_SHIFT 3 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT001_TO_QID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COS_MAP_IMP :: PRT000_TO_QID [02:00] */ |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT000_TO_QID_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT000_TO_QID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC2COS_MAP_IMP_PRT000_TO_QID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_REG_SPARE0 :: QOS_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_QOS_REG_SPARE0_QOS_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_QOS_REG_SPARE0_QOS_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_REG_SPARE0_QOS_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_REG_SPARE1 :: QOS_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_QOS_REG_SPARE1_QOS_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_QOS_REG_SPARE1_QOS_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_REG_SPARE1_QOS_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI1_P0 - Port 0 PCP to TC Map for DEI 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI1_P0 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P0 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P0_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI1_P1 - Port 1 PCP to TC Map for DEI 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI1_P1 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P1 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P1_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI1_P2 - Port 2 PCP to TC Map for DEI 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI1_P2 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P2 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P2_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI1_P3 - Port 3 PCP to TC Map for DEI 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI1_P3 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P3 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P3_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI1_P4 - Port 4 PCP to TC Map for DEI 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI1_P4 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P4 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P4_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI1_P5 - Port 5 PCP to TC Map for DEI 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI1_P5 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P5 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P5_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI1_P7 - Port 7 PCP to TC Map for DEI 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI1_P7 :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_P7 :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_P7_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PCP2TC_DEI1_IMP - Port 8 (IMP) PCP to TC Map for DEI 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PCP2TC_DEI1_IMP :: SWITCH_RESV [31:24] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_SWITCH_RESV_MASK 0xff000000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_SWITCH_RESV_SHIFT 24 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG111_PRI_MAP [23:21] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG111_PRI_MAP_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG111_PRI_MAP_SHIFT 21 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG111_PRI_MAP_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG110_PRI_MAP [20:18] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG110_PRI_MAP_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG110_PRI_MAP_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG110_PRI_MAP_DEFAULT 0x00000006 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG101_PRI_MAP [17:15] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG101_PRI_MAP_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG101_PRI_MAP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG101_PRI_MAP_DEFAULT 0x00000005 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG100_PRI_MAP [14:12] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG100_PRI_MAP_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG100_PRI_MAP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG100_PRI_MAP_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG011_PRI_MAP [11:09] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG011_PRI_MAP_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG011_PRI_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG011_PRI_MAP_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG010_PRI_MAP [08:06] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG010_PRI_MAP_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG010_PRI_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG010_PRI_MAP_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG001_PRI_MAP [05:03] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG001_PRI_MAP_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG001_PRI_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG001_PRI_MAP_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PCP2TC_DEI1_IMP :: TAG000_PRI_MAP [02:00] */ |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG000_PRI_MAP_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG000_PRI_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PCP2TC_DEI1_IMP_TAG000_PRI_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VLAN_CTL_P0 - PORT 0 VLAN Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTL_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P0 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P0_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P0_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P0 :: PORT_EGRESS_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P0_PORT_EGRESS_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P0_PORT_EGRESS_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P0_PORT_EGRESS_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *VLAN_CTL_P1 - PORT 1 VLAN Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTL_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P1 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P1_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P1_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P1 :: PORT_EGRESS_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P1_PORT_EGRESS_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P1_PORT_EGRESS_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P1_PORT_EGRESS_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *VLAN_CTL_P2 - PORT 2 VLAN Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTL_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P2 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P2_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P2_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P2 :: PORT_EGRESS_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P2_PORT_EGRESS_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P2_PORT_EGRESS_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P2_PORT_EGRESS_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *VLAN_CTL_P3 - PORT 3 VLAN Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTL_P3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P3 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P3_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P3_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P3 :: PORT_EGRESS_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P3_PORT_EGRESS_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P3_PORT_EGRESS_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P3_PORT_EGRESS_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *VLAN_CTL_P4 - PORT 4 VLAN Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTL_P4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P4 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P4_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P4_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P4 :: PORT_EGRESS_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P4_PORT_EGRESS_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P4_PORT_EGRESS_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P4_PORT_EGRESS_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *VLAN_CTL_P5 - PORT 5 VLAN Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTL_P5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P5 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P5_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P5_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P5 :: PORT_EGRESS_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P5_PORT_EGRESS_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P5_PORT_EGRESS_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P5_PORT_EGRESS_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *VLAN_CTL_P7 - PORT 7 VLAN Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTL_P7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P7 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P7_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P7_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTL_P7 :: PORT_EGRESS_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P7_PORT_EGRESS_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P7_PORT_EGRESS_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_P7_PORT_EGRESS_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *VLAN_CTL_IMP - PORT 8 VLAN Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTL_IMP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_IMP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_IMP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: VLAN_CTL_IMP :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_IMP_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_IMP_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTL_IMP :: PORT_EGRESS_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTL_IMP_PORT_EGRESS_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_VLAN_CTL_IMP_PORT_EGRESS_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTL_IMP_PORT_EGRESS_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *VLAN_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_REG_SPARE0 :: VLAN_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_REG_SPARE0_VLAN_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_VLAN_REG_SPARE0_VLAN_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_REG_SPARE0_VLAN_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VLAN_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_REG_SPARE1 :: VLAN_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_REG_SPARE1_VLAN_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_VLAN_REG_SPARE1_VLAN_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_REG_SPARE1_VLAN_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MAC_TRUNK_CTL - MAC Trunk Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MAC_TRUNK_CTL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: MAC_TRUNK_CTL :: SWITCH_RESV_1 [07:04] */ |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_1_MASK 0x000000f0 |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MAC_TRUNK_CTL :: EN_TRUNK_LOCAL [03:03] */ |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_SHIFT 3 |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MAC_TRUNK_CTL :: SWITCH_RESV_0 [02:02] */ |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_0_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_0_SHIFT 2 |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MAC_TRUNK_CTL :: HASH_SEL [01:00] */ |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_HASH_SEL_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_HASH_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MAC_TRUNK_CTL_HASH_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IMP0_GRP_CTL - IMP0 Group Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IMP0_GRP_CTL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_IMP0_GRP_CTL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_IMP0_GRP_CTL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: IMP0_GRP_CTL :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_IMP0_GRP_CTL_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_IMP0_GRP_CTL_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_IMP0_GRP_CTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IMP0_GRP_CTL :: IMP0_GRP_CTL [08:00] */ |
| #define BCHP_SWITCH_CORE_IMP0_GRP_CTL_IMP0_GRP_CTL_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_IMP0_GRP_CTL_IMP0_GRP_CTL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IMP0_GRP_CTL_IMP0_GRP_CTL_DEFAULT 0x00000100 |
| |
| /*************************************************************************** |
| *TRUNK_GRP_CTL0 - Trunk 0 Group Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TRUNK_GRP_CTL0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TRUNK_GRP_CTL0 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TRUNK_GRP_CTL0 :: EN_TRUNK_GRP [08:00] */ |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_EN_TRUNK_GRP_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_EN_TRUNK_GRP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL0_EN_TRUNK_GRP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TRUNK_GRP_CTL1 - Trunk 1 Group Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TRUNK_GRP_CTL1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TRUNK_GRP_CTL1 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TRUNK_GRP_CTL1 :: EN_TRUNK_GRP [08:00] */ |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_EN_TRUNK_GRP_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_EN_TRUNK_GRP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TRUNK_GRP_CTL1_EN_TRUNK_GRP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TRUNK_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TRUNK_REG_SPARE0 :: TRUNK_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TRUNK_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TRUNK_REG_SPARE1 :: TRUNK_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VLAN_CTRL0 - 802.1Q VLAN Control 0 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTRL0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: VLAN_CTRL0 :: VLAN_EN [07:07] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_EN_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_EN_SHIFT 7 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL0 :: VLAN_LEARN_MODE [06:05] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_LEARN_MODE_MASK 0x00000060 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_LEARN_MODE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_VLAN_LEARN_MODE_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: VLAN_CTRL0 :: SWITCH_RESV_1 [04:04] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_1_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL0 :: CHANGE_1Q_VID [03:03] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1Q_VID_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1Q_VID_SHIFT 3 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1Q_VID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL0 :: SWITCH_RESV_0 [02:02] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_0_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_0_SHIFT 2 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL0 :: CHANGE_1P_VID_OUTER [01:01] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_OUTER_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_OUTER_SHIFT 1 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_OUTER_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: VLAN_CTRL0 :: CHANGE_1P_VID_INNER [00:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_INNER_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_INNER_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL0_CHANGE_1P_VID_INNER_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *VLAN_CTRL1 - 802.1Q VLAN Control 1 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTRL1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_3 [07:07] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_3_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_3_SHIFT 7 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL1 :: EN_IPMC_BYPASS_UNTAG [06:06] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_SHIFT 6 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL1 :: EN_IPMC_BYPASS_FWDMAP [05:05] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_SHIFT 5 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_2 [04:04] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_2_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_2_SHIFT 4 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL1 :: EN_RSV_MCAST_UNTAG [03:03] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_SHIFT 3 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL1 :: EN_RSV_MCAST_FWDMAP [02:02] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_SHIFT 2 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_1 [01:01] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_1_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_1_SHIFT 1 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_1_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: VLAN_CTRL1 :: SWITCH_RESV_0 [00:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_0_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL1_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VLAN_CTRL2 - 802.1Q VLAN Control 2 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTRL2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: VLAN_CTRL2 :: SWITCH_RESV [07:07] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_SHIFT 7 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL2 :: EN_GMRP_GVRP_UNTAG_MAP [06:06] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL2 :: EN_GMRP_GVRP_V_FWDMAP [05:05] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_SHIFT 5 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL2 :: SWITCH_RESV_2 [04:03] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_2_MASK 0x00000018 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_2_SHIFT 3 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_2_DEFAULT 0x00000002 |
| |
| /* SWITCH_CORE :: VLAN_CTRL2 :: EN_MIIM_BYPASS_V_FWDMAP [02:02] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_SHIFT 2 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL2 :: SWITCH_RESV_0 [01:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_0_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL2_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VLAN_CTRL3 - 802.1Q VLAN Control 3 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTRL3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: VLAN_CTRL3 :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL3_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL3_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL3 :: EN_DROP_NON1Q [08:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL3_EN_DROP_NON1Q_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_VLAN_CTRL3_EN_DROP_NON1Q_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL3_EN_DROP_NON1Q_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VLAN_CTRL4 - 802.1Q VLAN Control 4 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTRL4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: VLAN_CTRL4 :: INGR_VID_CHK [07:06] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_INGR_VID_CHK_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_INGR_VID_CHK_SHIFT 6 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_INGR_VID_CHK_DEFAULT 0x00000003 |
| |
| /* SWITCH_CORE :: VLAN_CTRL4 :: EN_MGE_REV_GVRP [05:05] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GVRP_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GVRP_SHIFT 5 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GVRP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL4 :: EN_MGE_REV_GMRP [04:04] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GMRP_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GMRP_SHIFT 4 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_MGE_REV_GMRP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL4 :: EN_DOUBLE_TAG [03:02] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_DOUBLE_TAG_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_DOUBLE_TAG_SHIFT 2 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_EN_DOUBLE_TAG_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL4 :: RESV_MCAST_FLOOD [01:01] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_RESV_MCAST_FLOOD_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_RESV_MCAST_FLOOD_SHIFT 1 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_RESV_MCAST_FLOOD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL4 :: SWITCH_RESV_1 [00:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_SWITCH_RESV_1_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_SWITCH_RESV_1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL4_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VLAN_CTRL5 - 802.1Q VLAN Control 5 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTRL5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: VLAN_CTRL5 :: SWITCH_RESV_2 [07:07] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_2_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_2_SHIFT 7 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL5 :: PRESV_NON1Q [06:06] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_PRESV_NON1Q_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_PRESV_NON1Q_SHIFT 6 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_PRESV_NON1Q_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL5 :: SWITCH_RESV_1 [05:05] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_1_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_1_SHIFT 5 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL5 :: EGRESS_DIR_FRM_BYPASS_TRUNK_EN [04:04] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_SHIFT 4 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: VLAN_CTRL5 :: DROP_VTABLE_MISS [03:03] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_DROP_VTABLE_MISS_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_DROP_VTABLE_MISS_SHIFT 3 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_DROP_VTABLE_MISS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL5 :: EN_VID_FFF_FWD [02:02] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_VID_FFF_FWD_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_VID_FFF_FWD_SHIFT 2 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_VID_FFF_FWD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL5 :: SWITCH_RESV_0 [01:01] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_0_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_0_SHIFT 1 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL5 :: EN_CPU_RX_BYP_INNER_CRCCHK [00:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VLAN_CTRL6 - 802.1Q VLAN Control 6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_CTRL6 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: VLAN_CTRL6 :: SWITCH_RESV_1 [07:05] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_1_MASK 0x000000e0 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_1_SHIFT 5 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL6 :: DIS_ARL_BUST_LMT [04:04] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_DIS_ARL_BUST_LMT_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_DIS_ARL_BUST_LMT_SHIFT 4 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_DIS_ARL_BUST_LMT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL6 :: SWITCH_RESV_0 [03:01] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_0_MASK 0x0000000e |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_0_SHIFT 1 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_CTRL6 :: STRICT_SFD_DETECT [00:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_STRICT_SFD_DETECT_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_STRICT_SFD_DETECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_CTRL6_STRICT_SFD_DETECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VLAN_MULTI_PORT_ADDR_CTL - VLAN Multiport Address Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: SWITCH_RESV [15:12] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_SWITCH_RESV_MASK 0x0000f000 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_SWITCH_RESV_SHIFT 12 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT5_UTG_MAP [11:11] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_MASK 0x00000800 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_SHIFT 11 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT5_V_FWD_MAP [10:10] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_MASK 0x00000400 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_SHIFT 10 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT4_UTG_MAP [09:09] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_MASK 0x00000200 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_SHIFT 9 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT4_V_FWD_MAP [08:08] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_MASK 0x00000100 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_SHIFT 8 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT3_UTG_MAP [07:07] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_SHIFT 7 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT3_V_FWD_MAP [06:06] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT2_UTG_MAP [05:05] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_SHIFT 5 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT2_V_FWD_MAP [04:04] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_SHIFT 4 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT1_UTG_MAP [03:03] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT1_V_FWD_MAP [02:02] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_SHIFT 2 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT0_UTG_MAP [01:01] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_SHIFT 1 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: VLAN_MULTI_PORT_ADDR_CTL :: EN_MPORT0_V_FWD_MAP [00:00] */ |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DEFAULT_1Q_TAG_P0 - Port 0 802.1Q Default Tag Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P0 :: PRI [15:13] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_PRI_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_PRI_SHIFT 13 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_PRI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P0 :: CFI [12:12] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_CFI_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_CFI_SHIFT 12 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_CFI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P0 :: VID [11:00] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_VID_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_VID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P0_VID_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DEFAULT_1Q_TAG_P1 - Port 1 802.1Q Default Tag Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P1 :: PRI [15:13] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_PRI_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_PRI_SHIFT 13 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_PRI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P1 :: CFI [12:12] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_CFI_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_CFI_SHIFT 12 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_CFI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P1 :: VID [11:00] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_VID_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_VID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P1_VID_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DEFAULT_1Q_TAG_P2 - Port 2 802.1Q Default Tag Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P2 :: PRI [15:13] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_PRI_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_PRI_SHIFT 13 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_PRI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P2 :: CFI [12:12] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_CFI_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_CFI_SHIFT 12 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_CFI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P2 :: VID [11:00] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_VID_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_VID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P2_VID_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DEFAULT_1Q_TAG_P3 - Port 3 802.1Q Default Tag Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P3 :: PRI [15:13] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_PRI_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_PRI_SHIFT 13 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_PRI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P3 :: CFI [12:12] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_CFI_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_CFI_SHIFT 12 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_CFI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P3 :: VID [11:00] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_VID_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_VID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P3_VID_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DEFAULT_1Q_TAG_P4 - Port 4 802.1Q Default Tag Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P4 :: PRI [15:13] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_PRI_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_PRI_SHIFT 13 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_PRI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P4 :: CFI [12:12] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_CFI_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_CFI_SHIFT 12 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_CFI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P4 :: VID [11:00] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_VID_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_VID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P4_VID_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DEFAULT_1Q_TAG_P5 - Port 5 802.1Q Default Tag Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P5 :: PRI [15:13] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_PRI_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_PRI_SHIFT 13 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_PRI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P5 :: CFI [12:12] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_CFI_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_CFI_SHIFT 12 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_CFI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P5 :: VID [11:00] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_VID_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_VID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P5_VID_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DEFAULT_1Q_TAG_P7 - Port 7 802.1Q Default Tag Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: PRI [15:13] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_PRI_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_PRI_SHIFT 13 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_PRI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: CFI [12:12] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_CFI_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_CFI_SHIFT 12 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_CFI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_P7 :: VID [11:00] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_VID_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_VID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_P7_VID_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DEFAULT_1Q_TAG_IMP - Port 8 802.1Q Default Tag Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: PRI [15:13] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_PRI_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_PRI_SHIFT 13 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_PRI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: CFI [12:12] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_CFI_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_CFI_SHIFT 12 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_CFI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DEFAULT_1Q_TAG_IMP :: VID [11:00] */ |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_VID_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_VID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DEFAULT_1Q_TAG_IMP_VID_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DTAG_TPID - Double Tagging TPID Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DTAG_TPID :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_DTAG_TPID_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_DTAG_TPID_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: DTAG_TPID :: ISP_TPID [15:00] */ |
| #define BCHP_SWITCH_CORE_DTAG_TPID_ISP_TPID_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_DTAG_TPID_ISP_TPID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DTAG_TPID_ISP_TPID_DEFAULT 0x000088a8 |
| |
| /*************************************************************************** |
| *ISP_SEL_PORTMAP - ISP Port Selection Portmap Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ISP_SEL_PORTMAP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: ISP_SEL_PORTMAP :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ISP_SEL_PORTMAP :: ISP_PORTMAP [08:00] */ |
| #define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_ISP_PORTMAP_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_ISP_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ISP_SEL_PORTMAP_ISP_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_VID_RMK_TBL_ACS - Egress VID Remarking Table Access Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: GLOBAL_WR_EN [31:31] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_SHIFT 31 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: SWITCH_RESV1 [30:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV1_MASK 0x7fff0000 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV1_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: TBL_ADDR [15:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: EGRESS_PORT [07:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_MASK 0x000000f0 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: SWITCH_RESV2 [03:03] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV2_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV2_SHIFT 3 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_SWITCH_RESV2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: RESET_EVT [02:02] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_SHIFT 2 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: OP [01:01] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_OP_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_OP_SHIFT 1 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_OP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_ACS :: START_DONE [00:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_START_DONE_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_START_DONE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS_START_DONE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_VID_RMK_TBL_DATA - Egress VID Remarking Table Data Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: SWITCH_RESV1 [31:30] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV1_MASK 0xc0000000 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: OUTER_OP [29:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_MASK 0x30000000 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: OUTER_VID [27:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_MASK 0x0fff0000 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: SWITCH_RESV2 [15:14] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV2_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV2_SHIFT 14 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_SWITCH_RESV2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: INNER_OP [13:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_OP_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_OP_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_OP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EGRESS_VID_RMK_TBL_DATA :: INNER_VID [11:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_VID_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_VID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA_INNER_VID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *JOIN_ALL_VLAN_EN - Join All VLAN Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: JOIN_ALL_VLAN_EN :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: JOIN_ALL_VLAN_EN :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: JOIN_ALL_VLAN_EN :: JOIN_ALL_VLAN_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_IVL_SVL_CTRL - Port IVL or SVL Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: PORT_IVL_SVL_EN [15:15] */ |
| #define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_SHIFT 15 |
| #define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: SWITCH_RESV [14:09] */ |
| #define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_SWITCH_RESV_MASK 0x00007e00 |
| #define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_IVL_SVL_CTRL :: PORT_IVL_SVL_SEL [08:00] */ |
| #define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BCM8021Q_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BCM8021Q_REG_SPARE0 :: BCM8021Q_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BCM8021Q_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BCM8021Q_REG_SPARE1 :: BCM8021Q_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOS_CTRL - DoS Control RegisterRegister |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DOS_CTRL :: SWITCH_RESV_1 [31:14] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_1_MASK 0xffffc000 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_1_SHIFT 14 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: ICMPV6_LONG_PING_DROP_EN [13:13] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_SHIFT 13 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: ICMPV4_LONG_PING_DROP_EN [12:12] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_SHIFT 12 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: ICMPV6_FRAGMENT_DROP_EN [11:11] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_MASK 0x00000800 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_SHIFT 11 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: ICMPV4_FRAGMENT_DROP_EN [10:10] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_MASK 0x00000400 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_SHIFT 10 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: TCP_FRAG_ERR_DROP_EN [09:09] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_MASK 0x00000200 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_SHIFT 9 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: TCP_SHORT_HDR_DROP_EN [08:08] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_MASK 0x00000100 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_SHIFT 8 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: TCP_SYN_ERR_DROP_EN [07:07] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYN_ERR_DROP_EN_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYN_ERR_DROP_EN_SHIFT 7 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYN_ERR_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: TCP_SYNFIN_SCAN_DROP_EN [06:06] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_SHIFT 6 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: TCP_XMASS_SCAN_DROP_EN [05:05] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_SHIFT 5 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: TCP_NULL_SCAN_DROP_EN [04:04] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_SHIFT 4 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: UDP_BLAT_DROP_EN [03:03] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_UDP_BLAT_DROP_EN_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_UDP_BLAT_DROP_EN_SHIFT 3 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_UDP_BLAT_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: TCP_BLAT_DROP_EN [02:02] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_BLAT_DROP_EN_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_BLAT_DROP_EN_SHIFT 2 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_TCP_BLAT_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: IP_LAND_DROP_EN [01:01] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_IP_LAND_DROP_EN_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_IP_LAND_DROP_EN_SHIFT 1 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_IP_LAND_DROP_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_CTRL :: SWITCH_RESV_0 [00:00] */ |
| #define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_0_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DOS_CTRL_SWITCH_RESV_0_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *MINIMUM_TCP_HDR_SZ - Minimum TCP Header Size Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MINIMUM_TCP_HDR_SZ :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: MINIMUM_TCP_HDR_SZ :: MIN_TCP_HDR_SZ [07:00] */ |
| #define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_DEFAULT 0x00000014 |
| |
| /*************************************************************************** |
| *MAX_ICMPV4_SIZE_REG - Maximum ICMPv4 Size Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MAX_ICMPV4_SIZE_REG :: MAX_ICMPV4_SIZE [31:00] */ |
| #define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_DEFAULT 0x00000200 |
| |
| /*************************************************************************** |
| *MAX_ICMPV6_SIZE_REG - Maximum ICMPv6 Size Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MAX_ICMPV6_SIZE_REG :: MAX_ICMPV6_SIZE [31:00] */ |
| #define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_DEFAULT 0x00000200 |
| |
| /*************************************************************************** |
| *DOS_DIS_LRN_REG - DoS Disable Learn Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DOS_DIS_LRN_REG :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: DOS_DIS_LRN_REG :: SWITCH_RESV [07:01] */ |
| #define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_SWITCH_RESV_MASK 0x000000fe |
| #define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_SWITCH_RESV_SHIFT 1 |
| #define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DOS_DIS_LRN_REG :: DOS_DIS_LRN [00:00] */ |
| #define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_DOS_DIS_LRN_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_DOS_DIS_LRN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DOS_DIS_LRN_REG_DOS_DIS_LRN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOS_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DOS_REG_SPARE0 :: DOS_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_DOS_REG_SPARE0_DOS_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_DOS_REG_SPARE0_DOS_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DOS_REG_SPARE0_DOS_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DOS_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DOS_REG_SPARE1 :: DOS_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_DOS_REG_SPARE1_DOS_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_DOS_REG_SPARE1_DOS_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DOS_REG_SPARE1_DOS_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *JUMBO_PORT_MASK - Jumbo Frame Port Mask Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: JUMBO_PORT_MASK :: SWITCH_RESV_1 [31:25] */ |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_1_MASK 0xfe000000 |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_1_SHIFT 25 |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: JUMBO_PORT_MASK :: EN_10_100_JUMBO [24:24] */ |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_EN_10_100_JUMBO_MASK 0x01000000 |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_EN_10_100_JUMBO_SHIFT 24 |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_EN_10_100_JUMBO_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: JUMBO_PORT_MASK :: SWITCH_RESV_0 [23:09] */ |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_0_MASK 0x00fffe00 |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_0_SHIFT 9 |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: JUMBO_PORT_MASK :: JUMBO_FM_PORT_MASK [08:00] */ |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MIB_GD_FM_MAX_SIZE - Jumbo MIB Good Frame Max Size Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MIB_GD_FM_MAX_SIZE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: MIB_GD_FM_MAX_SIZE :: SWITCH_RESV [15:14] */ |
| #define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_SWITCH_RESV_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_SWITCH_RESV_SHIFT 14 |
| #define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MIB_GD_FM_MAX_SIZE :: MAX_SIZE [13:00] */ |
| #define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_MAX_SIZE_MASK 0x00003fff |
| #define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_MAX_SIZE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MIB_GD_FM_MAX_SIZE_MAX_SIZE_DEFAULT 0x000007d0 |
| |
| /*************************************************************************** |
| *JUMBO_CTRL_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: JUMBO_CTRL_REG_SPARE0 :: JUMBO_CTRL_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *JUMBO_CTRL_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: JUMBO_CTRL_REG_SPARE1 :: JUMBO_CTRL_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *COMM_IRC_CON - Common Ingress rate Control Configuration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: COMM_IRC_CON :: SWITCH_RESV_2 [31:18] */ |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_2_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_2_SHIFT 18 |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: COMM_IRC_CON :: RATE_TYPE1 [17:17] */ |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE1_MASK 0x00020000 |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE1_SHIFT 17 |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: COMM_IRC_CON :: SWITCH_RESV_1 [16:09] */ |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_1_MASK 0x0001fe00 |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_1_SHIFT 9 |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: COMM_IRC_CON :: RATE_TYPE0 [08:08] */ |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE0_MASK 0x00000100 |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE0_SHIFT 8 |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_RATE_TYPE0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: COMM_IRC_CON :: SWITCH_RESV_0 [07:00] */ |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_0_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_COMM_IRC_CON_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IRC_VIRTUAL_ZERO_THD - Ingress Rate Control Virtual Zero Threshold Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IRC_VIRTUAL_ZERO_THD :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: IRC_VIRTUAL_ZERO_THD :: IRC_VIRTUAL_ZERO_THD [15:00] */ |
| #define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_DEFAULT 0x00002fff |
| |
| /*************************************************************************** |
| *IRC_ALARM_THD - Ingress Rate Control Alarm Threshold Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IRC_ALARM_THD :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_IRC_ALARM_THD_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_IRC_ALARM_THD_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: IRC_ALARM_THD :: IRC_ALARM_THD [15:00] */ |
| #define BCHP_SWITCH_CORE_IRC_ALARM_THD_IRC_ALARM_THD_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_IRC_ALARM_THD_IRC_ALARM_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IRC_ALARM_THD_IRC_ALARM_THD_DEFAULT 0x00000bff |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_P0 - Port 0 Receive Rate Control Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: SWITCH_RESV_1 [31:31] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_SWITCH_RESV_1_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_SWITCH_RESV_1_SHIFT 31 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: BUCKET_MODE1 [30:30] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET_MODE1_MASK 0x40000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET_MODE1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET_MODE1_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: BUCKET_MODE0 [29:29] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET_MODE0_MASK 0x20000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET_MODE0_SHIFT 29 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET_MODE0_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: SWITCH_RESV_0 [28:24] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_SWITCH_RESV_0_MASK 0x1f000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_SWITCH_RESV_0_SHIFT 24 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: EN_BUCKET1 [23:23] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_EN_BUCKET1_MASK 0x00800000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_EN_BUCKET1_SHIFT 23 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_EN_BUCKET1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: EN_BUCKET0 [22:22] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_EN_BUCKET0_MASK 0x00400000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_EN_BUCKET0_SHIFT 22 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_EN_BUCKET0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: BUCKET1_SIZE [21:19] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET1_SIZE_MASK 0x00380000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET1_SIZE_SHIFT 19 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET1_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: BUCKET1_REF_CNT [18:11] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET1_REF_CNT_MASK 0x0007f800 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET1_REF_CNT_SHIFT 11 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET1_REF_CNT_DEFAULT 0x00000010 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: BUCKET0_SIZE [10:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET0_SIZE_MASK 0x00000700 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET0_SIZE_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET0_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P0 :: BUCKET0_REF_CNT [07:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET0_REF_CNT_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET0_REF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P0_BUCKET0_REF_CNT_DEFAULT 0x00000010 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_P1 - Port 1 Receive Rate Control Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: SWITCH_RESV_1 [31:31] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_SWITCH_RESV_1_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_SWITCH_RESV_1_SHIFT 31 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: BUCKET_MODE1 [30:30] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET_MODE1_MASK 0x40000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET_MODE1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET_MODE1_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: BUCKET_MODE0 [29:29] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET_MODE0_MASK 0x20000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET_MODE0_SHIFT 29 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET_MODE0_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: SWITCH_RESV_0 [28:24] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_SWITCH_RESV_0_MASK 0x1f000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_SWITCH_RESV_0_SHIFT 24 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: EN_BUCKET1 [23:23] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_EN_BUCKET1_MASK 0x00800000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_EN_BUCKET1_SHIFT 23 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_EN_BUCKET1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: EN_BUCKET0 [22:22] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_EN_BUCKET0_MASK 0x00400000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_EN_BUCKET0_SHIFT 22 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_EN_BUCKET0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: BUCKET1_SIZE [21:19] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET1_SIZE_MASK 0x00380000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET1_SIZE_SHIFT 19 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET1_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: BUCKET1_REF_CNT [18:11] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET1_REF_CNT_MASK 0x0007f800 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET1_REF_CNT_SHIFT 11 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET1_REF_CNT_DEFAULT 0x00000010 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: BUCKET0_SIZE [10:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET0_SIZE_MASK 0x00000700 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET0_SIZE_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET0_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P1 :: BUCKET0_REF_CNT [07:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET0_REF_CNT_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET0_REF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P1_BUCKET0_REF_CNT_DEFAULT 0x00000010 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_P2 - Port 2 Receive Rate Control Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: SWITCH_RESV_1 [31:31] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_SWITCH_RESV_1_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_SWITCH_RESV_1_SHIFT 31 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: BUCKET_MODE1 [30:30] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET_MODE1_MASK 0x40000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET_MODE1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET_MODE1_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: BUCKET_MODE0 [29:29] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET_MODE0_MASK 0x20000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET_MODE0_SHIFT 29 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET_MODE0_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: SWITCH_RESV_0 [28:24] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_SWITCH_RESV_0_MASK 0x1f000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_SWITCH_RESV_0_SHIFT 24 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: EN_BUCKET1 [23:23] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_EN_BUCKET1_MASK 0x00800000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_EN_BUCKET1_SHIFT 23 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_EN_BUCKET1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: EN_BUCKET0 [22:22] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_EN_BUCKET0_MASK 0x00400000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_EN_BUCKET0_SHIFT 22 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_EN_BUCKET0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: BUCKET1_SIZE [21:19] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET1_SIZE_MASK 0x00380000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET1_SIZE_SHIFT 19 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET1_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: BUCKET1_REF_CNT [18:11] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET1_REF_CNT_MASK 0x0007f800 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET1_REF_CNT_SHIFT 11 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET1_REF_CNT_DEFAULT 0x00000010 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: BUCKET0_SIZE [10:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET0_SIZE_MASK 0x00000700 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET0_SIZE_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET0_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P2 :: BUCKET0_REF_CNT [07:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET0_REF_CNT_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET0_REF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P2_BUCKET0_REF_CNT_DEFAULT 0x00000010 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_P3 - Port 3 Receive Rate Control Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: SWITCH_RESV_1 [31:31] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_SWITCH_RESV_1_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_SWITCH_RESV_1_SHIFT 31 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: BUCKET_MODE1 [30:30] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET_MODE1_MASK 0x40000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET_MODE1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET_MODE1_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: BUCKET_MODE0 [29:29] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET_MODE0_MASK 0x20000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET_MODE0_SHIFT 29 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET_MODE0_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: SWITCH_RESV_0 [28:24] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_SWITCH_RESV_0_MASK 0x1f000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_SWITCH_RESV_0_SHIFT 24 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: EN_BUCKET1 [23:23] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_EN_BUCKET1_MASK 0x00800000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_EN_BUCKET1_SHIFT 23 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_EN_BUCKET1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: EN_BUCKET0 [22:22] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_EN_BUCKET0_MASK 0x00400000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_EN_BUCKET0_SHIFT 22 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_EN_BUCKET0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: BUCKET1_SIZE [21:19] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET1_SIZE_MASK 0x00380000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET1_SIZE_SHIFT 19 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET1_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: BUCKET1_REF_CNT [18:11] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET1_REF_CNT_MASK 0x0007f800 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET1_REF_CNT_SHIFT 11 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET1_REF_CNT_DEFAULT 0x00000010 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: BUCKET0_SIZE [10:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET0_SIZE_MASK 0x00000700 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET0_SIZE_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET0_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P3 :: BUCKET0_REF_CNT [07:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET0_REF_CNT_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET0_REF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P3_BUCKET0_REF_CNT_DEFAULT 0x00000010 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_P4 - Port 4 Receive Rate Control Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: SWITCH_RESV_1 [31:31] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_SWITCH_RESV_1_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_SWITCH_RESV_1_SHIFT 31 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: BUCKET_MODE1 [30:30] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET_MODE1_MASK 0x40000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET_MODE1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET_MODE1_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: BUCKET_MODE0 [29:29] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET_MODE0_MASK 0x20000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET_MODE0_SHIFT 29 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET_MODE0_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: SWITCH_RESV_0 [28:24] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_SWITCH_RESV_0_MASK 0x1f000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_SWITCH_RESV_0_SHIFT 24 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: EN_BUCKET1 [23:23] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_EN_BUCKET1_MASK 0x00800000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_EN_BUCKET1_SHIFT 23 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_EN_BUCKET1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: EN_BUCKET0 [22:22] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_EN_BUCKET0_MASK 0x00400000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_EN_BUCKET0_SHIFT 22 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_EN_BUCKET0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: BUCKET1_SIZE [21:19] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET1_SIZE_MASK 0x00380000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET1_SIZE_SHIFT 19 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET1_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: BUCKET1_REF_CNT [18:11] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET1_REF_CNT_MASK 0x0007f800 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET1_REF_CNT_SHIFT 11 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET1_REF_CNT_DEFAULT 0x00000010 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: BUCKET0_SIZE [10:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET0_SIZE_MASK 0x00000700 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET0_SIZE_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET0_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P4 :: BUCKET0_REF_CNT [07:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET0_REF_CNT_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET0_REF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P4_BUCKET0_REF_CNT_DEFAULT 0x00000010 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_P5 - Port 5 Receive Rate Control Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: SWITCH_RESV_1 [31:31] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_SWITCH_RESV_1_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_SWITCH_RESV_1_SHIFT 31 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: BUCKET_MODE1 [30:30] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET_MODE1_MASK 0x40000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET_MODE1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET_MODE1_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: BUCKET_MODE0 [29:29] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET_MODE0_MASK 0x20000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET_MODE0_SHIFT 29 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET_MODE0_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: SWITCH_RESV_0 [28:24] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_SWITCH_RESV_0_MASK 0x1f000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_SWITCH_RESV_0_SHIFT 24 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: EN_BUCKET1 [23:23] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_EN_BUCKET1_MASK 0x00800000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_EN_BUCKET1_SHIFT 23 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_EN_BUCKET1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: EN_BUCKET0 [22:22] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_EN_BUCKET0_MASK 0x00400000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_EN_BUCKET0_SHIFT 22 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_EN_BUCKET0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: BUCKET1_SIZE [21:19] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET1_SIZE_MASK 0x00380000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET1_SIZE_SHIFT 19 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET1_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: BUCKET1_REF_CNT [18:11] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET1_REF_CNT_MASK 0x0007f800 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET1_REF_CNT_SHIFT 11 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET1_REF_CNT_DEFAULT 0x00000010 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: BUCKET0_SIZE [10:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET0_SIZE_MASK 0x00000700 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET0_SIZE_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET0_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P5 :: BUCKET0_REF_CNT [07:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET0_REF_CNT_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET0_REF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P5_BUCKET0_REF_CNT_DEFAULT 0x00000010 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_P7 - Port 7 Receive Rate Control Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: SWITCH_RESV_1 [31:31] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_1_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_1_SHIFT 31 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET_MODE1 [30:30] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE1_MASK 0x40000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE1_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET_MODE0 [29:29] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE0_MASK 0x20000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE0_SHIFT 29 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET_MODE0_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: SWITCH_RESV_0 [28:24] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_0_MASK 0x1f000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_0_SHIFT 24 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: EN_BUCKET1 [23:23] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET1_MASK 0x00800000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET1_SHIFT 23 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: EN_BUCKET0 [22:22] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET0_MASK 0x00400000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET0_SHIFT 22 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_EN_BUCKET0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET1_SIZE [21:19] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_MASK 0x00380000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_SHIFT 19 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET1_REF_CNT [18:11] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_MASK 0x0007f800 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_SHIFT 11 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_DEFAULT 0x00000010 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET0_SIZE [10:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_MASK 0x00000700 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_P7 :: BUCKET0_REF_CNT [07:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_DEFAULT 0x00000010 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_IMP - Port 8 Receive Rate Control Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: SWITCH_RESV_1 [31:31] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_1_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_1_SHIFT 31 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET_MODE1 [30:30] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_MASK 0x40000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_SHIFT 30 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET_MODE0 [29:29] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_MASK 0x20000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_SHIFT 29 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: SWITCH_RESV_0 [28:24] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_0_MASK 0x1f000000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_0_SHIFT 24 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: EN_BUCKET1 [23:23] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET1_MASK 0x00800000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET1_SHIFT 23 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: EN_BUCKET0 [22:22] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET0_MASK 0x00400000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET0_SHIFT 22 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_EN_BUCKET0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET1_SIZE [21:19] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_MASK 0x00380000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_SHIFT 19 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET1_REF_CNT [18:11] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_MASK 0x0007f800 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_SHIFT 11 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_DEFAULT 0x00000010 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET0_SIZE [10:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_MASK 0x00000700 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_IMP :: BUCKET0_REF_CNT [07:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_DEFAULT 0x00000010 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_1_P0 - Port 0 Receive Rate Control 1 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P0 :: IFG_BYTES1 [15:15] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_IFG_BYTES1_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_IFG_BYTES1_SHIFT 15 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_IFG_BYTES1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P0 :: PKT_MSK1 [14:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_PKT_MSK1_MASK 0x00007f00 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_PKT_MSK1_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_PKT_MSK1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P0 :: IFG_BYTES0 [07:07] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_IFG_BYTES0_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_IFG_BYTES0_SHIFT 7 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_IFG_BYTES0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P0 :: PKT_MSK0 [06:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_PKT_MSK0_MASK 0x0000007f |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_PKT_MSK0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P0_PKT_MSK0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_1_P1 - Port 1 Receive Rate Control 1 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P1 :: IFG_BYTES1 [15:15] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_IFG_BYTES1_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_IFG_BYTES1_SHIFT 15 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_IFG_BYTES1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P1 :: PKT_MSK1 [14:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_PKT_MSK1_MASK 0x00007f00 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_PKT_MSK1_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_PKT_MSK1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P1 :: IFG_BYTES0 [07:07] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_IFG_BYTES0_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_IFG_BYTES0_SHIFT 7 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_IFG_BYTES0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P1 :: PKT_MSK0 [06:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_PKT_MSK0_MASK 0x0000007f |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_PKT_MSK0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P1_PKT_MSK0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_1_P2 - Port 2 Receive Rate Control 1 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P2 :: IFG_BYTES1 [15:15] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_IFG_BYTES1_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_IFG_BYTES1_SHIFT 15 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_IFG_BYTES1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P2 :: PKT_MSK1 [14:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_PKT_MSK1_MASK 0x00007f00 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_PKT_MSK1_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_PKT_MSK1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P2 :: IFG_BYTES0 [07:07] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_IFG_BYTES0_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_IFG_BYTES0_SHIFT 7 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_IFG_BYTES0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P2 :: PKT_MSK0 [06:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_PKT_MSK0_MASK 0x0000007f |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_PKT_MSK0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P2_PKT_MSK0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_1_P3 - Port 3 Receive Rate Control 1 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P3 :: IFG_BYTES1 [15:15] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_IFG_BYTES1_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_IFG_BYTES1_SHIFT 15 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_IFG_BYTES1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P3 :: PKT_MSK1 [14:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_PKT_MSK1_MASK 0x00007f00 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_PKT_MSK1_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_PKT_MSK1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P3 :: IFG_BYTES0 [07:07] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_IFG_BYTES0_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_IFG_BYTES0_SHIFT 7 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_IFG_BYTES0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P3 :: PKT_MSK0 [06:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_PKT_MSK0_MASK 0x0000007f |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_PKT_MSK0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P3_PKT_MSK0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_1_P4 - Port 4 Receive Rate Control 1 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P4 :: IFG_BYTES1 [15:15] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_IFG_BYTES1_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_IFG_BYTES1_SHIFT 15 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_IFG_BYTES1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P4 :: PKT_MSK1 [14:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_PKT_MSK1_MASK 0x00007f00 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_PKT_MSK1_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_PKT_MSK1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P4 :: IFG_BYTES0 [07:07] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_IFG_BYTES0_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_IFG_BYTES0_SHIFT 7 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_IFG_BYTES0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P4 :: PKT_MSK0 [06:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_PKT_MSK0_MASK 0x0000007f |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_PKT_MSK0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P4_PKT_MSK0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_1_P5 - Port 5 Receive Rate Control 1 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P5 :: IFG_BYTES1 [15:15] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_IFG_BYTES1_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_IFG_BYTES1_SHIFT 15 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_IFG_BYTES1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P5 :: PKT_MSK1 [14:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_PKT_MSK1_MASK 0x00007f00 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_PKT_MSK1_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_PKT_MSK1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P5 :: IFG_BYTES0 [07:07] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_IFG_BYTES0_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_IFG_BYTES0_SHIFT 7 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_IFG_BYTES0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P5 :: PKT_MSK0 [06:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_PKT_MSK0_MASK 0x0000007f |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_PKT_MSK0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P5_PKT_MSK0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_1_P7 - Port 7 Receive Rate Control 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: IFG_BYTES1 [15:15] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_SHIFT 15 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: PKT_MSK1 [14:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK1_MASK 0x00007f00 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK1_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: IFG_BYTES0 [07:07] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_SHIFT 7 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_P7 :: PKT_MSK0 [06:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK0_MASK 0x0000007f |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_P7_PKT_MSK0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_RATECTRL_1_IMP - Port 8 Receive Rate Control 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: IFG_BYTES1 [15:15] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_SHIFT 15 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: PKT_MSK1 [14:08] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_MASK 0x00007f00 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: IFG_BYTES0 [07:07] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_SHIFT 7 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BC_SUP_RATECTRL_1_IMP :: PKT_MSK0 [06:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_MASK 0x0000007f |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_PKTDROP_CNT_P0 - Port 0 Suppressed Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P0 :: PK_DROP_CNT [31:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P0_PK_DROP_CNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P0_PK_DROP_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P0_PK_DROP_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_PKTDROP_CNT_P1 - Port 1 Suppressed Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P1 :: PK_DROP_CNT [31:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P1_PK_DROP_CNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P1_PK_DROP_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P1_PK_DROP_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_PKTDROP_CNT_P2 - Port 2 Suppressed Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P2 :: PK_DROP_CNT [31:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P2_PK_DROP_CNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P2_PK_DROP_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P2_PK_DROP_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_PKTDROP_CNT_P3 - Port 3 Suppressed Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P3 :: PK_DROP_CNT [31:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P3_PK_DROP_CNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P3_PK_DROP_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P3_PK_DROP_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_PKTDROP_CNT_P4 - Port 4 Suppressed Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P4 :: PK_DROP_CNT [31:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P4_PK_DROP_CNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P4_PK_DROP_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P4_PK_DROP_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_PKTDROP_CNT_P5 - Port 5 Suppressed Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P5 :: PK_DROP_CNT [31:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P5_PK_DROP_CNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P5_PK_DROP_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P5_PK_DROP_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_PKTDROP_CNT_P7 - P7 Suppressed Packet DropCounter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_P7 :: PK_DROP_CNT [31:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUP_PKTDROP_CNT_IMP - Port 8 Suppressed Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUP_PKTDROP_CNT_IMP :: PK_DROP_CNT [31:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUPPRESS_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUPPRESS_REG_SPARE0 :: BC_SUPPRESS_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BC_SUPPRESS_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BC_SUPPRESS_REG_SPARE1 :: BC_SUPPRESS_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EAP_GLO_CON - EAP Global Configuration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EAP_GLO_CON :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: EAP_GLO_CON :: SWITCH_RESV_0 [07:07] */ |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_0_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_0_SHIFT 7 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_GLO_CON :: EN_RARP [06:06] */ |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RARP_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RARP_SHIFT 6 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RARP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_GLO_CON :: EN_BPDU [05:05] */ |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_BPDU_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_BPDU_SHIFT 5 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_BPDU_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_GLO_CON :: EN_RMC [04:04] */ |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RMC_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RMC_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_RMC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_GLO_CON :: EN_DHCP [03:03] */ |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_DHCP_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_DHCP_SHIFT 3 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_DHCP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_GLO_CON :: EN_ARP [02:02] */ |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_ARP_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_ARP_SHIFT 2 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_ARP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_GLO_CON :: EN_2_DIP [01:01] */ |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_2_DIP_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_2_DIP_SHIFT 1 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_EN_2_DIP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_GLO_CON :: SWITCH_RESV [00:00] */ |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EAP_GLO_CON_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EAP_MULTI_ADDR_CTRL - EAP Multiport Address Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: SWITCH_RESV [07:06] */ |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_SWITCH_RESV_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_SWITCH_RESV_SHIFT 6 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT5 [05:05] */ |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT5_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT5_SHIFT 5 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT4 [04:04] */ |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT4_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT4_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT3 [03:03] */ |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT3_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT3_SHIFT 3 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT2 [02:02] */ |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT2_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT2_SHIFT 2 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT1 [01:01] */ |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT1_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT1_SHIFT 1 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EAP_MULTI_ADDR_CTRL :: EN_MPORT0 [00:00] */ |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT0_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EAP_MULTI_ADDR_CTRL_EN_MPORT0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EAP_DIP0 - EAP Destination IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EAP_DIP0 :: DIP_SUB_REG [63:32] */ |
| #define BCHP_SWITCH_CORE_EAP_DIP0_DIP_SUB_REG_MASK 0xffffffff00000000 |
| #define BCHP_SWITCH_CORE_EAP_DIP0_DIP_SUB_REG_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EAP_DIP0_DIP_SUB_REG_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_DIP0 :: DIP_MASK_REG [31:00] */ |
| #define BCHP_SWITCH_CORE_EAP_DIP0_DIP_MASK_REG_MASK 0x00000000ffffffff |
| #define BCHP_SWITCH_CORE_EAP_DIP0_DIP_MASK_REG_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EAP_DIP0_DIP_MASK_REG_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EAP_DIP1 - EAP Destination IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EAP_DIP1 :: DIP_SUB_REG [63:32] */ |
| #define BCHP_SWITCH_CORE_EAP_DIP1_DIP_SUB_REG_MASK 0xffffffff00000000 |
| #define BCHP_SWITCH_CORE_EAP_DIP1_DIP_SUB_REG_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EAP_DIP1_DIP_SUB_REG_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_DIP1 :: DIP_MASK_REG [31:00] */ |
| #define BCHP_SWITCH_CORE_EAP_DIP1_DIP_MASK_REG_MASK 0x00000000ffffffff |
| #define BCHP_SWITCH_CORE_EAP_DIP1_DIP_MASK_REG_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EAP_DIP1_DIP_MASK_REG_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EAP_CON_P0 - Port 0 EAP Configuration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EAP_CON_P0 :: SWITCH_RESV [63:53] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_SWITCH_RESV_MASK 0xffe0000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_SWITCH_RESV_SHIFT 53 |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P0 :: EAP_MODE [52:51] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_MODE_MASK 0x0018000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_MODE_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P0 :: EAP_BLK_MODE [50:49] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_BLK_MODE_MASK 0x0006000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_BLK_MODE_SHIFT 49 |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_BLK_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P0 :: EAP_EN_UNI_DA [48:48] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_EN_UNI_DA_MASK 0x0001000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_EN_UNI_DA_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P0 :: EAP_UNI_DA [47:00] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_UNI_DA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_UNI_DA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EAP_CON_P0_EAP_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EAP_CON_P1 - Port 1 EAP Configuration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EAP_CON_P1 :: SWITCH_RESV [63:53] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_SWITCH_RESV_MASK 0xffe0000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_SWITCH_RESV_SHIFT 53 |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P1 :: EAP_MODE [52:51] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_MODE_MASK 0x0018000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_MODE_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P1 :: EAP_BLK_MODE [50:49] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_BLK_MODE_MASK 0x0006000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_BLK_MODE_SHIFT 49 |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_BLK_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P1 :: EAP_EN_UNI_DA [48:48] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_EN_UNI_DA_MASK 0x0001000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_EN_UNI_DA_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P1 :: EAP_UNI_DA [47:00] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_UNI_DA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_UNI_DA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EAP_CON_P1_EAP_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EAP_CON_P2 - Port 2 EAP Configuration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EAP_CON_P2 :: SWITCH_RESV [63:53] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_SWITCH_RESV_MASK 0xffe0000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_SWITCH_RESV_SHIFT 53 |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P2 :: EAP_MODE [52:51] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_MODE_MASK 0x0018000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_MODE_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P2 :: EAP_BLK_MODE [50:49] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_BLK_MODE_MASK 0x0006000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_BLK_MODE_SHIFT 49 |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_BLK_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P2 :: EAP_EN_UNI_DA [48:48] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_EN_UNI_DA_MASK 0x0001000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_EN_UNI_DA_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P2 :: EAP_UNI_DA [47:00] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_UNI_DA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_UNI_DA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EAP_CON_P2_EAP_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EAP_CON_P3 - Port 3 EAP Configuration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EAP_CON_P3 :: SWITCH_RESV [63:53] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_SWITCH_RESV_MASK 0xffe0000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_SWITCH_RESV_SHIFT 53 |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P3 :: EAP_MODE [52:51] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_MODE_MASK 0x0018000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_MODE_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P3 :: EAP_BLK_MODE [50:49] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_BLK_MODE_MASK 0x0006000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_BLK_MODE_SHIFT 49 |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_BLK_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P3 :: EAP_EN_UNI_DA [48:48] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_EN_UNI_DA_MASK 0x0001000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_EN_UNI_DA_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P3 :: EAP_UNI_DA [47:00] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_UNI_DA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_UNI_DA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EAP_CON_P3_EAP_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EAP_CON_P4 - Port 4 EAP Configuration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EAP_CON_P4 :: SWITCH_RESV [63:53] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_SWITCH_RESV_MASK 0xffe0000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_SWITCH_RESV_SHIFT 53 |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P4 :: EAP_MODE [52:51] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_MODE_MASK 0x0018000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_MODE_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P4 :: EAP_BLK_MODE [50:49] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_BLK_MODE_MASK 0x0006000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_BLK_MODE_SHIFT 49 |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_BLK_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P4 :: EAP_EN_UNI_DA [48:48] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_EN_UNI_DA_MASK 0x0001000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_EN_UNI_DA_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P4 :: EAP_UNI_DA [47:00] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_UNI_DA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_UNI_DA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EAP_CON_P4_EAP_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EAP_CON_P5 - Port 5 EAP Configuration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EAP_CON_P5 :: SWITCH_RESV [63:53] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_SWITCH_RESV_MASK 0xffe0000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_SWITCH_RESV_SHIFT 53 |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P5 :: EAP_MODE [52:51] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_MODE_MASK 0x0018000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_MODE_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P5 :: EAP_BLK_MODE [50:49] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_BLK_MODE_MASK 0x0006000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_BLK_MODE_SHIFT 49 |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_BLK_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P5 :: EAP_EN_UNI_DA [48:48] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_EN_UNI_DA_MASK 0x0001000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_EN_UNI_DA_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P5 :: EAP_UNI_DA [47:00] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_UNI_DA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_UNI_DA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EAP_CON_P5_EAP_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EAP_CON_P7 - Port 7 EAP Configuration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EAP_CON_P7 :: SWITCH_RESV [63:53] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_SWITCH_RESV_MASK 0xffe0000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_SWITCH_RESV_SHIFT 53 |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P7 :: EAP_MODE [52:51] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_MODE_MASK 0x0018000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_MODE_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P7 :: EAP_BLK_MODE [50:49] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_BLK_MODE_MASK 0x0006000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_BLK_MODE_SHIFT 49 |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_BLK_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P7 :: EAP_EN_UNI_DA [48:48] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_EN_UNI_DA_MASK 0x0001000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_EN_UNI_DA_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_P7 :: EAP_UNI_DA [47:00] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_UNI_DA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_UNI_DA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EAP_CON_P7_EAP_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EAP_CON_IMP - IMP EAP Configuration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EAP_CON_IMP :: SWITCH_RESV [63:53] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_SWITCH_RESV_MASK 0xffe0000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_SWITCH_RESV_SHIFT 53 |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_SWITCH_RESV_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_IMP :: EAP_MODE [52:51] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_MODE_MASK 0x0018000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_MODE_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_IMP :: EAP_BLK_MODE [50:49] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_BLK_MODE_MASK 0x0006000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_BLK_MODE_SHIFT 49 |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_BLK_MODE_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_IMP :: EAP_EN_UNI_DA [48:48] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_EN_UNI_DA_MASK 0x0001000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_EN_UNI_DA_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_EN_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EAP_CON_IMP :: EAP_UNI_DA [47:00] */ |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_UNI_DA_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_UNI_DA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EAP_CON_IMP_EAP_UNI_DA_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *IEEE8021X_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IEEE8021X_REG_SPARE0 :: IEEE8021X_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IEEE8021X_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IEEE8021X_REG_SPARE1 :: IEEE8021X_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MST_CON - MST Control Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MST_CON :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_MST_CON_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_MST_CON_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: MST_CON :: SWITCH_RESV [07:01] */ |
| #define BCHP_SWITCH_CORE_MST_CON_SWITCH_RESV_MASK 0x000000fe |
| #define BCHP_SWITCH_CORE_MST_CON_SWITCH_RESV_SHIFT 1 |
| #define BCHP_SWITCH_CORE_MST_CON_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_CON :: EN_802_1S [00:00] */ |
| #define BCHP_SWITCH_CORE_MST_CON_EN_802_1S_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_MST_CON_EN_802_1S_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MST_CON_EN_802_1S_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MST_AGE - MST Ageing Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MST_AGE :: SWITCH_RESV [31:08] */ |
| #define BCHP_SWITCH_CORE_MST_AGE_SWITCH_RESV_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_MST_AGE_SWITCH_RESV_SHIFT 8 |
| #define BCHP_SWITCH_CORE_MST_AGE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_AGE :: AGE_EN_PRT [07:00] */ |
| #define BCHP_SWITCH_CORE_MST_AGE_AGE_EN_PRT_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_MST_AGE_AGE_EN_PRT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MST_AGE_AGE_EN_PRT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MST_TAB0 - MST Table 0 Enable Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MST_TAB0 :: MST_TAB_RSRV [31:27] */ |
| #define BCHP_SWITCH_CORE_MST_TAB0_MST_TAB_RSRV_MASK 0xf8000000 |
| #define BCHP_SWITCH_CORE_MST_TAB0_MST_TAB_RSRV_SHIFT 27 |
| #define BCHP_SWITCH_CORE_MST_TAB0_MST_TAB_RSRV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB0 :: SWITCH_RESV_1 [26:24] */ |
| #define BCHP_SWITCH_CORE_MST_TAB0_SWITCH_RESV_1_MASK 0x07000000 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SWITCH_RESV_1_SHIFT 24 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB0 :: SPT_STA7 [23:21] */ |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA7_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA7_SHIFT 21 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB0 :: SWITCH_RESV_0 [20:18] */ |
| #define BCHP_SWITCH_CORE_MST_TAB0_SWITCH_RESV_0_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SWITCH_RESV_0_SHIFT 18 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB0 :: SPT_STA5 [17:15] */ |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA5_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA5_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB0 :: SPT_STA4 [14:12] */ |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA4_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA4_SHIFT 12 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB0 :: SPT_STA3 [11:09] */ |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA3_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA3_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB0 :: SPT_STA2 [08:06] */ |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA2_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA2_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB0 :: SPT_STA1 [05:03] */ |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA1_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA1_SHIFT 3 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB0 :: SPT_STA0 [02:00] */ |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA0_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MST_TAB0_SPT_STA0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MST_TAB1 - MST Table 1 Enable Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MST_TAB1 :: MST_TAB_RSRV [31:27] */ |
| #define BCHP_SWITCH_CORE_MST_TAB1_MST_TAB_RSRV_MASK 0xf8000000 |
| #define BCHP_SWITCH_CORE_MST_TAB1_MST_TAB_RSRV_SHIFT 27 |
| #define BCHP_SWITCH_CORE_MST_TAB1_MST_TAB_RSRV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB1 :: SWITCH_RESV_1 [26:24] */ |
| #define BCHP_SWITCH_CORE_MST_TAB1_SWITCH_RESV_1_MASK 0x07000000 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SWITCH_RESV_1_SHIFT 24 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB1 :: SPT_STA7 [23:21] */ |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA7_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA7_SHIFT 21 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB1 :: SWITCH_RESV_0 [20:18] */ |
| #define BCHP_SWITCH_CORE_MST_TAB1_SWITCH_RESV_0_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SWITCH_RESV_0_SHIFT 18 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB1 :: SPT_STA5 [17:15] */ |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA5_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA5_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB1 :: SPT_STA4 [14:12] */ |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA4_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA4_SHIFT 12 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB1 :: SPT_STA3 [11:09] */ |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA3_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA3_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB1 :: SPT_STA2 [08:06] */ |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA2_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA2_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB1 :: SPT_STA1 [05:03] */ |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA1_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA1_SHIFT 3 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB1 :: SPT_STA0 [02:00] */ |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA0_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MST_TAB1_SPT_STA0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MST_TAB2 - MST Table 2 Enable Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MST_TAB2 :: MST_TAB_RSRV [31:27] */ |
| #define BCHP_SWITCH_CORE_MST_TAB2_MST_TAB_RSRV_MASK 0xf8000000 |
| #define BCHP_SWITCH_CORE_MST_TAB2_MST_TAB_RSRV_SHIFT 27 |
| #define BCHP_SWITCH_CORE_MST_TAB2_MST_TAB_RSRV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB2 :: SWITCH_RESV_1 [26:24] */ |
| #define BCHP_SWITCH_CORE_MST_TAB2_SWITCH_RESV_1_MASK 0x07000000 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SWITCH_RESV_1_SHIFT 24 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB2 :: SPT_STA7 [23:21] */ |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA7_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA7_SHIFT 21 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB2 :: SWITCH_RESV_0 [20:18] */ |
| #define BCHP_SWITCH_CORE_MST_TAB2_SWITCH_RESV_0_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SWITCH_RESV_0_SHIFT 18 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB2 :: SPT_STA5 [17:15] */ |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA5_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA5_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB2 :: SPT_STA4 [14:12] */ |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA4_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA4_SHIFT 12 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB2 :: SPT_STA3 [11:09] */ |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA3_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA3_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB2 :: SPT_STA2 [08:06] */ |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA2_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA2_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB2 :: SPT_STA1 [05:03] */ |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA1_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA1_SHIFT 3 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB2 :: SPT_STA0 [02:00] */ |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA0_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MST_TAB2_SPT_STA0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MST_TAB3 - MST Table 3 Enable Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MST_TAB3 :: MST_TAB_RSRV [31:27] */ |
| #define BCHP_SWITCH_CORE_MST_TAB3_MST_TAB_RSRV_MASK 0xf8000000 |
| #define BCHP_SWITCH_CORE_MST_TAB3_MST_TAB_RSRV_SHIFT 27 |
| #define BCHP_SWITCH_CORE_MST_TAB3_MST_TAB_RSRV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB3 :: SWITCH_RESV_1 [26:24] */ |
| #define BCHP_SWITCH_CORE_MST_TAB3_SWITCH_RESV_1_MASK 0x07000000 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SWITCH_RESV_1_SHIFT 24 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB3 :: SPT_STA7 [23:21] */ |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA7_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA7_SHIFT 21 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB3 :: SWITCH_RESV_0 [20:18] */ |
| #define BCHP_SWITCH_CORE_MST_TAB3_SWITCH_RESV_0_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SWITCH_RESV_0_SHIFT 18 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB3 :: SPT_STA5 [17:15] */ |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA5_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA5_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB3 :: SPT_STA4 [14:12] */ |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA4_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA4_SHIFT 12 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB3 :: SPT_STA3 [11:09] */ |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA3_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA3_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB3 :: SPT_STA2 [08:06] */ |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA2_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA2_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB3 :: SPT_STA1 [05:03] */ |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA1_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA1_SHIFT 3 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB3 :: SPT_STA0 [02:00] */ |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA0_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MST_TAB3_SPT_STA0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MST_TAB4 - MST Table 4 Enable Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MST_TAB4 :: MST_TAB_RSRV [31:27] */ |
| #define BCHP_SWITCH_CORE_MST_TAB4_MST_TAB_RSRV_MASK 0xf8000000 |
| #define BCHP_SWITCH_CORE_MST_TAB4_MST_TAB_RSRV_SHIFT 27 |
| #define BCHP_SWITCH_CORE_MST_TAB4_MST_TAB_RSRV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB4 :: SWITCH_RESV_1 [26:24] */ |
| #define BCHP_SWITCH_CORE_MST_TAB4_SWITCH_RESV_1_MASK 0x07000000 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SWITCH_RESV_1_SHIFT 24 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB4 :: SPT_STA7 [23:21] */ |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA7_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA7_SHIFT 21 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB4 :: SWITCH_RESV_0 [20:18] */ |
| #define BCHP_SWITCH_CORE_MST_TAB4_SWITCH_RESV_0_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SWITCH_RESV_0_SHIFT 18 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB4 :: SPT_STA5 [17:15] */ |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA5_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA5_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB4 :: SPT_STA4 [14:12] */ |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA4_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA4_SHIFT 12 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB4 :: SPT_STA3 [11:09] */ |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA3_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA3_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB4 :: SPT_STA2 [08:06] */ |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA2_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA2_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB4 :: SPT_STA1 [05:03] */ |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA1_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA1_SHIFT 3 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB4 :: SPT_STA0 [02:00] */ |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA0_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MST_TAB4_SPT_STA0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MST_TAB5 - MST Table 5 Enable Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MST_TAB5 :: MST_TAB_RSRV [31:27] */ |
| #define BCHP_SWITCH_CORE_MST_TAB5_MST_TAB_RSRV_MASK 0xf8000000 |
| #define BCHP_SWITCH_CORE_MST_TAB5_MST_TAB_RSRV_SHIFT 27 |
| #define BCHP_SWITCH_CORE_MST_TAB5_MST_TAB_RSRV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB5 :: SWITCH_RESV_1 [26:24] */ |
| #define BCHP_SWITCH_CORE_MST_TAB5_SWITCH_RESV_1_MASK 0x07000000 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SWITCH_RESV_1_SHIFT 24 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB5 :: SPT_STA7 [23:21] */ |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA7_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA7_SHIFT 21 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB5 :: SWITCH_RESV_0 [20:18] */ |
| #define BCHP_SWITCH_CORE_MST_TAB5_SWITCH_RESV_0_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SWITCH_RESV_0_SHIFT 18 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB5 :: SPT_STA5 [17:15] */ |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA5_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA5_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB5 :: SPT_STA4 [14:12] */ |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA4_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA4_SHIFT 12 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB5 :: SPT_STA3 [11:09] */ |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA3_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA3_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB5 :: SPT_STA2 [08:06] */ |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA2_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA2_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB5 :: SPT_STA1 [05:03] */ |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA1_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA1_SHIFT 3 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB5 :: SPT_STA0 [02:00] */ |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA0_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MST_TAB5_SPT_STA0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MST_TAB6 - MST Table 6 Enable Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MST_TAB6 :: MST_TAB_RSRV [31:27] */ |
| #define BCHP_SWITCH_CORE_MST_TAB6_MST_TAB_RSRV_MASK 0xf8000000 |
| #define BCHP_SWITCH_CORE_MST_TAB6_MST_TAB_RSRV_SHIFT 27 |
| #define BCHP_SWITCH_CORE_MST_TAB6_MST_TAB_RSRV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB6 :: SWITCH_RESV_1 [26:24] */ |
| #define BCHP_SWITCH_CORE_MST_TAB6_SWITCH_RESV_1_MASK 0x07000000 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SWITCH_RESV_1_SHIFT 24 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB6 :: SPT_STA7 [23:21] */ |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA7_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA7_SHIFT 21 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB6 :: SWITCH_RESV_0 [20:18] */ |
| #define BCHP_SWITCH_CORE_MST_TAB6_SWITCH_RESV_0_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SWITCH_RESV_0_SHIFT 18 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB6 :: SPT_STA5 [17:15] */ |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA5_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA5_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB6 :: SPT_STA4 [14:12] */ |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA4_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA4_SHIFT 12 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB6 :: SPT_STA3 [11:09] */ |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA3_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA3_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB6 :: SPT_STA2 [08:06] */ |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA2_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA2_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB6 :: SPT_STA1 [05:03] */ |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA1_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA1_SHIFT 3 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB6 :: SPT_STA0 [02:00] */ |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA0_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MST_TAB6_SPT_STA0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MST_TAB7 - MST Table 7 Enable Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MST_TAB7 :: MST_TAB_RSRV [31:27] */ |
| #define BCHP_SWITCH_CORE_MST_TAB7_MST_TAB_RSRV_MASK 0xf8000000 |
| #define BCHP_SWITCH_CORE_MST_TAB7_MST_TAB_RSRV_SHIFT 27 |
| #define BCHP_SWITCH_CORE_MST_TAB7_MST_TAB_RSRV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB7 :: SWITCH_RESV_1 [26:24] */ |
| #define BCHP_SWITCH_CORE_MST_TAB7_SWITCH_RESV_1_MASK 0x07000000 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SWITCH_RESV_1_SHIFT 24 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB7 :: SPT_STA7 [23:21] */ |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA7_MASK 0x00e00000 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA7_SHIFT 21 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA7_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB7 :: SWITCH_RESV_0 [20:18] */ |
| #define BCHP_SWITCH_CORE_MST_TAB7_SWITCH_RESV_0_MASK 0x001c0000 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SWITCH_RESV_0_SHIFT 18 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB7 :: SPT_STA5 [17:15] */ |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA5_MASK 0x00038000 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA5_SHIFT 15 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA5_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB7 :: SPT_STA4 [14:12] */ |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA4_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA4_SHIFT 12 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA4_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB7 :: SPT_STA3 [11:09] */ |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA3_MASK 0x00000e00 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA3_SHIFT 9 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA3_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB7 :: SPT_STA2 [08:06] */ |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA2_MASK 0x000001c0 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA2_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB7 :: SPT_STA1 [05:03] */ |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA1_MASK 0x00000038 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA1_SHIFT 3 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MST_TAB7 :: SPT_STA0 [02:00] */ |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA0_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MST_TAB7_SPT_STA0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPT_MULTI_ADDR_BPS_CTRL - STP Multiport Address Bypass Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: SWITCH_RESV [15:06] */ |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_SWITCH_RESV_MASK 0x0000ffc0 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_SWITCH_RESV_SHIFT 6 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT5_BYPASS_SPT [05:05] */ |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_SHIFT 5 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT4_BYPASS_SPT [04:04] */ |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_SHIFT 4 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT3_BYPASS_SPT [03:03] */ |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_SHIFT 3 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT2_BYPASS_SPT [02:02] */ |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_SHIFT 2 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT1_BYPASS_SPT [01:01] */ |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_SHIFT 1 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SPT_MULTI_ADDR_BPS_CTRL :: EN_MPORT0_BYPASS_SPT [00:00] */ |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IEEE8021S_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IEEE8021S_REG_SPARE0 :: IEEE8021S_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IEEE8021S_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IEEE8021S_REG_SPARE1 :: IEEE8021S_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_LIMIT_ENABLE - SA Limit Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LIMIT_ENABLE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LIMIT_ENABLE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_ENABLE :: SA_LIMIT_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SA_LIMIT_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SA_LIMIT_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_ENABLE_SA_LIMIT_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_LRN_CNTR_RST - SA Learned Counters Reset Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LRN_CNTR_RST :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_RST :: TOTAL_SA_LRN_CNTR_RST [15:15] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_SHIFT 15 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_RST :: SWITCH_RESV [14:09] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_SWITCH_RESV_MASK 0x00007e00 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_RST :: PORT_SA_LRN_CNTR_RST [08:00] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_OVERLIMIT_CNTR_RST - SA Over Limit Counters Reset Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_OVERLIMIT_CNTR_RST :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_OVERLIMIT_CNTR_RST :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_OVERLIMIT_CNTR_RST :: PORT_SA_OVER_LIMIT_CNTR_RST [08:00] */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TOTAL_SA_LIMIT_CTL - Total SA Limit Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TOTAL_SA_LIMIT_CTL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TOTAL_SA_LIMIT_CTL :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TOTAL_SA_LIMIT_CTL :: TOTAL_SA_LRN_CNT_LIM [12:00] */ |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_DEFAULT 0x00001000 |
| |
| /*************************************************************************** |
| *SA_LIMIT_CTL_P0 - Port 0 SA Limit Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P0 :: OVER_LIMIT_ACTIONS [15:14] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_OVER_LIMIT_ACTIONS_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_OVER_LIMIT_ACTIONS_SHIFT 14 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P0 :: SWITCH_RESV [13:13] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_SWITCH_RESV_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P0 :: SA_LRN_CNT_LIM [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_SA_LRN_CNT_LIM_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_SA_LRN_CNT_LIM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P0_SA_LRN_CNT_LIM_DEFAULT 0x00000400 |
| |
| /*************************************************************************** |
| *SA_LIMIT_CTL_P1 - Port 1 SA Limit Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P1 :: OVER_LIMIT_ACTIONS [15:14] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_OVER_LIMIT_ACTIONS_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_OVER_LIMIT_ACTIONS_SHIFT 14 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P1 :: SWITCH_RESV [13:13] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_SWITCH_RESV_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P1 :: SA_LRN_CNT_LIM [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_SA_LRN_CNT_LIM_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_SA_LRN_CNT_LIM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P1_SA_LRN_CNT_LIM_DEFAULT 0x00000400 |
| |
| /*************************************************************************** |
| *SA_LIMIT_CTL_P2 - Port 2 SA Limit Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P2 :: OVER_LIMIT_ACTIONS [15:14] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_OVER_LIMIT_ACTIONS_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_OVER_LIMIT_ACTIONS_SHIFT 14 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P2 :: SWITCH_RESV [13:13] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_SWITCH_RESV_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P2 :: SA_LRN_CNT_LIM [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_SA_LRN_CNT_LIM_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_SA_LRN_CNT_LIM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P2_SA_LRN_CNT_LIM_DEFAULT 0x00000400 |
| |
| /*************************************************************************** |
| *SA_LIMIT_CTL_P3 - Port 3 SA Limit Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P3 :: OVER_LIMIT_ACTIONS [15:14] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_OVER_LIMIT_ACTIONS_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_OVER_LIMIT_ACTIONS_SHIFT 14 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P3 :: SWITCH_RESV [13:13] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_SWITCH_RESV_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P3 :: SA_LRN_CNT_LIM [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_SA_LRN_CNT_LIM_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_SA_LRN_CNT_LIM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P3_SA_LRN_CNT_LIM_DEFAULT 0x00000400 |
| |
| /*************************************************************************** |
| *SA_LIMIT_CTL_P4 - Port 4 SA Limit Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P4 :: OVER_LIMIT_ACTIONS [15:14] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_OVER_LIMIT_ACTIONS_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_OVER_LIMIT_ACTIONS_SHIFT 14 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P4 :: SWITCH_RESV [13:13] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_SWITCH_RESV_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P4 :: SA_LRN_CNT_LIM [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_SA_LRN_CNT_LIM_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_SA_LRN_CNT_LIM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P4_SA_LRN_CNT_LIM_DEFAULT 0x00000400 |
| |
| /*************************************************************************** |
| *SA_LIMIT_CTL_P5 - Port 5 SA Limit Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P5 :: OVER_LIMIT_ACTIONS [15:14] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_OVER_LIMIT_ACTIONS_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_OVER_LIMIT_ACTIONS_SHIFT 14 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P5 :: SWITCH_RESV [13:13] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_SWITCH_RESV_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P5 :: SA_LRN_CNT_LIM [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_SA_LRN_CNT_LIM_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_SA_LRN_CNT_LIM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P5_SA_LRN_CNT_LIM_DEFAULT 0x00000400 |
| |
| /*************************************************************************** |
| *SA_LIMIT_CTL_P7 - Port 7 SA Limit Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P7 :: OVER_LIMIT_ACTIONS [15:14] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_OVER_LIMIT_ACTIONS_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_OVER_LIMIT_ACTIONS_SHIFT 14 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P7 :: SWITCH_RESV [13:13] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_SWITCH_RESV_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P7 :: SA_LRN_CNT_LIM [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_SA_LRN_CNT_LIM_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_SA_LRN_CNT_LIM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P7_SA_LRN_CNT_LIM_DEFAULT 0x00000400 |
| |
| /*************************************************************************** |
| *SA_LIMIT_CTL_P8 - Port 8 SA Limit Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P8 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P8 :: OVER_LIMIT_ACTIONS [15:14] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_OVER_LIMIT_ACTIONS_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_OVER_LIMIT_ACTIONS_SHIFT 14 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_OVER_LIMIT_ACTIONS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P8 :: SWITCH_RESV [13:13] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_SWITCH_RESV_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LIMIT_CTL_P8 :: SA_LRN_CNT_LIM [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_SA_LRN_CNT_LIM_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_SA_LRN_CNT_LIM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LIMIT_CTL_P8_SA_LRN_CNT_LIM_DEFAULT 0x00000400 |
| |
| /*************************************************************************** |
| *TOTAL_SA_LRN_CNTR - Total SA Learned Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TOTAL_SA_LRN_CNTR :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TOTAL_SA_LRN_CNTR :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TOTAL_SA_LRN_CNTR :: TOTAL_SA_LRN_CNT_NO [12:00] */ |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_LRN_CNTR_P0 - Port 0 SA Learned Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LRN_CNTR_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P0 :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P0 :: SA_LRN_CNT_NO [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_SA_LRN_CNT_NO_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_SA_LRN_CNT_NO_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P0_SA_LRN_CNT_NO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_LRN_CNTR_P1 - Port 1 SA Learned Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LRN_CNTR_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P1 :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P1 :: SA_LRN_CNT_NO [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_SA_LRN_CNT_NO_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_SA_LRN_CNT_NO_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P1_SA_LRN_CNT_NO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_LRN_CNTR_P2 - Port 2 SA Learned Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LRN_CNTR_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P2 :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P2 :: SA_LRN_CNT_NO [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_SA_LRN_CNT_NO_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_SA_LRN_CNT_NO_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P2_SA_LRN_CNT_NO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_LRN_CNTR_P3 - Port 3 SA Learned Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LRN_CNTR_P3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P3 :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P3 :: SA_LRN_CNT_NO [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_SA_LRN_CNT_NO_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_SA_LRN_CNT_NO_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P3_SA_LRN_CNT_NO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_LRN_CNTR_P4 - Port 4 SA Learned Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LRN_CNTR_P4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P4 :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P4 :: SA_LRN_CNT_NO [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_SA_LRN_CNT_NO_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_SA_LRN_CNT_NO_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P4_SA_LRN_CNT_NO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_LRN_CNTR_P5 - Port 5 SA Learned Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LRN_CNTR_P5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P5 :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P5 :: SA_LRN_CNT_NO [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_SA_LRN_CNT_NO_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_SA_LRN_CNT_NO_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P5_SA_LRN_CNT_NO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_LRN_CNTR_P7 - Port 7 SA Learned Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LRN_CNTR_P7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P7 :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P7 :: SA_LRN_CNT_NO [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_SA_LRN_CNT_NO_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_SA_LRN_CNT_NO_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P7_SA_LRN_CNT_NO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_LRN_CNTR_P8 - Port 8 SA Learned Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_LRN_CNTR_P8 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P8 :: SWITCH_RESV [15:13] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_SWITCH_RESV_MASK 0x0000e000 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_LRN_CNTR_P8 :: SA_LRN_CNT_NO [12:00] */ |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_SA_LRN_CNT_NO_MASK 0x00001fff |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_SA_LRN_CNT_NO_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_LRN_CNTR_P8_SA_LRN_CNT_NO_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_OVERLIMIT_CNTR_P0 - Port 0 SA Over Limit Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P0 :: SA_OVER_LIMIT_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P0_SA_OVER_LIMIT_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P0_SA_OVER_LIMIT_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P0_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_OVERLIMIT_CNTR_P1 - Port 1 SA Over Limit Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P1 :: SA_OVER_LIMIT_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P1_SA_OVER_LIMIT_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P1_SA_OVER_LIMIT_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P1_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_OVERLIMIT_CNTR_P2 - Port 2 SA Over Limit Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P2 :: SA_OVER_LIMIT_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P2_SA_OVER_LIMIT_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P2_SA_OVER_LIMIT_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P2_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_OVERLIMIT_CNTR_P3 - Port 3 SA Over Limit Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P3 :: SA_OVER_LIMIT_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P3_SA_OVER_LIMIT_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P3_SA_OVER_LIMIT_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P3_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_OVERLIMIT_CNTR_P4 - Port 4 SA Over Limit Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P4 :: SA_OVER_LIMIT_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P4_SA_OVER_LIMIT_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P4_SA_OVER_LIMIT_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P4_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_OVERLIMIT_CNTR_P5 - Port 5 SA Over Limit Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P5 :: SA_OVER_LIMIT_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P5_SA_OVER_LIMIT_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P5_SA_OVER_LIMIT_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P5_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_OVERLIMIT_CNTR_P7 - Port 7 SA Over Limit Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P7 :: SA_OVER_LIMIT_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P7_SA_OVER_LIMIT_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P7_SA_OVER_LIMIT_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P7_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_OVERLIMIT_CNTR_P8 - Port 8 SA Over Limit Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_OVERLIMIT_CNTR_P8 :: SA_OVER_LIMIT_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P8_SA_OVER_LIMIT_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P8_SA_OVER_LIMIT_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_OVERLIMIT_CNTR_P8_SA_OVER_LIMIT_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SA_OVER_LIMIT_COPY_REDIRECT - SA Over Limit Actions Config Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SA_OVER_LIMIT_COPY_REDIRECT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: SA_OVER_LIMIT_COPY_REDIRECT :: SWITCH_RESV [15:04] */ |
| #define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_SWITCH_RESV_MASK 0x0000fff0 |
| #define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_SWITCH_RESV_SHIFT 4 |
| #define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: SA_OVER_LIMIT_COPY_REDIRECT :: COPY_REDIRECT_PORT_ID [03:00] */ |
| #define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_DEFAULT 0x00000008 |
| |
| /*************************************************************************** |
| *MAC_LIMIT_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MAC_LIMIT_REG_SPARE0 :: MAC_LIMIT_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MAC_LIMIT_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MAC_LIMIT_REG_SPARE1 :: MAC_LIMIT_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_PRI_CTL_P0 - Port 0 QOS Priority Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_PRI_CTL_P0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P0 :: TXQ_EMPTY_STATUS_SELECT [07:07] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_TXQ_EMPTY_STATUS_SELECT_SHIFT 7 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P0 :: SWITCH_RESV [06:06] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_SWITCH_RESV_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_SWITCH_RESV_SHIFT 6 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P0 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P0 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P0 :: WDRR_GRANULARITY [03:03] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_WDRR_GRANULARITY_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_WDRR_GRANULARITY_SHIFT 3 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_WDRR_GRANULARITY_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P0 :: SCHEDULER_SELECT [02:00] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_SCHEDULER_SELECT_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_SCHEDULER_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P0_SCHEDULER_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_PRI_CTL_P1 - Port 1 QOS Priority Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_PRI_CTL_P1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P1 :: TXQ_EMPTY_STATUS_SELECT [07:07] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_TXQ_EMPTY_STATUS_SELECT_SHIFT 7 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P1 :: SWITCH_RESV [06:06] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_SWITCH_RESV_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_SWITCH_RESV_SHIFT 6 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P1 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P1 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P1 :: WDRR_GRANULARITY [03:03] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_WDRR_GRANULARITY_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_WDRR_GRANULARITY_SHIFT 3 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_WDRR_GRANULARITY_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P1 :: SCHEDULER_SELECT [02:00] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_SCHEDULER_SELECT_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_SCHEDULER_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P1_SCHEDULER_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_PRI_CTL_P2 - Port 2 QOS Priority Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_PRI_CTL_P2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P2 :: TXQ_EMPTY_STATUS_SELECT [07:07] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_TXQ_EMPTY_STATUS_SELECT_SHIFT 7 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P2 :: SWITCH_RESV [06:06] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_SWITCH_RESV_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_SWITCH_RESV_SHIFT 6 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P2 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P2 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P2 :: WDRR_GRANULARITY [03:03] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_WDRR_GRANULARITY_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_WDRR_GRANULARITY_SHIFT 3 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_WDRR_GRANULARITY_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P2 :: SCHEDULER_SELECT [02:00] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_SCHEDULER_SELECT_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_SCHEDULER_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P2_SCHEDULER_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_PRI_CTL_P3 - Port 3 QOS Priority Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_PRI_CTL_P3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P3 :: TXQ_EMPTY_STATUS_SELECT [07:07] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_TXQ_EMPTY_STATUS_SELECT_SHIFT 7 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P3 :: SWITCH_RESV [06:06] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_SWITCH_RESV_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_SWITCH_RESV_SHIFT 6 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P3 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P3 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P3 :: WDRR_GRANULARITY [03:03] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_WDRR_GRANULARITY_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_WDRR_GRANULARITY_SHIFT 3 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_WDRR_GRANULARITY_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P3 :: SCHEDULER_SELECT [02:00] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_SCHEDULER_SELECT_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_SCHEDULER_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P3_SCHEDULER_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_PRI_CTL_P4 - Port 4 QOS Priority Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_PRI_CTL_P4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P4 :: TXQ_EMPTY_STATUS_SELECT [07:07] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_TXQ_EMPTY_STATUS_SELECT_SHIFT 7 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P4 :: SWITCH_RESV [06:06] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_SWITCH_RESV_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_SWITCH_RESV_SHIFT 6 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P4 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P4 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P4 :: WDRR_GRANULARITY [03:03] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_WDRR_GRANULARITY_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_WDRR_GRANULARITY_SHIFT 3 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_WDRR_GRANULARITY_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P4 :: SCHEDULER_SELECT [02:00] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_SCHEDULER_SELECT_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_SCHEDULER_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P4_SCHEDULER_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_PRI_CTL_P5 - Port 5 QOS Priority Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_PRI_CTL_P5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P5 :: TXQ_EMPTY_STATUS_SELECT [07:07] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_TXQ_EMPTY_STATUS_SELECT_SHIFT 7 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P5 :: SWITCH_RESV [06:06] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_SWITCH_RESV_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_SWITCH_RESV_SHIFT 6 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P5 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P5 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P5 :: WDRR_GRANULARITY [03:03] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_WDRR_GRANULARITY_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_WDRR_GRANULARITY_SHIFT 3 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_WDRR_GRANULARITY_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P5 :: SCHEDULER_SELECT [02:00] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_SCHEDULER_SELECT_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_SCHEDULER_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P5_SCHEDULER_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_PRI_CTL_P7 - Port 7 QOS Priority Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_PRI_CTL_P7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P7 :: TXQ_EMPTY_STATUS_SELECT [07:07] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_TXQ_EMPTY_STATUS_SELECT_SHIFT 7 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P7 :: SWITCH_RESV [06:06] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_SWITCH_RESV_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_SWITCH_RESV_SHIFT 6 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P7 :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P7 :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P7 :: WDRR_GRANULARITY [03:03] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_WDRR_GRANULARITY_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_WDRR_GRANULARITY_SHIFT 3 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_WDRR_GRANULARITY_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_P7 :: SCHEDULER_SELECT [02:00] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_SCHEDULER_SELECT_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_SCHEDULER_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_P7_SCHEDULER_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_PRI_CTL_IMP - Port 8 QOS Priority Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_PRI_CTL_IMP :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_IMP :: TXQ_EMPTY_STATUS_SELECT [07:07] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_TXQ_EMPTY_STATUS_SELECT_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_TXQ_EMPTY_STATUS_SELECT_SHIFT 7 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_TXQ_EMPTY_STATUS_SELECT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_IMP :: SWITCH_RESV [06:06] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_SWITCH_RESV_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_SWITCH_RESV_SHIFT 6 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_IMP :: NEGATIVE_CREDIT_CLR_DISABLE [05:05] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_NEGATIVE_CREDIT_CLR_DISABLE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_IMP :: ROUNDROBIN_BURST_MODE_ENABLE [04:04] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_ROUNDROBIN_BURST_MODE_ENABLE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_IMP :: WDRR_GRANULARITY [03:03] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_WDRR_GRANULARITY_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_WDRR_GRANULARITY_SHIFT 3 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_WDRR_GRANULARITY_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QOS_PRI_CTL_IMP :: SCHEDULER_SELECT [02:00] */ |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_SCHEDULER_SELECT_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_SCHEDULER_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_PRI_CTL_IMP_SCHEDULER_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QOS_WEIGHT_P0 - Port 0 QOS Weight Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q7_WEIGHT [63:56] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q7_WEIGHT_MASK 0xff00000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q7_WEIGHT_SHIFT 56 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q7_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q6_WEIGHT [55:48] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q6_WEIGHT_MASK 0x00ff000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q6_WEIGHT_SHIFT 48 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q6_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q5_WEIGHT [47:40] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q5_WEIGHT_MASK 0x0000ff0000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q5_WEIGHT_SHIFT 40 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q5_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q4_WEIGHT [39:32] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q4_WEIGHT_MASK 0x000000ff00000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q4_WEIGHT_SHIFT 32 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q4_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q3_WEIGHT [31:24] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q3_WEIGHT_MASK 0x00000000ff000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q3_WEIGHT_SHIFT 24 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q3_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q2_WEIGHT [23:16] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q2_WEIGHT_MASK 0x0000000000ff0000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q2_WEIGHT_SHIFT 16 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q2_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q1_WEIGHT [15:08] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q1_WEIGHT_MASK 0x000000000000ff00 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q1_WEIGHT_SHIFT 8 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q1_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P0 :: Q0_WEIGHT [07:00] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q0_WEIGHT_MASK 0x00000000000000ff |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q0_WEIGHT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P0_Q0_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /*************************************************************************** |
| *QOS_WEIGHT_P1 - Port 1 QOS Weight Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q7_WEIGHT [63:56] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q7_WEIGHT_MASK 0xff00000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q7_WEIGHT_SHIFT 56 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q7_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q6_WEIGHT [55:48] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q6_WEIGHT_MASK 0x00ff000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q6_WEIGHT_SHIFT 48 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q6_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q5_WEIGHT [47:40] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q5_WEIGHT_MASK 0x0000ff0000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q5_WEIGHT_SHIFT 40 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q5_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q4_WEIGHT [39:32] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q4_WEIGHT_MASK 0x000000ff00000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q4_WEIGHT_SHIFT 32 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q4_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q3_WEIGHT [31:24] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q3_WEIGHT_MASK 0x00000000ff000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q3_WEIGHT_SHIFT 24 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q3_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q2_WEIGHT [23:16] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q2_WEIGHT_MASK 0x0000000000ff0000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q2_WEIGHT_SHIFT 16 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q2_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q1_WEIGHT [15:08] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q1_WEIGHT_MASK 0x000000000000ff00 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q1_WEIGHT_SHIFT 8 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q1_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P1 :: Q0_WEIGHT [07:00] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q0_WEIGHT_MASK 0x00000000000000ff |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q0_WEIGHT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P1_Q0_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /*************************************************************************** |
| *QOS_WEIGHT_P2 - Port 2 QOS Weight Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q7_WEIGHT [63:56] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q7_WEIGHT_MASK 0xff00000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q7_WEIGHT_SHIFT 56 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q7_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q6_WEIGHT [55:48] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q6_WEIGHT_MASK 0x00ff000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q6_WEIGHT_SHIFT 48 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q6_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q5_WEIGHT [47:40] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q5_WEIGHT_MASK 0x0000ff0000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q5_WEIGHT_SHIFT 40 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q5_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q4_WEIGHT [39:32] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q4_WEIGHT_MASK 0x000000ff00000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q4_WEIGHT_SHIFT 32 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q4_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q3_WEIGHT [31:24] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q3_WEIGHT_MASK 0x00000000ff000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q3_WEIGHT_SHIFT 24 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q3_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q2_WEIGHT [23:16] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q2_WEIGHT_MASK 0x0000000000ff0000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q2_WEIGHT_SHIFT 16 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q2_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q1_WEIGHT [15:08] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q1_WEIGHT_MASK 0x000000000000ff00 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q1_WEIGHT_SHIFT 8 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q1_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P2 :: Q0_WEIGHT [07:00] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q0_WEIGHT_MASK 0x00000000000000ff |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q0_WEIGHT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P2_Q0_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /*************************************************************************** |
| *QOS_WEIGHT_P3 - Port 3 QOS Weight Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q7_WEIGHT [63:56] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q7_WEIGHT_MASK 0xff00000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q7_WEIGHT_SHIFT 56 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q7_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q6_WEIGHT [55:48] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q6_WEIGHT_MASK 0x00ff000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q6_WEIGHT_SHIFT 48 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q6_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q5_WEIGHT [47:40] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q5_WEIGHT_MASK 0x0000ff0000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q5_WEIGHT_SHIFT 40 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q5_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q4_WEIGHT [39:32] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q4_WEIGHT_MASK 0x000000ff00000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q4_WEIGHT_SHIFT 32 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q4_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q3_WEIGHT [31:24] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q3_WEIGHT_MASK 0x00000000ff000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q3_WEIGHT_SHIFT 24 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q3_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q2_WEIGHT [23:16] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q2_WEIGHT_MASK 0x0000000000ff0000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q2_WEIGHT_SHIFT 16 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q2_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q1_WEIGHT [15:08] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q1_WEIGHT_MASK 0x000000000000ff00 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q1_WEIGHT_SHIFT 8 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q1_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P3 :: Q0_WEIGHT [07:00] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q0_WEIGHT_MASK 0x00000000000000ff |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q0_WEIGHT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P3_Q0_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /*************************************************************************** |
| *QOS_WEIGHT_P4 - Port 4 QOS Weight Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q7_WEIGHT [63:56] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q7_WEIGHT_MASK 0xff00000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q7_WEIGHT_SHIFT 56 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q7_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q6_WEIGHT [55:48] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q6_WEIGHT_MASK 0x00ff000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q6_WEIGHT_SHIFT 48 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q6_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q5_WEIGHT [47:40] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q5_WEIGHT_MASK 0x0000ff0000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q5_WEIGHT_SHIFT 40 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q5_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q4_WEIGHT [39:32] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q4_WEIGHT_MASK 0x000000ff00000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q4_WEIGHT_SHIFT 32 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q4_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q3_WEIGHT [31:24] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q3_WEIGHT_MASK 0x00000000ff000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q3_WEIGHT_SHIFT 24 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q3_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q2_WEIGHT [23:16] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q2_WEIGHT_MASK 0x0000000000ff0000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q2_WEIGHT_SHIFT 16 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q2_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q1_WEIGHT [15:08] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q1_WEIGHT_MASK 0x000000000000ff00 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q1_WEIGHT_SHIFT 8 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q1_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P4 :: Q0_WEIGHT [07:00] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q0_WEIGHT_MASK 0x00000000000000ff |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q0_WEIGHT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P4_Q0_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /*************************************************************************** |
| *QOS_WEIGHT_P5 - Port 5 QOS Weight Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q7_WEIGHT [63:56] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q7_WEIGHT_MASK 0xff00000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q7_WEIGHT_SHIFT 56 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q7_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q6_WEIGHT [55:48] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q6_WEIGHT_MASK 0x00ff000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q6_WEIGHT_SHIFT 48 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q6_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q5_WEIGHT [47:40] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q5_WEIGHT_MASK 0x0000ff0000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q5_WEIGHT_SHIFT 40 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q5_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q4_WEIGHT [39:32] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q4_WEIGHT_MASK 0x000000ff00000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q4_WEIGHT_SHIFT 32 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q4_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q3_WEIGHT [31:24] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q3_WEIGHT_MASK 0x00000000ff000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q3_WEIGHT_SHIFT 24 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q3_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q2_WEIGHT [23:16] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q2_WEIGHT_MASK 0x0000000000ff0000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q2_WEIGHT_SHIFT 16 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q2_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q1_WEIGHT [15:08] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q1_WEIGHT_MASK 0x000000000000ff00 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q1_WEIGHT_SHIFT 8 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q1_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P5 :: Q0_WEIGHT [07:00] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q0_WEIGHT_MASK 0x00000000000000ff |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q0_WEIGHT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P5_Q0_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /*************************************************************************** |
| *QOS_WEIGHT_P7 - Port 7 QOS Weight Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q7_WEIGHT [63:56] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q7_WEIGHT_MASK 0xff00000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q7_WEIGHT_SHIFT 56 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q7_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q6_WEIGHT [55:48] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q6_WEIGHT_MASK 0x00ff000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q6_WEIGHT_SHIFT 48 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q6_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q5_WEIGHT [47:40] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q5_WEIGHT_MASK 0x0000ff0000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q5_WEIGHT_SHIFT 40 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q5_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q4_WEIGHT [39:32] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q4_WEIGHT_MASK 0x000000ff00000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q4_WEIGHT_SHIFT 32 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q4_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q3_WEIGHT [31:24] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q3_WEIGHT_MASK 0x00000000ff000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q3_WEIGHT_SHIFT 24 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q3_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q2_WEIGHT [23:16] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q2_WEIGHT_MASK 0x0000000000ff0000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q2_WEIGHT_SHIFT 16 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q2_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q1_WEIGHT [15:08] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q1_WEIGHT_MASK 0x000000000000ff00 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q1_WEIGHT_SHIFT 8 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q1_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_P7 :: Q0_WEIGHT [07:00] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q0_WEIGHT_MASK 0x00000000000000ff |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q0_WEIGHT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_P7_Q0_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /*************************************************************************** |
| *QOS_WEIGHT_IMP - Port 8 QOS Weight Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q7_WEIGHT [63:56] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q7_WEIGHT_MASK 0xff00000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q7_WEIGHT_SHIFT 56 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q7_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q6_WEIGHT [55:48] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q6_WEIGHT_MASK 0x00ff000000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q6_WEIGHT_SHIFT 48 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q6_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q5_WEIGHT [47:40] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q5_WEIGHT_MASK 0x0000ff0000000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q5_WEIGHT_SHIFT 40 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q5_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q4_WEIGHT [39:32] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q4_WEIGHT_MASK 0x000000ff00000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q4_WEIGHT_SHIFT 32 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q4_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q3_WEIGHT [31:24] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q3_WEIGHT_MASK 0x00000000ff000000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q3_WEIGHT_SHIFT 24 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q3_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q2_WEIGHT [23:16] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q2_WEIGHT_MASK 0x0000000000ff0000 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q2_WEIGHT_SHIFT 16 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q2_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q1_WEIGHT [15:08] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q1_WEIGHT_MASK 0x000000000000ff00 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q1_WEIGHT_SHIFT 8 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q1_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: QOS_WEIGHT_IMP :: Q0_WEIGHT [07:00] */ |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q0_WEIGHT_MASK 0x00000000000000ff |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q0_WEIGHT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QOS_WEIGHT_IMP_Q0_WEIGHT_DEFAULT 0x0000000000000001 |
| |
| /*************************************************************************** |
| *WDRR_PENALTY_P0 - Port 0 WDRR Weight-Scaling Penalty Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WDRR_PENALTY_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P0 :: PEAK_ITERATION_CYCLES [15:08] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_PEAK_ITERATION_CYCLES_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_PEAK_ITERATION_CYCLES_SHIFT 8 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P0 :: PEAK_BACK2BACK_PENALTY [07:00] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_PEAK_BACK2BACK_PENALTY_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P0_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WDRR_PENALTY_P1 - Port 1 WDRR Weight-Scaling Penalty Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WDRR_PENALTY_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P1 :: PEAK_ITERATION_CYCLES [15:08] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_PEAK_ITERATION_CYCLES_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_PEAK_ITERATION_CYCLES_SHIFT 8 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P1 :: PEAK_BACK2BACK_PENALTY [07:00] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_PEAK_BACK2BACK_PENALTY_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P1_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WDRR_PENALTY_P2 - Port 2 WDRR Weight-Scaling Penalty Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WDRR_PENALTY_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P2 :: PEAK_ITERATION_CYCLES [15:08] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_PEAK_ITERATION_CYCLES_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_PEAK_ITERATION_CYCLES_SHIFT 8 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P2 :: PEAK_BACK2BACK_PENALTY [07:00] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_PEAK_BACK2BACK_PENALTY_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P2_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WDRR_PENALTY_P3 - Port 3 WDRR Weight-Scaling Penalty Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WDRR_PENALTY_P3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P3 :: PEAK_ITERATION_CYCLES [15:08] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_PEAK_ITERATION_CYCLES_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_PEAK_ITERATION_CYCLES_SHIFT 8 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P3 :: PEAK_BACK2BACK_PENALTY [07:00] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_PEAK_BACK2BACK_PENALTY_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P3_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WDRR_PENALTY_P4 - Port 4 WDRR Weight-Scaling Penalty Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WDRR_PENALTY_P4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P4 :: PEAK_ITERATION_CYCLES [15:08] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_PEAK_ITERATION_CYCLES_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_PEAK_ITERATION_CYCLES_SHIFT 8 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P4 :: PEAK_BACK2BACK_PENALTY [07:00] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_PEAK_BACK2BACK_PENALTY_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P4_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WDRR_PENALTY_P5 - Port 5 WDRR Weight-Scaling Penalty Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WDRR_PENALTY_P5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P5 :: PEAK_ITERATION_CYCLES [15:08] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_PEAK_ITERATION_CYCLES_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_PEAK_ITERATION_CYCLES_SHIFT 8 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P5 :: PEAK_BACK2BACK_PENALTY [07:00] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_PEAK_BACK2BACK_PENALTY_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P5_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WDRR_PENALTY_P7 - Port 7 WDRR Weight-Scaling Penalty Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WDRR_PENALTY_P7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P7 :: PEAK_ITERATION_CYCLES [15:08] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_PEAK_ITERATION_CYCLES_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_PEAK_ITERATION_CYCLES_SHIFT 8 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: WDRR_PENALTY_P7 :: PEAK_BACK2BACK_PENALTY [07:00] */ |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_PEAK_BACK2BACK_PENALTY_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WDRR_PENALTY_P7_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *P8_WDRR_PENALTY - Port 8 WDRR Weight-Scaling Penalty Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: P8_WDRR_PENALTY :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: P8_WDRR_PENALTY :: PEAK_ITERATION_CYCLES [15:08] */ |
| #define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_SHIFT 8 |
| #define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: P8_WDRR_PENALTY :: PEAK_BACK2BACK_PENALTY [07:00] */ |
| #define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_SHIFT 0 |
| #define BCHP_SWITCH_CORE_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCHEDULER_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SCHEDULER_REG_SPARE0 :: SCHEDULER_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCHEDULER_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: SCHEDULER_REG_SPARE1 :: SCHEDULER_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0 - Port 0 Byte-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1 - Port 1 Byte-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2 - Port 2 Byte-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3 - Port 3 Byte-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4 - Port 4 Byte-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5 - Port 5 Byte-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7 - Port 7 Byte-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP - Port 8 Byte-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0 - Port 0 Byte-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1 - Port 1 Byte-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2 - Port 2 Byte-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3 - Port 3 Byte-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4 - Port 4 Byte-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5 - Port 5 Byte-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7 - Port 7 Byte-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP - Port 8 Byte-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_STS_P0 - Port 0 PORT Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P0_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_STS_P1 - Port 1 PORT Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P1_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_STS_P2 - Port 2 PORT Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P2_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_STS_P3 - Port 3 PORT Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P3_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_STS_P4 - Port 4 PORT Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P4_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_STS_P5 - Port 5 PORT Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P5_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_STS_P7 - Port 7 PORT Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_P7_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_STS_IMP - Port 8 PORT Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0 - Port 0 Packet-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1 - Port 1 Packet-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2 - Port 2 Packet-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3 - Port 3 Packet-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4 - Port 4 Packet-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5 - Port 5 Packet-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7 - Port 7 Packet-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP - Port 8 Packet-Based, Port Shaper Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_CTLREG_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_CTLREG_REG_SPARE0 :: EGRESS_SHAPER_CTLREG_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_CTLREG_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_CTLREG_REG_SPARE1 :: EGRESS_SHAPER_CTLREG_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0 - Port 0 Packet-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1 - Port 1 Packet-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2 - Port 2 Packet-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3 - Port 3 Packet-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4 - Port 4 Packet-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5 - Port 5 Packet-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7 - Port 7 Packet-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP - Port 8 Packet-Based, Port Shaper Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_AVB_SHAPING_MODE - Port Shaper AVB Shaping Mode Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_AVB_SHAPING_MODE :: PORT_SHAPER_AVB_SHAPING_MODE [08:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_ENABLE - Port Shaper Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_ENABLE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_ENABLE :: PORT_SHAPER_ENABLE [08:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BUCKET_COUNT_SELECT - Port Shaper Bucket Count Select Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BUCKET_COUNT_SELECT :: PORT_SHAPER_BUCKET_COUNT_SELECT [08:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PORT_SHAPER_BLOCKING - Port Shaper Blocking Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PORT_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PORT_SHAPER_BLOCKING :: PORT_SHAPER_BLOCKING [08:00] */ |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IFG_BYTES - IFG Correction Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IFG_BYTES :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_IFG_BYTES_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_IFG_BYTES_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: IFG_BYTES :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_IFG_BYTES_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_IFG_BYTES_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_IFG_BYTES_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IFG_BYTES :: IFG_BYTES [08:00] */ |
| #define BCHP_SWITCH_CORE_IFG_BYTES_IFG_BYTES_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_IFG_BYTES_IFG_BYTES_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IFG_BYTES_IFG_BYTES_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_REFRESH_P0 - Port 0 Byte-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_REFRESH_P1 - Port 1 Byte-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_REFRESH_P2 - Port 2 Byte-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_REFRESH_P3 - Port 3 Byte-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_REFRESH_P4 - Port 4 Byte-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_REFRESH_P5 - Port 5 Byte-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_REFRESH_P7 - Port 7 Byte-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_REFRESH_IMP - Port 8 Byte-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_SHAPER_STS_P0 - Port 0 Queue 0 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P0_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_SHAPER_STS_P1 - Port 1 Queue 0 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P1_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_SHAPER_STS_P2 - Port 2 Queue 0 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P2_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_SHAPER_STS_P3 - Port 3 Queue 0 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P3_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_SHAPER_STS_P4 - Port 4 Queue 0 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P4_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_SHAPER_STS_P5 - Port 5 Queue 0 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P5_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_SHAPER_STS_P7 - Port 7 Queue 0 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_P7_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_SHAPER_STS_IMP - Port 8 Queue 0 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 0 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 0 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_AVB_SHAPING_MODE - Queue 0 AVB Shaping Mode Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE0_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_AVB_SHAPING_MODE :: QUEUE0_AVB_SHAPING_MODE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_SHAPER_ENABLE - Queue 0 Shaper Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_ENABLE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_ENABLE :: QUEUE0_SHAPER_ENABLE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_SHAPER_BUCKET_COUNT_SELECT - Queue 0 Bucket Count Select Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: QUEUE0_SHAPER_BUCKET_COUNT_SELECT [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE0_SHAPER_BLOCKING - Queue 0 Shaper Blocking Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE0_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE0_SHAPER_BLOCKING :: QUEUE0_SHAPER_BLOCKING [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_REFRESH_P0 - Port 0 Byte-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_REFRESH_P1 - Port 1 Byte-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_REFRESH_P2 - Port 2 Byte-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_REFRESH_P3 - Port 3 Byte-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_REFRESH_P4 - Port 4 Byte-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_REFRESH_P5 - Port 5 Byte-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_REFRESH_P7 - Port 7 Byte-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_REFRESH_IMP - Port 8 Byte-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_SHAPER_STS_P0 - Port 0 Queue 1 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P0_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_SHAPER_STS_P1 - Port 1 Queue 1 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P1_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_SHAPER_STS_P2 - Port 2 Queue 1 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P2_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_SHAPER_STS_P3 - Port 3 Queue 1 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P3_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_SHAPER_STS_P4 - Port 4 Queue 1 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P4_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_SHAPER_STS_P5 - Port 5 Queue 1 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P5_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_SHAPER_STS_P7 - Port 7 Queue 1 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_P7_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_SHAPER_STS_IMP - Port 8 Queue 1 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 1 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 1 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_AVB_SHAPING_MODE - Queue 1 AVB Shaping Mode Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE1_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_AVB_SHAPING_MODE :: QUEUE1_AVB_SHAPING_MODE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_SHAPER_ENABLE - Queue 1 Shaper Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_ENABLE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_ENABLE :: QUEUE1_SHAPER_ENABLE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_SHAPER_BUCKET_COUNT_SELECT - Queue 1 Bucket Count Select Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: QUEUE1_SHAPER_BUCKET_COUNT_SELECT [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE1_SHAPER_BLOCKING - Queue 1 Shaper Blocking Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE1_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE1_SHAPER_BLOCKING :: QUEUE1_SHAPER_BLOCKING [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_REFRESH_P0 - Port 0 Byte-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_REFRESH_P1 - Port 1 Byte-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_REFRESH_P2 - Port 2 Byte-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_REFRESH_P3 - Port 3 Byte-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_REFRESH_P4 - Port 4 Byte-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_REFRESH_P5 - Port 5 Byte-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_REFRESH_P7 - Port 7 Byte-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_REFRESH_IMP - Port 8 Byte-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_SHAPER_STS_P0 - Port 0 Queue 2 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P0_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_SHAPER_STS_P1 - Port 1 Queue 2 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P1_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_SHAPER_STS_P2 - Port 2 Queue 2 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P2_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_SHAPER_STS_P3 - Port 3 Queue 2 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P3_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_SHAPER_STS_P4 - Port 4 Queue 2 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P4_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_SHAPER_STS_P5 - Port 5 Queue 2 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P5_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_SHAPER_STS_P7 - Port 7 Queue 2 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_P7_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_SHAPER_STS_IMP - Port 8 Queue 2 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 2 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 2 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_AVB_SHAPING_MODE - Queue 2 AVB Shaping Mode Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE2_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_AVB_SHAPING_MODE :: QUEUE2_AVB_SHAPING_MODE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_SHAPER_ENABLE - Queue 2 Shaper Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_ENABLE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_ENABLE :: QUEUE2_SHAPER_ENABLE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_SHAPER_BUCKET_COUNT_SELECT - Queue 2 Bucket Count Select Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: QUEUE2_SHAPER_BUCKET_COUNT_SELECT [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE2_SHAPER_BLOCKING - Queue 2 Shaper Blocking Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE2_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE2_SHAPER_BLOCKING :: QUEUE2_SHAPER_BLOCKING [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_REFRESH_P0 - Port 0 Byte-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_REFRESH_P1 - Port 1 Byte-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_REFRESH_P2 - Port 2 Byte-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_REFRESH_P3 - Port 3 Byte-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_REFRESH_P4 - Port 4 Byte-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_REFRESH_P5 - Port 5 Byte-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_REFRESH_P7 - Port 7 Byte-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_REFRESH_IMP - Port 8 Byte-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_SHAPER_STS_P0 - Port 0 Queue 3 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P0_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_SHAPER_STS_P1 - Port 1 Queue 3 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P1_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_SHAPER_STS_P2 - Port 2 Queue 3 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P2_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_SHAPER_STS_P3 - Port 3 Queue 3 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P3_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_SHAPER_STS_P4 - Port 4 Queue 3 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P4_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_SHAPER_STS_P5 - Port 5 Queue 3 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P5_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_SHAPER_STS_P7 - Port 7 Queue 3 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_P7_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_SHAPER_STS_IMP - Port 8 Queue 3 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 3 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 3 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_AVB_SHAPING_MODE - Queue 3 AVB Shaping Mode Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE3_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_AVB_SHAPING_MODE :: QUEUE3_AVB_SHAPING_MODE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_SHAPER_ENABLE - Queue 3 Shaper Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_ENABLE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_ENABLE :: QUEUE3_SHAPER_ENABLE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_SHAPER_BUCKET_COUNT_SELECT - Queue 3 Bucket Count Select Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: QUEUE3_SHAPER_BUCKET_COUNT_SELECT [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE3_SHAPER_BLOCKING - Queue 3 Shaper Blocking Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE3_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE3_SHAPER_BLOCKING :: QUEUE3_SHAPER_BLOCKING [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_REFRESH_P0 - Port 0 Byte-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_REFRESH_P1 - Port 1 Byte-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_REFRESH_P2 - Port 2 Byte-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_REFRESH_P3 - Port 3 Byte-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_REFRESH_P4 - Port 4 Byte-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_REFRESH_P5 - Port 5 Byte-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_REFRESH_P7 - Port 7 Byte-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_REFRESH_IMP - Port 8 Byte-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_SHAPER_STS_P0 - Port 0 Queue 4 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P0_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_SHAPER_STS_P1 - Port 1 Queue 4 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P1_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_SHAPER_STS_P2 - Port 2 Queue 4 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P2_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_SHAPER_STS_P3 - Port 3 Queue 4 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P3_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_SHAPER_STS_P4 - Port 4 Queue 4 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P4_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_SHAPER_STS_P5 - Port 5 Queue 4 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P5_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_SHAPER_STS_P7 - Port 7 Queue 4 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_P7_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_SHAPER_STS_IMP - Port 8 Queue 4 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 4 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 4 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_AVB_SHAPING_MODE - Queue 4 AVB Shaping Mode Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE4_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_AVB_SHAPING_MODE :: QUEUE4_AVB_SHAPING_MODE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_SHAPER_ENABLE - Queue 4 Shaper Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_ENABLE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_ENABLE :: QUEUE4_SHAPER_ENABLE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_SHAPER_BUCKET_COUNT_SELECT - Queue 4 Bucket Count Select Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: QUEUE4_SHAPER_BUCKET_COUNT_SELECT [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE4_SHAPER_BLOCKING - Queue 4 Shaper Blocking Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE4_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE4_SHAPER_BLOCKING :: QUEUE4_SHAPER_BLOCKING [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_REFRESH_P0 - Port 0 Byte-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_REFRESH_P1 - Port 1 Byte-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_REFRESH_P2 - Port 2 Byte-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_REFRESH_P3 - Port 3 Byte-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_REFRESH_P4 - Port 4 Byte-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_REFRESH_P5 - Port 5 Byte-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_REFRESH_P7 - Port 7 Byte-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_REFRESH_IMP - Port 8 Byte-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_SHAPER_STS_P0 - Port 0 Queue 5 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P0_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_SHAPER_STS_P1 - Port 1 Queue 5 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P1_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_SHAPER_STS_P2 - Port 2 Queue 5 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P2_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_SHAPER_STS_P3 - Port 3 Queue 5 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P3_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_SHAPER_STS_P4 - Port 4 Queue 5 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P4_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_SHAPER_STS_P5 - Port 5 Queue 5 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P5_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_SHAPER_STS_P7 - Port 7 Queue 5 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_P7_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_SHAPER_STS_IMP - Port 8 Queue 5 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 5 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 5 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_AVB_SHAPING_MODE - Queue 5 AVB Shaping Mode Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE5_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_AVB_SHAPING_MODE :: QUEUE5_AVB_SHAPING_MODE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_SHAPER_ENABLE - Queue 5 Shaper Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_ENABLE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_ENABLE :: QUEUE5_SHAPER_ENABLE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_SHAPER_BUCKET_COUNT_SELECT - Queue 5 Bucket Count Select Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: QUEUE5_SHAPER_BUCKET_COUNT_SELECT [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE5_SHAPER_BLOCKING - Queue 5 Shaper Blocking Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE5_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE5_SHAPER_BLOCKING :: QUEUE5_SHAPER_BLOCKING [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_REFRESH_P0 - Port 0 Byte-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_REFRESH_P1 - Port 1 Byte-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_REFRESH_P2 - Port 2 Byte-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_REFRESH_P3 - Port 3 Byte-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_REFRESH_P4 - Port 4 Byte-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_REFRESH_P5 - Port 5 Byte-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_REFRESH_P7 - Port 7 Byte-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_REFRESH_IMP - Port 8 Byte-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_SHAPER_STS_P0 - Port 0 Queue 6 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P0_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_SHAPER_STS_P1 - Port 1 Queue 6 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P1_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_SHAPER_STS_P2 - Port 2 Queue 6 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P2_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_SHAPER_STS_P3 - Port 3 Queue 6 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P3_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_SHAPER_STS_P4 - Port 4 Queue 6 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P4_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_SHAPER_STS_P5 - Port 5 Queue 6 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P5_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_SHAPER_STS_P7 - Port 7 Queue 6 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_P7_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_SHAPER_STS_IMP - Port 8 Queue 6 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 6 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 6 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_AVB_SHAPING_MODE - Queue 6 AVB Shaping Mode Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE6_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_AVB_SHAPING_MODE :: QUEUE6_AVB_SHAPING_MODE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_SHAPER_ENABLE - Queue 6 Shaper Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_ENABLE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_ENABLE :: QUEUE6_SHAPER_ENABLE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_SHAPER_BUCKET_COUNT_SELECT - Queue 6 Bucket Count Select Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: QUEUE6_SHAPER_BUCKET_COUNT_SELECT [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE6_SHAPER_BLOCKING - Queue 6 Shaper Blocking Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE6_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE6_SHAPER_BLOCKING :: QUEUE6_SHAPER_BLOCKING [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_REFRESH_P0 - Port 0 Byte-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_REFRESH_P1 - Port 1 Byte-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_REFRESH_P2 - Port 2 Byte-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_REFRESH_P3 - Port 3 Byte-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_REFRESH_P4 - Port 4 Byte-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_REFRESH_P5 - Port 5 Byte-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_REFRESH_P7 - Port 7 Byte-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_REFRESH_IMP - Port 8 Byte-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_THD_SEL_P0 - Port 0 Byte-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_THD_SEL_P1 - Port 1 Byte-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_THD_SEL_P2 - Port 2 Byte-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_THD_SEL_P3 - Port 3 Byte-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_THD_SEL_P4 - Port 4 Byte-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_THD_SEL_P5 - Port 5 Byte-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_THD_SEL_P7 - Port 7 Byte-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_THD_SEL_IMP - Port 8 Byte-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_SHAPER_STS_P0 - Port 0 Queue 7 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P0 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P0 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P0 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P0_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_SHAPER_STS_P1 - Port 1 Queue 7 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P1 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P1 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P1 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P1_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_SHAPER_STS_P2 - Port 2 Queue 7 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P2 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P2 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P2 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P2_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_SHAPER_STS_P3 - Port 3 Queue 7 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P3 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P3 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P3 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P3_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_SHAPER_STS_P4 - Port 4 Queue 7 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P4 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P4 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P4 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P4_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_SHAPER_STS_P5 - Port 5 Queue 7 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P5 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P5 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P5 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P5_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_SHAPER_STS_P7 - Port 7 Queue 7 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P7 :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P7 :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_P7 :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_P7_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_SHAPER_STS_IMP - Port 8 Queue 7 Shaper Status Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_IMP :: IN_PROFILE_FLAG [31:31] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_IN_PROFILE_FLAG_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_IN_PROFILE_FLAG_SHIFT 31 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_IN_PROFILE_FLAG_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_IMP :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_STS_IMP :: BUCKET_CNT [28:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_BUCKET_CNT_MASK 0x1fffffff |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_BUCKET_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_STS_IMP_BUCKET_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_REFRESH_P0 - Port 0 Packet-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P0 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_REFRESH_P1 - Port 1 Packet-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P1 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_REFRESH_P2 - Port 2 Packet-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P2 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_REFRESH_P3 - Port 3 Packet-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P3 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_REFRESH_P4 - Port 4 Packet-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P4 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_REFRESH_P5 - Port 5 Packet-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P5 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_REFRESH_P7 - Port 7 Packet-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_P7 :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_REFRESH_IMP - Port 8 Packet-based Queue 7 Shaping Rate Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_REFRESH_IMP :: MAX_REFRESH [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP_MAX_REFRESH_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 :: EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_THD_SEL_P0 - Port 0 Packet-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P0 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P0 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_THD_SEL_P1 - Port 1 Packet-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P1 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P1 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_THD_SEL_P2 - Port 2 Packet-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P2 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P2 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_THD_SEL_P3 - Port 3 Packet-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P3 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P3 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_THD_SEL_P4 - Port 4 Packet-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P4 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P4 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_THD_SEL_P5 - Port 5 Packet-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P5 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P5 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_THD_SEL_P7 - Port 7 Packet-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P7 :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_P7 :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_MAX_PACKET_THD_SEL_IMP - Port 8 Packet-based Queue 7 Burst Size Configure Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_IMP :: SWITCH_RESV [31:18] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_MASK 0xfffc0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_SHIFT 18 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_MAX_PACKET_THD_SEL_IMP :: MAX_THD_SEL [17:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_MASK 0x0003ffff |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP_MAX_THD_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_AVB_SHAPING_MODE - Queue 7 AVB Shaping Mode Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_AVB_SHAPING_MODE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE7_AVB_SHAPING_MODE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_AVB_SHAPING_MODE :: QUEUE7_AVB_SHAPING_MODE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_SHAPER_ENABLE - Queue 7 Shaper Enable Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_SHAPER_ENABLE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_ENABLE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_ENABLE :: QUEUE7_SHAPER_ENABLE [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_SHAPER_BUCKET_COUNT_SELECT - Queue 7 Bucket Count Select Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: QUEUE7_SHAPER_BUCKET_COUNT_SELECT [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *QUEUE7_SHAPER_BLOCKING - Queue 7 Shaper Blocking Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: QUEUE7_SHAPER_BLOCKING :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_BLOCKING :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: QUEUE7_SHAPER_BLOCKING :: QUEUE7_SHAPER_BLOCKING [08:00] */ |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_SHIFT 0 |
| #define BCHP_SWITCH_CORE_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MIB_SNAPSHOT_CTL - MIB Snapshot Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SNAPSHOT_STDONE [07:07] */ |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_SHIFT 7 |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SNAPSHOT_MIRROR [06:06] */ |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_SHIFT 6 |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SWITCH_RESV [05:05] */ |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SWITCH_RESV_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SWITCH_RESV_SHIFT 5 |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: RST_MIB_SNAPSHOT_CNT_EN [04:04] */ |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_SHIFT 4 |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: MIB_SNAPSHOT_CTL :: SNAPSHOT_PORT [03:00] */ |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxOctets - Tx Octets |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxOctets :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_S_TxOctets_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_S_TxOctets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxOctets_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *S_TxDropPkts - Tx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxDropPkts :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxDropPkts_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxDropPkts_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxDropPkts_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxQPKTQ0 - Tx Q0 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxQPKTQ0 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ0_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ0_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ0_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxBroadcastPkts - Tx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxBroadcastPkts :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxBroadcastPkts_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxBroadcastPkts_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxBroadcastPkts_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxMulticastPkts - Tx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxMulticastPkts :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxMulticastPkts_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxMulticastPkts_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxMulticastPkts_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxUnicastPkts - Tx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxUnicastPkts :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxUnicastPkts_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxUnicastPkts_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxUnicastPkts_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxCollisions - Tx Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxCollisions :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxCollisions_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxCollisions_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxCollisions_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxSingleCollision - Tx Single Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxSingleCollision :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxSingleCollision_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxSingleCollision_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxSingleCollision_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxMultipleCollision - Tx Multiple collsion Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxMultipleCollision :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxMultipleCollision_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxMultipleCollision_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxMultipleCollision_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxDeferredTransmit - Tx Deferred Transmit Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxDeferredTransmit :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxDeferredTransmit_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxDeferredTransmit_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxDeferredTransmit_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxLateCollision - Tx Late Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxLateCollision :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxLateCollision_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxLateCollision_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxLateCollision_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxExcessiveCollision - Tx Excessive Collision Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxExcessiveCollision :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxExcessiveCollision_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxExcessiveCollision_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxExcessiveCollision_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxFrameInDisc - Tx Fram IN Disc Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxFrameInDisc :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxFrameInDisc_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxFrameInDisc_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxFrameInDisc_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxPausePkts - Tx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxPausePkts :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxPausePkts_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxPausePkts_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxPausePkts_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxQPKTQ1 - Tx Q1 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxQPKTQ1 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ1_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ1_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ1_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxQPKTQ2 - Tx Q2 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxQPKTQ2 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ2_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ2_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ2_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxQPKTQ3 - Tx Q3 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxQPKTQ3 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ3_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ3_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ3_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxQPKTQ4 - Tx Q4 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxQPKTQ4 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ4_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ4_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ4_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxQPKTQ5 - Tx Q5 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxQPKTQ5 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ5_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ5_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ5_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxOctets - Rx Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxOctets :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_S_RxOctets_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_S_RxOctets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxOctets_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *S_RxUndersizePkts - Rx Under Size Packet Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxUndersizePkts :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxUndersizePkts_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxUndersizePkts_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxUndersizePkts_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxPausePkts - Rx Pause Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxPausePkts :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxPausePkts_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxPausePkts_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxPausePkts_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxPkts64Octets - Rx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxPkts64Octets :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxPkts64Octets_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxPkts64Octets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxPkts64Octets_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxPkts65to127Octets - Rx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxPkts65to127Octets :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxPkts65to127Octets_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxPkts65to127Octets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxPkts65to127Octets_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxPkts128to255Octets - Rx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxPkts128to255Octets :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxPkts128to255Octets_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxPkts128to255Octets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxPkts128to255Octets_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxPkts256to511Octets - Rx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxPkts256to511Octets :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxPkts256to511Octets_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxPkts256to511Octets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxPkts256to511Octets_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxPkts512to1023Octets - Rx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxPkts512to1023Octets :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxPkts512to1023Octets_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxPkts1024toMaxPktOctets - Rx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxPkts1024toMaxPktOctets :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxPkts1024toMaxPktOctets_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxOversizePkts - Rx Over Size Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxOversizePkts :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxOversizePkts_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxOversizePkts_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxOversizePkts_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxJabbers - Rx Jabber Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxJabbers :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxJabbers_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxJabbers_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxJabbers_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxAlignmentErrors - Rx Alignment Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxAlignmentErrors :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxAlignmentErrors_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxAlignmentErrors_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxAlignmentErrors_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxFCSErrors - Rx FCS Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxFCSErrors :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxFCSErrors_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxFCSErrors_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxFCSErrors_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxGoodOctets - Rx Good Packet Octet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxGoodOctets :: COUNT [63:00] */ |
| #define BCHP_SWITCH_CORE_S_RxGoodOctets_COUNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_S_RxGoodOctets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxGoodOctets_COUNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *S_RxDropPkts - Rx Drop Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxDropPkts :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxDropPkts_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxDropPkts_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxDropPkts_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxUnicastPkts - Rx Unicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxUnicastPkts :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxUnicastPkts_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxUnicastPkts_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxUnicastPkts_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxMulticastPkts - Rx Multicast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxMulticastPkts :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxMulticastPkts_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxMulticastPkts_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxMulticastPkts_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxBroadcastPkts - Rx Broadcast Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxBroadcastPkts :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxBroadcastPkts_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxBroadcastPkts_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxBroadcastPkts_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxSAChanges - Rx SA Change Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxSAChanges :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxSAChanges_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxSAChanges_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxSAChanges_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxFragments - Rx Fragment Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxFragments :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxFragments_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxFragments_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxFragments_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxJumboPkt - Jumbo Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxJumboPkt :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxJumboPkt_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxJumboPkt_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxJumboPkt_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxSymblErr - Rx Symbol Error Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxSymblErr :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxSymblErr_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxSymblErr_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxSymblErr_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_InRangeErrCount - InRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_InRangeErrCount :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_InRangeErrCount_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_InRangeErrCount_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_InRangeErrCount_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_OutRangeErrCount - OutRangeErrCount Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_OutRangeErrCount :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_OutRangeErrCount_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_OutRangeErrCount_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_OutRangeErrCount_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_EEE_LPI_EVENT - EEE Low-Power Idle Event Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_EEE_LPI_EVENT :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_EEE_LPI_EVENT_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_EEE_LPI_DURATION - EEE Low-Power Idle Duration Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_EEE_LPI_DURATION :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_EEE_LPI_DURATION_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_RxDiscard - Rx Discard Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_RxDiscard :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_RxDiscard_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_RxDiscard_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_RxDiscard_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxQPKTQ6 - Tx Q6 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxQPKTQ6 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ6_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ6_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ6_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxQPKTQ7 - Tx Q7 Packet Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxQPKTQ7 :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ7_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ7_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxQPKTQ7_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxPkts64Octets - Tx 64 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxPkts64Octets :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxPkts64Octets_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxPkts64Octets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxPkts64Octets_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxPkts65to127Octets - Tx 65 to 127 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxPkts65to127Octets :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxPkts65to127Octets_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxPkts65to127Octets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxPkts65to127Octets_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxPkts128to255Octets - Tx 128 to 255 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxPkts128to255Octets :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxPkts128to255Octets_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxPkts128to255Octets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxPkts128to255Octets_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxPkts256to511Octets - Tx 256 to 511 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxPkts256to511Octets :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxPkts256to511Octets_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxPkts256to511Octets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxPkts256to511Octets_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxPkts512to1023Octets - Tx 512 to 1023 Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxPkts512to1023Octets :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxPkts512to1023Octets_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *S_TxPkts1024toMaxPktOctets - Tx 1024 to MaxPkt Bytes Octets Counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: S_TxPkts1024toMaxPktOctets :: COUNT [31:00] */ |
| #define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets_COUNT_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets_COUNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_S_TxPkts1024toMaxPktOctets_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LPDET_CFG - Loop Detection Configuration RegistersNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LPDET_CFG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_LPDET_CFG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: LPDET_CFG :: SWITCH_RESV [15:15] */ |
| #define BCHP_SWITCH_CORE_LPDET_CFG_SWITCH_RESV_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_SWITCH_RESV_SHIFT 15 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LPDET_CFG :: DFQ_SEL2 [14:14] */ |
| #define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL2_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL2_SHIFT 14 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LPDET_CFG :: EN_TXPASS [13:13] */ |
| #define BCHP_SWITCH_CORE_LPDET_CFG_EN_TXPASS_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_EN_TXPASS_SHIFT 13 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_EN_TXPASS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LPDET_CFG :: EN_LPDET [12:12] */ |
| #define BCHP_SWITCH_CORE_LPDET_CFG_EN_LPDET_MASK 0x00001000 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_EN_LPDET_SHIFT 12 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_EN_LPDET_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LPDET_CFG :: LOOP_IMP_SEL [11:11] */ |
| #define BCHP_SWITCH_CORE_LPDET_CFG_LOOP_IMP_SEL_MASK 0x00000800 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_LOOP_IMP_SEL_SHIFT 11 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_LOOP_IMP_SEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LPDET_CFG :: LED_RST_CTL [10:03] */ |
| #define BCHP_SWITCH_CORE_LPDET_CFG_LED_RST_CTL_MASK 0x000007f8 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_LED_RST_CTL_SHIFT 3 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_LED_RST_CTL_DEFAULT 0x00000004 |
| |
| /* SWITCH_CORE :: LPDET_CFG :: OV_PAUSE_ON [02:02] */ |
| #define BCHP_SWITCH_CORE_LPDET_CFG_OV_PAUSE_ON_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_OV_PAUSE_ON_SHIFT 2 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_OV_PAUSE_ON_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: LPDET_CFG :: DFQ_SEL [01:00] */ |
| #define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LPDET_CFG_DFQ_SEL_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *DF_TIMER - Discovery Frame Timer RegistersNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: DF_TIMER :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_DF_TIMER_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_DF_TIMER_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: DF_TIMER :: SWITCH_RESV [07:04] */ |
| #define BCHP_SWITCH_CORE_DF_TIMER_SWITCH_RESV_MASK 0x000000f0 |
| #define BCHP_SWITCH_CORE_DF_TIMER_SWITCH_RESV_SHIFT 4 |
| #define BCHP_SWITCH_CORE_DF_TIMER_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: DF_TIMER :: DF_TIME [03:00] */ |
| #define BCHP_SWITCH_CORE_DF_TIMER_DF_TIME_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_DF_TIMER_DF_TIME_SHIFT 0 |
| #define BCHP_SWITCH_CORE_DF_TIMER_DF_TIME_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LED_PORTMAP - LED Waming Portmap RegistersNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LED_PORTMAP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_LED_PORTMAP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_LED_PORTMAP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: LED_PORTMAP :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_LED_PORTMAP_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_LED_PORTMAP_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_LED_PORTMAP_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: LED_PORTMAP :: LED_WARNING_PORTMAP [08:00] */ |
| #define BCHP_SWITCH_CORE_LED_PORTMAP_LED_WARNING_PORTMAP_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_LED_PORTMAP_LED_WARNING_PORTMAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LED_PORTMAP_LED_WARNING_PORTMAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *MODULE_ID0 - Module ID 0 RegistersNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MODULE_ID0 :: MID_SA [47:00] */ |
| #define BCHP_SWITCH_CORE_MODULE_ID0_MID_SA_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_MODULE_ID0_MID_SA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MODULE_ID0_MID_SA_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *MODULE_ID1 - Module ID 1 RegistersNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: MODULE_ID1 :: MID_AVAIL [47:47] */ |
| #define BCHP_SWITCH_CORE_MODULE_ID1_MID_AVAIL_MASK 0x800000000000 |
| #define BCHP_SWITCH_CORE_MODULE_ID1_MID_AVAIL_SHIFT 47 |
| #define BCHP_SWITCH_CORE_MODULE_ID1_MID_AVAIL_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: MODULE_ID1 :: SWITCH_RESV [46:40] */ |
| #define BCHP_SWITCH_CORE_MODULE_ID1_SWITCH_RESV_MASK 0x7f0000000000 |
| #define BCHP_SWITCH_CORE_MODULE_ID1_SWITCH_RESV_SHIFT 40 |
| #define BCHP_SWITCH_CORE_MODULE_ID1_SWITCH_RESV_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: MODULE_ID1 :: MID_PORTNUM [39:32] */ |
| #define BCHP_SWITCH_CORE_MODULE_ID1_MID_PORTNUM_MASK 0x00ff00000000 |
| #define BCHP_SWITCH_CORE_MODULE_ID1_MID_PORTNUM_SHIFT 32 |
| #define BCHP_SWITCH_CORE_MODULE_ID1_MID_PORTNUM_DEFAULT 0x000000000000 |
| |
| /* SWITCH_CORE :: MODULE_ID1 :: MID_CRC [31:00] */ |
| #define BCHP_SWITCH_CORE_MODULE_ID1_MID_CRC_MASK 0x0000ffffffff |
| #define BCHP_SWITCH_CORE_MODULE_ID1_MID_CRC_SHIFT 0 |
| #define BCHP_SWITCH_CORE_MODULE_ID1_MID_CRC_DEFAULT 0x000000000000 |
| |
| /*************************************************************************** |
| *LPDET_SA - Loop Detect Frame SA RegistersNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LPDET_SA :: LPDET_SA [47:00] */ |
| #define BCHP_SWITCH_CORE_LPDET_SA_LPDET_SA_MASK 0x000000000000 |
| #define BCHP_SWITCH_CORE_LPDET_SA_LPDET_SA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LPDET_SA_LPDET_SA_DEFAULT 0x0180c2000001 |
| |
| /*************************************************************************** |
| *LPDET_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LPDET_REG_SPARE0 :: LPDET_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_LPDET_REG_SPARE0_LPDET_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_LPDET_REG_SPARE0_LPDET_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LPDET_REG_SPARE0_LPDET_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *LPDET_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: LPDET_REG_SPARE1 :: LPDET_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_LPDET_REG_SPARE1_LPDET_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_LPDET_REG_SPARE1_LPDET_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_LPDET_REG_SPARE1_LPDET_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BPM_CTRL - BPM Power Switching Control Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BPM_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_BPM_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: BPM_CTRL :: SWITCH_RESV [07:05] */ |
| #define BCHP_SWITCH_CORE_BPM_CTRL_SWITCH_RESV_MASK 0x000000e0 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_SWITCH_RESV_SHIFT 5 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_CTRL :: RX_PORT_KEEP2PAGE [04:04] */ |
| #define BCHP_SWITCH_CORE_BPM_CTRL_RX_PORT_KEEP2PAGE_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_RX_PORT_KEEP2PAGE_SHIFT 4 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_RX_PORT_KEEP2PAGE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_CTRL :: PDA_CHG_OPT [03:03] */ |
| #define BCHP_SWITCH_CORE_BPM_CTRL_PDA_CHG_OPT_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_PDA_CHG_OPT_SHIFT 3 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_PDA_CHG_OPT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_CTRL :: BFCFIFO_RECYCLE_EN [02:02] */ |
| #define BCHP_SWITCH_CORE_BPM_CTRL_BFCFIFO_RECYCLE_EN_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_BFCFIFO_RECYCLE_EN_SHIFT 2 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_BFCFIFO_RECYCLE_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_CTRL :: PTR_RECYCLE_EN [01:01] */ |
| #define BCHP_SWITCH_CORE_BPM_CTRL_PTR_RECYCLE_EN_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_PTR_RECYCLE_EN_SHIFT 1 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_PTR_RECYCLE_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_CTRL :: PSM_SW_EN [00:00] */ |
| #define BCHP_SWITCH_CORE_BPM_CTRL_PSM_SW_EN_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_PSM_SW_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BPM_CTRL_PSM_SW_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BPM_PSM_OVR_CTRL - BPM Power Switching SW Override Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: PSM_SW_OVERRIDE_EN [07:07] */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_SHIFT 7 |
| #define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: SWITCH_RESV [06:03] */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_SWITCH_RESV_MASK 0x00000078 |
| #define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_SWITCH_RESV_SHIFT 3 |
| #define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_PSM_OVR_CTRL :: PSM_SW_OVERRIDE [02:00] */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BPM_PSM_TIME_CFG - PSM_VDD Timing Parameter Configuration Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BPM_PSM_TIME_CFG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BPM_PSM_TIME_CFG :: DPSM_CNT [15:08] */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_DPSM_CNT_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_DPSM_CNT_SHIFT 8 |
| #define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_DPSM_CNT_DEFAULT 0x00000017 |
| |
| /* SWITCH_CORE :: BPM_PSM_TIME_CFG :: MPSM_CNT [07:00] */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_MPSM_CNT_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_MPSM_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BPM_PSM_TIME_CFG_MPSM_CNT_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *BPM_PSM_THD_CFG - PSM_VDD Switching Threshold Configuration Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BPM_PSM_THD_CFG :: SWITCH_RESV_1 [31:28] */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_1_MASK 0xf0000000 |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_1_SHIFT 28 |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_PSM_THD_CFG :: PSM_ON_THD [27:16] */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_ON_THD_MASK 0x0fff0000 |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_ON_THD_SHIFT 16 |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_ON_THD_DEFAULT 0x00000027 |
| |
| /* SWITCH_CORE :: BPM_PSM_THD_CFG :: SWITCH_RESV_0 [15:12] */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_0_MASK 0x0000f000 |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_0_SHIFT 12 |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_PSM_THD_CFG :: PSM_OFF_THD [11:00] */ |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_OFF_THD_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_OFF_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BPM_PSM_THD_CFG_PSM_OFF_THD_DEFAULT 0x00000050 |
| |
| /*************************************************************************** |
| *ROW_VMASK_OVR_CTRL - BUFCON Row Status Valid Mask SW Override Control Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: OVERRIDE_EN [15:15] */ |
| #define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_SHIFT 15 |
| #define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: SWITCH_RESV [14:12] */ |
| #define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_SWITCH_RESV_MASK 0x00007000 |
| #define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_SWITCH_RESV_SHIFT 12 |
| #define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ROW_VMASK_OVR_CTRL :: OVERRIDE_VAL [11:00] */ |
| #define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_DEFAULT 0x00000fff |
| |
| /*************************************************************************** |
| *BPM_STS - BPM Status Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BPM_STS :: PBB_PWR_STS [31:29] */ |
| #define BCHP_SWITCH_CORE_BPM_STS_PBB_PWR_STS_MASK 0xe0000000 |
| #define BCHP_SWITCH_CORE_BPM_STS_PBB_PWR_STS_SHIFT 29 |
| #define BCHP_SWITCH_CORE_BPM_STS_PBB_PWR_STS_DEFAULT 0x00000007 |
| |
| /* SWITCH_CORE :: BPM_STS :: SWITCH_RESV_1 [28:28] */ |
| #define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_1_MASK 0x10000000 |
| #define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_1_SHIFT 28 |
| #define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_STS :: ROW_USE_STS [27:16] */ |
| #define BCHP_SWITCH_CORE_BPM_STS_ROW_USE_STS_MASK 0x0fff0000 |
| #define BCHP_SWITCH_CORE_BPM_STS_ROW_USE_STS_SHIFT 16 |
| #define BCHP_SWITCH_CORE_BPM_STS_ROW_USE_STS_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: BPM_STS :: SWITCH_RESV_0 [15:14] */ |
| #define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_0_MASK 0x0000c000 |
| #define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_0_SHIFT 14 |
| #define BCHP_SWITCH_CORE_BPM_STS_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_STS :: CUR_PBB [13:12] */ |
| #define BCHP_SWITCH_CORE_BPM_STS_CUR_PBB_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_BPM_STS_CUR_PBB_SHIFT 12 |
| #define BCHP_SWITCH_CORE_BPM_STS_CUR_PBB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_STS :: ROW_VMASK [11:00] */ |
| #define BCHP_SWITCH_CORE_BPM_STS_ROW_VMASK_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_BPM_STS_ROW_VMASK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BPM_STS_ROW_VMASK_DEFAULT 0x00000fff |
| |
| /*************************************************************************** |
| *BPM_PDA_OVR_CTRL - BPM PDA Switching SW Override Control Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: OVERRIDE_EN [15:15] */ |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_EN_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_EN_SHIFT 15 |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: OVERRIDE_DONE [14:14] */ |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_SHIFT 14 |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: SWITCH_RESV [13:12] */ |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_SWITCH_RESV_MASK 0x00003000 |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_SWITCH_RESV_SHIFT 12 |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: BPM_PDA_OVR_CTRL :: OVERRIDE_VAL [11:00] */ |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_MASK 0x00000fff |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PDA_TIMEOUT_CFG - BPM PDA Switching Timeout Counter Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PDA_TIMEOUT_CFG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PDA_TIMEOUT_CFG :: PDA_TIMEOUT_CNT [15:00] */ |
| #define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_DEFAULT 0x00000100 |
| |
| /*************************************************************************** |
| *PDA_SETUP_TIME_CFG - BPM PDA Switching Setup Time Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PDA_SETUP_TIME_CFG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PDA_SETUP_TIME_CFG :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PDA_SETUP_TIME_CFG :: SETUP_TIME [10:00] */ |
| #define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SETUP_TIME_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SETUP_TIME_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PDA_SETUP_TIME_CFG_SETUP_TIME_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PDA_HOLD_TIME_CFG - BPM PDA Switching Hold Time Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PDA_HOLD_TIME_CFG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PDA_HOLD_TIME_CFG :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PDA_HOLD_TIME_CFG :: HOLD_TIME [10:00] */ |
| #define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_HOLD_TIME_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_HOLD_TIME_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PDA_HOLD_TIME_CFG_HOLD_TIME_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PBB_VBUFCNT_P0 - Packet Buffer Block 0 Valid Buffer Count Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PBB_VBUFCNT_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PBB_VBUFCNT_P0 :: SWITCH_RESV [15:10] */ |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_SWITCH_RESV_MASK 0x0000fc00 |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_SWITCH_RESV_SHIFT 10 |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PBB_VBUFCNT_P0 :: VALID_BUF_CNT [09:00] */ |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_VALID_BUF_CNT_MASK 0x000003ff |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_VALID_BUF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P0_VALID_BUF_CNT_DEFAULT 0x00000200 |
| |
| /*************************************************************************** |
| *PBB_VBUFCNT_P1 - Packet Buffer Block 1 Valid Buffer Count Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PBB_VBUFCNT_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PBB_VBUFCNT_P1 :: SWITCH_RESV [15:10] */ |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_SWITCH_RESV_MASK 0x0000fc00 |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_SWITCH_RESV_SHIFT 10 |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PBB_VBUFCNT_P1 :: VALID_BUF_CNT [09:00] */ |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_VALID_BUF_CNT_MASK 0x000003ff |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_VALID_BUF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P1_VALID_BUF_CNT_DEFAULT 0x00000200 |
| |
| /*************************************************************************** |
| *PBB_VBUFCNT_P2 - Packet Buffer Block 2 Valid Buffer Count Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PBB_VBUFCNT_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PBB_VBUFCNT_P2 :: SWITCH_RESV [15:10] */ |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_SWITCH_RESV_MASK 0x0000fc00 |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_SWITCH_RESV_SHIFT 10 |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PBB_VBUFCNT_P2 :: VALID_BUF_CNT [09:00] */ |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_VALID_BUF_CNT_MASK 0x000003ff |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_VALID_BUF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PBB_VBUFCNT_P2_VALID_BUF_CNT_DEFAULT 0x00000200 |
| |
| /*************************************************************************** |
| *RCY_TIME_CFG - Recycling Check Pulse Period Counter Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RCY_TIME_CFG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_RCY_TIME_CFG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_RCY_TIME_CFG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: RCY_TIME_CFG :: CHK_TIME [15:00] */ |
| #define BCHP_SWITCH_CORE_RCY_TIME_CFG_CHK_TIME_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_RCY_TIME_CFG_CHK_TIME_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RCY_TIME_CFG_CHK_TIME_DEFAULT 0x00000020 |
| |
| /*************************************************************************** |
| *PBB_PWRDWN_MON_CTRL - PBB Powerdown Monitor Control Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_PERIOD [15:08] */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_PERIOD_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_PERIOD_SHIFT 8 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_PERIOD_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_TIME_UNIT [07:03] */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_MASK 0x000000f8 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_SHIFT 3 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_DONE [02:02] */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_DONE_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_DONE_SHIFT 2 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_DONE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_CLR [01:01] */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_CLR_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_CLR_SHIFT 1 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_CLR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: PBB_PWRDWN_MON_CTRL :: MON_EN [00:00] */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_EN_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON_CTRL_MON_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PBB_PWRDWN_MON0 - PBB Powerdown Time Monitor 0 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PBB_PWRDWN_MON0 :: PWRDWN_CNT [63:00] */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON0_PWRDWN_CNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON0_PWRDWN_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON0_PWRDWN_CNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *PBB_PWRDWN_MON1 - PBB Powerdown Time Monitor 1 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PBB_PWRDWN_MON1 :: PWRDWN_CNT [63:00] */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON1_PWRDWN_CNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON1_PWRDWN_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON1_PWRDWN_CNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *PBB_PWRDWN_MON2 - PBB Powerdown Time Monitor 2 Register Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: PBB_PWRDWN_MON2 :: PWRDWN_CNT [63:00] */ |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON2_PWRDWN_CNT_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON2_PWRDWN_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_PBB_PWRDWN_MON2_PWRDWN_CNT_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *BPM_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BPM_REG_SPARE0 :: BPM_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_BPM_REG_SPARE0_BPM_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BPM_REG_SPARE0_BPM_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BPM_REG_SPARE0_BPM_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BPM_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: BPM_REG_SPARE1 :: BPM_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_BPM_REG_SPARE1_BPM_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_BPM_REG_SPARE1_BPM_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_BPM_REG_SPARE1_BPM_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TRREG_CTRL0 - Traffic Remarking Control 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TRREG_CTRL0 :: SWITCH_RESV_1 [31:25] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_1_MASK 0xfe000000 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_1_SHIFT 25 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TRREG_CTRL0 :: PCP_RMK_EN [24:16] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0_PCP_RMK_EN_MASK 0x01ff0000 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0_PCP_RMK_EN_SHIFT 16 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0_PCP_RMK_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TRREG_CTRL0 :: SWITCH_RESV_0 [15:09] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_0_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_0_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TRREG_CTRL0 :: CFI_RMK_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0_CFI_RMK_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0_CFI_RMK_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL0_CFI_RMK_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TRREG_CTRL1 - Traffic Remarking Control 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TRREG_CTRL1 :: SWITCH_RESV_1 [31:25] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_1_MASK 0xfe000000 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_1_SHIFT 25 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TRREG_CTRL1 :: DEI_RMK_EN [24:16] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_DEI_RMK_EN_MASK 0x01ff0000 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_DEI_RMK_EN_SHIFT 16 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_DEI_RMK_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TRREG_CTRL1 :: PPPOE_DSCP_RMK_EN [15:15] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_SHIFT 15 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TRREG_CTRL1 :: SWITCH_RESV_0 [14:09] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_0_MASK 0x00007e00 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_0_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TRREG_CTRL1 :: DSCP_RMK_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_DSCP_RMK_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_DSCP_RMK_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL1_DSCP_RMK_EN_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *TRREG_CTRL2 - Traffic Remarking Control 2 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TRREG_CTRL2 :: SWITCH_RESV_1 [31:25] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_1_MASK 0xfe000000 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_1_SHIFT 25 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TRREG_CTRL2 :: C_PCP_RMK_EN [24:16] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2_C_PCP_RMK_EN_MASK 0x01ff0000 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2_C_PCP_RMK_EN_SHIFT 16 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2_C_PCP_RMK_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TRREG_CTRL2 :: SWITCH_RESV_0 [15:09] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_0_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_0_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TRREG_CTRL2 :: S_PCP_RMK_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2_S_PCP_RMK_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2_S_PCP_RMK_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TRREG_CTRL2_S_PCP_RMK_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2PCP_MAP_P0 - Port 0 Egress TC to PCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC7 [63:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC7_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC6 [59:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC5 [55:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC4 [51:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC4_MASK 0x000f000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC3 [47:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC2 [43:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC1 [39:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC1_MASK 0x000000f000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV1_TC0 [35:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC7 [31:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC6 [27:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC6_MASK 0x000000000f000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC5 [23:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC4 [19:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC3 [15:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC3_MASK 0x000000000000f000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC2 [11:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC1 [07:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P0 :: PCP_FOR_RV0_TC0 [03:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC0_MASK 0x000000000000000f |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2PCP_MAP_P1 - Port 1 Egress TC to PCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC7 [63:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC7_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC6 [59:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC5 [55:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC4 [51:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC4_MASK 0x000f000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC3 [47:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC2 [43:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC1 [39:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC1_MASK 0x000000f000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV1_TC0 [35:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC7 [31:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC6 [27:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC6_MASK 0x000000000f000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC5 [23:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC4 [19:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC3 [15:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC3_MASK 0x000000000000f000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC2 [11:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC1 [07:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P1 :: PCP_FOR_RV0_TC0 [03:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC0_MASK 0x000000000000000f |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2PCP_MAP_P2 - Port 2 Egress TC to PCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC7 [63:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC7_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC6 [59:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC5 [55:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC4 [51:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC4_MASK 0x000f000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC3 [47:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC2 [43:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC1 [39:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC1_MASK 0x000000f000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV1_TC0 [35:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC7 [31:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC6 [27:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC6_MASK 0x000000000f000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC5 [23:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC4 [19:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC3 [15:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC3_MASK 0x000000000000f000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC2 [11:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC1 [07:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P2 :: PCP_FOR_RV0_TC0 [03:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC0_MASK 0x000000000000000f |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2PCP_MAP_P3 - Port 3 Egress TC to PCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC7 [63:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC7_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC6 [59:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC5 [55:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC4 [51:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC4_MASK 0x000f000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC3 [47:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC2 [43:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC1 [39:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC1_MASK 0x000000f000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV1_TC0 [35:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC7 [31:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC6 [27:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC6_MASK 0x000000000f000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC5 [23:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC4 [19:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC3 [15:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC3_MASK 0x000000000000f000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC2 [11:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC1 [07:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P3 :: PCP_FOR_RV0_TC0 [03:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC0_MASK 0x000000000000000f |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2PCP_MAP_P4 - Port 4 Egress TC to PCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC7 [63:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC7_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC6 [59:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC5 [55:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC4 [51:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC4_MASK 0x000f000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC3 [47:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC2 [43:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC1 [39:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC1_MASK 0x000000f000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV1_TC0 [35:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC7 [31:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC6 [27:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC6_MASK 0x000000000f000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC5 [23:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC4 [19:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC3 [15:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC3_MASK 0x000000000000f000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC2 [11:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC1 [07:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P4 :: PCP_FOR_RV0_TC0 [03:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC0_MASK 0x000000000000000f |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2PCP_MAP_P5 - Port 5 Egress TC to PCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC7 [63:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC7_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC6 [59:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC5 [55:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC4 [51:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC4_MASK 0x000f000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC3 [47:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC2 [43:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC1 [39:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC1_MASK 0x000000f000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV1_TC0 [35:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC7 [31:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC6 [27:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC6_MASK 0x000000000f000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC5 [23:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC4 [19:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC3 [15:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC3_MASK 0x000000000000f000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC2 [11:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC1 [07:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P5 :: PCP_FOR_RV0_TC0 [03:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC0_MASK 0x000000000000000f |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2PCP_MAP_P7 - Port 7 Egress TC to PCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC7 [63:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC7_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC6 [59:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC5 [55:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC4 [51:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC4_MASK 0x000f000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC3 [47:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC2 [43:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC1 [39:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC1_MASK 0x000000f000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV1_TC0 [35:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC7 [31:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC6 [27:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC6_MASK 0x000000000f000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC5 [23:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC4 [19:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC3 [15:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC3_MASK 0x000000000000f000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC2 [11:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC1 [07:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_P7 :: PCP_FOR_RV0_TC0 [03:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC0_MASK 0x000000000000000f |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2PCP_MAP_IMP - Port 8 Egress TC to PCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC7 [63:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC7_MASK 0xf000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC7_DEFAULT 0x000000000000000f |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC6 [59:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC6_DEFAULT 0x000000000000000e |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC5 [55:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC5_DEFAULT 0x000000000000000d |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC4 [51:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC4_MASK 0x000f000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC4_DEFAULT 0x000000000000000c |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC3 [47:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC3_DEFAULT 0x000000000000000b |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC2 [43:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC2_DEFAULT 0x000000000000000a |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC1 [39:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC1_MASK 0x000000f000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC1_DEFAULT 0x0000000000000009 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV1_TC0 [35:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV1_TC0_DEFAULT 0x0000000000000008 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC7 [31:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC6 [27:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC6_MASK 0x000000000f000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC5 [23:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC4 [19:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC3 [15:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC3_MASK 0x000000000000f000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC2 [11:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC1 [07:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2PCP_MAP_IMP :: PCP_FOR_RV0_TC0 [03:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC0_MASK 0x000000000000000f |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP_PCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2CPCP_MAP_P0 - Port 0 Egress TC to CPCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_15 [63:63] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_15_MASK 0x8000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_15_SHIFT 63 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_15_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC7 [62:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_14 [59:59] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_14_MASK 0x0800000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_14_SHIFT 59 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_14_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC6 [58:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_13 [55:55] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_13_MASK 0x0080000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_13_SHIFT 55 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_13_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC5 [54:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_12 [51:51] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_12_MASK 0x0008000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_12_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_12_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC4 [50:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_11 [47:47] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_11_MASK 0x0000800000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_11_SHIFT 47 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_11_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC3 [46:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_10 [43:43] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_10_MASK 0x0000080000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_10_SHIFT 43 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_10_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC2 [42:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_9 [39:39] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_9_MASK 0x0000008000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_9_SHIFT 39 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_9_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC1 [38:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_8 [35:35] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_8_MASK 0x0000000800000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_8_SHIFT 35 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_8_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV1_TC0 [34:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_7 [31:31] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_7_MASK 0x0000000080000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_7_SHIFT 31 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_7_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC7 [30:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_6 [27:27] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_6_MASK 0x0000000008000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_6_SHIFT 27 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_6_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC6 [26:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_5 [23:23] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_5_MASK 0x0000000000800000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_5_SHIFT 23 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_5_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC5 [22:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_4 [19:19] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_4_MASK 0x0000000000080000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_4_SHIFT 19 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_4_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC4 [18:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_3 [15:15] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_3_MASK 0x0000000000008000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_3_SHIFT 15 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_3_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC3 [14:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_2 [11:11] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_2_MASK 0x0000000000000800 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_2_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_2_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC2 [10:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_1_MASK 0x0000000000000080 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_1_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC1 [06:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: SWITCH_RESV_0 [03:03] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_0_MASK 0x0000000000000008 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_0_SHIFT 3 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_SWITCH_RESV_0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P0 :: CPCP_FOR_RV0_TC0 [02:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2CPCP_MAP_P1 - Port 1 Egress TC to CPCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_15 [63:63] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_15_MASK 0x8000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_15_SHIFT 63 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_15_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC7 [62:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_14 [59:59] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_14_MASK 0x0800000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_14_SHIFT 59 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_14_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC6 [58:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_13 [55:55] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_13_MASK 0x0080000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_13_SHIFT 55 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_13_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC5 [54:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_12 [51:51] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_12_MASK 0x0008000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_12_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_12_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC4 [50:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_11 [47:47] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_11_MASK 0x0000800000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_11_SHIFT 47 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_11_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC3 [46:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_10 [43:43] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_10_MASK 0x0000080000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_10_SHIFT 43 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_10_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC2 [42:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_9 [39:39] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_9_MASK 0x0000008000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_9_SHIFT 39 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_9_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC1 [38:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_8 [35:35] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_8_MASK 0x0000000800000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_8_SHIFT 35 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_8_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV1_TC0 [34:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_7 [31:31] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_7_MASK 0x0000000080000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_7_SHIFT 31 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_7_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC7 [30:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_6 [27:27] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_6_MASK 0x0000000008000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_6_SHIFT 27 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_6_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC6 [26:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_5 [23:23] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_5_MASK 0x0000000000800000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_5_SHIFT 23 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_5_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC5 [22:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_4 [19:19] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_4_MASK 0x0000000000080000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_4_SHIFT 19 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_4_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC4 [18:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_3 [15:15] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_3_MASK 0x0000000000008000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_3_SHIFT 15 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_3_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC3 [14:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_2 [11:11] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_2_MASK 0x0000000000000800 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_2_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_2_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC2 [10:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_1_MASK 0x0000000000000080 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_1_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC1 [06:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: SWITCH_RESV_0 [03:03] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_0_MASK 0x0000000000000008 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_0_SHIFT 3 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_SWITCH_RESV_0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P1 :: CPCP_FOR_RV0_TC0 [02:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2CPCP_MAP_P2 - Port 2 Egress TC to CPCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_15 [63:63] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_15_MASK 0x8000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_15_SHIFT 63 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_15_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC7 [62:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_14 [59:59] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_14_MASK 0x0800000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_14_SHIFT 59 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_14_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC6 [58:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_13 [55:55] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_13_MASK 0x0080000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_13_SHIFT 55 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_13_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC5 [54:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_12 [51:51] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_12_MASK 0x0008000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_12_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_12_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC4 [50:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_11 [47:47] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_11_MASK 0x0000800000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_11_SHIFT 47 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_11_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC3 [46:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_10 [43:43] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_10_MASK 0x0000080000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_10_SHIFT 43 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_10_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC2 [42:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_9 [39:39] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_9_MASK 0x0000008000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_9_SHIFT 39 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_9_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC1 [38:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_8 [35:35] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_8_MASK 0x0000000800000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_8_SHIFT 35 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_8_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV1_TC0 [34:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_7 [31:31] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_7_MASK 0x0000000080000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_7_SHIFT 31 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_7_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC7 [30:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_6 [27:27] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_6_MASK 0x0000000008000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_6_SHIFT 27 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_6_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC6 [26:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_5 [23:23] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_5_MASK 0x0000000000800000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_5_SHIFT 23 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_5_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC5 [22:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_4 [19:19] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_4_MASK 0x0000000000080000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_4_SHIFT 19 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_4_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC4 [18:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_3 [15:15] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_3_MASK 0x0000000000008000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_3_SHIFT 15 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_3_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC3 [14:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_2 [11:11] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_2_MASK 0x0000000000000800 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_2_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_2_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC2 [10:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_1_MASK 0x0000000000000080 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_1_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC1 [06:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: SWITCH_RESV_0 [03:03] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_0_MASK 0x0000000000000008 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_0_SHIFT 3 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_SWITCH_RESV_0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P2 :: CPCP_FOR_RV0_TC0 [02:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2CPCP_MAP_P3 - Port 3 Egress TC to CPCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_15 [63:63] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_15_MASK 0x8000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_15_SHIFT 63 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_15_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC7 [62:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_14 [59:59] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_14_MASK 0x0800000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_14_SHIFT 59 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_14_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC6 [58:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_13 [55:55] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_13_MASK 0x0080000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_13_SHIFT 55 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_13_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC5 [54:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_12 [51:51] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_12_MASK 0x0008000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_12_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_12_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC4 [50:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_11 [47:47] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_11_MASK 0x0000800000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_11_SHIFT 47 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_11_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC3 [46:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_10 [43:43] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_10_MASK 0x0000080000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_10_SHIFT 43 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_10_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC2 [42:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_9 [39:39] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_9_MASK 0x0000008000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_9_SHIFT 39 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_9_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC1 [38:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_8 [35:35] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_8_MASK 0x0000000800000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_8_SHIFT 35 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_8_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV1_TC0 [34:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_7 [31:31] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_7_MASK 0x0000000080000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_7_SHIFT 31 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_7_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC7 [30:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_6 [27:27] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_6_MASK 0x0000000008000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_6_SHIFT 27 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_6_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC6 [26:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_5 [23:23] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_5_MASK 0x0000000000800000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_5_SHIFT 23 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_5_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC5 [22:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_4 [19:19] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_4_MASK 0x0000000000080000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_4_SHIFT 19 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_4_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC4 [18:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_3 [15:15] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_3_MASK 0x0000000000008000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_3_SHIFT 15 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_3_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC3 [14:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_2 [11:11] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_2_MASK 0x0000000000000800 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_2_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_2_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC2 [10:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_1_MASK 0x0000000000000080 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_1_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC1 [06:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: SWITCH_RESV_0 [03:03] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_0_MASK 0x0000000000000008 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_0_SHIFT 3 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_SWITCH_RESV_0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P3 :: CPCP_FOR_RV0_TC0 [02:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2CPCP_MAP_P4 - Port 4 Egress TC to CPCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_15 [63:63] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_15_MASK 0x8000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_15_SHIFT 63 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_15_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC7 [62:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_14 [59:59] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_14_MASK 0x0800000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_14_SHIFT 59 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_14_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC6 [58:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_13 [55:55] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_13_MASK 0x0080000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_13_SHIFT 55 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_13_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC5 [54:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_12 [51:51] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_12_MASK 0x0008000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_12_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_12_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC4 [50:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_11 [47:47] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_11_MASK 0x0000800000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_11_SHIFT 47 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_11_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC3 [46:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_10 [43:43] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_10_MASK 0x0000080000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_10_SHIFT 43 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_10_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC2 [42:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_9 [39:39] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_9_MASK 0x0000008000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_9_SHIFT 39 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_9_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC1 [38:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_8 [35:35] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_8_MASK 0x0000000800000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_8_SHIFT 35 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_8_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV1_TC0 [34:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_7 [31:31] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_7_MASK 0x0000000080000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_7_SHIFT 31 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_7_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC7 [30:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_6 [27:27] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_6_MASK 0x0000000008000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_6_SHIFT 27 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_6_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC6 [26:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_5 [23:23] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_5_MASK 0x0000000000800000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_5_SHIFT 23 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_5_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC5 [22:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_4 [19:19] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_4_MASK 0x0000000000080000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_4_SHIFT 19 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_4_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC4 [18:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_3 [15:15] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_3_MASK 0x0000000000008000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_3_SHIFT 15 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_3_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC3 [14:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_2 [11:11] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_2_MASK 0x0000000000000800 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_2_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_2_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC2 [10:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_1_MASK 0x0000000000000080 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_1_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC1 [06:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: SWITCH_RESV_0 [03:03] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_0_MASK 0x0000000000000008 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_0_SHIFT 3 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_SWITCH_RESV_0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P4 :: CPCP_FOR_RV0_TC0 [02:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2CPCP_MAP_P5 - Port 5 Egress TC to CPCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_15 [63:63] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_15_MASK 0x8000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_15_SHIFT 63 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_15_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC7 [62:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_14 [59:59] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_14_MASK 0x0800000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_14_SHIFT 59 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_14_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC6 [58:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_13 [55:55] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_13_MASK 0x0080000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_13_SHIFT 55 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_13_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC5 [54:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_12 [51:51] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_12_MASK 0x0008000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_12_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_12_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC4 [50:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_11 [47:47] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_11_MASK 0x0000800000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_11_SHIFT 47 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_11_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC3 [46:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_10 [43:43] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_10_MASK 0x0000080000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_10_SHIFT 43 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_10_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC2 [42:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_9 [39:39] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_9_MASK 0x0000008000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_9_SHIFT 39 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_9_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC1 [38:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_8 [35:35] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_8_MASK 0x0000000800000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_8_SHIFT 35 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_8_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV1_TC0 [34:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_7 [31:31] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_7_MASK 0x0000000080000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_7_SHIFT 31 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_7_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC7 [30:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_6 [27:27] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_6_MASK 0x0000000008000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_6_SHIFT 27 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_6_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC6 [26:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_5 [23:23] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_5_MASK 0x0000000000800000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_5_SHIFT 23 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_5_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC5 [22:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_4 [19:19] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_4_MASK 0x0000000000080000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_4_SHIFT 19 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_4_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC4 [18:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_3 [15:15] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_3_MASK 0x0000000000008000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_3_SHIFT 15 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_3_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC3 [14:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_2 [11:11] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_2_MASK 0x0000000000000800 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_2_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_2_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC2 [10:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_1_MASK 0x0000000000000080 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_1_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC1 [06:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: SWITCH_RESV_0 [03:03] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_0_MASK 0x0000000000000008 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_0_SHIFT 3 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_SWITCH_RESV_0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P5 :: CPCP_FOR_RV0_TC0 [02:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2CPCP_MAP_P7 - Port 7 Egress TC to CPCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_15 [63:63] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_15_MASK 0x8000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_15_SHIFT 63 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_15_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC7 [62:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_14 [59:59] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_14_MASK 0x0800000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_14_SHIFT 59 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_14_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC6 [58:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_13 [55:55] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_13_MASK 0x0080000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_13_SHIFT 55 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_13_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC5 [54:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_12 [51:51] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_12_MASK 0x0008000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_12_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_12_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC4 [50:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_11 [47:47] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_11_MASK 0x0000800000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_11_SHIFT 47 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_11_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC3 [46:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_10 [43:43] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_10_MASK 0x0000080000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_10_SHIFT 43 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_10_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC2 [42:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_9 [39:39] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_9_MASK 0x0000008000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_9_SHIFT 39 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_9_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC1 [38:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_8 [35:35] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_8_MASK 0x0000000800000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_8_SHIFT 35 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_8_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV1_TC0 [34:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_7 [31:31] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_7_MASK 0x0000000080000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_7_SHIFT 31 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_7_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC7 [30:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_6 [27:27] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_6_MASK 0x0000000008000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_6_SHIFT 27 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_6_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC6 [26:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_5 [23:23] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_5_MASK 0x0000000000800000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_5_SHIFT 23 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_5_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC5 [22:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_4 [19:19] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_4_MASK 0x0000000000080000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_4_SHIFT 19 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_4_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC4 [18:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_3 [15:15] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_3_MASK 0x0000000000008000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_3_SHIFT 15 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_3_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC3 [14:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_2 [11:11] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_2_MASK 0x0000000000000800 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_2_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_2_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC2 [10:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_1_MASK 0x0000000000000080 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_1_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC1 [06:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: SWITCH_RESV_0 [03:03] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_0_MASK 0x0000000000000008 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_0_SHIFT 3 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_SWITCH_RESV_0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_P7 :: CPCP_FOR_RV0_TC0 [02:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *EGRESS_PKT_TC2CPCP_MAP_IMP - Port 8 Egress TC to CPCP mapping Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_15 [63:63] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_15_MASK 0x8000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_15_SHIFT 63 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_15_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC7 [62:60] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC7_SHIFT 60 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_14 [59:59] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_14_MASK 0x0800000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_14_SHIFT 59 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_14_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC6 [58:56] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC6_SHIFT 56 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_13 [55:55] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_13_MASK 0x0080000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_13_SHIFT 55 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_13_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC5 [54:52] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC5_SHIFT 52 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_12 [51:51] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_12_MASK 0x0008000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_12_SHIFT 51 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_12_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC4 [50:48] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC4_SHIFT 48 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_11 [47:47] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_11_MASK 0x0000800000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_11_SHIFT 47 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_11_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC3 [46:44] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC3_SHIFT 44 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_10 [43:43] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_10_MASK 0x0000080000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_10_SHIFT 43 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_10_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC2 [42:40] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC2_SHIFT 40 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_9 [39:39] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_9_MASK 0x0000008000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_9_SHIFT 39 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_9_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC1 [38:36] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC1_SHIFT 36 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_8 [35:35] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_8_MASK 0x0000000800000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_8_SHIFT 35 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_8_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV1_TC0 [34:32] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC0_SHIFT 32 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV1_TC0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_7 [31:31] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_7_MASK 0x0000000080000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_7_SHIFT 31 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_7_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC7 [30:28] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC7_SHIFT 28 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC7_DEFAULT 0x0000000000000007 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_6 [27:27] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_6_MASK 0x0000000008000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_6_SHIFT 27 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_6_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC6 [26:24] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC6_SHIFT 24 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC6_DEFAULT 0x0000000000000006 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_5 [23:23] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_5_MASK 0x0000000000800000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_5_SHIFT 23 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_5_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC5 [22:20] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC5_SHIFT 20 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC5_DEFAULT 0x0000000000000005 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_4 [19:19] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_4_MASK 0x0000000000080000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_4_SHIFT 19 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_4_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC4 [18:16] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC4_SHIFT 16 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC4_DEFAULT 0x0000000000000004 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_3 [15:15] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_3_MASK 0x0000000000008000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_3_SHIFT 15 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_3_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC3 [14:12] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC3_SHIFT 12 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC3_DEFAULT 0x0000000000000003 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_2 [11:11] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_2_MASK 0x0000000000000800 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_2_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_2_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC2 [10:08] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC2_SHIFT 8 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC2_DEFAULT 0x0000000000000002 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_1 [07:07] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_1_MASK 0x0000000000000080 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_1_SHIFT 7 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_1_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC1 [06:04] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC1_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC1_DEFAULT 0x0000000000000001 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: SWITCH_RESV_0 [03:03] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_0_MASK 0x0000000000000008 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_0_SHIFT 3 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_SWITCH_RESV_0_DEFAULT 0x0000000000000000 |
| |
| /* SWITCH_CORE :: EGRESS_PKT_TC2CPCP_MAP_IMP :: CPCP_FOR_RV0_TC0 [02:00] */ |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP_CPCP_FOR_RV0_TC0_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *TRREG_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TRREG_REG_SPARE0 :: TRREG_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_TRREG_REG_SPARE0_TRREG_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TRREG_REG_SPARE0_TRREG_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TRREG_REG_SPARE0_TRREG_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TRREG_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TRREG_REG_SPARE1 :: TRREG_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_TRREG_REG_SPARE1_TRREG_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_TRREG_REG_SPARE1_TRREG_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TRREG_REG_SPARE1_TRREG_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_EN_CTRL - EEE Enable Control Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_EN_CTRL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_EN_CTRL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_EN_CTRL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_EN_CTRL :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_EEE_EN_CTRL_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_EEE_EN_CTRL_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_EEE_EN_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_EN_CTRL :: EN_EEE [08:00] */ |
| #define BCHP_SWITCH_CORE_EEE_EN_CTRL_EN_EEE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_EEE_EN_CTRL_EN_EEE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_EN_CTRL_EN_EEE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_ASSERT - EEE Low Power Assert Status Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_ASSERT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_LPI_ASSERT :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_LPI_ASSERT :: LPI_ASSERT [08:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_LPI_ASSERT_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_LPI_ASSERT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_ASSERT_LPI_ASSERT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_INDICATE - EEE Low Power Indicate Status Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_INDICATE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_LPI_INDICATE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_LPI_INDICATE :: LPI_INDICATE [08:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_LPI_INDICATE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_LPI_INDICATE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_INDICATE_LPI_INDICATE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_RX_IDLE_SYMBOL - EEE Receiving Idle Symbols Status Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_RX_IDLE_SYMBOL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_RX_IDLE_SYMBOL :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_RX_IDLE_SYMBOL :: RX_IDLE_SYMBOL [08:00] */ |
| #define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LPI_SYMBOL_TX_DISABLE - EEE LPI Symbol Transmit Disable Registers(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LPI_SYMBOL_TX_DISABLE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_LPI_SYMBOL_TX_DISABLE :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_LPI_SYMBOL_TX_DISABLE :: EEE_LPI_SYMBOL_TX_DISABLE [08:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_PIPELINE_TIMER - EEE Pipeline Delay Timer Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_PIPELINE_TIMER :: PIPELINE_TIMER [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER_PIPELINE_TIMER_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER_PIPELINE_TIMER_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_PIPELINE_TIMER_PIPELINE_TIMER_DEFAULT 0x00000020 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_G_P0 - EEE Port 0 Sleep Delay Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P0 :: SLEEP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P0_SLEEP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P0_SLEEP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P0_SLEEP_TIMER_G_DEFAULT 0x00000190 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_G_P1 - EEE Port 1 Sleep Delay Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P1 :: SLEEP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P1_SLEEP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P1_SLEEP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P1_SLEEP_TIMER_G_DEFAULT 0x00000190 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_G_P2 - EEE Port 2 Sleep Delay Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P2 :: SLEEP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P2_SLEEP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P2_SLEEP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P2_SLEEP_TIMER_G_DEFAULT 0x00000190 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_G_P3 - EEE Port 3 Sleep Delay Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P3 :: SLEEP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P3_SLEEP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P3_SLEEP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P3_SLEEP_TIMER_G_DEFAULT 0x00000190 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_G_P4 - EEE Port 4 Sleep Delay Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P4 :: SLEEP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P4_SLEEP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P4_SLEEP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P4_SLEEP_TIMER_G_DEFAULT 0x00000190 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_G_P5 - EEE Port 5 Sleep Delay Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P5 :: SLEEP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P5_SLEEP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P5_SLEEP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P5_SLEEP_TIMER_G_DEFAULT 0x00000190 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_G_P7 - EEE Port 7 Sleep Delay Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_G_P7 :: SLEEP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_DEFAULT 0x00000190 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_G_IMP - EEE Port 8(IMP) Sleep Delay Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_G_IMP :: SLEEP_TIMER_G_IMP [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_DEFAULT 0x00000190 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_H_P0 - EEE Port 0 Sleep Delay Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P0 :: SLEEP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P0_SLEEP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P0_SLEEP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P0_SLEEP_TIMER_H_DEFAULT 0x00000fa0 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_H_P1 - EEE Port 1 Sleep Delay Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P1 :: SLEEP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P1_SLEEP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P1_SLEEP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P1_SLEEP_TIMER_H_DEFAULT 0x00000fa0 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_H_P2 - EEE Port 2 Sleep Delay Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P2 :: SLEEP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P2_SLEEP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P2_SLEEP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P2_SLEEP_TIMER_H_DEFAULT 0x00000fa0 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_H_P3 - EEE Port 3 Sleep Delay Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P3 :: SLEEP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P3_SLEEP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P3_SLEEP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P3_SLEEP_TIMER_H_DEFAULT 0x00000fa0 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_H_P4 - EEE Port 4 Sleep Delay Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P4 :: SLEEP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P4_SLEEP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P4_SLEEP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P4_SLEEP_TIMER_H_DEFAULT 0x00000fa0 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_H_P5 - EEE Port 5 Sleep Delay Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P5 :: SLEEP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P5_SLEEP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P5_SLEEP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P5_SLEEP_TIMER_H_DEFAULT 0x00000fa0 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_H_P7 - EEE Port 7 Sleep Delay Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_H_P7 :: SLEEP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_DEFAULT 0x00000fa0 |
| |
| /*************************************************************************** |
| *EEE_SLEEP_TIMER_H_IMP - EEE Port 8(IMP) Sleep Delay Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_SLEEP_TIMER_H_IMP :: SLEEP_TIMER_H_IMP [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_DEFAULT 0x00000fa0 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_G_P0 - EEE Port Minimum Low-Power Duration Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P0 :: MIN_LP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P0_MIN_LP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P0_MIN_LP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P0_MIN_LP_TIMER_G_DEFAULT 0x00000032 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_G_P1 - EEE Port Minimum Low-Power Duration Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P1 :: MIN_LP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P1_MIN_LP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P1_MIN_LP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P1_MIN_LP_TIMER_G_DEFAULT 0x00000032 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_G_P2 - EEE Port Minimum Low-Power Duration Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P2 :: MIN_LP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P2_MIN_LP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P2_MIN_LP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P2_MIN_LP_TIMER_G_DEFAULT 0x00000032 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_G_P3 - EEE Port Minimum Low-Power Duration Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P3 :: MIN_LP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P3_MIN_LP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P3_MIN_LP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P3_MIN_LP_TIMER_G_DEFAULT 0x00000032 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_G_P4 - EEE Port Minimum Low-Power Duration Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P4 :: MIN_LP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P4_MIN_LP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P4_MIN_LP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P4_MIN_LP_TIMER_G_DEFAULT 0x00000032 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_G_P5 - EEE Port Minimum Low-Power Duration Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P5 :: MIN_LP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P5_MIN_LP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P5_MIN_LP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P5_MIN_LP_TIMER_G_DEFAULT 0x00000032 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_G_P7 - EEE Port 7 Minimum Low-Power Duration Timer Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_P7 :: MIN_LP_TIMER_G [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_DEFAULT 0x00000032 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_G_IMP - EEE Port 8(IMP) Minimum Low-Power Duration Timer Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_G_IMP :: MIN_LP_TIMER_G_IMP [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_DEFAULT 0x00000032 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_H_P0 - EEE Port Minimum Low-Power Duration Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P0 :: MIN_LP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P0_MIN_LP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P0_MIN_LP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P0_MIN_LP_TIMER_H_DEFAULT 0x000001f4 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_H_P1 - EEE Port Minimum Low-Power Duration Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P1 :: MIN_LP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P1_MIN_LP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P1_MIN_LP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P1_MIN_LP_TIMER_H_DEFAULT 0x000001f4 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_H_P2 - EEE Port Minimum Low-Power Duration Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P2 :: MIN_LP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P2_MIN_LP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P2_MIN_LP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P2_MIN_LP_TIMER_H_DEFAULT 0x000001f4 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_H_P3 - EEE Port Minimum Low-Power Duration Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P3 :: MIN_LP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P3_MIN_LP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P3_MIN_LP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P3_MIN_LP_TIMER_H_DEFAULT 0x000001f4 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_H_P4 - EEE Port Minimum Low-Power Duration Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P4 :: MIN_LP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P4_MIN_LP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P4_MIN_LP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P4_MIN_LP_TIMER_H_DEFAULT 0x000001f4 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_H_P5 - EEE Port Minimum Low-Power Duration Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P5 :: MIN_LP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P5_MIN_LP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P5_MIN_LP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P5_MIN_LP_TIMER_H_DEFAULT 0x000001f4 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_H_P7 - EEE Port 7 Minimum Low-Power Duration Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_P7 :: MIN_LP_TIMER_H [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_DEFAULT 0x000001f4 |
| |
| /*************************************************************************** |
| *EEE_MIN_LP_TIMER_H_IMP - EEE Port 8(IMP) Minimum Low-Power Duration Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_MIN_LP_TIMER_H_IMP :: MIN_LP_TIMER_H_IMP [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_DEFAULT 0x000001f4 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_G_P0 - EEE Port 0 Wake Transition Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P0 :: WAKE_TIMER_G [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P0_WAKE_TIMER_G_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P0_WAKE_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P0_WAKE_TIMER_G_DEFAULT 0x00000011 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_G_P1 - EEE Port 1 Wake Transition Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P1 :: WAKE_TIMER_G [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P1_WAKE_TIMER_G_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P1_WAKE_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P1_WAKE_TIMER_G_DEFAULT 0x00000011 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_G_P2 - EEE Port 2 Wake Transition Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P2 :: WAKE_TIMER_G [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P2_WAKE_TIMER_G_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P2_WAKE_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P2_WAKE_TIMER_G_DEFAULT 0x00000011 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_G_P3 - EEE Port 3 Wake Transition Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P3 :: WAKE_TIMER_G [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P3_WAKE_TIMER_G_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P3_WAKE_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P3_WAKE_TIMER_G_DEFAULT 0x00000011 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_G_P4 - EEE Port 4 Wake Transition Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P4 :: WAKE_TIMER_G [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P4_WAKE_TIMER_G_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P4_WAKE_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P4_WAKE_TIMER_G_DEFAULT 0x00000011 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_G_P5 - EEE Port 5 Wake Transition Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P5 :: WAKE_TIMER_G [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P5_WAKE_TIMER_G_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P5_WAKE_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P5_WAKE_TIMER_G_DEFAULT 0x00000011 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_G_P7 - EEE Port 7 Wake Transition Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P7 :: WAKE_TIMER_G [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_DEFAULT 0x00000011 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_G_P8 - EEE Port 8(IMP) Wake Transition Timer - 1G Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P8 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P8_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P8_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_G_P8 :: WAKE_TIMER_G_IMP [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P8_WAKE_TIMER_G_IMP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P8_WAKE_TIMER_G_IMP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_G_P8_WAKE_TIMER_G_IMP_DEFAULT 0x00000011 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_H_P0 - EEE Port 0 Wake Transition Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P0 :: WAKE_TIMER_H [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P0_WAKE_TIMER_H_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P0_WAKE_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P0_WAKE_TIMER_H_DEFAULT 0x00000024 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_H_P1 - EEE Port 1 Wake Transition Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P1 :: WAKE_TIMER_H [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P1_WAKE_TIMER_H_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P1_WAKE_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P1_WAKE_TIMER_H_DEFAULT 0x00000024 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_H_P2 - EEE Port 2 Wake Transition Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P2 :: WAKE_TIMER_H [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P2_WAKE_TIMER_H_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P2_WAKE_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P2_WAKE_TIMER_H_DEFAULT 0x00000024 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_H_P3 - EEE Port 3 Wake Transition Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P3 :: WAKE_TIMER_H [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P3_WAKE_TIMER_H_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P3_WAKE_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P3_WAKE_TIMER_H_DEFAULT 0x00000024 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_H_P4 - EEE Port 4 Wake Transition Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P4 :: WAKE_TIMER_H [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P4_WAKE_TIMER_H_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P4_WAKE_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P4_WAKE_TIMER_H_DEFAULT 0x00000024 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_H_P5 - EEE Port 5 Wake Transition Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P5 :: WAKE_TIMER_H [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P5_WAKE_TIMER_H_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P5_WAKE_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P5_WAKE_TIMER_H_DEFAULT 0x00000024 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_H_P7 - EEE Port 7 Wake Transition Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_P7 :: WAKE_TIMER_H [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_DEFAULT 0x00000024 |
| |
| /*************************************************************************** |
| *EEE_WAKE_TIMER_H_IMP - EEE Port 8(IMP) Wake Transition Timer - 100M Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_IMP :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_WAKE_TIMER_H_IMP :: WAKE_TIMER_H_IMP [15:00] */ |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_DEFAULT 0x00000024 |
| |
| /*************************************************************************** |
| *EEE_GLB_CONG_TH - EEE Global Congestion Threshold Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_GLB_CONG_TH :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_GLB_CONG_TH :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_GLB_CONG_TH :: GLB_CONG_TH [10:00] */ |
| #define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_GLB_CONG_TH_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_GLB_CONG_TH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_GLB_CONG_TH_GLB_CONG_TH_DEFAULT 0x00000300 |
| |
| /*************************************************************************** |
| *EEE_TX_CONG_TH_Q0 - EEE TXQ 0 Congestion Threshold Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q0 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q0 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q0 :: TXQ_CONG_TH [10:00] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_TXQ_CONG_TH_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_TXQ_CONG_TH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q0_TXQ_CONG_TH_DEFAULT 0x00000050 |
| |
| /*************************************************************************** |
| *EEE_TX_CONG_TH_Q1 - EEE TXQ 1 Congestion Threshold Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q1 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q1 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q1 :: TXQ_CONG_TH [10:00] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_TXQ_CONG_TH_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_TXQ_CONG_TH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q1_TXQ_CONG_TH_DEFAULT 0x00000050 |
| |
| /*************************************************************************** |
| *EEE_TX_CONG_TH_Q2 - EEE TXQ 2 Congestion Threshold Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q2 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q2 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q2 :: TXQ_CONG_TH [10:00] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_TXQ_CONG_TH_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_TXQ_CONG_TH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q2_TXQ_CONG_TH_DEFAULT 0x00000050 |
| |
| /*************************************************************************** |
| *EEE_TX_CONG_TH_Q3 - EEE TXQ 3 Congestion Threshold Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q3 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q3 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q3 :: TXQ_CONG_TH [10:00] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_TXQ_CONG_TH_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_TXQ_CONG_TH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q3_TXQ_CONG_TH_DEFAULT 0x00000050 |
| |
| /*************************************************************************** |
| *EEE_TX_CONG_TH_Q4 - EEE TXQ 4 Congestion Threshold Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q4 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q4 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q4 :: TXQ_CONG_TH [10:00] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_TXQ_CONG_TH_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_TXQ_CONG_TH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q4_TXQ_CONG_TH_DEFAULT 0x00000050 |
| |
| /*************************************************************************** |
| *EEE_TX_CONG_TH_Q5 - EEE TXQ 5 Congestion Threshold Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q5 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q5 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q5 :: TXQ_CONG_TH [10:00] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_TXQ_CONG_TH_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_TXQ_CONG_TH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q5_TXQ_CONG_TH_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *EEE_PHY_CTRL - EEE PHY Control Registers(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_PHY_CTRL :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: EEE_PHY_CTRL :: SWITCH_RESV [07:04] */ |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_SWITCH_RESV_MASK 0x000000f0 |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_SWITCH_RESV_SHIFT 4 |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_PHY_CTRL :: EEE_100BASE_TX [03:03] */ |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_100BASE_TX_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_100BASE_TX_SHIFT 3 |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_100BASE_TX_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: EEE_PHY_CTRL :: EEE_1000BASE_TX [02:02] */ |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_1000BASE_TX_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_1000BASE_TX_SHIFT 2 |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EEE_1000BASE_TX_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: EEE_PHY_CTRL :: EN_PHY_LPI [01:01] */ |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_PHY_LPI_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_PHY_LPI_SHIFT 1 |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_PHY_LPI_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: EEE_PHY_CTRL :: EN_BIAS_10BTE [00:00] */ |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_BIAS_10BTE_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_BIAS_10BTE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_PHY_CTRL_EN_BIAS_10BTE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_TX_CONG_TH_Q6 - EEE TXQ 6 Congestion Threshold Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q6 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q6 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q6 :: TXQ_CONG_TH [10:00] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_TXQ_CONG_TH_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_TXQ_CONG_TH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q6_TXQ_CONG_TH_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *EEE_TX_CONG_TH_Q7 - EEE TXQ 7 Congestion Threshold Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q7 :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q7 :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_TX_CONG_TH_Q7 :: TXQ_CONG_TH [10:00] */ |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_TXQ_CONG_TH_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_TXQ_CONG_TH_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_TX_CONG_TH_Q7_TXQ_CONG_TH_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *EEE_CTL_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_CTL_REG_SPARE0 :: EEE_CTL_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_CTL_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_CTL_REG_SPARE1 :: EEE_CTL_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_DEBUG - EEE Debug Registers(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_DEBUG :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_EEE_DEBUG_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_EEE_DEBUG_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: EEE_DEBUG :: SWITCH_RESV [07:02] */ |
| #define BCHP_SWITCH_CORE_EEE_DEBUG_SWITCH_RESV_MASK 0x000000fc |
| #define BCHP_SWITCH_CORE_EEE_DEBUG_SWITCH_RESV_SHIFT 2 |
| #define BCHP_SWITCH_CORE_EEE_DEBUG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_DEBUG :: DIS_EXIT_LPI_FLOW_CON_TX [01:01] */ |
| #define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_SHIFT 1 |
| #define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_DEBUG :: DIS_EMPTY_FLOW_CON [00:00] */ |
| #define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EMPTY_FLOW_CON_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EMPTY_FLOW_CON_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_DEBUG_DIS_EMPTY_FLOW_CON_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EEE_LINK_DLY_TIMER - EEE Link Delay Timer Registers(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_LINK_DLY_TIMER :: LINK_DLY_TIMER [31:00] */ |
| #define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_DEFAULT 0x000f4240 |
| |
| /*************************************************************************** |
| *EEE_STATE - EEE Control Policy State Registers(Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: EEE_STATE :: SWITCH_RESV [31:27] */ |
| #define BCHP_SWITCH_CORE_EEE_STATE_SWITCH_RESV_MASK 0xf8000000 |
| #define BCHP_SWITCH_CORE_EEE_STATE_SWITCH_RESV_SHIFT 27 |
| #define BCHP_SWITCH_CORE_EEE_STATE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: EEE_STATE :: EEE_STATE [26:00] */ |
| #define BCHP_SWITCH_CORE_EEE_STATE_EEE_STATE_MASK 0x07ffffff |
| #define BCHP_SWITCH_CORE_EEE_STATE_EEE_STATE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_EEE_STATE_EEE_STATE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_CONTROL - RED Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_CONTROL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_RED_CONTROL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_RED_CONTROL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: RED_CONTROL :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_RED_CONTROL_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_RED_CONTROL_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_RED_CONTROL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_CONTROL :: RED_EN [08:00] */ |
| #define BCHP_SWITCH_CORE_RED_CONTROL_RED_EN_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_RED_CONTROL_RED_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_CONTROL_RED_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC2RED_PROFILE_TABLE - RED Table Configuration Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: TC2RED_TABLE_WR_RD [15:15] */ |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_SHIFT 15 |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: SWITCH_RESV [14:13] */ |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_SWITCH_RESV_MASK 0x00006000 |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_SWITCH_RESV_SHIFT 13 |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: TC2RED_TABLE_ADDR [12:04] */ |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_MASK 0x00001ff0 |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_SHIFT 4 |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2RED_PROFILE_TABLE :: TC2RED_TABLE_DATA [03:00] */ |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_EGRESS_BYPASS - RED Egress Bypass Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_EGRESS_BYPASS :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: RED_EGRESS_BYPASS :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_EGRESS_BYPASS :: RED_EGRESS_BYPASS [08:00] */ |
| #define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_DEFAULT 0x00000080 |
| |
| /*************************************************************************** |
| *RED_AQD_CONTROL - RED AQD Control Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_AQD_CONTROL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: RED_AQD_CONTROL :: SWITCH_RESV_2 [15:12] */ |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_2_MASK 0x0000f000 |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_2_SHIFT 12 |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_2_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_AQD_CONTROL :: AQD_PERIOD [11:08] */ |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_PERIOD_MASK 0x00000f00 |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_PERIOD_SHIFT 8 |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_PERIOD_DEFAULT 0x00000008 |
| |
| /* SWITCH_CORE :: RED_AQD_CONTROL :: SWITCH_RESV_1 [07:06] */ |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_1_MASK 0x000000c0 |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_1_SHIFT 6 |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_AQD_CONTROL :: AQD_RST [05:05] */ |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_RST_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_RST_SHIFT 5 |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_AQD_RST_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_AQD_CONTROL :: RED_FAST_CORR [04:04] */ |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_RED_FAST_CORR_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_RED_FAST_CORR_SHIFT 4 |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_RED_FAST_CORR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_AQD_CONTROL :: SWITCH_RESV_0 [03:00] */ |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_0_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_AQD_CONTROL_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_EXPONENT - RED AQD Weighted Factor Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_EXPONENT :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_RED_EXPONENT_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_RED_EXPONENT_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: RED_EXPONENT :: SWITCH_RESV [15:08] */ |
| #define BCHP_SWITCH_CORE_RED_EXPONENT_SWITCH_RESV_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_RED_EXPONENT_SWITCH_RESV_SHIFT 8 |
| #define BCHP_SWITCH_CORE_RED_EXPONENT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_EXPONENT :: RED_EXPONENT [07:00] */ |
| #define BCHP_SWITCH_CORE_RED_EXPONENT_RED_EXPONENT_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_RED_EXPONENT_RED_EXPONENT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_EXPONENT_RED_EXPONENT_DEFAULT 0x00000005 |
| |
| /*************************************************************************** |
| *RED_DROP_ADD_TO_MIB - RED Drop Add to MIB Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_DROP_ADD_TO_MIB :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: RED_DROP_ADD_TO_MIB :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_DROP_ADD_TO_MIB :: RED_DROP_ADD_TO_MIB [08:00] */ |
| #define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_DEFAULT 0x000001ff |
| |
| /*************************************************************************** |
| *RED_PROFILE_DEFAULT - Default RED profile Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE_DEFAULT :: SWITCH_RESV [31:04] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_SWITCH_RESV_MASK 0xfffffff0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_SWITCH_RESV_SHIFT 4 |
| #define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE_DEFAULT :: RED_PROFILE_DEFAULT [03:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_MASK 0x0000000f |
| #define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WRED_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WRED_REG_SPARE0 :: WRED_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_WRED_REG_SPARE0_WRED_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_WRED_REG_SPARE0_WRED_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WRED_REG_SPARE0_WRED_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WRED_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: WRED_REG_SPARE1 :: WRED_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_WRED_REG_SPARE1_WRED_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_WRED_REG_SPARE1_WRED_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_WRED_REG_SPARE1_WRED_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE0 - RED profile 0 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE0 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE0_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE0_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE0 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE0_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE0_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE0_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE0 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE0_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE0_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE0_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE0 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE0_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE0_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE0_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE1 - RED profile 1 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE1 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE1_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE1_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE1 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE1_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE1_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE1_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE1 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE1_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE1_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE1_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE1 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE1_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE1_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE1_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE2 - RED profile 2 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE2 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE2_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE2_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE2 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE2_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE2_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE2_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE2 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE2_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE2_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE2_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE2 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE2_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE2_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE2_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE3 - RED profile 3 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE3 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE3_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE3_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE3 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE3_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE3_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE3_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE3 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE3_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE3_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE3_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE3 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE3_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE3_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE3_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE4 - RED profile 4 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE4 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE4_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE4_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE4 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE4_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE4_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE4_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE4 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE4_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE4_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE4_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE4 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE4_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE4_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE4_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE5 - RED profile 5 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE5 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE5_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE5_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE5 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE5_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE5_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE5_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE5 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE5_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE5_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE5_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE5 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE5_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE5_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE5_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE6 - RED profile 6 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE6 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE6_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE6_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE6 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE6_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE6_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE6_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE6 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE6_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE6_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE6_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE6 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE6_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE6_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE6_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE7 - RED profile 7 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE7 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE7_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE7_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE7_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE7 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE7_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE7_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE7_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE7 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE7_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE7_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE7_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE7 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE7_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE7_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE7_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE8 - RED profile 8 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE8 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE8_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE8_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE8_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE8 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE8_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE8_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE8_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE8 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE8_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE8_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE8_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE8 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE8_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE8_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE8_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE9 - RED profile 9 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE9 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE9_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE9_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE9_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE9 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE9_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE9_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE9_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE9 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE9_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE9_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE9_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE9 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE9_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE9_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE9_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE10 - RED profile 10 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE10 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE10_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE10_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE10_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE10 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE10_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE10_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE10_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE10 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE10_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE10_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE10_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE10 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE10_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE10_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE10_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE11 - RED profile 11 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE11 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE11_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE11_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE11_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE11 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE11_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE11_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE11_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE11 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE11_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE11_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE11_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE11 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE11_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE11_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE11_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE12 - RED profile 12 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE12 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE12_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE12_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE12_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE12 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE12_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE12_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE12_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE12 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE12_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE12_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE12_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE12 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE12_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE12_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE12_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE13 - RED profile 13 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE13 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE13_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE13_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE13_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE13 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE13_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE13_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE13_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE13 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE13_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE13_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE13_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE13 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE13_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE13_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE13_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE14 - RED profile 14 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE14 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE14_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE14_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE14_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE14 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE14_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE14_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE14_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE14 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE14_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE14_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE14_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE14 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE14_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE14_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE14_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PROFILE15 - RED profile 15 Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PROFILE15 :: SWITCH_RESV [31:26] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE15_SWITCH_RESV_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE15_SWITCH_RESV_SHIFT 26 |
| #define BCHP_SWITCH_CORE_RED_PROFILE15_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE15 :: RED_DROP_PROB [25:22] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE15_RED_DROP_PROB_MASK 0x03c00000 |
| #define BCHP_SWITCH_CORE_RED_PROFILE15_RED_DROP_PROB_SHIFT 22 |
| #define BCHP_SWITCH_CORE_RED_PROFILE15_RED_DROP_PROB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE15 :: RED_MAX_THD [21:11] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE15_RED_MAX_THD_MASK 0x003ff800 |
| #define BCHP_SWITCH_CORE_RED_PROFILE15_RED_MAX_THD_SHIFT 11 |
| #define BCHP_SWITCH_CORE_RED_PROFILE15_RED_MAX_THD_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_PROFILE15 :: RED_MIN_THD [10:00] */ |
| #define BCHP_SWITCH_CORE_RED_PROFILE15_RED_MIN_THD_MASK 0x000007ff |
| #define BCHP_SWITCH_CORE_RED_PROFILE15_RED_MIN_THD_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PROFILE15_RED_MIN_THD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_DROP_CNTR_RST - RED Drop Counter Reset Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_DROP_CNTR_RST :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: RED_DROP_CNTR_RST :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RED_DROP_CNTR_RST :: RED_DROP_CNTR_RST [08:00] */ |
| #define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PKT_DROP_CNTR_P0 - PORT 0 RED Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PKT_DROP_CNTR_P0 :: RED_PKT_DROP_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P0_RED_PKT_DROP_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P0_RED_PKT_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P0_RED_PKT_DROP_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PKT_DROP_CNTR_P1 - PORT 1 RED Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PKT_DROP_CNTR_P1 :: RED_PKT_DROP_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P1_RED_PKT_DROP_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P1_RED_PKT_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P1_RED_PKT_DROP_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PKT_DROP_CNTR_P2 - PORT 2 RED Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PKT_DROP_CNTR_P2 :: RED_PKT_DROP_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P2_RED_PKT_DROP_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P2_RED_PKT_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P2_RED_PKT_DROP_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PKT_DROP_CNTR_P3 - PORT 3 RED Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PKT_DROP_CNTR_P3 :: RED_PKT_DROP_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P3_RED_PKT_DROP_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P3_RED_PKT_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P3_RED_PKT_DROP_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PKT_DROP_CNTR_P4 - PORT 4 RED Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PKT_DROP_CNTR_P4 :: RED_PKT_DROP_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P4_RED_PKT_DROP_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P4_RED_PKT_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P4_RED_PKT_DROP_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PKT_DROP_CNTR_P5 - PORT 5 RED Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PKT_DROP_CNTR_P5 :: RED_PKT_DROP_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P5_RED_PKT_DROP_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P5_RED_PKT_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P5_RED_PKT_DROP_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PKT_DROP_CNTR_P7 - PORT 7 RED Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PKT_DROP_CNTR_P7 :: RED_PKT_DROP_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P7_RED_PKT_DROP_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P7_RED_PKT_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_P7_RED_PKT_DROP_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_PKT_DROP_CNTR_IMP - PORT 8 RED Packet Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_PKT_DROP_CNTR_IMP :: RED_PKT_DROP_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_IMP_RED_PKT_DROP_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_IMP_RED_PKT_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_PKT_DROP_CNTR_IMP_RED_PKT_DROP_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RED_BYTE_DROP_CNTR_P0 - PORT 0 RED Byte Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P0 :: RED_BYTE_DROP_CNTR [63:00] */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P0_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P0_RED_BYTE_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P0_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RED_BYTE_DROP_CNTR_P1 - PORT 1 RED Byte Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P1 :: RED_BYTE_DROP_CNTR [63:00] */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P1_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P1_RED_BYTE_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P1_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RED_BYTE_DROP_CNTR_P2 - PORT 2 RED Byte Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P2 :: RED_BYTE_DROP_CNTR [63:00] */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P2_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P2_RED_BYTE_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P2_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RED_BYTE_DROP_CNTR_P3 - PORT 3 RED Byte Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P3 :: RED_BYTE_DROP_CNTR [63:00] */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P3_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P3_RED_BYTE_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P3_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RED_BYTE_DROP_CNTR_P4 - PORT 4 RED Byte Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P4 :: RED_BYTE_DROP_CNTR [63:00] */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P4_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P4_RED_BYTE_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P4_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RED_BYTE_DROP_CNTR_P5 - PORT 5 RED Byte Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P5 :: RED_BYTE_DROP_CNTR [63:00] */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P5_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P5_RED_BYTE_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P5_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RED_BYTE_DROP_CNTR_P7 - PORT 7 RED Byte Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_BYTE_DROP_CNTR_P7 :: RED_BYTE_DROP_CNTR [63:00] */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P7_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P7_RED_BYTE_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_P7_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *RED_BYTE_DROP_CNTR_IMP - PORT 8 RED Byte Drop Counter Register |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RED_BYTE_DROP_CNTR_IMP :: RED_BYTE_DROP_CNTR [63:00] */ |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_IMP_RED_BYTE_DROP_CNTR_MASK 0x0000000000000000 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_IMP_RED_BYTE_DROP_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RED_BYTE_DROP_CNTR_IMP_RED_BYTE_DROP_CNTR_DEFAULT 0x0000000000000000 |
| |
| /*************************************************************************** |
| *CFP_ACC - CFP Access Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_ACC :: RD_STS [31:28] */ |
| #define BCHP_SWITCH_CORE_CFP_ACC_RD_STS_MASK 0xf0000000 |
| #define BCHP_SWITCH_CORE_CFP_ACC_RD_STS_SHIFT 28 |
| #define BCHP_SWITCH_CORE_CFP_ACC_RD_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CFP_ACC :: SERCH_STS [27:27] */ |
| #define BCHP_SWITCH_CORE_CFP_ACC_SERCH_STS_MASK 0x08000000 |
| #define BCHP_SWITCH_CORE_CFP_ACC_SERCH_STS_SHIFT 27 |
| #define BCHP_SWITCH_CORE_CFP_ACC_SERCH_STS_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CFP_ACC :: SWITCH_RESV_1 [26:24] */ |
| #define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_1_MASK 0x07000000 |
| #define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_1_SHIFT 24 |
| #define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CFP_ACC :: XCESS_ADDR [23:16] */ |
| #define BCHP_SWITCH_CORE_CFP_ACC_XCESS_ADDR_MASK 0x00ff0000 |
| #define BCHP_SWITCH_CORE_CFP_ACC_XCESS_ADDR_SHIFT 16 |
| #define BCHP_SWITCH_CORE_CFP_ACC_XCESS_ADDR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CFP_ACC :: TCAM_RST [15:15] */ |
| #define BCHP_SWITCH_CORE_CFP_ACC_TCAM_RST_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_CFP_ACC_TCAM_RST_SHIFT 15 |
| #define BCHP_SWITCH_CORE_CFP_ACC_TCAM_RST_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CFP_ACC :: RAM_SEL [14:10] */ |
| #define BCHP_SWITCH_CORE_CFP_ACC_RAM_SEL_MASK 0x00007c00 |
| #define BCHP_SWITCH_CORE_CFP_ACC_RAM_SEL_SHIFT 10 |
| #define BCHP_SWITCH_CORE_CFP_ACC_RAM_SEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CFP_ACC :: SWITCH_RESV_0 [09:06] */ |
| #define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_0_MASK 0x000003c0 |
| #define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_0_SHIFT 6 |
| #define BCHP_SWITCH_CORE_CFP_ACC_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CFP_ACC :: KEY_0_1_RAW_ENC [05:05] */ |
| #define BCHP_SWITCH_CORE_CFP_ACC_KEY_0_1_RAW_ENC_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_CFP_ACC_KEY_0_1_RAW_ENC_SHIFT 5 |
| #define BCHP_SWITCH_CORE_CFP_ACC_KEY_0_1_RAW_ENC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CFP_ACC :: CFP_RAM_CLEAR [04:04] */ |
| #define BCHP_SWITCH_CORE_CFP_ACC_CFP_RAM_CLEAR_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_CFP_ACC_CFP_RAM_CLEAR_SHIFT 4 |
| #define BCHP_SWITCH_CORE_CFP_ACC_CFP_RAM_CLEAR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CFP_ACC :: OP_SEL [03:01] */ |
| #define BCHP_SWITCH_CORE_CFP_ACC_OP_SEL_MASK 0x0000000e |
| #define BCHP_SWITCH_CORE_CFP_ACC_OP_SEL_SHIFT 1 |
| #define BCHP_SWITCH_CORE_CFP_ACC_OP_SEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CFP_ACC :: OP_STR_DONE [00:00] */ |
| #define BCHP_SWITCH_CORE_CFP_ACC_OP_STR_DONE_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_CFP_ACC_OP_STR_DONE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_ACC_OP_STR_DONE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RATE_METER_GLOBAL_CTL - CFP RATE METER Global Control Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: SWITCH_RESV [15:03] */ |
| #define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_SWITCH_RESV_MASK 0x0000fff8 |
| #define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_SWITCH_RESV_SHIFT 3 |
| #define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: RATE_REFRESH_EN [02:02] */ |
| #define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_SHIFT 2 |
| #define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RATE_METER_GLOBAL_CTL :: PKT_LEN_CORR [01:00] */ |
| #define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_MASK 0x00000003 |
| #define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_DATA0 - CFP TCAM Data 0 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_DATA0 :: TCAM_DATA [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_DATA0_TCAM_DATA_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_DATA0_TCAM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_DATA0_TCAM_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_DATA1 - CFP TCAM Data 1 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_DATA1 :: TCAM_DATA [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_DATA1_TCAM_DATA_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_DATA1_TCAM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_DATA1_TCAM_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_DATA2 - CFP TCAM Data 2 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_DATA2 :: TCAM_DATA [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_DATA2_TCAM_DATA_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_DATA2_TCAM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_DATA2_TCAM_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_DATA3 - CFP TCAM Data 3 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_DATA3 :: TCAM_DATA [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_DATA3_TCAM_DATA_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_DATA3_TCAM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_DATA3_TCAM_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_DATA4 - CFP TCAM Data 4 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_DATA4 :: TCAM_DATA [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_DATA4_TCAM_DATA_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_DATA4_TCAM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_DATA4_TCAM_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_DATA5 - CFP TCAM Data 5 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_DATA5 :: TCAM_DATA [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_DATA5_TCAM_DATA_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_DATA5_TCAM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_DATA5_TCAM_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_DATA6 - CFP TCAM Data 6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_DATA6 :: TCAM_DATA [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_DATA6_TCAM_DATA_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_DATA6_TCAM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_DATA6_TCAM_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_DATA7 - CFP TCAM Data 7 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_DATA7 :: TCAM_DATA [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_DATA7_TCAM_DATA_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_DATA7_TCAM_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_DATA7_TCAM_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_MASK0 - CFP TCAM Mask 0 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_MASK0 :: TCAM_MASK [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_MASK0_TCAM_MASK_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_MASK0_TCAM_MASK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_MASK0_TCAM_MASK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_MASK1 - CFP TCAM Mask 1 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_MASK1 :: TCAM_MASK [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_MASK1_TCAM_MASK_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_MASK1_TCAM_MASK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_MASK1_TCAM_MASK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_MASK2 - CFP TCAM Mask 2 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_MASK2 :: TCAM_MASK [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_MASK2_TCAM_MASK_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_MASK2_TCAM_MASK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_MASK2_TCAM_MASK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_MASK3 - CFP TCAM Mask 3 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_MASK3 :: TCAM_MASK [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_MASK3_TCAM_MASK_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_MASK3_TCAM_MASK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_MASK3_TCAM_MASK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_MASK4 - CFP TCAM Mask 4 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_MASK4 :: TCAM_MASK [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_MASK4_TCAM_MASK_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_MASK4_TCAM_MASK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_MASK4_TCAM_MASK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_MASK5 - CFP TCAM Mask 5 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_MASK5 :: TCAM_MASK [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_MASK5_TCAM_MASK_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_MASK5_TCAM_MASK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_MASK5_TCAM_MASK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_MASK6 - CFP TCAM Mask 6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_MASK6 :: TCAM_MASK [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_MASK6_TCAM_MASK_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_MASK6_TCAM_MASK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_MASK6_TCAM_MASK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_MASK7 - CFP TCAM Mask 7 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_MASK7 :: TCAM_MASK [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_MASK7_TCAM_MASK_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_MASK7_TCAM_MASK_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_MASK7_TCAM_MASK_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ACT_POL_DATA0 - CFP Action/Policy Data 0 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ACT_POL_DATA0 :: NEW_DSCP_IB [31:26] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_DSCP_IB_MASK 0xfc000000 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_DSCP_IB_SHIFT 26 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_DSCP_IB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA0 :: CHANGE_FWRD_MAP_IB [25:24] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_MASK 0x03000000 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_SHIFT 24 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA0 :: DST_MAP_IB [23:14] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_DST_MAP_IB_MASK 0x00ffc000 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_DST_MAP_IB_SHIFT 14 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_DST_MAP_IB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA0 :: CHANGE_TC [13:13] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_TC_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_TC_SHIFT 13 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_CHANGE_TC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA0 :: NEW_TC [12:10] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_TC_MASK 0x00001c00 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_TC_SHIFT 10 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_NEW_TC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA0 :: LOOP_BK_EN [09:09] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_LOOP_BK_EN_MASK 0x00000200 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_LOOP_BK_EN_SHIFT 9 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_LOOP_BK_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA0 :: REASON_CODE [08:03] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_REASON_CODE_MASK 0x000001f8 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_REASON_CODE_SHIFT 3 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_REASON_CODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA0 :: STP_BYP [02:02] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_STP_BYP_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_STP_BYP_SHIFT 2 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_STP_BYP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA0 :: EAP_BYP [01:01] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_EAP_BYP_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_EAP_BYP_SHIFT 1 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_EAP_BYP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA0 :: VLAN_BYP [00:00] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_VLAN_BYP_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_VLAN_BYP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA0_VLAN_BYP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ACT_POL_DATA1 - CFP Action/Policy Data 1 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ACT_POL_DATA1 :: RED_DEFAULT [31:31] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_RED_DEFAULT_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_RED_DEFAULT_SHIFT 31 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_RED_DEFAULT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA1 :: NEW_COLOR [30:29] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_COLOR_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_COLOR_SHIFT 29 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_COLOR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_COLOR [28:28] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_COLOR_MASK 0x10000000 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_COLOR_SHIFT 28 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_COLOR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA1 :: CHAIN_ID [27:20] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHAIN_ID_MASK 0x0ff00000 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHAIN_ID_SHIFT 20 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHAIN_ID_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_DSCP_OB [19:19] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_OB_MASK 0x00080000 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_OB_SHIFT 19 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_OB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA1 :: NEW_DSCP_OB [18:13] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_DSCP_OB_MASK 0x0007e000 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_DSCP_OB_SHIFT 13 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_NEW_DSCP_OB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_FWRD_MAP_OB [12:11] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_MASK 0x00001800 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_SHIFT 11 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA1 :: DST_MAP_OB [10:01] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_DST_MAP_OB_MASK 0x000007fe |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_DST_MAP_OB_SHIFT 1 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_DST_MAP_OB_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA1 :: CHANGE_DSCP_IB [00:00] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_IB_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_IB_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA1_CHANGE_DSCP_IB_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ACT_POL_DATA2 - CFP Action/Policy Data 2 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: ACT_POL_DATA2 :: SWITCH_RESV [31:08] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_SWITCH_RESV_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_SWITCH_RESV_SHIFT 8 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA2 :: DEI_RMK_DISABLE [07:07] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_DEI_RMK_DISABLE_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_DEI_RMK_DISABLE_SHIFT 7 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_DEI_RMK_DISABLE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA2 :: CPCP_RMK_DISABLE [06:06] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_CPCP_RMK_DISABLE_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_CPCP_RMK_DISABLE_SHIFT 6 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_CPCP_RMK_DISABLE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA2 :: SPCP_RMK_DISABLE [05:05] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_SPCP_RMK_DISABLE_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_SPCP_RMK_DISABLE_SHIFT 5 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_SPCP_RMK_DISABLE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA2 :: NEW_TC_O [04:02] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_NEW_TC_O_MASK 0x0000001c |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_NEW_TC_O_SHIFT 2 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_NEW_TC_O_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA2 :: CHANGE_TC_O [01:01] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_CHANGE_TC_O_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_CHANGE_TC_O_SHIFT 1 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_CHANGE_TC_O_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: ACT_POL_DATA2 :: MAC_LIMIT_BYPASS [00:00] */ |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_MAC_LIMIT_BYPASS_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_MAC_LIMIT_BYPASS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_ACT_POL_DATA2_MAC_LIMIT_BYPASS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RATE_METER0 - CFP RATE METER DATA 0 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RATE_METER0 :: SWITCH_RESV [31:05] */ |
| #define BCHP_SWITCH_CORE_RATE_METER0_SWITCH_RESV_MASK 0xffffffe0 |
| #define BCHP_SWITCH_CORE_RATE_METER0_SWITCH_RESV_SHIFT 5 |
| #define BCHP_SWITCH_CORE_RATE_METER0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RATE_METER0 :: POLICER_MODE [04:03] */ |
| #define BCHP_SWITCH_CORE_RATE_METER0_POLICER_MODE_MASK 0x00000018 |
| #define BCHP_SWITCH_CORE_RATE_METER0_POLICER_MODE_SHIFT 3 |
| #define BCHP_SWITCH_CORE_RATE_METER0_POLICER_MODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RATE_METER0 :: CF [02:02] */ |
| #define BCHP_SWITCH_CORE_RATE_METER0_CF_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_RATE_METER0_CF_SHIFT 2 |
| #define BCHP_SWITCH_CORE_RATE_METER0_CF_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RATE_METER0 :: POLICER_ACTION [01:01] */ |
| #define BCHP_SWITCH_CORE_RATE_METER0_POLICER_ACTION_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_RATE_METER0_POLICER_ACTION_SHIFT 1 |
| #define BCHP_SWITCH_CORE_RATE_METER0_POLICER_ACTION_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RATE_METER0 :: CM [00:00] */ |
| #define BCHP_SWITCH_CORE_RATE_METER0_CM_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_RATE_METER0_CM_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RATE_METER0_CM_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RATE_METER1 - CFP RATE METER DATA 1 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RATE_METER1 :: SWITCH_RESV [31:23] */ |
| #define BCHP_SWITCH_CORE_RATE_METER1_SWITCH_RESV_MASK 0xff800000 |
| #define BCHP_SWITCH_CORE_RATE_METER1_SWITCH_RESV_SHIFT 23 |
| #define BCHP_SWITCH_CORE_RATE_METER1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RATE_METER1 :: EIR_TK_BKT [22:00] */ |
| #define BCHP_SWITCH_CORE_RATE_METER1_EIR_TK_BKT_MASK 0x007fffff |
| #define BCHP_SWITCH_CORE_RATE_METER1_EIR_TK_BKT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RATE_METER1_EIR_TK_BKT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RATE_METER2 - CFP RATE METER DATA 2 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RATE_METER2 :: SWITCH_RESV [31:20] */ |
| #define BCHP_SWITCH_CORE_RATE_METER2_SWITCH_RESV_MASK 0xfff00000 |
| #define BCHP_SWITCH_CORE_RATE_METER2_SWITCH_RESV_SHIFT 20 |
| #define BCHP_SWITCH_CORE_RATE_METER2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RATE_METER2 :: EIR_BKT_SIZE [19:00] */ |
| #define BCHP_SWITCH_CORE_RATE_METER2_EIR_BKT_SIZE_MASK 0x000fffff |
| #define BCHP_SWITCH_CORE_RATE_METER2_EIR_BKT_SIZE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RATE_METER2_EIR_BKT_SIZE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RATE_METER3 - CFP RATE METER DATA 3 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RATE_METER3 :: SWITCH_RESV [31:19] */ |
| #define BCHP_SWITCH_CORE_RATE_METER3_SWITCH_RESV_MASK 0xfff80000 |
| #define BCHP_SWITCH_CORE_RATE_METER3_SWITCH_RESV_SHIFT 19 |
| #define BCHP_SWITCH_CORE_RATE_METER3_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RATE_METER3 :: EIR_REF_CNT [18:00] */ |
| #define BCHP_SWITCH_CORE_RATE_METER3_EIR_REF_CNT_MASK 0x0007ffff |
| #define BCHP_SWITCH_CORE_RATE_METER3_EIR_REF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RATE_METER3_EIR_REF_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RATE_METER4 - CFP RATE METER DATA 4 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RATE_METER4 :: SWITCH_RESV [31:23] */ |
| #define BCHP_SWITCH_CORE_RATE_METER4_SWITCH_RESV_MASK 0xff800000 |
| #define BCHP_SWITCH_CORE_RATE_METER4_SWITCH_RESV_SHIFT 23 |
| #define BCHP_SWITCH_CORE_RATE_METER4_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RATE_METER4 :: CIR_TK_BKT [22:00] */ |
| #define BCHP_SWITCH_CORE_RATE_METER4_CIR_TK_BKT_MASK 0x007fffff |
| #define BCHP_SWITCH_CORE_RATE_METER4_CIR_TK_BKT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RATE_METER4_CIR_TK_BKT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RATE_METER5 - CFP RATE METER DATA 5 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RATE_METER5 :: SWITCH_RESV [31:20] */ |
| #define BCHP_SWITCH_CORE_RATE_METER5_SWITCH_RESV_MASK 0xfff00000 |
| #define BCHP_SWITCH_CORE_RATE_METER5_SWITCH_RESV_SHIFT 20 |
| #define BCHP_SWITCH_CORE_RATE_METER5_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RATE_METER5 :: CIR_BKT_SIZE [19:00] */ |
| #define BCHP_SWITCH_CORE_RATE_METER5_CIR_BKT_SIZE_MASK 0x000fffff |
| #define BCHP_SWITCH_CORE_RATE_METER5_CIR_BKT_SIZE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RATE_METER5_CIR_BKT_SIZE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RATE_METER6 - CFP RATE METER DATA 6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: RATE_METER6 :: SWITCH_RESV [31:19] */ |
| #define BCHP_SWITCH_CORE_RATE_METER6_SWITCH_RESV_MASK 0xfff80000 |
| #define BCHP_SWITCH_CORE_RATE_METER6_SWITCH_RESV_SHIFT 19 |
| #define BCHP_SWITCH_CORE_RATE_METER6_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: RATE_METER6 :: CIR_REF_CNT [18:00] */ |
| #define BCHP_SWITCH_CORE_RATE_METER6_CIR_REF_CNT_MASK 0x0007ffff |
| #define BCHP_SWITCH_CORE_RATE_METER6_CIR_REF_CNT_SHIFT 0 |
| #define BCHP_SWITCH_CORE_RATE_METER6_CIR_REF_CNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TC2COLOR - TC to COLOR Mapping Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TC2COLOR :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_TC2COLOR_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TC2COLOR_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: TC2COLOR :: SWITCH_RESV [15:11] */ |
| #define BCHP_SWITCH_CORE_TC2COLOR_SWITCH_RESV_MASK 0x0000f800 |
| #define BCHP_SWITCH_CORE_TC2COLOR_SWITCH_RESV_SHIFT 11 |
| #define BCHP_SWITCH_CORE_TC2COLOR_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_COLOR [10:09] */ |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_COLOR_MASK 0x00000600 |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_COLOR_SHIFT 9 |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_COLOR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_DEI [08:08] */ |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_DEI_MASK 0x00000100 |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_DEI_SHIFT 8 |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_DEI_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_TC [07:05] */ |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_TC_MASK 0x000000e0 |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_TC_SHIFT 5 |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_TC_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_ING_PORT [04:01] */ |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_ING_PORT_MASK 0x0000001e |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_ING_PORT_SHIFT 1 |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_ING_PORT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TC2COLOR :: TC2COLOR_MAP_RW [00:00] */ |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_RW_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_RW_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TC2COLOR_TC2COLOR_MAP_RW_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STAT_GREEN_CNTR - Policer Green color statistic counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STAT_GREEN_CNTR :: GREEN_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_STAT_GREEN_CNTR_GREEN_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_STAT_GREEN_CNTR_GREEN_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STAT_GREEN_CNTR_GREEN_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STAT_YELLOW_CNTR - Policer Yellow color statistic counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STAT_YELLOW_CNTR :: YELLOW_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR_YELLOW_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR_YELLOW_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STAT_YELLOW_CNTR_YELLOW_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STAT_RED_CNTR - Policer RED color statistic counter |
| ***************************************************************************/ |
| /* SWITCH_CORE :: STAT_RED_CNTR :: RED_CNTR [31:00] */ |
| #define BCHP_SWITCH_CORE_STAT_RED_CNTR_RED_CNTR_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_STAT_RED_CNTR_RED_CNTR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_STAT_RED_CNTR_RED_CNTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TCAM_BIST_CONTROL - TCAM BIST Control Registers (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_DONE [31:31] */ |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_DONE_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_DONE_SHIFT 31 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_DONE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_BIST_CONTROL :: SWITCH_RESV_1 [30:17] */ |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_1_MASK 0x7ffe0000 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_1_SHIFT 17 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_TEST_COMPARE [16:16] */ |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_MASK 0x00010000 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_SHIFT 16 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_SKIP_ERR_CNT [15:08] */ |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_MASK 0x0000ff00 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_SHIFT 8 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_STATUS_SEL [07:04] */ |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_MASK 0x000000f0 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_SHIFT 4 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_BIST_CONTROL :: SWITCH_RESV_0 [03:02] */ |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_0_MASK 0x0000000c |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_0_SHIFT 2 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_SEL [01:01] */ |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_SEL_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_SEL_SHIFT 1 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_SEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_BIST_CONTROL :: TCAM_BIST_EN [00:00] */ |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_EN_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_EN_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_CONTROL_TCAM_BIST_EN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TCAM_BIST_STATUS - TCAM BIST Status Registers (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TCAM_BIST_STATUS :: SWITCH_RESV [31:16] */ |
| #define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_SWITCH_RESV_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_SWITCH_RESV_SHIFT 16 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_BIST_STATUS :: TCAM_BIST_STATUS [15:00] */ |
| #define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_TCAM_BIST_STATUS_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_TCAM_BIST_STATUS_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TCAM_BIST_STATUS_TCAM_BIST_STATUS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TCAM_TEST_COMPARE_STATUS - TCAM Test Compare Status Registers (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: SWITCH_RESV_1 [31:16] */ |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_1_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_1_SHIFT 16 |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: TCAM_HIT [15:15] */ |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_SHIFT 15 |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: SWITCH_RESV_0 [14:07] */ |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_0_MASK 0x00007f80 |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_0_SHIFT 7 |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_SWITCH_RESV_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: TCAM_TEST_COMPARE_STATUS :: TCAM_HIT_ADDR [06:00] */ |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_MASK 0x0000007f |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_REG_SPARE0 - Spare 0 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_REG_SPARE0 :: CFP_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_REG_SPARE0_CFP_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_REG_SPARE0_CFP_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_REG_SPARE0_CFP_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_REG_SPARE1 - Spare 1 Register (Not2Release) |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_REG_SPARE1 :: CFP_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_CFP_REG_SPARE1_CFP_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_CFP_REG_SPARE1_CFP_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_REG_SPARE1_CFP_REG_SPARE1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CFP_CTL_REG - CFP Control Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: CFP_CTL_REG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_CFP_CTL_REG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_CFP_CTL_REG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: CFP_CTL_REG :: SWITCH_RESV [15:09] */ |
| #define BCHP_SWITCH_CORE_CFP_CTL_REG_SWITCH_RESV_MASK 0x0000fe00 |
| #define BCHP_SWITCH_CORE_CFP_CTL_REG_SWITCH_RESV_SHIFT 9 |
| #define BCHP_SWITCH_CORE_CFP_CTL_REG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: CFP_CTL_REG :: CFP_EN_MAP [08:00] */ |
| #define BCHP_SWITCH_CORE_CFP_CTL_REG_CFP_EN_MAP_MASK 0x000001ff |
| #define BCHP_SWITCH_CORE_CFP_CTL_REG_CFP_EN_MAP_SHIFT 0 |
| #define BCHP_SWITCH_CORE_CFP_CTL_REG_CFP_EN_MAP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_A_0_8_0 - UDFs of slice 0 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_A_0_8_0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_A_0_8_0 :: CFG_UDF_0_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_0_CFG_UDF_0_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_0_CFG_UDF_0_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_0_CFG_UDF_0_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_A_0_8_1 - UDFs of slice 0 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_A_0_8_1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_A_0_8_1 :: CFG_UDF_0_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_1_CFG_UDF_0_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_1_CFG_UDF_0_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_1_CFG_UDF_0_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_A_0_8_2 - UDFs of slice 0 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_A_0_8_2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_A_0_8_2 :: CFG_UDF_0_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_2_CFG_UDF_0_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_2_CFG_UDF_0_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_2_CFG_UDF_0_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_A_0_8_3 - UDFs of slice 0 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_A_0_8_3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_A_0_8_3 :: CFG_UDF_0_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_3_CFG_UDF_0_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_3_CFG_UDF_0_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_3_CFG_UDF_0_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_A_0_8_4 - UDFs of slice 0 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_A_0_8_4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_A_0_8_4 :: CFG_UDF_0_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_4_CFG_UDF_0_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_4_CFG_UDF_0_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_4_CFG_UDF_0_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_A_0_8_5 - UDFs of slice 0 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_A_0_8_5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_A_0_8_5 :: CFG_UDF_0_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_5_CFG_UDF_0_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_5_CFG_UDF_0_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_5_CFG_UDF_0_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_A_0_8_6 - UDFs of slice 0 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_A_0_8_6 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_6_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_6_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_A_0_8_6 :: CFG_UDF_0_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_6_CFG_UDF_0_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_6_CFG_UDF_0_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_6_CFG_UDF_0_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_A_0_8_7 - UDFs of slice 0 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_A_0_8_7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_A_0_8_7 :: CFG_UDF_0_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_7_CFG_UDF_0_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_7_CFG_UDF_0_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_7_CFG_UDF_0_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_A_0_8_8 - UDFs of slice 0 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_A_0_8_8 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_8_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_8_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_A_0_8_8 :: CFG_UDF_0_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_8_CFG_UDF_0_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_8_CFG_UDF_0_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_A_0_8_8_CFG_UDF_0_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_A_0_8_0 - UDFs of slice 1 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_A_0_8_0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_A_0_8_0 :: CFG_UDF_1_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_0_CFG_UDF_1_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_0_CFG_UDF_1_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_0_CFG_UDF_1_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_A_0_8_1 - UDFs of slice 1 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_A_0_8_1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_A_0_8_1 :: CFG_UDF_1_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_1_CFG_UDF_1_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_1_CFG_UDF_1_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_1_CFG_UDF_1_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_A_0_8_2 - UDFs of slice 1 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_A_0_8_2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_A_0_8_2 :: CFG_UDF_1_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_2_CFG_UDF_1_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_2_CFG_UDF_1_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_2_CFG_UDF_1_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_A_0_8_3 - UDFs of slice 1 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_A_0_8_3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_A_0_8_3 :: CFG_UDF_1_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_3_CFG_UDF_1_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_3_CFG_UDF_1_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_3_CFG_UDF_1_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_A_0_8_4 - UDFs of slice 1 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_A_0_8_4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_A_0_8_4 :: CFG_UDF_1_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_4_CFG_UDF_1_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_4_CFG_UDF_1_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_4_CFG_UDF_1_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_A_0_8_5 - UDFs of slice 1 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_A_0_8_5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_A_0_8_5 :: CFG_UDF_1_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_5_CFG_UDF_1_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_5_CFG_UDF_1_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_5_CFG_UDF_1_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_A_0_8_6 - UDFs of slice 1 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_A_0_8_6 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_6_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_6_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_A_0_8_6 :: CFG_UDF_1_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_6_CFG_UDF_1_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_6_CFG_UDF_1_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_6_CFG_UDF_1_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_A_0_8_7 - UDFs of slice 1 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_A_0_8_7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_A_0_8_7 :: CFG_UDF_1_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_7_CFG_UDF_1_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_7_CFG_UDF_1_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_7_CFG_UDF_1_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_A_0_8_8 - UDFs of slice 1 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_A_0_8_8 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_8_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_8_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_A_0_8_8 :: CFG_UDF_1_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_8_CFG_UDF_1_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_8_CFG_UDF_1_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_A_0_8_8_CFG_UDF_1_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_A_0_8_0 - UDFs of slice 2 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_A_0_8_0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_A_0_8_0 :: CFG_UDF_2_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_0_CFG_UDF_2_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_0_CFG_UDF_2_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_0_CFG_UDF_2_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_A_0_8_1 - UDFs of slice 2 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_A_0_8_1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_A_0_8_1 :: CFG_UDF_2_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_1_CFG_UDF_2_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_1_CFG_UDF_2_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_1_CFG_UDF_2_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_A_0_8_2 - UDFs of slice 2 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_A_0_8_2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_A_0_8_2 :: CFG_UDF_2_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_2_CFG_UDF_2_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_2_CFG_UDF_2_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_2_CFG_UDF_2_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_A_0_8_3 - UDFs of slice 2 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_A_0_8_3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_A_0_8_3 :: CFG_UDF_2_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_3_CFG_UDF_2_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_3_CFG_UDF_2_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_3_CFG_UDF_2_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_A_0_8_4 - UDFs of slice 2 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_A_0_8_4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_A_0_8_4 :: CFG_UDF_2_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_4_CFG_UDF_2_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_4_CFG_UDF_2_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_4_CFG_UDF_2_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_A_0_8_5 - UDFs of slice 2 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_A_0_8_5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_A_0_8_5 :: CFG_UDF_2_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_5_CFG_UDF_2_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_5_CFG_UDF_2_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_5_CFG_UDF_2_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_A_0_8_6 - UDFs of slice 2 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_A_0_8_6 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_6_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_6_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_A_0_8_6 :: CFG_UDF_2_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_6_CFG_UDF_2_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_6_CFG_UDF_2_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_6_CFG_UDF_2_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_A_0_8_7 - UDFs of slice 2 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_A_0_8_7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_A_0_8_7 :: CFG_UDF_2_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_7_CFG_UDF_2_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_7_CFG_UDF_2_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_7_CFG_UDF_2_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_A_0_8_8 - UDFs of slice 2 for IPv4 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_A_0_8_8 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_8_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_8_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_A_0_8_8 :: CFG_UDF_2_A_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_8_CFG_UDF_2_A_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_8_CFG_UDF_2_A_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_A_0_8_8_CFG_UDF_2_A_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_B_0_8_0 - UDFs of slice 0 for IPv6 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_B_0_8_0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_B_0_8_0 :: CFG_UDF_0_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_0_CFG_UDF_0_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_0_CFG_UDF_0_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_0_CFG_UDF_0_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_B_0_8_1 - UDFs of slice 0 for IPv6 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_B_0_8_1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_B_0_8_1 :: CFG_UDF_0_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_1_CFG_UDF_0_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_1_CFG_UDF_0_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_1_CFG_UDF_0_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_B_0_8_2 - UDFs of slice 0 for IPv6 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_B_0_8_2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_B_0_8_2 :: CFG_UDF_0_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_2_CFG_UDF_0_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_2_CFG_UDF_0_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_2_CFG_UDF_0_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_B_0_8_3 - UDFs of slice 0 for IPv6 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_B_0_8_3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_B_0_8_3 :: CFG_UDF_0_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_3_CFG_UDF_0_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_3_CFG_UDF_0_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_3_CFG_UDF_0_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_B_0_8_4 - UDFs of slice 0 for IPv6 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_B_0_8_4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_B_0_8_4 :: CFG_UDF_0_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_4_CFG_UDF_0_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_4_CFG_UDF_0_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_4_CFG_UDF_0_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_B_0_8_5 - UDFs of slice 0 for IPv6 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_B_0_8_5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_B_0_8_5 :: CFG_UDF_0_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_5_CFG_UDF_0_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_5_CFG_UDF_0_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_5_CFG_UDF_0_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_B_0_8_6 - UDFs of slice 0 for IPv6 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_B_0_8_6 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_6_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_6_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_B_0_8_6 :: CFG_UDF_0_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_6_CFG_UDF_0_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_6_CFG_UDF_0_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_6_CFG_UDF_0_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_B_0_8_7 - UDFs of slice 0 for IPv6 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_B_0_8_7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_B_0_8_7 :: CFG_UDF_0_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_7_CFG_UDF_0_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_7_CFG_UDF_0_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_7_CFG_UDF_0_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_B_0_8_8 - UDFs of slice 0 for IPv6 packet Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_B_0_8_8 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_8_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_8_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_B_0_8_8 :: CFG_UDF_0_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_8_CFG_UDF_0_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_8_CFG_UDF_0_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_B_0_8_8_CFG_UDF_0_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_B_0_8_0 - UDFs of slice 1 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_B_0_8_0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_B_0_8_0 :: CFG_UDF_1_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_0_CFG_UDF_1_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_0_CFG_UDF_1_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_0_CFG_UDF_1_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_B_0_8_1 - UDFs of slice 1 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_B_0_8_1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_B_0_8_1 :: CFG_UDF_1_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_1_CFG_UDF_1_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_1_CFG_UDF_1_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_1_CFG_UDF_1_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_B_0_8_2 - UDFs of slice 1 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_B_0_8_2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_B_0_8_2 :: CFG_UDF_1_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_2_CFG_UDF_1_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_2_CFG_UDF_1_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_2_CFG_UDF_1_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_B_0_8_3 - UDFs of slice 1 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_B_0_8_3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_B_0_8_3 :: CFG_UDF_1_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_3_CFG_UDF_1_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_3_CFG_UDF_1_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_3_CFG_UDF_1_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_B_0_8_4 - UDFs of slice 1 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_B_0_8_4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_B_0_8_4 :: CFG_UDF_1_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_4_CFG_UDF_1_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_4_CFG_UDF_1_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_4_CFG_UDF_1_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_B_0_8_5 - UDFs of slice 1 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_B_0_8_5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_B_0_8_5 :: CFG_UDF_1_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_5_CFG_UDF_1_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_5_CFG_UDF_1_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_5_CFG_UDF_1_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_B_0_8_6 - UDFs of slice 1 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_B_0_8_6 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_6_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_6_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_B_0_8_6 :: CFG_UDF_1_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_6_CFG_UDF_1_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_6_CFG_UDF_1_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_6_CFG_UDF_1_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_B_0_8_7 - UDFs of slice 1 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_B_0_8_7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_B_0_8_7 :: CFG_UDF_1_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_7_CFG_UDF_1_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_7_CFG_UDF_1_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_7_CFG_UDF_1_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_B_0_8_8 - UDFs of slice 1 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_B_0_8_8 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_8_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_8_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_B_0_8_8 :: CFG_UDF_1_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_8_CFG_UDF_1_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_8_CFG_UDF_1_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_B_0_8_8_CFG_UDF_1_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_B_0_8_0 - UDFs of slice 2 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_B_0_8_0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_B_0_8_0 :: CFG_UDF_2_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_0_CFG_UDF_2_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_0_CFG_UDF_2_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_0_CFG_UDF_2_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_B_0_8_1 - UDFs of slice 2 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_B_0_8_1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_B_0_8_1 :: CFG_UDF_2_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_1_CFG_UDF_2_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_1_CFG_UDF_2_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_1_CFG_UDF_2_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_B_0_8_2 - UDFs of slice 2 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_B_0_8_2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_B_0_8_2 :: CFG_UDF_2_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_2_CFG_UDF_2_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_2_CFG_UDF_2_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_2_CFG_UDF_2_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_B_0_8_3 - UDFs of slice 2 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_B_0_8_3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_B_0_8_3 :: CFG_UDF_2_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_3_CFG_UDF_2_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_3_CFG_UDF_2_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_3_CFG_UDF_2_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_B_0_8_4 - UDFs of slice 2 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_B_0_8_4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_B_0_8_4 :: CFG_UDF_2_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_4_CFG_UDF_2_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_4_CFG_UDF_2_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_4_CFG_UDF_2_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_B_0_8_5 - UDFs of slice 2 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_B_0_8_5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_B_0_8_5 :: CFG_UDF_2_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_5_CFG_UDF_2_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_5_CFG_UDF_2_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_5_CFG_UDF_2_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_B_0_8_6 - UDFs of slice 2 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_B_0_8_6 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_6_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_6_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_B_0_8_6 :: CFG_UDF_2_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_6_CFG_UDF_2_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_6_CFG_UDF_2_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_6_CFG_UDF_2_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_B_0_8_7 - UDFs of slice 2 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_B_0_8_7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_B_0_8_7 :: CFG_UDF_2_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_7_CFG_UDF_2_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_7_CFG_UDF_2_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_7_CFG_UDF_2_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_B_0_8_8 - UDFs of slice 2 for IPv6 Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_B_0_8_8 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_8_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_8_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_B_0_8_8 :: CFG_UDF_2_B_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_8_CFG_UDF_2_B_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_8_CFG_UDF_2_B_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_B_0_8_8_CFG_UDF_2_B_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_C_0_8_0 - UDFs of slice 0 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_C_0_8_0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_C_0_8_0 :: CFG_UDF_0_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_0_CFG_UDF_0_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_0_CFG_UDF_0_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_0_CFG_UDF_0_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_C_0_8_1 - UDFs of slice 0 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_C_0_8_1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_C_0_8_1 :: CFG_UDF_0_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_1_CFG_UDF_0_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_1_CFG_UDF_0_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_1_CFG_UDF_0_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_C_0_8_2 - UDFs of slice 0 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_C_0_8_2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_C_0_8_2 :: CFG_UDF_0_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_2_CFG_UDF_0_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_2_CFG_UDF_0_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_2_CFG_UDF_0_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_C_0_8_3 - UDFs of slice 0 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_C_0_8_3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_C_0_8_3 :: CFG_UDF_0_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_3_CFG_UDF_0_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_3_CFG_UDF_0_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_3_CFG_UDF_0_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_C_0_8_4 - UDFs of slice 0 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_C_0_8_4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_C_0_8_4 :: CFG_UDF_0_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_4_CFG_UDF_0_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_4_CFG_UDF_0_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_4_CFG_UDF_0_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_C_0_8_5 - UDFs of slice 0 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_C_0_8_5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_C_0_8_5 :: CFG_UDF_0_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_5_CFG_UDF_0_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_5_CFG_UDF_0_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_5_CFG_UDF_0_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_C_0_8_6 - UDFs of slice 0 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_C_0_8_6 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_6_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_6_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_C_0_8_6 :: CFG_UDF_0_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_6_CFG_UDF_0_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_6_CFG_UDF_0_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_6_CFG_UDF_0_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_C_0_8_7 - UDFs of slice 0 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_C_0_8_7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_C_0_8_7 :: CFG_UDF_0_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_7_CFG_UDF_0_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_7_CFG_UDF_0_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_7_CFG_UDF_0_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_C_0_8_8 - UDFs of slice 0 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_C_0_8_8 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_8_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_8_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_C_0_8_8 :: CFG_UDF_0_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_8_CFG_UDF_0_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_8_CFG_UDF_0_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_C_0_8_8_CFG_UDF_0_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_C_0_8_0 - UDFs of slice 1 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_C_0_8_0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_C_0_8_0 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_0_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_0_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_0_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_C_0_8_1 - UDFs of slice 1 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_C_0_8_1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_C_0_8_1 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_1_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_1_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_1_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_C_0_8_2 - UDFs of slice 1 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_C_0_8_2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_C_0_8_2 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_2_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_2_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_2_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_C_0_8_3 - UDFs of slice 1 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_C_0_8_3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_C_0_8_3 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_3_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_3_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_3_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_C_0_8_4 - UDFs of slice 1 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_C_0_8_4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_C_0_8_4 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_4_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_4_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_4_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_C_0_8_5 - UDFs of slice 1 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_C_0_8_5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_C_0_8_5 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_5_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_5_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_5_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_C_0_8_6 - UDFs of slice 1 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_C_0_8_6 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_6_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_6_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_C_0_8_6 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_6_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_6_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_6_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_C_0_8_7 - UDFs of slice 1 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_C_0_8_7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_C_0_8_7 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_7_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_7_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_7_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_1_C_0_8_8 - UDFs of slice 1 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_1_C_0_8_8 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_8_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_8_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_1_C_0_8_8 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_8_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_8_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_1_C_0_8_8_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_C_0_8_0 - UDFs of slice 2 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_C_0_8_0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_C_0_8_0 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_0_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_0_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_0_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_C_0_8_1 - UDFs of slice 2 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_C_0_8_1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_C_0_8_1 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_1_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_1_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_1_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_C_0_8_2 - UDFs of slice 2 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_C_0_8_2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_C_0_8_2 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_2_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_2_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_2_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_C_0_8_3 - UDFs of slice 2 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_C_0_8_3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_C_0_8_3 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_3_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_3_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_3_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_C_0_8_4 - UDFs of slice 2 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_C_0_8_4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_C_0_8_4 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_4_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_4_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_4_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_C_0_8_5 - UDFs of slice 2 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_C_0_8_5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_C_0_8_5 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_5_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_5_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_5_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_C_0_8_6 - UDFs of slice 2 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_C_0_8_6 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_6_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_6_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_C_0_8_6 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_6_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_6_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_6_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_C_0_8_7 - UDFs of slice 2 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_C_0_8_7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_C_0_8_7 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_7_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_7_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_7_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_2_C_0_8_8 - UDFs of slice 2 for none-IP Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_2_C_0_8_8 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_8_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_8_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_2_C_0_8_8 :: CFG_UDF_1_C_0_8 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_8_CFG_UDF_1_C_0_8_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_8_CFG_UDF_1_C_0_8_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_2_C_0_8_8_CFG_UDF_1_C_0_8_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_D_0_11_0 - UDFs for IPv6 Chain Rule Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_D_0_11_0 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_0_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_0_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_D_0_11_0 :: CFG_UDF_0_D_0_11 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_0_CFG_UDF_0_D_0_11_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_0_CFG_UDF_0_D_0_11_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_0_CFG_UDF_0_D_0_11_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_D_0_11_1 - UDFs for IPv6 Chain Rule Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_D_0_11_1 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_1_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_1_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_D_0_11_1 :: CFG_UDF_0_D_0_11 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_1_CFG_UDF_0_D_0_11_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_1_CFG_UDF_0_D_0_11_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_1_CFG_UDF_0_D_0_11_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_D_0_11_2 - UDFs for IPv6 Chain Rule Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_D_0_11_2 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_2_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_2_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_D_0_11_2 :: CFG_UDF_0_D_0_11 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_2_CFG_UDF_0_D_0_11_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_2_CFG_UDF_0_D_0_11_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_2_CFG_UDF_0_D_0_11_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_D_0_11_3 - UDFs for IPv6 Chain Rule Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_D_0_11_3 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_3_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_3_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_D_0_11_3 :: CFG_UDF_0_D_0_11 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_3_CFG_UDF_0_D_0_11_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_3_CFG_UDF_0_D_0_11_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_3_CFG_UDF_0_D_0_11_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_D_0_11_4 - UDFs for IPv6 Chain Rule Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_D_0_11_4 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_4_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_4_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_D_0_11_4 :: CFG_UDF_0_D_0_11 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_4_CFG_UDF_0_D_0_11_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_4_CFG_UDF_0_D_0_11_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_4_CFG_UDF_0_D_0_11_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_D_0_11_5 - UDFs for IPv6 Chain Rule Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_D_0_11_5 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_5_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_5_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_D_0_11_5 :: CFG_UDF_0_D_0_11 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_5_CFG_UDF_0_D_0_11_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_5_CFG_UDF_0_D_0_11_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_5_CFG_UDF_0_D_0_11_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_D_0_11_6 - UDFs for IPv6 Chain Rule Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_D_0_11_6 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_6_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_6_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_D_0_11_6 :: CFG_UDF_0_D_0_11 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_6_CFG_UDF_0_D_0_11_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_6_CFG_UDF_0_D_0_11_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_6_CFG_UDF_0_D_0_11_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_D_0_11_7 - UDFs for IPv6 Chain Rule Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_D_0_11_7 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_7_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_7_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_D_0_11_7 :: CFG_UDF_0_D_0_11 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_7_CFG_UDF_0_D_0_11_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_7_CFG_UDF_0_D_0_11_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_7_CFG_UDF_0_D_0_11_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_D_0_11_8 - UDFs for IPv6 Chain Rule Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_D_0_11_8 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_8_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_8_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_D_0_11_8 :: CFG_UDF_0_D_0_11 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_8_CFG_UDF_0_D_0_11_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_8_CFG_UDF_0_D_0_11_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_8_CFG_UDF_0_D_0_11_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_D_0_11_9 - UDFs for IPv6 Chain Rule Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_D_0_11_9 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_9_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_9_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_D_0_11_9 :: CFG_UDF_0_D_0_11 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_9_CFG_UDF_0_D_0_11_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_9_CFG_UDF_0_D_0_11_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_9_CFG_UDF_0_D_0_11_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_D_0_11_10 - UDFs for IPv6 Chain Rule Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_D_0_11_10 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_10_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_10_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_D_0_11_10 :: CFG_UDF_0_D_0_11 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_10_CFG_UDF_0_D_0_11_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_10_CFG_UDF_0_D_0_11_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_10_CFG_UDF_0_D_0_11_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UDF_0_D_0_11_11 - UDFs for IPv6 Chain Rule Registers |
| ***************************************************************************/ |
| /* SWITCH_CORE :: UDF_0_D_0_11_11 :: reserved_for_padding0 [31:08] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_11_reserved_for_padding0_MASK 0xffffff00 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_11_reserved_for_padding0_SHIFT 8 |
| |
| /* SWITCH_CORE :: UDF_0_D_0_11_11 :: CFG_UDF_0_D_0_11 [07:00] */ |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_11_CFG_UDF_0_D_0_11_MASK 0x000000ff |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_11_CFG_UDF_0_D_0_11_SHIFT 0 |
| #define BCHP_SWITCH_CORE_UDF_0_D_0_11_11_CFG_UDF_0_D_0_11_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_CTL_REG - CPU OTP Control RegistersNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OTP_CTL_REG :: BYPASS_OTP_CLK [31:31] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_BYPASS_OTP_CLK_MASK 0x80000000 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_BYPASS_OTP_CLK_SHIFT 31 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_BYPASS_OTP_CLK_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: SWITCH_RESV [30:29] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_SWITCH_RESV_MASK 0x60000000 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_SWITCH_RESV_SHIFT 29 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: CPU_DEBUG_SEL [28:25] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_CPU_DEBUG_SEL_MASK 0x1e000000 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_CPU_DEBUG_SEL_SHIFT 25 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_CPU_DEBUG_SEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: BURST_STAT_SEL [24:24] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_BURST_STAT_SEL_MASK 0x01000000 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_BURST_STAT_SEL_SHIFT 24 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_BURST_STAT_SEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: ACCESS_MODE [23:22] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_ACCESS_MODE_MASK 0x00c00000 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_ACCESS_MODE_SHIFT 22 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_ACCESS_MODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: OTP_PROG_EN [21:21] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_PROG_EN_MASK 0x00200000 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_PROG_EN_SHIFT 21 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_PROG_EN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: OTP_DEBUG_MODE [20:20] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_DEBUG_MODE_MASK 0x00100000 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_DEBUG_MODE_SHIFT 20 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_OTP_DEBUG_MODE_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: WRP_CONTINUE_ON_FAIL [19:19] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_CONTINUE_ON_FAIL_MASK 0x00080000 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_CONTINUE_ON_FAIL_SHIFT 19 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_CONTINUE_ON_FAIL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: WRP_TIME_MARGIN [18:16] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_TIME_MARGIN_MASK 0x00070000 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_TIME_MARGIN_SHIFT 16 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_TIME_MARGIN_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: WRP_SADBYP [15:15] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_SADBYP_MASK 0x00008000 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_SADBYP_SHIFT 15 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_SADBYP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: UNUSED [14:14] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_UNUSED_MASK 0x00004000 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_UNUSED_SHIFT 14 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_UNUSED_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: WRP_PBYP [13:13] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PBYP_MASK 0x00002000 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PBYP_SHIFT 13 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PBYP_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: WRP_PCOUNT [12:10] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PCOUNT_MASK 0x00001c00 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PCOUNT_SHIFT 10 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PCOUNT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: WRP_VSEL [09:06] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_VSEL_MASK 0x000003c0 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_VSEL_SHIFT 6 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_VSEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: WRP_PROG_SEL [05:05] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PROG_SEL_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PROG_SEL_SHIFT 5 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_WRP_PROG_SEL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: COMMAND [04:01] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_COMMAND_MASK 0x0000001e |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_COMMAND_SHIFT 1 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_COMMAND_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_CTL_REG :: START [00:00] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_START_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_START_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_START_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_ADDR_REG - CPU OTP Address RegistersNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OTP_ADDR_REG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_OTP_ADDR_REG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_OTP_ADDR_REG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: OTP_ADDR_REG :: CPU_ADDR [15:00] */ |
| #define BCHP_SWITCH_CORE_OTP_ADDR_REG_CPU_ADDR_MASK 0x0000ffff |
| #define BCHP_SWITCH_CORE_OTP_ADDR_REG_CPU_ADDR_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OTP_ADDR_REG_CPU_ADDR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_STS_REG - CPU OTP Status RegistersNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OTP_STS_REG :: reserved_for_padding0 [31:16] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_reserved_for_padding0_MASK 0xffff0000 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_reserved_for_padding0_SHIFT 16 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: UNUSED_0 [15:12] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_0_MASK 0x0000f000 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_0_SHIFT 12 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_0_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: CONTROL_ERR [11:11] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_CONTROL_ERR_MASK 0x00000800 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_CONTROL_ERR_SHIFT 11 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_CONTROL_ERR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: WRP_ERROR [10:10] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_ERROR_MASK 0x00000400 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_ERROR_SHIFT 10 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_ERROR_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: INVALID_COMMAND [09:09] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_COMMAND_MASK 0x00000200 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_COMMAND_SHIFT 9 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_COMMAND_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: UNUSED_1 [08:08] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_1_MASK 0x00000100 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_1_SHIFT 8 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_UNUSED_1_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: INIT_WAIT_DONE [07:07] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_INIT_WAIT_DONE_MASK 0x00000080 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_INIT_WAIT_DONE_SHIFT 7 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_INIT_WAIT_DONE_DEFAULT 0x00000001 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: PROG_BLOCKED [06:06] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_PROG_BLOCKED_MASK 0x00000040 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_PROG_BLOCKED_SHIFT 6 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_PROG_BLOCKED_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: INVALID_PROG_REQ [05:05] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_PROG_REQ_MASK 0x00000020 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_PROG_REQ_SHIFT 5 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_INVALID_PROG_REQ_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: WRP_FAIL [04:04] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_FAIL_MASK 0x00000010 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_FAIL_SHIFT 4 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_FAIL_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: WRP_BUSY [03:03] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_BUSY_MASK 0x00000008 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_BUSY_SHIFT 3 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_BUSY_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: WRP_DOUT [02:02] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DOUT_MASK 0x00000004 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DOUT_SHIFT 2 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DOUT_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: WRP_DATA_READY [01:01] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DATA_READY_MASK 0x00000002 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DATA_READY_SHIFT 1 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_WRP_DATA_READY_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: OTP_STS_REG :: COMMAND_DONE [00:00] */ |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_COMMAND_DONE_MASK 0x00000001 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_COMMAND_DONE_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OTP_STS_REG_COMMAND_DONE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_WR_DATA - CPU OTP Write Data RegistersNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OTP_WR_DATA :: CPU_WR_DATA [31:00] */ |
| #define BCHP_SWITCH_CORE_OTP_WR_DATA_CPU_WR_DATA_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_OTP_WR_DATA_CPU_WR_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OTP_WR_DATA_CPU_WR_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_RD_DATA - CPU OTP Read Data RegistersNot2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OTP_RD_DATA :: CPU_RD_DATA [31:00] */ |
| #define BCHP_SWITCH_CORE_OTP_RD_DATA_CPU_RD_DATA_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_OTP_RD_DATA_CPU_RD_DATA_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OTP_RD_DATA_CPU_RD_DATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IO_SR_CTL - I/O Pad Slew Rate Control Register (Engineering use only)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IO_SR_CTL :: SWITCH_RESV [31:19] */ |
| #define BCHP_SWITCH_CORE_IO_SR_CTL_SWITCH_RESV_MASK 0xfff80000 |
| #define BCHP_SWITCH_CORE_IO_SR_CTL_SWITCH_RESV_SHIFT 19 |
| #define BCHP_SWITCH_CORE_IO_SR_CTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IO_SR_CTL :: IO_SR_CTL [18:00] */ |
| #define BCHP_SWITCH_CORE_IO_SR_CTL_IO_SR_CTL_MASK 0x0007ffff |
| #define BCHP_SWITCH_CORE_IO_SR_CTL_IO_SR_CTL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IO_SR_CTL_IO_SR_CTL_DEFAULT 0x00000600 |
| |
| /*************************************************************************** |
| *IO_DS_SEL0 - I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IO_DS_SEL0 :: SWITCH_RESV [31:19] */ |
| #define BCHP_SWITCH_CORE_IO_DS_SEL0_SWITCH_RESV_MASK 0xfff80000 |
| #define BCHP_SWITCH_CORE_IO_DS_SEL0_SWITCH_RESV_SHIFT 19 |
| #define BCHP_SWITCH_CORE_IO_DS_SEL0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IO_DS_SEL0 :: IO_DS_SEL0 [18:00] */ |
| #define BCHP_SWITCH_CORE_IO_DS_SEL0_IO_DS_SEL0_MASK 0x0007ffff |
| #define BCHP_SWITCH_CORE_IO_DS_SEL0_IO_DS_SEL0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IO_DS_SEL0_IO_DS_SEL0_DEFAULT 0x0007ffff |
| |
| /*************************************************************************** |
| *IO_DS_SEL2 - I/O Pad Drive Strength Select 2 Register (Engineering use only)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: IO_DS_SEL2 :: SWITCH_RESV [31:19] */ |
| #define BCHP_SWITCH_CORE_IO_DS_SEL2_SWITCH_RESV_MASK 0xfff80000 |
| #define BCHP_SWITCH_CORE_IO_DS_SEL2_SWITCH_RESV_SHIFT 19 |
| #define BCHP_SWITCH_CORE_IO_DS_SEL2_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: IO_DS_SEL2 :: IO_DS_SEL2 [18:00] */ |
| #define BCHP_SWITCH_CORE_IO_DS_SEL2_IO_DS_SEL2_MASK 0x0007ffff |
| #define BCHP_SWITCH_CORE_IO_DS_SEL2_IO_DS_SEL2_SHIFT 0 |
| #define BCHP_SWITCH_CORE_IO_DS_SEL2_IO_DS_SEL2_DEFAULT 0x0007ffff |
| |
| /*************************************************************************** |
| *GMII_IO_SR_CTL - GMII I/O Pad Slew Rate Control Register (Engineering use only)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: GMII_IO_SR_CTL :: SWITCH_RESV [31:03] */ |
| #define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_SWITCH_RESV_MASK 0xfffffff8 |
| #define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_SWITCH_RESV_SHIFT 3 |
| #define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: GMII_IO_SR_CTL :: GMII_IO_SR_CTL [02:00] */ |
| #define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_GMII_IO_SR_CTL_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_GMII_IO_SR_CTL_SHIFT 0 |
| #define BCHP_SWITCH_CORE_GMII_IO_SR_CTL_GMII_IO_SR_CTL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GMII_IO_DS_SEL0 - GMII I/O Pad Drive Strength Select 0 Register (Engineering use only)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: GMII_IO_DS_SEL0 :: SWITCH_RESV [31:03] */ |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_SWITCH_RESV_MASK 0xfffffff8 |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_SWITCH_RESV_SHIFT 3 |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: GMII_IO_DS_SEL0 :: GMII_IO_DS_SEL0 [02:00] */ |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_GMII_IO_DS_SEL0_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_GMII_IO_DS_SEL0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL0_GMII_IO_DS_SEL0_DEFAULT 0x00000007 |
| |
| /*************************************************************************** |
| *GMII_IO_DS_SEL1 - GMII I/O Pad Drive Strength Select 1 Register (Engineering use only)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: GMII_IO_DS_SEL1 :: SWITCH_RESV [31:03] */ |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_SWITCH_RESV_MASK 0xfffffff8 |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_SWITCH_RESV_SHIFT 3 |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_SWITCH_RESV_DEFAULT 0x00000000 |
| |
| /* SWITCH_CORE :: GMII_IO_DS_SEL1 :: GMII_IO_DS_SEL1 [02:00] */ |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_GMII_IO_DS_SEL1_MASK 0x00000007 |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_GMII_IO_DS_SEL1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_GMII_IO_DS_SEL1_GMII_IO_DS_SEL1_DEFAULT 0x00000007 |
| |
| /*************************************************************************** |
| *OTP_CTL_REG_SPARE0 - Spare 0 Register (Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OTP_CTL_REG_SPARE0 :: OTP_CTL_REG_SPARE0 [31:00] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0_OTP_CTL_REG_SPARE0_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0_OTP_CTL_REG_SPARE0_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE0_OTP_CTL_REG_SPARE0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_CTL_REG_SPARE1 - Spare 1 Register (Not2Release)Not2Release |
| ***************************************************************************/ |
| /* SWITCH_CORE :: OTP_CTL_REG_SPARE1 :: OTP_CTL_REG_SPARE1 [31:00] */ |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1_OTP_CTL_REG_SPARE1_MASK 0xffffffff |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1_OTP_CTL_REG_SPARE1_SHIFT 0 |
| #define BCHP_SWITCH_CORE_OTP_CTL_REG_SPARE1_OTP_CTL_REG_SPARE1_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_SWITCH_CORE_H__ */ |
| |
| /* End of File */ |
