| /*************************************************************************** |
| * Copyright (c) 1999-2014, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Wed Sep 3 11:52:58 2014 |
| * Full Compile MD5 Checksum 4a20c0e31b928020bbfa96c583b9e661 |
| * (minus title and desc) |
| * MD5 Checksum 077c6f684bcabb645ae9da4069fea8e4 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008005 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_SUN_TOP_CTRL_H__ |
| #define BCHP_SUN_TOP_CTRL_H__ |
| |
| /*************************************************************************** |
| *SUN_TOP_CTRL - Top Control registers |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID 0x00404000 /* Chip family ID */ |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID 0x00404004 /* Product Revision ID */ |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0 0x0040401c /* Strapping values */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1 0x00404020 /* Strapping values */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS 0x00404024 /* Bond option value register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0 0x00404028 /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1 0x0040402c /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0 0x00404030 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1 0x00404034 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0 0x00404038 /* Semaphore channel 0 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1 0x0040403c /* Semaphore channel 1 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2 0x00404040 /* Semaphore channel 2 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3 0x00404044 /* Semaphore channel 3 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4 0x00404048 /* Semaphore channel 4 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5 0x0040404c /* Semaphore channel 5 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6 0x00404050 /* Semaphore channel 6 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7 0x00404054 /* Semaphore channel 7 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8 0x00404058 /* Semaphore channel 8 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9 0x0040405c /* Semaphore channel 9 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10 0x00404060 /* Semaphore channel 10 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11 0x00404064 /* Semaphore channel 11 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12 0x00404068 /* Semaphore channel 12 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13 0x0040406c /* Semaphore channel 13 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14 0x00404070 /* Semaphore channel 14 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15 0x00404074 /* Semaphore channel 15 */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0 0x00404078 /* General watchdog timer 0 */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1 0x0040407c /* General watchdog timer 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 0x00404080 /* General control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1 0x00404084 /* General control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2 0x00404088 /* General control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3 0x0040408c /* General control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4 0x00404090 /* General control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5 0x00404094 /* General control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0 0x00404098 /* General status register 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1 0x0040409c /* General status register 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2 0x004040a0 /* General status register 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3 0x004040bc /* General status register 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4 0x004040c0 /* General status register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x00404100 /* Pinmux control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1 0x00404104 /* Pinmux control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2 0x00404108 /* Pinmux control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3 0x0040410c /* Pinmux control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4 0x00404110 /* Pinmux control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5 0x00404114 /* Pinmux control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6 0x00404118 /* Pinmux control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7 0x0040411c /* Pinmux control register 7 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8 0x00404120 /* Pinmux control register 8 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9 0x00404124 /* Pinmux control register 9 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10 0x00404128 /* Pinmux control register 10 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11 0x0040412c /* Pinmux control register 11 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12 0x00404130 /* Pinmux control register 12 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13 0x00404134 /* Pinmux control register 13 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14 0x00404138 /* Pinmux control register 14 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15 0x0040413c /* Pinmux control register 15 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16 0x00404140 /* Pinmux control register 16 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17 0x00404144 /* Pinmux control register 17 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18 0x00404148 /* Pinmux control register 18 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19 0x0040414c /* Pinmux control register 19 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20 0x00404150 /* Pinmux control register 20 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21 0x00404154 /* Pinmux control register 21 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22 0x00404158 /* Pinmux control register 22 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0 0x0040415c /* Pad pull-up/pull-down control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1 0x00404160 /* Pad pull-up/pull-down control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2 0x00404164 /* Pad pull-up/pull-down control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3 0x00404168 /* Pad pull-up/pull-down control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4 0x0040416c /* Pad pull-up/pull-down control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5 0x00404170 /* Pad pull-up/pull-down control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6 0x00404174 /* Pad pull-up/pull-down control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7 0x00404178 /* Pad pull-up/pull-down control register 7 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8 0x0040417c /* Pad pull-up/pull-down control register 8 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9 0x00404180 /* Pad pull-up/pull-down control register 9 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10 0x00404184 /* Pad pull-up/pull-down control register 10 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11 0x00404188 /* Pad pull-up/pull-down control register 11 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12 0x0040418c /* Pad pull-up/pull-down control register 12 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13 0x00404190 /* Pad pull-up/pull-down control register 13 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14 0x00404194 /* Pad pull-up/pull-down control register 14 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_15 0x00404198 /* Pad pull-up/pull-down control register 15 */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0 0x0040419c /* Bypass clock unselect register 0 */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL 0x00404300 /* Reset control */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE 0x00404304 /* Reset source enable */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET 0x00404308 /* Software master reset */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION 0x0040430c /* Hardware reset extension */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR 0x00404310 /* Reset Monitor */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY 0x00404314 /* Reset history */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET 0x00404318 /* Software init 0 set */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR 0x0040431c /* Software init 0 clear */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS 0x00404320 /* Software init 0 status */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR 0x00404324 /* Security software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET 0x00404330 /* Software init 1 set */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR 0x00404334 /* Software init 1 clear */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS 0x00404338 /* Software init 1 status */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR 0x0040433c /* Security software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */ |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH 0x00404364 /* Scratch register */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL 0x00404368 /* Spare control bits reserved for future use */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL 0x00404380 /* Test port control */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK 0x00404384 /* Testport peek register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE 0x00404388 /* Testport poke register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK 0x0040438c /* Testport peek register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE 0x00404390 /* Testport poke register */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN 0x00404394 /* EJTAG input bus enables */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL 0x00404398 /* EJTAG output select */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL 0x004043a0 /* VTRAP Control */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS 0x004043a4 /* VTRAP Status */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0 0x004043a8 /* UART Router select 0 */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1 0x004043ac /* UART Router select 1 */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG 0x00404400 /* Serial Slave Port configuration register */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV 0x00404420 /* SERS Revision Register */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG 0x00404424 /* SERS Configuration Register */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL 0x00404514 /* Block select for RO testmode */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION 0x00404518 /* Test configuration */ |
| |
| /*************************************************************************** |
| *CHIP_FAMILY_ID - Chip family ID |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT 0x74450030 |
| |
| /*************************************************************************** |
| *PRODUCT_ID - Product Revision ID |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT 0x74450030 |
| |
| /*************************************************************************** |
| *BSP_FEATURE_TABLE_ADDR - BSP feature table address |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STRAP_VALUE_0 - Strapping values |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:11] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK 0xfffff800 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie_rc_ep [08:07] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_rc_ep_MASK 0x00000180 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_rc_ep_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_rc_ep_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie_sata_combo_sel [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_sata_combo_sel_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_sata_combo_sel_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_sata_combo_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [05:01] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK 0x0000003e |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STRAP_VALUE_1 - Strapping values |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK 0xffffffe0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [04:01] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK 0x0000001e |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_DEFAULT 0x00000004 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *BOND_STATUS - Bond option value register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_0 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pcie0_disable [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_4kx2k_disable [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_pass_thru_disable [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_pass_thru_disable_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_pass_thru_disable_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_pass_thru_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_rx_disable [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rv9_disable [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [20:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK 0x001e0000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_memsys_2_disable [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memsys_2_disable_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memsys_2_disable_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memsys_2_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_memsys_1_disable [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memsys_1_disable_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memsys_1_disable_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memsys_1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hvd2_disable [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd2_disable_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd2_disable_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd2_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hvd1_disable [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd1_disable_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd1_disable_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hvd0_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vice2_1_disable [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_1_disable_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_1_disable_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vice2_0_disable [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_0_disable_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_0_disable_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK 0x00000060 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_1 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_cpus_to_use [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_cpus_to_use_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_cpus_to_use_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_cpus_to_use_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hdcp22_disable [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pcie1_disable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rfm_disable [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb3_disable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb2_disable [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb1_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb0_disable [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca2_disable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_0 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pcie0_disable [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie0_disable_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie0_disable_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_4kx2k_disable [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_pass_thru_disable [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_pass_thru_disable_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_pass_thru_disable_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_rx_disable [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rv9_disable [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [20:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK 0x001e0000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_memsys_2_disable [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_memsys_2_disable_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_memsys_2_disable_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_memsys_1_disable [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_memsys_1_disable_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_memsys_1_disable_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hvd2_disable [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd2_disable_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd2_disable_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hvd1_disable [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd1_disable_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd1_disable_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hvd0_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vice2_1_disable [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vice2_1_disable_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vice2_1_disable_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vice2_0_disable [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vice2_0_disable_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vice2_0_disable_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_1 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_cpus_to_use [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_cpus_to_use_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_cpus_to_use_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_cpus_to_use_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hdcp22_disable [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pcie1_disable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie1_disable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie1_disable_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rfm_disable [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb3_disable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb2_disable [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb1_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb0_disable [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca2_disable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca2_disable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca2_disable_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_0 - Semaphore channel 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_1 - Semaphore channel 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_2 - Semaphore channel 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_3 - Semaphore channel 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_4 - Semaphore channel 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_5 - Semaphore channel 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_6 - Semaphore channel 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_7 - Semaphore channel 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_8 - Semaphore channel 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_9 - Semaphore channel 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_10 - Semaphore channel 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_11 - Semaphore channel 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_12 - Semaphore channel 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_13 - Semaphore channel 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_14 - Semaphore channel 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_15 - Semaphore channel 15 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GEN_WATCHDOG_0 - General watchdog timer 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GEN_WATCHDOG_1 - General watchdog timer 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_0 - General control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_1_pd [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_0_pd [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_1_pad_modehv_override [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_0_pad_modehv_override [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio0_pin_sel [04:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_pin_sel_MASK 0x00000018 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_pin_sel_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio0_pin_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio1_pin_sel [02:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio1_pin_sel_MASK 0x00000006 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio1_pin_sel_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio1_pin_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_1 - General control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_2 - General control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_3 - General control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_4 - General control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_5 - General control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_0 - General status register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: ebi_pad_config [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_1 - General status register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_1_pad_vddo [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_0_pad_vddo [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_2 - General status register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK 0xfffc0000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_amp_en [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel_gmii [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_gmii_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_gmii_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_gmii_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_modehv [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_modehv_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_modehv_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_modehv_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel [14:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_MASK 0x00007000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_amp_en [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_amp_en_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel_gmii [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_gmii_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_modehv [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_modehv_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_sel [08:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_MASK 0x000001c0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_amp_en [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel_gmii [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_modehv [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_16MA 7 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_059 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_059_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_058 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_058_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_057 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_056 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_055 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_054 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_053 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_052 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_051 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_050 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_049 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_048 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_047 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_046 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_045 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_044 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_043 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_042 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_041 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_040 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_039 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_038 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_037 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_036 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_035 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_034 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_033 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_032 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_slew [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_sel [26:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_MASK 0x07000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_src [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_sel [22:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_MASK 0x00700000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_src [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_sel [18:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_MASK 0x00070000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_src [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_sel [14:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_MASK 0x00007000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_src [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_sel [10:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_MASK 0x00000700 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_src [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_sel [06:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_MASK 0x00000070 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_src [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_16MA 7 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: egphy_test_pin_mux_sel [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_3 - General status register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: cpu_system_counter [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_4 - General status register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: cpu_system_counter [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_0 - Pinmux control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_07 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_EBI_DATA_07 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_07_ALT_TP_IN_07 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_06 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_EBI_DATA_06 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_06_ALT_TP_IN_06 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_05 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_EBI_DATA_05 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_05_ALT_TP_IN_05 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_04 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_EBI_DATA_04 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_04_ALT_TP_IN_04 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_03 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_EBI_DATA_03 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_03_ALT_TP_IN_03 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_02 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_EBI_DATA_02 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_02_ALT_TP_IN_02 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_01 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_EBI_DATA_01 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_01_ALT_TP_IN_01 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: ebi_data_00 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_EBI_DATA_00 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_ebi_data_00_ALT_TP_IN_00 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_1 - Pinmux control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_15 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_EBI_DATA_15 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_15_ALT_TP_IN_15 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_14 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_EBI_DATA_14 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_14_ALT_TP_IN_14 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_13 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_EBI_DATA_13 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_13_ALT_TP_IN_13 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_12 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_EBI_DATA_12 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_12_ALT_TP_IN_12 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_11 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_EBI_DATA_11 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_11_ALT_TP_IN_11 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_10 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_EBI_DATA_10 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_10_ALT_TP_IN_10 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_09 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_EBI_DATA_09 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_09_ALT_TP_IN_09 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_08 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_EBI_DATA_08 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_08_ALT_TP_IN_08 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_2 - Pinmux control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_07 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_EBI_ADDR_07 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_07_ALT_TP_OUT_07 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_06 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_EBI_ADDR_06 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_06_ALT_TP_OUT_06 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_05 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_EBI_ADDR_05 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_05_ALT_TP_OUT_05 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_04 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_EBI_ADDR_04 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_04_ALT_TP_OUT_04 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_03 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_EBI_ADDR_03 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_03_ALT_TP_OUT_03 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_02 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_EBI_ADDR_02 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_02_ALT_TP_OUT_02 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_01 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_EBI_ADDR_01 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_01_ALT_TP_OUT_01 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_addr_00 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_EBI_ADDR_00 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_addr_00_ALT_TP_OUT_00 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_3 - Pinmux control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_15 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_15_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_15_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_15_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_15_EBI_ADDR_15 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_15_TSPI_S1_MOSI 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_14 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_14_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_14_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_14_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_14_EBI_ADDR_14 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_14_ALT_TP_OUT_22 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_13 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_13_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_13_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_13_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_13_EBI_ADDR_13 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_13_ALT_TP_OUT_21 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_12 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_12_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_12_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_12_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_12_EBI_ADDR_12 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_12_ALT_TP_OUT_20 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_11 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_11_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_11_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_11_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_11_EBI_ADDR_11 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_11_ALT_TP_OUT_19 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_10 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_10_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_10_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_10_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_10_EBI_ADDR_10 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_10_ALT_TP_OUT_18 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_09 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_09_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_09_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_09_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_09_EBI_ADDR_09 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_09_ALT_TP_OUT_17 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_addr_08 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_08_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_08_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_08_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_08_EBI_ADDR_08 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_addr_08_ALT_TP_OUT_16 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_4 - Pinmux control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_23 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_23_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_23_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_23_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_23_EBI_ADDR_23 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_23_ALT_TP_OUT_31 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_22 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_22_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_22_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_22_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_22_EBI_ADDR_22 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_22_ALT_TP_OUT_30 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_21 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_21_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_21_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_21_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_21_EBI_ADDR_21 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_21_ALT_TP_OUT_29 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_20 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_20_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_20_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_20_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_20_EBI_ADDR_20 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_20_ALT_TP_OUT_28 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_19 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_19_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_19_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_19_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_19_EBI_ADDR_19 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_19_ALT_TP_OUT_27 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_18 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_18_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_18_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_18_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_18_EBI_ADDR_18 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_18_ALT_TP_OUT_26 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_17 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_17_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_17_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_17_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_17_EBI_ADDR_17 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_17_ALT_TP_OUT_25 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: ebi_addr_16 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_16_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_16_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_16_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_16_EBI_ADDR_16 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_ebi_addr_16_ALT_TP_OUT_24 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_5 - Pinmux control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_cs4b [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs4b_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs4b_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs4b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs4b_EBI_CS4B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs4b_EBI_ADDR_13 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs4b_TSPI_S3_MISO 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_cs3b [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs3b_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs3b_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs3b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs3b_EBI_CS3B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs3b_TSPI_S2_MISO 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_cs2b [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs2b_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs2b_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs2b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs2b_EBI_CS2B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs2b_TSPI_S1_MISO 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_cs1b [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs1b_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs1b_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs1b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs1b_EBI_CS1B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_cs1b_TSPI_S0_MISO 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr_27 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_27_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_27_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_27_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_27_EBI_ADDR_27 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_27_TSPI_S0_SCK 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr_26 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_26_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_26_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_26_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_26_EBI_ADDR_26 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_26_ALT_TP_OUT_12 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr_25 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_25_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_25_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_25_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_25_EBI_ADDR_25 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_25_ALT_TP_OUT_15 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: ebi_addr_24 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_24_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_24_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_24_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_24_EBI_ADDR_24 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_ebi_addr_24_ALT_TP_OUT_11 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_6 - Pinmux control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_nand_rbb [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_nand_rbb_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_nand_rbb_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_nand_rbb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_nand_rbb_EBI_NAND_RBB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_nand_rbb_TSPI_S3_MOSI 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_dsb [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_dsb_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_dsb_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_dsb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_dsb_EBI_DSB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_dsb_TSPI_S3_SCK 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_tsb [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsb_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsb_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsb_EBI_TSB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_tsb_TSPI_S2_SS0B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_rdb [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rdb_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rdb_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rdb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rdb_EBI_RDB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rdb_TSPI_S0_SS0B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_we1b [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_we1b_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_we1b_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_we1b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_we1b_EBI_WE1B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_we1b_TSPI_S2_MOSI 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_we0b [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_we0b_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_we0b_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_we0b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_we0b_EBI_WE0B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_we0b_TSPI_S2_SCK 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_rwb [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rwb_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rwb_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rwb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rwb_EBI_RWB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_rwb_TSPI_S1_SS0B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: ebi_cs5b [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_cs5b_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_cs5b_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_cs5b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_cs5b_EBI_CS5B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_cs5b_EBI_ADDR_14 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_ebi_cs5b_TSPI_S0_MOSI 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_7 - Pinmux control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_001 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_GPIO_001 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_EMAC0_MII_TX_ERR 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_GPHY_ACTIVITY 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_SW_LED_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_EMAC1_MII_TX_ERR 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_TP_OUT_13 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_001_PM_GPIO_001 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_000 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_GPIO_000 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_EMAC0_MII_RX_ERR 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_GPHY_LINK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_SW_LED_DATA 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_EMAC1_MII_RX_ERR 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_TP_OUT_12 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_000_PM_GPIO_000 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: uart_txd_0 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_uart_txd_0_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_uart_txd_0_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_uart_txd_0_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_uart_txd_0_UART_TXD_0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_uart_txd_0_TP_OUT_03 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: uart_rxd_0 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_uart_rxd_0_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_uart_rxd_0_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_uart_rxd_0_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_uart_rxd_0_UART_RXD_0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_uart_rxd_0_TP_IN_05 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: emmc1_clk [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_emmc1_clk_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_emmc1_clk_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_emmc1_clk_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_emmc1_clk_EMMC1_CLK 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_emmc1_clk_PM_EMMC1_CLK 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: emmc1_cmd [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_emmc1_cmd_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_emmc1_cmd_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_emmc1_cmd_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_emmc1_cmd_EMMC1_CMD 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_emmc1_cmd_PM_EMMC1_CMD 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: ebi_waitb [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_waitb_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_waitb_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_waitb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_waitb_EBI_WAITB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_waitb_TSPI_S1_SCK 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: ebi_nand_dqs [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_nand_dqs_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_nand_dqs_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_nand_dqs_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_nand_dqs_EBI_NAND_DQS 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_ebi_nand_dqs_TSPI_S3_SS0B 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_8 - Pinmux control register 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_009 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_GPIO_009 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_EMAC0_TX_EN_CTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_UART_RTS_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_CPU_TRACE_DATA11 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_TP_OUT_21 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_009_PM_GPIO_009 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_008 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_GPIO_008 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_EMAC0_TX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_UART_CTS_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_CPU_TRACE_DATA10 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_TP_IN_20 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_008_PM_GPIO_008 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_007 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_GPIO_007 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_EMAC0_RXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_UART_TXD_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_CPU_TRACE_DATA9 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_EXT_IRQB_4 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_TP_OUT_19 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_007_PM_GPIO_007 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_006 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_GPIO_006 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_EMAC0_RXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_UART_RXD_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_CPU_TRACE_DATA8 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_EXT_IRQB_3 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_TP_IN_18 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_006_PM_GPIO_006 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_005 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_GPIO_005 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_EMAC0_RXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_UART_RTS_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_CPU_TRACE_DATA7 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_TP_OUT_17 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_005_PM_GPIO_005 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_004 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_004_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_004_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_004_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_004_GPIO_004 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_004_EMAC0_RXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_004_UART_CTS_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_004_CPU_TRACE_DATA6 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_004_TP_OUT_16 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_004_PM_GPIO_004 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_003 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_003_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_003_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_003_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_003_GPIO_003 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_003_EMAC0_RX_EN_CTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_003_VEC_HSYNC_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_003_CPU_TRACE_DATA5 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_003_TP_OUT_15 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_003_PM_GPIO_003 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_002 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_002_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_002_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_002_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_002_GPIO_002 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_002_EMAC0_RX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_002_IR_IN1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_002_CPU_TRACE_DATA4 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_002_PM_GPIO_002 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_9 - Pinmux control register 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_017 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_GPIO_017 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_EMAC0_MII_CRS 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_RMX_DATA0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_MOCA_ACTIVITY 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_EMAC1_MII_CRS 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_017_PM_GPIO_017 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_016 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_GPIO_016 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_EMAC0_IRQ 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_RMX_CLK0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_MOCA_LINK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_EMAC1_IRQ 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_016_PM_GPIO_016 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_015 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_GPIO_015 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_EMAC0_MDC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_SPI_S_MISO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_EMAC1_MDC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_SW_SPI_S_MISO 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_015_PM_GPIO_015 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_014 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_GPIO_014 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_EMAC0_MDIO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_SPI_S_SS0B 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_EMAC1_MDIO 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_SW_SPI_S_SS0B 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_014_PM_GPIO_014 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_013 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_GPIO_013 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_EMAC0_TXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_UART_RTS_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_CPU_TRACE_DATA15 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_VEC_VSYNC_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_TP_OUT_25 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_013_PM_GPIO_013 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_012 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_012_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_012_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_012_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_012_GPIO_012 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_012_EMAC0_TXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_012_UART_CTS_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_012_CPU_TRACE_DATA14 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_012_TP_OUT_24 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_012_PM_GPIO_012 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_011 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_011_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_011_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_011_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_011_GPIO_011 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_011_EMAC0_TXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_011_UART_TXD_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_011_CPU_TRACE_DATA13 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_011_TP_OUT_23 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_011_PM_GPIO_011 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_010 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_010_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_010_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_010_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_010_GPIO_010 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_010_EMAC0_TXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_010_UART_RXD_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_010_CPU_TRACE_DATA12 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_010_TP_IN_22 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_010_PM_GPIO_010 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_10 - Pinmux control register 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_025 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_GPIO_025 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_MTSIF0_DATA3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_PPKT_DATA3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_UART_CTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_025_PM_GPIO_025 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_024 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_GPIO_024 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_MTSIF0_DATA2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_PPKT_DATA2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_EXT_IRQB_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_024_PM_GPIO_024 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_023 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_GPIO_023 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_PPKT_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_UART_RTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_023_PM_GPIO_023 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_022 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_GPIO_022 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_MTSIF0_DATA1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_PPKT_DATA1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_UART_CTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_022_PM_GPIO_022 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_021 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_GPIO_021 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_MTSIF0_SYNC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_PPKT_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_TP_OUT_30 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_021_PM_GPIO_021 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_020 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_020_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_020_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_020_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_020_GPIO_020 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_020_MTSIF0_DATA0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_020_PPKT_DATA0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_020_TP_OUT_29 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_020_PM_GPIO_020 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_019 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_019_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_019_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_019_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_019_GPIO_019 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_019_MTSIF0_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_019_PPKT_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_019_EXT_IRQB_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_019_TP_OUT_28 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_019_PM_GPIO_019 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_018 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_018_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_018_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_018_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_018_GPIO_018 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_018_EMAC0_MII_COL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_018_RMX_SYNC0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_018_MOCA_LINK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_018_EMAC1_MII_COL 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_018_PM_GPIO_018 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_11 - Pinmux control register 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_033 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_GPIO_033 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_CHIP2POD_MCLKO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_RMXP_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_EBI_ADDR_15 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_TP_IN_09 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_033_PM_GPIO_033 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_032 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_GPIO_032 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_POD2CHIP_MCLKI 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_PPKT_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_EBI_ADDR_14 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_TP_IN_08 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_032_PM_GPIO_032 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_031 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_GPIO_031 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_MTSIF_ATS_RST 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_UART_TXD_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_UART_RTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_TP_OUT_26 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_031_PM_GPIO_031 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_030 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_GPIO_030 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_MTSIF_ATS_INC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_UART_RXD_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_UART_CTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_TP_IN_07 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_030_PM_GPIO_030 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_029 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_GPIO_029 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_MTSIF0_DATA7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_PPKT_DATA7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_TP_IN_06 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_029_PM_GPIO_029 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_028 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_028_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_028_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_028_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_028_GPIO_028 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_028_MTSIF0_DATA6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_028_PPKT_DATA6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_028_UART_TXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_028_TP_OUT_14 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_028_PM_GPIO_028 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_027 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_027_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_027_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_027_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_027_GPIO_027 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_027_MTSIF0_DATA5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_027_PPKT_DATA5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_027_UART_RXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_027_TP_IN_02 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_027_PM_GPIO_027 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_026 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_026_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_026_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_026_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_026_GPIO_026 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_026_MTSIF0_DATA4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_026_PPKT_DATA4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_026_UART_RTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_026_PM_GPIO_026 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_12 - Pinmux control register 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_041 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_GPIO_041 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_POD2CHIP_MDI1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_PPKT_DATA1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_UART_RXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_TP_IN_19 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_041_PM_GPIO_041 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_040 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_GPIO_040 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_POD2CHIP_MDI0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_PPKT_DATA0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_I2S_CLK0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_TP_OUT_18 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_040_PM_GPIO_040 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_039 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_GPIO_039 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_POD2CHIP_MIVAL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_PPKT_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_I2S_LR0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_TP_IN_17 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_039_PM_GPIO_039 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_038 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_GPIO_038 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_POD2CHIP_MISTRT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_PPKT_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_I2S_DATA0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_TP_IN_15 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_038_PM_GPIO_038 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_037 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_GPIO_037 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_CHIP2POD_SCTL_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_SPI_M_SS0B 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_EBI_ADDR_02 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_TP_IN_14 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_037_PM_GPIO_037 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_036 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_036_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_036_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_036_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_036_GPIO_036 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_036_CHIP2POD_SDO_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_036_SPI_M_MOSI 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_036_EBI_ADDR_00 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_036_VEC_VSYNC_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_036_TP_IN_13 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_036_PM_GPIO_036 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_035 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_035_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_035_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_035_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_035_GPIO_035 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_035_POD2CHIP_SDI_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_035_SPI_M_MISO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_035_PM_GPIO_035 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_034 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_034_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_034_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_034_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_034_GPIO_034 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_034_CHIP2POD_SCLK_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_034_SPI_M_SCK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_034_EBI_ADDR_01 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_034_PM_GPIO_034 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_13 - Pinmux control register 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_049 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_GPIO_049 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_CHIP2POD_MOVAL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_RMXP_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_EBI_ADDR_16 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_SC0_IO 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_TP_IN_26 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_049_PM_GPIO_049 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_048 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_GPIO_048 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_POD2CHIP_MICLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_PPKT_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_EBI_ADDR_13 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_POD2CHIP_MCLKI 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_TP_IN_25 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_048_PM_GPIO_048 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_047 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_GPIO_047 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_POD2CHIP_MDI7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_PPKT_DATA7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_I2S_CLK1_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_TP_IN_24 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_047_PM_GPIO_047 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_046 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_GPIO_046 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_POD2CHIP_MDI6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_PPKT_DATA6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_I2S_LR1_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_TP_IN_23 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_046_PM_GPIO_046 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_045 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_GPIO_045 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_POD2CHIP_MDI5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_PPKT_DATA5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_I2S_DATA1_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_045_PM_GPIO_045 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_044 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_044_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_044_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_044_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_044_GPIO_044 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_044_POD2CHIP_MDI4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_044_PPKT_DATA4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_044_UART_TXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_044_TP_OUT_22 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_044_PM_GPIO_044 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_043 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_043_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_043_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_043_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_043_GPIO_043 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_043_POD2CHIP_MDI3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_043_PPKT_DATA3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_043_UART_RXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_043_TP_IN_21 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_043_PM_GPIO_043 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_042 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_042_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_042_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_042_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_042_GPIO_042 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_042_POD2CHIP_MDI2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_042_PPKT_DATA2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_042_UART_TXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_042_TP_OUT_20 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_042_PM_GPIO_042 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_14 - Pinmux control register 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_057 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_GPIO_057 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_CHIP2POD_MDO6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_RMXP_DATA6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_EBI_ADDR_24 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_I2S_DATA1_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_ALT_TP_IN_17 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_057_PM_GPIO_057 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_056 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_GPIO_056 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_CHIP2POD_MDO5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_RMXP_DATA5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_EBI_ADDR_23 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_SC0_VPP 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_ALT_TP_IN_16 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_056_PM_GPIO_056 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_055 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_GPIO_055 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_CHIP2POD_MDO4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_RMXP_DATA4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_EBI_ADDR_22 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_SC0_AUX2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_055_PM_GPIO_055 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_054 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_GPIO_054 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_CHIP2POD_MDO3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_RMXP_DATA3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_EBI_ADDR_21 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_SC0_AUX1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_TP_IN_31 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_054_PM_GPIO_054 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_053 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_GPIO_053 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_CHIP2POD_MDO2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_RMXP_DATA2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_EBI_ADDR_20 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_SC0_VCC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_TP_IN_30 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_053_PM_GPIO_053 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_052 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_052_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_052_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_052_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_052_GPIO_052 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_052_CHIP2POD_MDO1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_052_RMXP_DATA1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_052_EBI_ADDR_19 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_052_SC0_PRES 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_052_TP_IN_29 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_052_PM_GPIO_052 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_051 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_051_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_051_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_051_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_051_GPIO_051 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_051_CHIP2POD_MDO0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_051_RMXP_DATA0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_051_EBI_ADDR_18 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_051_SC0_RST 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_051_TP_IN_28 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_051_PM_GPIO_051 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_050 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_050_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_050_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_050_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_050_GPIO_050 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_050_CHIP2POD_MOSTRT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_050_RMXP_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_050_EBI_ADDR_17 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_050_SC0_CLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_050_TP_IN_27 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_050_PM_GPIO_050 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_15 - Pinmux control register 15 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_065 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_GPIO_065 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_MTSIF1_DATA2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_EMAC1_RXD_03 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_EXT_IRQB_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_ALT_TP_IN_25 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_065_PM_GPIO_065 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_064 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_GPIO_064 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_EMAC1_RXD_02 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_PKT_VALID1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_ALT_TP_IN_24 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_064_PM_GPIO_064 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_063 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_GPIO_063 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_MTSIF1_DATA1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_EMAC1_RXD_01 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_PKT_ERROR1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_ALT_TP_IN_23 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_063_PM_GPIO_063 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_062 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_GPIO_062 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_MTSIF1_SYNC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_EMAC1_RXD_00 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_PKT_SYNC1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_062_PM_GPIO_062 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_061 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_GPIO_061 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_MTSIF1_DATA0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_EMAC1_RX_EN_CTL 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_PKT_DATA1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_ALT_TP_IN_21 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_061_PM_GPIO_061 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_060 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_060_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_060_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_060_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_060_GPIO_060 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_060_MTSIF1_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_060_EMAC1_RX_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_060_PKT_CLK1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_060_EXT_IRQB_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_060_ALT_TP_IN_20 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_060_PM_GPIO_060 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_059 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_059_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_059_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_059_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_059_GPIO_059 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_059_CHIP2POD_MOCLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_059_RMXP_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_059_EBI_ADDR_12 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_059_I2S_CLK1_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_059_CHIP2POD_MCLKO 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_059_ALT_TP_IN_19 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_059_PM_GPIO_059 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_058 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_058_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_058_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_058_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_058_GPIO_058 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_058_CHIP2POD_MDO7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_058_RMXP_DATA7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_058_EBI_ADDR_25 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_058_I2S_LR1_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_058_ALT_TP_IN_18 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_058_PM_GPIO_058 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_16 - Pinmux control register 16 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_073 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_GPIO_073 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_PKT_SYNC0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_PWM_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_UART_TXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_GPHY_ACTIVITY 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_SW_LED_DATA 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_ALT_TP_OUT_09 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_073_PM_GPIO_073 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_072 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_GPIO_072 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_PKT_DATA0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_PWM_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_UART_RXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_GPHY_LINK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_SW_LED_CLK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_ALT_TP_IN_31 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_072_PM_GPIO_072 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_071 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_GPIO_071 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_PKT_CLK0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_IR_IN1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_MOCA_LINK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_SW_LED_CLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_ALT_TP_IN_30 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_071_PM_GPIO_071 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_070 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_GPIO_070 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_MTSIF1_DATA7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_EMAC1_TXD_03 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_ALT_TP_IN_29 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_070_PM_GPIO_070 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_069 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_GPIO_069 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_MTSIF1_DATA6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_EMAC1_TXD_02 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_UART_TXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_TP_OUT_27 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_069_PM_GPIO_069 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_068 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_068_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_068_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_068_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_068_GPIO_068 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_068_MTSIF1_DATA5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_068_EMAC1_TXD_01 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_068_UART_RXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_068_ALT_TP_IN_28 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_068_PM_GPIO_068 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_067 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_067_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_067_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_067_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_067_GPIO_067 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_067_MTSIF1_DATA4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_067_EMAC1_TXD_00 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_067_UART_RTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_067_ALT_TP_IN_26 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_067_PM_GPIO_067 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_066 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_066_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_066_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_066_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_066_GPIO_066 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_066_MTSIF1_DATA3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_066_EMAC1_TX_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_066_UART_CTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_066_TP_OUT_31 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_066_PM_GPIO_066 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_17 - Pinmux control register 17 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_081 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_GPIO_081 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_SD_CARD0_DAT1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_EMMC0_DAT1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_EXT_IRQB_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_UART_RXD_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_TP_IN_00 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_081_PM_GPIO_081 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_080 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_GPIO_080 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_SD_CARD0_DAT0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_EMMC0_DAT0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_EXT_IRQB_5 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_IR_IN1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_TP_IN_11 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_080_PM_GPIO_080 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_079 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_079_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_079_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_079_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_079_GPIO_079 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_079_SD_CARD0_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_079_EMMC0_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_079_PWM_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_079_TP_IN_10 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_079_PM_GPIO_079 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_078 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_078_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_078_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_078_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_078_GPIO_078 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_078_SD_CARD0_PWR0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_078_EMMC0_DAT7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_078_RMX_PAUSE1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_078_PM_GPIO_078 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_077 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_077_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_077_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_077_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_077_GPIO_077 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_077_SD_CARD0_WPROT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_077_EMMC0_DAT6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_077_RMX_PAUSE0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_077_ALT_TP_OUT_14 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_077_PM_GPIO_077 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_076 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_076_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_076_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_076_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_076_GPIO_076 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_076_SD_CARD0_CMD 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_076_EMMC0_CMD 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_076_ALT_TP_OUT_13 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_076_PM_GPIO_076 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_075 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_075_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_075_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_075_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_075_GPIO_075 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_075_PKT_VALID0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_075_PWM_3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_075_SPI_S_MISO 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_075_SW_SPI_S_MISO 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_075_ALT_TP_OUT_10 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_075_PM_GPIO_075 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_074 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_074_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_074_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_074_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_074_GPIO_074 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_074_PKT_ERROR0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_074_PWM_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_074_SPI_M_SS2B 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_074_SW_LED_DATA 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_074_SPI_S_SS0B 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_074_SW_SPI_S_SS0B 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_074_PM_GPIO_074 7 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_18 - Pinmux control register 18 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_089 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_GPIO_089 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_SC1_PRES 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_PWM_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_UART_RTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_CHIP2POD_SCTL_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_ALT_TP_IN_27 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_089_PM_GPIO_089 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_088 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_GPIO_088 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_SC1_RST 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_PWM_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_CHIP2POD_SDO_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_TP_IN_16 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_088_PM_GPIO_088 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_087 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_087_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_087_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_087_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_087_GPIO_087 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_087_SC1_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_087_PWM_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_087_PM_GPIO_087 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_086 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_086_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_086_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_086_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_086_GPIO_086 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_086_SC1_IO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_086_IR_IN1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_086_CHIP2POD_SCLK_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_086_PM_GPIO_086 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_085 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_085_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_085_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_085_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_085_GPIO_085 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_085_SD_CARD0_LED 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_085_EMMC0_DAT5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_085_EXT_IRQB_4 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_085_PWM_3 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_085_TP_IN_04 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_085_PM_GPIO_085 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_084 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_084_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_084_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_084_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_084_GPIO_084 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_084_SD_CARD0_PRES 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_084_EMMC0_DAT4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_084_EXT_IRQB_3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_084_UART_CTS_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_084_TP_IN_03 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_084_PM_GPIO_084 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_083 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_083_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_083_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_083_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_083_GPIO_083 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_083_SD_CARD0_DAT3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_083_EMMC0_DAT3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_083_EXT_IRQB_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_083_UART_RTS_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_083_PM_GPIO_083 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_082 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_082_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_082_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_082_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_082_GPIO_082 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_082_SD_CARD0_DAT2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_082_EMMC0_DAT2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_082_EXT_IRQB_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_082_UART_TXD_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_082_TP_OUT_00 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_082_PM_GPIO_082 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_19 - Pinmux control register 19 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_097 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_GPIO_097 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_VO0_656_3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_LED_LD_11 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_RMX_SYNC0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_SD_CARD1_VOLT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_AUD_FS_CLK1 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_PKT_SYNC2 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_TP_OUT_05 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_097_PM_GPIO_097 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_096 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_GPIO_096 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_VO0_656_2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_LED_LD_10 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_RMX_DATA0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_SD_CARD1_PWR0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_096_TP_OUT_04 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_095 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_095_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_095_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_095_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_095_GPIO_095 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_095_VO0_656_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_095_LED_LD_9 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_095_RMX_CLK0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_095_SD_CARD1_LED 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_095_PKT_ERROR2 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_094 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_GPIO_094 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_VO0_656_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_LED_LD_8 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_PWM_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_SD_CARD1_CMD 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_CPU_TRACE_RXD 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_VEC_VSYNC_0 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_EMAC1_IRQ 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_TP_OUT_02 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_094_PM_GPIO_094 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_093 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_093_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_093_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_093_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_093_GPIO_093 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_093_SC1_VPP 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_093_CODEC_MCLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_093_SC0_VPP 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_093_PM_GPIO_093 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_092 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_092_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_092_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_092_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_092_GPIO_092 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_092_SC1_AUX2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_092_CODEC_FSYNCB 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_092_SC0_AUX2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_092_UART_TXD_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_092_EMAC1_MDC 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_092_TP_OUT_11 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_092_PM_GPIO_092 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_091 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_091_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_091_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_091_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_091_GPIO_091 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_091_SC1_AUX1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_091_CODEC_SCLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_091_SC0_AUX1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_091_UART_RXD_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_091_EMAC1_MDIO 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_091_TP_IN_12 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_091_PM_GPIO_091 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_090 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_090_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_090_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_090_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_090_GPIO_090 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_090_SC1_VCC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_090_PWM_3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_090_UART_CTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_090_POD2CHIP_SDI_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_090_ALT_TP_OUT_08 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_090_PM_GPIO_090 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_20 - Pinmux control register 20 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_105 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_GPIO_105 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_SD_CARD1_DAT2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_TTX0_REQ 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_CPU_TRACE_DATA2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_105_PM_GPIO_105 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_104 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_GPIO_104 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_SD_CARD1_DAT1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_AUD_FS_CLK0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_CPU_TRACE_DATA1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_104_PM_GPIO_104 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_103 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_103_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_103_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_103_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_103_GPIO_103 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_103_IR_INT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_103_SC_CLK_OUT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_103_PKT_VALID2 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_102 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_102_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_102_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_102_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_102_GPIO_102 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_102_VO0_656_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_102_SD_CARD0_VOLT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_102_PWM_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_102_SPI_M_SS2B 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_102_TP_OUT_10 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_101 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_101_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_101_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_101_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_101_GPIO_101 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_101_VO0_656_7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_101_LED_LD_15 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_101_RMX_SYNC1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_101_SD_CARD1_CLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_101_CPU_TRACE_CLK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_101_TP_OUT_09 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_101_PM_GPIO_101 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_100 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_100_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_100_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_100_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_100_GPIO_100 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_100_VO0_656_6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_100_LED_LD_14 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_100_RMX_DATA1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_100_SD_CARD1_WPROT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_100_PKT_DATA2 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_100_TP_OUT_08 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_100_PM_GPIO_100 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_099 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_099_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_099_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_099_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_099_GPIO_099 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_099_VO0_656_5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_099_LED_LD_13 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_099_RMX_CLK1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_099_SD_CARD1_PRES 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_099_PKT_CLK2 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_099_TP_OUT_07 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_099_PM_GPIO_099 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_098 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_098_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_098_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_098_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_098_GPIO_098 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_098_VO0_656_4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_098_LED_LD_12 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_098_PWM_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_098_SD_CARD1_DAT0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_098_CPU_TRACE_DATA0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_098_TP_OUT_06 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_098_PM_GPIO_098 7 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_21 - Pinmux control register 21 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: sgpio_01 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_01_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_01_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_01_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_01_SGPIO_01 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_01_BSC_M3_SDA 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: sgpio_00 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_00_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_00_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_00_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_00_SGPIO_00 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_00_BSC_M3_SCL 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: gpio_111 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_111_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_111_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_111_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_111_GPIO_111 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_111_SD_CARD1_CLK_IN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_111_GPHY_ACTIVITY 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_111_MOCA_ACTIVITY 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_111_SW_LED_DATA 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_111_EMAC1_IRQ 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_111_PM_GPIO_111 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: gpio_110 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_110_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_110_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_110_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_110_GPIO_110 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_110_SD_CARD0_CLK_IN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_110_GPHY_LINK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_110_MOCA_LINK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_110_SW_LED_CLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_110_PM_GPIO_110 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: gpio_109 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_109_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_109_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_109_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_109_GPIO_109 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_109_AUD_FS_CLK1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_109_EMAC1_TX_EN_CTL 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_109_PM_GPIO_109 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: gpio_108 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_108_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_108_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_108_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_108_GPIO_108 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_108_CODEC_SDO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_108_TTX0_DATA 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_108_SC_CLK_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_108_EBI_ADDR_14 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_108_PM_GPIO_108 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: gpio_107 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_107_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_107_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_107_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_107_GPIO_107 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_107_CODEC_SDI 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_107_TTX0_REQ 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_107_EMAC1_IRQ 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_107_EXT_SC_CLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_107_EBI_ADDR_13 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_107_PM_GPIO_107 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: gpio_106 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_106_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_106_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_106_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_106_GPIO_106 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_106_SD_CARD1_DAT3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_106_TTX0_DATA 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_106_CPU_TRACE_DATA3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_gpio_106_PM_GPIO_106 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_22 - Pinmux control register 22 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_22 :: byp_clk_1 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_byp_clk_1_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_byp_clk_1_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_byp_clk_1_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_byp_clk_1_BYP_CLK_1 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_byp_clk_1_BYP_CLK_OUT_1 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_22 :: byp_clk_0 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_byp_clk_0_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_byp_clk_0_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_byp_clk_0_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_byp_clk_0_BYP_CLK_0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_byp_clk_0_BYP_CLK_OUT_0 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_22 :: bsc_s_sda [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_bsc_s_sda_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_bsc_s_sda_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_bsc_s_sda_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_bsc_s_sda_BSC_S_SDA 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_bsc_s_sda_SW_SPI_S_MOSI 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_22 :: bsc_s_scl [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_bsc_s_scl_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_bsc_s_scl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_bsc_s_scl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_bsc_s_scl_BSC_S_SCL 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_bsc_s_scl_SW_SPI_S_SCK 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_22 :: sgpio_05 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_05_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_05_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_05_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_05_SGPIO_05 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_05_MOCA_BSC_SDA 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_22 :: sgpio_04 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_04_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_04_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_04_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_04_SGPIO_04 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_04_MOCA_BSC_SCL 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_22 :: sgpio_03 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_03_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_03_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_03_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_03_SGPIO_03 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_03_BSC_M4_SDA 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_22 :: sgpio_02 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_02_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_02_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_02_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_02_SGPIO_02 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_22_sgpio_02_BSC_M4_SCL 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_10_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_10_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_09_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_09_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_08_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_08_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_07_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_07_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_06_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_06_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_05_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_05_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_04_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_04_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_03_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_03_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_02_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_02_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_01_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_01_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ebi_data_00_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ebi_data_00_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_09_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_09_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_08_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_08_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_07_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_07_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_06_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_06_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_05_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_05_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_04_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_04_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_03_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_03_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_02_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_02_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_01_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_01_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_addr_00_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_addr_00_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_15_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_15_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_14_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_14_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_13_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_13_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_12_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_12_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_12_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_12_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_12_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_12_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_12_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ebi_data_11_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_11_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_11_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_11_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_11_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_11_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ebi_data_11_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_24_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_24_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_23_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_23_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_22_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_22_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_21_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_21_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_20_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_20_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_19_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_19_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_18_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_18_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_17_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_17_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_16_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_16_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_15_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_15_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_14_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_14_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_13_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_13_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_12_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_12_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_11_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_11_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_11_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_11_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_11_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_11_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_11_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_addr_10_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_10_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_10_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_10_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_10_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_10_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_addr_10_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_dsb_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_tsb_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_rdb_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_we1b_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_we0b_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_rwb_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs5b_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs5b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs4b_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs4b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs3b_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs3b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs2b_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs2b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs1b_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs1b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_cs0b_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_cs0b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_addr_27_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_27_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_addr_26_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_26_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_26_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_26_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_26_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_26_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_26_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_addr_25_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_25_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_25_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_25_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_25_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_25_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_addr_25_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [29:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK 0x3c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: pcie_clkreqb_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_clkreqb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: pcie_rstb_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_pcie_rstb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: emmc1_clk_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_emmc1_clk_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_emmc1_clk_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_emmc1_clk_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_emmc1_clk_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_emmc1_clk_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_emmc1_clk_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: emmc1_cmd_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_emmc1_cmd_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_emmc1_cmd_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_emmc1_cmd_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_emmc1_cmd_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_emmc1_cmd_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_emmc1_cmd_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_wpb_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_wpb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_holdb_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_holdb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_mosi_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_mosi_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_miso_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_miso_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: sf_sck_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_sf_sck_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_waitb_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_waitb_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_waitb_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_waitb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_waitb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_waitb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_waitb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_nand_dqs_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_dqs_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_dqs_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_dqs_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_dqs_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_dqs_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_dqs_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_nand_wpb_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_wpb_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_wpb_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_wpb_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_wpb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_wpb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_wpb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: ebi_nand_rbb_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_rbb_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_rbb_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_rbb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_rbb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_rbb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_ebi_nand_rbb_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_001_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_001_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_000_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_000_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [25:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK 0x03ff0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: pcie1_clkreqb_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_pcie1_clkreqb_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_pcie1_clkreqb_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_pcie1_clkreqb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_pcie1_clkreqb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_pcie1_clkreqb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_pcie1_clkreqb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: pcie1_rstb_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_pcie1_rstb_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_pcie1_rstb_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_pcie1_rstb_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_pcie1_rstb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_pcie1_rstb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_pcie1_rstb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved1 [11:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved1_MASK 0x00000fff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_016_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_016_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_015_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_015_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_014_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_014_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_013_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_013_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_012_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_012_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_011_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_011_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_011_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_011_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_011_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_011_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_011_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_010_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_010_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_009_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_009_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_008_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_008_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_008_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_008_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_008_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_008_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_008_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_007_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_007_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_006_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_006_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_005_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_005_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_004_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_004_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_003_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_003_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_002_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_002_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_031_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_031_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_030_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_030_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_029_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_029_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_028_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_028_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_027_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_027_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_026_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_026_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_025_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_025_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_025_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_025_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_025_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_025_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_025_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_024_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_024_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_023_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_023_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_022_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_022_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_021_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_021_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_020_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_020_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_019_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_019_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_018_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_018_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_017_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_017_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_046_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_046_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_045_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_045_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_044_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_044_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_043_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_043_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_042_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_042_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_041_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_041_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_040_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_040_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_039_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_039_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_038_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_038_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_037_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_037_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_036_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_036_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_035_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_035_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_034_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_034_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_033_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_033_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_032_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_032_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_061_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_061_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_060_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_060_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_059_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_059_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_058_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_058_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_057_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_057_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_056_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_056_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_055_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_055_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_054_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_054_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_053_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_053_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_052_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_052_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_051_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_051_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_050_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_050_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_049_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_049_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_048_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_048_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_047_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_047_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_076_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_076_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_075_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_075_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_074_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_074_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_073_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_073_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_072_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_072_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_071_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_071_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_070_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_070_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_069_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_069_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_068_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_068_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_067_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_067_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_066_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_066_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_065_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_065_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_064_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_064_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_063_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_063_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_062_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_062_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_091_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_091_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_090_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_090_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_089_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_089_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_088_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_088_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_087_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_087_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_086_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_086_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_086_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_086_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_086_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_086_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_086_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_085_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_085_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_085_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_085_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_085_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_085_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_085_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_084_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_084_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_084_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_084_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_084_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_084_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_084_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_083_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_083_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_083_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_083_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_083_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_083_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_083_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_082_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_082_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_082_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_082_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_082_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_082_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_082_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_081_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_081_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_081_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_081_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_081_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_081_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_081_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_080_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_080_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_080_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_080_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_080_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_080_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_080_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_079_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_079_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_079_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_079_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_079_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_079_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_079_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_078_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_078_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_078_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_078_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_078_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_078_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_078_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_077_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_077_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_077_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_077_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_077_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_077_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_077_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_12 - Pad pull-up/pull-down control register 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: spare_pad_ctrl_12 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_106_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_106_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_106_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_106_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_106_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_106_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_106_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_105_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_105_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_105_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_105_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_105_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_105_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_105_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_104_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_104_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_104_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_104_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_104_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_104_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_104_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_103_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_103_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_103_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_103_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_103_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_103_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_103_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_102_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_102_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_102_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_102_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_102_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_102_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_102_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_101_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_101_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_101_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_101_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_101_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_101_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_101_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_100_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_100_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_100_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_100_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_100_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_100_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_100_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_099_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_099_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_099_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_099_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_099_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_099_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_099_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_098_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_098_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_098_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_098_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_098_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_098_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_098_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_097_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_097_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_097_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_097_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_097_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_097_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_097_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_096_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_096_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_096_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_096_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_096_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_096_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_096_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_095_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_095_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_095_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_095_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_095_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_095_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_095_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_094_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_094_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_094_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_094_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_094_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_094_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_094_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_093_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_093_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_093_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_093_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_093_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_093_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_093_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_092_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_092_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_092_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_092_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_092_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_092_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_092_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_13 - Pad pull-up/pull-down control register 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: spare_pad_ctrl_13 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: reserved0 [29:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved0_MASK 0x3ffffc00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: gpio_111_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_111_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_111_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_111_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_111_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_111_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_111_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: gpio_110_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_110_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_110_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_110_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_110_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_110_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_110_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: reserved1 [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved1_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved1_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: gpio_108_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_108_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_108_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_108_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_108_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_108_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_108_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: gpio_107_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_107_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_107_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_107_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_107_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_107_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_gpio_107_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_14 - Pad pull-up/pull-down control register 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_14 :: spare_pad_ctrl_14 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_14 :: reserved0 [29:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_reserved0_MASK 0x3fffffff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_15 - Pad pull-up/pull-down control register 15 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_15 :: reserved0 [31:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_15_reserved0_MASK 0xfffffc00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_15_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_15 :: spare_pad_ctrl_15 [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_15_spare_pad_ctrl_15_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_15_spare_pad_ctrl_15_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_15_spare_pad_ctrl_15_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_15_spare_pad_ctrl_15_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_15_spare_pad_ctrl_15_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_15_spare_pad_ctrl_15_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_15 :: reserved1 [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_15_reserved1_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_15_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_9 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_9_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_9_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_8 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_8_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_8_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_6 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_6_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_6_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_2_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_CTRL - Reset control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_SOURCE_ENABLE - Reset source enable |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK 0xfffffc00 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_MASTER_RESET - Software master reset |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HW_RESET_EXTENSION - Hardware reset extension |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_MONITOR - Reset Monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0 |
| |
| /*************************************************************************** |
| *RESET_HISTORY - Reset history |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:19] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK 0xfff80000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: gen_watchdog_1_reset [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_0_reset [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_1_reset [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_1_reset [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_0_SET - Software init 0 set |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: systemport_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_systemport_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_systemport_sw_init_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_systemport_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_27_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: switch_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_switch_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_switch_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_switch_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga1_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga1_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga1_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: hvd1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd1_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_hr_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie1_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_0_CLEAR - Software init 0 clear |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: systemport_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_systemport_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_systemport_sw_init_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_systemport_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_27_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: switch_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_switch_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_switch_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_switch_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga1_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga1_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga1_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: hvd1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd1_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_hr_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie1_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_0_STATUS - Software init 0 status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: systemport_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_systemport_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_systemport_sw_init_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_systemport_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_27_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: switch_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_switch_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_switch_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_switch_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga1_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga1_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga1_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: hvd1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd1_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_hr_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie1_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: systemport_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_systemport_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_systemport_sw_init_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: switch_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_switch_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_switch_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga1_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga1_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga1_sw_init_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: hvd1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd1_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie1_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: systemport_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_systemport_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_systemport_sw_init_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: switch_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_switch_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_switch_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga1_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga1_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga1_sw_init_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: hvd1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd1_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie1_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: systemport_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_systemport_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_systemport_sw_init_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_27_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: switch_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_switch_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_switch_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga1_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga1_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga1_sw_init_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: hvd1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd1_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_hr_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie1_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_1_SET - Software init 1 set |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK 0xffffc000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: avs_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: gphy_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: ddr2_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ddr2_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ddr2_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ddr2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: memc2_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_memc2_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_memc2_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_memc2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: hvd2_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hvd2_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hvd2_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hvd2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: m2mc1_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: v3d_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: vice21_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice21_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice21_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice21_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_1_CLEAR - Software init 1 clear |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK 0xffffc000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: avs_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: gphy_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ddr2_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ddr2_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ddr2_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ddr2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: memc2_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_memc2_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_memc2_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_memc2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: hvd2_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hvd2_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hvd2_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hvd2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: m2mc1_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: v3d_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vice21_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice21_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice21_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice21_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_1_STATUS - Software init 1 status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK 0xffffc000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: avs_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: gphy_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ddr2_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ddr2_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ddr2_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ddr2_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: memc2_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_memc2_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_memc2_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_memc2_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: hvd2_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hvd2_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hvd2_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hvd2_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: m2mc1_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: v3d_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vice21_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice21_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice21_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice21_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:14] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK 0xffffc000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: avs_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: gphy_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ddr2_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ddr2_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ddr2_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: memc2_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_memc2_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_memc2_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: hvd2_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_hvd2_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_hvd2_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: m2mc1_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: v3d_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vice21_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice21_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice21_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:14] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffc000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: avs_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: gphy_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ddr2_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ddr2_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ddr2_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: memc2_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_memc2_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_memc2_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: hvd2_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_hvd2_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_hvd2_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: m2mc1_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: v3d_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vice21_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice21_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice21_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:14] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK 0xffffc000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: avs_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: gphy_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ddr2_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ddr2_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ddr2_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: memc2_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_memc2_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_memc2_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: hvd2_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_hvd2_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_hvd2_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: m2mc1_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: v3d_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vice21_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice21_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice21_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: systemport_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_systemport_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_systemport_sw_init_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_systemport_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: switch_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_switch_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_switch_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_switch_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga1_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga1_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga1_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: hvd1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd1_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie1_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffc000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: avs_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: gphy_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ddr2_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ddr2_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ddr2_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ddr2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: memc2_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_memc2_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_memc2_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_memc2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: hvd2_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hvd2_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hvd2_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hvd2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: m2mc1_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: v3d_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vice21_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice21_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice21_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice21_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: systemport_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_systemport_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_systemport_sw_init_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_systemport_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_27_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: switch_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_switch_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_switch_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_switch_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga1_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga1_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga1_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: hvd1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd1_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_hr_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_hr_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie1_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffc000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: avs_top_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: gphy_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ddr2_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ddr2_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ddr2_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ddr2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: memc2_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_memc2_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_memc2_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_memc2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: hvd2_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hvd2_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hvd2_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hvd2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: m2mc1_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: v3d_top_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vice21_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice21_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice21_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice21_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UNCLEARED_SCRATCH - Scratch register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPARE_CTRL - Spare control bits reserved for future use |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TEST_PORT_CTRL - Test port control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_AVS_TP_OUT 13 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK 0x0ffffc00 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK 0x00000180 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK 0x0000007f |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SWITCH 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA 1 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS 16 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK 17 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON 18 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF 20 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP 21 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC 25 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HVD0 27 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HVD1 28 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HVD2 29 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO 30 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA0 31 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA1 32 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT 33 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0 35 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC1 36 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC2 37 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VICE20 38 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VICE21 39 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_PCIE0 43 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_PCIE1 44 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0 45 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1 46 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA 47 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM 49 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_V3D_TOP 54 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYSTEMPORT 60 |
| |
| /*************************************************************************** |
| *TEST_PORT_OUT_PEEK - Testport peek register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_OUT_POKE - Testport poke register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TEST_PORT_IN_PEEK - Testport peek register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_IN_POKE - Testport poke register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EJTAG_INPUT_EN - EJTAG input bus enables |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:11] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK 0xfffff800 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [10:00] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK 0x000007ff |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_CPU_ONE_HOT 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA0_CPU_ONE_HOT 4 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA1_CPU_ONE_HOT 8 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE20_ARC0_CPU_ONE_HOT 16 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE20_ARC1_CPU_ONE_HOT 32 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE21_ARC0_CPU_ONE_HOT 64 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE21_ARC1_CPU_ONE_HOT 128 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AVS_CPU_ONE_HOT 256 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SCPU_CPU_ONE_HOT 512 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 1024 |
| |
| /*************************************************************************** |
| *EJTAG_OUTPUT_SEL - EJTAG output select |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_CPU 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA0_CPU 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA1_CPU 3 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE20_ARC0_CPU 4 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE20_ARC1_CPU 5 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE21_ARC0_CPU 6 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE21_ARC1_CPU 7 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AVS_CPU 8 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SCPU_CPU 9 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 10 |
| |
| /*************************************************************************** |
| *VTRAP_CTRL - VTRAP Control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:23] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK 0xff800000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_1_threshold [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_1_threshold [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_0_threshold [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_1_threshold [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_0_threshold [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [17:05] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x0003ffe0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_1_status_clear [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_0_status_clear [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_1_status_clear [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_0_status_clear [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_1_status_clear [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VTRAP_STATUS - VTRAP Status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:05] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_1_status [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_0_status [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_1_status [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_0_status [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_1_status [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UART_ROUTER_SEL_0 - UART Router select 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: reserved0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_5_cpu_sel [29:25] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_MASK 0x3e000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AUDIO_FP1 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_OL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_IL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_ILP2 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD1_OL 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD1_IL 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD2_OL 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD2_IL 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SID 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_VICE20_ARC0 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_VICE20_ARC1 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_VICE21_ARC0 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_VICE21_ARC1 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AVS_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SCPU 16 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_4_cpu_sel [24:20] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_MASK 0x01f00000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AUDIO_FP1 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_OL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_IL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_ILP2 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD1_OL 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD1_IL 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD2_OL 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD2_IL 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SID 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_VICE20_ARC0 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_VICE20_ARC1 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_VICE21_ARC0 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_VICE21_ARC1 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AVS_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SCPU 16 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_3_cpu_sel [19:15] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_MASK 0x000f8000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AUDIO_FP1 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_OL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_IL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_ILP2 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD1_OL 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD1_IL 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD2_OL 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD2_IL 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SID 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_VICE20_ARC0 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_VICE20_ARC1 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_VICE21_ARC0 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_VICE21_ARC1 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AVS_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SCPU 16 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_2_cpu_sel [14:10] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_MASK 0x00007c00 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AUDIO_FP1 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_OL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_IL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_ILP2 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD1_OL 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD1_IL 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD2_OL 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD2_IL 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SID 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_VICE20_ARC0 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_VICE20_ARC1 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_VICE21_ARC0 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_VICE21_ARC1 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AVS_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SCPU 16 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_1_cpu_sel [09:05] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_MASK 0x000003e0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AUDIO_FP1 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_OL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_IL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_ILP2 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD1_OL 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD1_IL 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD2_OL 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD2_IL 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SID 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_VICE20_ARC0 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_VICE20_ARC1 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_VICE21_ARC0 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_VICE21_ARC1 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AVS_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SCPU 16 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_0_cpu_sel [04:00] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_MASK 0x0000001f |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AUDIO_FP1 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_OL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_IL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_ILP2 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD1_OL 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD1_IL 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD2_OL 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD2_IL 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SID 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_VICE20_ARC0 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_VICE20_ARC1 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_VICE21_ARC0 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_VICE21_ARC1 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AVS_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SCPU 16 |
| |
| /*************************************************************************** |
| *UART_ROUTER_SEL_1 - UART Router select 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: reserved0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_11_cpu_sel [29:25] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_MASK 0x3e000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AUDIO_FP1 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_OL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_IL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_ILP2 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD1_OL 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD1_IL 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD2_OL 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD2_IL 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SID 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_VICE20_ARC0 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_VICE20_ARC1 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_VICE21_ARC0 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_VICE21_ARC1 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AVS_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SCPU 16 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_10_cpu_sel [24:20] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_MASK 0x01f00000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AUDIO_FP1 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_OL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_IL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_ILP2 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD1_OL 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD1_IL 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD2_OL 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD2_IL 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SID 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_VICE20_ARC0 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_VICE20_ARC1 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_VICE21_ARC0 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_VICE21_ARC1 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AVS_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SCPU 16 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_9_cpu_sel [19:15] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_MASK 0x000f8000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AUDIO_FP1 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_OL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_IL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_ILP2 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD1_OL 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD1_IL 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD2_OL 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD2_IL 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SID 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_VICE20_ARC0 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_VICE20_ARC1 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_VICE21_ARC0 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_VICE21_ARC1 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AVS_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SCPU 16 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_8_cpu_sel [14:10] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_MASK 0x00007c00 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AUDIO_FP1 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_OL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_IL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_ILP2 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD1_OL 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD1_IL 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD2_OL 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD2_IL 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SID 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_VICE20_ARC0 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_VICE20_ARC1 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_VICE21_ARC0 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_VICE21_ARC1 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AVS_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SCPU 16 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_7_cpu_sel [09:05] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_MASK 0x000003e0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AUDIO_FP1 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_OL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_IL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_ILP2 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD1_OL 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD1_IL 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD2_OL 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD2_IL 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SID 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_VICE20_ARC0 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_VICE20_ARC1 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_VICE21_ARC0 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_VICE21_ARC1 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AVS_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SCPU 16 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_6_cpu_sel [04:00] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_MASK 0x0000001f |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AUDIO_FP1 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_OL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_IL 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_ILP2 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD1_OL 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD1_IL 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD2_OL 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD2_IL 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SID 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_VICE20_ARC0 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_VICE20_ARC1 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_VICE21_ARC0 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_VICE21_ARC1 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AVS_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SCPU 16 |
| |
| /*************************************************************************** |
| *SSP_CONFIG - Serial Slave Port configuration register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK 0xfffff800 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK 0x00000780 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT 0x00000004 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK 0x00000078 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SERS_REV - SERS Revision Register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK 0x0000ff00 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SERS_CFG - SERS Configuration Register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode 1 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT 0x00000000 |
| |
| /* union - case mapped_buffer_mode [26:08] */ |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000 |
| |
| /* union - case cmd_fifo_mode [26:08] */ |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK 0x07c00000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK 0x003e0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK 0x000000fe |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SERS_CMD_BUF_%i - Host Serial Write Command Buffer |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE 0x00404428 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END 7 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *SERS_CMD_BUF_%i - Host Serial Write Command Buffer |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT 0 |
| |
| |
| /*************************************************************************** |
| *SERS_STAT_BUF_%i - Host Serial Read Status Buffer |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE 0x00404448 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END 1 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *SERS_STAT_BUF_%i - Host Serial Read Status Buffer |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT 0 |
| |
| |
| /*************************************************************************** |
| *RO_TEST_BLOCK_SEL - Block select for RO testmode |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:18] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK 0xfffc0000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [17:14] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0003c000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_CMOS 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_CMOS 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_CMOS 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_NMOS 3 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_NMOS 4 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_NMOS 5 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_PMOS 6 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_PMOS 7 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_PMOS 8 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_CMOS 9 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_NMOS 10 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_PMOS 11 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_en [13:02] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_MASK 0x00003ffc |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DISABLE_RO 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_CMOS_ONE_HOT 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_CMOS_ONE_HOT 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_CMOS_ONE_HOT 4 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_NMOS_ONE_HOT 8 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_NMOS_ONE_HOT 16 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_NMOS_ONE_HOT 32 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_PMOS_ONE_HOT 64 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_PMOS_ONE_HOT 128 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_PMOS_ONE_HOT 256 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_CMOS_ONE_HOT 512 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_NMOS_ONE_HOT 1024 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_PMOS_ONE_HOT 2048 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3 |
| |
| /*************************************************************************** |
| *TEST_CONFIGURATION - Test configuration |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */ |
| |
| /* End of File */ |
