Optimus Prime: GPIO setup for POE_ACTIVE,POE_RESET
On Optimus Prime and Sideswipe Prime, we have
POE_ACTIVE on GPIO 49: This is an input signal. It is low if a PoE
powered device is connected to the WAN port.
POE_RESET on GPIO 50: This is an output signal. It is pulled low on the
board. Software can drive it high if it wants to cut PoE power i.e. to
power cycle a PoE powered device (Fiber Jack).
Change-Id: I70fa5e220bb9ecd0d3866d37ad51dc8171f12cde
diff --git a/arch/arm/boards/optimus/optimus.c b/arch/arm/boards/optimus/optimus.c
index e3dee77..bda7177 100644
--- a/arch/arm/boards/optimus/optimus.c
+++ b/arch/arm/boards/optimus/optimus.c
@@ -467,6 +467,9 @@
* GPIO 15: USB power switch enable, active high
* GPIO 48: Power enable for high power wifi 11AC 4.2V PA, needs to be
* set high
+ * GPIO 49: POE_ACTIVE. GPIO input. Lets software read PoE status.
+ * GPIO 50: POE_RESET needs to be low for PoE circuit to provide
+ * power.
*/
comcerto_gpio_enable_output(GPIO_BLUE_LED|GPIO_RED_LED);
/* Turn blue LED off, red LED on, to indicate the uloader is running. */
@@ -501,6 +504,14 @@
writel(readl(COMCERTO_GPIO_63_32_OUTPUT_REG) | 1<<(48-32), COMCERTO_GPIO_63_32_OUTPUT_REG);
/* Set GPIO[48] direction to output */
writel(readl(COMCERTO_GPIO_63_32_OE_REG) & ~(1 << (48-32)), COMCERTO_GPIO_63_32_OE_REG);
+
+ /* GPIO 49 has already been turned into an input as part of the
+ * operation where we turned GPIO 44 through GPIO 59 into inputs. See
+ * above. */
+ /* Set GPIO[50] to low */
+ writel(readl(COMCERTO_GPIO_63_32_OUTPUT_REG) & ~(1 << (50-32)), COMCERTO_GPIO_63_32_OUTPUT_REG);
+ /* Set GPIO[50] direction to output */
+ writel(readl(COMCERTO_GPIO_63_32_OE_REG) & ~(1 << (50-32)), COMCERTO_GPIO_63_32_OE_REG);
#endif
#ifdef CONFIG_COMCERTO_BOOTLOADER
/* Turn blue LED off, red LED on, to indicate the bootloader is running. */
