commit 05d98f464be486a509aad3194a3937889c766540
author Daniel Mentz <danielmentz@google.com> Tue Jul 28 16:06:55 2015 -0700
committer Daniel Mentz <danielmentz@google.com> Mon Aug 03 15:27:03 2015 -0700
tree dd439de1ab4b8616ca70910ff9c2e0d52a0ff2f7
parent 8f95cbfd66cc3e794ca5b6f8af105f8e460368a7

Add DDR configuration for Optimus/Sideswipe Prime

Optimus Prime and Sideswipe Prime have board ids (GPIO[55:57]) that are
different from Optimus and Sideswipe, but the DRAM chips are the same.

Change-Id: I62f68a45d6246bf3bde4b2a442b9924527ea3470

arch/arm/boards/optimus/ddr.c

diff --git a/arch/arm/boards/optimus/ddr.c b/arch/arm/boards/optimus/ddr.c
index ec86ce4..eb834ea 100644
--- a/arch/arm/boards/optimus/ddr.c
+++ b/arch/arm/boards/optimus/ddr.c
@@ -252,6 +252,9 @@
 	/* Nanya NT5CB128M16FP-DI, 533MHz, 32bit, NoECC */
 	{sideswipe_ddr_phy_cfg, sideswipe_ddrc_cfg, SZ_512M, "Sideswipe"},
 	{optimus_ddr_phy_cfg, spacecast_ddrc_cfg, SZ_1G, "SpaceCast"},
+	{0, 0, 0, "Unknown 3"},
+	{optimus_ddr_phy_cfg, optimus_ddrc_cfg, SZ_1G, "Optimus Prime"},
+	{sideswipe_ddr_phy_cfg, sideswipe_ddrc_cfg, SZ_512M, "Sideswipe Prime"},
 };
 
 static struct ddr_config bad_board_id_ddr_config = {0, 0, 0, "Unknown"};