Support for BCM6803 rev C0 hardware
A few driver changes were necessary to support C0 silicon:
For B0 hardware, we need to set port mode to 3 which is defined as
RGMII_0 <-> MoCA, GPHY and RGMII_1 powered down
For C0 hardware, we need to set port mode to 2 which is defined as
RGMII_1 <-> GPHY, RGMII_0 <-> MoCA
Previously, port mode was always set to 3.
Also, we had to change the order in which we write certain registers. It
turned out that we have to write to SUN_TOP_CTRL_SW_INIT_0_CLEAR before
we can write to registers in the MoCA block (0x10600000 - 0x107fffff)
Change-Id: Iaa17dc159a8d1c32273d1ad1c1fd1f83e8b52020
2 files changed
