Support for BCM6803 rev C0 hardware
A few driver changes were necessary to support C0 silicon:
For B0 hardware, we need to set port mode to 3 which is defined as
RGMII_0 <-> MoCA, GPHY and RGMII_1 powered down
For C0 hardware, we need to set port mode to 2 which is defined as
RGMII_1 <-> GPHY, RGMII_0 <-> MoCA
Previously, port mode was always set to 3.
Also, we had to change the order in which we write certain registers. It
turned out that we have to write to SUN_TOP_CTRL_SW_INIT_0_CLEAR before
we can write to registers in the MoCA block (0x10600000 - 0x107fffff)
Change-Id: Iaa17dc159a8d1c32273d1ad1c1fd1f83e8b52020
diff --git a/3.3/bmoca.c b/3.3/bmoca.c
index e8f1829..c39fa17 100644
--- a/3.3/bmoca.c
+++ b/3.3/bmoca.c
@@ -1738,6 +1738,10 @@
{
u32 data;
+ /* some platforms connect the i2c directly to the MoCA core */
+ if (!priv->i2c_base)
+ return;
+
mutex_lock(&priv->moca_i2c_mutex);
if (action == MOCA_ENABLE) {
diff --git a/bmoca-6802.c b/bmoca-6802.c
index 0df7bd6..cdf7f3a 100644
--- a/bmoca-6802.c
+++ b/bmoca-6802.c
@@ -436,8 +436,6 @@
if (action == MOCA_ENABLE && !priv->enabled) {
clk_enable(priv->clk);
- MOCA_WR(0x10404318, 0xfffffffd); // SUN_TOP_CTRL_SW_INIT_0_SET
- udelay(20);
MOCA_WR(0x1040431c, ~(1 << 26)); // SUN_TOP_CTRL_SW_INIT_0_CLEAR --> Do this at start of sequence, don't touch gphy_sw_init
udelay(20);
moca_gphy_init(priv);
@@ -452,14 +450,6 @@
moca_hw_reset(priv);
udelay(1);
- MOCA_WR(0x10800000, 0x03); // EMUX_CNTRL
- MOCA_WR(0x1080000c, 0x11); // RGMII_0_CNTRL
- MOCA_WR(0x10800014, 0xc0); // RGMII_0_RX_CLK_DELAY_CNTRL
-
- MOCA_WR(0x104040a4, 0x01); // GENERAL_CTRL_NO_SCAN_0
- MOCA_WR(0x10404100, 0x11110011); // PIN_MUX_CTRL_0
- MOCA_WR(0x10404104, 0x11111111); // PIN_MUX_CTRL_1
-
if (action == MOCA_ENABLE) {
/* Power up all zones */
@@ -915,6 +905,7 @@
{
#ifdef DSL_MOCA
struct moca_platform_data *pMocaData;
+ u32 port_mode;
pMocaData = (struct moca_platform_data *)priv->pdev->dev.platform_data;
@@ -926,6 +917,22 @@
return -EFAULT;
}
+ MOCA_WR(0x1040431c, 0x0FFFFFFF); // SUN_TOP_CTRL_SW_INIT_0_CLEAR
+ MOCA_WR(0x104040a4, 0x01); // GENERAL_CTRL_NO_SCAN_0
+ MOCA_WR(0x10404100, 0x11110011); // PIN_MUX_CTRL_0
+ MOCA_WR(0x10404104, 0x11111111); // PIN_MUX_CTRL_1
+
+ /* The definition of PORT_MODE has changed from chip revision B0 to C0
+ * */
+ if ((pMocaData->chip_id & 0xFFFEFFF0) == 0x680200C0)
+ port_mode = 2; /* RGMII_1 <-> GPHY, RGMII_0 <-> MoCA */
+ else
+ port_mode = 3; /* RGMII_0 <-> MoCA */
+
+ MOCA_WR(0x10800000, port_mode); // EMUX_CNTRL
+ MOCA_WR(0x1080000c, 0x11); // RGMII_0_CNTRL
+ MOCA_WR(0x10800014, 0xc0); // RGMII_0_RX_CLK_DELAY_CNTRL
+
if (((pMocaData->chip_id & 0xFFFFFFF0) == 0x680200C0) || ((pMocaData->chip_id & 0xFFFFFFF0) == 0x680300C0))
{
priv->i2c_base = NULL;
