blob: 1de41efff9673a760f0e0a51499a4348843314c6 [file] [log] [blame]
/*
* QCA 955x series processor SOC registers
*
* Copyright (c) 2013 Qualcomm Atheros, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _QCA955X_H
#define _QCA955X_H
#ifndef __ASSEMBLY__
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <linux/types.h>
#endif /* __ASSEMBLY__ */
#undef is_qca955x
#undef is_sco
#define is_qca955x() (1)
#define is_sco() (1)
#define CPU_PLL_CONFIG_UPDATING_MSB 31
#define CPU_PLL_CONFIG_UPDATING_LSB 31
#define CPU_PLL_CONFIG_UPDATING_MASK 0x80000000
#define CPU_PLL_CONFIG_UPDATING_GET(x) (((x) & CPU_PLL_CONFIG_UPDATING_MASK) >> CPU_PLL_CONFIG_UPDATING_LSB)
#define CPU_PLL_CONFIG_UPDATING_SET(x) (((x) << CPU_PLL_CONFIG_UPDATING_LSB) & CPU_PLL_CONFIG_UPDATING_MASK)
#define CPU_PLL_CONFIG_UPDATING_RESET 0x1 // 1
#define CPU_PLL_CONFIG_PLLPWD_MSB 30
#define CPU_PLL_CONFIG_PLLPWD_LSB 30
#define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000
#define CPU_PLL_CONFIG_PLLPWD_GET(x) (((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB)
#define CPU_PLL_CONFIG_PLLPWD_SET(x) (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
#define CPU_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
#define CPU_PLL_CONFIG_SPARE_MSB 29
#define CPU_PLL_CONFIG_SPARE_LSB 22
#define CPU_PLL_CONFIG_SPARE_MASK 0x3fc00000
#define CPU_PLL_CONFIG_SPARE_GET(x) (((x) & CPU_PLL_CONFIG_SPARE_MASK) >> CPU_PLL_CONFIG_SPARE_LSB)
#define CPU_PLL_CONFIG_SPARE_SET(x) (((x) << CPU_PLL_CONFIG_SPARE_LSB) & CPU_PLL_CONFIG_SPARE_MASK)
#define CPU_PLL_CONFIG_SPARE_RESET 0x0 // 0
#define CPU_PLL_CONFIG_OUTDIV_MSB 21
#define CPU_PLL_CONFIG_OUTDIV_LSB 19
#define CPU_PLL_CONFIG_OUTDIV_MASK 0x00380000
#define CPU_PLL_CONFIG_OUTDIV_GET(x) (((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB)
#define CPU_PLL_CONFIG_OUTDIV_SET(x) (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK)
#define CPU_PLL_CONFIG_OUTDIV_RESET 0x0 // 0
#define CPU_PLL_CONFIG_RANGE_MSB 18
#define CPU_PLL_CONFIG_RANGE_LSB 17
#define CPU_PLL_CONFIG_RANGE_MASK 0x00060000
#define CPU_PLL_CONFIG_RANGE_GET(x) (((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB)
#define CPU_PLL_CONFIG_RANGE_SET(x) (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK)
#define CPU_PLL_CONFIG_RANGE_RESET 0x3 // 3
#define CPU_PLL_CONFIG_REFDIV_MSB 16
#define CPU_PLL_CONFIG_REFDIV_LSB 12
#define CPU_PLL_CONFIG_REFDIV_MASK 0x0001f000
#define CPU_PLL_CONFIG_REFDIV_GET(x) (((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB)
#define CPU_PLL_CONFIG_REFDIV_SET(x) (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK)
#define CPU_PLL_CONFIG_REFDIV_RESET 0x2 // 2
#define CPU_PLL_CONFIG_NINT_MSB 11
#define CPU_PLL_CONFIG_NINT_LSB 6
#define CPU_PLL_CONFIG_NINT_MASK 0x00000fc0
#define CPU_PLL_CONFIG_NINT_GET(x) (((x) & CPU_PLL_CONFIG_NINT_MASK) >> CPU_PLL_CONFIG_NINT_LSB)
#define CPU_PLL_CONFIG_NINT_SET(x) (((x) << CPU_PLL_CONFIG_NINT_LSB) & CPU_PLL_CONFIG_NINT_MASK)
#define CPU_PLL_CONFIG_NINT_RESET 0x14 // 20
#define CPU_PLL_CONFIG_NFRAC_MSB 5
#define CPU_PLL_CONFIG_NFRAC_LSB 0
#define CPU_PLL_CONFIG_NFRAC_MASK 0x0000003f
#define CPU_PLL_CONFIG_NFRAC_GET(x) (((x) & CPU_PLL_CONFIG_NFRAC_MASK) >> CPU_PLL_CONFIG_NFRAC_LSB)
#define CPU_PLL_CONFIG_NFRAC_SET(x) (((x) << CPU_PLL_CONFIG_NFRAC_LSB) & CPU_PLL_CONFIG_NFRAC_MASK)
#define CPU_PLL_CONFIG_NFRAC_RESET 0x10 // 16
#define CPU_PLL_CONFIG_ADDRESS 0x18050000
#define DDR_PLL_CONFIG_UPDATING_MSB 31
#define DDR_PLL_CONFIG_UPDATING_LSB 31
#define DDR_PLL_CONFIG_UPDATING_MASK 0x80000000
#define DDR_PLL_CONFIG_UPDATING_GET(x) (((x) & DDR_PLL_CONFIG_UPDATING_MASK) >> DDR_PLL_CONFIG_UPDATING_LSB)
#define DDR_PLL_CONFIG_UPDATING_SET(x) (((x) << DDR_PLL_CONFIG_UPDATING_LSB) & DDR_PLL_CONFIG_UPDATING_MASK)
#define DDR_PLL_CONFIG_UPDATING_RESET 0x1 // 1
#define DDR_PLL_CONFIG_PLLPWD_MSB 30
#define DDR_PLL_CONFIG_PLLPWD_LSB 30
#define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000
#define DDR_PLL_CONFIG_PLLPWD_GET(x) (((x) & DDR_PLL_CONFIG_PLLPWD_MASK) >> DDR_PLL_CONFIG_PLLPWD_LSB)
#define DDR_PLL_CONFIG_PLLPWD_SET(x) (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
#define DDR_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
#define DDR_PLL_CONFIG_SPARE_MSB 29
#define DDR_PLL_CONFIG_SPARE_LSB 26
#define DDR_PLL_CONFIG_SPARE_MASK 0x3c000000
#define DDR_PLL_CONFIG_SPARE_GET(x) (((x) & DDR_PLL_CONFIG_SPARE_MASK) >> DDR_PLL_CONFIG_SPARE_LSB)
#define DDR_PLL_CONFIG_SPARE_SET(x) (((x) << DDR_PLL_CONFIG_SPARE_LSB) & DDR_PLL_CONFIG_SPARE_MASK)
#define DDR_PLL_CONFIG_SPARE_RESET 0x0 // 0
#define DDR_PLL_CONFIG_OUTDIV_MSB 25
#define DDR_PLL_CONFIG_OUTDIV_LSB 23
#define DDR_PLL_CONFIG_OUTDIV_MASK 0x03800000
#define DDR_PLL_CONFIG_OUTDIV_GET(x) (((x) & DDR_PLL_CONFIG_OUTDIV_MASK) >> DDR_PLL_CONFIG_OUTDIV_LSB)
#define DDR_PLL_CONFIG_OUTDIV_SET(x) (((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK)
#define DDR_PLL_CONFIG_OUTDIV_RESET 0x0 // 0
#define DDR_PLL_CONFIG_RANGE_MSB 22
#define DDR_PLL_CONFIG_RANGE_LSB 21
#define DDR_PLL_CONFIG_RANGE_MASK 0x00600000
#define DDR_PLL_CONFIG_RANGE_GET(x) (((x) & DDR_PLL_CONFIG_RANGE_MASK) >> DDR_PLL_CONFIG_RANGE_LSB)
#define DDR_PLL_CONFIG_RANGE_SET(x) (((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK)
#define DDR_PLL_CONFIG_RANGE_RESET 0x3 // 3
#define DDR_PLL_CONFIG_REFDIV_MSB 20
#define DDR_PLL_CONFIG_REFDIV_LSB 16
#define DDR_PLL_CONFIG_REFDIV_MASK 0x001f0000
#define DDR_PLL_CONFIG_REFDIV_GET(x) (((x) & DDR_PLL_CONFIG_REFDIV_MASK) >> DDR_PLL_CONFIG_REFDIV_LSB)
#define DDR_PLL_CONFIG_REFDIV_SET(x) (((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK)
#define DDR_PLL_CONFIG_REFDIV_RESET 0x2 // 2
#define DDR_PLL_CONFIG_NINT_MSB 15
#define DDR_PLL_CONFIG_NINT_LSB 10
#define DDR_PLL_CONFIG_NINT_MASK 0x0000fc00
#define DDR_PLL_CONFIG_NINT_GET(x) (((x) & DDR_PLL_CONFIG_NINT_MASK) >> DDR_PLL_CONFIG_NINT_LSB)
#define DDR_PLL_CONFIG_NINT_SET(x) (((x) << DDR_PLL_CONFIG_NINT_LSB) & DDR_PLL_CONFIG_NINT_MASK)
#define DDR_PLL_CONFIG_NINT_RESET 0x14 // 20
#define DDR_PLL_CONFIG_NFRAC_MSB 9
#define DDR_PLL_CONFIG_NFRAC_LSB 0
#define DDR_PLL_CONFIG_NFRAC_MASK 0x000003ff
#define DDR_PLL_CONFIG_NFRAC_GET(x) (((x) & DDR_PLL_CONFIG_NFRAC_MASK) >> DDR_PLL_CONFIG_NFRAC_LSB)
#define DDR_PLL_CONFIG_NFRAC_SET(x) (((x) << DDR_PLL_CONFIG_NFRAC_LSB) & DDR_PLL_CONFIG_NFRAC_MASK)
#define DDR_PLL_CONFIG_NFRAC_RESET 0x200 // 512
#define DDR_PLL_CONFIG_ADDRESS 0x18050004
#define DDR_CTL_CONFIG_SRAM_TSEL_MSB 31
#define DDR_CTL_CONFIG_SRAM_TSEL_LSB 30
#define DDR_CTL_CONFIG_SRAM_TSEL_MASK 0xc0000000
#define DDR_CTL_CONFIG_SRAM_TSEL_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) >> DDR_CTL_CONFIG_SRAM_TSEL_LSB)
#define DDR_CTL_CONFIG_SRAM_TSEL_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK)
#define DDR_CTL_CONFIG_SRAM_TSEL_RESET 0x1 // 1
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MSB 29
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB 21
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK 0x3fe00000
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_GET(x) (((x) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) >> DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB)
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_SET(x) (((x) << DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK)
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_RESET 0x0 // 0
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MSB 20
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB 20
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK 0x00100000
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_RESET 0x1 // 1
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MSB 19
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB 19
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK 0x00080000
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_RESET 0x1 // 1
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MSB 18
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB 18
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK 0x00040000
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_RESET 0x1 // 1
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MSB 17
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB 17
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK 0x00020000
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_RESET 0x1 // 1
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MSB 16
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB 16
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK 0x00010000
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_RESET 0x1 // 1
#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MSB 15
#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_LSB 15
#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK 0x00008000
#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_RESET 0x1 // 1
#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MSB 14
#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_LSB 14
#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK 0x00004000
#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_RESET 0x1 // 1
#define DDR_CTL_CONFIG_SPARE_MSB 13
#define DDR_CTL_CONFIG_SPARE_LSB 7
#define DDR_CTL_CONFIG_SPARE_MASK 0x00003f80
#define DDR_CTL_CONFIG_SPARE_GET(x) (((x) & DDR_CTL_CONFIG_SPARE_MASK) >> DDR_CTL_CONFIG_SPARE_LSB)
#define DDR_CTL_CONFIG_SPARE_SET(x) (((x) << DDR_CTL_CONFIG_SPARE_LSB) & DDR_CTL_CONFIG_SPARE_MASK)
#define DDR_CTL_CONFIG_SPARE_RESET 0x0 // 0
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MSB 6
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB 6
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK 0x00000040
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_GET(x) (((x) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK) >> DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB)
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(x) (((x) << DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK)
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_RESET 0x0 // 0
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_MSB 4
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB 4
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK 0x00000010
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_GET(x) (((x) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK) >> DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB)
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_SET(x) (((x) << DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK)
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_RESET 0x0 // 0
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_MSB 3
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB 3
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK 0x00000008
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK) >> DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB)
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK)
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_RESET 0x0 // 0
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MSB 2
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB 2
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK 0x00000004
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK) >> DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB)
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK)
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_RESET 0x0 // 0
#define DDR_CTL_CONFIG_HALF_WIDTH_MSB 1
#define DDR_CTL_CONFIG_HALF_WIDTH_LSB 1
#define DDR_CTL_CONFIG_HALF_WIDTH_MASK 0x00000002
#define DDR_CTL_CONFIG_HALF_WIDTH_GET(x) (((x) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) >> DDR_CTL_CONFIG_HALF_WIDTH_LSB)
#define DDR_CTL_CONFIG_HALF_WIDTH_SET(x) (((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & DDR_CTL_CONFIG_HALF_WIDTH_MASK)
#define DDR_CTL_CONFIG_HALF_WIDTH_RESET 0x1 // 1
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_MSB 0
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB 0
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK 0x00000001
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_GET(x) (((x) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK) >> DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB)
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_SET(x) (((x) << DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK)
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_RESET 0x0 // 0
#define DDR_CTL_CONFIG_ADDRESS 0x18000108
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MSB 31
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB 31
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK 0x80000000
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_GET(x) (((x) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK) >> DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB)
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_SET(x) (((x) << DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK)
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MSB 30
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB 30
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK 0x40000000
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_GET(x) (((x) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK) >> DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB)
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_SET(x) (((x) << DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK)
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_MSB 29
#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB 29
#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK 0x20000000
#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_GET(x) (((x) & DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK) >> DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB)
#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_SET(x) (((x) << DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB) & DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK)
#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MSB 28
#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB 28
#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK 0x10000000
#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_GET(x) (((x) & DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK) >> DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB)
#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_SET(x) (((x) << DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB) & DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK)
#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_RESET 0x1 // 1
#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MSB 27
#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB 27
#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK 0x08000000
#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_GET(x) (((x) & DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK) >> DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB)
#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_SET(x) (((x) << DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB) & DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK)
#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MSB 14
#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB 13
#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK 0x00006000
#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK) >> DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB)
#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB) & DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK)
#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_GATE_TAP_MSB 12
#define DDR_DEBUG_RD_CNTL_GATE_TAP_LSB 8
#define DDR_DEBUG_RD_CNTL_GATE_TAP_MASK 0x00001f00
#define DDR_DEBUG_RD_CNTL_GATE_TAP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_TAP_MASK) >> DDR_DEBUG_RD_CNTL_GATE_TAP_LSB)
#define DDR_DEBUG_RD_CNTL_GATE_TAP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_TAP_LSB) & DDR_DEBUG_RD_CNTL_GATE_TAP_MASK)
#define DDR_DEBUG_RD_CNTL_GATE_TAP_RESET 0x1 // 1
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MSB 6
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB 5
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK 0x00000060
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB)
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB) & DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK)
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_MSB 4
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB 0
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK 0x0000001f
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB)
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB) & DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK)
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_RESET 0x1 // 1
#define DDR_DEBUG_RD_CNTL_ADDRESS 0x18000118
#define DDR2_CONFIG_DDR2_TWL_MSB 13
#define DDR2_CONFIG_DDR2_TWL_LSB 10
#define DDR2_CONFIG_DDR2_TWL_MASK 0x00003c00
#define DDR2_CONFIG_DDR2_TWL_GET(x) (((x) & DDR2_CONFIG_DDR2_TWL_MASK) >> DDR2_CONFIG_DDR2_TWL_LSB)
#define DDR2_CONFIG_DDR2_TWL_SET(x) (((x) << DDR2_CONFIG_DDR2_TWL_LSB) & DDR2_CONFIG_DDR2_TWL_MASK)
#define DDR2_CONFIG_DDR2_TWL_RESET 0x1 // 1
#define DDR2_CONFIG_DDR2_ODT_MSB 9
#define DDR2_CONFIG_DDR2_ODT_LSB 9
#define DDR2_CONFIG_DDR2_ODT_MASK 0x00000200
#define DDR2_CONFIG_DDR2_ODT_GET(x) (((x) & DDR2_CONFIG_DDR2_ODT_MASK) >> DDR2_CONFIG_DDR2_ODT_LSB)
#define DDR2_CONFIG_DDR2_ODT_SET(x) (((x) << DDR2_CONFIG_DDR2_ODT_LSB) & DDR2_CONFIG_DDR2_ODT_MASK)
#define DDR2_CONFIG_DDR2_ODT_RESET 0x1 // 1
#define DDR2_CONFIG_TFAW_MSB 7
#define DDR2_CONFIG_TFAW_LSB 2
#define DDR2_CONFIG_TFAW_MASK 0x000000fc
#define DDR2_CONFIG_TFAW_GET(x) (((x) & DDR2_CONFIG_TFAW_MASK) >> DDR2_CONFIG_TFAW_LSB)
#define DDR2_CONFIG_TFAW_SET(x) (((x) << DDR2_CONFIG_TFAW_LSB) & DDR2_CONFIG_TFAW_MASK)
#define DDR2_CONFIG_TFAW_RESET 0x16 // 22
#define DDR2_CONFIG_ENABLE_DDR2_MSB 0
#define DDR2_CONFIG_ENABLE_DDR2_LSB 0
#define DDR2_CONFIG_ENABLE_DDR2_MASK 0x00000001
#define DDR2_CONFIG_ENABLE_DDR2_GET(x) (((x) & DDR2_CONFIG_ENABLE_DDR2_MASK) >> DDR2_CONFIG_ENABLE_DDR2_LSB)
#define DDR2_CONFIG_ENABLE_DDR2_SET(x) (((x) << DDR2_CONFIG_ENABLE_DDR2_LSB) & DDR2_CONFIG_ENABLE_DDR2_MASK)
#define DDR2_CONFIG_ENABLE_DDR2_RESET 0x0 // 0
#define DDR2_CONFIG_ADDRESS 0x180000b8
#define DDR_CONTROL_EMR3S_MSB 5
#define DDR_CONTROL_EMR3S_LSB 5
#define DDR_CONTROL_EMR3S_MASK 0x00000020
#define DDR_CONTROL_EMR3S_GET(x) (((x) & DDR_CONTROL_EMR3S_MASK) >> DDR_CONTROL_EMR3S_LSB)
#define DDR_CONTROL_EMR3S_SET(x) (((x) << DDR_CONTROL_EMR3S_LSB) & DDR_CONTROL_EMR3S_MASK)
#define DDR_CONTROL_EMR3S_RESET 0x0 // 0
#define DDR_CONTROL_EMR2S_MSB 4
#define DDR_CONTROL_EMR2S_LSB 4
#define DDR_CONTROL_EMR2S_MASK 0x00000010
#define DDR_CONTROL_EMR2S_GET(x) (((x) & DDR_CONTROL_EMR2S_MASK) >> DDR_CONTROL_EMR2S_LSB)
#define DDR_CONTROL_EMR2S_SET(x) (((x) << DDR_CONTROL_EMR2S_LSB) & DDR_CONTROL_EMR2S_MASK)
#define DDR_CONTROL_EMR2S_RESET 0x0 // 0
#define DDR_CONTROL_PREA_MSB 3
#define DDR_CONTROL_PREA_LSB 3
#define DDR_CONTROL_PREA_MASK 0x00000008
#define DDR_CONTROL_PREA_GET(x) (((x) & DDR_CONTROL_PREA_MASK) >> DDR_CONTROL_PREA_LSB)
#define DDR_CONTROL_PREA_SET(x) (((x) << DDR_CONTROL_PREA_LSB) & DDR_CONTROL_PREA_MASK)
#define DDR_CONTROL_PREA_RESET 0x0 // 0
#define DDR_CONTROL_REF_MSB 2
#define DDR_CONTROL_REF_LSB 2
#define DDR_CONTROL_REF_MASK 0x00000004
#define DDR_CONTROL_REF_GET(x) (((x) & DDR_CONTROL_REF_MASK) >> DDR_CONTROL_REF_LSB)
#define DDR_CONTROL_REF_SET(x) (((x) << DDR_CONTROL_REF_LSB) & DDR_CONTROL_REF_MASK)
#define DDR_CONTROL_REF_RESET 0x0 // 0
#define DDR_CONTROL_EMRS_MSB 1
#define DDR_CONTROL_EMRS_LSB 1
#define DDR_CONTROL_EMRS_MASK 0x00000002
#define DDR_CONTROL_EMRS_GET(x) (((x) & DDR_CONTROL_EMRS_MASK) >> DDR_CONTROL_EMRS_LSB)
#define DDR_CONTROL_EMRS_SET(x) (((x) << DDR_CONTROL_EMRS_LSB) & DDR_CONTROL_EMRS_MASK)
#define DDR_CONTROL_EMRS_RESET 0x0 // 0
#define DDR_CONTROL_MRS_MSB 0
#define DDR_CONTROL_MRS_LSB 0
#define DDR_CONTROL_MRS_MASK 0x00000001
#define DDR_CONTROL_MRS_GET(x) (((x) & DDR_CONTROL_MRS_MASK) >> DDR_CONTROL_MRS_LSB)
#define DDR_CONTROL_MRS_SET(x) (((x) << DDR_CONTROL_MRS_LSB) & DDR_CONTROL_MRS_MASK)
#define DDR_CONTROL_MRS_RESET 0x0 // 0
#define DDR_CONTROL_ADDRESS 0x18000010
#define DDR_CONFIG_CAS_LATENCY_MSB_MSB 31
#define DDR_CONFIG_CAS_LATENCY_MSB_LSB 31
#define DDR_CONFIG_CAS_LATENCY_MSB_MASK 0x80000000
#define DDR_CONFIG_CAS_LATENCY_MSB_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) >> DDR_CONFIG_CAS_LATENCY_MSB_LSB)
#define DDR_CONFIG_CAS_LATENCY_MSB_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & DDR_CONFIG_CAS_LATENCY_MSB_MASK)
#define DDR_CONFIG_CAS_LATENCY_MSB_RESET 0x0 // 0
#define DDR_CONFIG_OPEN_PAGE_MSB 30
#define DDR_CONFIG_OPEN_PAGE_LSB 30
#define DDR_CONFIG_OPEN_PAGE_MASK 0x40000000
#define DDR_CONFIG_OPEN_PAGE_GET(x) (((x) & DDR_CONFIG_OPEN_PAGE_MASK) >> DDR_CONFIG_OPEN_PAGE_LSB)
#define DDR_CONFIG_OPEN_PAGE_SET(x) (((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK)
#define DDR_CONFIG_OPEN_PAGE_RESET 0x1 // 1
#define DDR_CONFIG_CAS_LATENCY_MSB 29
#define DDR_CONFIG_CAS_LATENCY_LSB 27
#define DDR_CONFIG_CAS_LATENCY_MASK 0x38000000
#define DDR_CONFIG_CAS_LATENCY_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MASK) >> DDR_CONFIG_CAS_LATENCY_LSB)
#define DDR_CONFIG_CAS_LATENCY_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK)
#define DDR_CONFIG_CAS_LATENCY_RESET 0x6 // 6
#define DDR_CONFIG_TMRD_MSB 26
#define DDR_CONFIG_TMRD_LSB 23
#define DDR_CONFIG_TMRD_MASK 0x07800000
#define DDR_CONFIG_TMRD_GET(x) (((x) & DDR_CONFIG_TMRD_MASK) >> DDR_CONFIG_TMRD_LSB)
#define DDR_CONFIG_TMRD_SET(x) (((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK)
#define DDR_CONFIG_TMRD_RESET 0xf // 15
#define DDR_CONFIG_TRFC_MSB 22
#define DDR_CONFIG_TRFC_LSB 17
#define DDR_CONFIG_TRFC_MASK 0x007e0000
#define DDR_CONFIG_TRFC_GET(x) (((x) & DDR_CONFIG_TRFC_MASK) >> DDR_CONFIG_TRFC_LSB)
#define DDR_CONFIG_TRFC_SET(x) (((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK)
#define DDR_CONFIG_TRFC_RESET 0x24 // 36
#define DDR_CONFIG_TRRD_MSB 16
#define DDR_CONFIG_TRRD_LSB 13
#define DDR_CONFIG_TRRD_MASK 0x0001e000
#define DDR_CONFIG_TRRD_GET(x) (((x) & DDR_CONFIG_TRRD_MASK) >> DDR_CONFIG_TRRD_LSB)
#define DDR_CONFIG_TRRD_SET(x) (((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK)
#define DDR_CONFIG_TRRD_RESET 0x4 // 4
#define DDR_CONFIG_TRP_MSB 12
#define DDR_CONFIG_TRP_LSB 9
#define DDR_CONFIG_TRP_MASK 0x00001e00
#define DDR_CONFIG_TRP_GET(x) (((x) & DDR_CONFIG_TRP_MASK) >> DDR_CONFIG_TRP_LSB)
#define DDR_CONFIG_TRP_SET(x) (((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK)
#define DDR_CONFIG_TRP_RESET 0x6 // 6
#define DDR_CONFIG_TRCD_MSB 8
#define DDR_CONFIG_TRCD_LSB 5
#define DDR_CONFIG_TRCD_MASK 0x000001e0
#define DDR_CONFIG_TRCD_GET(x) (((x) & DDR_CONFIG_TRCD_MASK) >> DDR_CONFIG_TRCD_LSB)
#define DDR_CONFIG_TRCD_SET(x) (((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK)
#define DDR_CONFIG_TRCD_RESET 0x6 // 6
#define DDR_CONFIG_TRAS_MSB 4
#define DDR_CONFIG_TRAS_LSB 0
#define DDR_CONFIG_TRAS_MASK 0x0000001f
#define DDR_CONFIG_TRAS_GET(x) (((x) & DDR_CONFIG_TRAS_MASK) >> DDR_CONFIG_TRAS_LSB)
#define DDR_CONFIG_TRAS_SET(x) (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
#define DDR_CONFIG_TRAS_RESET 0x10 // 16
#define DDR_CONFIG_ADDRESS 0x18000000
#define DDR_CONFIG2_HALF_WIDTH_LOW_MSB 31
#define DDR_CONFIG2_HALF_WIDTH_LOW_LSB 31
#define DDR_CONFIG2_HALF_WIDTH_LOW_MASK 0x80000000
#define DDR_CONFIG2_HALF_WIDTH_LOW_GET(x) (((x) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) >> DDR_CONFIG2_HALF_WIDTH_LOW_LSB)
#define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x) (((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK)
#define DDR_CONFIG2_HALF_WIDTH_LOW_RESET 0x1 // 1
#define DDR_CONFIG2_SWAP_A26_A27_MSB 30
#define DDR_CONFIG2_SWAP_A26_A27_LSB 30
#define DDR_CONFIG2_SWAP_A26_A27_MASK 0x40000000
#define DDR_CONFIG2_SWAP_A26_A27_GET(x) (((x) & DDR_CONFIG2_SWAP_A26_A27_MASK) >> DDR_CONFIG2_SWAP_A26_A27_LSB)
#define DDR_CONFIG2_SWAP_A26_A27_SET(x) (((x) << DDR_CONFIG2_SWAP_A26_A27_LSB) & DDR_CONFIG2_SWAP_A26_A27_MASK)
#define DDR_CONFIG2_SWAP_A26_A27_RESET 0x0 // 0
#define DDR_CONFIG2_GATE_OPEN_LATENCY_MSB 29
#define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB 26
#define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK 0x3c000000
#define DDR_CONFIG2_GATE_OPEN_LATENCY_GET(x) (((x) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) >> DDR_CONFIG2_GATE_OPEN_LATENCY_LSB)
#define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x) (((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK)
#define DDR_CONFIG2_GATE_OPEN_LATENCY_RESET 0x6 // 6
#define DDR_CONFIG2_TWTR_MSB 25
#define DDR_CONFIG2_TWTR_LSB 21
#define DDR_CONFIG2_TWTR_MASK 0x03e00000
#define DDR_CONFIG2_TWTR_GET(x) (((x) & DDR_CONFIG2_TWTR_MASK) >> DDR_CONFIG2_TWTR_LSB)
#define DDR_CONFIG2_TWTR_SET(x) (((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK)
#define DDR_CONFIG2_TWTR_RESET 0xe // 14
#define DDR_CONFIG2_TRTP_MSB 20
#define DDR_CONFIG2_TRTP_LSB 17
#define DDR_CONFIG2_TRTP_MASK 0x001e0000
#define DDR_CONFIG2_TRTP_GET(x) (((x) & DDR_CONFIG2_TRTP_MASK) >> DDR_CONFIG2_TRTP_LSB)
#define DDR_CONFIG2_TRTP_SET(x) (((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK)
#define DDR_CONFIG2_TRTP_RESET 0x8 // 8
#define DDR_CONFIG2_TRTW_MSB 16
#define DDR_CONFIG2_TRTW_LSB 12
#define DDR_CONFIG2_TRTW_MASK 0x0001f000
#define DDR_CONFIG2_TRTW_GET(x) (((x) & DDR_CONFIG2_TRTW_MASK) >> DDR_CONFIG2_TRTW_LSB)
#define DDR_CONFIG2_TRTW_SET(x) (((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK)
#define DDR_CONFIG2_TRTW_RESET 0x10 // 16
#define DDR_CONFIG2_TWR_MSB 11
#define DDR_CONFIG2_TWR_LSB 8
#define DDR_CONFIG2_TWR_MASK 0x00000f00
#define DDR_CONFIG2_TWR_GET(x) (((x) & DDR_CONFIG2_TWR_MASK) >> DDR_CONFIG2_TWR_LSB)
#define DDR_CONFIG2_TWR_SET(x) (((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK)
#define DDR_CONFIG2_TWR_RESET 0x6 // 6
#define DDR_CONFIG2_CKE_MSB 7
#define DDR_CONFIG2_CKE_LSB 7
#define DDR_CONFIG2_CKE_MASK 0x00000080
#define DDR_CONFIG2_CKE_GET(x) (((x) & DDR_CONFIG2_CKE_MASK) >> DDR_CONFIG2_CKE_LSB)
#define DDR_CONFIG2_CKE_SET(x) (((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK)
#define DDR_CONFIG2_CKE_RESET 0x0 // 0
#define DDR_CONFIG2_PHASE_SELECT_MSB 6
#define DDR_CONFIG2_PHASE_SELECT_LSB 6
#define DDR_CONFIG2_PHASE_SELECT_MASK 0x00000040
#define DDR_CONFIG2_PHASE_SELECT_GET(x) (((x) & DDR_CONFIG2_PHASE_SELECT_MASK) >> DDR_CONFIG2_PHASE_SELECT_LSB)
#define DDR_CONFIG2_PHASE_SELECT_SET(x) (((x) << DDR_CONFIG2_PHASE_SELECT_LSB) & DDR_CONFIG2_PHASE_SELECT_MASK)
#define DDR_CONFIG2_PHASE_SELECT_RESET 0x0 // 0
#define DDR_CONFIG2_CNTL_OE_EN_MSB 5
#define DDR_CONFIG2_CNTL_OE_EN_LSB 5
#define DDR_CONFIG2_CNTL_OE_EN_MASK 0x00000020
#define DDR_CONFIG2_CNTL_OE_EN_GET(x) (((x) & DDR_CONFIG2_CNTL_OE_EN_MASK) >> DDR_CONFIG2_CNTL_OE_EN_LSB)
#define DDR_CONFIG2_CNTL_OE_EN_SET(x) (((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK)
#define DDR_CONFIG2_CNTL_OE_EN_RESET 0x1 // 1
#define DDR_CONFIG2_BURST_TYPE_MSB 4
#define DDR_CONFIG2_BURST_TYPE_LSB 4
#define DDR_CONFIG2_BURST_TYPE_MASK 0x00000010
#define DDR_CONFIG2_BURST_TYPE_GET(x) (((x) & DDR_CONFIG2_BURST_TYPE_MASK) >> DDR_CONFIG2_BURST_TYPE_LSB)
#define DDR_CONFIG2_BURST_TYPE_SET(x) (((x) << DDR_CONFIG2_BURST_TYPE_LSB) & DDR_CONFIG2_BURST_TYPE_MASK)
#define DDR_CONFIG2_BURST_TYPE_RESET 0x0 // 0
#define DDR_CONFIG2_BURST_LENGTH_MSB 3
#define DDR_CONFIG2_BURST_LENGTH_LSB 0
#define DDR_CONFIG2_BURST_LENGTH_MASK 0x0000000f
#define DDR_CONFIG2_BURST_LENGTH_GET(x) (((x) & DDR_CONFIG2_BURST_LENGTH_MASK) >> DDR_CONFIG2_BURST_LENGTH_LSB)
#define DDR_CONFIG2_BURST_LENGTH_SET(x) (((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK)
#define DDR_CONFIG2_BURST_LENGTH_RESET 0x8 // 8
#define DDR_CONFIG2_ADDRESS 0x18000004
#define DDR_CONFIG_3_SPARE_MSB 31
#define DDR_CONFIG_3_SPARE_LSB 4
#define DDR_CONFIG_3_SPARE_MASK 0xfffffff0
#define DDR_CONFIG_3_SPARE_GET(x) (((x) & DDR_CONFIG_3_SPARE_MASK) >> DDR_CONFIG_3_SPARE_LSB)
#define DDR_CONFIG_3_SPARE_SET(x) (((x) << DDR_CONFIG_3_SPARE_LSB) & DDR_CONFIG_3_SPARE_MASK)
#define DDR_CONFIG_3_SPARE_RESET 0x0 // 0
#define DDR_CONFIG_3_TWR_MSB_MSB 3
#define DDR_CONFIG_3_TWR_MSB_LSB 3
#define DDR_CONFIG_3_TWR_MSB_MASK 0x00000008
#define DDR_CONFIG_3_TWR_MSB_GET(x) (((x) & DDR_CONFIG_3_TWR_MSB_MASK) >> DDR_CONFIG_3_TWR_MSB_LSB)
#define DDR_CONFIG_3_TWR_MSB_SET(x) (((x) << DDR_CONFIG_3_TWR_MSB_LSB) & DDR_CONFIG_3_TWR_MSB_MASK)
#define DDR_CONFIG_3_TWR_MSB_RESET 0x0 // 0
#define DDR_CONFIG_3_TRAS_MSB_MSB 2
#define DDR_CONFIG_3_TRAS_MSB_LSB 2
#define DDR_CONFIG_3_TRAS_MSB_MASK 0x00000004
#define DDR_CONFIG_3_TRAS_MSB_GET(x) (((x) & DDR_CONFIG_3_TRAS_MSB_MASK) >> DDR_CONFIG_3_TRAS_MSB_LSB)
#define DDR_CONFIG_3_TRAS_MSB_SET(x) (((x) << DDR_CONFIG_3_TRAS_MSB_LSB) & DDR_CONFIG_3_TRAS_MSB_MASK)
#define DDR_CONFIG_3_TRAS_MSB_RESET 0x0 // 0
#define DDR_CONFIG_3_TRFC_LSB_MSB 1
#define DDR_CONFIG_3_TRFC_LSB_LSB 0
#define DDR_CONFIG_3_TRFC_LSB_MASK 0x00000003
#define DDR_CONFIG_3_TRFC_LSB_GET(x) (((x) & DDR_CONFIG_3_TRFC_LSB_MASK) >> DDR_CONFIG_3_TRFC_LSB_LSB)
#define DDR_CONFIG_3_TRFC_LSB_SET(x) (((x) << DDR_CONFIG_3_TRFC_LSB_LSB) & DDR_CONFIG_3_TRFC_LSB_MASK)
#define DDR_CONFIG_3_TRFC_LSB_RESET 0x0 // 0
#define DDR_CONFIG_3_ADDRESS 0x1800015c
#define DDR_MODE_REGISTER_VALUE_MSB 13
#define DDR_MODE_REGISTER_VALUE_LSB 0
#define DDR_MODE_REGISTER_VALUE_MASK 0x00003fff
#define DDR_MODE_REGISTER_VALUE_GET(x) (((x) & DDR_MODE_REGISTER_VALUE_MASK) >> DDR_MODE_REGISTER_VALUE_LSB)
#define DDR_MODE_REGISTER_VALUE_SET(x) (((x) << DDR_MODE_REGISTER_VALUE_LSB) & DDR_MODE_REGISTER_VALUE_MASK)
#define DDR_MODE_REGISTER_VALUE_RESET 0x133 // 307
#define DDR_MODE_REGISTER_ADDRESS 0x18000008
#define DDR_EXTENDED_MODE_REGISTER_VALUE_MSB 13
#define DDR_EXTENDED_MODE_REGISTER_VALUE_LSB 0
#define DDR_EXTENDED_MODE_REGISTER_VALUE_MASK 0x00003fff
#define DDR_EXTENDED_MODE_REGISTER_VALUE_GET(x) (((x) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK) >> DDR_EXTENDED_MODE_REGISTER_VALUE_LSB)
#define DDR_EXTENDED_MODE_REGISTER_VALUE_SET(x) (((x) << DDR_EXTENDED_MODE_REGISTER_VALUE_LSB) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK)
#define DDR_EXTENDED_MODE_REGISTER_VALUE_RESET 0x2 // 2
#define DDR_EXTENDED_MODE_REGISTER_ADDRESS 0x1800000c
#define DDR_REFRESH_ENABLE_MSB 14
#define DDR_REFRESH_ENABLE_LSB 14
#define DDR_REFRESH_ENABLE_MASK 0x00004000
#define DDR_REFRESH_ENABLE_GET(x) (((x) & DDR_REFRESH_ENABLE_MASK) >> DDR_REFRESH_ENABLE_LSB)
#define DDR_REFRESH_ENABLE_SET(x) (((x) << DDR_REFRESH_ENABLE_LSB) & DDR_REFRESH_ENABLE_MASK)
#define DDR_REFRESH_ENABLE_RESET 0x0 // 0
#define DDR_REFRESH_PERIOD_MSB 13
#define DDR_REFRESH_PERIOD_LSB 0
#define DDR_REFRESH_PERIOD_MASK 0x00003fff
#define DDR_REFRESH_PERIOD_GET(x) (((x) & DDR_REFRESH_PERIOD_MASK) >> DDR_REFRESH_PERIOD_LSB)
#define DDR_REFRESH_PERIOD_SET(x) (((x) << DDR_REFRESH_PERIOD_LSB) & DDR_REFRESH_PERIOD_MASK)
#define DDR_REFRESH_PERIOD_RESET 0x12c // 300
#define DDR_REFRESH_ADDRESS 0x18000014
#define BB_DPLL2_RANGE_MSB 31
#define BB_DPLL2_RANGE_LSB 31
#define BB_DPLL2_RANGE_MASK 0x80000000
#define BB_DPLL2_RANGE_GET(x) (((x) & BB_DPLL2_RANGE_MASK) >> BB_DPLL2_RANGE_LSB)
#define BB_DPLL2_RANGE_SET(x) (((x) << BB_DPLL2_RANGE_LSB) & BB_DPLL2_RANGE_MASK)
#define BB_DPLL2_RANGE_RESET 0x0 // 0
#define BB_DPLL2_LOCAL_PLL_MSB 30
#define BB_DPLL2_LOCAL_PLL_LSB 30
#define BB_DPLL2_LOCAL_PLL_MASK 0x40000000
#define BB_DPLL2_LOCAL_PLL_GET(x) (((x) & BB_DPLL2_LOCAL_PLL_MASK) >> BB_DPLL2_LOCAL_PLL_LSB)
#define BB_DPLL2_LOCAL_PLL_SET(x) (((x) << BB_DPLL2_LOCAL_PLL_LSB) & BB_DPLL2_LOCAL_PLL_MASK)
#define BB_DPLL2_LOCAL_PLL_RESET 0x0 // 0
#define BB_DPLL2_KI_MSB 29
#define BB_DPLL2_KI_LSB 26
#define BB_DPLL2_KI_MASK 0x3c000000
#define BB_DPLL2_KI_GET(x) (((x) & BB_DPLL2_KI_MASK) >> BB_DPLL2_KI_LSB)
#define BB_DPLL2_KI_SET(x) (((x) << BB_DPLL2_KI_LSB) & BB_DPLL2_KI_MASK)
#define BB_DPLL2_KI_RESET 0x6 // 6
#define BB_DPLL2_KD_MSB 25
#define BB_DPLL2_KD_LSB 19
#define BB_DPLL2_KD_MASK 0x03f80000
#define BB_DPLL2_KD_GET(x) (((x) & BB_DPLL2_KD_MASK) >> BB_DPLL2_KD_LSB)
#define BB_DPLL2_KD_SET(x) (((x) << BB_DPLL2_KD_LSB) & BB_DPLL2_KD_MASK)
#define BB_DPLL2_KD_RESET 0x7f // 127
#define BB_DPLL2_EN_NEGTRIG_MSB 18
#define BB_DPLL2_EN_NEGTRIG_LSB 18
#define BB_DPLL2_EN_NEGTRIG_MASK 0x00040000
#define BB_DPLL2_EN_NEGTRIG_GET(x) (((x) & BB_DPLL2_EN_NEGTRIG_MASK) >> BB_DPLL2_EN_NEGTRIG_LSB)
#define BB_DPLL2_EN_NEGTRIG_SET(x) (((x) << BB_DPLL2_EN_NEGTRIG_LSB) & BB_DPLL2_EN_NEGTRIG_MASK)
#define BB_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
#define BB_DPLL2_SEL_1SDM_MSB 17
#define BB_DPLL2_SEL_1SDM_LSB 17
#define BB_DPLL2_SEL_1SDM_MASK 0x00020000
#define BB_DPLL2_SEL_1SDM_GET(x) (((x) & BB_DPLL2_SEL_1SDM_MASK) >> BB_DPLL2_SEL_1SDM_LSB)
#define BB_DPLL2_SEL_1SDM_SET(x) (((x) << BB_DPLL2_SEL_1SDM_LSB) & BB_DPLL2_SEL_1SDM_MASK)
#define BB_DPLL2_SEL_1SDM_RESET 0x0 // 0
#define BB_DPLL2_PLL_PWD_MSB 16
#define BB_DPLL2_PLL_PWD_LSB 16
#define BB_DPLL2_PLL_PWD_MASK 0x00010000
#define BB_DPLL2_PLL_PWD_GET(x) (((x) & BB_DPLL2_PLL_PWD_MASK) >> BB_DPLL2_PLL_PWD_LSB)
#define BB_DPLL2_PLL_PWD_SET(x) (((x) << BB_DPLL2_PLL_PWD_LSB) & BB_DPLL2_PLL_PWD_MASK)
#define BB_DPLL2_PLL_PWD_RESET 0x1 // 1
#define BB_DPLL2_OUTDIV_MSB 15
#define BB_DPLL2_OUTDIV_LSB 13
#define BB_DPLL2_OUTDIV_MASK 0x0000e000
#define BB_DPLL2_OUTDIV_GET(x) (((x) & BB_DPLL2_OUTDIV_MASK) >> BB_DPLL2_OUTDIV_LSB)
#define BB_DPLL2_OUTDIV_SET(x) (((x) << BB_DPLL2_OUTDIV_LSB) & BB_DPLL2_OUTDIV_MASK)
#define BB_DPLL2_OUTDIV_RESET 0x0 // 0
#define BB_DPLL2_DELTA_MSB 12
#define BB_DPLL2_DELTA_LSB 7
#define BB_DPLL2_DELTA_MASK 0x00001f80
#define BB_DPLL2_DELTA_GET(x) (((x) & BB_DPLL2_DELTA_MASK) >> BB_DPLL2_DELTA_LSB)
#define BB_DPLL2_DELTA_SET(x) (((x) << BB_DPLL2_DELTA_LSB) & BB_DPLL2_DELTA_MASK)
#define BB_DPLL2_DELTA_RESET 0x1e // 30
#define BB_DPLL2_TESTINMSB_MSB 6
#define BB_DPLL2_TESTINMSB_LSB 0
#define BB_DPLL2_TESTINMSB_MASK 0x0000007f
#define BB_DPLL2_TESTINMSB_GET(x) (((x) & BB_DPLL2_TESTINMSB_MASK) >> BB_DPLL2_TESTINMSB_LSB)
#define BB_DPLL2_TESTINMSB_SET(x) (((x) << BB_DPLL2_TESTINMSB_LSB) & BB_DPLL2_TESTINMSB_MASK)
#define BB_DPLL2_TESTINMSB_RESET 0x0 // 0
#define BB_DPLL2_ADDRESS 0x18116184
#define PCIe_DPLL2_RANGE_MSB 31
#define PCIe_DPLL2_RANGE_LSB 31
#define PCIe_DPLL2_RANGE_MASK 0x80000000
#define PCIe_DPLL2_RANGE_GET(x) (((x) & PCIe_DPLL2_RANGE_MASK) >> PCIe_DPLL2_RANGE_LSB)
#define PCIe_DPLL2_RANGE_SET(x) (((x) << PCIe_DPLL2_RANGE_LSB) & PCIe_DPLL2_RANGE_MASK)
#define PCIe_DPLL2_RANGE_RESET 0x0 // 0
#define PCIe_DPLL2_LOCAL_PLL_MSB 30
#define PCIe_DPLL2_LOCAL_PLL_LSB 30
#define PCIe_DPLL2_LOCAL_PLL_MASK 0x40000000
#define PCIe_DPLL2_LOCAL_PLL_GET(x) (((x) & PCIe_DPLL2_LOCAL_PLL_MASK) >> PCIe_DPLL2_LOCAL_PLL_LSB)
#define PCIe_DPLL2_LOCAL_PLL_SET(x) (((x) << PCIe_DPLL2_LOCAL_PLL_LSB) & PCIe_DPLL2_LOCAL_PLL_MASK)
#define PCIe_DPLL2_LOCAL_PLL_RESET 0x0 // 0
#define PCIe_DPLL2_KI_MSB 29
#define PCIe_DPLL2_KI_LSB 26
#define PCIe_DPLL2_KI_MASK 0x3c000000
#define PCIe_DPLL2_KI_GET(x) (((x) & PCIe_DPLL2_KI_MASK) >> PCIe_DPLL2_KI_LSB)
#define PCIe_DPLL2_KI_SET(x) (((x) << PCIe_DPLL2_KI_LSB) & PCIe_DPLL2_KI_MASK)
#define PCIe_DPLL2_KI_RESET 0x6 // 6
#define PCIe_DPLL2_KD_MSB 25
#define PCIe_DPLL2_KD_LSB 19
#define PCIe_DPLL2_KD_MASK 0x03f80000
#define PCIe_DPLL2_KD_GET(x) (((x) & PCIe_DPLL2_KD_MASK) >> PCIe_DPLL2_KD_LSB)
#define PCIe_DPLL2_KD_SET(x) (((x) << PCIe_DPLL2_KD_LSB) & PCIe_DPLL2_KD_MASK)
#define PCIe_DPLL2_KD_RESET 0x7f // 127
#define PCIe_DPLL2_EN_NEGTRIG_MSB 18
#define PCIe_DPLL2_EN_NEGTRIG_LSB 18
#define PCIe_DPLL2_EN_NEGTRIG_MASK 0x00040000
#define PCIe_DPLL2_EN_NEGTRIG_GET(x) (((x) & PCIe_DPLL2_EN_NEGTRIG_MASK) >> PCIe_DPLL2_EN_NEGTRIG_LSB)
#define PCIe_DPLL2_EN_NEGTRIG_SET(x) (((x) << PCIe_DPLL2_EN_NEGTRIG_LSB) & PCIe_DPLL2_EN_NEGTRIG_MASK)
#define PCIe_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
#define PCIe_DPLL2_SEL_1SDM_MSB 17
#define PCIe_DPLL2_SEL_1SDM_LSB 17
#define PCIe_DPLL2_SEL_1SDM_MASK 0x00020000
#define PCIe_DPLL2_SEL_1SDM_GET(x) (((x) & PCIe_DPLL2_SEL_1SDM_MASK) >> PCIe_DPLL2_SEL_1SDM_LSB)
#define PCIe_DPLL2_SEL_1SDM_SET(x) (((x) << PCIe_DPLL2_SEL_1SDM_LSB) & PCIe_DPLL2_SEL_1SDM_MASK)
#define PCIe_DPLL2_SEL_1SDM_RESET 0x0 // 0
#define PCIe_DPLL2_PLL_PWD_MSB 16
#define PCIe_DPLL2_PLL_PWD_LSB 16
#define PCIe_DPLL2_PLL_PWD_MASK 0x00010000
#define PCIe_DPLL2_PLL_PWD_GET(x) (((x) & PCIe_DPLL2_PLL_PWD_MASK) >> PCIe_DPLL2_PLL_PWD_LSB)
#define PCIe_DPLL2_PLL_PWD_SET(x) (((x) << PCIe_DPLL2_PLL_PWD_LSB) & PCIe_DPLL2_PLL_PWD_MASK)
#define PCIe_DPLL2_PLL_PWD_RESET 0x1 // 1
#define PCIe_DPLL2_OUTDIV_MSB 15
#define PCIe_DPLL2_OUTDIV_LSB 13
#define PCIe_DPLL2_OUTDIV_MASK 0x0000e000
#define PCIe_DPLL2_OUTDIV_GET(x) (((x) & PCIe_DPLL2_OUTDIV_MASK) >> PCIe_DPLL2_OUTDIV_LSB)
#define PCIe_DPLL2_OUTDIV_SET(x) (((x) << PCIe_DPLL2_OUTDIV_LSB) & PCIe_DPLL2_OUTDIV_MASK)
#define PCIe_DPLL2_OUTDIV_RESET 0x0 // 0
#define PCIe_DPLL2_DELTA_MSB 12
#define PCIe_DPLL2_DELTA_LSB 7
#define PCIe_DPLL2_DELTA_MASK 0x00001f80
#define PCIe_DPLL2_DELTA_GET(x) (((x) & PCIe_DPLL2_DELTA_MASK) >> PCIe_DPLL2_DELTA_LSB)
#define PCIe_DPLL2_DELTA_SET(x) (((x) << PCIe_DPLL2_DELTA_LSB) & PCIe_DPLL2_DELTA_MASK)
#define PCIe_DPLL2_DELTA_RESET 0x1e // 30
#define PCIe_DPLL2_TESTINMSB_MSB 6
#define PCIe_DPLL2_TESTINMSB_LSB 0
#define PCIe_DPLL2_TESTINMSB_MASK 0x0000007f
#define PCIe_DPLL2_TESTINMSB_GET(x) (((x) & PCIe_DPLL2_TESTINMSB_MASK) >> PCIe_DPLL2_TESTINMSB_LSB)
#define PCIe_DPLL2_TESTINMSB_SET(x) (((x) << PCIe_DPLL2_TESTINMSB_LSB) & PCIe_DPLL2_TESTINMSB_MASK)
#define PCIe_DPLL2_TESTINMSB_RESET 0x0 // 0
#define PCIe_DPLL2_ADDRESS 0x18116c84
#define DDR_DPLL2_RANGE_MSB 31
#define DDR_DPLL2_RANGE_LSB 31
#define DDR_DPLL2_RANGE_MASK 0x80000000
#define DDR_DPLL2_RANGE_GET(x) (((x) & DDR_DPLL2_RANGE_MASK) >> DDR_DPLL2_RANGE_LSB)
#define DDR_DPLL2_RANGE_SET(x) (((x) << DDR_DPLL2_RANGE_LSB) & DDR_DPLL2_RANGE_MASK)
#define DDR_DPLL2_RANGE_RESET 0x0 // 0
#define DDR_DPLL2_LOCAL_PLL_MSB 30
#define DDR_DPLL2_LOCAL_PLL_LSB 30
#define DDR_DPLL2_LOCAL_PLL_MASK 0x40000000
#define DDR_DPLL2_LOCAL_PLL_GET(x) (((x) & DDR_DPLL2_LOCAL_PLL_MASK) >> DDR_DPLL2_LOCAL_PLL_LSB)
#define DDR_DPLL2_LOCAL_PLL_SET(x) (((x) << DDR_DPLL2_LOCAL_PLL_LSB) & DDR_DPLL2_LOCAL_PLL_MASK)
#define DDR_DPLL2_LOCAL_PLL_RESET 0x0 // 0
#define DDR_DPLL2_KI_MSB 29
#define DDR_DPLL2_KI_LSB 26
#define DDR_DPLL2_KI_MASK 0x3c000000
#define DDR_DPLL2_KI_GET(x) (((x) & DDR_DPLL2_KI_MASK) >> DDR_DPLL2_KI_LSB)
#define DDR_DPLL2_KI_SET(x) (((x) << DDR_DPLL2_KI_LSB) & DDR_DPLL2_KI_MASK)
#define DDR_DPLL2_KI_RESET 0x6 // 6
#define DDR_DPLL2_KD_MSB 25
#define DDR_DPLL2_KD_LSB 19
#define DDR_DPLL2_KD_MASK 0x03f80000
#define DDR_DPLL2_KD_GET(x) (((x) & DDR_DPLL2_KD_MASK) >> DDR_DPLL2_KD_LSB)
#define DDR_DPLL2_KD_SET(x) (((x) << DDR_DPLL2_KD_LSB) & DDR_DPLL2_KD_MASK)
#define DDR_DPLL2_KD_RESET 0x7f // 127
#define DDR_DPLL2_EN_NEGTRIG_MSB 18
#define DDR_DPLL2_EN_NEGTRIG_LSB 18
#define DDR_DPLL2_EN_NEGTRIG_MASK 0x00040000
#define DDR_DPLL2_EN_NEGTRIG_GET(x) (((x) & DDR_DPLL2_EN_NEGTRIG_MASK) >> DDR_DPLL2_EN_NEGTRIG_LSB)
#define DDR_DPLL2_EN_NEGTRIG_SET(x) (((x) << DDR_DPLL2_EN_NEGTRIG_LSB) & DDR_DPLL2_EN_NEGTRIG_MASK)
#define DDR_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
#define DDR_DPLL2_SEL_1SDM_MSB 17
#define DDR_DPLL2_SEL_1SDM_LSB 17
#define DDR_DPLL2_SEL_1SDM_MASK 0x00020000
#define DDR_DPLL2_SEL_1SDM_GET(x) (((x) & DDR_DPLL2_SEL_1SDM_MASK) >> DDR_DPLL2_SEL_1SDM_LSB)
#define DDR_DPLL2_SEL_1SDM_SET(x) (((x) << DDR_DPLL2_SEL_1SDM_LSB) & DDR_DPLL2_SEL_1SDM_MASK)
#define DDR_DPLL2_SEL_1SDM_RESET 0x0 // 0
#define DDR_DPLL2_PLL_PWD_MSB 16
#define DDR_DPLL2_PLL_PWD_LSB 16
#define DDR_DPLL2_PLL_PWD_MASK 0x00010000
#define DDR_DPLL2_PLL_PWD_GET(x) (((x) & DDR_DPLL2_PLL_PWD_MASK) >> DDR_DPLL2_PLL_PWD_LSB)
#define DDR_DPLL2_PLL_PWD_SET(x) (((x) << DDR_DPLL2_PLL_PWD_LSB) & DDR_DPLL2_PLL_PWD_MASK)
#define DDR_DPLL2_PLL_PWD_RESET 0x1 // 1
#define DDR_DPLL2_OUTDIV_MSB 15
#define DDR_DPLL2_OUTDIV_LSB 13
#define DDR_DPLL2_OUTDIV_MASK 0x0000e000
#define DDR_DPLL2_OUTDIV_GET(x) (((x) & DDR_DPLL2_OUTDIV_MASK) >> DDR_DPLL2_OUTDIV_LSB)
#define DDR_DPLL2_OUTDIV_SET(x) (((x) << DDR_DPLL2_OUTDIV_LSB) & DDR_DPLL2_OUTDIV_MASK)
#define DDR_DPLL2_OUTDIV_RESET 0x0 // 0
#define DDR_DPLL2_DELTA_MSB 12
#define DDR_DPLL2_DELTA_LSB 7
#define DDR_DPLL2_DELTA_MASK 0x00001f80
#define DDR_DPLL2_DELTA_GET(x) (((x) & DDR_DPLL2_DELTA_MASK) >> DDR_DPLL2_DELTA_LSB)
#define DDR_DPLL2_DELTA_SET(x) (((x) << DDR_DPLL2_DELTA_LSB) & DDR_DPLL2_DELTA_MASK)
#define DDR_DPLL2_DELTA_RESET 0x1e // 30
#define DDR_DPLL2_TESTINMSB_MSB 6
#define DDR_DPLL2_TESTINMSB_LSB 0
#define DDR_DPLL2_TESTINMSB_MASK 0x0000007f
#define DDR_DPLL2_TESTINMSB_GET(x) (((x) & DDR_DPLL2_TESTINMSB_MASK) >> DDR_DPLL2_TESTINMSB_LSB)
#define DDR_DPLL2_TESTINMSB_SET(x) (((x) << DDR_DPLL2_TESTINMSB_LSB) & DDR_DPLL2_TESTINMSB_MASK)
#define DDR_DPLL2_TESTINMSB_RESET 0x0 // 0
#define DDR_DPLL2_ADDRESS 0x18116ec4
#define CPU_DPLL2_RANGE_MSB 31
#define CPU_DPLL2_RANGE_LSB 31
#define CPU_DPLL2_RANGE_MASK 0x80000000
#define CPU_DPLL2_RANGE_GET(x) (((x) & CPU_DPLL2_RANGE_MASK) >> CPU_DPLL2_RANGE_LSB)
#define CPU_DPLL2_RANGE_SET(x) (((x) << CPU_DPLL2_RANGE_LSB) & CPU_DPLL2_RANGE_MASK)
#define CPU_DPLL2_RANGE_RESET 0x0 // 0
#define CPU_DPLL2_LOCAL_PLL_MSB 30
#define CPU_DPLL2_LOCAL_PLL_LSB 30
#define CPU_DPLL2_LOCAL_PLL_MASK 0x40000000
#define CPU_DPLL2_LOCAL_PLL_GET(x) (((x) & CPU_DPLL2_LOCAL_PLL_MASK) >> CPU_DPLL2_LOCAL_PLL_LSB)
#define CPU_DPLL2_LOCAL_PLL_SET(x) (((x) << CPU_DPLL2_LOCAL_PLL_LSB) & CPU_DPLL2_LOCAL_PLL_MASK)
#define CPU_DPLL2_LOCAL_PLL_RESET 0x0 // 0
#define CPU_DPLL2_KI_MSB 29
#define CPU_DPLL2_KI_LSB 26
#define CPU_DPLL2_KI_MASK 0x3c000000
#define CPU_DPLL2_KI_GET(x) (((x) & CPU_DPLL2_KI_MASK) >> CPU_DPLL2_KI_LSB)
#define CPU_DPLL2_KI_SET(x) (((x) << CPU_DPLL2_KI_LSB) & CPU_DPLL2_KI_MASK)
#define CPU_DPLL2_KI_RESET 0x6 // 6
#define CPU_DPLL2_KD_MSB 25
#define CPU_DPLL2_KD_LSB 19
#define CPU_DPLL2_KD_MASK 0x03f80000
#define CPU_DPLL2_KD_GET(x) (((x) & CPU_DPLL2_KD_MASK) >> CPU_DPLL2_KD_LSB)
#define CPU_DPLL2_KD_SET(x) (((x) << CPU_DPLL2_KD_LSB) & CPU_DPLL2_KD_MASK)
#define CPU_DPLL2_KD_RESET 0x7f // 127
#define CPU_DPLL2_EN_NEGTRIG_MSB 18
#define CPU_DPLL2_EN_NEGTRIG_LSB 18
#define CPU_DPLL2_EN_NEGTRIG_MASK 0x00040000
#define CPU_DPLL2_EN_NEGTRIG_GET(x) (((x) & CPU_DPLL2_EN_NEGTRIG_MASK) >> CPU_DPLL2_EN_NEGTRIG_LSB)
#define CPU_DPLL2_EN_NEGTRIG_SET(x) (((x) << CPU_DPLL2_EN_NEGTRIG_LSB) & CPU_DPLL2_EN_NEGTRIG_MASK)
#define CPU_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
#define CPU_DPLL2_SEL_1SDM_MSB 17
#define CPU_DPLL2_SEL_1SDM_LSB 17
#define CPU_DPLL2_SEL_1SDM_MASK 0x00020000
#define CPU_DPLL2_SEL_1SDM_GET(x) (((x) & CPU_DPLL2_SEL_1SDM_MASK) >> CPU_DPLL2_SEL_1SDM_LSB)
#define CPU_DPLL2_SEL_1SDM_SET(x) (((x) << CPU_DPLL2_SEL_1SDM_LSB) & CPU_DPLL2_SEL_1SDM_MASK)
#define CPU_DPLL2_SEL_1SDM_RESET 0x0 // 0
#define CPU_DPLL2_PLL_PWD_MSB 16
#define CPU_DPLL2_PLL_PWD_LSB 16
#define CPU_DPLL2_PLL_PWD_MASK 0x00010000
#define CPU_DPLL2_PLL_PWD_GET(x) (((x) & CPU_DPLL2_PLL_PWD_MASK) >> CPU_DPLL2_PLL_PWD_LSB)
#define CPU_DPLL2_PLL_PWD_SET(x) (((x) << CPU_DPLL2_PLL_PWD_LSB) & CPU_DPLL2_PLL_PWD_MASK)
#define CPU_DPLL2_PLL_PWD_RESET 0x1 // 1
#define CPU_DPLL2_OUTDIV_MSB 15
#define CPU_DPLL2_OUTDIV_LSB 13
#define CPU_DPLL2_OUTDIV_MASK 0x0000e000
#define CPU_DPLL2_OUTDIV_GET(x) (((x) & CPU_DPLL2_OUTDIV_MASK) >> CPU_DPLL2_OUTDIV_LSB)
#define CPU_DPLL2_OUTDIV_SET(x) (((x) << CPU_DPLL2_OUTDIV_LSB) & CPU_DPLL2_OUTDIV_MASK)
#define CPU_DPLL2_OUTDIV_RESET 0x0 // 0
#define CPU_DPLL2_DELTA_MSB 12
#define CPU_DPLL2_DELTA_LSB 7
#define CPU_DPLL2_DELTA_MASK 0x00001f80
#define CPU_DPLL2_DELTA_GET(x) (((x) & CPU_DPLL2_DELTA_MASK) >> CPU_DPLL2_DELTA_LSB)
#define CPU_DPLL2_DELTA_SET(x) (((x) << CPU_DPLL2_DELTA_LSB) & CPU_DPLL2_DELTA_MASK)
#define CPU_DPLL2_DELTA_RESET 0x1e // 30
#define CPU_DPLL2_TESTINMSB_MSB 6
#define CPU_DPLL2_TESTINMSB_LSB 0
#define CPU_DPLL2_TESTINMSB_MASK 0x0000007f
#define CPU_DPLL2_TESTINMSB_GET(x) (((x) & CPU_DPLL2_TESTINMSB_MASK) >> CPU_DPLL2_TESTINMSB_LSB)
#define CPU_DPLL2_TESTINMSB_SET(x) (((x) << CPU_DPLL2_TESTINMSB_LSB) & CPU_DPLL2_TESTINMSB_MASK)
#define CPU_DPLL2_TESTINMSB_RESET 0x0 // 0
#define CPU_DPLL2_ADDRESS 0x18116f04
#define DDR_RD_DATA_THIS_CYCLE_ADDRESS 0x18000018
#define TAP_CONTROL_0_ADDRESS 0x1800001c
#define TAP_CONTROL_1_ADDRESS 0x18000020
#define TAP_CONTROL_2_ADDRESS 0x18000024
#define TAP_CONTROL_3_ADDRESS 0x18000028
#define DDR_BURST_ADDRESS 0x180000c4
#define DDR_BURST2_ADDRESS 0x180000c8
#define DDR_AHB_MASTER_TIMEOUT_MAX_ADDRESS 0x180000cc
#define PMU1_ADDRESS 0x18116cc0
#define PMU2_SWREGMSB_MSB 31
#define PMU2_SWREGMSB_LSB 22
#define PMU2_SWREGMSB_MASK 0xffc00000
#define PMU2_SWREGMSB_GET(x) (((x) & PMU2_SWREGMSB_MASK) >> PMU2_SWREGMSB_LSB)
#define PMU2_SWREGMSB_SET(x) (((x) << PMU2_SWREGMSB_LSB) & PMU2_SWREGMSB_MASK)
#define PMU2_SWREGMSB_RESET 0x0 // 0
#define PMU2_PGM_MSB 21
#define PMU2_PGM_LSB 21
#define PMU2_PGM_MASK 0x00200000
#define PMU2_PGM_GET(x) (((x) & PMU2_PGM_MASK) >> PMU2_PGM_LSB)
#define PMU2_PGM_SET(x) (((x) << PMU2_PGM_LSB) & PMU2_PGM_MASK)
#define PMU2_PGM_RESET 0x0 // 0
#define PMU2_LDO_TUNE_MSB 20
#define PMU2_LDO_TUNE_LSB 19
#define PMU2_LDO_TUNE_MASK 0x00180000
#define PMU2_LDO_TUNE_GET(x) (((x) & PMU2_LDO_TUNE_MASK) >> PMU2_LDO_TUNE_LSB)
#define PMU2_LDO_TUNE_SET(x) (((x) << PMU2_LDO_TUNE_LSB) & PMU2_LDO_TUNE_MASK)
#define PMU2_LDO_TUNE_RESET 0x0 // 0
#define PMU2_PWDLDO_DDR_MSB 18
#define PMU2_PWDLDO_DDR_LSB 18
#define PMU2_PWDLDO_DDR_MASK 0x00040000
#define PMU2_PWDLDO_DDR_GET(x) (((x) & PMU2_PWDLDO_DDR_MASK) >> PMU2_PWDLDO_DDR_LSB)
#define PMU2_PWDLDO_DDR_SET(x) (((x) << PMU2_PWDLDO_DDR_LSB) & PMU2_PWDLDO_DDR_MASK)
#define PMU2_PWDLDO_DDR_RESET 0x0 // 0
#define PMU2_LPOPWD_MSB 17
#define PMU2_LPOPWD_LSB 17
#define PMU2_LPOPWD_MASK 0x00020000
#define PMU2_LPOPWD_GET(x) (((x) & PMU2_LPOPWD_MASK) >> PMU2_LPOPWD_LSB)
#define PMU2_LPOPWD_SET(x) (((x) << PMU2_LPOPWD_LSB) & PMU2_LPOPWD_MASK)
#define PMU2_LPOPWD_RESET 0x0 // 0
#define PMU2_SPARE_MSB 16
#define PMU2_SPARE_LSB 0
#define PMU2_SPARE_MASK 0x0001ffff
#define PMU2_SPARE_GET(x) (((x) & PMU2_SPARE_MASK) >> PMU2_SPARE_LSB)
#define PMU2_SPARE_SET(x) (((x) << PMU2_SPARE_LSB) & PMU2_SPARE_MASK)
#define PMU2_SPARE_RESET 0x0 // 0
#define PMU2_ADDRESS 0x18116cc4
#define CPU_DDR_CLOCK_CONTROL_SPARE_MSB 31
#define CPU_DDR_CLOCK_CONTROL_SPARE_LSB 25
#define CPU_DDR_CLOCK_CONTROL_SPARE_MASK 0xfe000000
#define CPU_DDR_CLOCK_CONTROL_SPARE_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) >> CPU_DDR_CLOCK_CONTROL_SPARE_LSB)
#define CPU_DDR_CLOCK_CONTROL_SPARE_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_SPARE_LSB) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK)
#define CPU_DDR_CLOCK_CONTROL_SPARE_RESET 0
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MSB 24
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB)
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK)
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_RESET 1
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MSB 23
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB 23
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK 0x00800000
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_RESET 0
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MSB 22
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB 22
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK 0x00400000
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_RESET 0x0
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MSB 21
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB 21
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK 0x00200000
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_RESET 0x0
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MSB 20
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB 20
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK 0x00100000
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_RESET 0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MSB 19
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB)
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK)
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_RESET 0
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MSB 14
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB)
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_RESET 0
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MSB 9
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_RESET 0
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MSB 4
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB)
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_RESET 1
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MSB 3
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB)
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_RESET 1
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MSB 2
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_RESET 1
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MSB 1
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB 1
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK 0x00000002
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB)
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK)
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_RESET 0
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MSB 0
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB 0
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK 0x00000001
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB)
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK)
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_RESET 0
#define CPU_DDR_CLOCK_CONTROL_ADDRESS 0x18050008
#define PCIE_PLL_CONFIG_UPDATING_MSB 31
#define PCIE_PLL_CONFIG_UPDATING_LSB 31
#define PCIE_PLL_CONFIG_UPDATING_MASK 0x80000000
#define PCIE_PLL_CONFIG_UPDATING_GET(x) (((x) & PCIE_PLL_CONFIG_UPDATING_MASK) >> PCIE_PLL_CONFIG_UPDATING_LSB)
#define PCIE_PLL_CONFIG_UPDATING_SET(x) (((x) << PCIE_PLL_CONFIG_UPDATING_LSB) & PCIE_PLL_CONFIG_UPDATING_MASK)
#define PCIE_PLL_CONFIG_UPDATING_RESET 0x0 // 0
#define PCIE_PLL_CONFIG_PLLPWD_MSB 30
#define PCIE_PLL_CONFIG_PLLPWD_LSB 30
#define PCIE_PLL_CONFIG_PLLPWD_MASK 0x40000000
#define PCIE_PLL_CONFIG_PLLPWD_GET(x) (((x) & PCIE_PLL_CONFIG_PLLPWD_MASK) >> PCIE_PLL_CONFIG_PLLPWD_LSB)
#define PCIE_PLL_CONFIG_PLLPWD_SET(x) (((x) << PCIE_PLL_CONFIG_PLLPWD_LSB) & PCIE_PLL_CONFIG_PLLPWD_MASK)
#define PCIE_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
#define PCIE_PLL_CONFIG_BYPASS_MSB 16
#define PCIE_PLL_CONFIG_BYPASS_LSB 16
#define PCIE_PLL_CONFIG_BYPASS_MASK 0x00010000
#define PCIE_PLL_CONFIG_BYPASS_GET(x) (((x) & PCIE_PLL_CONFIG_BYPASS_MASK) >> PCIE_PLL_CONFIG_BYPASS_LSB)
#define PCIE_PLL_CONFIG_BYPASS_SET(x) (((x) << PCIE_PLL_CONFIG_BYPASS_LSB) & PCIE_PLL_CONFIG_BYPASS_MASK)
#define PCIE_PLL_CONFIG_BYPASS_RESET 0x1 // 1
#define PCIE_PLL_CONFIG_REFDIV_MSB 14
#define PCIE_PLL_CONFIG_REFDIV_LSB 10
#define PCIE_PLL_CONFIG_REFDIV_MASK 0x00007c00
#define PCIE_PLL_CONFIG_REFDIV_GET(x) (((x) & PCIE_PLL_CONFIG_REFDIV_MASK) >> PCIE_PLL_CONFIG_REFDIV_LSB)
#define PCIE_PLL_CONFIG_REFDIV_SET(x) (((x) << PCIE_PLL_CONFIG_REFDIV_LSB) & PCIE_PLL_CONFIG_REFDIV_MASK)
#define PCIE_PLL_CONFIG_REFDIV_RESET 0x1 // 1
#define PCIE_PLL_CONFIG_ADDRESS 0x1805000c
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MSB 31
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB 31
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK 0x80000000
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) >> PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB)
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK)
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_RESET 0x1 // 1
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MSB 30
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB 30
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK 0x40000000
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) >> PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB)
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK)
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_RESET 0x1 // 1
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MSB 20
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB 15
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK 0x001f8000
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB)
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK)
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_RESET 0x13 // 19
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MSB 14
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB 1
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK 0x00007ffe
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB)
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK)
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_RESET 0x3fff // 16383
#define PCIE_PLL_DITHER_DIV_MAX_ADDRESS 0x18050010
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MSB 20
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB 15
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK 0x001f8000
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB)
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK)
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_RESET 0x13 // 19
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MSB 14
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB 1
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK 0x00007ffe
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB)
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK)
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_RESET 0x399d // 14749
#define PCIE_PLL_DITHER_DIV_MIN_ADDRESS 0x18050014
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MSB 31
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB 28
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK 0xf0000000
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) >> PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB)
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK)
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_RESET 0x0 // 0
#define PCIE_PLL_DITHER_STEP_STEP_INT_MSB 24
#define PCIE_PLL_DITHER_STEP_STEP_INT_LSB 15
#define PCIE_PLL_DITHER_STEP_STEP_INT_MASK 0x01ff8000
#define PCIE_PLL_DITHER_STEP_STEP_INT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) >> PCIE_PLL_DITHER_STEP_STEP_INT_LSB)
#define PCIE_PLL_DITHER_STEP_STEP_INT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_INT_LSB) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK)
#define PCIE_PLL_DITHER_STEP_STEP_INT_RESET 0x0 // 0
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MSB 14
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB 1
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK 0x00007ffe
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) >> PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB)
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK)
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_RESET 0xa // 10
#define PCIE_PLL_DITHER_STEP_ADDRESS 0x18050018
#define LDO_POWER_CONTROL_PKG_SEL_MSB 5
#define LDO_POWER_CONTROL_PKG_SEL_LSB 5
#define LDO_POWER_CONTROL_PKG_SEL_MASK 0x00000020
#define LDO_POWER_CONTROL_PKG_SEL_GET(x) (((x) & LDO_POWER_CONTROL_PKG_SEL_MASK) >> LDO_POWER_CONTROL_PKG_SEL_LSB)
#define LDO_POWER_CONTROL_PKG_SEL_SET(x) (((x) << LDO_POWER_CONTROL_PKG_SEL_LSB) & LDO_POWER_CONTROL_PKG_SEL_MASK)
#define LDO_POWER_CONTROL_PKG_SEL_RESET 0x0 // 0
#define LDO_POWER_CONTROL_PWDLDO_CPU_MSB 4
#define LDO_POWER_CONTROL_PWDLDO_CPU_LSB 4
#define LDO_POWER_CONTROL_PWDLDO_CPU_MASK 0x00000010
#define LDO_POWER_CONTROL_PWDLDO_CPU_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) >> LDO_POWER_CONTROL_PWDLDO_CPU_LSB)
#define LDO_POWER_CONTROL_PWDLDO_CPU_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_CPU_LSB) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK)
#define LDO_POWER_CONTROL_PWDLDO_CPU_RESET 0x0 // 0
#define LDO_POWER_CONTROL_PWDLDO_DDR_MSB 3
#define LDO_POWER_CONTROL_PWDLDO_DDR_LSB 3
#define LDO_POWER_CONTROL_PWDLDO_DDR_MASK 0x00000008
#define LDO_POWER_CONTROL_PWDLDO_DDR_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) >> LDO_POWER_CONTROL_PWDLDO_DDR_LSB)
#define LDO_POWER_CONTROL_PWDLDO_DDR_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_DDR_LSB) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK)
#define LDO_POWER_CONTROL_PWDLDO_DDR_RESET 0x0 // 0
#define LDO_POWER_CONTROL_CPU_REFSEL_MSB 2
#define LDO_POWER_CONTROL_CPU_REFSEL_LSB 1
#define LDO_POWER_CONTROL_CPU_REFSEL_MASK 0x00000006
#define LDO_POWER_CONTROL_CPU_REFSEL_GET(x) (((x) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) >> LDO_POWER_CONTROL_CPU_REFSEL_LSB)
#define LDO_POWER_CONTROL_CPU_REFSEL_SET(x) (((x) << LDO_POWER_CONTROL_CPU_REFSEL_LSB) & LDO_POWER_CONTROL_CPU_REFSEL_MASK)
#define LDO_POWER_CONTROL_CPU_REFSEL_RESET 0x3 // 3
#define LDO_POWER_CONTROL_SELECT_DDR1_MSB 0
#define LDO_POWER_CONTROL_SELECT_DDR1_LSB 0
#define LDO_POWER_CONTROL_SELECT_DDR1_MASK 0x00000001
#define LDO_POWER_CONTROL_SELECT_DDR1_GET(x) (((x) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) >> LDO_POWER_CONTROL_SELECT_DDR1_LSB)
#define LDO_POWER_CONTROL_SELECT_DDR1_SET(x) (((x) << LDO_POWER_CONTROL_SELECT_DDR1_LSB) & LDO_POWER_CONTROL_SELECT_DDR1_MASK)
#define LDO_POWER_CONTROL_SELECT_DDR1_RESET 0x0 // 0
#define LDO_POWER_CONTROL_ADDRESS 0x1805001c
#define SWITCH_CLOCK_SPARE_SPARE_MSB 31
#define SWITCH_CLOCK_SPARE_SPARE_LSB 16
#define SWITCH_CLOCK_SPARE_SPARE_MASK 0xffff0000
#define SWITCH_CLOCK_SPARE_SPARE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_MASK) >> SWITCH_CLOCK_SPARE_SPARE_LSB)
#define SWITCH_CLOCK_SPARE_SPARE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_LSB) & SWITCH_CLOCK_SPARE_SPARE_MASK)
#define SWITCH_CLOCK_SPARE_SPARE_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MSB 15
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_LSB 15
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MASK 0x00008000
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_LSB)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MASK)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MSB 14
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_LSB 14
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MASK 0x00004000
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_LSB)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MASK)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MSB 13
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_LSB 13
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MASK 0x00002000
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_LSB)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MASK)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_MSB 12
#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_LSB 12
#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_MASK 0x00001000
#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_LSB)
#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_MASK)
#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MSB 11
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB 8
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0x00000f00
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) >> SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB)
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK)
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_RESET 0x5 // 5
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MSB 7
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB 7
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK 0x00000080
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB)
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK)
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MSB 6
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_LSB 6
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MASK 0x00000040
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_LSB)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MASK)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MSB 5
#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_LSB 5
#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MASK 0x00000020
#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_I2C_CLK_SEL_LSB)
#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_I2C_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MASK)
#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_SPARE_0_MSB 4
#define SWITCH_CLOCK_SPARE_SPARE_0_LSB 0
#define SWITCH_CLOCK_SPARE_SPARE_0_MASK 0x0000001f
#define SWITCH_CLOCK_SPARE_SPARE_0_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_0_MASK) >> SWITCH_CLOCK_SPARE_SPARE_0_LSB)
#define SWITCH_CLOCK_SPARE_SPARE_0_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_0_LSB) & SWITCH_CLOCK_SPARE_SPARE_0_MASK)
#define SWITCH_CLOCK_SPARE_SPARE_0_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_ADDRESS 0x18050020
#define CURRENT_PCIE_PLL_DITHER_INT_MSB 20
#define CURRENT_PCIE_PLL_DITHER_INT_LSB 15
#define CURRENT_PCIE_PLL_DITHER_INT_MASK 0x001f8000
#define CURRENT_PCIE_PLL_DITHER_INT_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_INT_MASK) >> CURRENT_PCIE_PLL_DITHER_INT_LSB)
#define CURRENT_PCIE_PLL_DITHER_INT_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_INT_LSB) & CURRENT_PCIE_PLL_DITHER_INT_MASK)
#define CURRENT_PCIE_PLL_DITHER_INT_RESET 0x1 // 1
#define CURRENT_PCIE_PLL_DITHER_FRAC_MSB 13
#define CURRENT_PCIE_PLL_DITHER_FRAC_LSB 0
#define CURRENT_PCIE_PLL_DITHER_FRAC_MASK 0x00003fff
#define CURRENT_PCIE_PLL_DITHER_FRAC_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) >> CURRENT_PCIE_PLL_DITHER_FRAC_LSB)
#define CURRENT_PCIE_PLL_DITHER_FRAC_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_FRAC_LSB) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK)
#define CURRENT_PCIE_PLL_DITHER_FRAC_RESET 0x0 // 0
#define CURRENT_PCIE_PLL_DITHER_ADDRESS 0x18050024
#define ETH_XMII_TX_INVERT_MSB 31
#define ETH_XMII_TX_INVERT_LSB 31
#define ETH_XMII_TX_INVERT_MASK 0x80000000
#define ETH_XMII_TX_INVERT_GET(x) (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB)
#define ETH_XMII_TX_INVERT_SET(x) (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK)
#define ETH_XMII_TX_INVERT_RESET 0x0 // 0
#define ETH_XMII_GIGE_QUAD_MSB 30
#define ETH_XMII_GIGE_QUAD_LSB 30
#define ETH_XMII_GIGE_QUAD_MASK 0x40000000
#define ETH_XMII_GIGE_QUAD_GET(x) (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB)
#define ETH_XMII_GIGE_QUAD_SET(x) (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK)
#define ETH_XMII_GIGE_QUAD_RESET 0x0 // 0
#define ETH_XMII_RX_DELAY_MSB 29
#define ETH_XMII_RX_DELAY_LSB 28
#define ETH_XMII_RX_DELAY_MASK 0x30000000
#define ETH_XMII_RX_DELAY_GET(x) (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB)
#define ETH_XMII_RX_DELAY_SET(x) (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK)
#define ETH_XMII_RX_DELAY_RESET 0x0 // 0
#define ETH_XMII_TX_DELAY_MSB 27
#define ETH_XMII_TX_DELAY_LSB 26
#define ETH_XMII_TX_DELAY_MASK 0x0c000000
#define ETH_XMII_TX_DELAY_GET(x) (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB)
#define ETH_XMII_TX_DELAY_SET(x) (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK)
#define ETH_XMII_TX_DELAY_RESET 0x0 // 0
#define ETH_XMII_GIGE_MSB 25
#define ETH_XMII_GIGE_LSB 25
#define ETH_XMII_GIGE_MASK 0x02000000
#define ETH_XMII_GIGE_GET(x) (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB)
#define ETH_XMII_GIGE_SET(x) (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK)
#define ETH_XMII_GIGE_RESET 0x0 // 0
#define ETH_XMII_OFFSET_PHASE_MSB 24
#define ETH_XMII_OFFSET_PHASE_LSB 24
#define ETH_XMII_OFFSET_PHASE_MASK 0x01000000
#define ETH_XMII_OFFSET_PHASE_GET(x) (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB)
#define ETH_XMII_OFFSET_PHASE_SET(x) (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK)
#define ETH_XMII_OFFSET_PHASE_RESET 0x0 // 0
#define ETH_XMII_OFFSET_COUNT_MSB 23
#define ETH_XMII_OFFSET_COUNT_LSB 16
#define ETH_XMII_OFFSET_COUNT_MASK 0x00ff0000
#define ETH_XMII_OFFSET_COUNT_GET(x) (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB)
#define ETH_XMII_OFFSET_COUNT_SET(x) (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK)
#define ETH_XMII_OFFSET_COUNT_RESET 0x0 // 0
#define ETH_XMII_PHASE1_COUNT_MSB 15
#define ETH_XMII_PHASE1_COUNT_LSB 8
#define ETH_XMII_PHASE1_COUNT_MASK 0x0000ff00
#define ETH_XMII_PHASE1_COUNT_GET(x) (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB)
#define ETH_XMII_PHASE1_COUNT_SET(x) (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK)
#define ETH_XMII_PHASE1_COUNT_RESET 0x1 // 1
#define ETH_XMII_PHASE0_COUNT_MSB 7
#define ETH_XMII_PHASE0_COUNT_LSB 0
#define ETH_XMII_PHASE0_COUNT_MASK 0x000000ff
#define ETH_XMII_PHASE0_COUNT_GET(x) (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB)
#define ETH_XMII_PHASE0_COUNT_SET(x) (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK)
#define ETH_XMII_PHASE0_COUNT_RESET 0x1 // 1
#define ETH_XMII_ADDRESS 0x18050028
#define AUDIO_PLL_CONFIG_UPDATING_MSB 31
#define AUDIO_PLL_CONFIG_UPDATING_LSB 31
#define AUDIO_PLL_CONFIG_UPDATING_MASK 0x80000000
#define AUDIO_PLL_CONFIG_UPDATING_GET(x) (((x) & AUDIO_PLL_CONFIG_UPDATING_MASK) >> AUDIO_PLL_CONFIG_UPDATING_LSB)
#define AUDIO_PLL_CONFIG_UPDATING_SET(x) (((x) << AUDIO_PLL_CONFIG_UPDATING_LSB) & AUDIO_PLL_CONFIG_UPDATING_MASK)
#define AUDIO_PLL_CONFIG_UPDATING_RESET 0x1 // 1
#define AUDIO_PLL_CONFIG_EXT_DIV_MSB 14
#define AUDIO_PLL_CONFIG_EXT_DIV_LSB 12
#define AUDIO_PLL_CONFIG_EXT_DIV_MASK 0x00007000
#define AUDIO_PLL_CONFIG_EXT_DIV_GET(x) (((x) & AUDIO_PLL_CONFIG_EXT_DIV_MASK) >> AUDIO_PLL_CONFIG_EXT_DIV_LSB)
#define AUDIO_PLL_CONFIG_EXT_DIV_SET(x) (((x) << AUDIO_PLL_CONFIG_EXT_DIV_LSB) & AUDIO_PLL_CONFIG_EXT_DIV_MASK)
#define AUDIO_PLL_CONFIG_EXT_DIV_RESET 0x1 // 1
#define AUDIO_PLL_CONFIG_POSTPLLDIV_MSB 9
#define AUDIO_PLL_CONFIG_POSTPLLDIV_LSB 7
#define AUDIO_PLL_CONFIG_POSTPLLDIV_MASK 0x00000380
#define AUDIO_PLL_CONFIG_POSTPLLDIV_GET(x) (((x) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK) >> AUDIO_PLL_CONFIG_POSTPLLDIV_LSB)
#define AUDIO_PLL_CONFIG_POSTPLLDIV_SET(x) (((x) << AUDIO_PLL_CONFIG_POSTPLLDIV_LSB) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK)
#define AUDIO_PLL_CONFIG_POSTPLLDIV_RESET 0x1 // 1
#define AUDIO_PLL_CONFIG_PLLPWD_MSB 5
#define AUDIO_PLL_CONFIG_PLLPWD_LSB 5
#define AUDIO_PLL_CONFIG_PLLPWD_MASK 0x00000020
#define AUDIO_PLL_CONFIG_PLLPWD_GET(x) (((x) & AUDIO_PLL_CONFIG_PLLPWD_MASK) >> AUDIO_PLL_CONFIG_PLLPWD_LSB)
#define AUDIO_PLL_CONFIG_PLLPWD_SET(x) (((x) << AUDIO_PLL_CONFIG_PLLPWD_LSB) & AUDIO_PLL_CONFIG_PLLPWD_MASK)
#define AUDIO_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
#define AUDIO_PLL_CONFIG_BYPASS_MSB 4
#define AUDIO_PLL_CONFIG_BYPASS_LSB 4
#define AUDIO_PLL_CONFIG_BYPASS_MASK 0x00000010
#define AUDIO_PLL_CONFIG_BYPASS_GET(x) (((x) & AUDIO_PLL_CONFIG_BYPASS_MASK) >> AUDIO_PLL_CONFIG_BYPASS_LSB)
#define AUDIO_PLL_CONFIG_BYPASS_SET(x) (((x) << AUDIO_PLL_CONFIG_BYPASS_LSB) & AUDIO_PLL_CONFIG_BYPASS_MASK)
#define AUDIO_PLL_CONFIG_BYPASS_RESET 0x1 // 1
#define AUDIO_PLL_CONFIG_REFDIV_MSB 3
#define AUDIO_PLL_CONFIG_REFDIV_LSB 0
#define AUDIO_PLL_CONFIG_REFDIV_MASK 0x0000000f
#define AUDIO_PLL_CONFIG_REFDIV_GET(x) (((x) & AUDIO_PLL_CONFIG_REFDIV_MASK) >> AUDIO_PLL_CONFIG_REFDIV_LSB)
#define AUDIO_PLL_CONFIG_REFDIV_SET(x) (((x) << AUDIO_PLL_CONFIG_REFDIV_LSB) & AUDIO_PLL_CONFIG_REFDIV_MASK)
#define AUDIO_PLL_CONFIG_REFDIV_RESET 0x3 // 3
#define AUDIO_PLL_CONFIG_ADDRESS 0x1805002c
#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MSB 28
#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB 11
#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK 0x1ffff800
#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_GET(x) (((x) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB)
#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_SET(x) (((x) << AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK)
#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_RESET 0x148fe // 84222
#define AUDIO_PLL_MODULATION_TGT_DIV_INT_MSB 6
#define AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB 1
#define AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK 0x0000007e
#define AUDIO_PLL_MODULATION_TGT_DIV_INT_GET(x) (((x) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB)
#define AUDIO_PLL_MODULATION_TGT_DIV_INT_SET(x) (((x) << AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK)
#define AUDIO_PLL_MODULATION_TGT_DIV_INT_RESET 0x14 // 20
#define AUDIO_PLL_MODULATION_START_MSB 0
#define AUDIO_PLL_MODULATION_START_LSB 0
#define AUDIO_PLL_MODULATION_START_MASK 0x00000001
#define AUDIO_PLL_MODULATION_START_GET(x) (((x) & AUDIO_PLL_MODULATION_START_MASK) >> AUDIO_PLL_MODULATION_START_LSB)
#define AUDIO_PLL_MODULATION_START_SET(x) (((x) << AUDIO_PLL_MODULATION_START_LSB) & AUDIO_PLL_MODULATION_START_MASK)
#define AUDIO_PLL_MODULATION_START_RESET 0x0 // 0
#define AUDIO_PLL_MODULATION_ADDRESS 0x18050030
#define AUDIO_PLL_MOD_STEP_FRAC_MSB 31
#define AUDIO_PLL_MOD_STEP_FRAC_LSB 14
#define AUDIO_PLL_MOD_STEP_FRAC_MASK 0xffffc000
#define AUDIO_PLL_MOD_STEP_FRAC_GET(x) (((x) & AUDIO_PLL_MOD_STEP_FRAC_MASK) >> AUDIO_PLL_MOD_STEP_FRAC_LSB)
#define AUDIO_PLL_MOD_STEP_FRAC_SET(x) (((x) << AUDIO_PLL_MOD_STEP_FRAC_LSB) & AUDIO_PLL_MOD_STEP_FRAC_MASK)
#define AUDIO_PLL_MOD_STEP_FRAC_RESET 0x1 // 1
#define AUDIO_PLL_MOD_STEP_INT_MSB 13
#define AUDIO_PLL_MOD_STEP_INT_LSB 4
#define AUDIO_PLL_MOD_STEP_INT_MASK 0x00003ff0
#define AUDIO_PLL_MOD_STEP_INT_GET(x) (((x) & AUDIO_PLL_MOD_STEP_INT_MASK) >> AUDIO_PLL_MOD_STEP_INT_LSB)
#define AUDIO_PLL_MOD_STEP_INT_SET(x) (((x) << AUDIO_PLL_MOD_STEP_INT_LSB) & AUDIO_PLL_MOD_STEP_INT_MASK)
#define AUDIO_PLL_MOD_STEP_INT_RESET 0x0 // 0
#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MSB 3
#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB 0
#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK 0x0000000f
#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_GET(x) (((x) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK) >> AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB)
#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_SET(x) (((x) << AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK)
#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_RESET 0x0 // 0
#define AUDIO_PLL_MOD_STEP_ADDRESS 0x18050034
#define CURRENT_AUDIO_PLL_MODULATION_FRAC_MSB 27
#define CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB 10
#define CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK 0x0ffffc00
#define CURRENT_AUDIO_PLL_MODULATION_FRAC_GET(x) (((x) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK) >> CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB)
#define CURRENT_AUDIO_PLL_MODULATION_FRAC_SET(x) (((x) << CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK)
#define CURRENT_AUDIO_PLL_MODULATION_FRAC_RESET 0x1 // 1
#define CURRENT_AUDIO_PLL_MODULATION_INT_MSB 6
#define CURRENT_AUDIO_PLL_MODULATION_INT_LSB 1
#define CURRENT_AUDIO_PLL_MODULATION_INT_MASK 0x0000007e
#define CURRENT_AUDIO_PLL_MODULATION_INT_GET(x) (((x) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK) >> CURRENT_AUDIO_PLL_MODULATION_INT_LSB)
#define CURRENT_AUDIO_PLL_MODULATION_INT_SET(x) (((x) << CURRENT_AUDIO_PLL_MODULATION_INT_LSB) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK)
#define CURRENT_AUDIO_PLL_MODULATION_INT_RESET 0x0 // 0
#define CURRENT_AUDIO_PLL_MODULATION_ADDRESS 0x18050038
#define BB_PLL_CONFIG_UPDATING_MSB 31
#define BB_PLL_CONFIG_UPDATING_LSB 31
#define BB_PLL_CONFIG_UPDATING_MASK 0x80000000
#define BB_PLL_CONFIG_UPDATING_GET(x) (((x) & BB_PLL_CONFIG_UPDATING_MASK) >> BB_PLL_CONFIG_UPDATING_LSB)
#define BB_PLL_CONFIG_UPDATING_SET(x) (((x) << BB_PLL_CONFIG_UPDATING_LSB) & BB_PLL_CONFIG_UPDATING_MASK)
#define BB_PLL_CONFIG_UPDATING_RESET 0x1 // 1
#define BB_PLL_CONFIG_PLLPWD_MSB 30
#define BB_PLL_CONFIG_PLLPWD_LSB 30
#define BB_PLL_CONFIG_PLLPWD_MASK 0x40000000
#define BB_PLL_CONFIG_PLLPWD_GET(x) (((x) & BB_PLL_CONFIG_PLLPWD_MASK) >> BB_PLL_CONFIG_PLLPWD_LSB)
#define BB_PLL_CONFIG_PLLPWD_SET(x) (((x) << BB_PLL_CONFIG_PLLPWD_LSB) & BB_PLL_CONFIG_PLLPWD_MASK)
#define BB_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
#define BB_PLL_CONFIG_SPARE_MSB 29
#define BB_PLL_CONFIG_SPARE_LSB 29
#define BB_PLL_CONFIG_SPARE_MASK 0x20000000
#define BB_PLL_CONFIG_SPARE_GET(x) (((x) & BB_PLL_CONFIG_SPARE_MASK) >> BB_PLL_CONFIG_SPARE_LSB)
#define BB_PLL_CONFIG_SPARE_SET(x) (((x) << BB_PLL_CONFIG_SPARE_LSB) & BB_PLL_CONFIG_SPARE_MASK)
#define BB_PLL_CONFIG_SPARE_RESET 0x0 // 0
#define BB_PLL_CONFIG_REFDIV_MSB 28
#define BB_PLL_CONFIG_REFDIV_LSB 24
#define BB_PLL_CONFIG_REFDIV_MASK 0x1f000000
#define BB_PLL_CONFIG_REFDIV_GET(x) (((x) & BB_PLL_CONFIG_REFDIV_MASK) >> BB_PLL_CONFIG_REFDIV_LSB)
#define BB_PLL_CONFIG_REFDIV_SET(x) (((x) << BB_PLL_CONFIG_REFDIV_LSB) & BB_PLL_CONFIG_REFDIV_MASK)
#define BB_PLL_CONFIG_REFDIV_RESET 0x1 // 1
#define BB_PLL_CONFIG_NINT_MSB 21
#define BB_PLL_CONFIG_NINT_LSB 16
#define BB_PLL_CONFIG_NINT_MASK 0x003f0000
#define BB_PLL_CONFIG_NINT_GET(x) (((x) & BB_PLL_CONFIG_NINT_MASK) >> BB_PLL_CONFIG_NINT_LSB)
#define BB_PLL_CONFIG_NINT_SET(x) (((x) << BB_PLL_CONFIG_NINT_LSB) & BB_PLL_CONFIG_NINT_MASK)
#define BB_PLL_CONFIG_NINT_RESET 0x2 // 2
#define BB_PLL_CONFIG_NFRAC_MSB 13
#define BB_PLL_CONFIG_NFRAC_LSB 0
#define BB_PLL_CONFIG_NFRAC_MASK 0x00003fff
#define BB_PLL_CONFIG_NFRAC_GET(x) (((x) & BB_PLL_CONFIG_NFRAC_MASK) >> BB_PLL_CONFIG_NFRAC_LSB)
#define BB_PLL_CONFIG_NFRAC_SET(x) (((x) << BB_PLL_CONFIG_NFRAC_LSB) & BB_PLL_CONFIG_NFRAC_MASK)
#define BB_PLL_CONFIG_NFRAC_RESET 0xccc // 3276
#define BB_PLL_CONFIG_ADDRESS 0x1805003c
#define DDR_PLL_DITHER_DITHER_EN_MSB 31
#define DDR_PLL_DITHER_DITHER_EN_LSB 31
#define DDR_PLL_DITHER_DITHER_EN_MASK 0x80000000
#define DDR_PLL_DITHER_DITHER_EN_GET(x) (((x) & DDR_PLL_DITHER_DITHER_EN_MASK) >> DDR_PLL_DITHER_DITHER_EN_LSB)
#define DDR_PLL_DITHER_DITHER_EN_SET(x) (((x) << DDR_PLL_DITHER_DITHER_EN_LSB) & DDR_PLL_DITHER_DITHER_EN_MASK)
#define DDR_PLL_DITHER_DITHER_EN_RESET 0x0 // 0
#define DDR_PLL_DITHER_UPDATE_COUNT_MSB 30
#define DDR_PLL_DITHER_UPDATE_COUNT_LSB 27
#define DDR_PLL_DITHER_UPDATE_COUNT_MASK 0x78000000
#define DDR_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) >> DDR_PLL_DITHER_UPDATE_COUNT_LSB)
#define DDR_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) & DDR_PLL_DITHER_UPDATE_COUNT_MASK)
#define DDR_PLL_DITHER_UPDATE_COUNT_RESET 0xf // 15
#define DDR_PLL_DITHER_NFRAC_STEP_MSB 26
#define DDR_PLL_DITHER_NFRAC_STEP_LSB 20
#define DDR_PLL_DITHER_NFRAC_STEP_MASK 0x07f00000
#define DDR_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_STEP_MASK) >> DDR_PLL_DITHER_NFRAC_STEP_LSB)
#define DDR_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_STEP_LSB) & DDR_PLL_DITHER_NFRAC_STEP_MASK)
#define DDR_PLL_DITHER_NFRAC_STEP_RESET 0x1 // 1
#define DDR_PLL_DITHER_NFRAC_MIN_MSB 19
#define DDR_PLL_DITHER_NFRAC_MIN_LSB 10
#define DDR_PLL_DITHER_NFRAC_MIN_MASK 0x000ffc00
#define DDR_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MIN_MASK) >> DDR_PLL_DITHER_NFRAC_MIN_LSB)
#define DDR_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MIN_LSB) & DDR_PLL_DITHER_NFRAC_MIN_MASK)
#define DDR_PLL_DITHER_NFRAC_MIN_RESET 0x19 // 25
#define DDR_PLL_DITHER_NFRAC_MAX_MSB 9
#define DDR_PLL_DITHER_NFRAC_MAX_LSB 0
#define DDR_PLL_DITHER_NFRAC_MAX_MASK 0x000003ff
#define DDR_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MAX_MASK) >> DDR_PLL_DITHER_NFRAC_MAX_LSB)
#define DDR_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MAX_LSB) & DDR_PLL_DITHER_NFRAC_MAX_MASK)
#define DDR_PLL_DITHER_NFRAC_MAX_RESET 0x3e8 // 1000
#define DDR_PLL_DITHER_ADDRESS 0x18050040
#define CPU_PLL_DITHER_DITHER_EN_MSB 31
#define CPU_PLL_DITHER_DITHER_EN_LSB 31
#define CPU_PLL_DITHER_DITHER_EN_MASK 0x80000000
#define CPU_PLL_DITHER_DITHER_EN_GET(x) (((x) & CPU_PLL_DITHER_DITHER_EN_MASK) >> CPU_PLL_DITHER_DITHER_EN_LSB)
#define CPU_PLL_DITHER_DITHER_EN_SET(x) (((x) << CPU_PLL_DITHER_DITHER_EN_LSB) & CPU_PLL_DITHER_DITHER_EN_MASK)
#define CPU_PLL_DITHER_DITHER_EN_RESET 0x0 // 0
#define CPU_PLL_DITHER_UPDATE_COUNT_MSB 23
#define CPU_PLL_DITHER_UPDATE_COUNT_LSB 18
#define CPU_PLL_DITHER_UPDATE_COUNT_MASK 0x00fc0000
#define CPU_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) >> CPU_PLL_DITHER_UPDATE_COUNT_LSB)
#define CPU_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << CPU_PLL_DITHER_UPDATE_COUNT_LSB) & CPU_PLL_DITHER_UPDATE_COUNT_MASK)
#define CPU_PLL_DITHER_UPDATE_COUNT_RESET 0x14 // 20
#define CPU_PLL_DITHER_NFRAC_STEP_MSB 17
#define CPU_PLL_DITHER_NFRAC_STEP_LSB 12
#define CPU_PLL_DITHER_NFRAC_STEP_MASK 0x0003f000
#define CPU_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_STEP_MASK) >> CPU_PLL_DITHER_NFRAC_STEP_LSB)
#define CPU_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_STEP_LSB) & CPU_PLL_DITHER_NFRAC_STEP_MASK)
#define CPU_PLL_DITHER_NFRAC_STEP_RESET 0x1 // 1
#define CPU_PLL_DITHER_NFRAC_MIN_MSB 11
#define CPU_PLL_DITHER_NFRAC_MIN_LSB 6
#define CPU_PLL_DITHER_NFRAC_MIN_MASK 0x00000fc0
#define CPU_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MIN_MASK) >> CPU_PLL_DITHER_NFRAC_MIN_LSB)
#define CPU_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MIN_LSB) & CPU_PLL_DITHER_NFRAC_MIN_MASK)
#define CPU_PLL_DITHER_NFRAC_MIN_RESET 0x3 // 3
#define CPU_PLL_DITHER_NFRAC_MAX_MSB 5
#define CPU_PLL_DITHER_NFRAC_MAX_LSB 0
#define CPU_PLL_DITHER_NFRAC_MAX_MASK 0x0000003f
#define CPU_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MAX_MASK) >> CPU_PLL_DITHER_NFRAC_MAX_LSB)
#define CPU_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MAX_LSB) & CPU_PLL_DITHER_NFRAC_MAX_MASK)
#define CPU_PLL_DITHER_NFRAC_MAX_RESET 0x3c // 60
#define CPU_PLL_DITHER_ADDRESS 0x18050044
#define RST_RESET_HOST_RESET_MSB 31
#define RST_RESET_HOST_RESET_LSB 31
#define RST_RESET_HOST_RESET_MASK 0x80000000
#define RST_RESET_HOST_RESET_GET(x) (((x) & RST_RESET_HOST_RESET_MASK) >> RST_RESET_HOST_RESET_LSB)
#define RST_RESET_HOST_RESET_SET(x) (((x) << RST_RESET_HOST_RESET_LSB) & RST_RESET_HOST_RESET_MASK)
#define RST_RESET_HOST_RESET_RESET 0x0 // 0
#define RST_RESET_SLIC_RESET_MSB 30
#define RST_RESET_SLIC_RESET_LSB 30
#define RST_RESET_SLIC_RESET_MASK 0x40000000
#define RST_RESET_SLIC_RESET_GET(x) (((x) & RST_RESET_SLIC_RESET_MASK) >> RST_RESET_SLIC_RESET_LSB)
#define RST_RESET_SLIC_RESET_SET(x) (((x) << RST_RESET_SLIC_RESET_LSB) & RST_RESET_SLIC_RESET_MASK)
#define RST_RESET_SLIC_RESET_RESET 0x0 // 0
#define RST_RESET_HDMA_RESET_MSB 29
#define RST_RESET_HDMA_RESET_LSB 29
#define RST_RESET_HDMA_RESET_MASK 0x20000000
#define RST_RESET_HDMA_RESET_GET(x) (((x) & RST_RESET_HDMA_RESET_MASK) >> RST_RESET_HDMA_RESET_LSB)
#define RST_RESET_HDMA_RESET_SET(x) (((x) << RST_RESET_HDMA_RESET_LSB) & RST_RESET_HDMA_RESET_MASK)
#define RST_RESET_HDMA_RESET_RESET 0x1 // 1
#define RST_RESET_EXTERNAL_RESET_MSB 28
#define RST_RESET_EXTERNAL_RESET_LSB 28
#define RST_RESET_EXTERNAL_RESET_MASK 0x10000000
#define RST_RESET_EXTERNAL_RESET_GET(x) (((x) & RST_RESET_EXTERNAL_RESET_MASK) >> RST_RESET_EXTERNAL_RESET_LSB)
#define RST_RESET_EXTERNAL_RESET_SET(x) (((x) << RST_RESET_EXTERNAL_RESET_LSB) & RST_RESET_EXTERNAL_RESET_MASK)
#define RST_RESET_EXTERNAL_RESET_RESET 0x0 // 0
#define RST_RESET_RTC_RESET_MSB 27
#define RST_RESET_RTC_RESET_LSB 27
#define RST_RESET_RTC_RESET_MASK 0x08000000
#define RST_RESET_RTC_RESET_GET(x) (((x) & RST_RESET_RTC_RESET_MASK) >> RST_RESET_RTC_RESET_LSB)
#define RST_RESET_RTC_RESET_SET(x) (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK)
#define RST_RESET_RTC_RESET_RESET 0x1 // 1
#define RST_RESET_PCIEEP_RST_INT_MSB 26
#define RST_RESET_PCIEEP_RST_INT_LSB 26
#define RST_RESET_PCIEEP_RST_INT_MASK 0x04000000
#define RST_RESET_PCIEEP_RST_INT_GET(x) (((x) & RST_RESET_PCIEEP_RST_INT_MASK) >> RST_RESET_PCIEEP_RST_INT_LSB)
#define RST_RESET_PCIEEP_RST_INT_SET(x) (((x) << RST_RESET_PCIEEP_RST_INT_LSB) & RST_RESET_PCIEEP_RST_INT_MASK)
#define RST_RESET_PCIEEP_RST_INT_RESET 0x0 // 0
#define RST_RESET_CHKSUM_ACC_RESET_MSB 25
#define RST_RESET_CHKSUM_ACC_RESET_LSB 25
#define RST_RESET_CHKSUM_ACC_RESET_MASK 0x02000000
#define RST_RESET_CHKSUM_ACC_RESET_GET(x) (((x) & RST_RESET_CHKSUM_ACC_RESET_MASK) >> RST_RESET_CHKSUM_ACC_RESET_LSB)
#define RST_RESET_CHKSUM_ACC_RESET_SET(x) (((x) << RST_RESET_CHKSUM_ACC_RESET_LSB) & RST_RESET_CHKSUM_ACC_RESET_MASK)
#define RST_RESET_CHKSUM_ACC_RESET_RESET 0x0 // 0
#define RST_RESET_FULL_CHIP_RESET_MSB 24
#define RST_RESET_FULL_CHIP_RESET_LSB 24
#define RST_RESET_FULL_CHIP_RESET_MASK 0x01000000
#define RST_RESET_FULL_CHIP_RESET_GET(x) (((x) & RST_RESET_FULL_CHIP_RESET_MASK) >> RST_RESET_FULL_CHIP_RESET_LSB)
#define RST_RESET_FULL_CHIP_RESET_SET(x) (((x) << RST_RESET_FULL_CHIP_RESET_LSB) & RST_RESET_FULL_CHIP_RESET_MASK)
#define RST_RESET_FULL_CHIP_RESET_RESET 0x0 // 0
#define RST_RESET_GE1_MDIO_RESET_MSB 23
#define RST_RESET_GE1_MDIO_RESET_LSB 23
#define RST_RESET_GE1_MDIO_RESET_MASK 0x00800000
#define RST_RESET_GE1_MDIO_RESET_GET(x) (((x) & RST_RESET_GE1_MDIO_RESET_MASK) >> RST_RESET_GE1_MDIO_RESET_LSB)
#define RST_RESET_GE1_MDIO_RESET_SET(x) (((x) << RST_RESET_GE1_MDIO_RESET_LSB) & RST_RESET_GE1_MDIO_RESET_MASK)
#define RST_RESET_GE1_MDIO_RESET_RESET 0x1 // 1
#define RST_RESET_GE0_MDIO_RESET_MSB 22
#define RST_RESET_GE0_MDIO_RESET_LSB 22
#define RST_RESET_GE0_MDIO_RESET_MASK 0x00400000
#define RST_RESET_GE0_MDIO_RESET_GET(x) (((x) & RST_RESET_GE0_MDIO_RESET_MASK) >> RST_RESET_GE0_MDIO_RESET_LSB)
#define RST_RESET_GE0_MDIO_RESET_SET(x) (((x) << RST_RESET_GE0_MDIO_RESET_LSB) & RST_RESET_GE0_MDIO_RESET_MASK)
#define RST_RESET_GE0_MDIO_RESET_RESET 0x1 // 1
#define RST_RESET_CPU_NMI_MSB 21
#define RST_RESET_CPU_NMI_LSB 21
#define RST_RESET_CPU_NMI_MASK 0x00200000
#define RST_RESET_CPU_NMI_GET(x) (((x) & RST_RESET_CPU_NMI_MASK) >> RST_RESET_CPU_NMI_LSB)
#define RST_RESET_CPU_NMI_SET(x) (((x) << RST_RESET_CPU_NMI_LSB) & RST_RESET_CPU_NMI_MASK)
#define RST_RESET_CPU_NMI_RESET 0x0 // 0
#define RST_RESET_CPU_COLD_RESET_MSB 20
#define RST_RESET_CPU_COLD_RESET_LSB 20
#define RST_RESET_CPU_COLD_RESET_MASK 0x00100000
#define RST_RESET_CPU_COLD_RESET_GET(x) (((x) & RST_RESET_CPU_COLD_RESET_MASK) >> RST_RESET_CPU_COLD_RESET_LSB)
#define RST_RESET_CPU_COLD_RESET_SET(x) (((x) << RST_RESET_CPU_COLD_RESET_LSB) & RST_RESET_CPU_COLD_RESET_MASK)
#define RST_RESET_CPU_COLD_RESET_RESET 0x0 // 0
#define RST_RESET_HOST_RESET_INT_MSB 19
#define RST_RESET_HOST_RESET_INT_LSB 19
#define RST_RESET_HOST_RESET_INT_MASK 0x00080000
#define RST_RESET_HOST_RESET_INT_GET(x) (((x) & RST_RESET_HOST_RESET_INT_MASK) >> RST_RESET_HOST_RESET_INT_LSB)
#define RST_RESET_HOST_RESET_INT_SET(x) (((x) << RST_RESET_HOST_RESET_INT_LSB) & RST_RESET_HOST_RESET_INT_MASK)
#define RST_RESET_HOST_RESET_INT_RESET 0x0 // 0
#define RST_RESET_PCIEEP_RESET_MSB 18
#define RST_RESET_PCIEEP_RESET_LSB 18
#define RST_RESET_PCIEEP_RESET_MASK 0x00040000
#define RST_RESET_PCIEEP_RESET_GET(x) (((x) & RST_RESET_PCIEEP_RESET_MASK) >> RST_RESET_PCIEEP_RESET_LSB)
#define RST_RESET_PCIEEP_RESET_SET(x) (((x) << RST_RESET_PCIEEP_RESET_LSB) & RST_RESET_PCIEEP_RESET_MASK)
#define RST_RESET_PCIEEP_RESET_RESET 0x0 // 0
#define RST_RESET_UART1_RESET_MSB 17
#define RST_RESET_UART1_RESET_LSB 17
#define RST_RESET_UART1_RESET_MASK 0x00020000
#define RST_RESET_UART1_RESET_GET(x) (((x) & RST_RESET_UART1_RESET_MASK) >> RST_RESET_UART1_RESET_LSB)
#define RST_RESET_UART1_RESET_SET(x) (((x) << RST_RESET_UART1_RESET_LSB) & RST_RESET_UART1_RESET_MASK)
#define RST_RESET_UART1_RESET_RESET 0x0 // 0
#define RST_RESET_DDR_RESET_MSB 16
#define RST_RESET_DDR_RESET_LSB 16
#define RST_RESET_DDR_RESET_MASK 0x00010000
#define RST_RESET_DDR_RESET_GET(x) (((x) & RST_RESET_DDR_RESET_MASK) >> RST_RESET_DDR_RESET_LSB)
#define RST_RESET_DDR_RESET_SET(x) (((x) << RST_RESET_DDR_RESET_LSB) & RST_RESET_DDR_RESET_MASK)
#define RST_RESET_DDR_RESET_RESET 0x0 // 0
#define RST_RESET_USB_PHY_PLL_PWD_EXT_MSB 15
#define RST_RESET_USB_PHY_PLL_PWD_EXT_LSB 15
#define RST_RESET_USB_PHY_PLL_PWD_EXT_MASK 0x00008000
#define RST_RESET_USB_PHY_PLL_PWD_EXT_GET(x) (((x) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) >> RST_RESET_USB_PHY_PLL_PWD_EXT_LSB)
#define RST_RESET_USB_PHY_PLL_PWD_EXT_SET(x) (((x) << RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK)
#define RST_RESET_USB_PHY_PLL_PWD_EXT_RESET 0x0 // 0
#define RST_RESET_NANDF_RESET_MSB 14
#define RST_RESET_NANDF_RESET_LSB 14
#define RST_RESET_NANDF_RESET_MASK 0x00004000
#define RST_RESET_NANDF_RESET_GET(x) (((x) & RST_RESET_NANDF_RESET_MASK) >> RST_RESET_NANDF_RESET_LSB)
#define RST_RESET_NANDF_RESET_SET(x) (((x) << RST_RESET_NANDF_RESET_LSB) & RST_RESET_NANDF_RESET_MASK)
#define RST_RESET_NANDF_RESET_RESET 0x1 // 1
#define RST_RESET_GE1_MAC_RESET_MSB 13
#define RST_RESET_GE1_MAC_RESET_LSB 13
#define RST_RESET_GE1_MAC_RESET_MASK 0x00002000
#define RST_RESET_GE1_MAC_RESET_GET(x) (((x) & RST_RESET_GE1_MAC_RESET_MASK) >> RST_RESET_GE1_MAC_RESET_LSB)
#define RST_RESET_GE1_MAC_RESET_SET(x) (((x) << RST_RESET_GE1_MAC_RESET_LSB) & RST_RESET_GE1_MAC_RESET_MASK)
#define RST_RESET_GE1_MAC_RESET_RESET 0x1 // 1
#define RST_RESET_ETH_SGMII_ARESET_MSB 12
#define RST_RESET_ETH_SGMII_ARESET_LSB 12
#define RST_RESET_ETH_SGMII_ARESET_MASK 0x00001000
#define RST_RESET_ETH_SGMII_ARESET_GET(x) (((x) & RST_RESET_ETH_SGMII_ARESET_MASK) >> RST_RESET_ETH_SGMII_ARESET_LSB)
#define RST_RESET_ETH_SGMII_ARESET_SET(x) (((x) << RST_RESET_ETH_SGMII_ARESET_LSB) & RST_RESET_ETH_SGMII_ARESET_MASK)
#define RST_RESET_ETH_SGMII_ARESET_RESET 0x1 // 1
#define RST_RESET_USB_PHY_ARESET_MSB 11
#define RST_RESET_USB_PHY_ARESET_LSB 11
#define RST_RESET_USB_PHY_ARESET_MASK 0x00000800
#define RST_RESET_USB_PHY_ARESET_GET(x) (((x) & RST_RESET_USB_PHY_ARESET_MASK) >> RST_RESET_USB_PHY_ARESET_LSB)
#define RST_RESET_USB_PHY_ARESET_SET(x) (((x) << RST_RESET_USB_PHY_ARESET_LSB) & RST_RESET_USB_PHY_ARESET_MASK)
#define RST_RESET_USB_PHY_ARESET_RESET 0x1 // 1
#define RST_RESET_HOST_DMA_INT_MSB 10
#define RST_RESET_HOST_DMA_INT_LSB 10
#define RST_RESET_HOST_DMA_INT_MASK 0x00000400
#define RST_RESET_HOST_DMA_INT_GET(x) (((x) & RST_RESET_HOST_DMA_INT_MASK) >> RST_RESET_HOST_DMA_INT_LSB)
#define RST_RESET_HOST_DMA_INT_SET(x) (((x) << RST_RESET_HOST_DMA_INT_LSB) & RST_RESET_HOST_DMA_INT_MASK)
#define RST_RESET_HOST_DMA_INT_RESET 0x0 // 0
#define RST_RESET_GE0_MAC_RESET_MSB 9
#define RST_RESET_GE0_MAC_RESET_LSB 9
#define RST_RESET_GE0_MAC_RESET_MASK 0x00000200
#define RST_RESET_GE0_MAC_RESET_GET(x) (((x) & RST_RESET_GE0_MAC_RESET_MASK) >> RST_RESET_GE0_MAC_RESET_LSB)
#define RST_RESET_GE0_MAC_RESET_SET(x) (((x) << RST_RESET_GE0_MAC_RESET_LSB) & RST_RESET_GE0_MAC_RESET_MASK)
#define RST_RESET_GE0_MAC_RESET_RESET 0x1 // 1
#define RST_RESET_ETH_SGMII_RESET_MSB 8
#define RST_RESET_ETH_SGMII_RESET_LSB 8
#define RST_RESET_ETH_SGMII_RESET_MASK 0x00000100
#define RST_RESET_ETH_SGMII_RESET_GET(x) (((x) & RST_RESET_ETH_SGMII_RESET_MASK) >> RST_RESET_ETH_SGMII_RESET_LSB)
#define RST_RESET_ETH_SGMII_RESET_SET(x) (((x) << RST_RESET_ETH_SGMII_RESET_LSB) & RST_RESET_ETH_SGMII_RESET_MASK)
#define RST_RESET_ETH_SGMII_RESET_RESET 0x1 // 1
#define RST_RESET_PCIE_PHY_RESET_MSB 7
#define RST_RESET_PCIE_PHY_RESET_LSB 7
#define RST_RESET_PCIE_PHY_RESET_MASK 0x00000080
#define RST_RESET_PCIE_PHY_RESET_GET(x) (((x) & RST_RESET_PCIE_PHY_RESET_MASK) >> RST_RESET_PCIE_PHY_RESET_LSB)
#define RST_RESET_PCIE_PHY_RESET_SET(x) (((x) << RST_RESET_PCIE_PHY_RESET_LSB) & RST_RESET_PCIE_PHY_RESET_MASK)
#define RST_RESET_PCIE_PHY_RESET_RESET 0x1 // 1
#define RST_RESET_PCIE_RESET_MSB 6
#define RST_RESET_PCIE_RESET_LSB 6
#define RST_RESET_PCIE_RESET_MASK 0x00000040
#define RST_RESET_PCIE_RESET_GET(x) (((x) & RST_RESET_PCIE_RESET_MASK) >> RST_RESET_PCIE_RESET_LSB)
#define RST_RESET_PCIE_RESET_SET(x) (((x) << RST_RESET_PCIE_RESET_LSB) & RST_RESET_PCIE_RESET_MASK)
#define RST_RESET_PCIE_RESET_RESET 0x1 // 1
#define RST_RESET_USB_HOST_RESET_MSB 5
#define RST_RESET_USB_HOST_RESET_LSB 5
#define RST_RESET_USB_HOST_RESET_MASK 0x00000020
#define RST_RESET_USB_HOST_RESET_GET(x) (((x) & RST_RESET_USB_HOST_RESET_MASK) >> RST_RESET_USB_HOST_RESET_LSB)
#define RST_RESET_USB_HOST_RESET_SET(x) (((x) << RST_RESET_USB_HOST_RESET_LSB) & RST_RESET_USB_HOST_RESET_MASK)
#define RST_RESET_USB_HOST_RESET_RESET 0x1 // 1
#define RST_RESET_USB_PHY_RESET_MSB 4
#define RST_RESET_USB_PHY_RESET_LSB 4
#define RST_RESET_USB_PHY_RESET_MASK 0x00000010
#define RST_RESET_USB_PHY_RESET_GET(x) (((x) & RST_RESET_USB_PHY_RESET_MASK) >> RST_RESET_USB_PHY_RESET_LSB)
#define RST_RESET_USB_PHY_RESET_SET(x) (((x) << RST_RESET_USB_PHY_RESET_LSB) & RST_RESET_USB_PHY_RESET_MASK)
#define RST_RESET_USB_PHY_RESET_RESET 0x1 // 1
#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MSB 3
#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB 3
#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK 0x00000008
#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_GET(x) (((x) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) >> RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB)
#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(x) (((x) << RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK)
#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_RESET 0x0 // 0
#define RST_RESET_LUT_RESET_MSB 2
#define RST_RESET_LUT_RESET_LSB 2
#define RST_RESET_LUT_RESET_MASK 0x00000004
#define RST_RESET_LUT_RESET_GET(x) (((x) & RST_RESET_LUT_RESET_MASK) >> RST_RESET_LUT_RESET_LSB)
#define RST_RESET_LUT_RESET_SET(x) (((x) << RST_RESET_LUT_RESET_LSB) & RST_RESET_LUT_RESET_MASK)
#define RST_RESET_LUT_RESET_RESET 0x0 // 0
#define RST_RESET_MBOX_RESET_MSB 1
#define RST_RESET_MBOX_RESET_LSB 1
#define RST_RESET_MBOX_RESET_MASK 0x00000002
#define RST_RESET_MBOX_RESET_GET(x) (((x) & RST_RESET_MBOX_RESET_MASK) >> RST_RESET_MBOX_RESET_LSB)
#define RST_RESET_MBOX_RESET_SET(x) (((x) << RST_RESET_MBOX_RESET_LSB) & RST_RESET_MBOX_RESET_MASK)
#define RST_RESET_MBOX_RESET_RESET 0x0 // 0
#define RST_RESET_I2S_RESET_MSB 0
#define RST_RESET_I2S_RESET_LSB 0
#define RST_RESET_I2S_RESET_MASK 0x00000001
#define RST_RESET_I2S_RESET_GET(x) (((x) & RST_RESET_I2S_RESET_MASK) >> RST_RESET_I2S_RESET_LSB)
#define RST_RESET_I2S_RESET_SET(x) (((x) << RST_RESET_I2S_RESET_LSB) & RST_RESET_I2S_RESET_MASK)
#define RST_RESET_I2S_RESET_RESET 0x0 // 0
#define RST_RESET_ADDRESS 0x1806001c
#define RST_MISC2_PCIEEP_LINK_UP_MSB 30
#define RST_MISC2_PCIEEP_LINK_UP_LSB 30
#define RST_MISC2_PCIEEP_LINK_UP_MASK 0x40000000
#define RST_MISC2_PCIEEP_LINK_UP_GET(x) (((x) & RST_MISC2_PCIEEP_LINK_UP_MASK) >> RST_MISC2_PCIEEP_LINK_UP_LSB)
#define RST_MISC2_PCIEEP_LINK_UP_SET(x) (((x) << RST_MISC2_PCIEEP_LINK_UP_LSB) & RST_MISC2_PCIEEP_LINK_UP_MASK)
#define RST_MISC2_PCIEEP_LINK_UP_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_CLKOBS2_SEL_MSB 29
#define RST_MISC2_PCIEEP_CLKOBS2_SEL_LSB 29
#define RST_MISC2_PCIEEP_CLKOBS2_SEL_MASK 0x20000000
#define RST_MISC2_PCIEEP_CLKOBS2_SEL_GET(x) (((x) & RST_MISC2_PCIEEP_CLKOBS2_SEL_MASK) >> RST_MISC2_PCIEEP_CLKOBS2_SEL_LSB)
#define RST_MISC2_PCIEEP_CLKOBS2_SEL_SET(x) (((x) << RST_MISC2_PCIEEP_CLKOBS2_SEL_LSB) & RST_MISC2_PCIEEP_CLKOBS2_SEL_MASK)
#define RST_MISC2_PCIEEP_CLKOBS2_SEL_RESET 0x0 // 0
#define RST_MISC2_PCIE_CLKOBS1_SEL_MSB 28
#define RST_MISC2_PCIE_CLKOBS1_SEL_LSB 28
#define RST_MISC2_PCIE_CLKOBS1_SEL_MASK 0x10000000
#define RST_MISC2_PCIE_CLKOBS1_SEL_GET(x) (((x) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK) >> RST_MISC2_PCIE_CLKOBS1_SEL_LSB)
#define RST_MISC2_PCIE_CLKOBS1_SEL_SET(x) (((x) << RST_MISC2_PCIE_CLKOBS1_SEL_LSB) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK)
#define RST_MISC2_PCIE_CLKOBS1_SEL_RESET 0x0 // 0
#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MSB 27
#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_LSB 27
#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MASK 0x08000000
#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_GET(x) (((x) & RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MASK) >> RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_LSB)
#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_SET(x) (((x) << RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_LSB) & RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MASK)
#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_RESET 0x0 // 0
#define RST_MISC2_WOW_STATUS_MSB 26
#define RST_MISC2_WOW_STATUS_LSB 26
#define RST_MISC2_WOW_STATUS_MASK 0x04000000
#define RST_MISC2_WOW_STATUS_GET(x) (((x) & RST_MISC2_WOW_STATUS_MASK) >> RST_MISC2_WOW_STATUS_LSB)
#define RST_MISC2_WOW_STATUS_SET(x) (((x) << RST_MISC2_WOW_STATUS_LSB) & RST_MISC2_WOW_STATUS_MASK)
#define RST_MISC2_WOW_STATUS_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_L2_EXIT_INT_MSB 25
#define RST_MISC2_PCIEEP_L2_EXIT_INT_LSB 25
#define RST_MISC2_PCIEEP_L2_EXIT_INT_MASK 0x02000000
#define RST_MISC2_PCIEEP_L2_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L2_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L2_EXIT_INT_LSB)
#define RST_MISC2_PCIEEP_L2_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L2_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L2_EXIT_INT_MASK)
#define RST_MISC2_PCIEEP_L2_EXIT_INT_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_L2_ENTR_INT_MSB 24
#define RST_MISC2_PCIEEP_L2_ENTR_INT_LSB 24
#define RST_MISC2_PCIEEP_L2_ENTR_INT_MASK 0x01000000
#define RST_MISC2_PCIEEP_L2_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L2_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L2_ENTR_INT_LSB)
#define RST_MISC2_PCIEEP_L2_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L2_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L2_ENTR_INT_MASK)
#define RST_MISC2_PCIEEP_L2_ENTR_INT_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_L1_EXIT_INT_MSB 23
#define RST_MISC2_PCIEEP_L1_EXIT_INT_LSB 23
#define RST_MISC2_PCIEEP_L1_EXIT_INT_MASK 0x00800000
#define RST_MISC2_PCIEEP_L1_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L1_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L1_EXIT_INT_LSB)
#define RST_MISC2_PCIEEP_L1_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L1_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L1_EXIT_INT_MASK)
#define RST_MISC2_PCIEEP_L1_EXIT_INT_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_L1_ENTR_INT_MSB 22
#define RST_MISC2_PCIEEP_L1_ENTR_INT_LSB 22
#define RST_MISC2_PCIEEP_L1_ENTR_INT_MASK 0x00400000
#define RST_MISC2_PCIEEP_L1_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L1_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L1_ENTR_INT_LSB)
#define RST_MISC2_PCIEEP_L1_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L1_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L1_ENTR_INT_MASK)
#define RST_MISC2_PCIEEP_L1_ENTR_INT_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_L0S_EXIT_INT_MSB 21
#define RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB 21
#define RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK 0x00200000
#define RST_MISC2_PCIEEP_L0S_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB)
#define RST_MISC2_PCIEEP_L0S_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK)
#define RST_MISC2_PCIEEP_L0S_EXIT_INT_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_L0S_ENTR_INT_MSB 20
#define RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB 20
#define RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK 0x00100000
#define RST_MISC2_PCIEEP_L0S_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB)
#define RST_MISC2_PCIEEP_L0S_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK)
#define RST_MISC2_PCIEEP_L0S_ENTR_INT_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_REGWR_EN_MSB 19
#define RST_MISC2_PCIEEP_REGWR_EN_LSB 19
#define RST_MISC2_PCIEEP_REGWR_EN_MASK 0x00080000
#define RST_MISC2_PCIEEP_REGWR_EN_GET(x) (((x) & RST_MISC2_PCIEEP_REGWR_EN_MASK) >> RST_MISC2_PCIEEP_REGWR_EN_LSB)
#define RST_MISC2_PCIEEP_REGWR_EN_SET(x) (((x) << RST_MISC2_PCIEEP_REGWR_EN_LSB) & RST_MISC2_PCIEEP_REGWR_EN_MASK)
#define RST_MISC2_PCIEEP_REGWR_EN_RESET 0x1 // 1
#define RST_MISC2_EXT_HOST_WASP_RST_EN_MSB 18
#define RST_MISC2_EXT_HOST_WASP_RST_EN_LSB 18
#define RST_MISC2_EXT_HOST_WASP_RST_EN_MASK 0x00040000
#define RST_MISC2_EXT_HOST_WASP_RST_EN_GET(x) (((x) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) >> RST_MISC2_EXT_HOST_WASP_RST_EN_LSB)
#define RST_MISC2_EXT_HOST_WASP_RST_EN_SET(x) (((x) << RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK)
#define RST_MISC2_EXT_HOST_WASP_RST_EN_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_RST_INT_MSB 17
#define RST_MISC2_PCIEEP_RST_INT_LSB 17
#define RST_MISC2_PCIEEP_RST_INT_MASK 0x00020000
#define RST_MISC2_PCIEEP_RST_INT_GET(x) (((x) & RST_MISC2_PCIEEP_RST_INT_MASK) >> RST_MISC2_PCIEEP_RST_INT_LSB)
#define RST_MISC2_PCIEEP_RST_INT_SET(x) (((x) << RST_MISC2_PCIEEP_RST_INT_LSB) & RST_MISC2_PCIEEP_RST_INT_MASK)
#define RST_MISC2_PCIEEP_RST_INT_RESET 0x0 // 0
#define RST_MISC2_HOST_RESET_INT_MSB 16
#define RST_MISC2_HOST_RESET_INT_LSB 16
#define RST_MISC2_HOST_RESET_INT_MASK 0x00010000
#define RST_MISC2_HOST_RESET_INT_GET(x) (((x) & RST_MISC2_HOST_RESET_INT_MASK) >> RST_MISC2_HOST_RESET_INT_LSB)
#define RST_MISC2_HOST_RESET_INT_SET(x) (((x) << RST_MISC2_HOST_RESET_INT_LSB) & RST_MISC2_HOST_RESET_INT_MASK)
#define RST_MISC2_HOST_RESET_INT_RESET 0x0 // 0
#define RST_MISC2_CPU_HOST_WA_MSB 15
#define RST_MISC2_CPU_HOST_WA_LSB 15
#define RST_MISC2_CPU_HOST_WA_MASK 0x00008000
#define RST_MISC2_CPU_HOST_WA_GET(x) (((x) & RST_MISC2_CPU_HOST_WA_MASK) >> RST_MISC2_CPU_HOST_WA_LSB)
#define RST_MISC2_CPU_HOST_WA_SET(x) (((x) << RST_MISC2_CPU_HOST_WA_LSB) & RST_MISC2_CPU_HOST_WA_MASK)
#define RST_MISC2_CPU_HOST_WA_RESET 0x0 // 0
#define RST_MISC2_PERSTN_RCPHY2_MSB 14
#define RST_MISC2_PERSTN_RCPHY2_LSB 14
#define RST_MISC2_PERSTN_RCPHY2_MASK 0x00004000
#define RST_MISC2_PERSTN_RCPHY2_GET(x) (((x) & RST_MISC2_PERSTN_RCPHY2_MASK) >> RST_MISC2_PERSTN_RCPHY2_LSB)
#define RST_MISC2_PERSTN_RCPHY2_SET(x) (((x) << RST_MISC2_PERSTN_RCPHY2_LSB) & RST_MISC2_PERSTN_RCPHY2_MASK)
#define RST_MISC2_PERSTN_RCPHY2_RESET 0x1 // 1
#define RST_MISC2_PERSTN_RCPHY_MSB 13
#define RST_MISC2_PERSTN_RCPHY_LSB 13
#define RST_MISC2_PERSTN_RCPHY_MASK 0x00002000
#define RST_MISC2_PERSTN_RCPHY_GET(x) (((x) & RST_MISC2_PERSTN_RCPHY_MASK) >> RST_MISC2_PERSTN_RCPHY_LSB)
#define RST_MISC2_PERSTN_RCPHY_SET(x) (((x) << RST_MISC2_PERSTN_RCPHY_LSB) & RST_MISC2_PERSTN_RCPHY_MASK)
#define RST_MISC2_PERSTN_RCPHY_RESET 0x1 // 1
#define RST_MISC2_PCIEEP_LTSSM_STATE_MSB 12
#define RST_MISC2_PCIEEP_LTSSM_STATE_LSB 8
#define RST_MISC2_PCIEEP_LTSSM_STATE_MASK 0x00001f00
#define RST_MISC2_PCIEEP_LTSSM_STATE_GET(x) (((x) & RST_MISC2_PCIEEP_LTSSM_STATE_MASK) >> RST_MISC2_PCIEEP_LTSSM_STATE_LSB)
#define RST_MISC2_PCIEEP_LTSSM_STATE_SET(x) (((x) << RST_MISC2_PCIEEP_LTSSM_STATE_LSB) & RST_MISC2_PCIEEP_LTSSM_STATE_MASK)
#define RST_MISC2_PCIEEP_LTSSM_STATE_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_LINK_STATUS_MSB 4
#define RST_MISC2_PCIEEP_LINK_STATUS_LSB 4
#define RST_MISC2_PCIEEP_LINK_STATUS_MASK 0x00000010
#define RST_MISC2_PCIEEP_LINK_STATUS_GET(x) (((x) & RST_MISC2_PCIEEP_LINK_STATUS_MASK) >> RST_MISC2_PCIEEP_LINK_STATUS_LSB)
#define RST_MISC2_PCIEEP_LINK_STATUS_SET(x) (((x) << RST_MISC2_PCIEEP_LINK_STATUS_LSB) & RST_MISC2_PCIEEP_LINK_STATUS_MASK)
#define RST_MISC2_PCIEEP_LINK_STATUS_RESET 0x0 // 0
#define RST_MISC2_WOW_DETECT_MSB 3
#define RST_MISC2_WOW_DETECT_LSB 3
#define RST_MISC2_WOW_DETECT_MASK 0x00000008
#define RST_MISC2_WOW_DETECT_GET(x) (((x) & RST_MISC2_WOW_DETECT_MASK) >> RST_MISC2_WOW_DETECT_LSB)
#define RST_MISC2_WOW_DETECT_SET(x) (((x) << RST_MISC2_WOW_DETECT_LSB) & RST_MISC2_WOW_DETECT_MASK)
#define RST_MISC2_WOW_DETECT_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_RXDETECT_DONE_MSB 2
#define RST_MISC2_PCIEEP_RXDETECT_DONE_LSB 2
#define RST_MISC2_PCIEEP_RXDETECT_DONE_MASK 0x00000004
#define RST_MISC2_PCIEEP_RXDETECT_DONE_GET(x) (((x) & RST_MISC2_PCIEEP_RXDETECT_DONE_MASK) >> RST_MISC2_PCIEEP_RXDETECT_DONE_LSB)
#define RST_MISC2_PCIEEP_RXDETECT_DONE_SET(x) (((x) << RST_MISC2_PCIEEP_RXDETECT_DONE_LSB) & RST_MISC2_PCIEEP_RXDETECT_DONE_MASK)
#define RST_MISC2_PCIEEP_RXDETECT_DONE_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_WOW_INT_MSB 1
#define RST_MISC2_PCIEEP_WOW_INT_LSB 1
#define RST_MISC2_PCIEEP_WOW_INT_MASK 0x00000002
#define RST_MISC2_PCIEEP_WOW_INT_GET(x) (((x) & RST_MISC2_PCIEEP_WOW_INT_MASK) >> RST_MISC2_PCIEEP_WOW_INT_LSB)
#define RST_MISC2_PCIEEP_WOW_INT_SET(x) (((x) << RST_MISC2_PCIEEP_WOW_INT_LSB) & RST_MISC2_PCIEEP_WOW_INT_MASK)
#define RST_MISC2_PCIEEP_WOW_INT_RESET 0x0 // 0
#define RST_MISC2_PCIEEP_CFG_DONE_MSB 0
#define RST_MISC2_PCIEEP_CFG_DONE_LSB 0
#define RST_MISC2_PCIEEP_CFG_DONE_MASK 0x00000001
#define RST_MISC2_PCIEEP_CFG_DONE_GET(x) (((x) & RST_MISC2_PCIEEP_CFG_DONE_MASK) >> RST_MISC2_PCIEEP_CFG_DONE_LSB)
#define RST_MISC2_PCIEEP_CFG_DONE_SET(x) (((x) << RST_MISC2_PCIEEP_CFG_DONE_LSB) & RST_MISC2_PCIEEP_CFG_DONE_MASK)
#define RST_MISC2_PCIEEP_CFG_DONE_RESET 0x0 // 0
#define RST_MISC2_ADDRESS 0x180600bc
#define PCIE_APP_CFG_TYPE_MSB 21
#define PCIE_APP_CFG_TYPE_LSB 20
#define PCIE_APP_CFG_TYPE_MASK 0x00300000
#define PCIE_APP_CFG_TYPE_GET(x) (((x) & PCIE_APP_CFG_TYPE_MASK) >> PCIE_APP_CFG_TYPE_LSB)
#define PCIE_APP_CFG_TYPE_SET(x) (((x) << PCIE_APP_CFG_TYPE_LSB) & PCIE_APP_CFG_TYPE_MASK)
#define PCIE_APP_CFG_TYPE_RESET 0x0 // 0
#define PCIE_APP_PCIE_BAR_MSN_MSB 19
#define PCIE_APP_PCIE_BAR_MSN_LSB 16
#define PCIE_APP_PCIE_BAR_MSN_MASK 0x000f0000
#define PCIE_APP_PCIE_BAR_MSN_GET(x) (((x) & PCIE_APP_PCIE_BAR_MSN_MASK) >> PCIE_APP_PCIE_BAR_MSN_LSB)
#define PCIE_APP_PCIE_BAR_MSN_SET(x) (((x) << PCIE_APP_PCIE_BAR_MSN_LSB) & PCIE_APP_PCIE_BAR_MSN_MASK)
#define PCIE_APP_PCIE_BAR_MSN_RESET 0x1 // 1
#define PCIE_APP_CFG_BE_MSB 15
#define PCIE_APP_CFG_BE_LSB 12
#define PCIE_APP_CFG_BE_MASK 0x0000f000
#define PCIE_APP_CFG_BE_GET(x) (((x) & PCIE_APP_CFG_BE_MASK) >> PCIE_APP_CFG_BE_LSB)
#define PCIE_APP_CFG_BE_SET(x) (((x) << PCIE_APP_CFG_BE_LSB) & PCIE_APP_CFG_BE_MASK)
#define PCIE_APP_CFG_BE_RESET 0xf // 15
#define PCIE_APP_SLV_RESP_ERR_MAP_MSB 11
#define PCIE_APP_SLV_RESP_ERR_MAP_LSB 6
#define PCIE_APP_SLV_RESP_ERR_MAP_MASK 0x00000fc0
#define PCIE_APP_SLV_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_SLV_RESP_ERR_MAP_MASK) >> PCIE_APP_SLV_RESP_ERR_MAP_LSB)
#define PCIE_APP_SLV_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_SLV_RESP_ERR_MAP_LSB) & PCIE_APP_SLV_RESP_ERR_MAP_MASK)
#define PCIE_APP_SLV_RESP_ERR_MAP_RESET 0x3f // 63
#define PCIE_APP_MSTR_RESP_ERR_MAP_MSB 5
#define PCIE_APP_MSTR_RESP_ERR_MAP_LSB 4
#define PCIE_APP_MSTR_RESP_ERR_MAP_MASK 0x00000030
#define PCIE_APP_MSTR_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK) >> PCIE_APP_MSTR_RESP_ERR_MAP_LSB)
#define PCIE_APP_MSTR_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_MSTR_RESP_ERR_MAP_LSB) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK)
#define PCIE_APP_MSTR_RESP_ERR_MAP_RESET 0x0 // 0
#define PCIE_APP_INIT_RST_MSB 3
#define PCIE_APP_INIT_RST_LSB 3
#define PCIE_APP_INIT_RST_MASK 0x00000008
#define PCIE_APP_INIT_RST_GET(x) (((x) & PCIE_APP_INIT_RST_MASK) >> PCIE_APP_INIT_RST_LSB)
#define PCIE_APP_INIT_RST_SET(x) (((x) << PCIE_APP_INIT_RST_LSB) & PCIE_APP_INIT_RST_MASK)
#define PCIE_APP_INIT_RST_RESET 0x0 // 0
#define PCIE_APP_PM_XMT_TURNOFF_MSB 2
#define PCIE_APP_PM_XMT_TURNOFF_LSB 2
#define PCIE_APP_PM_XMT_TURNOFF_MASK 0x00000004
#define PCIE_APP_PM_XMT_TURNOFF_GET(x) (((x) & PCIE_APP_PM_XMT_TURNOFF_MASK) >> PCIE_APP_PM_XMT_TURNOFF_LSB)
#define PCIE_APP_PM_XMT_TURNOFF_SET(x) (((x) << PCIE_APP_PM_XMT_TURNOFF_LSB) & PCIE_APP_PM_XMT_TURNOFF_MASK)
#define PCIE_APP_PM_XMT_TURNOFF_RESET 0x0 // 0
#define PCIE_APP_UNLOCK_MSG_MSB 1
#define PCIE_APP_UNLOCK_MSG_LSB 1
#define PCIE_APP_UNLOCK_MSG_MASK 0x00000002
#define PCIE_APP_UNLOCK_MSG_GET(x) (((x) & PCIE_APP_UNLOCK_MSG_MASK) >> PCIE_APP_UNLOCK_MSG_LSB)
#define PCIE_APP_UNLOCK_MSG_SET(x) (((x) << PCIE_APP_UNLOCK_MSG_LSB) & PCIE_APP_UNLOCK_MSG_MASK)
#define PCIE_APP_UNLOCK_MSG_RESET 0x0 // 0
#define PCIE_APP_LTSSM_ENABLE_MSB 0
#define PCIE_APP_LTSSM_ENABLE_LSB 0
#define PCIE_APP_LTSSM_ENABLE_MASK 0x00000001
#define PCIE_APP_LTSSM_ENABLE_GET(x) (((x) & PCIE_APP_LTSSM_ENABLE_MASK) >> PCIE_APP_LTSSM_ENABLE_LSB)
#define PCIE_APP_LTSSM_ENABLE_SET(x) (((x) << PCIE_APP_LTSSM_ENABLE_LSB) & PCIE_APP_LTSSM_ENABLE_MASK)
#define PCIE_APP_LTSSM_ENABLE_RESET 0x0 // 0
#define PCIE_APP_ADDRESS 0x180f0000
#define XTAL_TCXODET_MSB 31
#define XTAL_TCXODET_LSB 31
#define XTAL_TCXODET_MASK 0x80000000
#define XTAL_TCXODET_GET(x) (((x) & XTAL_TCXODET_MASK) >> XTAL_TCXODET_LSB)
#define XTAL_TCXODET_SET(x) (((x) << XTAL_TCXODET_LSB) & XTAL_TCXODET_MASK)
#define XTAL_TCXODET_RESET 0x0 // 0
#define XTAL_XTAL_CAPINDAC_MSB 30
#define XTAL_XTAL_CAPINDAC_LSB 24
#define XTAL_XTAL_CAPINDAC_MASK 0x7f000000
#define XTAL_XTAL_CAPINDAC_GET(x) (((x) & XTAL_XTAL_CAPINDAC_MASK) >> XTAL_XTAL_CAPINDAC_LSB)
#define XTAL_XTAL_CAPINDAC_SET(x) (((x) << XTAL_XTAL_CAPINDAC_LSB) & XTAL_XTAL_CAPINDAC_MASK)
#define XTAL_XTAL_CAPINDAC_RESET 0x4b // 75
#define XTAL_XTAL_CAPOUTDAC_MSB 23
#define XTAL_XTAL_CAPOUTDAC_LSB 17
#define XTAL_XTAL_CAPOUTDAC_MASK 0x00fe0000
#define XTAL_XTAL_CAPOUTDAC_GET(x) (((x) & XTAL_XTAL_CAPOUTDAC_MASK) >> XTAL_XTAL_CAPOUTDAC_LSB)
#define XTAL_XTAL_CAPOUTDAC_SET(x) (((x) << XTAL_XTAL_CAPOUTDAC_LSB) & XTAL_XTAL_CAPOUTDAC_MASK)
#define XTAL_XTAL_CAPOUTDAC_RESET 0x4b // 75
#define XTAL_XTAL_DRVSTR_MSB 16
#define XTAL_XTAL_DRVSTR_LSB 15
#define XTAL_XTAL_DRVSTR_MASK 0x00018000
#define XTAL_XTAL_DRVSTR_GET(x) (((x) & XTAL_XTAL_DRVSTR_MASK) >> XTAL_XTAL_DRVSTR_LSB)
#define XTAL_XTAL_DRVSTR_SET(x) (((x) << XTAL_XTAL_DRVSTR_LSB) & XTAL_XTAL_DRVSTR_MASK)
#define XTAL_XTAL_DRVSTR_RESET 0x0 // 0
#define XTAL_XTAL_SHORTXIN_MSB 14
#define XTAL_XTAL_SHORTXIN_LSB 14
#define XTAL_XTAL_SHORTXIN_MASK 0x00004000
#define XTAL_XTAL_SHORTXIN_GET(x) (((x) & XTAL_XTAL_SHORTXIN_MASK) >> XTAL_XTAL_SHORTXIN_LSB)
#define XTAL_XTAL_SHORTXIN_SET(x) (((x) << XTAL_XTAL_SHORTXIN_LSB) & XTAL_XTAL_SHORTXIN_MASK)
#define XTAL_XTAL_SHORTXIN_RESET 0x0 // 0
#define XTAL_XTAL_LOCALBIAS_MSB 13
#define XTAL_XTAL_LOCALBIAS_LSB 13
#define XTAL_XTAL_LOCALBIAS_MASK 0x00002000
#define XTAL_XTAL_LOCALBIAS_GET(x) (((x) & XTAL_XTAL_LOCALBIAS_MASK) >> XTAL_XTAL_LOCALBIAS_LSB)
#define XTAL_XTAL_LOCALBIAS_SET(x) (((x) << XTAL_XTAL_LOCALBIAS_LSB) & XTAL_XTAL_LOCALBIAS_MASK)
#define XTAL_XTAL_LOCALBIAS_RESET 0x1 // 1
#define XTAL_XTAL_PWDCLKD_MSB 12
#define XTAL_XTAL_PWDCLKD_LSB 12
#define XTAL_XTAL_PWDCLKD_MASK 0x00001000
#define XTAL_XTAL_PWDCLKD_GET(x) (((x) & XTAL_XTAL_PWDCLKD_MASK) >> XTAL_XTAL_PWDCLKD_LSB)
#define XTAL_XTAL_PWDCLKD_SET(x) (((x) << XTAL_XTAL_PWDCLKD_LSB) & XTAL_XTAL_PWDCLKD_MASK)
#define XTAL_XTAL_PWDCLKD_RESET 0x0 // 0
#define XTAL_XTAL_BIAS2X_MSB 11
#define XTAL_XTAL_BIAS2X_LSB 11
#define XTAL_XTAL_BIAS2X_MASK 0x00000800
#define XTAL_XTAL_BIAS2X_GET(x) (((x) & XTAL_XTAL_BIAS2X_MASK) >> XTAL_XTAL_BIAS2X_LSB)
#define XTAL_XTAL_BIAS2X_SET(x) (((x) << XTAL_XTAL_BIAS2X_LSB) & XTAL_XTAL_BIAS2X_MASK)
#define XTAL_XTAL_BIAS2X_RESET 0x1 // 1
#define XTAL_XTAL_LBIAS2X_MSB 10
#define XTAL_XTAL_LBIAS2X_LSB 10
#define XTAL_XTAL_LBIAS2X_MASK 0x00000400
#define XTAL_XTAL_LBIAS2X_GET(x) (((x) & XTAL_XTAL_LBIAS2X_MASK) >> XTAL_XTAL_LBIAS2X_LSB)
#define XTAL_XTAL_LBIAS2X_SET(x) (((x) << XTAL_XTAL_LBIAS2X_LSB) & XTAL_XTAL_LBIAS2X_MASK)
#define XTAL_XTAL_LBIAS2X_RESET 0x1 // 1
#define XTAL_XTAL_ATBVREG_MSB 9
#define XTAL_XTAL_ATBVREG_LSB 9
#define XTAL_XTAL_ATBVREG_MASK 0x00000200
#define XTAL_XTAL_ATBVREG_GET(x) (((x) & XTAL_XTAL_ATBVREG_MASK) >> XTAL_XTAL_ATBVREG_LSB)
#define XTAL_XTAL_ATBVREG_SET(x) (((x) << XTAL_XTAL_ATBVREG_LSB) & XTAL_XTAL_ATBVREG_MASK)
#define XTAL_XTAL_ATBVREG_RESET 0x0 // 0
#define XTAL_XTAL_OSCON_MSB 8
#define XTAL_XTAL_OSCON_LSB 8
#define XTAL_XTAL_OSCON_MASK 0x00000100
#define XTAL_XTAL_OSCON_GET(x) (((x) & XTAL_XTAL_OSCON_MASK) >> XTAL_XTAL_OSCON_LSB)
#define XTAL_XTAL_OSCON_SET(x) (((x) << XTAL_XTAL_OSCON_LSB) & XTAL_XTAL_OSCON_MASK)
#define XTAL_XTAL_OSCON_RESET 0x1 // 1
#define XTAL_XTAL_PWDCLKIN_MSB 7
#define XTAL_XTAL_PWDCLKIN_LSB 7
#define XTAL_XTAL_PWDCLKIN_MASK 0x00000080
#define XTAL_XTAL_PWDCLKIN_GET(x) (((x) & XTAL_XTAL_PWDCLKIN_MASK) >> XTAL_XTAL_PWDCLKIN_LSB)
#define XTAL_XTAL_PWDCLKIN_SET(x) (((x) << XTAL_XTAL_PWDCLKIN_LSB) & XTAL_XTAL_PWDCLKIN_MASK)
#define XTAL_XTAL_PWDCLKIN_RESET 0x0 // 0
#define XTAL_LOCAL_XTAL_MSB 6
#define XTAL_LOCAL_XTAL_LSB 6
#define XTAL_LOCAL_XTAL_MASK 0x00000040
#define XTAL_LOCAL_XTAL_GET(x) (((x) & XTAL_LOCAL_XTAL_MASK) >> XTAL_LOCAL_XTAL_LSB)
#define XTAL_LOCAL_XTAL_SET(x) (((x) << XTAL_LOCAL_XTAL_LSB) & XTAL_LOCAL_XTAL_MASK)
#define XTAL_LOCAL_XTAL_RESET 0x0 // 0
#define XTAL_PWD_SWREGCLK_MSB 5
#define XTAL_PWD_SWREGCLK_LSB 5
#define XTAL_PWD_SWREGCLK_MASK 0x00000020
#define XTAL_PWD_SWREGCLK_GET(x) (((x) & XTAL_PWD_SWREGCLK_MASK) >> XTAL_PWD_SWREGCLK_LSB)
#define XTAL_PWD_SWREGCLK_SET(x) (((x) << XTAL_PWD_SWREGCLK_LSB) & XTAL_PWD_SWREGCLK_MASK)
#define XTAL_PWD_SWREGCLK_RESET 0x0 // 0
#define XTAL_SWREGCLK_EDGE_SEL_MSB 4
#define XTAL_SWREGCLK_EDGE_SEL_LSB 4
#define XTAL_SWREGCLK_EDGE_SEL_MASK 0x00000010
#define XTAL_SWREGCLK_EDGE_SEL_GET(x) (((x) & XTAL_SWREGCLK_EDGE_SEL_MASK) >> XTAL_SWREGCLK_EDGE_SEL_LSB)
#define XTAL_SWREGCLK_EDGE_SEL_SET(x) (((x) << XTAL_SWREGCLK_EDGE_SEL_LSB) & XTAL_SWREGCLK_EDGE_SEL_MASK)
#define XTAL_SWREGCLK_EDGE_SEL_RESET 0x0 // 0
#define XTAL_SPARE_MSB 3
#define XTAL_SPARE_LSB 0
#define XTAL_SPARE_MASK 0x0000000f
#define XTAL_SPARE_GET(x) (((x) & XTAL_SPARE_MASK) >> XTAL_SPARE_LSB)
#define XTAL_SPARE_SET(x) (((x) << XTAL_SPARE_LSB) & XTAL_SPARE_MASK)
#define XTAL_SPARE_RESET 0xf // 15
#define XTAL_ADDRESS 0x18116290
#define RST_REVISION_ID_ADDRESS 0x18060090
#define is_drqfn() (!(ath_reg_rd(RST_REVISION_ID_ADDRESS) & 0x1000))
#define RST_BOOTSTRAP_BOOT_INTF_SEL_MSB 17
#define RST_BOOTSTRAP_BOOT_INTF_SEL_LSB 16
#define RST_BOOTSTRAP_BOOT_INTF_SEL_MASK 0x00030000
#define RST_BOOTSTRAP_BOOT_INTF_SEL_GET(x) (((x) & RST_BOOTSTRAP_BOOT_INTF_SEL_MASK) >> RST_BOOTSTRAP_BOOT_INTF_SEL_LSB)
#define RST_BOOTSTRAP_BOOT_INTF_SEL_SET(x) (((x) << RST_BOOTSTRAP_BOOT_INTF_SEL_LSB) & RST_BOOTSTRAP_BOOT_INTF_SEL_MASK)
#define RST_BOOTSTRAP_BOOT_INTF_SEL_RESET 0x0 // 0
#define RST_BOOTSTRAP_RES0_MSB 15
#define RST_BOOTSTRAP_RES0_LSB 13
#define RST_BOOTSTRAP_RES0_MASK 0x0000e000
#define RST_BOOTSTRAP_RES0_GET(x) (((x) & RST_BOOTSTRAP_RES0_MASK) >> RST_BOOTSTRAP_RES0_LSB)
#define RST_BOOTSTRAP_RES0_SET(x) (((x) << RST_BOOTSTRAP_RES0_LSB) & RST_BOOTSTRAP_RES0_MASK)
#define RST_BOOTSTRAP_RES0_RESET 0x0 // 0
#define RST_BOOTSTRAP_SW_OPTION2_MSB 12
#define RST_BOOTSTRAP_SW_OPTION2_LSB 12
#define RST_BOOTSTRAP_SW_OPTION2_MASK 0x00001000
#define RST_BOOTSTRAP_SW_OPTION2_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION2_MASK) >> RST_BOOTSTRAP_SW_OPTION2_LSB)
#define RST_BOOTSTRAP_SW_OPTION2_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION2_LSB) & RST_BOOTSTRAP_SW_OPTION2_MASK)
#define RST_BOOTSTRAP_SW_OPTION2_RESET 0x0 // 0
#define RST_BOOTSTRAP_SW_OPTION1_MSB 11
#define RST_BOOTSTRAP_SW_OPTION1_LSB 11
#define RST_BOOTSTRAP_SW_OPTION1_MASK 0x00000800
#define RST_BOOTSTRAP_SW_OPTION1_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION1_MASK) >> RST_BOOTSTRAP_SW_OPTION1_LSB)
#define RST_BOOTSTRAP_SW_OPTION1_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION1_LSB) & RST_BOOTSTRAP_SW_OPTION1_MASK)
#define RST_BOOTSTRAP_SW_OPTION1_RESET 0x0 // 0
#define RST_BOOTSTRAP_TESTROM_DISABLE_MSB 10
#define RST_BOOTSTRAP_TESTROM_DISABLE_LSB 10
#define RST_BOOTSTRAP_TESTROM_DISABLE_MASK 0x00000400
#define RST_BOOTSTRAP_TESTROM_DISABLE_GET(x) (((x) & RST_BOOTSTRAP_TESTROM_DISABLE_MASK) >> RST_BOOTSTRAP_TESTROM_DISABLE_LSB)
#define RST_BOOTSTRAP_TESTROM_DISABLE_SET(x) (((x) << RST_BOOTSTRAP_TESTROM_DISABLE_LSB) & RST_BOOTSTRAP_TESTROM_DISABLE_MASK)
#define RST_BOOTSTRAP_TESTROM_DISABLE_RESET 0x1 // 1
#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_MSB 9
#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_LSB 9
#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_MASK 0x00000200
#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_GET(x) (((x) & RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_MASK) >> RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_LSB)
#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_SET(x) (((x) << RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_LSB) & RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_MASK)
#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_RESET 0x0 // 0
#define RST_BOOTSTRAP_SRIF_ENABLE_MSB 8
#define RST_BOOTSTRAP_SRIF_ENABLE_LSB 8
#define RST_BOOTSTRAP_SRIF_ENABLE_MASK 0x00000100
#define RST_BOOTSTRAP_SRIF_ENABLE_GET(x) (((x) & RST_BOOTSTRAP_SRIF_ENABLE_MASK) >> RST_BOOTSTRAP_SRIF_ENABLE_LSB)
#define RST_BOOTSTRAP_SRIF_ENABLE_SET(x) (((x) << RST_BOOTSTRAP_SRIF_ENABLE_LSB) & RST_BOOTSTRAP_SRIF_ENABLE_MASK)
#define RST_BOOTSTRAP_SRIF_ENABLE_RESET 0x0 // 0
#define RST_BOOTSTRAP_USB_MODE_MSB 7
#define RST_BOOTSTRAP_USB_MODE_LSB 7
#define RST_BOOTSTRAP_USB_MODE_MASK 0x00000080
#define RST_BOOTSTRAP_USB_MODE_GET(x) (((x) & RST_BOOTSTRAP_USB_MODE_MASK) >> RST_BOOTSTRAP_USB_MODE_LSB)
#define RST_BOOTSTRAP_USB_MODE_SET(x) (((x) << RST_BOOTSTRAP_USB_MODE_LSB) & RST_BOOTSTRAP_USB_MODE_MASK)
#define RST_BOOTSTRAP_USB_MODE_RESET 0x0 // 0
#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MSB 6
#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_LSB 6
#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK 0x00000040
#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_GET(x) (((x) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK) >> RST_BOOTSTRAP_PCIE_RC_EP_SELECT_LSB)
#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_SET(x) (((x) << RST_BOOTSTRAP_PCIE_RC_EP_SELECT_LSB) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)
#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_RESET 0x0 // 0
#define RST_BOOTSTRAP_JTAG_MODE_MSB 5
#define RST_BOOTSTRAP_JTAG_MODE_LSB 5
#define RST_BOOTSTRAP_JTAG_MODE_MASK 0x00000020
#define RST_BOOTSTRAP_JTAG_MODE_GET(x) (((x) & RST_BOOTSTRAP_JTAG_MODE_MASK) >> RST_BOOTSTRAP_JTAG_MODE_LSB)
#define RST_BOOTSTRAP_JTAG_MODE_SET(x) (((x) << RST_BOOTSTRAP_JTAG_MODE_LSB) & RST_BOOTSTRAP_JTAG_MODE_MASK)
#define RST_BOOTSTRAP_JTAG_MODE_RESET 0x1 // 1
#define RST_BOOTSTRAP_REF_CLK_MSB 4
#define RST_BOOTSTRAP_REF_CLK_LSB 4
#define RST_BOOTSTRAP_REF_CLK_MASK 0x00000010
#define RST_BOOTSTRAP_REF_CLK_GET(x) (((x) & RST_BOOTSTRAP_REF_CLK_MASK) >> RST_BOOTSTRAP_REF_CLK_LSB)
#define RST_BOOTSTRAP_REF_CLK_SET(x) (((x) << RST_BOOTSTRAP_REF_CLK_LSB) & RST_BOOTSTRAP_REF_CLK_MASK)
#define RST_BOOTSTRAP_REF_CLK_RESET 0x0 // 0
#define RST_BOOTSTRAP_DDR_WIDTH_MSB 3
#define RST_BOOTSTRAP_DDR_WIDTH_LSB 3
#define RST_BOOTSTRAP_DDR_WIDTH_MASK 0x00000008
#define RST_BOOTSTRAP_DDR_WIDTH_GET(x) (((x) & RST_BOOTSTRAP_DDR_WIDTH_MASK) >> RST_BOOTSTRAP_DDR_WIDTH_LSB)
#define RST_BOOTSTRAP_DDR_WIDTH_SET(x) (((x) << RST_BOOTSTRAP_DDR_WIDTH_LSB) & RST_BOOTSTRAP_DDR_WIDTH_MASK)
#define RST_BOOTSTRAP_DDR_WIDTH_RESET 0x0 // 0
#define RST_BOOTSTRAP_BOOT_SELECT_MSB 2
#define RST_BOOTSTRAP_BOOT_SELECT_LSB 2
#define RST_BOOTSTRAP_BOOT_SELECT_MASK 0x00000004
#define RST_BOOTSTRAP_BOOT_SELECT_GET(x) (((x) & RST_BOOTSTRAP_BOOT_SELECT_MASK) >> RST_BOOTSTRAP_BOOT_SELECT_LSB)
#define RST_BOOTSTRAP_BOOT_SELECT_SET(x) (((x) << RST_BOOTSTRAP_BOOT_SELECT_LSB) & RST_BOOTSTRAP_BOOT_SELECT_MASK)
#define RST_BOOTSTRAP_BOOT_SELECT_RESET 0x0 // 0
#define RST_BOOTSTRAP_SDRAM_DISABLE_MSB 1
#define RST_BOOTSTRAP_SDRAM_DISABLE_LSB 1
#define RST_BOOTSTRAP_SDRAM_DISABLE_MASK 0x00000002
#define RST_BOOTSTRAP_SDRAM_DISABLE_GET(x) (((x) & RST_BOOTSTRAP_SDRAM_DISABLE_MASK) >> RST_BOOTSTRAP_SDRAM_DISABLE_LSB)
#define RST_BOOTSTRAP_SDRAM_DISABLE_SET(x) (((x) << RST_BOOTSTRAP_SDRAM_DISABLE_LSB) & RST_BOOTSTRAP_SDRAM_DISABLE_MASK)
#define RST_BOOTSTRAP_SDRAM_DISABLE_RESET 0x0 // 0
#define RST_BOOTSTRAP_DDR_SELECT_MSB 0
#define RST_BOOTSTRAP_DDR_SELECT_LSB 0
#define RST_BOOTSTRAP_DDR_SELECT_MASK 0x00000001
#define RST_BOOTSTRAP_DDR_SELECT_GET(x) (((x) & RST_BOOTSTRAP_DDR_SELECT_MASK) >> RST_BOOTSTRAP_DDR_SELECT_LSB)
#define RST_BOOTSTRAP_DDR_SELECT_SET(x) (((x) << RST_BOOTSTRAP_DDR_SELECT_LSB) & RST_BOOTSTRAP_DDR_SELECT_MASK)
#define RST_BOOTSTRAP_DDR_SELECT_RESET 0x0 // 0
#define RST_BOOTSTRAP_ADDRESS 0x180600b0
#define GPIO_OE_ADDRESS 0x18040000
#define GPIO_OUT_ADDRESS 0x18040008
#define GPIO_SPARE_ADDRESS 0x18040028
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MSB 31
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB 24
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK 0xff000000
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_RESET 0xb // 11
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MSB 23
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB 16
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK 0x00ff0000
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_RESET 0xa // 10
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MSB 15
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB 8
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK 0x0000ff00
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_RESET 0x9 // 9
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MSB 7
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB 0
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK 0x000000ff
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_RESET 0x14 // 20
#define GPIO_OUT_FUNCTION1_ADDRESS 0x18040030
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MSB 31
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB 24
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK 0xff000000
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_RESET 0x0 // 0
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MSB 23
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB 16
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK 0x00ff0000
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_RESET 0x0 // 0
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MSB 15
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB 8
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK 0x0000ff00
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_RESET 0x0 // 0
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MSB 7
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB 0
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK 0x000000ff
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_RESET 0x0 // 0
#define GPIO_OUT_FUNCTION2_ADDRESS 0x18040034
#define GPIO_IN_ENABLE0_UART_SIN_MSB 15
#define GPIO_IN_ENABLE0_UART_SIN_LSB 8
#define GPIO_IN_ENABLE0_UART_SIN_MASK 0x0000ff00
#define GPIO_IN_ENABLE0_UART_SIN_GET(x) (((x) & GPIO_IN_ENABLE0_UART_SIN_MASK) >> GPIO_IN_ENABLE0_UART_SIN_LSB)
#define GPIO_IN_ENABLE0_UART_SIN_SET(x) (((x) << GPIO_IN_ENABLE0_UART_SIN_LSB) & GPIO_IN_ENABLE0_UART_SIN_MASK)
#define GPIO_IN_ENABLE0_UART_SIN_RESET 0x0 // 0
#define GPIO_IN_ENABLE0_SPI_DATA_IN_MSB 7
#define GPIO_IN_ENABLE0_SPI_DATA_IN_LSB 0
#define GPIO_IN_ENABLE0_SPI_DATA_IN_MASK 0x000000ff
#define GPIO_IN_ENABLE0_SPI_DATA_IN_GET(x) (((x) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK) >> GPIO_IN_ENABLE0_SPI_DATA_IN_LSB)
#define GPIO_IN_ENABLE0_SPI_DATA_IN_SET(x) (((x) << GPIO_IN_ENABLE0_SPI_DATA_IN_LSB) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK)
#define GPIO_IN_ENABLE0_SPI_DATA_IN_RESET 0x8 // 8
#define GPIO_IN_ENABLE0_ADDRESS 0x18040044
#define GPIO_IN_ENABLE3_MII_GE1_MDI_MSB 23
#define GPIO_IN_ENABLE3_MII_GE1_MDI_LSB 16
#define GPIO_IN_ENABLE3_MII_GE1_MDI_MASK 0x00ff0000
#define GPIO_IN_ENABLE3_MII_GE1_MDI_GET(x) (((x) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK) >> GPIO_IN_ENABLE3_MII_GE1_MDI_LSB)
#define GPIO_IN_ENABLE3_MII_GE1_MDI_SET(x) (((x) << GPIO_IN_ENABLE3_MII_GE1_MDI_LSB) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK)
#define GPIO_IN_ENABLE3_MII_GE1_MDI_RESET 0x80 // 128
#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_MSB 15
#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_LSB 8
#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_MASK 0x0000ff00
#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_GET(x) (((x) & GPIO_IN_ENABLE3_BOOT_EXT_MDC_MASK) >> GPIO_IN_ENABLE3_BOOT_EXT_MDC_LSB)
#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_SET(x) (((x) << GPIO_IN_ENABLE3_BOOT_EXT_MDC_LSB) & GPIO_IN_ENABLE3_BOOT_EXT_MDC_MASK)