blob: c293ae54022b69ba8162a6bd3f11550a10d96371 [file] [log] [blame]
/*
* Copyright (c) 2013 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _QCA953X_H
#define _QCA953X_H
#ifndef __ASSEMBLY__
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <linux/types.h>
#endif /* __ASSEMBLY__ */
#undef is_qca953x
#undef is_hb
#define is_qca953x() (1)
#define is_hb() (1)
#define CPU_PLL_CONFIG_UPDATING_MSB 31
#define CPU_PLL_CONFIG_UPDATING_LSB 31
#define CPU_PLL_CONFIG_UPDATING_MASK 0x80000000
#define CPU_PLL_CONFIG_UPDATING_GET(x) (((x) & CPU_PLL_CONFIG_UPDATING_MASK) >> CPU_PLL_CONFIG_UPDATING_LSB)
#define CPU_PLL_CONFIG_UPDATING_SET(x) (((x) << CPU_PLL_CONFIG_UPDATING_LSB) & CPU_PLL_CONFIG_UPDATING_MASK)
#define CPU_PLL_CONFIG_UPDATING_RESET 0x1 // 1
#define CPU_PLL_CONFIG_PLLPWD_MSB 30
#define CPU_PLL_CONFIG_PLLPWD_LSB 30
#define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000
#define CPU_PLL_CONFIG_PLLPWD_GET(x) (((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB)
#define CPU_PLL_CONFIG_PLLPWD_SET(x) (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
#define CPU_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
#define CPU_PLL_CONFIG_SPARE_MSB 29
#define CPU_PLL_CONFIG_SPARE_LSB 22
#define CPU_PLL_CONFIG_SPARE_MASK 0x3fc00000
#define CPU_PLL_CONFIG_SPARE_GET(x) (((x) & CPU_PLL_CONFIG_SPARE_MASK) >> CPU_PLL_CONFIG_SPARE_LSB)
#define CPU_PLL_CONFIG_SPARE_SET(x) (((x) << CPU_PLL_CONFIG_SPARE_LSB) & CPU_PLL_CONFIG_SPARE_MASK)
#define CPU_PLL_CONFIG_SPARE_RESET 0x0 // 0
#define CPU_PLL_CONFIG_OUTDIV_MSB 21
#define CPU_PLL_CONFIG_OUTDIV_LSB 19
#define CPU_PLL_CONFIG_OUTDIV_MASK 0x00380000
#define CPU_PLL_CONFIG_OUTDIV_GET(x) (((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB)
#define CPU_PLL_CONFIG_OUTDIV_SET(x) (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK)
#define CPU_PLL_CONFIG_OUTDIV_RESET 0x0 // 0
#define CPU_PLL_CONFIG_RANGE_MSB 18
#define CPU_PLL_CONFIG_RANGE_LSB 17
#define CPU_PLL_CONFIG_RANGE_MASK 0x00060000
#define CPU_PLL_CONFIG_RANGE_GET(x) (((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB)
#define CPU_PLL_CONFIG_RANGE_SET(x) (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK)
#define CPU_PLL_CONFIG_RANGE_RESET 0x3 // 3
#define CPU_PLL_CONFIG_REFDIV_MSB 16
#define CPU_PLL_CONFIG_REFDIV_LSB 12
#define CPU_PLL_CONFIG_REFDIV_MASK 0x0001f000
#define CPU_PLL_CONFIG_REFDIV_GET(x) (((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB)
#define CPU_PLL_CONFIG_REFDIV_SET(x) (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK)
#define CPU_PLL_CONFIG_REFDIV_RESET 0x2 // 2
#define CPU_PLL_CONFIG_NINT_MSB 11
#define CPU_PLL_CONFIG_NINT_LSB 6
#define CPU_PLL_CONFIG_NINT_MASK 0x00000fc0
#define CPU_PLL_CONFIG_NINT_GET(x) (((x) & CPU_PLL_CONFIG_NINT_MASK) >> CPU_PLL_CONFIG_NINT_LSB)
#define CPU_PLL_CONFIG_NINT_SET(x) (((x) << CPU_PLL_CONFIG_NINT_LSB) & CPU_PLL_CONFIG_NINT_MASK)
#define CPU_PLL_CONFIG_NINT_RESET 0x14 // 20
#define CPU_PLL_CONFIG_NFRAC_MSB 5
#define CPU_PLL_CONFIG_NFRAC_LSB 0
#define CPU_PLL_CONFIG_NFRAC_MASK 0x0000003f
#define CPU_PLL_CONFIG_NFRAC_GET(x) (((x) & CPU_PLL_CONFIG_NFRAC_MASK) >> CPU_PLL_CONFIG_NFRAC_LSB)
#define CPU_PLL_CONFIG_NFRAC_SET(x) (((x) << CPU_PLL_CONFIG_NFRAC_LSB) & CPU_PLL_CONFIG_NFRAC_MASK)
#define CPU_PLL_CONFIG_NFRAC_RESET 0x10 // 16
#define CPU_PLL_CONFIG_ADDRESS 0x18050000
#define DDR_PLL_CONFIG_UPDATING_MSB 31
#define DDR_PLL_CONFIG_UPDATING_LSB 31
#define DDR_PLL_CONFIG_UPDATING_MASK 0x80000000
#define DDR_PLL_CONFIG_UPDATING_GET(x) (((x) & DDR_PLL_CONFIG_UPDATING_MASK) >> DDR_PLL_CONFIG_UPDATING_LSB)
#define DDR_PLL_CONFIG_UPDATING_SET(x) (((x) << DDR_PLL_CONFIG_UPDATING_LSB) & DDR_PLL_CONFIG_UPDATING_MASK)
#define DDR_PLL_CONFIG_UPDATING_RESET 0x1 // 1
#define DDR_PLL_CONFIG_PLLPWD_MSB 30
#define DDR_PLL_CONFIG_PLLPWD_LSB 30
#define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000
#define DDR_PLL_CONFIG_PLLPWD_GET(x) (((x) & DDR_PLL_CONFIG_PLLPWD_MASK) >> DDR_PLL_CONFIG_PLLPWD_LSB)
#define DDR_PLL_CONFIG_PLLPWD_SET(x) (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
#define DDR_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
#define DDR_PLL_CONFIG_SPARE_MSB 29
#define DDR_PLL_CONFIG_SPARE_LSB 26
#define DDR_PLL_CONFIG_SPARE_MASK 0x3c000000
#define DDR_PLL_CONFIG_SPARE_GET(x) (((x) & DDR_PLL_CONFIG_SPARE_MASK) >> DDR_PLL_CONFIG_SPARE_LSB)
#define DDR_PLL_CONFIG_SPARE_SET(x) (((x) << DDR_PLL_CONFIG_SPARE_LSB) & DDR_PLL_CONFIG_SPARE_MASK)
#define DDR_PLL_CONFIG_SPARE_RESET 0x0 // 0
#define DDR_PLL_CONFIG_OUTDIV_MSB 25
#define DDR_PLL_CONFIG_OUTDIV_LSB 23
#define DDR_PLL_CONFIG_OUTDIV_MASK 0x03800000
#define DDR_PLL_CONFIG_OUTDIV_GET(x) (((x) & DDR_PLL_CONFIG_OUTDIV_MASK) >> DDR_PLL_CONFIG_OUTDIV_LSB)
#define DDR_PLL_CONFIG_OUTDIV_SET(x) (((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK)
#define DDR_PLL_CONFIG_OUTDIV_RESET 0x0 // 0
#define DDR_PLL_CONFIG_RANGE_MSB 22
#define DDR_PLL_CONFIG_RANGE_LSB 21
#define DDR_PLL_CONFIG_RANGE_MASK 0x00600000
#define DDR_PLL_CONFIG_RANGE_GET(x) (((x) & DDR_PLL_CONFIG_RANGE_MASK) >> DDR_PLL_CONFIG_RANGE_LSB)
#define DDR_PLL_CONFIG_RANGE_SET(x) (((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK)
#define DDR_PLL_CONFIG_RANGE_RESET 0x3 // 3
#define DDR_PLL_CONFIG_REFDIV_MSB 20
#define DDR_PLL_CONFIG_REFDIV_LSB 16
#define DDR_PLL_CONFIG_REFDIV_MASK 0x001f0000
#define DDR_PLL_CONFIG_REFDIV_GET(x) (((x) & DDR_PLL_CONFIG_REFDIV_MASK) >> DDR_PLL_CONFIG_REFDIV_LSB)
#define DDR_PLL_CONFIG_REFDIV_SET(x) (((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK)
#define DDR_PLL_CONFIG_REFDIV_RESET 0x2 // 2
#define DDR_PLL_CONFIG_NINT_MSB 15
#define DDR_PLL_CONFIG_NINT_LSB 10
#define DDR_PLL_CONFIG_NINT_MASK 0x0000fc00
#define DDR_PLL_CONFIG_NINT_GET(x) (((x) & DDR_PLL_CONFIG_NINT_MASK) >> DDR_PLL_CONFIG_NINT_LSB)
#define DDR_PLL_CONFIG_NINT_SET(x) (((x) << DDR_PLL_CONFIG_NINT_LSB) & DDR_PLL_CONFIG_NINT_MASK)
#define DDR_PLL_CONFIG_NINT_RESET 0x14 // 20
#define DDR_PLL_CONFIG_NFRAC_MSB 9
#define DDR_PLL_CONFIG_NFRAC_LSB 0
#define DDR_PLL_CONFIG_NFRAC_MASK 0x000003ff
#define DDR_PLL_CONFIG_NFRAC_GET(x) (((x) & DDR_PLL_CONFIG_NFRAC_MASK) >> DDR_PLL_CONFIG_NFRAC_LSB)
#define DDR_PLL_CONFIG_NFRAC_SET(x) (((x) << DDR_PLL_CONFIG_NFRAC_LSB) & DDR_PLL_CONFIG_NFRAC_MASK)
#define DDR_PLL_CONFIG_NFRAC_RESET 0x200 // 512
#define DDR_PLL_CONFIG_ADDRESS 0x18050004
#define DDR_CTL_CONFIG_SRAM_TSEL_MSB 31
#define DDR_CTL_CONFIG_SRAM_TSEL_LSB 30
#define DDR_CTL_CONFIG_SRAM_TSEL_MASK 0xc0000000
#define DDR_CTL_CONFIG_SRAM_TSEL_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) >> DDR_CTL_CONFIG_SRAM_TSEL_LSB)
#define DDR_CTL_CONFIG_SRAM_TSEL_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK)
#define DDR_CTL_CONFIG_SRAM_TSEL_RESET 0x1 // 1
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MSB 29
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB 21
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK 0x3fe00000
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_GET(x) (((x) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) >> DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB)
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_SET(x) (((x) << DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK)
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_RESET 0x0 // 0
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MSB 20
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB 20
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK 0x00100000
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_RESET 0x1 // 1
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MSB 19
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB 19
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK 0x00080000
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_RESET 0x1 // 1
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MSB 18
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB 18
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK 0x00040000
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_RESET 0x1 // 1
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MSB 17
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB 17
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK 0x00020000
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_RESET 0x1 // 1
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MSB 16
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB 16
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK 0x00010000
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_RESET 0x1 // 1
#define DDR_CTL_CONFIG_SPARE_MSB 13
#define DDR_CTL_CONFIG_SPARE_LSB 7
#define DDR_CTL_CONFIG_SPARE_MASK 0x00003f80
#define DDR_CTL_CONFIG_SPARE_GET(x) (((x) & DDR_CTL_CONFIG_SPARE_MASK) >> DDR_CTL_CONFIG_SPARE_LSB)
#define DDR_CTL_CONFIG_SPARE_SET(x) (((x) << DDR_CTL_CONFIG_SPARE_LSB) & DDR_CTL_CONFIG_SPARE_MASK)
#define DDR_CTL_CONFIG_SPARE_RESET 0x0 // 0
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MSB 6
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB 6
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK 0x00000040
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_GET(x) (((x) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK) >> DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB)
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(x) (((x) << DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK)
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_RESET 0x0 // 0
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_MSB 4
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB 4
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK 0x00000010
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_GET(x) (((x) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK) >> DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB)
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_SET(x) (((x) << DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK)
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_RESET 0x0 // 0
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_MSB 3
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB 3
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK 0x00000008
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK) >> DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB)
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK)
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_RESET 0x0 // 0
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MSB 2
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB 2
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK 0x00000004
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK) >> DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB)
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK)
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_RESET 0x0 // 0
#define DDR_CTL_CONFIG_HALF_WIDTH_MSB 1
#define DDR_CTL_CONFIG_HALF_WIDTH_LSB 1
#define DDR_CTL_CONFIG_HALF_WIDTH_MASK 0x00000002
#define DDR_CTL_CONFIG_HALF_WIDTH_GET(x) (((x) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) >> DDR_CTL_CONFIG_HALF_WIDTH_LSB)
#define DDR_CTL_CONFIG_HALF_WIDTH_SET(x) (((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & DDR_CTL_CONFIG_HALF_WIDTH_MASK)
#define DDR_CTL_CONFIG_HALF_WIDTH_RESET 0x1 // 1
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_MSB 0
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB 0
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK 0x00000001
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_GET(x) (((x) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK) >> DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB)
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_SET(x) (((x) << DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK)
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_RESET 0x0 // 0
#define DDR_CTL_CONFIG_ADDRESS 0x18000108
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MSB 31
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB 31
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK 0x80000000
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_GET(x) (((x) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK) >> DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB)
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_SET(x) (((x) << DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK)
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MSB 30
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB 30
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK 0x40000000
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_GET(x) (((x) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK) >> DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB)
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_SET(x) (((x) << DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK)
#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_MSB 29
#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB 29
#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK 0x20000000
#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_GET(x) (((x) & DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK) >> DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB)
#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_SET(x) (((x) << DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB) & DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK)
#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MSB 28
#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB 28
#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK 0x10000000
#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_GET(x) (((x) & DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK) >> DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB)
#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_SET(x) (((x) << DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB) & DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK)
#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_RESET 0x1 // 1
#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MSB 27
#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB 27
#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK 0x08000000
#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_GET(x) (((x) & DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK) >> DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB)
#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_SET(x) (((x) << DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB) & DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK)
#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MSB 16
#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB 16
#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK 0x00010000
#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB)
#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB) & DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK)
#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MSB 15
#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB 15
#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK 0x00008000
#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK) >> DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB)
#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB) & DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK)
#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MSB 14
#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB 13
#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK 0x00006000
#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK) >> DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB)
#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB) & DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK)
#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_GATE_TAP_MSB 12
#define DDR_DEBUG_RD_CNTL_GATE_TAP_LSB 8
#define DDR_DEBUG_RD_CNTL_GATE_TAP_MASK 0x00001f00
#define DDR_DEBUG_RD_CNTL_GATE_TAP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_TAP_MASK) >> DDR_DEBUG_RD_CNTL_GATE_TAP_LSB)
#define DDR_DEBUG_RD_CNTL_GATE_TAP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_TAP_LSB) & DDR_DEBUG_RD_CNTL_GATE_TAP_MASK)
#define DDR_DEBUG_RD_CNTL_GATE_TAP_RESET 0x1 // 1
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MSB 6
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB 5
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK 0x00000060
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB)
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB) & DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK)
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_RESET 0x0 // 0
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_MSB 4
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB 0
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK 0x0000001f
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB)
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB) & DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK)
#define DDR_DEBUG_RD_CNTL_CK_P_TAP_RESET 0x1 // 1
#define DDR_DEBUG_RD_CNTL_ADDRESS 0x18000118
#define DDR2_CONFIG_DDR2_TWL_MSB 13
#define DDR2_CONFIG_DDR2_TWL_LSB 10
#define DDR2_CONFIG_DDR2_TWL_MASK 0x00003c00
#define DDR2_CONFIG_DDR2_TWL_GET(x) (((x) & DDR2_CONFIG_DDR2_TWL_MASK) >> DDR2_CONFIG_DDR2_TWL_LSB)
#define DDR2_CONFIG_DDR2_TWL_SET(x) (((x) << DDR2_CONFIG_DDR2_TWL_LSB) & DDR2_CONFIG_DDR2_TWL_MASK)
#define DDR2_CONFIG_DDR2_TWL_RESET 0x1 // 1
#define DDR2_CONFIG_DDR2_ODT_MSB 9
#define DDR2_CONFIG_DDR2_ODT_LSB 9
#define DDR2_CONFIG_DDR2_ODT_MASK 0x00000200
#define DDR2_CONFIG_DDR2_ODT_GET(x) (((x) & DDR2_CONFIG_DDR2_ODT_MASK) >> DDR2_CONFIG_DDR2_ODT_LSB)
#define DDR2_CONFIG_DDR2_ODT_SET(x) (((x) << DDR2_CONFIG_DDR2_ODT_LSB) & DDR2_CONFIG_DDR2_ODT_MASK)
#define DDR2_CONFIG_DDR2_ODT_RESET 0x1 // 1
#define DDR2_CONFIG_TFAW_MSB 7
#define DDR2_CONFIG_TFAW_LSB 2
#define DDR2_CONFIG_TFAW_MASK 0x000000fc
#define DDR2_CONFIG_TFAW_GET(x) (((x) & DDR2_CONFIG_TFAW_MASK) >> DDR2_CONFIG_TFAW_LSB)
#define DDR2_CONFIG_TFAW_SET(x) (((x) << DDR2_CONFIG_TFAW_LSB) & DDR2_CONFIG_TFAW_MASK)
#define DDR2_CONFIG_TFAW_RESET 0x16 // 22
#define DDR2_CONFIG_ENABLE_DDR2_MSB 0
#define DDR2_CONFIG_ENABLE_DDR2_LSB 0
#define DDR2_CONFIG_ENABLE_DDR2_MASK 0x00000001
#define DDR2_CONFIG_ENABLE_DDR2_GET(x) (((x) & DDR2_CONFIG_ENABLE_DDR2_MASK) >> DDR2_CONFIG_ENABLE_DDR2_LSB)
#define DDR2_CONFIG_ENABLE_DDR2_SET(x) (((x) << DDR2_CONFIG_ENABLE_DDR2_LSB) & DDR2_CONFIG_ENABLE_DDR2_MASK)
#define DDR2_CONFIG_ENABLE_DDR2_RESET 0x0 // 0
#define DDR2_CONFIG_ADDRESS 0x180000b8
#define DDR_CONTROL_EMR3S_MSB 5
#define DDR_CONTROL_EMR3S_LSB 5
#define DDR_CONTROL_EMR3S_MASK 0x00000020
#define DDR_CONTROL_EMR3S_GET(x) (((x) & DDR_CONTROL_EMR3S_MASK) >> DDR_CONTROL_EMR3S_LSB)
#define DDR_CONTROL_EMR3S_SET(x) (((x) << DDR_CONTROL_EMR3S_LSB) & DDR_CONTROL_EMR3S_MASK)
#define DDR_CONTROL_EMR3S_RESET 0x0 // 0
#define DDR_CONTROL_EMR2S_MSB 4
#define DDR_CONTROL_EMR2S_LSB 4
#define DDR_CONTROL_EMR2S_MASK 0x00000010
#define DDR_CONTROL_EMR2S_GET(x) (((x) & DDR_CONTROL_EMR2S_MASK) >> DDR_CONTROL_EMR2S_LSB)
#define DDR_CONTROL_EMR2S_SET(x) (((x) << DDR_CONTROL_EMR2S_LSB) & DDR_CONTROL_EMR2S_MASK)
#define DDR_CONTROL_EMR2S_RESET 0x0 // 0
#define DDR_CONTROL_PREA_MSB 3
#define DDR_CONTROL_PREA_LSB 3
#define DDR_CONTROL_PREA_MASK 0x00000008
#define DDR_CONTROL_PREA_GET(x) (((x) & DDR_CONTROL_PREA_MASK) >> DDR_CONTROL_PREA_LSB)
#define DDR_CONTROL_PREA_SET(x) (((x) << DDR_CONTROL_PREA_LSB) & DDR_CONTROL_PREA_MASK)
#define DDR_CONTROL_PREA_RESET 0x0 // 0
#define DDR_CONTROL_REF_MSB 2
#define DDR_CONTROL_REF_LSB 2
#define DDR_CONTROL_REF_MASK 0x00000004
#define DDR_CONTROL_REF_GET(x) (((x) & DDR_CONTROL_REF_MASK) >> DDR_CONTROL_REF_LSB)
#define DDR_CONTROL_REF_SET(x) (((x) << DDR_CONTROL_REF_LSB) & DDR_CONTROL_REF_MASK)
#define DDR_CONTROL_REF_RESET 0x0 // 0
#define DDR_CONTROL_EMRS_MSB 1
#define DDR_CONTROL_EMRS_LSB 1
#define DDR_CONTROL_EMRS_MASK 0x00000002
#define DDR_CONTROL_EMRS_GET(x) (((x) & DDR_CONTROL_EMRS_MASK) >> DDR_CONTROL_EMRS_LSB)
#define DDR_CONTROL_EMRS_SET(x) (((x) << DDR_CONTROL_EMRS_LSB) & DDR_CONTROL_EMRS_MASK)
#define DDR_CONTROL_EMRS_RESET 0x0 // 0
#define DDR_CONTROL_MRS_MSB 0
#define DDR_CONTROL_MRS_LSB 0
#define DDR_CONTROL_MRS_MASK 0x00000001
#define DDR_CONTROL_MRS_GET(x) (((x) & DDR_CONTROL_MRS_MASK) >> DDR_CONTROL_MRS_LSB)
#define DDR_CONTROL_MRS_SET(x) (((x) << DDR_CONTROL_MRS_LSB) & DDR_CONTROL_MRS_MASK)
#define DDR_CONTROL_MRS_RESET 0x0 // 0
#define DDR_CONTROL_ADDRESS 0x18000010
#define DDR_CONFIG_CAS_LATENCY_MSB_MSB 31
#define DDR_CONFIG_CAS_LATENCY_MSB_LSB 31
#define DDR_CONFIG_CAS_LATENCY_MSB_MASK 0x80000000
#define DDR_CONFIG_CAS_LATENCY_MSB_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) >> DDR_CONFIG_CAS_LATENCY_MSB_LSB)
#define DDR_CONFIG_CAS_LATENCY_MSB_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & DDR_CONFIG_CAS_LATENCY_MSB_MASK)
#define DDR_CONFIG_CAS_LATENCY_MSB_RESET 0x0 // 0
#define DDR_CONFIG_OPEN_PAGE_MSB 30
#define DDR_CONFIG_OPEN_PAGE_LSB 30
#define DDR_CONFIG_OPEN_PAGE_MASK 0x40000000
#define DDR_CONFIG_OPEN_PAGE_GET(x) (((x) & DDR_CONFIG_OPEN_PAGE_MASK) >> DDR_CONFIG_OPEN_PAGE_LSB)
#define DDR_CONFIG_OPEN_PAGE_SET(x) (((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK)
#define DDR_CONFIG_OPEN_PAGE_RESET 0x1 // 1
#define DDR_CONFIG_CAS_LATENCY_MSB 29
#define DDR_CONFIG_CAS_LATENCY_LSB 27
#define DDR_CONFIG_CAS_LATENCY_MASK 0x38000000
#define DDR_CONFIG_CAS_LATENCY_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MASK) >> DDR_CONFIG_CAS_LATENCY_LSB)
#define DDR_CONFIG_CAS_LATENCY_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK)
#define DDR_CONFIG_CAS_LATENCY_RESET 0x6 // 6
#define DDR_CONFIG_TMRD_MSB 26
#define DDR_CONFIG_TMRD_LSB 23
#define DDR_CONFIG_TMRD_MASK 0x07800000
#define DDR_CONFIG_TMRD_GET(x) (((x) & DDR_CONFIG_TMRD_MASK) >> DDR_CONFIG_TMRD_LSB)
#define DDR_CONFIG_TMRD_SET(x) (((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK)
#define DDR_CONFIG_TMRD_RESET 0xf // 15
#define DDR_CONFIG_TRFC_MSB 22
#define DDR_CONFIG_TRFC_LSB 17
#define DDR_CONFIG_TRFC_MASK 0x007e0000
#define DDR_CONFIG_TRFC_GET(x) (((x) & DDR_CONFIG_TRFC_MASK) >> DDR_CONFIG_TRFC_LSB)
#define DDR_CONFIG_TRFC_SET(x) (((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK)
#define DDR_CONFIG_TRFC_RESET 0x24 // 36
#define DDR_CONFIG_TRRD_MSB 16
#define DDR_CONFIG_TRRD_LSB 13
#define DDR_CONFIG_TRRD_MASK 0x0001e000
#define DDR_CONFIG_TRRD_GET(x) (((x) & DDR_CONFIG_TRRD_MASK) >> DDR_CONFIG_TRRD_LSB)
#define DDR_CONFIG_TRRD_SET(x) (((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK)
#define DDR_CONFIG_TRRD_RESET 0x4 // 4
#define DDR_CONFIG_TRP_MSB 12
#define DDR_CONFIG_TRP_LSB 9
#define DDR_CONFIG_TRP_MASK 0x00001e00
#define DDR_CONFIG_TRP_GET(x) (((x) & DDR_CONFIG_TRP_MASK) >> DDR_CONFIG_TRP_LSB)
#define DDR_CONFIG_TRP_SET(x) (((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK)
#define DDR_CONFIG_TRP_RESET 0x6 // 6
#define DDR_CONFIG_TRCD_MSB 8
#define DDR_CONFIG_TRCD_LSB 5
#define DDR_CONFIG_TRCD_MASK 0x000001e0
#define DDR_CONFIG_TRCD_GET(x) (((x) & DDR_CONFIG_TRCD_MASK) >> DDR_CONFIG_TRCD_LSB)
#define DDR_CONFIG_TRCD_SET(x) (((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK)
#define DDR_CONFIG_TRCD_RESET 0x6 // 6
#define DDR_CONFIG_TRAS_MSB 4
#define DDR_CONFIG_TRAS_LSB 0
#define DDR_CONFIG_TRAS_MASK 0x0000001f
#define DDR_CONFIG_TRAS_GET(x) (((x) & DDR_CONFIG_TRAS_MASK) >> DDR_CONFIG_TRAS_LSB)
#define DDR_CONFIG_TRAS_SET(x) (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
#define DDR_CONFIG_TRAS_RESET 0x10 // 16
#define DDR_CONFIG_ADDRESS 0x18000000
#define DDR_CONFIG2_HALF_WIDTH_LOW_MSB 31
#define DDR_CONFIG2_HALF_WIDTH_LOW_LSB 31
#define DDR_CONFIG2_HALF_WIDTH_LOW_MASK 0x80000000
#define DDR_CONFIG2_HALF_WIDTH_LOW_GET(x) (((x) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) >> DDR_CONFIG2_HALF_WIDTH_LOW_LSB)
#define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x) (((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK)
#define DDR_CONFIG2_HALF_WIDTH_LOW_RESET 0x1 // 1
#define DDR_CONFIG2_SWAP_A26_A27_MSB 30
#define DDR_CONFIG2_SWAP_A26_A27_LSB 30
#define DDR_CONFIG2_SWAP_A26_A27_MASK 0x40000000
#define DDR_CONFIG2_SWAP_A26_A27_GET(x) (((x) & DDR_CONFIG2_SWAP_A26_A27_MASK) >> DDR_CONFIG2_SWAP_A26_A27_LSB)
#define DDR_CONFIG2_SWAP_A26_A27_SET(x) (((x) << DDR_CONFIG2_SWAP_A26_A27_LSB) & DDR_CONFIG2_SWAP_A26_A27_MASK)
#define DDR_CONFIG2_SWAP_A26_A27_RESET 0x0 // 0
#define DDR_CONFIG2_GATE_OPEN_LATENCY_MSB 29
#define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB 26
#define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK 0x3c000000
#define DDR_CONFIG2_GATE_OPEN_LATENCY_GET(x) (((x) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) >> DDR_CONFIG2_GATE_OPEN_LATENCY_LSB)
#define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x) (((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK)
#define DDR_CONFIG2_GATE_OPEN_LATENCY_RESET 0x6 // 6
#define DDR_CONFIG2_TWTR_MSB 25
#define DDR_CONFIG2_TWTR_LSB 21
#define DDR_CONFIG2_TWTR_MASK 0x03e00000
#define DDR_CONFIG2_TWTR_GET(x) (((x) & DDR_CONFIG2_TWTR_MASK) >> DDR_CONFIG2_TWTR_LSB)
#define DDR_CONFIG2_TWTR_SET(x) (((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK)
#define DDR_CONFIG2_TWTR_RESET 0xe // 14
#define DDR_CONFIG2_TRTP_MSB 20
#define DDR_CONFIG2_TRTP_LSB 17
#define DDR_CONFIG2_TRTP_MASK 0x001e0000
#define DDR_CONFIG2_TRTP_GET(x) (((x) & DDR_CONFIG2_TRTP_MASK) >> DDR_CONFIG2_TRTP_LSB)
#define DDR_CONFIG2_TRTP_SET(x) (((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK)
#define DDR_CONFIG2_TRTP_RESET 0x8 // 8
#define DDR_CONFIG2_TRTW_MSB 16
#define DDR_CONFIG2_TRTW_LSB 12
#define DDR_CONFIG2_TRTW_MASK 0x0001f000
#define DDR_CONFIG2_TRTW_GET(x) (((x) & DDR_CONFIG2_TRTW_MASK) >> DDR_CONFIG2_TRTW_LSB)
#define DDR_CONFIG2_TRTW_SET(x) (((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK)
#define DDR_CONFIG2_TRTW_RESET 0x10 // 16
#define DDR_CONFIG2_TWR_MSB 11
#define DDR_CONFIG2_TWR_LSB 8
#define DDR_CONFIG2_TWR_MASK 0x00000f00
#define DDR_CONFIG2_TWR_GET(x) (((x) & DDR_CONFIG2_TWR_MASK) >> DDR_CONFIG2_TWR_LSB)
#define DDR_CONFIG2_TWR_SET(x) (((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK)
#define DDR_CONFIG2_TWR_RESET 0x6 // 6
#define DDR_CONFIG2_CKE_MSB 7
#define DDR_CONFIG2_CKE_LSB 7
#define DDR_CONFIG2_CKE_MASK 0x00000080
#define DDR_CONFIG2_CKE_GET(x) (((x) & DDR_CONFIG2_CKE_MASK) >> DDR_CONFIG2_CKE_LSB)
#define DDR_CONFIG2_CKE_SET(x) (((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK)
#define DDR_CONFIG2_CKE_RESET 0x0 // 0
#define DDR_CONFIG2_PHASE_SELECT_MSB 6
#define DDR_CONFIG2_PHASE_SELECT_LSB 6
#define DDR_CONFIG2_PHASE_SELECT_MASK 0x00000040
#define DDR_CONFIG2_PHASE_SELECT_GET(x) (((x) & DDR_CONFIG2_PHASE_SELECT_MASK) >> DDR_CONFIG2_PHASE_SELECT_LSB)
#define DDR_CONFIG2_PHASE_SELECT_SET(x) (((x) << DDR_CONFIG2_PHASE_SELECT_LSB) & DDR_CONFIG2_PHASE_SELECT_MASK)
#define DDR_CONFIG2_PHASE_SELECT_RESET 0x0 // 0
#define DDR_CONFIG2_CNTL_OE_EN_MSB 5
#define DDR_CONFIG2_CNTL_OE_EN_LSB 5
#define DDR_CONFIG2_CNTL_OE_EN_MASK 0x00000020
#define DDR_CONFIG2_CNTL_OE_EN_GET(x) (((x) & DDR_CONFIG2_CNTL_OE_EN_MASK) >> DDR_CONFIG2_CNTL_OE_EN_LSB)
#define DDR_CONFIG2_CNTL_OE_EN_SET(x) (((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK)
#define DDR_CONFIG2_CNTL_OE_EN_RESET 0x1 // 1
#define DDR_CONFIG2_BURST_TYPE_MSB 4
#define DDR_CONFIG2_BURST_TYPE_LSB 4
#define DDR_CONFIG2_BURST_TYPE_MASK 0x00000010
#define DDR_CONFIG2_BURST_TYPE_GET(x) (((x) & DDR_CONFIG2_BURST_TYPE_MASK) >> DDR_CONFIG2_BURST_TYPE_LSB)
#define DDR_CONFIG2_BURST_TYPE_SET(x) (((x) << DDR_CONFIG2_BURST_TYPE_LSB) & DDR_CONFIG2_BURST_TYPE_MASK)
#define DDR_CONFIG2_BURST_TYPE_RESET 0x0 // 0
#define DDR_CONFIG2_BURST_LENGTH_MSB 3
#define DDR_CONFIG2_BURST_LENGTH_LSB 0
#define DDR_CONFIG2_BURST_LENGTH_MASK 0x0000000f
#define DDR_CONFIG2_BURST_LENGTH_GET(x) (((x) & DDR_CONFIG2_BURST_LENGTH_MASK) >> DDR_CONFIG2_BURST_LENGTH_LSB)
#define DDR_CONFIG2_BURST_LENGTH_SET(x) (((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK)
#define DDR_CONFIG2_BURST_LENGTH_RESET 0x8 // 8
#define DDR_CONFIG2_ADDRESS 0x18000004
#define DDR_CONFIG_3_SPARE_MSB 31
#define DDR_CONFIG_3_SPARE_LSB 4
#define DDR_CONFIG_3_SPARE_MASK 0xfffffff0
#define DDR_CONFIG_3_SPARE_GET(x) (((x) & DDR_CONFIG_3_SPARE_MASK) >> DDR_CONFIG_3_SPARE_LSB)
#define DDR_CONFIG_3_SPARE_SET(x) (((x) << DDR_CONFIG_3_SPARE_LSB) & DDR_CONFIG_3_SPARE_MASK)
#define DDR_CONFIG_3_SPARE_RESET 0x0 // 0
#define DDR_CONFIG_3_TWR_MSB_MSB 3
#define DDR_CONFIG_3_TWR_MSB_LSB 3
#define DDR_CONFIG_3_TWR_MSB_MASK 0x00000008
#define DDR_CONFIG_3_TWR_MSB_GET(x) (((x) & DDR_CONFIG_3_TWR_MSB_MASK) >> DDR_CONFIG_3_TWR_MSB_LSB)
#define DDR_CONFIG_3_TWR_MSB_SET(x) (((x) << DDR_CONFIG_3_TWR_MSB_LSB) & DDR_CONFIG_3_TWR_MSB_MASK)
#define DDR_CONFIG_3_TWR_MSB_RESET 0x0 // 0
#define DDR_CONFIG_3_TRAS_MSB_MSB 2
#define DDR_CONFIG_3_TRAS_MSB_LSB 2
#define DDR_CONFIG_3_TRAS_MSB_MASK 0x00000004
#define DDR_CONFIG_3_TRAS_MSB_GET(x) (((x) & DDR_CONFIG_3_TRAS_MSB_MASK) >> DDR_CONFIG_3_TRAS_MSB_LSB)
#define DDR_CONFIG_3_TRAS_MSB_SET(x) (((x) << DDR_CONFIG_3_TRAS_MSB_LSB) & DDR_CONFIG_3_TRAS_MSB_MASK)
#define DDR_CONFIG_3_TRAS_MSB_RESET 0x0 // 0
#define DDR_CONFIG_3_TRFC_LSB_MSB 1
#define DDR_CONFIG_3_TRFC_LSB_LSB 0
#define DDR_CONFIG_3_TRFC_LSB_MASK 0x00000003
#define DDR_CONFIG_3_TRFC_LSB_GET(x) (((x) & DDR_CONFIG_3_TRFC_LSB_MASK) >> DDR_CONFIG_3_TRFC_LSB_LSB)
#define DDR_CONFIG_3_TRFC_LSB_SET(x) (((x) << DDR_CONFIG_3_TRFC_LSB_LSB) & DDR_CONFIG_3_TRFC_LSB_MASK)
#define DDR_CONFIG_3_TRFC_LSB_RESET 0x0 // 0
#define DDR_CONFIG_3_ADDRESS 0x1800015c
#define DDR_MODE_REGISTER_VALUE_MSB 13
#define DDR_MODE_REGISTER_VALUE_LSB 0
#define DDR_MODE_REGISTER_VALUE_MASK 0x00003fff
#define DDR_MODE_REGISTER_VALUE_GET(x) (((x) & DDR_MODE_REGISTER_VALUE_MASK) >> DDR_MODE_REGISTER_VALUE_LSB)
#define DDR_MODE_REGISTER_VALUE_SET(x) (((x) << DDR_MODE_REGISTER_VALUE_LSB) & DDR_MODE_REGISTER_VALUE_MASK)
#define DDR_MODE_REGISTER_VALUE_RESET 0x133 // 307
#define DDR_MODE_REGISTER_ADDRESS 0x18000008
#define DDR_EXTENDED_MODE_REGISTER_VALUE_MSB 13
#define DDR_EXTENDED_MODE_REGISTER_VALUE_LSB 0
#define DDR_EXTENDED_MODE_REGISTER_VALUE_MASK 0x00003fff
#define DDR_EXTENDED_MODE_REGISTER_VALUE_GET(x) (((x) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK) >> DDR_EXTENDED_MODE_REGISTER_VALUE_LSB)
#define DDR_EXTENDED_MODE_REGISTER_VALUE_SET(x) (((x) << DDR_EXTENDED_MODE_REGISTER_VALUE_LSB) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK)
#define DDR_EXTENDED_MODE_REGISTER_VALUE_RESET 0x2 // 2
#define DDR_EXTENDED_MODE_REGISTER_ADDRESS 0x1800000c
#define DDR_REFRESH_ENABLE_MSB 14
#define DDR_REFRESH_ENABLE_LSB 14
#define DDR_REFRESH_ENABLE_MASK 0x00004000
#define DDR_REFRESH_ENABLE_GET(x) (((x) & DDR_REFRESH_ENABLE_MASK) >> DDR_REFRESH_ENABLE_LSB)
#define DDR_REFRESH_ENABLE_SET(x) (((x) << DDR_REFRESH_ENABLE_LSB) & DDR_REFRESH_ENABLE_MASK)
#define DDR_REFRESH_ENABLE_RESET 0x0 // 0
#define DDR_REFRESH_PERIOD_MSB 13
#define DDR_REFRESH_PERIOD_LSB 0
#define DDR_REFRESH_PERIOD_MASK 0x00003fff
#define DDR_REFRESH_PERIOD_GET(x) (((x) & DDR_REFRESH_PERIOD_MASK) >> DDR_REFRESH_PERIOD_LSB)
#define DDR_REFRESH_PERIOD_SET(x) (((x) << DDR_REFRESH_PERIOD_LSB) & DDR_REFRESH_PERIOD_MASK)
#define DDR_REFRESH_PERIOD_RESET 0x12c // 300
#define DDR_REFRESH_ADDRESS 0x18000014
#define BB_DPLL2_LOCAL_PLL_MSB 31
#define BB_DPLL2_LOCAL_PLL_LSB 31
#define BB_DPLL2_LOCAL_PLL_MASK 0x80000000
#define BB_DPLL2_LOCAL_PLL_GET(x) (((x) & BB_DPLL2_LOCAL_PLL_MASK) >> BB_DPLL2_LOCAL_PLL_LSB)
#define BB_DPLL2_LOCAL_PLL_SET(x) (((x) << BB_DPLL2_LOCAL_PLL_LSB) & BB_DPLL2_LOCAL_PLL_MASK)
#define BB_DPLL2_LOCAL_PLL_RESET 0x0 // 0
#define BB_DPLL2_KI_MSB 30
#define BB_DPLL2_KI_LSB 29
#define BB_DPLL2_KI_MASK 0x60000000
#define BB_DPLL2_KI_GET(x) (((x) & BB_DPLL2_KI_MASK) >> BB_DPLL2_KI_LSB)
#define BB_DPLL2_KI_SET(x) (((x) << BB_DPLL2_KI_LSB) & BB_DPLL2_KI_MASK)
#define BB_DPLL2_KI_RESET 0x2 // 2
#define BB_DPLL2_KD_MSB 28
#define BB_DPLL2_KD_LSB 25
#define BB_DPLL2_KD_MASK 0x1e000000
#define BB_DPLL2_KD_GET(x) (((x) & BB_DPLL2_KD_MASK) >> BB_DPLL2_KD_LSB)
#define BB_DPLL2_KD_SET(x) (((x) << BB_DPLL2_KD_LSB) & BB_DPLL2_KD_MASK)
#define BB_DPLL2_KD_RESET 0xa // 10
#define BB_DPLL2_EN_NEGTRIG_MSB 24
#define BB_DPLL2_EN_NEGTRIG_LSB 24
#define BB_DPLL2_EN_NEGTRIG_MASK 0x01000000
#define BB_DPLL2_EN_NEGTRIG_GET(x) (((x) & BB_DPLL2_EN_NEGTRIG_MASK) >> BB_DPLL2_EN_NEGTRIG_LSB)
#define BB_DPLL2_EN_NEGTRIG_SET(x) (((x) << BB_DPLL2_EN_NEGTRIG_LSB) & BB_DPLL2_EN_NEGTRIG_MASK)
#define BB_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
#define BB_DPLL2_SEL_1SDM_MSB 23
#define BB_DPLL2_SEL_1SDM_LSB 23
#define BB_DPLL2_SEL_1SDM_MASK 0x00800000
#define BB_DPLL2_SEL_1SDM_GET(x) (((x) & BB_DPLL2_SEL_1SDM_MASK) >> BB_DPLL2_SEL_1SDM_LSB)
#define BB_DPLL2_SEL_1SDM_SET(x) (((x) << BB_DPLL2_SEL_1SDM_LSB) & BB_DPLL2_SEL_1SDM_MASK)
#define BB_DPLL2_SEL_1SDM_RESET 0x0 // 0
#define BB_DPLL2_PLL_PWD_MSB 22
#define BB_DPLL2_PLL_PWD_LSB 22
#define BB_DPLL2_PLL_PWD_MASK 0x00400000
#define BB_DPLL2_PLL_PWD_GET(x) (((x) & BB_DPLL2_PLL_PWD_MASK) >> BB_DPLL2_PLL_PWD_LSB)
#define BB_DPLL2_PLL_PWD_SET(x) (((x) << BB_DPLL2_PLL_PWD_LSB) & BB_DPLL2_PLL_PWD_MASK)
#define BB_DPLL2_PLL_PWD_RESET 0x1 // 1
#define BB_DPLL2_OUTDIV_MSB 21
#define BB_DPLL2_OUTDIV_LSB 19
#define BB_DPLL2_OUTDIV_MASK 0x00380000
#define BB_DPLL2_OUTDIV_GET(x) (((x) & BB_DPLL2_OUTDIV_MASK) >> BB_DPLL2_OUTDIV_LSB)
#define BB_DPLL2_OUTDIV_SET(x) (((x) << BB_DPLL2_OUTDIV_LSB) & BB_DPLL2_OUTDIV_MASK)
#define BB_DPLL2_OUTDIV_RESET 0x1 // 1
#define BB_DPLL2_PHASE_SHIFT_MSB 18
#define BB_DPLL2_PHASE_SHIFT_LSB 12
#define BB_DPLL2_PHASE_SHIFT_MASK 0x0007f000
#define BB_DPLL2_PHASE_SHIFT_GET(x) (((x) & BB_DPLL2_PHASE_SHIFT_MASK) >> BB_DPLL2_PHASE_SHIFT_LSB)
#define BB_DPLL2_PHASE_SHIFT_SET(x) (((x) << BB_DPLL2_PHASE_SHIFT_LSB) & BB_DPLL2_PHASE_SHIFT_MASK)
#define BB_DPLL2_PHASE_SHIFT_RESET 0x0 // 0
#define BB_DPLL2_TESTIN_MSB 11
#define BB_DPLL2_TESTIN_LSB 2
#define BB_DPLL2_TESTIN_MASK 0x00000ffc
#define BB_DPLL2_TESTIN_GET(x) (((x) & BB_DPLL2_TESTIN_MASK) >> BB_DPLL2_TESTIN_LSB)
#define BB_DPLL2_TESTIN_SET(x) (((x) << BB_DPLL2_TESTIN_LSB) & BB_DPLL2_TESTIN_MASK)
#define BB_DPLL2_TESTIN_RESET 0x0 // 0
#define BB_DPLL2_SEL_COUNT_MSB 1
#define BB_DPLL2_SEL_COUNT_LSB 1
#define BB_DPLL2_SEL_COUNT_MASK 0x00000002
#define BB_DPLL2_SEL_COUNT_GET(x) (((x) & BB_DPLL2_SEL_COUNT_MASK) >> BB_DPLL2_SEL_COUNT_LSB)
#define BB_DPLL2_SEL_COUNT_SET(x) (((x) << BB_DPLL2_SEL_COUNT_LSB) & BB_DPLL2_SEL_COUNT_MASK)
#define BB_DPLL2_SEL_COUNT_RESET 0x0 // 0
#define BB_DPLL2_RESET_TEST_MSB 0
#define BB_DPLL2_RESET_TEST_LSB 0
#define BB_DPLL2_RESET_TEST_MASK 0x00000001
#define BB_DPLL2_RESET_TEST_GET(x) (((x) & BB_DPLL2_RESET_TEST_MASK) >> BB_DPLL2_RESET_TEST_LSB)
#define BB_DPLL2_RESET_TEST_SET(x) (((x) << BB_DPLL2_RESET_TEST_LSB) & BB_DPLL2_RESET_TEST_MASK)
#define BB_DPLL2_RESET_TEST_RESET 0x0 // 0
#define BB_DPLL2_ADDRESS 0x18116184
#define PCIe_DPLL2_LOCAL_PLL_MSB 31
#define PCIe_DPLL2_LOCAL_PLL_LSB 31
#define PCIe_DPLL2_LOCAL_PLL_MASK 0x80000000
#define PCIe_DPLL2_LOCAL_PLL_GET(x) (((x) & PCIe_DPLL2_LOCAL_PLL_MASK) >> PCIe_DPLL2_LOCAL_PLL_LSB)
#define PCIe_DPLL2_LOCAL_PLL_SET(x) (((x) << PCIe_DPLL2_LOCAL_PLL_LSB) & PCIe_DPLL2_LOCAL_PLL_MASK)
#define PCIe_DPLL2_LOCAL_PLL_RESET 0x0 // 0
#define PCIe_DPLL2_KI_MSB 30
#define PCIe_DPLL2_KI_LSB 29
#define PCIe_DPLL2_KI_MASK 0x60000000
#define PCIe_DPLL2_KI_GET(x) (((x) & PCIe_DPLL2_KI_MASK) >> PCIe_DPLL2_KI_LSB)
#define PCIe_DPLL2_KI_SET(x) (((x) << PCIe_DPLL2_KI_LSB) & PCIe_DPLL2_KI_MASK)
#define PCIe_DPLL2_KI_RESET 0x2 // 2
#define PCIe_DPLL2_KD_MSB 28
#define PCIe_DPLL2_KD_LSB 25
#define PCIe_DPLL2_KD_MASK 0x1e000000
#define PCIe_DPLL2_KD_GET(x) (((x) & PCIe_DPLL2_KD_MASK) >> PCIe_DPLL2_KD_LSB)
#define PCIe_DPLL2_KD_SET(x) (((x) << PCIe_DPLL2_KD_LSB) & PCIe_DPLL2_KD_MASK)
#define PCIe_DPLL2_KD_RESET 0xa // 10
#define PCIe_DPLL2_EN_NEGTRIG_MSB 24
#define PCIe_DPLL2_EN_NEGTRIG_LSB 24
#define PCIe_DPLL2_EN_NEGTRIG_MASK 0x01000000
#define PCIe_DPLL2_EN_NEGTRIG_GET(x) (((x) & PCIe_DPLL2_EN_NEGTRIG_MASK) >> PCIe_DPLL2_EN_NEGTRIG_LSB)
#define PCIe_DPLL2_EN_NEGTRIG_SET(x) (((x) << PCIe_DPLL2_EN_NEGTRIG_LSB) & PCIe_DPLL2_EN_NEGTRIG_MASK)
#define PCIe_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
#define PCIe_DPLL2_SEL_1SDM_MSB 23
#define PCIe_DPLL2_SEL_1SDM_LSB 23
#define PCIe_DPLL2_SEL_1SDM_MASK 0x00800000
#define PCIe_DPLL2_SEL_1SDM_GET(x) (((x) & PCIe_DPLL2_SEL_1SDM_MASK) >> PCIe_DPLL2_SEL_1SDM_LSB)
#define PCIe_DPLL2_SEL_1SDM_SET(x) (((x) << PCIe_DPLL2_SEL_1SDM_LSB) & PCIe_DPLL2_SEL_1SDM_MASK)
#define PCIe_DPLL2_SEL_1SDM_RESET 0x0 // 0
#define PCIe_DPLL2_PLL_PWD_MSB 22
#define PCIe_DPLL2_PLL_PWD_LSB 22
#define PCIe_DPLL2_PLL_PWD_MASK 0x00400000
#define PCIe_DPLL2_PLL_PWD_GET(x) (((x) & PCIe_DPLL2_PLL_PWD_MASK) >> PCIe_DPLL2_PLL_PWD_LSB)
#define PCIe_DPLL2_PLL_PWD_SET(x) (((x) << PCIe_DPLL2_PLL_PWD_LSB) & PCIe_DPLL2_PLL_PWD_MASK)
#define PCIe_DPLL2_PLL_PWD_RESET 0x1 // 1
#define PCIe_DPLL2_OUTDIV_MSB 21
#define PCIe_DPLL2_OUTDIV_LSB 19
#define PCIe_DPLL2_OUTDIV_MASK 0x00380000
#define PCIe_DPLL2_OUTDIV_GET(x) (((x) & PCIe_DPLL2_OUTDIV_MASK) >> PCIe_DPLL2_OUTDIV_LSB)
#define PCIe_DPLL2_OUTDIV_SET(x) (((x) << PCIe_DPLL2_OUTDIV_LSB) & PCIe_DPLL2_OUTDIV_MASK)
#define PCIe_DPLL2_OUTDIV_RESET 0x1 // 1
#define PCIe_DPLL2_PHASE_SHIFT_MSB 18
#define PCIe_DPLL2_PHASE_SHIFT_LSB 12
#define PCIe_DPLL2_PHASE_SHIFT_MASK 0x0007f000
#define PCIe_DPLL2_PHASE_SHIFT_GET(x) (((x) & PCIe_DPLL2_PHASE_SHIFT_MASK) >> PCIe_DPLL2_PHASE_SHIFT_LSB)
#define PCIe_DPLL2_PHASE_SHIFT_SET(x) (((x) << PCIe_DPLL2_PHASE_SHIFT_LSB) & PCIe_DPLL2_PHASE_SHIFT_MASK)
#define PCIe_DPLL2_PHASE_SHIFT_RESET 0x0 // 0
#define PCIe_DPLL2_TESTIN_MSB 11
#define PCIe_DPLL2_TESTIN_LSB 2
#define PCIe_DPLL2_TESTIN_MASK 0x00000ffc
#define PCIe_DPLL2_TESTIN_GET(x) (((x) & PCIe_DPLL2_TESTIN_MASK) >> PCIe_DPLL2_TESTIN_LSB)
#define PCIe_DPLL2_TESTIN_SET(x) (((x) << PCIe_DPLL2_TESTIN_LSB) & PCIe_DPLL2_TESTIN_MASK)
#define PCIe_DPLL2_TESTIN_RESET 0x0 // 0
#define PCIe_DPLL2_SEL_COUNT_MSB 1
#define PCIe_DPLL2_SEL_COUNT_LSB 1
#define PCIe_DPLL2_SEL_COUNT_MASK 0x00000002
#define PCIe_DPLL2_SEL_COUNT_GET(x) (((x) & PCIe_DPLL2_SEL_COUNT_MASK) >> PCIe_DPLL2_SEL_COUNT_LSB)
#define PCIe_DPLL2_SEL_COUNT_SET(x) (((x) << PCIe_DPLL2_SEL_COUNT_LSB) & PCIe_DPLL2_SEL_COUNT_MASK)
#define PCIe_DPLL2_SEL_COUNT_RESET 0x0 // 0
#define PCIe_DPLL2_RESET_TEST_MSB 0
#define PCIe_DPLL2_RESET_TEST_LSB 0
#define PCIe_DPLL2_RESET_TEST_MASK 0x00000001
#define PCIe_DPLL2_RESET_TEST_GET(x) (((x) & PCIe_DPLL2_RESET_TEST_MASK) >> PCIe_DPLL2_RESET_TEST_LSB)
#define PCIe_DPLL2_RESET_TEST_SET(x) (((x) << PCIe_DPLL2_RESET_TEST_LSB) & PCIe_DPLL2_RESET_TEST_MASK)
#define PCIe_DPLL2_RESET_TEST_RESET 0x0 // 0
#define PCIe_DPLL2_ADDRESS 0x18116c04
#define DDR_DPLL2_LOCAL_PLL_MSB 31
#define DDR_DPLL2_LOCAL_PLL_LSB 31
#define DDR_DPLL2_LOCAL_PLL_MASK 0x80000000
#define DDR_DPLL2_LOCAL_PLL_GET(x) (((x) & DDR_DPLL2_LOCAL_PLL_MASK) >> DDR_DPLL2_LOCAL_PLL_LSB)
#define DDR_DPLL2_LOCAL_PLL_SET(x) (((x) << DDR_DPLL2_LOCAL_PLL_LSB) & DDR_DPLL2_LOCAL_PLL_MASK)
#define DDR_DPLL2_LOCAL_PLL_RESET 0x0 // 0
#define DDR_DPLL2_KI_MSB 30
#define DDR_DPLL2_KI_LSB 29
#define DDR_DPLL2_KI_MASK 0x60000000
#define DDR_DPLL2_KI_GET(x) (((x) & DDR_DPLL2_KI_MASK) >> DDR_DPLL2_KI_LSB)
#define DDR_DPLL2_KI_SET(x) (((x) << DDR_DPLL2_KI_LSB) & DDR_DPLL2_KI_MASK)
#define DDR_DPLL2_KI_RESET 0x2 // 2
#define DDR_DPLL2_KD_MSB 28
#define DDR_DPLL2_KD_LSB 25
#define DDR_DPLL2_KD_MASK 0x1e000000
#define DDR_DPLL2_KD_GET(x) (((x) & DDR_DPLL2_KD_MASK) >> DDR_DPLL2_KD_LSB)
#define DDR_DPLL2_KD_SET(x) (((x) << DDR_DPLL2_KD_LSB) & DDR_DPLL2_KD_MASK)
#define DDR_DPLL2_KD_RESET 0xa // 10
#define DDR_DPLL2_EN_NEGTRIG_MSB 24
#define DDR_DPLL2_EN_NEGTRIG_LSB 24
#define DDR_DPLL2_EN_NEGTRIG_MASK 0x01000000
#define DDR_DPLL2_EN_NEGTRIG_GET(x) (((x) & DDR_DPLL2_EN_NEGTRIG_MASK) >> DDR_DPLL2_EN_NEGTRIG_LSB)
#define DDR_DPLL2_EN_NEGTRIG_SET(x) (((x) << DDR_DPLL2_EN_NEGTRIG_LSB) & DDR_DPLL2_EN_NEGTRIG_MASK)
#define DDR_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
#define DDR_DPLL2_SEL_1SDM_MSB 23
#define DDR_DPLL2_SEL_1SDM_LSB 23
#define DDR_DPLL2_SEL_1SDM_MASK 0x00800000
#define DDR_DPLL2_SEL_1SDM_GET(x) (((x) & DDR_DPLL2_SEL_1SDM_MASK) >> DDR_DPLL2_SEL_1SDM_LSB)
#define DDR_DPLL2_SEL_1SDM_SET(x) (((x) << DDR_DPLL2_SEL_1SDM_LSB) & DDR_DPLL2_SEL_1SDM_MASK)
#define DDR_DPLL2_SEL_1SDM_RESET 0x0 // 0
#define DDR_DPLL2_PLL_PWD_MSB 22
#define DDR_DPLL2_PLL_PWD_LSB 22
#define DDR_DPLL2_PLL_PWD_MASK 0x00400000
#define DDR_DPLL2_PLL_PWD_GET(x) (((x) & DDR_DPLL2_PLL_PWD_MASK) >> DDR_DPLL2_PLL_PWD_LSB)
#define DDR_DPLL2_PLL_PWD_SET(x) (((x) << DDR_DPLL2_PLL_PWD_LSB) & DDR_DPLL2_PLL_PWD_MASK)
#define DDR_DPLL2_PLL_PWD_RESET 0x1 // 1
#define DDR_DPLL2_OUTDIV_MSB 21
#define DDR_DPLL2_OUTDIV_LSB 19
#define DDR_DPLL2_OUTDIV_MASK 0x00380000
#define DDR_DPLL2_OUTDIV_GET(x) (((x) & DDR_DPLL2_OUTDIV_MASK) >> DDR_DPLL2_OUTDIV_LSB)
#define DDR_DPLL2_OUTDIV_SET(x) (((x) << DDR_DPLL2_OUTDIV_LSB) & DDR_DPLL2_OUTDIV_MASK)
#define DDR_DPLL2_OUTDIV_RESET 0x1 // 1
#define DDR_DPLL2_PHASE_SHIFT_MSB 18
#define DDR_DPLL2_PHASE_SHIFT_LSB 12
#define DDR_DPLL2_PHASE_SHIFT_MASK 0x0007f000
#define DDR_DPLL2_PHASE_SHIFT_GET(x) (((x) & DDR_DPLL2_PHASE_SHIFT_MASK) >> DDR_DPLL2_PHASE_SHIFT_LSB)
#define DDR_DPLL2_PHASE_SHIFT_SET(x) (((x) << DDR_DPLL2_PHASE_SHIFT_LSB) & DDR_DPLL2_PHASE_SHIFT_MASK)
#define DDR_DPLL2_PHASE_SHIFT_RESET 0x0 // 0
#define DDR_DPLL2_TESTIN_MSB 11
#define DDR_DPLL2_TESTIN_LSB 2
#define DDR_DPLL2_TESTIN_MASK 0x00000ffc
#define DDR_DPLL2_TESTIN_GET(x) (((x) & DDR_DPLL2_TESTIN_MASK) >> DDR_DPLL2_TESTIN_LSB)
#define DDR_DPLL2_TESTIN_SET(x) (((x) << DDR_DPLL2_TESTIN_LSB) & DDR_DPLL2_TESTIN_MASK)
#define DDR_DPLL2_TESTIN_RESET 0x0 // 0
#define DDR_DPLL2_SEL_COUNT_MSB 1
#define DDR_DPLL2_SEL_COUNT_LSB 1
#define DDR_DPLL2_SEL_COUNT_MASK 0x00000002
#define DDR_DPLL2_SEL_COUNT_GET(x) (((x) & DDR_DPLL2_SEL_COUNT_MASK) >> DDR_DPLL2_SEL_COUNT_LSB)
#define DDR_DPLL2_SEL_COUNT_SET(x) (((x) << DDR_DPLL2_SEL_COUNT_LSB) & DDR_DPLL2_SEL_COUNT_MASK)
#define DDR_DPLL2_SEL_COUNT_RESET 0x0 // 0
#define DDR_DPLL2_RESET_TEST_MSB 0
#define DDR_DPLL2_RESET_TEST_LSB 0
#define DDR_DPLL2_RESET_TEST_MASK 0x00000001
#define DDR_DPLL2_RESET_TEST_GET(x) (((x) & DDR_DPLL2_RESET_TEST_MASK) >> DDR_DPLL2_RESET_TEST_LSB)
#define DDR_DPLL2_RESET_TEST_SET(x) (((x) << DDR_DPLL2_RESET_TEST_LSB) & DDR_DPLL2_RESET_TEST_MASK)
#define DDR_DPLL2_RESET_TEST_RESET 0x0 // 0
#define DDR_DPLL2_ADDRESS 0x18116244
#define CPU_DPLL2_LOCAL_PLL_MSB 31
#define CPU_DPLL2_LOCAL_PLL_LSB 31
#define CPU_DPLL2_LOCAL_PLL_MASK 0x80000000
#define CPU_DPLL2_LOCAL_PLL_GET(x) (((x) & CPU_DPLL2_LOCAL_PLL_MASK) >> CPU_DPLL2_LOCAL_PLL_LSB)
#define CPU_DPLL2_LOCAL_PLL_SET(x) (((x) << CPU_DPLL2_LOCAL_PLL_LSB) & CPU_DPLL2_LOCAL_PLL_MASK)
#define CPU_DPLL2_LOCAL_PLL_RESET 0x0 // 0
#define CPU_DPLL2_KI_MSB 30
#define CPU_DPLL2_KI_LSB 29
#define CPU_DPLL2_KI_MASK 0x60000000
#define CPU_DPLL2_KI_GET(x) (((x) & CPU_DPLL2_KI_MASK) >> CPU_DPLL2_KI_LSB)
#define CPU_DPLL2_KI_SET(x) (((x) << CPU_DPLL2_KI_LSB) & CPU_DPLL2_KI_MASK)
#define CPU_DPLL2_KI_RESET 0x2 // 2
#define CPU_DPLL2_KD_MSB 28
#define CPU_DPLL2_KD_LSB 25
#define CPU_DPLL2_KD_MASK 0x1e000000
#define CPU_DPLL2_KD_GET(x) (((x) & CPU_DPLL2_KD_MASK) >> CPU_DPLL2_KD_LSB)
#define CPU_DPLL2_KD_SET(x) (((x) << CPU_DPLL2_KD_LSB) & CPU_DPLL2_KD_MASK)
#define CPU_DPLL2_KD_RESET 0xa // 10
#define CPU_DPLL2_EN_NEGTRIG_MSB 24
#define CPU_DPLL2_EN_NEGTRIG_LSB 24
#define CPU_DPLL2_EN_NEGTRIG_MASK 0x01000000
#define CPU_DPLL2_EN_NEGTRIG_GET(x) (((x) & CPU_DPLL2_EN_NEGTRIG_MASK) >> CPU_DPLL2_EN_NEGTRIG_LSB)
#define CPU_DPLL2_EN_NEGTRIG_SET(x) (((x) << CPU_DPLL2_EN_NEGTRIG_LSB) & CPU_DPLL2_EN_NEGTRIG_MASK)
#define CPU_DPLL2_EN_NEGTRIG_RESET 0x0 // 0
#define CPU_DPLL2_SEL_1SDM_MSB 23
#define CPU_DPLL2_SEL_1SDM_LSB 23
#define CPU_DPLL2_SEL_1SDM_MASK 0x00800000
#define CPU_DPLL2_SEL_1SDM_GET(x) (((x) & CPU_DPLL2_SEL_1SDM_MASK) >> CPU_DPLL2_SEL_1SDM_LSB)
#define CPU_DPLL2_SEL_1SDM_SET(x) (((x) << CPU_DPLL2_SEL_1SDM_LSB) & CPU_DPLL2_SEL_1SDM_MASK)
#define CPU_DPLL2_SEL_1SDM_RESET 0x0 // 0
#define CPU_DPLL2_PLL_PWD_MSB 22
#define CPU_DPLL2_PLL_PWD_LSB 22
#define CPU_DPLL2_PLL_PWD_MASK 0x00400000
#define CPU_DPLL2_PLL_PWD_GET(x) (((x) & CPU_DPLL2_PLL_PWD_MASK) >> CPU_DPLL2_PLL_PWD_LSB)
#define CPU_DPLL2_PLL_PWD_SET(x) (((x) << CPU_DPLL2_PLL_PWD_LSB) & CPU_DPLL2_PLL_PWD_MASK)
#define CPU_DPLL2_PLL_PWD_RESET 0x1 // 1
#define CPU_DPLL2_OUTDIV_MSB 21
#define CPU_DPLL2_OUTDIV_LSB 19
#define CPU_DPLL2_OUTDIV_MASK 0x00380000
#define CPU_DPLL2_OUTDIV_GET(x) (((x) & CPU_DPLL2_OUTDIV_MASK) >> CPU_DPLL2_OUTDIV_LSB)
#define CPU_DPLL2_OUTDIV_SET(x) (((x) << CPU_DPLL2_OUTDIV_LSB) & CPU_DPLL2_OUTDIV_MASK)
#define CPU_DPLL2_OUTDIV_RESET 0x1 // 1
#define CPU_DPLL2_PHASE_SHIFT_MSB 18
#define CPU_DPLL2_PHASE_SHIFT_LSB 12
#define CPU_DPLL2_PHASE_SHIFT_MASK 0x0007f000
#define CPU_DPLL2_PHASE_SHIFT_GET(x) (((x) & CPU_DPLL2_PHASE_SHIFT_MASK) >> CPU_DPLL2_PHASE_SHIFT_LSB)
#define CPU_DPLL2_PHASE_SHIFT_SET(x) (((x) << CPU_DPLL2_PHASE_SHIFT_LSB) & CPU_DPLL2_PHASE_SHIFT_MASK)
#define CPU_DPLL2_PHASE_SHIFT_RESET 0x0 // 0
#define CPU_DPLL2_TESTIN_MSB 11
#define CPU_DPLL2_TESTIN_LSB 2
#define CPU_DPLL2_TESTIN_MASK 0x00000ffc
#define CPU_DPLL2_TESTIN_GET(x) (((x) & CPU_DPLL2_TESTIN_MASK) >> CPU_DPLL2_TESTIN_LSB)
#define CPU_DPLL2_TESTIN_SET(x) (((x) << CPU_DPLL2_TESTIN_LSB) & CPU_DPLL2_TESTIN_MASK)
#define CPU_DPLL2_TESTIN_RESET 0x0 // 0
#define CPU_DPLL2_SEL_COUNT_MSB 1
#define CPU_DPLL2_SEL_COUNT_LSB 1
#define CPU_DPLL2_SEL_COUNT_MASK 0x00000002
#define CPU_DPLL2_SEL_COUNT_GET(x) (((x) & CPU_DPLL2_SEL_COUNT_MASK) >> CPU_DPLL2_SEL_COUNT_LSB)
#define CPU_DPLL2_SEL_COUNT_SET(x) (((x) << CPU_DPLL2_SEL_COUNT_LSB) & CPU_DPLL2_SEL_COUNT_MASK)
#define CPU_DPLL2_SEL_COUNT_RESET 0x0 // 0
#define CPU_DPLL2_RESET_TEST_MSB 0
#define CPU_DPLL2_RESET_TEST_LSB 0
#define CPU_DPLL2_RESET_TEST_MASK 0x00000001
#define CPU_DPLL2_RESET_TEST_GET(x) (((x) & CPU_DPLL2_RESET_TEST_MASK) >> CPU_DPLL2_RESET_TEST_LSB)
#define CPU_DPLL2_RESET_TEST_SET(x) (((x) << CPU_DPLL2_RESET_TEST_LSB) & CPU_DPLL2_RESET_TEST_MASK)
#define CPU_DPLL2_RESET_TEST_RESET 0x0 // 0
#define CPU_DPLL2_ADDRESS 0x181161c4
#define DDR_RD_DATA_THIS_CYCLE_ADDRESS 0x18000018
#define TAP_CONTROL_0_ADDRESS 0x1800001c
#define TAP_CONTROL_1_ADDRESS 0x18000020
#define TAP_CONTROL_2_ADDRESS 0x18000024
#define TAP_CONTROL_3_ADDRESS 0x18000028
#define DDR_BURST_CPU_PRIORITY_MSB 31
#define DDR_BURST_CPU_PRIORITY_LSB 31
#define DDR_BURST_CPU_PRIORITY_MASK 0x80000000
#define DDR_BURST_CPU_PRIORITY_GET(x) (((x) & DDR_BURST_CPU_PRIORITY_MASK) >> DDR_BURST_CPU_PRIORITY_LSB)
#define DDR_BURST_CPU_PRIORITY_SET(x) (((x) << DDR_BURST_CPU_PRIORITY_LSB) & DDR_BURST_CPU_PRIORITY_MASK)
#define DDR_BURST_CPU_PRIORITY_RESET 0x0 // 0
#define DDR_BURST_CPU_PRIORITY_BE_MSB 30
#define DDR_BURST_CPU_PRIORITY_BE_LSB 30
#define DDR_BURST_CPU_PRIORITY_BE_MASK 0x40000000
#define DDR_BURST_CPU_PRIORITY_BE_GET(x) (((x) & DDR_BURST_CPU_PRIORITY_BE_MASK) >> DDR_BURST_CPU_PRIORITY_BE_LSB)
#define DDR_BURST_CPU_PRIORITY_BE_SET(x) (((x) << DDR_BURST_CPU_PRIORITY_BE_LSB) & DDR_BURST_CPU_PRIORITY_BE_MASK)
#define DDR_BURST_CPU_PRIORITY_BE_RESET 0x1 // 1
#define DDR_BURST_ENABLE_RWP_MASK_MSB 29
#define DDR_BURST_ENABLE_RWP_MASK_LSB 28
#define DDR_BURST_ENABLE_RWP_MASK_MASK 0x30000000
#define DDR_BURST_ENABLE_RWP_MASK_GET(x) (((x) & DDR_BURST_ENABLE_RWP_MASK_MASK) >> DDR_BURST_ENABLE_RWP_MASK_LSB)
#define DDR_BURST_ENABLE_RWP_MASK_SET(x) (((x) << DDR_BURST_ENABLE_RWP_MASK_LSB) & DDR_BURST_ENABLE_RWP_MASK_MASK)
#define DDR_BURST_ENABLE_RWP_MASK_RESET 0x3 // 3
#define DDR_BURST_MAX_WRITE_BURST_MSB 27
#define DDR_BURST_MAX_WRITE_BURST_LSB 24
#define DDR_BURST_MAX_WRITE_BURST_MASK 0x0f000000
#define DDR_BURST_MAX_WRITE_BURST_GET(x) (((x) & DDR_BURST_MAX_WRITE_BURST_MASK) >> DDR_BURST_MAX_WRITE_BURST_LSB)
#define DDR_BURST_MAX_WRITE_BURST_SET(x) (((x) << DDR_BURST_MAX_WRITE_BURST_LSB) & DDR_BURST_MAX_WRITE_BURST_MASK)
#define DDR_BURST_MAX_WRITE_BURST_RESET 0x4 // 4
#define DDR_BURST_MAX_READ_BURST_MSB 23
#define DDR_BURST_MAX_READ_BURST_LSB 20
#define DDR_BURST_MAX_READ_BURST_MASK 0x00f00000
#define DDR_BURST_MAX_READ_BURST_GET(x) (((x) & DDR_BURST_MAX_READ_BURST_MASK) >> DDR_BURST_MAX_READ_BURST_LSB)
#define DDR_BURST_MAX_READ_BURST_SET(x) (((x) << DDR_BURST_MAX_READ_BURST_LSB) & DDR_BURST_MAX_READ_BURST_MASK)
#define DDR_BURST_MAX_READ_BURST_RESET 0x4 // 4
#define DDR_BURST_CPU_MAX_BL_MSB 19
#define DDR_BURST_CPU_MAX_BL_LSB 16
#define DDR_BURST_CPU_MAX_BL_MASK 0x000f0000
#define DDR_BURST_CPU_MAX_BL_GET(x) (((x) & DDR_BURST_CPU_MAX_BL_MASK) >> DDR_BURST_CPU_MAX_BL_LSB)
#define DDR_BURST_CPU_MAX_BL_SET(x) (((x) << DDR_BURST_CPU_MAX_BL_LSB) & DDR_BURST_CPU_MAX_BL_MASK)
#define DDR_BURST_CPU_MAX_BL_RESET 0x3 // 3
#define DDR_BURST_USB_MAX_BL_MSB 15
#define DDR_BURST_USB_MAX_BL_LSB 12
#define DDR_BURST_USB_MAX_BL_MASK 0x0000f000
#define DDR_BURST_USB_MAX_BL_GET(x) (((x) & DDR_BURST_USB_MAX_BL_MASK) >> DDR_BURST_USB_MAX_BL_LSB)
#define DDR_BURST_USB_MAX_BL_SET(x) (((x) << DDR_BURST_USB_MAX_BL_LSB) & DDR_BURST_USB_MAX_BL_MASK)
#define DDR_BURST_USB_MAX_BL_RESET 0x4 // 4
#define DDR_BURST_PCIE_MAX_BL_MSB 11
#define DDR_BURST_PCIE_MAX_BL_LSB 8
#define DDR_BURST_PCIE_MAX_BL_MASK 0x00000f00
#define DDR_BURST_PCIE_MAX_BL_GET(x) (((x) & DDR_BURST_PCIE_MAX_BL_MASK) >> DDR_BURST_PCIE_MAX_BL_LSB)
#define DDR_BURST_PCIE_MAX_BL_SET(x) (((x) << DDR_BURST_PCIE_MAX_BL_LSB) & DDR_BURST_PCIE_MAX_BL_MASK)
#define DDR_BURST_PCIE_MAX_BL_RESET 0x3 // 3
#define DDR_BURST_GE1_MAX_BL_MSB 7
#define DDR_BURST_GE1_MAX_BL_LSB 4
#define DDR_BURST_GE1_MAX_BL_MASK 0x000000f0
#define DDR_BURST_GE1_MAX_BL_GET(x) (((x) & DDR_BURST_GE1_MAX_BL_MASK) >> DDR_BURST_GE1_MAX_BL_LSB)
#define DDR_BURST_GE1_MAX_BL_SET(x) (((x) << DDR_BURST_GE1_MAX_BL_LSB) & DDR_BURST_GE1_MAX_BL_MASK)
#define DDR_BURST_GE1_MAX_BL_RESET 0x3 // 3
#define DDR_BURST_GE0_MAX_BL_MSB 3
#define DDR_BURST_GE0_MAX_BL_LSB 0
#define DDR_BURST_GE0_MAX_BL_MASK 0x0000000f
#define DDR_BURST_GE0_MAX_BL_GET(x) (((x) & DDR_BURST_GE0_MAX_BL_MASK) >> DDR_BURST_GE0_MAX_BL_LSB)
#define DDR_BURST_GE0_MAX_BL_SET(x) (((x) << DDR_BURST_GE0_MAX_BL_LSB) & DDR_BURST_GE0_MAX_BL_MASK)
#define DDR_BURST_GE0_MAX_BL_RESET 0x3 // 3
#define DDR_BURST_ADDRESS 0x180000c4
#define DDR_BURST2_WMAC_MAX_BL_MSB 3
#define DDR_BURST2_WMAC_MAX_BL_LSB 0
#define DDR_BURST2_WMAC_MAX_BL_MASK 0x0000000f
#define DDR_BURST2_WMAC_MAX_BL_GET(x) (((x) & DDR_BURST2_WMAC_MAX_BL_MASK) >> DDR_BURST2_WMAC_MAX_BL_LSB)
#define DDR_BURST2_WMAC_MAX_BL_SET(x) (((x) << DDR_BURST2_WMAC_MAX_BL_LSB) & DDR_BURST2_WMAC_MAX_BL_MASK)
#define DDR_BURST2_WMAC_MAX_BL_RESET 0x3 // 3
#define DDR_BURST2_ADDRESS 0x180000c8
#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MSB 19
#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB 0
#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK 0x000fffff
#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_GET(x) (((x) & DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK) >> DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB)
#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_SET(x) (((x) << DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB) & DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK)
#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_RESET 0x8000 // 32768
#define DDR_AHB_MASTER_TIMEOUT_MAX_ADDRESS 0x180000cc
#define PMU1_ADDRESS 0x18116c40
#define PMU2_SWREGMSB_MSB 31
#define PMU2_SWREGMSB_LSB 22
#define PMU2_SWREGMSB_MASK 0xffc00000
#define PMU2_SWREGMSB_GET(x) (((x) & PMU2_SWREGMSB_MASK) >> PMU2_SWREGMSB_LSB)
#define PMU2_SWREGMSB_SET(x) (((x) << PMU2_SWREGMSB_LSB) & PMU2_SWREGMSB_MASK)
#define PMU2_SWREGMSB_RESET 0x0 // 0
#define PMU2_PGM_MSB 21
#define PMU2_PGM_LSB 21
#define PMU2_PGM_MASK 0x00200000
#define PMU2_PGM_GET(x) (((x) & PMU2_PGM_MASK) >> PMU2_PGM_LSB)
#define PMU2_PGM_SET(x) (((x) << PMU2_PGM_LSB) & PMU2_PGM_MASK)
#define PMU2_PGM_RESET 0x0 // 0
#define PMU2_LDO_TUNE_MSB 20
#define PMU2_LDO_TUNE_LSB 19
#define PMU2_LDO_TUNE_MASK 0x00180000
#define PMU2_LDO_TUNE_GET(x) (((x) & PMU2_LDO_TUNE_MASK) >> PMU2_LDO_TUNE_LSB)
#define PMU2_LDO_TUNE_SET(x) (((x) << PMU2_LDO_TUNE_LSB) & PMU2_LDO_TUNE_MASK)
#define PMU2_LDO_TUNE_RESET 0x0 // 0
#define PMU2_PWDLDO_DDR_MSB 18
#define PMU2_PWDLDO_DDR_LSB 18
#define PMU2_PWDLDO_DDR_MASK 0x00040000
#define PMU2_PWDLDO_DDR_GET(x) (((x) & PMU2_PWDLDO_DDR_MASK) >> PMU2_PWDLDO_DDR_LSB)
#define PMU2_PWDLDO_DDR_SET(x) (((x) << PMU2_PWDLDO_DDR_LSB) & PMU2_PWDLDO_DDR_MASK)
#define PMU2_PWDLDO_DDR_RESET 0x0 // 0
#define PMU2_LPOPWD_MSB 17
#define PMU2_LPOPWD_LSB 17
#define PMU2_LPOPWD_MASK 0x00020000
#define PMU2_LPOPWD_GET(x) (((x) & PMU2_LPOPWD_MASK) >> PMU2_LPOPWD_LSB)
#define PMU2_LPOPWD_SET(x) (((x) << PMU2_LPOPWD_LSB) & PMU2_LPOPWD_MASK)
#define PMU2_LPOPWD_RESET 0x0 // 0
#define PMU2_SPARE_MSB 16
#define PMU2_SPARE_LSB 0
#define PMU2_SPARE_MASK 0x0001ffff
#define PMU2_SPARE_GET(x) (((x) & PMU2_SPARE_MASK) >> PMU2_SPARE_LSB)
#define PMU2_SPARE_SET(x) (((x) << PMU2_SPARE_LSB) & PMU2_SPARE_MASK)
#define PMU2_SPARE_RESET 0x0 // 0
#define PMU2_ADDRESS 0x18116c44
#define PHY_CTRL0_LOOPBACK_ERR_CNT_MSB 31
#define PHY_CTRL0_LOOPBACK_ERR_CNT_LSB 24
#define PHY_CTRL0_LOOPBACK_ERR_CNT_MASK 0xff000000
#define PHY_CTRL0_LOOPBACK_ERR_CNT_GET(x) (((x) & PHY_CTRL0_LOOPBACK_ERR_CNT_MASK) >> PHY_CTRL0_LOOPBACK_ERR_CNT_LSB)
#define PHY_CTRL0_LOOPBACK_ERR_CNT_SET(x) (((x) << PHY_CTRL0_LOOPBACK_ERR_CNT_LSB) & PHY_CTRL0_LOOPBACK_ERR_CNT_MASK)
#define PHY_CTRL0_LOOPBACK_ERR_CNT_RESET 0x0 // 0
#define PHY_CTRL0_DIG_LOOPBACK_EN_MSB 23
#define PHY_CTRL0_DIG_LOOPBACK_EN_LSB 23
#define PHY_CTRL0_DIG_LOOPBACK_EN_MASK 0x00800000
#define PHY_CTRL0_DIG_LOOPBACK_EN_GET(x) (((x) & PHY_CTRL0_DIG_LOOPBACK_EN_MASK) >> PHY_CTRL0_DIG_LOOPBACK_EN_LSB)
#define PHY_CTRL0_DIG_LOOPBACK_EN_SET(x) (((x) << PHY_CTRL0_DIG_LOOPBACK_EN_LSB) & PHY_CTRL0_DIG_LOOPBACK_EN_MASK)
#define PHY_CTRL0_DIG_LOOPBACK_EN_RESET 0x0 // 0
#define PHY_CTRL0_ANA_LOOPBACK_EN_MSB 22
#define PHY_CTRL0_ANA_LOOPBACK_EN_LSB 22
#define PHY_CTRL0_ANA_LOOPBACK_EN_MASK 0x00400000
#define PHY_CTRL0_ANA_LOOPBACK_EN_GET(x) (((x) & PHY_CTRL0_ANA_LOOPBACK_EN_MASK) >> PHY_CTRL0_ANA_LOOPBACK_EN_LSB)
#define PHY_CTRL0_ANA_LOOPBACK_EN_SET(x) (((x) << PHY_CTRL0_ANA_LOOPBACK_EN_LSB) & PHY_CTRL0_ANA_LOOPBACK_EN_MASK)
#define PHY_CTRL0_ANA_LOOPBACK_EN_RESET 0x0 // 0
#define PHY_CTRL0_TX_PATTERN_EN_MSB 21
#define PHY_CTRL0_TX_PATTERN_EN_LSB 21
#define PHY_CTRL0_TX_PATTERN_EN_MASK 0x00200000
#define PHY_CTRL0_TX_PATTERN_EN_GET(x) (((x) & PHY_CTRL0_TX_PATTERN_EN_MASK) >> PHY_CTRL0_TX_PATTERN_EN_LSB)
#define PHY_CTRL0_TX_PATTERN_EN_SET(x) (((x) << PHY_CTRL0_TX_PATTERN_EN_LSB) & PHY_CTRL0_TX_PATTERN_EN_MASK)
#define PHY_CTRL0_TX_PATTERN_EN_RESET 0x0 // 0
#define PHY_CTRL0_RX_PATTERN_EN_MSB 20
#define PHY_CTRL0_RX_PATTERN_EN_LSB 20
#define PHY_CTRL0_RX_PATTERN_EN_MASK 0x00100000
#define PHY_CTRL0_RX_PATTERN_EN_GET(x) (((x) & PHY_CTRL0_RX_PATTERN_EN_MASK) >> PHY_CTRL0_RX_PATTERN_EN_LSB)
#define PHY_CTRL0_RX_PATTERN_EN_SET(x) (((x) << PHY_CTRL0_RX_PATTERN_EN_LSB) & PHY_CTRL0_RX_PATTERN_EN_MASK)
#define PHY_CTRL0_RX_PATTERN_EN_RESET 0x0 // 0
#define PHY_CTRL0_TEST_SPEED_SELECT_MSB 19
#define PHY_CTRL0_TEST_SPEED_SELECT_LSB 19
#define PHY_CTRL0_TEST_SPEED_SELECT_MASK 0x00080000
#define PHY_CTRL0_TEST_SPEED_SELECT_GET(x) (((x) & PHY_CTRL0_TEST_SPEED_SELECT_MASK) >> PHY_CTRL0_TEST_SPEED_SELECT_LSB)
#define PHY_CTRL0_TEST_SPEED_SELECT_SET(x) (((x) << PHY_CTRL0_TEST_SPEED_SELECT_LSB) & PHY_CTRL0_TEST_SPEED_SELECT_MASK)
#define PHY_CTRL0_TEST_SPEED_SELECT_RESET 0x0 // 0
#define PHY_CTRL0_PLL_OVERIDE_MSB 18
#define PHY_CTRL0_PLL_OVERIDE_LSB 18
#define PHY_CTRL0_PLL_OVERIDE_MASK 0x00040000
#define PHY_CTRL0_PLL_OVERIDE_GET(x) (((x) & PHY_CTRL0_PLL_OVERIDE_MASK) >> PHY_CTRL0_PLL_OVERIDE_LSB)
#define PHY_CTRL0_PLL_OVERIDE_SET(x) (((x) << PHY_CTRL0_PLL_OVERIDE_LSB) & PHY_CTRL0_PLL_OVERIDE_MASK)
#define PHY_CTRL0_PLL_OVERIDE_RESET 0x0 // 0
#define PHY_CTRL0_PLL_MOD_MSB 17
#define PHY_CTRL0_PLL_MOD_LSB 15
#define PHY_CTRL0_PLL_MOD_MASK 0x00038000
#define PHY_CTRL0_PLL_MOD_GET(x) (((x) & PHY_CTRL0_PLL_MOD_MASK) >> PHY_CTRL0_PLL_MOD_LSB)
#define PHY_CTRL0_PLL_MOD_SET(x) (((x) << PHY_CTRL0_PLL_MOD_LSB) & PHY_CTRL0_PLL_MOD_MASK)
#define PHY_CTRL0_PLL_MOD_RESET 0x0 // 0
#define PHY_CTRL0_PLL_DIV_MSB 14
#define PHY_CTRL0_PLL_DIV_LSB 6
#define PHY_CTRL0_PLL_DIV_MASK 0x00007fc0
#define PHY_CTRL0_PLL_DIV_GET(x) (((x) & PHY_CTRL0_PLL_DIV_MASK) >> PHY_CTRL0_PLL_DIV_LSB)
#define PHY_CTRL0_PLL_DIV_SET(x) (((x) << PHY_CTRL0_PLL_DIV_LSB) & PHY_CTRL0_PLL_DIV_MASK)
#define PHY_CTRL0_PLL_DIV_RESET 0x0 // 0
#define PHY_CTRL0_PLL_RS_MSB 5
#define PHY_CTRL0_PLL_RS_LSB 3
#define PHY_CTRL0_PLL_RS_MASK 0x00000038
#define PHY_CTRL0_PLL_RS_GET(x) (((x) & PHY_CTRL0_PLL_RS_MASK) >> PHY_CTRL0_PLL_RS_LSB)
#define PHY_CTRL0_PLL_RS_SET(x) (((x) << PHY_CTRL0_PLL_RS_LSB) & PHY_CTRL0_PLL_RS_MASK)
#define PHY_CTRL0_PLL_RS_RESET 0x2 // 2
#define PHY_CTRL0_PLL_ICP_MSB 2
#define PHY_CTRL0_PLL_ICP_LSB 0
#define PHY_CTRL0_PLL_ICP_MASK 0x00000007
#define PHY_CTRL0_PLL_ICP_GET(x) (((x) & PHY_CTRL0_PLL_ICP_MASK) >> PHY_CTRL0_PLL_ICP_LSB)
#define PHY_CTRL0_PLL_ICP_SET(x) (((x) << PHY_CTRL0_PLL_ICP_LSB) & PHY_CTRL0_PLL_ICP_MASK)
#define PHY_CTRL0_PLL_ICP_RESET 0x5 // 5
#define PHY_CTRL0_ADDRESS 0x18116c80
#define PHY_CTRL0_OFFSET 0x0000
// SW modifiable bits
#define PHY_CTRL0_SW_MASK 0xffffffff
// bits defined at reset
#define PHY_CTRL0_RSTMASK 0xffffffff
// reset value (ignore bits undefined at reset)
#define PHY_CTRL0_RESET 0x00000015
#define PHY_CTRL1_PLL_OBS_MODE_N_MSB 31
#define PHY_CTRL1_PLL_OBS_MODE_N_LSB 31
#define PHY_CTRL1_PLL_OBS_MODE_N_MASK 0x80000000
#define PHY_CTRL1_PLL_OBS_MODE_N_GET(x) (((x) & PHY_CTRL1_PLL_OBS_MODE_N_MASK) >> PHY_CTRL1_PLL_OBS_MODE_N_LSB)
#define PHY_CTRL1_PLL_OBS_MODE_N_SET(x) (((x) << PHY_CTRL1_PLL_OBS_MODE_N_LSB) & PHY_CTRL1_PLL_OBS_MODE_N_MASK)
#define PHY_CTRL1_PLL_OBS_MODE_N_RESET 0x1 // 1
#define PHY_CTRL1_DISABLE_CLK_GATING_MSB 27
#define PHY_CTRL1_DISABLE_CLK_GATING_LSB 27
#define PHY_CTRL1_DISABLE_CLK_GATING_MASK 0x08000000
#define PHY_CTRL1_DISABLE_CLK_GATING_GET(x) (((x) & PHY_CTRL1_DISABLE_CLK_GATING_MASK) >> PHY_CTRL1_DISABLE_CLK_GATING_LSB)
#define PHY_CTRL1_DISABLE_CLK_GATING_SET(x) (((x) << PHY_CTRL1_DISABLE_CLK_GATING_LSB) & PHY_CTRL1_DISABLE_CLK_GATING_MASK)
#define PHY_CTRL1_DISABLE_CLK_GATING_RESET 0x0 // 0
#define PHY_CTRL1_ENABLE_REFCLK_GATE_MSB 26
#define PHY_CTRL1_ENABLE_REFCLK_GATE_LSB 26
#define PHY_CTRL1_ENABLE_REFCLK_GATE_MASK 0x04000000
#define PHY_CTRL1_ENABLE_REFCLK_GATE_GET(x) (((x) & PHY_CTRL1_ENABLE_REFCLK_GATE_MASK) >> PHY_CTRL1_ENABLE_REFCLK_GATE_LSB)
#define PHY_CTRL1_ENABLE_REFCLK_GATE_SET(x) (((x) << PHY_CTRL1_ENABLE_REFCLK_GATE_LSB) & PHY_CTRL1_ENABLE_REFCLK_GATE_MASK)
#define PHY_CTRL1_ENABLE_REFCLK_GATE_RESET 0x1 // 1
#define PHY_CTRL1_CLKOBS_SEL_MSB 25
#define PHY_CTRL1_CLKOBS_SEL_LSB 23
#define PHY_CTRL1_CLKOBS_SEL_MASK 0x03800000
#define PHY_CTRL1_CLKOBS_SEL_GET(x) (((x) & PHY_CTRL1_CLKOBS_SEL_MASK) >> PHY_CTRL1_CLKOBS_SEL_LSB)
#define PHY_CTRL1_CLKOBS_SEL_SET(x) (((x) << PHY_CTRL1_CLKOBS_SEL_LSB) & PHY_CTRL1_CLKOBS_SEL_MASK)
#define PHY_CTRL1_CLKOBS_SEL_RESET 0x0 // 0
#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MSB 22
#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB 21
#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK 0x00600000
#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_GET(x) (((x) & PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK) >> PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB)
#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_SET(x) (((x) << PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB) & PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK)
#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_RESET 0x3 // 3
#define PHY_CTRL1_USE_PLL_LOCKDETECT_MSB 20
#define PHY_CTRL1_USE_PLL_LOCKDETECT_LSB 20
#define PHY_CTRL1_USE_PLL_LOCKDETECT_MASK 0x00100000
#define PHY_CTRL1_USE_PLL_LOCKDETECT_GET(x) (((x) & PHY_CTRL1_USE_PLL_LOCKDETECT_MASK) >> PHY_CTRL1_USE_PLL_LOCKDETECT_LSB)
#define PHY_CTRL1_USE_PLL_LOCKDETECT_SET(x) (((x) << PHY_CTRL1_USE_PLL_LOCKDETECT_LSB) & PHY_CTRL1_USE_PLL_LOCKDETECT_MASK)
#define PHY_CTRL1_USE_PLL_LOCKDETECT_RESET 0x0 // 0
#define PHY_CTRL1_TX_PATTERN_SEL_MSB 19
#define PHY_CTRL1_TX_PATTERN_SEL_LSB 18
#define PHY_CTRL1_TX_PATTERN_SEL_MASK 0x000c0000
#define PHY_CTRL1_TX_PATTERN_SEL_GET(x) (((x) & PHY_CTRL1_TX_PATTERN_SEL_MASK) >> PHY_CTRL1_TX_PATTERN_SEL_LSB)
#define PHY_CTRL1_TX_PATTERN_SEL_SET(x) (((x) << PHY_CTRL1_TX_PATTERN_SEL_LSB) & PHY_CTRL1_TX_PATTERN_SEL_MASK)
#define PHY_CTRL1_TX_PATTERN_SEL_RESET 0x0 // 0
#define PHY_CTRL1_FORCE_SUSPEND_MSB 13
#define PHY_CTRL1_FORCE_SUSPEND_LSB 13
#define PHY_CTRL1_FORCE_SUSPEND_MASK 0x00002000
#define PHY_CTRL1_FORCE_SUSPEND_GET(x) (((x) & PHY_CTRL1_FORCE_SUSPEND_MASK) >> PHY_CTRL1_FORCE_SUSPEND_LSB)
#define PHY_CTRL1_FORCE_SUSPEND_SET(x) (((x) << PHY_CTRL1_FORCE_SUSPEND_LSB) & PHY_CTRL1_FORCE_SUSPEND_MASK)
#define PHY_CTRL1_FORCE_SUSPEND_RESET 0x0 // 0
#define PHY_CTRL1_NO_PLL_PWD_MSB 12
#define PHY_CTRL1_NO_PLL_PWD_LSB 12
#define PHY_CTRL1_NO_PLL_PWD_MASK 0x00001000
#define PHY_CTRL1_NO_PLL_PWD_GET(x) (((x) & PHY_CTRL1_NO_PLL_PWD_MASK) >> PHY_CTRL1_NO_PLL_PWD_LSB)
#define PHY_CTRL1_NO_PLL_PWD_SET(x) (((x) << PHY_CTRL1_NO_PLL_PWD_LSB) & PHY_CTRL1_NO_PLL_PWD_MASK)
#define PHY_CTRL1_NO_PLL_PWD_RESET 0x0 // 0
#define PHY_CTRL1_RX_RSVD_MSB 11
#define PHY_CTRL1_RX_RSVD_LSB 9
#define PHY_CTRL1_RX_RSVD_MASK 0x00000e00
#define PHY_CTRL1_RX_RSVD_GET(x) (((x) & PHY_CTRL1_RX_RSVD_MASK) >> PHY_CTRL1_RX_RSVD_LSB)
#define PHY_CTRL1_RX_RSVD_SET(x) (((x) << PHY_CTRL1_RX_RSVD_LSB) & PHY_CTRL1_RX_RSVD_MASK)
#define PHY_CTRL1_RX_RSVD_RESET 0x0 // 0
#define PHY_CTRL1_RX_SELVREF0P25_MSB 8
#define PHY_CTRL1_RX_SELVREF0P25_LSB 8
#define PHY_CTRL1_RX_SELVREF0P25_MASK 0x00000100
#define PHY_CTRL1_RX_SELVREF0P25_GET(x) (((x) & PHY_CTRL1_RX_SELVREF0P25_MASK) >> PHY_CTRL1_RX_SELVREF0P25_LSB)
#define PHY_CTRL1_RX_SELVREF0P25_SET(x) (((x) << PHY_CTRL1_RX_SELVREF0P25_LSB) & PHY_CTRL1_RX_SELVREF0P25_MASK)
#define PHY_CTRL1_RX_SELVREF0P25_RESET 0x0 // 0
#define PHY_CTRL1_RX_SELVREF0P6_MSB 7
#define PHY_CTRL1_RX_SELVREF0P6_LSB 7
#define PHY_CTRL1_RX_SELVREF0P6_MASK 0x00000080
#define PHY_CTRL1_RX_SELVREF0P6_GET(x) (((x) & PHY_CTRL1_RX_SELVREF0P6_MASK) >> PHY_CTRL1_RX_SELVREF0P6_LSB)
#define PHY_CTRL1_RX_SELVREF0P6_SET(x) (((x) << PHY_CTRL1_RX_SELVREF0P6_LSB) & PHY_CTRL1_RX_SELVREF0P6_MASK)
#define PHY_CTRL1_RX_SELVREF0P6_RESET 0x1 // 1
#define PHY_CTRL1_RX_SELIR_100M_MSB 6
#define PHY_CTRL1_RX_SELIR_100M_LSB 5
#define PHY_CTRL1_RX_SELIR_100M_MASK 0x00000060
#define PHY_CTRL1_RX_SELIR_100M_GET(x) (((x) & PHY_CTRL1_RX_SELIR_100M_MASK) >> PHY_CTRL1_RX_SELIR_100M_LSB)
#define PHY_CTRL1_RX_SELIR_100M_SET(x) (((x) << PHY_CTRL1_RX_SELIR_100M_LSB) & PHY_CTRL1_RX_SELIR_100M_MASK)
#define PHY_CTRL1_RX_SELIR_100M_RESET 0x0 // 0
#define PHY_CTRL1_RX_LOWR_PDET_MSB 4
#define PHY_CTRL1_RX_LOWR_PDET_LSB 4
#define PHY_CTRL1_RX_LOWR_PDET_MASK 0x00000010
#define PHY_CTRL1_RX_LOWR_PDET_GET(x) (((x) & PHY_CTRL1_RX_LOWR_PDET_MASK) >> PHY_CTRL1_RX_LOWR_PDET_LSB)
#define PHY_CTRL1_RX_LOWR_PDET_SET(x) (((x) << PHY_CTRL1_RX_LOWR_PDET_LSB) & PHY_CTRL1_RX_LOWR_PDET_MASK)
#define PHY_CTRL1_RX_LOWR_PDET_RESET 0x1 // 1
#define PHY_CTRL1_RX_BYPASSEQ_MSB 3
#define PHY_CTRL1_RX_BYPASSEQ_LSB 3
#define PHY_CTRL1_RX_BYPASSEQ_MASK 0x00000008
#define PHY_CTRL1_RX_BYPASSEQ_GET(x) (((x) & PHY_CTRL1_RX_BYPASSEQ_MASK) >> PHY_CTRL1_RX_BYPASSEQ_LSB)
#define PHY_CTRL1_RX_BYPASSEQ_SET(x) (((x) << PHY_CTRL1_RX_BYPASSEQ_LSB) & PHY_CTRL1_RX_BYPASSEQ_MASK)
#define PHY_CTRL1_RX_BYPASSEQ_RESET 0x0 // 0
#define PHY_CTRL1_RX_FORCERXON_MSB 2
#define PHY_CTRL1_RX_FORCERXON_LSB 2
#define PHY_CTRL1_RX_FORCERXON_MASK 0x00000004
#define PHY_CTRL1_RX_FORCERXON_GET(x) (((x) & PHY_CTRL1_RX_FORCERXON_MASK) >> PHY_CTRL1_RX_FORCERXON_LSB)
#define PHY_CTRL1_RX_FORCERXON_SET(x) (((x) << PHY_CTRL1_RX_FORCERXON_LSB) & PHY_CTRL1_RX_FORCERXON_MASK)
#define PHY_CTRL1_RX_FORCERXON_RESET 0x1 // 1
#define PHY_CTRL1_RX_FILBW_SEL_MSB 1
#define PHY_CTRL1_RX_FILBW_SEL_LSB 0
#define PHY_CTRL1_RX_FILBW_SEL_MASK 0x00000003
#define PHY_CTRL1_RX_FILBW_SEL_GET(x) (((x) & PHY_CTRL1_RX_FILBW_SEL_MASK) >> PHY_CTRL1_RX_FILBW_SEL_LSB)
#define PHY_CTRL1_RX_FILBW_SEL_SET(x) (((x) << PHY_CTRL1_RX_FILBW_SEL_LSB) & PHY_CTRL1_RX_FILBW_SEL_MASK)
#define PHY_CTRL1_RX_FILBW_SEL_RESET 0x1 // 1
#define PHY_CTRL1_ADDRESS 0x18116c84
#define PHY_CTRL1_OFFSET 0x0004
// SW modifiable bits
#define PHY_CTRL1_SW_MASK 0x8ffc3fff
// bits defined at reset
#define PHY_CTRL1_RSTMASK 0xffffffff
// reset value (ignore bits undefined at reset)
#define PHY_CTRL1_RESET 0x84600095
#define PHY_CTRL2_PWD_EXTBIAS_MSB 31
#define PHY_CTRL2_PWD_EXTBIAS_LSB 31
#define PHY_CTRL2_PWD_EXTBIAS_MASK 0x80000000
#define PHY_CTRL2_PWD_EXTBIAS_GET(x) (((x) & PHY_CTRL2_PWD_EXTBIAS_MASK) >> PHY_CTRL2_PWD_EXTBIAS_LSB)
#define PHY_CTRL2_PWD_EXTBIAS_SET(x) (((x) << PHY_CTRL2_PWD_EXTBIAS_LSB) & PHY_CTRL2_PWD_EXTBIAS_MASK)
#define PHY_CTRL2_PWD_EXTBIAS_RESET 0x0 // 0
#define PHY_CTRL2_TX_RSVD_MSB 30
#define PHY_CTRL2_TX_RSVD_LSB 27
#define PHY_CTRL2_TX_RSVD_MASK 0x78000000
#define PHY_CTRL2_TX_RSVD_GET(x) (((x) & PHY_CTRL2_TX_RSVD_MASK) >> PHY_CTRL2_TX_RSVD_LSB)
#define PHY_CTRL2_TX_RSVD_SET(x) (((x) << PHY_CTRL2_TX_RSVD_LSB) & PHY_CTRL2_TX_RSVD_MASK)
#define PHY_CTRL2_TX_RSVD_RESET 0x0 // 0
#define PHY_CTRL2_TX_LCKDET_OVR_MSB 26
#define PHY_CTRL2_TX_LCKDET_OVR_LSB 26
#define PHY_CTRL2_TX_LCKDET_OVR_MASK 0x04000000
#define PHY_CTRL2_TX_LCKDET_OVR_GET(x) (((x) & PHY_CTRL2_TX_LCKDET_OVR_MASK) >> PHY_CTRL2_TX_LCKDET_OVR_LSB)
#define PHY_CTRL2_TX_LCKDET_OVR_SET(x) (((x) << PHY_CTRL2_TX_LCKDET_OVR_LSB) & PHY_CTRL2_TX_LCKDET_OVR_MASK)
#define PHY_CTRL2_TX_LCKDET_OVR_RESET 0x0 // 0
#define PHY_CTRL2_TX_MAN_CAL_MSB 25
#define PHY_CTRL2_TX_MAN_CAL_LSB 22
#define PHY_CTRL2_TX_MAN_CAL_MASK 0x03c00000
#define PHY_CTRL2_TX_MAN_CAL_GET(x) (((x) & PHY_CTRL2_TX_MAN_CAL_MASK) >> PHY_CTRL2_TX_MAN_CAL_LSB)
#define PHY_CTRL2_TX_MAN_CAL_SET(x) (((x) << PHY_CTRL2_TX_MAN_CAL_LSB) & PHY_CTRL2_TX_MAN_CAL_MASK)
#define PHY_CTRL2_TX_MAN_CAL_RESET 0x3 // 3
#define PHY_CTRL2_TX_CAL_SEL_MSB 21
#define PHY_CTRL2_TX_CAL_SEL_LSB 21
#define PHY_CTRL2_TX_CAL_SEL_MASK 0x00200000
#define PHY_CTRL2_TX_CAL_SEL_GET(x) (((x) & PHY_CTRL2_TX_CAL_SEL_MASK) >> PHY_CTRL2_TX_CAL_SEL_LSB)
#define PHY_CTRL2_TX_CAL_SEL_SET(x) (((x) << PHY_CTRL2_TX_CAL_SEL_LSB) & PHY_CTRL2_TX_CAL_SEL_MASK)
#define PHY_CTRL2_TX_CAL_SEL_RESET 0x1 // 1
#define PHY_CTRL2_TX_CAL_EN_MSB 20
#define PHY_CTRL2_TX_CAL_EN_LSB 20
#define PHY_CTRL2_TX_CAL_EN_MASK 0x00100000
#define PHY_CTRL2_TX_CAL_EN_GET(x) (((x) & PHY_CTRL2_TX_CAL_EN_MASK) >> PHY_CTRL2_TX_CAL_EN_LSB)
#define PHY_CTRL2_TX_CAL_EN_SET(x) (((x) << PHY_CTRL2_TX_CAL_EN_LSB) & PHY_CTRL2_TX_CAL_EN_MASK)
#define PHY_CTRL2_TX_CAL_EN_RESET 0x1 // 1
#define PHY_CTRL2_PWD_ISP_MSB 13
#define PHY_CTRL2_PWD_ISP_LSB 8
#define PHY_CTRL2_PWD_ISP_MASK 0x00003f00
#define PHY_CTRL2_PWD_ISP_GET(x) (((x) & PHY_CTRL2_PWD_ISP_MASK) >> PHY_CTRL2_PWD_ISP_LSB)
#define PHY_CTRL2_PWD_ISP_SET(x) (((x) << PHY_CTRL2_PWD_ISP_LSB) & PHY_CTRL2_PWD_ISP_MASK)
#define PHY_CTRL2_PWD_ISP_RESET 0x1b // 27
#define PHY_CTRL2_PWD_IPLL_MSB 7
#define PHY_CTRL2_PWD_IPLL_LSB 2
#define PHY_CTRL2_PWD_IPLL_MASK 0x000000fc
#define PHY_CTRL2_PWD_IPLL_GET(x) (((x) & PHY_CTRL2_PWD_IPLL_MASK) >> PHY_CTRL2_PWD_IPLL_LSB)
#define PHY_CTRL2_PWD_IPLL_SET(x) (((x) << PHY_CTRL2_PWD_IPLL_LSB) & PHY_CTRL2_PWD_IPLL_MASK)
#define PHY_CTRL2_PWD_IPLL_RESET 0x1b // 27
#define PHY_CTRL2_HSRXPHASE_PS_EN_MSB 1
#define PHY_CTRL2_HSRXPHASE_PS_EN_LSB 1
#define PHY_CTRL2_HSRXPHASE_PS_EN_MASK 0x00000002
#define PHY_CTRL2_HSRXPHASE_PS_EN_GET(x) (((x) & PHY_CTRL2_HSRXPHASE_PS_EN_MASK) >> PHY_CTRL2_HSRXPHASE_PS_EN_LSB)
#define PHY_CTRL2_HSRXPHASE_PS_EN_SET(x) (((x) << PHY_CTRL2_HSRXPHASE_PS_EN_LSB) & PHY_CTRL2_HSRXPHASE_PS_EN_MASK)
#define PHY_CTRL2_HSRXPHASE_PS_EN_RESET 0x0 // 0
#define PHY_CTRL2_HSTXBIAS_PS_EN_MSB 0
#define PHY_CTRL2_HSTXBIAS_PS_EN_LSB 0
#define PHY_CTRL2_HSTXBIAS_PS_EN_MASK 0x00000001
#define PHY_CTRL2_HSTXBIAS_PS_EN_GET(x) (((x) & PHY_CTRL2_HSTXBIAS_PS_EN_MASK) >> PHY_CTRL2_HSTXBIAS_PS_EN_LSB)
#define PHY_CTRL2_HSTXBIAS_PS_EN_SET(x) (((x) << PHY_CTRL2_HSTXBIAS_PS_EN_LSB) & PHY_CTRL2_HSTXBIAS_PS_EN_MASK)
#define PHY_CTRL2_HSTXBIAS_PS_EN_RESET 0x0 // 0
#define PHY_CTRL2_ADDRESS 0x18116c88
#define PHY_CTRL2_OFFSET 0x0008
// SW modifiable bits
#define PHY_CTRL2_SW_MASK 0xfff03fff
// bits defined at reset
#define PHY_CTRL2_RSTMASK 0xffffffff
// reset value (ignore bits undefined at reset)
#define PHY_CTRL2_RESET 0x00f01b6c
#define PHY_CTRL3_SPARE_BITS_MSB 31
#define PHY_CTRL3_SPARE_BITS_LSB 27
#define PHY_CTRL3_SPARE_BITS_MASK 0xf8000000
#define PHY_CTRL3_SPARE_BITS_GET(x) (((x) & PHY_CTRL3_SPARE_BITS_MASK) >> PHY_CTRL3_SPARE_BITS_LSB)
#define PHY_CTRL3_SPARE_BITS_SET(x) (((x) << PHY_CTRL3_SPARE_BITS_LSB) & PHY_CTRL3_SPARE_BITS_MASK)
#define PHY_CTRL3_SPARE_BITS_RESET 0x0 // 0
#define PHY_CTRL3_SUS_RES_FIX_DIS_MSB 26
#define PHY_CTRL3_SUS_RES_FIX_DIS_LSB 26
#define PHY_CTRL3_SUS_RES_FIX_DIS_MASK 0x04000000
#define PHY_CTRL3_SUS_RES_FIX_DIS_GET(x) (((x) & PHY_CTRL3_SUS_RES_FIX_DIS_MASK) >> PHY_CTRL3_SUS_RES_FIX_DIS_LSB)
#define PHY_CTRL3_SUS_RES_FIX_DIS_SET(x) (((x) << PHY_CTRL3_SUS_RES_FIX_DIS_LSB) & PHY_CTRL3_SUS_RES_FIX_DIS_MASK)
#define PHY_CTRL3_SUS_RES_FIX_DIS_RESET 0x0 // 0
#define PHY_CTRL3_TX_STARTCAL_MSB 25
#define PHY_CTRL3_TX_STARTCAL_LSB 25
#define PHY_CTRL3_TX_STARTCAL_MASK 0x02000000
#define PHY_CTRL3_TX_STARTCAL_GET(x) (((x) & PHY_CTRL3_TX_STARTCAL_MASK) >> PHY_CTRL3_TX_STARTCAL_LSB)
#define PHY_CTRL3_TX_STARTCAL_SET(x) (((x) << PHY_CTRL3_TX_STARTCAL_LSB) & PHY_CTRL3_TX_STARTCAL_MASK)
#define PHY_CTRL3_TX_STARTCAL_RESET 0x0 // 0
#define PHY_CTRL3_TX_SELTEST_MSB 24
#define PHY_CTRL3_TX_SELTEST_LSB 22
#define PHY_CTRL3_TX_SELTEST_MASK 0x01c00000
#define PHY_CTRL3_TX_SELTEST_GET(x) (((x) & PHY_CTRL3_TX_SELTEST_MASK) >> PHY_CTRL3_TX_SELTEST_LSB)
#define PHY_CTRL3_TX_SELTEST_SET(x) (((x) << PHY_CTRL3_TX_SELTEST_LSB) & PHY_CTRL3_TX_SELTEST_MASK)
#define PHY_CTRL3_TX_SELTEST_RESET 0x0 // 0
#define PHY_CTRL3_TX_DISABLE_SHORT_DET_MSB 21
#define PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB 21
#define PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK 0x00200000
#define PHY_CTRL3_TX_DISABLE_SHORT_DET_GET(x) (((x) & PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK) >> PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB)
#define PHY_CTRL3_TX_DISABLE_SHORT_DET_SET(x) (((x) << PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB) & PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK)
#define PHY_CTRL3_TX_DISABLE_SHORT_DET_RESET 0x0 // 0
#define PHY_CTRL3_PWD_ITX_MSB 18
#define PHY_CTRL3_PWD_ITX_LSB 0
#define PHY_CTRL3_PWD_ITX_MASK 0x0007ffff
#define PHY_CTRL3_PWD_ITX_GET(x) (((x) & PHY_CTRL3_PWD_ITX_MASK) >> PHY_CTRL3_PWD_ITX_LSB)
#define PHY_CTRL3_PWD_ITX_SET(x) (((x) << PHY_CTRL3_PWD_ITX_LSB) & PHY_CTRL3_PWD_ITX_MASK)
#define PHY_CTRL3_PWD_ITX_RESET 0x14765 // 83813
#define PHY_CTRL3_ADDRESS 0x18116c8c
#define PHY_CTRL3_OFFSET 0x000c
// SW modifiable bits
#define PHY_CTRL3_SW_MASK 0xffe7ffff
// bits defined at reset
#define PHY_CTRL3_RSTMASK 0xffffffff
// reset value (ignore bits undefined at reset)
#define PHY_CTRL3_RESET 0x00014765
#define PHY_CTRL4_PPRBS_ERR_CNT_MSB 31
#define PHY_CTRL4_PPRBS_ERR_CNT_LSB 24
#define PHY_CTRL4_PPRBS_ERR_CNT_MASK 0xff000000
#define PHY_CTRL4_PPRBS_ERR_CNT_GET(x) (((x) & PHY_CTRL4_PPRBS_ERR_CNT_MASK) >> PHY_CTRL4_PPRBS_ERR_CNT_LSB)
#define PHY_CTRL4_PPRBS_ERR_CNT_SET(x) (((x) << PHY_CTRL4_PPRBS_ERR_CNT_LSB) & PHY_CTRL4_PPRBS_ERR_CNT_MASK)
#define PHY_CTRL4_PPRBS_ERR_CNT_RESET 0x0 // 0
#define PHY_CTRL4_LS_PRBS_EN_MSB 21
#define PHY_CTRL4_LS_PRBS_EN_LSB 21
#define PHY_CTRL4_LS_PRBS_EN_MASK 0x00200000
#define PHY_CTRL4_LS_PRBS_EN_GET(x) (((x) & PHY_CTRL4_LS_PRBS_EN_MASK) >> PHY_CTRL4_LS_PRBS_EN_LSB)
#define PHY_CTRL4_LS_PRBS_EN_SET(x) (((x) << PHY_CTRL4_LS_PRBS_EN_LSB) & PHY_CTRL4_LS_PRBS_EN_MASK)
#define PHY_CTRL4_LS_PRBS_EN_RESET 0x0 // 0
#define PHY_CTRL4_PPRBS_TERM_SEL_MSB 20
#define PHY_CTRL4_PPRBS_TERM_SEL_LSB 20
#define PHY_CTRL4_PPRBS_TERM_SEL_MASK 0x00100000
#define PHY_CTRL4_PPRBS_TERM_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_TERM_SEL_MASK) >> PHY_CTRL4_PPRBS_TERM_SEL_LSB)
#define PHY_CTRL4_PPRBS_TERM_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_TERM_SEL_LSB) & PHY_CTRL4_PPRBS_TERM_SEL_MASK)
#define PHY_CTRL4_PPRBS_TERM_SEL_RESET 0x0 // 0
#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_MSB 19
#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB 19
#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK 0x00080000
#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK) >> PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB)
#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB) & PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK)
#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_RESET 0x0 // 0
#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_MSB 18
#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB 18
#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK 0x00040000
#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK) >> PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB)
#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB) & PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK)
#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_RESET 0x0 // 0
#define PHY_CTRL4_PPRBS_PAT_SEL_MSB 17
#define PHY_CTRL4_PPRBS_PAT_SEL_LSB 16
#define PHY_CTRL4_PPRBS_PAT_SEL_MASK 0x00030000
#define PHY_CTRL4_PPRBS_PAT_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_PAT_SEL_MASK) >> PHY_CTRL4_PPRBS_PAT_SEL_LSB)
#define PHY_CTRL4_PPRBS_PAT_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_PAT_SEL_LSB) & PHY_CTRL4_PPRBS_PAT_SEL_MASK)
#define PHY_CTRL4_PPRBS_PAT_SEL_RESET 0x0 // 0
#define PHY_CTRL4_PPRBS_TX_EN_MSB 15
#define PHY_CTRL4_PPRBS_TX_EN_LSB 15
#define PHY_CTRL4_PPRBS_TX_EN_MASK 0x00008000
#define PHY_CTRL4_PPRBS_TX_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_TX_EN_MASK) >> PHY_CTRL4_PPRBS_TX_EN_LSB)
#define PHY_CTRL4_PPRBS_TX_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_TX_EN_LSB) & PHY_CTRL4_PPRBS_TX_EN_MASK)
#define PHY_CTRL4_PPRBS_TX_EN_RESET 0x0 // 0
#define PHY_CTRL4_PPRBS_RX_EN_MSB 14
#define PHY_CTRL4_PPRBS_RX_EN_LSB 14
#define PHY_CTRL4_PPRBS_RX_EN_MASK 0x00004000
#define PHY_CTRL4_PPRBS_RX_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_RX_EN_MASK) >> PHY_CTRL4_PPRBS_RX_EN_LSB)
#define PHY_CTRL4_PPRBS_RX_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_RX_EN_LSB) & PHY_CTRL4_PPRBS_RX_EN_MASK)
#define PHY_CTRL4_PPRBS_RX_EN_RESET 0x0 // 0
#define PHY_CTRL4_PPRBS_SPEED_SEL_MSB 13
#define PHY_CTRL4_PPRBS_SPEED_SEL_LSB 13
#define PHY_CTRL4_PPRBS_SPEED_SEL_MASK 0x00002000
#define PHY_CTRL4_PPRBS_SPEED_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_SPEED_SEL_MASK) >> PHY_CTRL4_PPRBS_SPEED_SEL_LSB)
#define PHY_CTRL4_PPRBS_SPEED_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_SPEED_SEL_LSB) & PHY_CTRL4_PPRBS_SPEED_SEL_MASK)
#define PHY_CTRL4_PPRBS_SPEED_SEL_RESET 0x0 // 0
#define PHY_CTRL4_PPRBS_RX_INV_MSB 12
#define PHY_CTRL4_PPRBS_RX_INV_LSB 12
#define PHY_CTRL4_PPRBS_RX_INV_MASK 0x00001000
#define PHY_CTRL4_PPRBS_RX_INV_GET(x) (((x) & PHY_CTRL4_PPRBS_RX_INV_MASK) >> PHY_CTRL4_PPRBS_RX_INV_LSB)
#define PHY_CTRL4_PPRBS_RX_INV_SET(x) (((x) << PHY_CTRL4_PPRBS_RX_INV_LSB) & PHY_CTRL4_PPRBS_RX_INV_MASK)
#define PHY_CTRL4_PPRBS_RX_INV_RESET 0x0 // 0
#define PHY_CTRL4_PWD_IRX_MSB 11
#define PHY_CTRL4_PWD_IRX_LSB 0
#define PHY_CTRL4_PWD_IRX_MASK 0x00000fff
#define PHY_CTRL4_PWD_IRX_GET(x) (((x) & PHY_CTRL4_PWD_IRX_MASK) >> PHY_CTRL4_PWD_IRX_LSB)
#define PHY_CTRL4_PWD_IRX_SET(x) (((x) << PHY_CTRL4_PWD_IRX_LSB) & PHY_CTRL4_PWD_IRX_MASK)
#define PHY_CTRL4_PWD_IRX_RESET 0x6dd // 1757
#define PHY_CTRL4_ADDRESS 0x18116c90
#define PHY_CTRL4_OFFSET 0x0010
// SW modifiable bits
#define PHY_CTRL4_SW_MASK 0xff3fffff
// bits defined at reset
#define PHY_CTRL4_RSTMASK 0xffffffff
// reset value (ignore bits undefined at reset)
#define PHY_CTRL4_RESET 0x000006dd
#define PHY_CTRL5_SPARE_BITS_MSB 31
#define PHY_CTRL5_SPARE_BITS_LSB 30
#define PHY_CTRL5_SPARE_BITS_MASK 0xc0000000
#define PHY_CTRL5_SPARE_BITS_GET(x) (((x) & PHY_CTRL5_SPARE_BITS_MASK) >> PHY_CTRL5_SPARE_BITS_LSB)
#define PHY_CTRL5_SPARE_BITS_SET(x) (((x) << PHY_CTRL5_SPARE_BITS_LSB) & PHY_CTRL5_SPARE_BITS_MASK)
#define PHY_CTRL5_SPARE_BITS_RESET 0x0 // 0
#define PHY_CTRL5_HOST_RES_FIX_EN_MSB 29
#define PHY_CTRL5_HOST_RES_FIX_EN_LSB 29
#define PHY_CTRL5_HOST_RES_FIX_EN_MASK 0x20000000
#define PHY_CTRL5_HOST_RES_FIX_EN_GET(x) (((x) & PHY_CTRL5_HOST_RES_FIX_EN_MASK) >> PHY_CTRL5_HOST_RES_FIX_EN_LSB)
#define PHY_CTRL5_HOST_RES_FIX_EN_SET(x) (((x) << PHY_CTRL5_HOST_RES_FIX_EN_LSB) & PHY_CTRL5_HOST_RES_FIX_EN_MASK)
#define PHY_CTRL5_HOST_RES_FIX_EN_RESET 0x1 // 1
#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MSB 28
#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB 26
#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK 0x1c000000
#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK) >> PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB)
#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB) & PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK)
#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_RESET 0x6 // 6
#define PHY_CTRL5_HOST_DISCON_DETECT_ON_MSB 25
#define PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB 25
#define PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK 0x02000000
#define PHY_CTRL5_HOST_DISCON_DETECT_ON_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK) >> PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB)
#define PHY_CTRL5_HOST_DISCON_DETECT_ON_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB) & PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK)
#define PHY_CTRL5_HOST_DISCON_DETECT_ON_RESET 0x1 // 1
#define PHY_CTRL5_HOST_DISCON_FIX_ON_MSB 24
#define PHY_CTRL5_HOST_DISCON_FIX_ON_LSB 24
#define PHY_CTRL5_HOST_DISCON_FIX_ON_MASK 0x01000000
#define PHY_CTRL5_HOST_DISCON_FIX_ON_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_FIX_ON_MASK) >> PHY_CTRL5_HOST_DISCON_FIX_ON_LSB)
#define PHY_CTRL5_HOST_DISCON_FIX_ON_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_FIX_ON_LSB) & PHY_CTRL5_HOST_DISCON_FIX_ON_MASK)
#define PHY_CTRL5_HOST_DISCON_FIX_ON_RESET 0x1 // 1
#define PHY_CTRL5_DM_PULLDOWN_MSB 23
#define PHY_CTRL5_DM_PULLDOWN_LSB 23
#define PHY_CTRL5_DM_PULLDOWN_MASK 0x00800000
#define PHY_CTRL5_DM_PULLDOWN_GET(x) (((x) & PHY_CTRL5_DM_PULLDOWN_MASK) >> PHY_CTRL5_DM_PULLDOWN_LSB)
#define PHY_CTRL5_DM_PULLDOWN_SET(x) (((x) << PHY_CTRL5_DM_PULLDOWN_LSB) & PHY_CTRL5_DM_PULLDOWN_MASK)
#define PHY_CTRL5_DM_PULLDOWN_RESET 0x0 // 0
#define PHY_CTRL5_DP_PULLDOWN_MSB 22
#define PHY_CTRL5_DP_PULLDOWN_LSB 22
#define PHY_CTRL5_DP_PULLDOWN_MASK 0x00400000
#define PHY_CTRL5_DP_PULLDOWN_GET(x) (((x) & PHY_CTRL5_DP_PULLDOWN_MASK) >> PHY_CTRL5_DP_PULLDOWN_LSB)
#define PHY_CTRL5_DP_PULLDOWN_SET(x) (((x) << PHY_CTRL5_DP_PULLDOWN_LSB) & PHY_CTRL5_DP_PULLDOWN_MASK)
#define PHY_CTRL5_DP_PULLDOWN_RESET 0x0 // 0
#define PHY_CTRL5_SUSPEND_N_MSB 21
#define PHY_CTRL5_SUSPEND_N_LSB 21
#define PHY_CTRL5_SUSPEND_N_MASK 0x00200000
#define PHY_CTRL5_SUSPEND_N_GET(x) (((x) & PHY_CTRL5_SUSPEND_N_MASK) >> PHY_CTRL5_SUSPEND_N_LSB)
#define PHY_CTRL5_SUSPEND_N_SET(x) (((x) << PHY_CTRL5_SUSPEND_N_LSB) & PHY_CTRL5_SUSPEND_N_MASK)
#define PHY_CTRL5_SUSPEND_N_RESET 0x1 // 1
#define PHY_CTRL5_TERM_SEL_MSB 20
#define PHY_CTRL5_TERM_SEL_LSB 20
#define PHY_CTRL5_TERM_SEL_MASK 0x00100000
#define PHY_CTRL5_TERM_SEL_GET(x) (((x) & PHY_CTRL5_TERM_SEL_MASK) >> PHY_CTRL5_TERM_SEL_LSB)
#define PHY_CTRL5_TERM_SEL_SET(x) (((x) << PHY_CTRL5_TERM_SEL_LSB) & PHY_CTRL5_TERM_SEL_MASK)
#define PHY_CTRL5_TERM_SEL_RESET 0x0 // 0
#define PHY_CTRL5_XCVR_SEL_MSB 19
#define PHY_CTRL5_XCVR_SEL_LSB 18
#define PHY_CTRL5_XCVR_SEL_MASK 0x000c0000
#define PHY_CTRL5_XCVR_SEL_GET(x) (((x) & PHY_CTRL5_XCVR_SEL_MASK) >> PHY_CTRL5_XCVR_SEL_LSB)
#define PHY_CTRL5_XCVR_SEL_SET(x) (((x) << PHY_CTRL5_XCVR_SEL_LSB) & PHY_CTRL5_XCVR_SEL_MASK)
#define PHY_CTRL5_XCVR_SEL_RESET 0x0 // 0
#define PHY_CTRL5_TEST_JK_OVERRIDE_MSB 17
#define PHY_CTRL5_TEST_JK_OVERRIDE_LSB 17
#define PHY_CTRL5_TEST_JK_OVERRIDE_MASK 0x00020000
#define PHY_CTRL5_TEST_JK_OVERRIDE_GET(x) (((x) & PHY_CTRL5_TEST_JK_OVERRIDE_MASK) >> PHY_CTRL5_TEST_JK_OVERRIDE_LSB)
#define PHY_CTRL5_TEST_JK_OVERRIDE_SET(x) (((x) << PHY_CTRL5_TEST_JK_OVERRIDE_LSB) & PHY_CTRL5_TEST_JK_OVERRIDE_MASK)
#define PHY_CTRL5_TEST_JK_OVERRIDE_RESET 0x0 // 0
#define PHY_CTRL5_FORCE_TEST_SE0_NAK_MSB 16
#define PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB 16
#define PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK 0x00010000
#define PHY_CTRL5_FORCE_TEST_SE0_NAK_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK) >> PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB)
#define PHY_CTRL5_FORCE_TEST_SE0_NAK_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB) & PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK)
#define PHY_CTRL5_FORCE_TEST_SE0_NAK_RESET 0x0 // 0
#define PHY_CTRL5_FORCE_TEST_K_MSB 15
#define PHY_CTRL5_FORCE_TEST_K_LSB 15
#define PHY_CTRL5_FORCE_TEST_K_MASK 0x00008000
#define PHY_CTRL5_FORCE_TEST_K_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_K_MASK) >> PHY_CTRL5_FORCE_TEST_K_LSB)
#define PHY_CTRL5_FORCE_TEST_K_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_K_LSB) & PHY_CTRL5_FORCE_TEST_K_MASK)
#define PHY_CTRL5_FORCE_TEST_K_RESET 0x0 // 0
#define PHY_CTRL5_FORCE_TEST_J_MSB 14
#define PHY_CTRL5_FORCE_TEST_J_LSB 14
#define PHY_CTRL5_FORCE_TEST_J_MASK 0x00004000
#define PHY_CTRL5_FORCE_TEST_J_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_J_MASK) >> PHY_CTRL5_FORCE_TEST_J_LSB)
#define PHY_CTRL5_FORCE_TEST_J_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_J_LSB) & PHY_CTRL5_FORCE_TEST_J_MASK)
#define PHY_CTRL5_FORCE_TEST_J_RESET 0x0 // 0
#define PHY_CTRL5_FORCE_IDDQ_MSB 13
#define PHY_CTRL5_FORCE_IDDQ_LSB 13
#define PHY_CTRL5_FORCE_IDDQ_MASK 0x00002000
#define PHY_CTRL5_FORCE_IDDQ_GET(x) (((x) & PHY_CTRL5_FORCE_IDDQ_MASK) >> PHY_CTRL5_FORCE_IDDQ_LSB)
#define PHY_CTRL5_FORCE_IDDQ_SET(x) (((x) << PHY_CTRL5_FORCE_IDDQ_LSB) & PHY_CTRL5_FORCE_IDDQ_MASK)
#define PHY_CTRL5_FORCE_IDDQ_RESET 0x0 // 0
#define PHY_CTRL5_EB_WATERMARK_MSB 12
#define PHY_CTRL5_EB_WATERMARK_LSB 7
#define PHY_CTRL5_EB_WATERMARK_MASK 0x00001f80
#define PHY_CTRL5_EB_WATERMARK_GET(x) (((x) & PHY_CTRL5_EB_WATERMARK_MASK) >> PHY_CTRL5_EB_WATERMARK_LSB)
#define PHY_CTRL5_EB_WATERMARK_SET(x) (((x) << PHY_CTRL5_EB_WATERMARK_LSB) & PHY_CTRL5_EB_WATERMARK_MASK)
#define PHY_CTRL5_EB_WATERMARK_RESET 0x14 // 20
#define PHY_CTRL5_TX_BIAS_DELAY_MSB 6
#define PHY_CTRL5_TX_BIAS_DELAY_LSB 0
#define PHY_CTRL5_TX_BIAS_DELAY_MASK 0x0000007f
#define PHY_CTRL5_TX_BIAS_DELAY_GET(x) (((x) & PHY_CTRL5_TX_BIAS_DELAY_MASK) >> PHY_CTRL5_TX_BIAS_DELAY_LSB)
#define PHY_CTRL5_TX_BIAS_DELAY_SET(x) (((x) << PHY_CTRL5_TX_BIAS_DELAY_LSB) & PHY_CTRL5_TX_BIAS_DELAY_MASK)
#define PHY_CTRL5_TX_BIAS_DELAY_RESET 0x32 // 50
#define PHY_CTRL5_ADDRESS 0x18116c94
#define PHY_CTRL5_OFFSET 0x0014
// SW modifiable bits
#define PHY_CTRL5_SW_MASK 0xffffffff
// bits defined at reset
#define PHY_CTRL5_RSTMASK 0xffffffff
// reset value (ignore bits undefined at reset)
#define PHY_CTRL5_RESET 0x3b200a32
#define PHY_CTRL5_RESET_1 0x3b202a58
#define PHY_CTRL6_SPARE_BITS_MSB 31
#define PHY_CTRL6_SPARE_BITS_LSB 9
#define PHY_CTRL6_SPARE_BITS_MASK 0xfffffe00
#define PHY_CTRL6_SPARE_BITS_GET(x) (((x) & PHY_CTRL6_SPARE_BITS_MASK) >> PHY_CTRL6_SPARE_BITS_LSB)
#define PHY_CTRL6_SPARE_BITS_SET(x) (((x) << PHY_CTRL6_SPARE_BITS_LSB) & PHY_CTRL6_SPARE_BITS_MASK)
#define PHY_CTRL6_SPARE_BITS_RESET 0x0 // 0
#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_MSB 8
#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB 8
#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK 0x00000100
#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_GET(x) (((x) & PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK) >> PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB)
#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_SET(x) (((x) << PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB) & PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK)
#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_RESET 0x0 // 0
#define PHY_CTRL6_XCVR_SEL_MSB 7
#define PHY_CTRL6_XCVR_SEL_LSB 6
#define PHY_CTRL6_XCVR_SEL_MASK 0x000000c0
#define PHY_CTRL6_XCVR_SEL_GET(x) (((x) & PHY_CTRL6_XCVR_SEL_MASK) >> PHY_CTRL6_XCVR_SEL_LSB)
#define PHY_CTRL6_XCVR_SEL_SET(x) (((x) << PHY_CTRL6_XCVR_SEL_LSB) & PHY_CTRL6_XCVR_SEL_MASK)
#define PHY_CTRL6_XCVR_SEL_RESET 0x0 // 0
#define PHY_CTRL6_XCVRSEL_OVERRIDE_MSB 5
#define PHY_CTRL6_XCVRSEL_OVERRIDE_LSB 5
#define PHY_CTRL6_XCVRSEL_OVERRIDE_MASK 0x00000020
#define PHY_CTRL6_XCVRSEL_OVERRIDE_GET(x) (((x) & PHY_CTRL6_XCVRSEL_OVERRIDE_MASK) >> PHY_CTRL6_XCVRSEL_OVERRIDE_LSB)
#define PHY_CTRL6_XCVRSEL_OVERRIDE_SET(x) (((x) << PHY_CTRL6_XCVRSEL_OVERRIDE_LSB) & PHY_CTRL6_XCVRSEL_OVERRIDE_MASK)
#define PHY_CTRL6_XCVRSEL_OVERRIDE_RESET 0x0 // 0
#define PHY_CTRL6_IDDIG_MSB 4
#define PHY_CTRL6_IDDIG_LSB 4
#define PHY_CTRL6_IDDIG_MASK 0x00000010
#define PHY_CTRL6_IDDIG_GET(x) (((x) & PHY_CTRL6_IDDIG_MASK) >> PHY_CTRL6_IDDIG_LSB)
#define PHY_CTRL6_IDDIG_SET(x) (((x) << PHY_CTRL6_IDDIG_LSB) & PHY_CTRL6_IDDIG_MASK)
#define PHY_CTRL6_IDDIG_RESET 0x0 // 0
#define PHY_CTRL6_SESSEND_MSB 3
#define PHY_CTRL6_SESSEND_LSB 3
#define PHY_CTRL6_SESSEND_MASK 0x00000008
#define PHY_CTRL6_SESSEND_GET(x) (((x) & PHY_CTRL6_SESSEND_MASK) >> PHY_CTRL6_SESSEND_LSB)
#define PHY_CTRL6_SESSEND_SET(x) (((x) << PHY_CTRL6_SESSEND_LSB) & PHY_CTRL6_SESSEND_MASK)
#define PHY_CTRL6_SESSEND_RESET 0x0 // 0
#define PHY_CTRL6_VBUSVALID_MSB 2
#define PHY_CTRL6_VBUSVALID_LSB 2
#define PHY_CTRL6_VBUSVALID_MASK 0x00000004
#define PHY_CTRL6_VBUSVALID_GET(x) (((x) & PHY_CTRL6_VBUSVALID_MASK) >> PHY_CTRL6_VBUSVALID_LSB)
#define PHY_CTRL6_VBUSVALID_SET(x) (((x) << PHY_CTRL6_VBUSVALID_LSB) & PHY_CTRL6_VBUSVALID_MASK)
#define PHY_CTRL6_VBUSVALID_RESET 0x1 // 1
#define PHY_CTRL6_BVALID_MSB 1
#define PHY_CTRL6_BVALID_LSB 1
#define PHY_CTRL6_BVALID_MASK 0x00000002
#define PHY_CTRL6_BVALID_GET(x) (((x) & PHY_CTRL6_BVALID_MASK) >> PHY_CTRL6_BVALID_LSB)
#define PHY_CTRL6_BVALID_SET(x) (((x) << PHY_CTRL6_BVALID_LSB) & PHY_CTRL6_BVALID_MASK)
#define PHY_CTRL6_BVALID_RESET 0x1 // 1
#define PHY_CTRL6_AVALID_MSB 0
#define PHY_CTRL6_AVALID_LSB 0
#define PHY_CTRL6_AVALID_MASK 0x00000001
#define PHY_CTRL6_AVALID_GET(x) (((x) & PHY_CTRL6_AVALID_MASK) >> PHY_CTRL6_AVALID_LSB)
#define PHY_CTRL6_AVALID_SET(x) (((x) << PHY_CTRL6_AVALID_LSB) & PHY_CTRL6_AVALID_MASK)
#define PHY_CTRL6_AVALID_RESET 0x1 // 1
#define PHY_CTRL6_ADDRESS 0x18116c98
#define PHY_CTRL6_OFFSET 0x0018
// SW modifiable bits
#define PHY_CTRL6_SW_MASK 0xffffffff
// bits defined at reset
#define PHY_CTRL6_RSTMASK 0xffffffff
// reset value (ignore bits undefined at reset)
#define PHY_CTRL6_RESET 0x00000007
#define PHY_STATUS_TX_CAL_MSB 3
#define PHY_STATUS_TX_CAL_LSB 0
#define PHY_STATUS_TX_CAL_MASK 0x0000000f
#define PHY_STATUS_TX_CAL_GET(x) (((x) & PHY_STATUS_TX_CAL_MASK) >> PHY_STATUS_TX_CAL_LSB)
#define PHY_STATUS_TX_CAL_SET(x) (((x) << PHY_STATUS_TX_CAL_LSB) & PHY_STATUS_TX_CAL_MASK)
#define PHY_STATUS_TX_CAL_RESET 0x0 // 0
#define PHY_STATUS_ADDRESS 0x18116c9c
#define PHY_STATUS_OFFSET 0x001c
// SW modifiable bits
#define PHY_STATUS_SW_MASK 0x0000000f
// bits defined at reset
#define PHY_STATUS_RSTMASK 0xffffffff
// reset value (ignore bits undefined at reset)
#define PHY_STATUS_RESET 0x00000000
#define PHY_CTRL7_PPRBS_ERROR_RATE_MSB 31
#define PHY_CTRL7_PPRBS_ERROR_RATE_LSB 11
#define PHY_CTRL7_PPRBS_ERROR_RATE_MASK 0xfffff800
#define PHY_CTRL7_PPRBS_ERROR_RATE_GET(x) (((x) & PHY_CTRL7_PPRBS_ERROR_RATE_MASK) >> PHY_CTRL7_PPRBS_ERROR_RATE_LSB)
#define PHY_CTRL7_PPRBS_ERROR_RATE_SET(x) (((x) << PHY_CTRL7_PPRBS_ERROR_RATE_LSB) & PHY_CTRL7_PPRBS_ERROR_RATE_MASK)
#define PHY_CTRL7_PPRBS_ERROR_RATE_RESET 0xa000 // 40960
#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MSB 10
#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB 1
#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK 0x000007fe
#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_GET(x) (((x) & PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK) >> PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB)
#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_SET(x) (((x) << PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB) & PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK)
#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_RESET 0x0 // 0
#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_MSB 0
#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB 0
#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK 0x00000001
#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_GET(x) (((x) & PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK) >> PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB)
#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_SET(x) (((x) << PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB) & PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK)
#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_RESET 0x0 // 0
#define PHY_CTRL7_ADDRESS 0x18116ca0
#define PHY_CTRL7_OFFSET 0x0020
// SW modifiable bits
#define PHY_CTRL7_SW_MASK 0xffffffff
// bits defined at reset
#define PHY_CTRL7_RSTMASK 0xffffffff
// reset value (ignore bits undefined at reset)
#define PHY_CTRL7_RESET 0x05000000
#define PHY_CTRL8_USBPLL_PWD_MSB 7
#define PHY_CTRL8_USBPLL_PWD_LSB 7
#define PHY_CTRL8_USBPLL_PWD_MASK 0x00000080
#define PHY_CTRL8_USBPLL_PWD_GET(x) (((x) & PHY_CTRL8_USBPLL_PWD_MASK) >> PHY_CTRL8_USBPLL_PWD_LSB)
#define PHY_CTRL8_USBPLL_PWD_SET(x) (((x) << PHY_CTRL8_USBPLL_PWD_LSB) & PHY_CTRL8_USBPLL_PWD_MASK)
#define PHY_CTRL8_USBPLL_PWD_RESET 0x0 // 0
#define PHY_CTRL8_TX_FASTRISE_MSB 6
#define PHY_CTRL8_TX_FASTRISE_LSB 4
#define PHY_CTRL8_TX_FASTRISE_MASK 0x00000070
#define PHY_CTRL8_TX_FASTRISE_GET(x) (((x) & PHY_CTRL8_TX_FASTRISE_MASK) >> PHY_CTRL8_TX_FASTRISE_LSB)
#define PHY_CTRL8_TX_FASTRISE_SET(x) (((x) << PHY_CTRL8_TX_FASTRISE_LSB) & PHY_CTRL8_TX_FASTRISE_MASK)
#define PHY_CTRL8_TX_FASTRISE_RESET 0x5 // 5
#define PHY_CTRL8_TX_ENPRE_MSB 3
#define PHY_CTRL8_TX_ENPRE_LSB 2
#define PHY_CTRL8_TX_ENPRE_MASK 0x0000000c
#define PHY_CTRL8_TX_ENPRE_GET(x) (((x) & PHY_CTRL8_TX_ENPRE_MASK) >> PHY_CTRL8_TX_ENPRE_LSB)
#define PHY_CTRL8_TX_ENPRE_SET(x) (((x) << PHY_CTRL8_TX_ENPRE_LSB) & PHY_CTRL8_TX_ENPRE_MASK)
#define PHY_CTRL8_TX_ENPRE_RESET 0x0 // 0
#define PHY_CTRL8_RX_SQ_HYST_EN_MSB 1
#define PHY_CTRL8_RX_SQ_HYST_EN_LSB 1
#define PHY_CTRL8_RX_SQ_HYST_EN_MASK 0x00000002
#define PHY_CTRL8_RX_SQ_HYST_EN_GET(x) (((x) & PHY_CTRL8_RX_SQ_HYST_EN_MASK) >> PHY_CTRL8_RX_SQ_HYST_EN_LSB)
#define PHY_CTRL8_RX_SQ_HYST_EN_SET(x) (((x) << PHY_CTRL8_RX_SQ_HYST_EN_LSB) & PHY_CTRL8_RX_SQ_HYST_EN_MASK)
#define PHY_CTRL8_RX_SQ_HYST_EN_RESET 0x0 // 0
#define PHY_CTRL8_RX_SKIP2_MSB 0
#define PHY_CTRL8_RX_SKIP2_LSB 0
#define PHY_CTRL8_RX_SKIP2_MASK 0x00000001
#define PHY_CTRL8_RX_SKIP2_GET(x) (((x) & PHY_CTRL8_RX_SKIP2_MASK) >> PHY_CTRL8_RX_SKIP2_LSB)
#define PHY_CTRL8_RX_SKIP2_SET(x) (((x) << PHY_CTRL8_RX_SKIP2_LSB) & PHY_CTRL8_RX_SKIP2_MASK)
#define PHY_CTRL8_RX_SKIP2_RESET 0x0 // 0
#define PHY_CTRL8_ADDRESS 0x18116ca4
#define PHY_CTRL8_OFFSET 0x0024
// SW modifiable bits
#define PHY_CTRL8_SW_MASK 0x000000ff
// bits defined at reset
#define PHY_CTRL8_RSTMASK 0xffffffff
// reset value (ignore bits undefined at reset)
#define PHY_CTRL8_RESET 0x00000050
#define CPU_DDR_CLOCK_CONTROL_SPARE_MSB 31
#define CPU_DDR_CLOCK_CONTROL_SPARE_LSB 25
#define CPU_DDR_CLOCK_CONTROL_SPARE_MASK 0xfe000000
#define CPU_DDR_CLOCK_CONTROL_SPARE_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) >> CPU_DDR_CLOCK_CONTROL_SPARE_LSB)
#define CPU_DDR_CLOCK_CONTROL_SPARE_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_SPARE_LSB) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK)
#define CPU_DDR_CLOCK_CONTROL_SPARE_RESET 0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MSB 24
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB)
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK)
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_RESET 0x1 // 1
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MSB 23
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB 23
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK 0x00800000
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_RESET 0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MSB 22
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB 22
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK 0x00400000
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_RESET 0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MSB 21
#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB 21
#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK 0x00200000
#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB)
#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK)
#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_RESET 0x1 // 1
#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MSB 20
#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB 20
#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK 0x00100000
#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_RESET 0x1 // 1
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MSB 19
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB)
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK)
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_RESET 0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MSB 14
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB)
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_RESET 0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MSB 9
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_RESET 0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MSB 4
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB)
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_RESET 0x1 // 1
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MSB 3
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB)
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_RESET 0x1 // 1
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MSB 2
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_RESET 0x1 // 1
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MSB 1
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB 1
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK 0x00000002
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB)
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK)
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_RESET 0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MSB 0
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB 0
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK 0x00000001
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB)
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK)
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_RESET 0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_ADDRESS 0x18050008
#define PCIE_PLL_CONFIG_UPDATING_MSB 31
#define PCIE_PLL_CONFIG_UPDATING_LSB 31
#define PCIE_PLL_CONFIG_UPDATING_MASK 0x80000000
#define PCIE_PLL_CONFIG_UPDATING_GET(x) (((x) & PCIE_PLL_CONFIG_UPDATING_MASK) >> PCIE_PLL_CONFIG_UPDATING_LSB)
#define PCIE_PLL_CONFIG_UPDATING_SET(x) (((x) << PCIE_PLL_CONFIG_UPDATING_LSB) & PCIE_PLL_CONFIG_UPDATING_MASK)
#define PCIE_PLL_CONFIG_UPDATING_RESET 0x0 // 0
#define PCIE_PLL_CONFIG_PLLPWD_MSB 30
#define PCIE_PLL_CONFIG_PLLPWD_LSB 30
#define PCIE_PLL_CONFIG_PLLPWD_MASK 0x40000000
#define PCIE_PLL_CONFIG_PLLPWD_GET(x) (((x) & PCIE_PLL_CONFIG_PLLPWD_MASK) >> PCIE_PLL_CONFIG_PLLPWD_LSB)
#define PCIE_PLL_CONFIG_PLLPWD_SET(x) (((x) << PCIE_PLL_CONFIG_PLLPWD_LSB) & PCIE_PLL_CONFIG_PLLPWD_MASK)
#define PCIE_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
#define PCIE_PLL_CONFIG_BYPASS_MSB 16
#define PCIE_PLL_CONFIG_BYPASS_LSB 16
#define PCIE_PLL_CONFIG_BYPASS_MASK 0x00010000
#define PCIE_PLL_CONFIG_BYPASS_GET(x) (((x) & PCIE_PLL_CONFIG_BYPASS_MASK) >> PCIE_PLL_CONFIG_BYPASS_LSB)
#define PCIE_PLL_CONFIG_BYPASS_SET(x) (((x) << PCIE_PLL_CONFIG_BYPASS_LSB) & PCIE_PLL_CONFIG_BYPASS_MASK)
#define PCIE_PLL_CONFIG_BYPASS_RESET 0x1 // 1
#define PCIE_PLL_CONFIG_REFDIV_MSB 14
#define PCIE_PLL_CONFIG_REFDIV_LSB 10
#define PCIE_PLL_CONFIG_REFDIV_MASK 0x00007c00
#define PCIE_PLL_CONFIG_REFDIV_GET(x) (((x) & PCIE_PLL_CONFIG_REFDIV_MASK) >> PCIE_PLL_CONFIG_REFDIV_LSB)
#define PCIE_PLL_CONFIG_REFDIV_SET(x) (((x) << PCIE_PLL_CONFIG_REFDIV_LSB) & PCIE_PLL_CONFIG_REFDIV_MASK)
#define PCIE_PLL_CONFIG_REFDIV_RESET 0x1 // 1
#define PCIE_PLL_CONFIG_ADDRESS 0x18050010
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MSB 31
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB 31
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK 0x80000000
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) >> PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB)
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK)
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_RESET 0x1 // 1
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MSB 30
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB 30
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK 0x40000000
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) >> PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB)
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK)
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_RESET 0x1 // 1
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MSB 20
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB 15
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK 0x001f8000
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB)
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK)
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_RESET 0x13 // 19
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MSB 14
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB 1
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK 0x00007ffe
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB)
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK)
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_RESET 0x3fff // 16383
#define PCIE_PLL_DITHER_DIV_MAX_ADDRESS 0x18050014
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MSB 20
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB 15
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK 0x001f8000
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB)
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK)
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_RESET 0x13 // 19
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MSB 14
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB 1
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK 0x00007ffe
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB)
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK)
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_RESET 0x399d // 14749
#define PCIE_PLL_DITHER_DIV_MIN_ADDRESS 0x18050018
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MSB 31
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB 28
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK 0xf0000000
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) >> PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB)
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK)
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_RESET 0x0 // 0
#define PCIE_PLL_DITHER_STEP_STEP_INT_MSB 24
#define PCIE_PLL_DITHER_STEP_STEP_INT_LSB 15
#define PCIE_PLL_DITHER_STEP_STEP_INT_MASK 0x01ff8000
#define PCIE_PLL_DITHER_STEP_STEP_INT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) >> PCIE_PLL_DITHER_STEP_STEP_INT_LSB)
#define PCIE_PLL_DITHER_STEP_STEP_INT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_INT_LSB) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK)
#define PCIE_PLL_DITHER_STEP_STEP_INT_RESET 0x0 // 0
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MSB 14
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB 1
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK 0x00007ffe
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) >> PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB)
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK)
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_RESET 0xa // 10
#define PCIE_PLL_DITHER_STEP_ADDRESS 0x1805001c
// 32'h180f0008 (PCIE_PWR_MGMT)
#define PCIE_PWR_MGMT_PME_INT_MSB 8
#define PCIE_PWR_MGMT_PME_INT_LSB 8
#define PCIE_PWR_MGMT_PME_INT_MASK 0x00000100
#define PCIE_PWR_MGMT_PME_INT_GET(x) (((x) & PCIE_PWR_MGMT_PME_INT_MASK) >> PCIE_PWR_MGMT_PME_INT_LSB)
#define PCIE_PWR_MGMT_PME_INT_SET(x) (((x) << PCIE_PWR_MGMT_PME_INT_LSB) & PCIE_PWR_MGMT_PME_INT_MASK)
#define PCIE_PWR_MGMT_PME_INT_RESET 0x0 // 0
#define PCIE_PWR_MGMT_ASSERT_CLKREQN_MSB 7
#define PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB 7
#define PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK 0x00000080
#define PCIE_PWR_MGMT_ASSERT_CLKREQN_GET(x) (((x) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) >> PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB)
#define PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(x) (((x) << PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK)
#define PCIE_PWR_MGMT_ASSERT_CLKREQN_RESET 0x0 // 0
#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MSB 6
#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB 6
#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK 0x00000040
#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) >> PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB)
#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK)
#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_RESET 0x0 // 0
#define PCIE_PWR_MGMT_RADM_PM_PME_MSB 5
#define PCIE_PWR_MGMT_RADM_PM_PME_LSB 5
#define PCIE_PWR_MGMT_RADM_PM_PME_MASK 0x00000020
#define PCIE_PWR_MGMT_RADM_PM_PME_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) >> PCIE_PWR_MGMT_RADM_PM_PME_LSB)
#define PCIE_PWR_MGMT_RADM_PM_PME_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_PME_LSB) & PCIE_PWR_MGMT_RADM_PM_PME_MASK)
#define PCIE_PWR_MGMT_RADM_PM_PME_RESET 0x0 // 0
#define PCIE_PWR_MGMT_AUX_PM_EN_MSB 4
#define PCIE_PWR_MGMT_AUX_PM_EN_LSB 4
#define PCIE_PWR_MGMT_AUX_PM_EN_MASK 0x00000010
#define PCIE_PWR_MGMT_AUX_PM_EN_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) >> PCIE_PWR_MGMT_AUX_PM_EN_LSB)
#define PCIE_PWR_MGMT_AUX_PM_EN_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PM_EN_LSB) & PCIE_PWR_MGMT_AUX_PM_EN_MASK)
#define PCIE_PWR_MGMT_AUX_PM_EN_RESET 0x0 // 0
#define PCIE_PWR_MGMT_READY_ENTR_L23_MSB 3
#define PCIE_PWR_MGMT_READY_ENTR_L23_LSB 3
#define PCIE_PWR_MGMT_READY_ENTR_L23_MASK 0x00000008
#define PCIE_PWR_MGMT_READY_ENTR_L23_GET(x) (((x) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) >> PCIE_PWR_MGMT_READY_ENTR_L23_LSB)
#define PCIE_PWR_MGMT_READY_ENTR_L23_SET(x) (((x) << PCIE_PWR_MGMT_READY_ENTR_L23_LSB) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK)
#define PCIE_PWR_MGMT_READY_ENTR_L23_RESET 0x0 // 0
#define PCIE_PWR_MGMT_REQ_EXIT_L1_MSB 2
#define PCIE_PWR_MGMT_REQ_EXIT_L1_LSB 2
#define PCIE_PWR_MGMT_REQ_EXIT_L1_MASK 0x00000004
#define PCIE_PWR_MGMT_REQ_EXIT_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) >> PCIE_PWR_MGMT_REQ_EXIT_L1_LSB)
#define PCIE_PWR_MGMT_REQ_EXIT_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK)
#define PCIE_PWR_MGMT_REQ_EXIT_L1_RESET 0x0 // 0
#define PCIE_PWR_MGMT_REQ_ENTRY_L1_MSB 1
#define PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB 1
#define PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK 0x00000002
#define PCIE_PWR_MGMT_REQ_ENTRY_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) >> PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB)
#define PCIE_PWR_MGMT_REQ_ENTRY_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK)
#define PCIE_PWR_MGMT_REQ_ENTRY_L1_RESET 0x0 // 0
#define PCIE_PWR_MGMT_AUX_PWR_DET_MSB 0
#define PCIE_PWR_MGMT_AUX_PWR_DET_LSB 0
#define PCIE_PWR_MGMT_AUX_PWR_DET_MASK 0x00000001
#define PCIE_PWR_MGMT_AUX_PWR_DET_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) >> PCIE_PWR_MGMT_AUX_PWR_DET_LSB)
#define PCIE_PWR_MGMT_AUX_PWR_DET_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PWR_DET_LSB) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK)
#define PCIE_PWR_MGMT_AUX_PWR_DET_RESET 0x0 // 0
#define PCIE_PWR_MGMT_ADDRESS 0x180f0008
#define PCIE_PWR_MGMT_OFFSET 0x0008
// SW modifiable bits
#define PCIE_PWR_MGMT_SW_MASK 0x000001ff
// bits defined at reset
#define PCIE_PWR_MGMT_RSTMASK 0xffffffff
// reset value (ignore bits undefined at reset)
#define PCIE_PWR_MGMT_RESET 0x00000000
// 32'h180600c0 (RST_CLKGAT_EN)
#define RST_CLKGAT_EN_SPARE_MSB 31
#define RST_CLKGAT_EN_SPARE_LSB 12
#define RST_CLKGAT_EN_SPARE_MASK 0xfffff000
#define RST_CLKGAT_EN_SPARE_GET(x) (((x) & RST_CLKGAT_EN_SPARE_MASK) >> RST_CLKGAT_EN_SPARE_LSB)
#define RST_CLKGAT_EN_SPARE_SET(x) (((x) << RST_CLKGAT_EN_SPARE_LSB) & RST_CLKGAT_EN_SPARE_MASK)
#define RST_CLKGAT_EN_SPARE_RESET 0x0 // 0
#define RST_CLKGAT_EN_WMAC_MSB 9
#define RST_CLKGAT_EN_WMAC_LSB 9
#define RST_CLKGAT_EN_WMAC_MASK 0x00000200
#define RST_CLKGAT_EN_WMAC_GET(x) (((x) & RST_CLKGAT_EN_WMAC_MASK) >> RST_CLKGAT_EN_WMAC_LSB)
#define RST_CLKGAT_EN_WMAC_SET(x) (((x) << RST_CLKGAT_EN_WMAC_LSB) & RST_CLKGAT_EN_WMAC_MASK)
#define RST_CLKGAT_EN_WMAC_RESET 0x1 // 1
#define RST_CLKGAT_EN_USB1_MSB 7
#define RST_CLKGAT_EN_USB1_LSB 7
#define RST_CLKGAT_EN_USB1_MASK 0x00000080
#define RST_CLKGAT_EN_USB1_GET(x) (((x) & RST_CLKGAT_EN_USB1_MASK) >> RST_CLKGAT_EN_USB1_LSB)
#define RST_CLKGAT_EN_USB1_SET(x) (((x) << RST_CLKGAT_EN_USB1_LSB) & RST_CLKGAT_EN_USB1_MASK)
#define RST_CLKGAT_EN_USB1_RESET 0x1 // 1
#define RST_CLKGAT_EN_GE1_MSB 6
#define RST_CLKGAT_EN_GE1_LSB 6
#define RST_CLKGAT_EN_GE1_MASK 0x00000040
#define RST_CLKGAT_EN_GE1_GET(x) (((x) & RST_CLKGAT_EN_GE1_MASK) >> RST_CLKGAT_EN_GE1_LSB)
#define RST_CLKGAT_EN_GE1_SET(x) (((x) << RST_CLKGAT_EN_GE1_LSB) & RST_CLKGAT_EN_GE1_MASK)
#define RST_CLKGAT_EN_GE1_RESET 0x1 // 1
#define RST_CLKGAT_EN_GE0_MSB 5
#define RST_CLKGAT_EN_GE0_LSB 5
#define RST_CLKGAT_EN_GE0_MASK 0x00000020
#define RST_CLKGAT_EN_GE0_GET(x) (((x) & RST_CLKGAT_EN_GE0_MASK) >> RST_CLKGAT_EN_GE0_LSB)
#define RST_CLKGAT_EN_GE0_SET(x) (((x) << RST_CLKGAT_EN_GE0_LSB) & RST_CLKGAT_EN_GE0_MASK)
#define RST_CLKGAT_EN_GE0_RESET 0x1 // 1
#define RST_CLKGAT_EN_PCIE_RC_MSB 1
#define RST_CLKGAT_EN_PCIE_RC_LSB 1
#define RST_CLKGAT_EN_PCIE_RC_MASK 0x00000002
#define RST_CLKGAT_EN_PCIE_RC_GET(x) (((x) & RST_CLKGAT_EN_PCIE_RC_MASK) >> RST_CLKGAT_EN_PCIE_RC_LSB)
#define RST_CLKGAT_EN_PCIE_RC_SET(x) (((x) << RST_CLKGAT_EN_PCIE_RC_LSB) & RST_CLKGAT_EN_PCIE_RC_MASK)
#define RST_CLKGAT_EN_PCIE_RC_RESET 0x1 // 1
#define RST_CLKGAT_EN_ADDRESS 0x180600c0
#define RST_CLKGAT_EN_OFFSET 0x00c0
// SW modifiable bits
#define RST_CLKGAT_EN_SW_MASK 0xfffff2e2
// bits defined at reset
#define RST_CLKGAT_EN_RSTMASK 0xffffffff
// reset value (ignore bits undefined at reset)
#define RST_CLKGAT_EN_RESET 0x000002e2
#define PCIE_PHY_REG_1_ADDRESS 0x18116cc0
#define PCIE_PHY_REG_3_ADDRESS 0x18116cc8
#define LDO_POWER_CONTROL_PKG_SEL_MSB 5
#define LDO_POWER_CONTROL_PKG_SEL_LSB 5
#define LDO_POWER_CONTROL_PKG_SEL_MASK 0x00000020
#define LDO_POWER_CONTROL_PKG_SEL_GET(x) (((x) & LDO_POWER_CONTROL_PKG_SEL_MASK) >> LDO_POWER_CONTROL_PKG_SEL_LSB)
#define LDO_POWER_CONTROL_PKG_SEL_SET(x) (((x) << LDO_POWER_CONTROL_PKG_SEL_LSB) & LDO_POWER_CONTROL_PKG_SEL_MASK)
#define LDO_POWER_CONTROL_PKG_SEL_RESET 0x0 // 0
#define LDO_POWER_CONTROL_PWDLDO_CPU_MSB 4
#define LDO_POWER_CONTROL_PWDLDO_CPU_LSB 4
#define LDO_POWER_CONTROL_PWDLDO_CPU_MASK 0x00000010
#define LDO_POWER_CONTROL_PWDLDO_CPU_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) >> LDO_POWER_CONTROL_PWDLDO_CPU_LSB)
#define LDO_POWER_CONTROL_PWDLDO_CPU_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_CPU_LSB) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK)
#define LDO_POWER_CONTROL_PWDLDO_CPU_RESET 0x0 // 0
#define LDO_POWER_CONTROL_PWDLDO_DDR_MSB 3
#define LDO_POWER_CONTROL_PWDLDO_DDR_LSB 3
#define LDO_POWER_CONTROL_PWDLDO_DDR_MASK 0x00000008
#define LDO_POWER_CONTROL_PWDLDO_DDR_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) >> LDO_POWER_CONTROL_PWDLDO_DDR_LSB)
#define LDO_POWER_CONTROL_PWDLDO_DDR_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_DDR_LSB) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK)
#define LDO_POWER_CONTROL_PWDLDO_DDR_RESET 0x0 // 0
#define LDO_POWER_CONTROL_CPU_REFSEL_MSB 2
#define LDO_POWER_CONTROL_CPU_REFSEL_LSB 1
#define LDO_POWER_CONTROL_CPU_REFSEL_MASK 0x00000006
#define LDO_POWER_CONTROL_CPU_REFSEL_GET(x) (((x) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) >> LDO_POWER_CONTROL_CPU_REFSEL_LSB)
#define LDO_POWER_CONTROL_CPU_REFSEL_SET(x) (((x) << LDO_POWER_CONTROL_CPU_REFSEL_LSB) & LDO_POWER_CONTROL_CPU_REFSEL_MASK)
#define LDO_POWER_CONTROL_CPU_REFSEL_RESET 0x3 // 3
#define LDO_POWER_CONTROL_SELECT_DDR1_MSB 0
#define LDO_POWER_CONTROL_SELECT_DDR1_LSB 0
#define LDO_POWER_CONTROL_SELECT_DDR1_MASK 0x00000001
#define LDO_POWER_CONTROL_SELECT_DDR1_GET(x) (((x) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) >> LDO_POWER_CONTROL_SELECT_DDR1_LSB)
#define LDO_POWER_CONTROL_SELECT_DDR1_SET(x) (((x) << LDO_POWER_CONTROL_SELECT_DDR1_LSB) & LDO_POWER_CONTROL_SELECT_DDR1_MASK)
#define LDO_POWER_CONTROL_SELECT_DDR1_RESET 0x0 // 0
#define LDO_POWER_CONTROL_ADDRESS 0x18050020
#define SWITCH_CLOCK_SPARE_SPARE_MSB 31
#define SWITCH_CLOCK_SPARE_SPARE_LSB 12
#define SWITCH_CLOCK_SPARE_SPARE_MASK 0xfffff000
#define SWITCH_CLOCK_SPARE_SPARE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_MASK) >> SWITCH_CLOCK_SPARE_SPARE_LSB)
#define SWITCH_CLOCK_SPARE_SPARE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_LSB) & SWITCH_CLOCK_SPARE_SPARE_MASK)
#define SWITCH_CLOCK_SPARE_SPARE_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MSB 11
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB 8
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0x00000f00
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) >> SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB)
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK)
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_RESET 0x5 // 5
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MSB 7
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB 7
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK 0x00000080
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB)
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK)
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MSB 6
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB 6
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK 0x00000040
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MSB 5
#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB 5
#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK 0x00000020
#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_GET(x) (((x) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK) >> SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB)
#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_SET(x) (((x) << SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK)
#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_RESET 0x1 // 1
#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MSB 4
#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB 4
#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK 0x00000010
#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_GET(x) (((x) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK) >> SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB)
#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_SET(x) (((x) << SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK)
#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_RESET 0x1 // 1
#define SWITCH_CLOCK_SPARE_EEE_ENABLE_MSB 3
#define SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB 3
#define SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK 0x00000008
#define SWITCH_CLOCK_SPARE_EEE_ENABLE_GET(x) (((x) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK) >> SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB)
#define SWITCH_CLOCK_SPARE_EEE_ENABLE_SET(x) (((x) << SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK)
#define SWITCH_CLOCK_SPARE_EEE_ENABLE_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MSB 2
#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB 2
#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK 0x00000004
#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB)
#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK)
#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MSB 1
#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB 1
#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK 0x00000002
#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK) >> SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB)
#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK)
#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_RESET 0x0 // 0
#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MSB 0
#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB 0
#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK 0x00000001
#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB)
#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK)
#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_RESET 0x1 // 1
#define SWITCH_CLOCK_SPARE_ADDRESS 0x18050024
#define CURRENT_PCIE_PLL_DITHER_INT_MSB 20
#define CURRENT_PCIE_PLL_DITHER_INT_LSB 15
#define CURRENT_PCIE_PLL_DITHER_INT_MASK 0x001f8000
#define CURRENT_PCIE_PLL_DITHER_INT_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_INT_MASK) >> CURRENT_PCIE_PLL_DITHER_INT_LSB)
#define CURRENT_PCIE_PLL_DITHER_INT_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_INT_LSB) & CURRENT_PCIE_PLL_DITHER_INT_MASK)
#define CURRENT_PCIE_PLL_DITHER_INT_RESET 0x1 // 1
#define CURRENT_PCIE_PLL_DITHER_FRAC_MSB 13
#define CURRENT_PCIE_PLL_DITHER_FRAC_LSB 0
#define CURRENT_PCIE_PLL_DITHER_FRAC_MASK 0x00003fff
#define CURRENT_PCIE_PLL_DITHER_FRAC_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) >> CURRENT_PCIE_PLL_DITHER_FRAC_LSB)
#define CURRENT_PCIE_PLL_DITHER_FRAC_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_FRAC_LSB) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK)
#define CURRENT_PCIE_PLL_DITHER_FRAC_RESET 0x0 // 0
#define CURRENT_PCIE_PLL_DITHER_ADDRESS 0x18050028
#define ETH_XMII_TX_INVERT_MSB 31
#define ETH_XMII_TX_INVERT_LSB 31
#define ETH_XMII_TX_INVERT_MASK 0x80000000
#define ETH_XMII_TX_INVERT_GET(x) (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB)
#define ETH_XMII_TX_INVERT_SET(x) (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK)
#define ETH_XMII_TX_INVERT_RESET 0x0 // 0
#define ETH_XMII_GIGE_QUAD_MSB 30
#define ETH_XMII_GIGE_QUAD_LSB 30
#define ETH_XMII_GIGE_QUAD_MASK 0x40000000
#define ETH_XMII_GIGE_QUAD_GET(x) (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB)
#define ETH_XMII_GIGE_QUAD_SET(x) (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK)
#define ETH_XMII_GIGE_QUAD_RESET 0x0 // 0
#define ETH_XMII_RX_DELAY_MSB 29
#define ETH_XMII_RX_DELAY_LSB 28
#define ETH_XMII_RX_DELAY_MASK 0x30000000
#define ETH_XMII_RX_DELAY_GET(x) (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB)
#define ETH_XMII_RX_DELAY_SET(x) (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK)
#define ETH_XMII_RX_DELAY_RESET 0x0 // 0
#define ETH_XMII_TX_DELAY_MSB 27
#define ETH_XMII_TX_DELAY_LSB 26
#define ETH_XMII_TX_DELAY_MASK 0x0c000000
#define ETH_XMII_TX_DELAY_GET(x) (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB)
#define ETH_XMII_TX_DELAY_SET(x) (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK)
#define ETH_XMII_TX_DELAY_RESET 0x0 // 0
#define ETH_XMII_GIGE_MSB 25
#define ETH_XMII_GIGE_LSB 25
#define ETH_XMII_GIGE_MASK 0x02000000
#define ETH_XMII_GIGE_GET(x) (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB)
#define ETH_XMII_GIGE_SET(x) (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK)
#define ETH_XMII_GIGE_RESET 0x0 // 0
#define ETH_XMII_OFFSET_PHASE_MSB 24
#define ETH_XMII_OFFSET_PHASE_LSB 24
#define ETH_XMII_OFFSET_PHASE_MASK 0x01000000
#define ETH_XMII_OFFSET_PHASE_GET(x) (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB)
#define ETH_XMII_OFFSET_PHASE_SET(x) (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK)
#define ETH_XMII_OFFSET_PHASE_RESET 0x0 // 0
#define ETH_XMII_OFFSET_COUNT_MSB 23
#define ETH_XMII_OFFSET_COUNT_LSB 16
#define ETH_XMII_OFFSET_COUNT_MASK 0x00ff0000
#define ETH_XMII_OFFSET_COUNT_GET(x) (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB)
#define ETH_XMII_OFFSET_COUNT_SET(x) (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK)
#define ETH_XMII_OFFSET_COUNT_RESET 0x0 // 0
#define ETH_XMII_PHASE1_COUNT_MSB 15
#define ETH_XMII_PHASE1_COUNT_LSB 8
#define ETH_XMII_PHASE1_COUNT_MASK 0x0000ff00
#define ETH_XMII_PHASE1_COUNT_GET(x) (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB)
#define ETH_XMII_PHASE1_COUNT_SET(x) (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK)
#define ETH_XMII_PHASE1_COUNT_RESET 0x1 // 1
#define ETH_XMII_PHASE0_COUNT_MSB 7
#define ETH_XMII_PHASE0_COUNT_LSB 0
#define ETH_XMII_PHASE0_COUNT_MASK 0x000000ff
#define ETH_XMII_PHASE0_COUNT_GET(x) (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB)
#define ETH_XMII_PHASE0_COUNT_SET(x) (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK)
#define ETH_XMII_PHASE0_COUNT_RESET 0x1 // 1
#define ETH_XMII_ADDRESS 0x1805002c
#define BB_PLL_CONFIG_UPDATING_MSB 31
#define BB_PLL_CONFIG_UPDATING_LSB 31
#define BB_PLL_CONFIG_UPDATING_MASK 0x80000000
#define BB_PLL_CONFIG_UPDATING_GET(x) (((x) & BB_PLL_CONFIG_UPDATING_MASK) >> BB_PLL_CONFIG_UPDATING_LSB)
#define BB_PLL_CONFIG_UPDATING_SET(x) (((x) << BB_PLL_CONFIG_UPDATING_LSB) & BB_PLL_CONFIG_UPDATING_MASK)
#define BB_PLL_CONFIG_UPDATING_RESET 0x1 // 1
#define BB_PLL_CONFIG_PLLPWD_MSB 30
#define BB_PLL_CONFIG_PLLPWD_LSB 30
#define BB_PLL_CONFIG_PLLPWD_MASK 0x40000000
#define BB_PLL_CONFIG_PLLPWD_GET(x) (((x) & BB_PLL_CONFIG_PLLPWD_MASK) >> BB_PLL_CONFIG_PLLPWD_LSB)
#define BB_PLL_CONFIG_PLLPWD_SET(x) (((x) << BB_PLL_CONFIG_PLLPWD_LSB) & BB_PLL_CONFIG_PLLPWD_MASK)
#define BB_PLL_CONFIG_PLLPWD_RESET 0x1 // 1
#define BB_PLL_CONFIG_SPARE_MSB 29
#define BB_PLL_CONFIG_SPARE_LSB 29
#define BB_PLL_CONFIG_SPARE_MASK 0x20000000
#define BB_PLL_CONFIG_SPARE_GET(x) (((x) & BB_PLL_CONFIG_SPARE_MASK) >> BB_PLL_CONFIG_SPARE_LSB)
#define BB_PLL_CONFIG_SPARE_SET(x) (((x) << BB_PLL_CONFIG_SPARE_LSB) & BB_PLL_CONFIG_SPARE_MASK)
#define BB_PLL_CONFIG_SPARE_RESET 0x0 // 0
#define BB_PLL_CONFIG_REFDIV_MSB 28
#define BB_PLL_CONFIG_REFDIV_LSB 24
#define BB_PLL_CONFIG_REFDIV_MASK 0x1f000000
#define BB_PLL_CONFIG_REFDIV_GET(x) (((x) & BB_PLL_CONFIG_REFDIV_MASK) >> BB_PLL_CONFIG_REFDIV_LSB)
#define BB_PLL_CONFIG_REFDIV_SET(x) (((x) << BB_PLL_CONFIG_REFDIV_LSB) & BB_PLL_CONFIG_REFDIV_MASK)
#define BB_PLL_CONFIG_REFDIV_RESET 0x1 // 1
#define BB_PLL_CONFIG_NINT_MSB 21
#define BB_PLL_CONFIG_NINT_LSB 16
#define BB_PLL_CONFIG_NINT_MASK 0x003f0000
#define BB_PLL_CONFIG_NINT_GET(x) (((x) & BB_PLL_CONFIG_NINT_MASK) >> BB_PLL_CONFIG_NINT_LSB)
#define BB_PLL_CONFIG_NINT_SET(x) (((x) << BB_PLL_CONFIG_NINT_LSB) & BB_PLL_CONFIG_NINT_MASK)
#define BB_PLL_CONFIG_NINT_RESET 0x2 // 2
#define BB_PLL_CONFIG_NFRAC_MSB 13
#define BB_PLL_CONFIG_NFRAC_LSB 0
#define BB_PLL_CONFIG_NFRAC_MASK 0x00003fff
#define BB_PLL_CONFIG_NFRAC_GET(x) (((x) & BB_PLL_CONFIG_NFRAC_MASK) >> BB_PLL_CONFIG_NFRAC_LSB)
#define BB_PLL_CONFIG_NFRAC_SET(x) (((x) << BB_PLL_CONFIG_NFRAC_LSB) & BB_PLL_CONFIG_NFRAC_MASK)
#define BB_PLL_CONFIG_NFRAC_RESET 0xccc // 3276
#define BB_PLL_CONFIG_ADDRESS 0x18050040
#define DDR_PLL_DITHER_DITHER_EN_MSB 31
#define DDR_PLL_DITHER_DITHER_EN_LSB 31
#define DDR_PLL_DITHER_DITHER_EN_MASK 0x80000000
#define DDR_PLL_DITHER_DITHER_EN_GET(x) (((x) & DDR_PLL_DITHER_DITHER_EN_MASK) >> DDR_PLL_DITHER_DITHER_EN_LSB)
#define DDR_PLL_DITHER_DITHER_EN_SET(x) (((x) << DDR_PLL_DITHER_DITHER_EN_LSB) & DDR_PLL_DITHER_DITHER_EN_MASK)
#define DDR_PLL_DITHER_DITHER_EN_RESET 0x0 // 0
#define DDR_PLL_DITHER_UPDATE_COUNT_MSB 30
#define DDR_PLL_DITHER_UPDATE_COUNT_LSB 27
#define DDR_PLL_DITHER_UPDATE_COUNT_MASK 0x78000000
#define DDR_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) >> DDR_PLL_DITHER_UPDATE_COUNT_LSB)
#define DDR_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) & DDR_PLL_DITHER_UPDATE_COUNT_MASK)
#define DDR_PLL_DITHER_UPDATE_COUNT_RESET 0xf // 15
#define DDR_PLL_DITHER_NFRAC_STEP_MSB 26
#define DDR_PLL_DITHER_NFRAC_STEP_LSB 20
#define DDR_PLL_DITHER_NFRAC_STEP_MASK 0x07f00000
#define DDR_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_STEP_MASK) >> DDR_PLL_DITHER_NFRAC_STEP_LSB)