| /* DDR system configuration */ |
| M_DDR_REG 0xe0000000 0x00000004 |
| M_DDR_REG 0xe0000004 0x00000004 |
| |
| /* make sure we are in soft reset */ |
| M_DDR_REG 0xf6000000 0x00000200 |
| |
| /* DDR speed */ |
| M_DDR_REG 0xe0000008 0x01c00180 |
| #if (RUBY_DDR_SPEED == 160) |
| M_DDR_REG 0xe000000c 0x01000080 |
| M_DDR_REG 0xf6000004 0x00081027 |
| #elif (RUBY_DDR_SPEED == 200) |
| M_DDR_REG 0xe000000c 0x00c00080 |
| M_DDR_REG 0xf6000004 0x00081030 |
| #elif (RUBY_DDR_SPEED == 250) |
| M_DDR_REG 0xe000000c 0x00800080 |
| M_DDR_REG 0xf6000004 0x0008103c |
| #elif (RUBY_DDR_SPEED == 320) |
| M_DDR_REG 0xe000000c 0x00400080 |
| M_DDR_REG 0xf6000004 0x0008104e |
| #elif (RUBY_DDR_SPEED == 400) |
| M_DDR_REG 0xe000000c 0x00000080 |
| M_DDR_REG 0xf6000004 0x00081061 |
| #else |
| #error RUBY_DDR_SPEED not supported |
| #endif |
| |
| /* timing setup */ |
| M_DDR_REG 0xf6000048 0x00000000 |
| M_DDR_REG 0xf600002c 0x00000000 |
| M_DDR_REG 0xf6000030 0x00020b42 |
| M_DDR_REG 0xf6000058 0x0001ffff |
| M_DDR_REG 0xf60000a4 0x10300800 |
| |
| /* memory organization */ |
| #if RUBY_DDR_MICRON |
| M_DDR_REG 0xf6000078 0x00004444 |
| M_DDR_REG 0xf600007c 0x3c3c3c3c |
| M_DDR_REG 0xf600003c 0x00000777 |
| M_DDR_REG 0xf6000040 0xfff00000 |
| M_DDR_REG 0xf6000044 0x0fff3333 |
| #elif RUBY_DDR_ETRON |
| M_DDR_REG 0xf6000078 0x00004343 |
| M_DDR_REG 0xf600007c 0x20202020 |
| M_DDR_REG 0xf600003c 0x00000f77 |
| M_DDR_REG 0xf6000040 0xfff00000 |
| M_DDR_REG 0xf6000044 0x0fff2222 |
| #else |
| #error no memory organization defined |
| #endif |
| |
| #if RUBY_DDR_16BIT |
| M_DDR_REG 0xf6000000 0x00000205 |
| #else |
| M_DDR_REG 0xf6000000 0x00000201 |
| #endif |
