| commit | 48ab1509254a4c175e4f65c478a978928ffe09ec | [log] [tgz] |
|---|---|---|
| author | Mike Frysinger <vapier@gentoo.org> | Sat Apr 04 08:10:22 2009 -0400 |
| committer | Mike Frysinger <vapier@gentoo.org> | Mon Apr 06 17:37:48 2009 -0400 |
| tree | 16a43aec668305a3dce6e08be4fc5f1387574cfe | |
| parent | ce1fe4ba6bb9df7c57351436fa17d1af8bbe7916 [diff] |
Blackfin: add workaround for anomaly 05000242 DESCRIPTION: If the DF bit is set prior to a hardware reset, the PLL will continue to divide CLKIN by 2 after the hardware reset, but the DF bit itself will be cleared in the PLL_CTL register. WORKAROUND: Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by 2 after reset. Signed-off-by: Mike Frysinger <vapier@gentoo.org>