tree 7ac021abc9b1e6f08dc64de6128868a28cabd175
parent f97db54d7e773a32100247ee002686b6a014a87d
author Dave Liu <daveliu@freescale.com> 1238135563 +0800
committer Wolfgang Denk <wd@denx.de> 1244581085 +0200

85xx: Fix the clock adjust of mpc8569mds board

Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.

Signed-off-by: Dave Liu <daveliu@freescale.com>