diff --git a/Makefile.gfiber b/Makefile.gfiber
new file mode 100644
index 0000000..7442d4a
--- /dev/null
+++ b/Makefile.gfiber
@@ -0,0 +1,80 @@
+#
+# Google makefile to build uboot for quantenna qsr1000 products
+#
+
+export ARCH=arm
+export TOP=$(PWD)
+export CROSS_TOOLDIR=$(TOP)/../../toolchains/quantenna/usr/bin/
+export CROSS_PREFIX=arc-buildroot-linux-uclibc-
+export CROSS_COMPILE=$(CROSS_TOOLDIR)/$(CROSS_PREFIX)
+
+version = $(shell ./version)
+
+LOADERBIN_GFRG240 = ../../loader-bin/quantenna/gfrg240
+
+GFRG240 = gfrg240-dev gfrg240-prod gfrg240-openbox
+
+all:		clean $(GFRG240)
+
+# don't run parallel, the several builds would mix .o files
+.NOTPARALLEL:
+
+clean:
+	make clean
+	rm -rf output.*
+
+clobber: clean
+	-make distclean
+	rm -rf output
+
+gfiber_private.pem:
+	@echo "$@ is required to sign binaries. Get a copy and put it next to Makefile.gfiber"
+	exit 1
+
+#
+# GENERATE_DIGEST(DIR, NAME)
+#
+define GENERATE_DIGEST
+	@echo "Generating digest for $(1)/$(2)"
+	openssl dgst -sign gfiber_private.pem -sha512 -binary -keyform \
+		PEM $(1)/$(2).bin > $(1)/$(2).sig
+endef
+
+install: gfiber_private.pem
+	mkdir -p $(LOADERBIN_GFRG240)
+	cp output/gfrg240-dev/*dev.bin $(LOADERBIN_GFRG240)/u-boot-dev.bin
+	cp output/gfrg240-prod/*prod.bin $(LOADERBIN_GFRG240)/u-boot-prod.bin
+	cp output/gfrg240-openbox/*openbox.bin $(LOADERBIN_GFRG240)/u-boot-openbox.bin
+	$(call GENERATE_DIGEST,$(LOADERBIN_GFRG240),u-boot-dev)
+	$(call GENERATE_DIGEST,$(LOADERBIN_GFRG240),u-boot-prod)
+	$(call GENERATE_DIGEST,$(LOADERBIN_GFRG240),u-boot-openbox)
+
+gfrg240-dev:
+	make -f Makefile clean
+	make -f Makefile ruby_config
+	make -f Makefile all
+	make -f Makefile ruby_mini_config
+	make -f piggy.mk TARGET=u-boot
+	mkdir -p output/$@
+	cp u-boot-piggy.bin output/$@/u-boot-dev.bin
+
+gfrg240-prod:
+	make -f Makefile clean
+	make -f Makefile ruby_config
+	echo "#define CONFIG_DISABLE_INPUT" >> include/config.h
+	echo "#define CONFIG_BOOT_DELAY 0" >> include/config.h
+	make -f Makefile all
+	make -f Makefile ruby_mini_config
+	make -f piggy.mk TARGET=u-boot
+	mkdir -p output/$@
+	cp u-boot-piggy.bin output/$@/u-boot-prod.bin
+
+gfrg240-openbox:
+	make -f Makefile clean
+	make -f Makefile ruby_config
+	echo "#undef CONFIG_DISABLE_INPUT" >> include/config.h
+	make -f Makefile all
+	make -f Makefile ruby_mini_config
+	make -f piggy.mk TARGET=u-boot
+	mkdir -p output/$@
+	cp u-boot-piggy.bin output/$@/u-boot-openbox.bin
diff --git a/board/ruby/Makefile b/board/ruby/Makefile
index 67d055c..f5a4413 100644
--- a/board/ruby/Makefile
+++ b/board/ruby/Makefile
@@ -59,7 +59,7 @@
 	rm -f $(LIB) core *.bak .depend
 
 $(obj)u-boot.lds: u-boot.lds.S force
-	$(CPP) -I../../../ -I../../ $(CPPFLAGS) -D__ASSEMBLY__ -P $< > $@
+	$(CPP) -I../../quantenna/ -I../../ $(CPPFLAGS) -D__ASSEMBLY__ -P $< > $@
 
 .PHONY: force
 
diff --git a/board/ruby/ar8236.c b/board/ruby/ar8236.c
index 1c18a93..43bd33d 100644
--- a/board/ruby/ar8236.c
+++ b/board/ruby/ar8236.c
@@ -157,12 +157,12 @@
 //      Functions
 ////////////////////////////////////////////////////////////////////
 
-inline u32 ar8236_emac_rdreg(int reg)
+u32 ar8236_emac_rdreg(int reg)
 {
 	return *(volatile u32 *)(g8236Dev.base + reg);
 }
 
-inline void ar8236_emac_wrreg(int reg, u32 val)
+void ar8236_emac_wrreg(int reg, u32 val)
 {
 	*(volatile u32 *)(g8236Dev.base + reg) = val;
 }
diff --git a/board/ruby/ar8237.c b/board/ruby/ar8237.c
index 08e39aa..e5e9f61 100755
--- a/board/ruby/ar8237.c
+++ b/board/ruby/ar8237.c
@@ -120,14 +120,30 @@
 #define AR8237_MASK_CTL_RESET       (0x80000000)
 #define AR8237_MASK_CLEAR_DEF       (0)
 #define AR8237_MODE_CTRL            (0x04)
-#define AR8237_MODE_RGMII_PHY     (0x07600000)
+
+#define S17_MAC0_RGMII_RXCLK_SHIFT	20
+#define S17_MAC0_RGMII_TXCLK_SHIFT	22
+#define S17_MAC0_RGMII_TXCLK_DELAY_EN	(1 << 25)
+#define S17_MAC0_RGMII_EN		(1 << 26)
+
+#define AR8237_MODE_RGMII_PHY     (S17_MAC0_RGMII_EN)
+
+//#define AR8237_MODE_RGMII_PHY     (0x07600000)
 //#define AR8237_MODE_RGMII_PHY       (0x07402000)
 #define AR8237_PWS_CTRL             (0x10)
 #define AR8237_PWS_CTRL_DEF         (0x40000000)
 #define AR8237_FWCTL_CTRL           (0x0624)
 #define AR8237_FWCTL_CTRL_DEF       (0x007f7f7f)
+
+#define S17_P0STATUS_REG                0x007c
+#define S17_P5STATUS_REG                0x0090
+#define S17_P6STATUS_REG                0x0094
+
 #define AR8237_PORT6_CTRL           (0xc)
-#define AR8237_PORT6_CTRL_DEF       (0x01000000)
+#define S17_PHY4_RGMII_EN		(1 << 17)
+#define S17_MAC6_RGMII_EN		(1 << 26)
+#define AR8237_PORT6_CTRL_DEF       (S17_PHY4_RGMII_EN)	
+
 #define AR8237_PORT0_CTRL           (0x7c)
 #define AR8237_PORT0_CTRL_DEF       (0x7e)
 
@@ -143,6 +159,27 @@
 #define AR8237_MIN_PHY_NUM          (0)
 #define AR8237_MAX_PHY_NUM          (4)
 
+
+#define S17_P5PAD_MODE_REG              0x0008
+#define S17_MAC_RGMII_RXCLK_DELAY_EN	(1 << 24)
+
+#define S17_SPEED_10M			(0 << 0)
+#define S17_SPEED_100M			(1 << 0)
+#define S17_SPEED_1000M			(2 << 0)
+#define S17_TXMAC_EN			(1 << 2)
+#define S17_RXMAC_EN			(1 << 3)
+#define S17_TX_FLOW_EN			(1 << 4)
+#define S17_RX_FLOW_EN			(1 << 5)
+#define S17_DUPLEX_FULL			(1 << 6)
+#define S17_DUPLEX_HALF			(0 << 6)
+#define S17_TX_HALF_FLOW_EN		(1 << 7)
+#define S17_LINK_EN			(1 << 9)
+#define S17_FLOW_LINK_EN		(1 << 12)
+#define S17_PORT_STATUS_DEFAULT		(S17_SPEED_1000M | S17_TXMAC_EN | \
+                                        S17_RXMAC_EN | \
+                                        S17_DUPLEX_FULL )
+                                        
+
 ////////////////////////////////////////////////////////////////////
 //      Types
 ////////////////////////////////////////////////////////////////////
@@ -157,12 +194,12 @@
 //      Functions
 ////////////////////////////////////////////////////////////////////
 
-inline u32 ar8237_emac_rdreg(int reg)
+u32 ar8237_emac_rdreg(int reg)
 {
 	return *(volatile u32 *)(g8237Dev.base + reg);
 }
 
-inline void ar8237_emac_wrreg(int reg, u32 val)
+void ar8237_emac_wrreg(int reg, u32 val)
 {
 	*(volatile u32 *)(g8237Dev.base + reg) = val;
 }
@@ -190,6 +227,42 @@
 	return 0;
 }
 
+int ar8237_normal_mdio_write(u16 phyAddr, u8 regAddr, u16 data)
+{
+	// check for clear MDIO status
+	if (ar8237_mdio_poll() != 0) {
+		return -1;
+	}
+
+	ar8237_emac_wrreg(EMAC_MAC_MDIO_DATA, data & 0xffff);
+	ar8237_emac_wrreg(EMAC_MAC_MDIO_CTRL,
+			  ((mdc_clk_divisor & MacMdioCtrlClkMask) << MacMdioCtrlClkShift) |
+			  (regAddr << 5) | (phyAddr & 0x1f) |
+			  AR8237_MDIO_START);
+	if (ar8237_mdio_poll() != 0) {
+		return -1;
+	}
+	// return without waiting for final completion
+	return 0;
+}
+int ar8237_normal_mdio_read(u16 phyAddr, u8 regAddr, u16 *data)
+{
+	if (ar8237_mdio_poll() != 0) {
+		return -1;
+	}
+
+	ar8237_emac_wrreg(EMAC_MAC_MDIO_CTRL, ( (regAddr & 0x1f) << 5) | AR8237_MDIO_START |
+			  ((mdc_clk_divisor & MacMdioCtrlClkMask) << MacMdioCtrlClkShift) |
+			  AR8237_MDIO_READ | (phyAddr & 0x1f));
+	if (ar8237_mdio_poll() != 0) {
+		return -1;
+	}
+
+	*data = ar8237_emac_rdreg(EMAC_MAC_MDIO_DATA);
+	return 0;
+}
+int __ar8237_mdio_read(u32 phyAddr, u32 regAddr, u32 * data);
+
 /*********************************************************************
  Name:      ar8237_mdio_write
  Purpose:   mdio write routine for AR8237 device
@@ -204,6 +277,9 @@
 	u32 rg = (regAddr & 0x3c) >> 1;
 	u32 ph = (regAddr & 0x1c0) >> 6;
 
+	u32 prev;
+	__ar8237_mdio_read(phyAddr, regAddr, &prev);
+
 	// check for clear MDIO status
 	if (ar8237_mdio_poll() != 0) {
 		return -1;
@@ -237,6 +313,8 @@
 		return -1;
 	}
 
+	// printf("%s reg 0x%04x data 0x%08x previously %08x\n", __func__, regAddr, data, prev);
+
 	// return without waiting for final completion
 	return 0;
 }
@@ -248,7 +326,7 @@
             more than one cycle to complete the write.
             checks for completion first
 *********************************************************************/
-int ar8237_mdio_read(u32 phyAddr, u32 regAddr, u32 * data)
+int __ar8237_mdio_read(u32 phyAddr, u32 regAddr, u32 * data)
 {
 	u32 highAddr = regAddr >> 9;
 	// need to swizzle the bits into arasan's fields which are different          
@@ -288,6 +366,16 @@
 	*data = *data | (ar8237_emac_rdreg(EMAC_MAC_MDIO_DATA) << 16);
 	return 0;
 }
+int ar8237_mdio_read(u32 phyAddr, u32 regAddr, u32 * data) {
+	int rc;
+	rc = __ar8237_mdio_read(phyAddr, regAddr, data);
+	if (!rc) {
+		// printf("%s  reg 0x%04x data 0x%08x\n", __func__, regAddr, *data);
+	} else {
+		printf("%s  failed reg 0x%04x data 0x%08x\n", __func__, regAddr, *data);
+	}
+	return rc;
+}
 
 /*********************************************************************
  Name:      ar8237_init
@@ -299,6 +387,7 @@
 {
 	u32 addr;
 	u32 devID;
+	u16 val;
 	g8237Dev.base = baseAddr;
 
 	// need to scan?
@@ -315,29 +404,37 @@
 	while (addr <  AR8237_MAX_PHY_NUM) {
 		uint32_t reset = AR8237_MASK_CTL_RESET;
 		ar8237_mdio_read(addr, AR8237_MASK_CTL, &devID);
-		if ((devID & 0xff00) == 0x1200) {
-			printf("Detected AR8237 Switch %d - set for RGMII, 1000FD\n",addr);
+		if ((devID & 0xff00) == 0x1300) {
+			printf("Detected AR8337 Switch %d - set for RGMII, 1000FD devID 0x%x\n",addr, devID);
 
 			// do a softreset
-			ar8237_mdio_write(phy_addr, AR8237_MODE_CTRL,  AR8237_MODE_RGMII_PHY);
-
 			// do a clean reset and wait for completion 
 			ar8237_mdio_write(phy_addr, AR8237_MASK_CTL, AR8237_MASK_CTL_RESET);
 			while (reset & AR8237_MASK_CTL_RESET) {
 				ar8237_mdio_read(addr, AR8237_MASK_CTL, &reset);
 			}
 
+			ar8237_mdio_write(phy_addr, AR8237_MODE_CTRL, AR8237_MODE_RGMII_PHY);
+
 			ar8237_mdio_write(phy_addr, AR8237_MASK_CTL, AR8237_MASK_CLEAR_DEF);	
 
-
-			ar8237_mdio_write(phy_addr, AR8237_PWS_CTRL, AR8237_PWS_CTRL_DEF);
 			ar8237_mdio_write(phy_addr, AR8237_FWCTL_CTRL, AR8237_FWCTL_CTRL_DEF);
 			ar8237_mdio_write(phy_addr, AR8237_PORT6_CTRL, AR8237_PORT6_CTRL_DEF);
-			ar8237_mdio_write(phy_addr, AR8237_PORT0_CTRL, AR8237_PORT0_CTRL_DEF);
-			g8237Dev.phy = addr;
+	
+			/* Disable MAC5 and MAC6 (due to PHY4), QCA */
+			ar8237_mdio_write(phy_addr, S17_P5STATUS_REG, 0);
+			ar8237_mdio_write(phy_addr, S17_P6STATUS_REG, 0);
 
-			//set the register 0xe00000b4 for RGMII Dll control register
-			*(volatile u32 *)(0xe00000b4) = 0x86868f8f;
+			ar8237_mdio_write(phy_addr, S17_P0STATUS_REG, S17_PORT_STATUS_DEFAULT);
+
+			ar8237_normal_mdio_write(4, 29, 0x12);
+			ar8237_normal_mdio_read(4, 30, &val);
+			val |= (1<<3);
+			ar8237_normal_mdio_write(4, 30, val);
+			ar8237_normal_mdio_write(4, 29, 0);
+
+
+			g8237Dev.phy = addr;
 
 			return addr;
 		}
diff --git a/board/ruby/arasan-emac-ahb.c b/board/ruby/arasan-emac-ahb.c
index 479a682..940d087 100644
--- a/board/ruby/arasan-emac-ahb.c
+++ b/board/ruby/arasan-emac-ahb.c
@@ -394,7 +394,7 @@
 static int emac_reset(struct emac_private * priv)
 {
 	unsigned int i;
-	uintptr_t base, mdio_base;
+	uintptr_t base;
 	uint16_t macaddr16[3];
 	uint16_t rx_desc_size = 0;
 	uint16_t tx_ring_size = 0;
@@ -402,7 +402,6 @@
 	struct eth_device * br = priv->parent;
 
 	base = priv->io_base;
-	mdio_base = priv->mdio->base;
 	memcpy(macaddr16, br->enetaddr, sizeof(macaddr16));
 	emac_reset_dma(base);
 
@@ -886,6 +885,11 @@
 	const char *dbg_bus = getenv("debug_bus");
 	int i;
 
+	printf("Resetting QCA8337\n");
+	gpio_config(7, GPIO_MODE_OUTPUT);
+	gpio_output(7, 1);
+	udelay(10);
+
 	if (!((emac0_cfg & EMAC_IN_USE) || (emac1_cfg & EMAC_IN_USE))) {
 		printf("error: no emac enabled\n");
 		return -1;
@@ -944,7 +948,7 @@
 	if (strcmp(argv[1],"read") == 0) {
 		uint32_t a1,a2,val;
 		a1 = simple_strtoul (argv[2], NULL, 10);
-		a2 = simple_strtoul (argv[3], NULL, 16);
+		a2 = simple_strtoul (argv[3], NULL, 10);
 		mdio_postrd_raw(base, a1, a2);
 		val = mdio_rdval_raw(base, 1);
 		printf("phy:%d reg:%d=0x%x\n",a1,a2,val);
diff --git a/board/ruby/newlib_asm.h b/board/ruby/newlib_asm.h
index e1f5c23..3144159 100644
--- a/board/ruby/newlib_asm.h
+++ b/board/ruby/newlib_asm.h
@@ -8,7 +8,7 @@
 #define _ENTRY(name) \
 	.text ` .balign 4 ` .globl name ` name:
 #define FUNC(name)         .type name,@function
-#define ENDFUNC0(name) .Lfe_##X##name: .size name,.Lfe_##name-name
+#define ENDFUNC0(name) .Lfe_##X##name: .size name,.Lfe_##X##name-name
 #define ENDFUNC(name) ENDFUNC0(name)
 #define ENTRY(name) _ENTRY(name) ` FUNC(name)
 
diff --git a/board/ruby/pcie.c b/board/ruby/pcie.c
index c128d38..861ff97 100755
--- a/board/ruby/pcie.c
+++ b/board/ruby/pcie.c
@@ -45,7 +45,7 @@
  */
 static int32_t setup_atu_shmem(void)
 {
-	uint32_t val = 0x0;
+	uint32_t __attribute__((unused)) val = 0x0;
 
 	/* Select shared mem region */
 	writel(PCIE_SHMEM_REGION, RUBY_PCIE_ATU_VIEW);
@@ -75,7 +75,7 @@
  */
 static int32_t setup_atu_sysctl(void)
 {
-	uint32_t val = 0x0;
+	uint32_t __attribute__((unused)) val = 0x0;
 
 	/* Select shared mem region */
 	writel(PCIE_SYSCTL_REGION, RUBY_PCIE_ATU_VIEW);
@@ -106,7 +106,7 @@
  */
 static int32_t setup_atu_dma(void)
 {
-	uint32_t val = 0x0;
+	uint32_t __attribute__((unused)) val = 0x0;
 
 	/* Select dma register region */
 	writel(PCIE_DMAREG_REGION, RUBY_PCIE_ATU_VIEW);
@@ -138,7 +138,7 @@
 static int32_t setup_atu_host(volatile qdpc_pcie_bda_t *bda)
 {
 	uint32_t host_mem_start = PCIE_HOSTMEM_EP_START_LO - readl(&bda->bda_dma_offset);
-	uint32_t val = 0x0;
+	uint32_t __attribute__((unused)) val = 0x0;
 
 	/* Select shared mem region */
 	writel(PCIE_HOSTMEM_REGION, RUBY_PCIE_ATU_VIEW);
@@ -202,7 +202,7 @@
 	uint16_t flag = 0;
 	uint32_t msi_addr = 0x0;
 	uint32_t msi_addr_up = 0x0;
-	uint32_t val = 0x0;
+	uint32_t __attribute__((unused)) val = 0x0;
 	uint32_t msi64 = 0;
 
 	flag = readl(PCIE_MSI_CAP) >> 16;
diff --git a/board/ruby/pcie2.c b/board/ruby/pcie2.c
index 9d1aa42..0c0ffb5 100644
--- a/board/ruby/pcie2.c
+++ b/board/ruby/pcie2.c
@@ -223,7 +223,7 @@
  *****************************************************************************/
 void pcie_cfg_map(u32 base,u32 size, u32 ch)
 {
-	u32 tmp = 0;
+	u32 __attribute__((unused)) tmp = 0;
 
 	REG_WRITE(PCIE_ATU_VIEW, ch);
 	REG_WRITE(PCIE_ATU_LBAR, base);
@@ -302,7 +302,7 @@
 
 void pcie_bar_map(u32 bar, u32 target, u32 size, u32 atu_chan)
 {
-	u32 tmp;
+	u32 __attribute__((unused)) tmp;
 	REG_WRITE(PCIE_ATU_VIEW, atu_chan | PCIE_ATU_VIEW_INBOUND);
 	REG_WRITE(PCIE_ATU_LAR, size);
 	REG_WRITE(PCIE_ATU_LTAR, target);
@@ -330,7 +330,7 @@
  *****************************************************************************/
 void pcie_mem_map(u32 base,u32 target,u32 size,u32 ch,u32 dir)
 {
-	u32 tmp;
+	u32 __attribute__((unused)) tmp;
 
 	REG_WRITE(PCIE_ATU_VIEW,ch|dir);
 	REG_WRITE(PCIE_ATU_LBAR,base);
@@ -353,7 +353,7 @@
  *****************************************************************************/
 void pcie_msi_map(u32 base)
 {
-	u32 tmp;
+	u32 __attribute__((unused)) tmp;
 	REG_WRITE(PCIE_MSI_ADDR,base);
 	REG_WRITE(PCIE_MSI_ADDR_UPPER,0);
 	REG_WRITE(PCIE_MSI_ENABLE,BIT(0));
@@ -677,7 +677,7 @@
 void topaz_ep_mmap(u32 target)
 {
 	volatile qdpc_pcie_bda_t *bda = (qdpc_pcie_bda_t *)(RUBY_PCIE_BDA_ADDR);
-	u32 tmp;
+	u32 __attribute__((unused)) tmp;
 
 	if (atu_is_init)
 		return;
diff --git a/board/ruby/ruby.c b/board/ruby/ruby.c
index a4ecd69..c1e0c5c 100644
--- a/board/ruby/ruby.c
+++ b/board/ruby/ruby.c
@@ -198,6 +198,9 @@
 			spi_protect_mode_off();
 		}
 	}
+#ifdef CONFIG_CMD_HNVRAM
+        RUN("hnvram");
+#endif
 	return 0;
 }
 
diff --git a/board/ruby/start.S b/board/ruby/start.S
index 647f5ad..6974204 100644
--- a/board/ruby/start.S
+++ b/board/ruby/start.S
@@ -128,22 +128,22 @@
         /* reset bus monitors */
         mov     r0, 0
         mov     r1, 0xe0000200
-        st.di	r0,[r1, 0x00]
-        st.di	r0,[r1, 0x40]
-        st.di	r0,[r1, 0x80]
-        st.di	r0,[r1, 0xc0]
-        st.di	r0,[r1, 0x100]
-        st.di	r0,[r1, 0x140]
-        st.di	r0,[r1, 0x180]
-        st.di	r0,[r1, 0x1c0]
-        ld.di	r0,[r1, 0x00]
-        ld.di	r0,[r1, 0x40]
-        ld.di	r0,[r1, 0x80]
-        ld.di	r0,[r1, 0xc0]
-        ld.di	r0,[r1, 0x100]
-        ld.di	r0,[r1, 0x140]
-        ld.di	r0,[r1, 0x180]
-        ld.di	r0,[r1, 0x1c0]
+        st.di.as r0,[r1, 0x00]
+        st.di.as r0,[r1, 0x10]
+        st.di.as r0,[r1, 0x20]
+        st.di.as r0,[r1, 0x30]
+        st.di.as r0,[r1, 0x40]
+        st.di.as r0,[r1, 0x50]
+        st.di.as r0,[r1, 0x60]
+        st.di.as r0,[r1, 0x70]
+        ld.di.as r0,[r1, 0x00]
+        ld.di.as r0,[r1, 0x10]
+        ld.di.as r0,[r1, 0x20]
+        ld.di.as r0,[r1, 0x30]
+        ld.di.as r0,[r1, 0x40]
+        ld.di.as r0,[r1, 0x50]
+        ld.di.as r0,[r1, 0x60]
+        ld.di.as r0,[r1, 0x70]
 #endif
 
 	M_REMOVE_FROM_RESET
diff --git a/board/ruby_mini/ruby_mini_common.c b/board/ruby_mini/ruby_mini_common.c
index e1df98a..bf1e3bf 100644
--- a/board/ruby_mini/ruby_mini_common.c
+++ b/board/ruby_mini/ruby_mini_common.c
@@ -71,7 +71,7 @@
 void printf(const char *fmt, ...)
 {
 	va_list args;
-	uint i;
+	uint __attribute__((unused)) i;
 	char printbuffer[256];
 
 	va_start (args, fmt);
@@ -89,7 +89,7 @@
 
 void vprintf(const char *fmt, va_list args)
 {
-	uint i;
+	uint __attribute__((unused)) i;
 	char printbuffer[256];
 
 	/*
diff --git a/board/ruby_mini/ruby_piggy.c b/board/ruby_mini/ruby_piggy.c
index 9a17af9..bd93c63 100644
--- a/board/ruby_mini/ruby_piggy.c
+++ b/board/ruby_mini/ruby_piggy.c
@@ -57,7 +57,7 @@
 	extern unsigned int early_flash_config_end;
 	unsigned int *pin;
 	unsigned int *pout;
-	int rc;
+	int __attribute__((unused)) rc;
 
 	unsigned long decompression_addr = RUBY_SRAM_BEGIN + TEXT_BASE_OFFSET_CHILD;
 	unsigned long uncompressed_size;
diff --git a/common/Makefile b/common/Makefile
index 8a875ac..1d0cbd2 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -96,6 +96,7 @@
 ifdef CONFIG_FPGA
 COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o
 endif
+COBJS-$(CONFIG_CMD_HNVRAM) += cmd_hnvram.o
 COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
 COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o
 COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o
diff --git a/common/cmd_hnvram.c b/common/cmd_hnvram.c
new file mode 100644
index 0000000..52f0ae1
--- /dev/null
+++ b/common/cmd_hnvram.c
@@ -0,0 +1,266 @@
+/*
+ * cmd_hnvram.c -- makes hnvram contents available in u-boot.
+ *      Loads contents of hnvram from spi flash and saves it
+ *      to environment variables named HNV_<name>.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Author: Chris Gibson <cgibson@google.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <command.h>
+#include <common.h>
+#include <malloc.h>
+#include <spi_flash.h>
+
+/* local debug macro */
+#undef HNVRAM_DEBUG
+
+#ifdef HNVRAM_DEBUG
+#define DEBUG(fmt, args...)  printf(fmt, ##args)
+#else
+#define DEBUG(fmt, args...)
+#endif  /* HNVRAM_DEBUG */
+
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+
+
+// Flash erase block size
+#define HNVRAM_BLOCKSIZE 0x00010000
+
+// Location in DRAM where hnvram variables are stored during boot
+// DRAM is 128 MB [0x80000000 - 0x88000000]
+// Store hnvram at 120 - 122 MB
+#define HNVRAM_DRAM_OFFSET 0x87800000
+
+// Where in flash does hnvram partition start
+#define HNVRAM_MTD_OFFSET 0x00200000
+
+// Total hnvram is 2MB with 4 partitions
+#define MAX_HNVRAM_SIZE     0x00200000
+
+#define HNVRAM_RO_SIZE      0x00100000
+#define HNVRAM_RW_SIZE      0x00040000
+#define HNVRAM_RWB_SIZE     0x00020000
+#define HNVRAM_RAW_FS_SIZE  0x00020000
+
+// B1 and B2 corresponding to RW_OFFSET and RWB_OFFSET
+#define HNVRAM_B1_OFFSET  (HNVRAM_RO_SIZE)
+#define HNVRAM_B2_OFFSET  (HNVRAM_RO_SIZE + HNVRAM_RW_SIZE)
+
+#define CMD_RET_SUCCESS 0
+#define CMD_RET_FAILURE 1
+#define CMD_RET_USAGE -1
+
+// These keys are stored in binary format for historical reasons
+const char *hnvram_binary_keys[] = {
+        "LOADER_VERSION",
+        "HDCP_KEY",
+        "DTCP_KEY",
+};
+
+static void *xmalloc(size_t size)
+{
+        void *p = NULL;
+        if (!(p = malloc(size))) {
+                printf("error: memory not allocated\n");
+                return 0;
+        }
+        memset(p, 0, size);
+        return p;
+}
+
+int read_u8(const char **p)
+{
+        int v = *(const unsigned char *)(*p);
+        *p += 1;
+        return v;
+}
+
+int read_s32_be(const char **p)
+{
+        const unsigned char *vp = (const unsigned char *)*p;
+        *p += 4;
+        return (vp[0]<<24) + (vp[1]<<16) + (vp[2]<<8) + vp[3];
+}
+
+int read_u16_le(const char **p)
+{
+        const unsigned char *up = (const unsigned char *)(*p);
+        *p += 2;
+        return up[0] + (up[1] << 8);
+}
+
+int is_hnvram_binary(const char *name, int namelen)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(hnvram_binary_keys); i++) {
+                const char *k = hnvram_binary_keys[i];
+                if ((int)strlen(k) == namelen && strncmp(k, name, namelen) == 0) {
+                        return 1;
+                }
+        }
+        return 0;
+}
+
+char *encode_hex(const char *s, int len)
+{
+        char *optr, *out = xmalloc(len * 2 + 1);
+        for (optr = out; len > 0; len--) {
+                sprintf(optr, "%02x", read_u8(&s));
+                optr += 2;
+        }
+        return out;
+}
+
+char *encode_macaddr(const char *mac)
+{
+        int i;
+        char *out = xmalloc(6 * 2 + 5 + 2);
+        for (i = 0; i < 6; i++) {
+                sprintf(out + i * 3, "%02X:", read_u8(&mac));
+        }
+        out[6*2 + 5] = '\0';
+        return out;
+}
+
+static void _copy_setenv(const char *name, int namelen,
+                const char *val, int vallen)
+{
+        char *n, *v;
+        if (namelen + vallen < 128) {
+                n = xmalloc(4 + namelen + 1);
+                v = xmalloc(vallen + 1);
+                memcpy(n, "HNV_", 4);
+                memcpy(n + 4, name, namelen);
+                memcpy(v, val, vallen);
+                n[namelen+4] = 0;
+                v[vallen] = 0;
+                setenv(n, v);
+                free(n);
+                free(v);
+        } else {
+                DEBUG("ignoring oversized val: %.15s, vallen: %d\n", val, vallen);
+        }
+}
+
+static int _parse_hnvram(const char *buf, int len)
+{
+        // An hnvram structure. Format is a tag-length-value sequence of:
+        //    [1 byte]   type (1 for notdone, 0 for done)
+        //    [4 bytes]  record length
+        //    [1 byte]   key length
+        //    [x bytes]  key
+        //    [4 bytes]  value length
+        //    [y bytes]  value
+        int rectype, reclen, namelen, vallen;
+        int done = 0;
+        const char *name, *val, *p = buf;
+        while (p - buf <= len + 11) {
+                rectype = read_u8(&p);
+                if (rectype == 0x00) {
+                        printf("done processing hnvram block!\n");
+                        done = 1;
+                        break;
+                }
+                if (rectype != 0x01) {
+                        printf("error: hnvram invalid rectype %x\n", rectype);
+                        return -1;
+                }
+
+                reclen = read_s32_be(&p);
+                if (reclen <= 6 || (p - buf) + reclen >= len) {
+                        printf("error: hnvram invalid reclen %d\n", reclen);
+                        return -1;
+                }
+                namelen = read_u8(&p);
+                if (namelen < 1 || (p - buf) + namelen >= len) {
+                        printf("error: hnvram invalid namelen %d\n", namelen);
+                        return -1;
+                }
+                name = p;
+                p += namelen;
+                vallen = read_s32_be(&p);
+                if (vallen < 0 || (p - buf) + vallen >= len) {
+                        printf("error: hnvram invalid vallen %d\n", vallen);
+                        return -1;
+                }
+                val = p;
+                p += vallen;
+                if (vallen == 6 && namelen >= 8 &&
+                                strncmp("MAC_ADDR", name, 8) == 0) {
+                        char *macstr = encode_macaddr(val);
+                        _copy_setenv(name, namelen, macstr, strlen(macstr));
+                        free(macstr);
+                } else if (is_hnvram_binary(name, namelen)) {
+                        char *hexstr = encode_hex(val, vallen);
+                        _copy_setenv(name, namelen, hexstr, strlen(hexstr));
+                        free(hexstr);
+                } else {
+                        _copy_setenv(name, namelen, val, vallen);
+                }
+        }
+        if (!done) {
+                printf("error: failed to find final hnvram record?\n");
+                return -1;
+        }
+        return 0;
+}
+
+#if defined(CONFIG_CMD_HNVRAM)
+int do_hnvram(void) {
+        char command[60];
+        sprintf(command, "spi_flash read 0x%x 0x%x 0x%x", HNVRAM_MTD_OFFSET, HNVRAM_DRAM_OFFSET, MAX_HNVRAM_SIZE);
+        int ret = run_command(command, 0);
+
+        if (ret) {
+          printf("failed reading from spi-flash at addr: %d\n", HNVRAM_MTD_OFFSET);
+          return ret;
+        }
+
+        char *buf = HNVRAM_DRAM_OFFSET;
+
+        // Next step: Seek to different parts of the buffer that contain the
+        // first, second, and third sections of hnvram.
+        if (_parse_hnvram(buf, HNVRAM_BLOCKSIZE) != 0) {
+                printf("failed parsing hnvram at offset: 0x%p\n", buf);
+                return -1;
+        }
+        if (_parse_hnvram(buf+HNVRAM_B1_OFFSET, HNVRAM_BLOCKSIZE) != 0) {
+                printf("failed parsing hnvram at offset: 0x%p\n", buf+HNVRAM_B1_OFFSET);
+                return -1;
+        }
+        if (_parse_hnvram(buf+HNVRAM_B2_OFFSET, HNVRAM_BLOCKSIZE) != 0) {
+                printf("failed parsing hnvram at offset: 0x%p\n", buf+HNVRAM_B2_OFFSET);
+                return -1;
+        }
+
+        free(buf);
+        return CMD_RET_SUCCESS;
+}
+
+static int do_hnvram_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+                char * const argv[]) {
+        return do_hnvram();
+}
+
+U_BOOT_CMD(
+        hnvram, 1, 0, do_hnvram_cmd,
+        "load hnvram from flash",
+        "\n"
+        "load hnvram from flash into environment vars named HNV_<name>\n"
+        );
+#endif  /* CONFIG_CMD_HNVRAM */
diff --git a/common/console.c b/common/console.c
index 2add047..e60bcbd 100644
--- a/common/console.c
+++ b/common/console.c
@@ -295,6 +295,10 @@
 
 int getc(void)
 {
+#ifdef CONFIG_DISABLE_INPUT
+	return 0;
+#endif
+
 #ifdef CONFIG_DISABLE_CONSOLE
 	if (gd->flags & GD_FLG_DISABLE_CONSOLE)
 		return 0;
@@ -311,6 +315,10 @@
 
 int tstc(void)
 {
+#ifdef CONFIG_DISABLE_INPUT
+	return 0;
+#endif
+
 #ifdef CONFIG_DISABLE_CONSOLE
 	if (gd->flags & GD_FLG_DISABLE_CONSOLE)
 		return 0;
diff --git a/common/main.c b/common/main.c
index f2f3d6e..3d4b3b5 100755
--- a/common/main.c
+++ b/common/main.c
@@ -47,7 +47,7 @@
 /*
  * Board-specific Platform code can reimplement show_boot_progress () if needed
  */
-void inline __show_boot_progress (int val) {}
+void __show_boot_progress (int val) {}
 void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
 
 #if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY)
diff --git a/config.mk b/config.mk
index 68b4906..e163ba8 100644
--- a/config.mk
+++ b/config.mk
@@ -60,10 +60,10 @@
 	# PLATFORM_CPPFLAGS+= -D__ARC__ -mA7 -mno-sdata -O0 -g -mno-volatile-cache -fomit-frame-pointer
 	# Enable optimization. Disable cache bypassing for "volatile" references.
 	# It is bad design to enable cache bypassing for "volatile" references - readX()/writeX() has to be used.
-	PLATFORM_CPPFLAGS_PATH = -I$(OBJTREE)/../common -I$(OBJTREE)/../include/qtn
+	PLATFORM_CPPFLAGS_PATH = -I$(OBJTREE)/quantenna/common -I$(OBJTREE)/quantenna/include/qtn
 	PLATFORM_CPPFLAGS += -D__ARC__ -mA7 -mno-sdata -Os -g -mvolatile-cache -fomit-frame-pointer $(PLATFORM_CPPFLAGS_PATH)
 endif
-HOST_CFLAGS += -I$(OBJTREE)/../common
+HOST_CFLAGS += -I$(OBJTREE)/quantenna/common
 
 #########################################################################
 #
@@ -157,6 +157,7 @@
 endif
 
 CFLAGS += $(call cc-option,-fno-stack-protector)
+CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
 
 # avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9)
 # this option have to be placed behind -Wall -- that's why it is here
diff --git a/helper.mk b/helper.mk
index 751519e..70648d9 100644
--- a/helper.mk
+++ b/helper.mk
@@ -3,6 +3,6 @@
 
 define build-mini-ldmap
 	@mkdir -p ${@D}
-	$(CPP) -D__ASSEMBLY__ -I../common -Iinclude $1 $< | grep -vE '^\#' > $@
+	$(CPP) -D__ASSEMBLY__ -Iquantenna/common -Iinclude $1 $< | grep -vE '^\#' > $@
 endef
 
diff --git a/include/asm-arc/arch-arc/arasan_emac_ahb.h b/include/asm-arc/arch-arc/arasan_emac_ahb.h
index 8990890..e3315a7 100755
--- a/include/asm-arc/arch-arc/arasan_emac_ahb.h
+++ b/include/asm-arc/arch-arc/arasan_emac_ahb.h
@@ -36,7 +36,7 @@
 
 /* All the common defines for the Ethernet controller */
 #include <config.h>
-#include "../../../../common/ruby_arasan_emac_ahb.h"
+#include "../../../quantenna/common/ruby_arasan_emac_ahb.h"
 
 #ifndef __ASSEMBLY__
 
diff --git a/include/configs/ruby.h b/include/configs/ruby.h
index 882682c..ffda11b 100644
--- a/include/configs/ruby.h
+++ b/include/configs/ruby.h
@@ -33,6 +33,7 @@
 /* Commands */
 #define CONFIG_CMD_CONSOLE
 #define CONFIG_CMD_ECHO
+#define CONFIG_CMD_HNVRAM
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_MISC
 #define CONFIG_CMD_RUN
@@ -168,7 +169,7 @@
 	#define CONFIG_NET_MULTI		1
 	#define CONFIG_ARASAN_GBE		1
 	#define CONFIG_IPADDR			192.168.1.100
-	#define CONFIG_SERVERIP			192.168.1.150
+	#define CONFIG_SERVERIP			192.168.1.2
 	#define CONFIG_ETHADDR			30:46:9a:25:be:e4
 	#define CONFIG_BOOTFILE			"topaz-linux.lzma.img"
 	#ifndef PLATFORM_NOSPI
diff --git a/include/configs/ruby_mini.h b/include/configs/ruby_mini.h
index d14332d..2071c40 100644
--- a/include/configs/ruby_mini.h
+++ b/include/configs/ruby_mini.h
@@ -36,6 +36,7 @@
 
 #ifndef  TOPAZ_EP_MINI_UBOOT
 /* Commands */
+#define CONFIG_CMD_HNVRAM
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_INTR
diff --git a/piggy.mk b/piggy.mk
index 78a6458..3c368f6 100644
--- a/piggy.mk
+++ b/piggy.mk
@@ -1,6 +1,5 @@
 
 include helper.mk
-include ../Make.toolchain
 
 CFLAGS =
 CC = $(CROSS_COMPILE)gcc
@@ -53,7 +52,7 @@
 		-nostdinc \
 		-mno-sdata -mvolatile-cache -mno-millicode \
 		-pipe \
-		-Iinclude/ -Iboard/ruby/ -I../common/ -I../include/qtn/ \
+		-Iinclude/ -Iboard/ruby/ -Iquantenna/common/ -Iquantenna/include/qtn/ \
 		-isystem $(gccincdir) \
 		-DTEXT_BASE_OFFSET=$(TEXT_BASE_OFFSET_PARENT) \
 		-DTEXT_BASE_OFFSET_CHILD=$(TEXT_BASE_OFFSET_CHILD) \
@@ -88,7 +87,7 @@
 	lib_generic/vsprintf.o			\
 	lib_generic/string.o
 
-LDFLAGS = -L $(tools_path)../lib/gcc/arc-linux-uclibc/4.2.1/ -lgcc
+LDFLAGS = -lgcc
 endif
 
 ifeq ($(TOPAZ_EP_MINI_UBOOT),1)
@@ -104,7 +103,7 @@
 	lib_generic/lzma/LzmaTools.o	\
 	$(LZMA_LIB)
 
-LZMA = ../host/utilities/lzma
+LZMA = quantenna/host/utilities/lzma
 LDMAP = $(BUILD_DIR)/u-boot-piggy.lds
 
 %.lzma: %
diff --git a/qtn_tiny.mk b/qtn_tiny.mk
index a415801..c1a6ee4 100644
--- a/qtn_tiny.mk
+++ b/qtn_tiny.mk
@@ -5,7 +5,6 @@
 #
 
 include helper.mk
-include ../Make.toolchain
 
 CFLAGS =
 CC = $(CROSS_COMPILE)gcc
@@ -34,7 +33,7 @@
 		-nostdinc \
 		-mno-sdata -mvolatile-cache -mno-millicode \
 		-pipe \
-		-Iboard/ruby/ -Iinclude/ -I../common/ -I../include/qtn/ \
+		-Iboard/ruby/ -Iinclude/ -Iquantenna/common/ -Iquantenna/include/qtn/ \
 		-isystem $(gccincdir) \
 		-DTEXT_BASE_OFFSET=$(UBOOT_TINY_TEXT_BASE_OFFSET) \
 
@@ -70,7 +69,7 @@
 	board/ruby_mini/ruby_mini_common.o	\
 	board/ruby_mini/ruby_tiny.o
 
-LDFLAGS = -L $(tools_path)../lib/gcc/arc-linux-uclibc/4.2.1/ -lgcc
+LDFLAGS = -lgcc
 
 LDMAP = $(BUILD_DIR)/u-boot-$(TARGET).lds
 
diff --git a/quantenna/Make.toolchain b/quantenna/Make.toolchain
deleted file mode 100644
index f23b873..0000000
--- a/quantenna/Make.toolchain
+++ /dev/null
@@ -1,6 +0,0 @@
-tools_path := /usr/local/ARC/gcc/bin/
-target_prefix := arc-linux-uclibc-
-compile_prefix := ${tools_path}${target_prefix}
-CROSS_COMPILE := ${compile_prefix}
-ARCH := arc
-
diff --git a/quantenna/common/ruby_arasan_emac_ahb.h b/quantenna/common/ruby_arasan_emac_ahb.h
index 2d36410..e31bbf4 100755
--- a/quantenna/common/ruby_arasan_emac_ahb.h
+++ b/quantenna/common/ruby_arasan_emac_ahb.h
@@ -27,7 +27,7 @@
 #include <include/qtn/amber.h>
 #endif
 
-extern __inline__ void __mydelay(unsigned long loops)
+static __inline__ void __mydelay(unsigned long loops)
 {
 	__asm__ __volatile__ ( "1: \n\t"
 			     "sub.f %0, %1, 1\n\t"