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#ifndef __NS16550_H__
#define __NS16550_H__

#ifdef __cplusplus
extern "C" {
#endif

#include "mvCommon.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"

#ifdef MV78XX0
#include "idma/mvIdma.h"
#include "ctrlEnv/sys/mvSysIdma.h"
#endif
/* This structure describes the registers offsets for one UART port(channel) */
	typedef struct mvUartPort {
		MV_U8 rbr;	/* 0 = 0-3 */
		MV_U8 pad1[3];

		MV_U8 ier;	/* 1 = 4-7 */
		MV_U8 pad2[3];

		MV_U8 fcr;	/* 2 = 8-b */
		MV_U8 pad3[3];

		MV_U8 lcr;	/* 3 = c-f */
		MV_U8 pad4[3];

		MV_U8 mcr;	/* 4 = 10-13 */
		MV_U8 pad5[3];

		MV_U8 lsr;	/* 5 = 14-17 */
		MV_U8 pad6[3];

		MV_U8 msr;	/* 6 =18-1b */
		MV_U8 pad7[3];

		MV_U8 scr;	/* 7 =1c-1f */
		MV_U8 pad8[3];
	} MV_UART_PORT;

#if defined(MV_UART_OVER_PEX_WA) || defined(MV_UART_OVER_PCI_WA)
#define mvUartBase(port)  \
		((MV_UART_PORT *)(0xF2000000 + MV_UART_REGS_OFFSET(port)))
#else
#define mvUartBase(port)  \
		((MV_UART_PORT *)(INTER_REGS_BASE + MV_UART_REGS_OFFSET(port)))
#endif

/* aliases - for registers which has the same offsets */
#define thr rbr
#define iir fcr
#define dll rbr
#define dlm ier

/* registers feilds */
#define FCR_FIFO_EN     	BIT0	/* fifo enable */
#define FCR_RXSR        	BIT1	/* reciever soft reset */
#define FCR_TXSR        	BIT2	/* transmitter soft reset */

#define MCR_RTS         	BIT1	/* ready to send */
#define MCR_AFCE         	BIT5	/* Auto Flow Control Enable */

#define LCR_WLS_OFFS		0
#define LCR_WLS_MASK 		(0x3 << LCR_WLS_OFFS)	/* character length mask  */
#define LCR_WLS_5   		(0x0 << LCR_WLS_OFFS)	/* 5 bit character length */
#define LCR_WLS_6   		(0x1 << LCR_WLS_OFFS)	/* 6 bit character length */
#define LCR_WLS_7   		(0x2 << LCR_WLS_OFFS)	/* 7 bit character length */
#define LCR_WLS_8   		(0x3 << LCR_WLS_OFFS)	/* 8 bit character length */
#define LCR_STP_OFFS		2
#define LCR_1_STB     		(0x0 << LCR_STP_OFFS)	/* Number of stop Bits */
#define LCR_2_STB     		(0x1 << LCR_STP_OFFS)	/* Number of stop Bits */
#define LCR_PEN     		0x8	/* Parity eneble */
#define LCR_PS_OFFS		4
#define LCR_EPS     		(0x1 << LCR_PS_OFFS)	/* Even Parity Select */
#define LCR_OPS     		(0x0 << LCR_PS_OFFS)	/* Odd Parity Select */
#define LCR_SBRK_OFFS		0x6
#define LCR_SBRK    		(0x1 << LCR_SBRK_OFFS)	/* Set Break */
#define LCR_DIVL_OFFS		7
#define LCR_DIVL_EN    		(0x1 << LCR_DIVL_OFFS)	/* Divisior latch enable */

#define LSR_DR      		BIT0	/* Data ready */
#define LSR_OE      		BIT1	/* Overrun */
#define LSR_PE      		BIT2	/* Parity error */
#define LSR_FE      		BIT3	/* Framing error */
#define LSR_BI      		BIT4	/* Break */
#define LSR_THRE    		BIT5	/* Xmit holding register empty */
#define LSR_TEMT    		BIT6	/* Xmitter empty */
#define LSR_ERR     		BIT7	/* Error */

/* useful defaults for LCR*/
#define LCR_8N1     (LCR_WLS_8 | LCR_1_STB)

/* APIs */
	MV_VOID mvUartPutc(MV_U32 port, MV_U8 c);
	MV_U8 mvUartGetc(MV_U32 port);
	MV_BOOL mvUartTstc(MV_U32 port);
	MV_VOID mvUartInit(MV_U32 port, MV_U32 baudDivisor, MV_UART_PORT *base);

#ifdef __cplusplus
}
#endif
#endif