diff --git a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvLib.c b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvLib.c
index 38b5617..28979e1 100644
--- a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvLib.c
@@ -2296,7 +2296,8 @@
 		mvOsOutput("       3xFE PHY Module.\n");
 
 	/* Internal FE/GE Phy */
-	if (DB_88F6601_BP_ID == mvBoardIdGet()) {
+	if (DB_88F6601_BP_ID == mvBoardIdGet() ||
+            GFLT400_ID == mvBoardIdGet() ) {
 		if (ethConfig & ESC_OPT_GEPHY_MAC0) {
 			mvOsOutput("       GE-PHY on MAC0.\n");
 			mvOsOutput("       LP SERDES on MAC1.\n");
diff --git a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.c b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.c
index 902a50e..a03b2bd 100644
--- a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.c
+++ b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.c
@@ -1714,7 +1714,7 @@
 MV_BOARD_MPP_TYPE_INFO gflt400InfoBoardMppTypeInfo[] = {
 	{
 		.boardMppTdm = MV_BOARD_AUTO,
-		.ethSataComplexOpt = ESC_OPT_GEPHY_MAC0,
+		.ethSataComplexOpt = ESC_OPT_GEPHY_MAC0 | ESC_OPT_SGMII,
 		.ethPortsMode = 0x0
 	}
 };
diff --git a/board/mv_feroceon/mv_kw2/mv_phy.c b/board/mv_feroceon/mv_kw2/mv_phy.c
index d5f8ce9..bf374ad 100755
--- a/board/mv_feroceon/mv_kw2/mv_phy.c
+++ b/board/mv_feroceon/mv_kw2/mv_phy.c
@@ -489,6 +489,14 @@
       MV_REG_WRITE(SYNC_PATTERN_REG, reg |= (1 << 10));
     }
 
+    // Configuring this bit sets eth1 into SGMII, which Marvell's patch does do
+    // for 2.5G (right below), but not for 1G. So we had to add it manually
+    if (mvBoardIdGet() == GFLT400_ID)
+    {
+      reg = MV_REG_READ(PORT_MAC_CTRL_REG2(port));
+      MV_REG_WRITE(PORT_MAC_CTRL_REG2(port), reg |= (1 << 3));
+      printf("MTL: Init SGMII@1G on MAC %d: 0x%x=0x%x\n", port, PORT_MAC_CTRL_REG2(port), reg |= (1 << 3));
+    }
   }
   else if (mode == PHY_SGMII_2_5G)
   {