diff --git a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.c b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.c
index 655b861..93f1019 100644
--- a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.c
+++ b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.c
@@ -1189,6 +1189,15 @@
 	{BOARD_GPP_LED, 24, .activeLow = 1, .name = "eth-link"},
 };
 
+MV_BOARD_GPP_INFO gflt200Evt2InfoBoardGppInfo[] = {
+	/* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
+	{BOARD_GPP_PON_XVR_TX, 17},
+	{BOARD_GPP_LED, 11, .name = "pon-red"},
+	{BOARD_GPP_LED, 12, .name = "pon-blue"},
+	{BOARD_GPP_LED, 14, .activeLow = 1, .name = "eth-link"},
+	{BOARD_GPP_LED, 26, .activeLow = 1, .name = "eth-data"},
+};
+
 MV_DEV_CS_INFO gflt200InfoBoardDeCsInfo[] = {
 	/*{deviceCS, params, devType, devWidth} */
 #ifdef MV_SPI
@@ -1210,6 +1219,17 @@
 	 }
 };
 
+MV_BOARD_MPP_INFO gflt200Evt2InfoBoardMppConfigValue[] = {
+	{{
+	  GFLT200_EVT2_MPP0_7,
+	  GFLT200_EVT2_MPP8_15,
+	  GFLT200_EVT2_MPP16_23,
+	  GFLT200_EVT2_MPP24_31,
+	  GFLT200_EVT2_MPP32_37
+	  }
+	 }
+};
+
 /*
 MV_BOARD_SPEC_INIT gflt200BoardSpecInit[] = {
 	{
@@ -1226,6 +1246,7 @@
 
 #define GFLT200_GPP_BOARD_VER_MASK	((1 << 18) | (1 << 15) | (1 << 13))
 #define GFLT200_EVT1_BOARD_VER		(0)
+#define GFLT200_EVT2_BOARD_VER		(1 << 13)
 
 static MV_VOID gflt200BoardInit(MV_BOARD_INFO *pBoardInfo)
 {
@@ -1233,7 +1254,6 @@
 
 	switch (mvGppValueGet(0, GFLT200_GPP_BOARD_VER_MASK)) {
 	case GFLT200_EVT1_BOARD_VER:
-	default: /* latest */
 		pBoardInfo->numBoardMppConfigValue
 			= MV_ARRAY_SIZE(gflt200Evt1InfoBoardMppConfigValue);
 		pBoardInfo->pBoardMppConfigValue
@@ -1248,6 +1268,24 @@
 		pBoardInfo->gppPolarityValLow = GFLT200_EVT1_GPP_POL_LOW;
 		pBoardInfo->gppPolarityValMid = GFLT200_EVT1_GPP_POL_MID;
 		break;
+
+	default:
+		/* fallthrough */
+	case GFLT200_EVT2_BOARD_VER:
+		pBoardInfo->numBoardMppConfigValue
+			= MV_ARRAY_SIZE(gflt200Evt2InfoBoardMppConfigValue);
+		pBoardInfo->pBoardMppConfigValue
+			= gflt200Evt2InfoBoardMppConfigValue;
+		pBoardInfo->numBoardGppInfo
+			= MV_ARRAY_SIZE(gflt200Evt2InfoBoardGppInfo);
+		pBoardInfo->pBoardGppInfo = gflt200Evt2InfoBoardGppInfo;
+		pBoardInfo->gppOutEnValLow = GFLT200_EVT2_GPP_OUT_ENA_LOW;
+		pBoardInfo->gppOutEnValMid = GFLT200_EVT2_GPP_OUT_ENA_MID;
+		pBoardInfo->gppOutValLow = GFLT200_EVT2_GPP_OUT_VAL_LOW;
+		pBoardInfo->gppOutValMid = GFLT200_EVT2_GPP_OUT_VAL_MID;
+		pBoardInfo->gppPolarityValLow = GFLT200_EVT2_GPP_POL_LOW;
+		pBoardInfo->gppPolarityValMid = GFLT200_EVT2_GPP_POL_MID;
+		break;
 	}
 }
 
diff --git a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.h b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.h
index 50ffbd1..25c29b8 100644
--- a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.h
+++ b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.h
@@ -472,34 +472,47 @@
 #define GFLT200_EVT1_MPP24_31		0x40200000
 #define GFLT200_EVT1_MPP32_37		0x00000004
 
+#define GFLT200_EVT2_MPP0_7		0x22222220
+#define GFLT200_EVT2_MPP8_15		0x00000002
+#define GFLT200_EVT2_MPP16_23		0x00000000
+#define GFLT200_EVT2_MPP24_31		0x40200004
+#define GFLT200_EVT2_MPP32_37		0x00000004
+
 /* GPPs
- 1 SPI_MOSI (out)
- 2 SPI_SCK (out)
- 3 SPI_CS_L (out)
- 4 SPI_MISO (in)
- 5 I2C_SDA (inout)
- 6 I2C_SCLK (inout)
- 7 UART0_TX (out)
- 8 UART0_RX (in)
- 9 VDD_MARGIN_EN (out)
-10 VDD_MARGIN_CTRL (out)
-11 PON_LINK_LED (out)
-12 PON_ERROR_LED (out)
-13 BOARD_VER[0] (in)
-15 BOARD_VER[1] (in)
-17 SW_RESET (out)
-18 BOARD_VER[2] (in)
-21 PON_TX_DIS (out)
-23 GE_DATA_LED (out)
-24 GE_LINK_LED (out)
-26 PON_C2_DATA (out)
-27 PON_C2_CLK (out)
-28 SPI_WP_L (out)
-29 PON_RX_LOS (in)
-31 UART1_RX (out)
-32 UART2_TX (in)
-36 PON_RX_PMON (in)
-37 PON_PWR_EN_L (out)
+   ... ditto
+   --- unused
+
+   EVT1                   EVT2
+ 1 SPI_MOSI (out)         ...
+ 2 SPI_SCK (out)          ...
+ 3 SPI_CS_L (out)         ...
+ 4 SPI_MISO (in)          ...
+ 5 I2C_SDA (inout)        ...
+ 6 I2C_SCLK (out)         ...
+ 7 UART0_TX (out)         ...
+ 8 UART0_RX (in)          ...
+ 9 VDD_MARGIN_EN (out)    ---
+10 VDD_MARGIN_CTRL (out)  ---
+11 PON_LINK_LED (out)     PON_LED_RED (out)
+12 PON_ERROR_LED (out)    PON_LED_BLUE (out)
+13 BOARD_VER[0] (in)      ...
+14 ---                    GE_LINK_LED (out)
+15 BOARD_VER[1] (in)      ...
+17 SW_RESET (out)         ...
+18 BOARD_VER[2] (in)      ...
+21 PON_TX_DIS (out)       ...
+22 ---                    DOLOS_DETECT (in)
+23 GE_DATA_LED (out)      ---
+24 GE_LINK_LED (out)      PTP_TRIG_GEN (out)
+25 ---                    PTP_EVENT_REQ (in)
+26 PON_C2_DATA (out)      GE_DATA_LED (out)
+27 PON_C2_CLK (out)       PTP_CLK (in)
+28 SPI_WP_L (out)         ...
+29 PON_RX_LOS (in)        ...
+31 UART1_RX (out)         ...
+32 UART2_TX (in)          ...
+36 PON_RX_PMON (in)       ...
+37 PON_PWR_EN_L (out)     ...
 */
 
 #define GFLT200_EVT1_GPP_OUT_ENA_LOW	(BIT13 | BIT15 | BIT18 | BIT29)
@@ -511,6 +524,14 @@
 #define GFLT200_EVT1_GPP_POL_LOW	0x0
 #define GFLT200_EVT1_GPP_POL_MID	0x0
 
+#define GFLT200_EVT2_GPP_OUT_ENA_LOW	(BIT13 | BIT15 | BIT18 | BIT22 | BIT29)
+#define GFLT200_EVT2_GPP_OUT_ENA_MID	(BIT4)
+
+#define GFLT200_EVT2_GPP_OUT_VAL_LOW	(BIT21 | BIT28)
+#define GFLT200_EVT2_GPP_OUT_VAL_MID	0x0
+
+#define GFLT200_EVT2_GPP_POL_LOW	0x0
+#define GFLT200_EVT2_GPP_POL_MID	0x0
 
 /***************************************************************************
 ** GFLT110