#include "comcerto_2000.h"

/* DDR Controller Registers */
#define DDRC_CTL_00_REG          (COMCERTO_APB_DDR_BASE + 0x00)
#define DDRC_CTL_01_REG          (COMCERTO_APB_DDR_BASE + 0x04)
#define DDRC_CTL_02_REG          (COMCERTO_APB_DDR_BASE + 0x08)
#define DDRC_CTL_03_REG          (COMCERTO_APB_DDR_BASE + 0x0c)
#define DDRC_CTL_04_REG          (COMCERTO_APB_DDR_BASE + 0x10)
#define DDRC_CTL_05_REG          (COMCERTO_APB_DDR_BASE + 0x14)
#define DDRC_CTL_06_REG          (COMCERTO_APB_DDR_BASE + 0x18)
#define DDRC_CTL_07_REG          (COMCERTO_APB_DDR_BASE + 0x1c)
#define DDRC_CTL_08_REG          (COMCERTO_APB_DDR_BASE + 0x20)
#define DDRC_CTL_09_REG          (COMCERTO_APB_DDR_BASE + 0x24)
#define DDRC_CTL_10_REG          (COMCERTO_APB_DDR_BASE + 0x28)
#define DDRC_CTL_11_REG          (COMCERTO_APB_DDR_BASE + 0x2c)
#define DDRC_CTL_12_REG          (COMCERTO_APB_DDR_BASE + 0x30)
#define DDRC_CTL_13_REG          (COMCERTO_APB_DDR_BASE + 0x34)
#define DDRC_CTL_14_REG          (COMCERTO_APB_DDR_BASE + 0x38)
#define DDRC_CTL_15_REG          (COMCERTO_APB_DDR_BASE + 0x3c)
#define DDRC_CTL_16_REG          (COMCERTO_APB_DDR_BASE + 0x40)
#define DDRC_CTL_17_REG          (COMCERTO_APB_DDR_BASE + 0x44)
#define DDRC_CTL_18_REG          (COMCERTO_APB_DDR_BASE + 0x48)
#define DDRC_CTL_19_REG          (COMCERTO_APB_DDR_BASE + 0x4c)
#define DDRC_CTL_20_REG          (COMCERTO_APB_DDR_BASE + 0x50)
#define DDRC_CTL_21_REG          (COMCERTO_APB_DDR_BASE + 0x54)
#define DDRC_CTL_22_REG          (COMCERTO_APB_DDR_BASE + 0x58)
#define DDRC_CTL_23_REG          (COMCERTO_APB_DDR_BASE + 0x5c)
#define DDRC_CTL_24_REG          (COMCERTO_APB_DDR_BASE + 0x60)
#define DDRC_CTL_25_REG          (COMCERTO_APB_DDR_BASE + 0x64)
#define DDRC_CTL_26_REG          (COMCERTO_APB_DDR_BASE + 0x68)
#define DDRC_CTL_27_REG          (COMCERTO_APB_DDR_BASE + 0x6c)
#define DDRC_CTL_28_REG          (COMCERTO_APB_DDR_BASE + 0x70)
#define DDRC_CTL_29_REG          (COMCERTO_APB_DDR_BASE + 0x74)
#define DDRC_CTL_30_REG          (COMCERTO_APB_DDR_BASE + 0x78)
#define DDRC_CTL_31_REG          (COMCERTO_APB_DDR_BASE + 0x7c)
#define DDRC_CTL_32_REG          (COMCERTO_APB_DDR_BASE + 0x80)
#define DDRC_CTL_33_REG          (COMCERTO_APB_DDR_BASE + 0x84)
#define DDRC_CTL_34_REG          (COMCERTO_APB_DDR_BASE + 0x88)
#define DDRC_CTL_35_REG          (COMCERTO_APB_DDR_BASE + 0x8c)
#define DDRC_CTL_36_REG          (COMCERTO_APB_DDR_BASE + 0x90)
#define DDRC_CTL_37_REG          (COMCERTO_APB_DDR_BASE + 0x94)
#define DDRC_CTL_38_REG          (COMCERTO_APB_DDR_BASE + 0x98)
#define DDRC_CTL_39_REG          (COMCERTO_APB_DDR_BASE + 0x9c)
#define DDRC_CTL_40_REG          (COMCERTO_APB_DDR_BASE + 0xa0)
#define DDRC_CTL_41_REG          (COMCERTO_APB_DDR_BASE + 0xa4)
#define DDRC_CTL_42_REG          (COMCERTO_APB_DDR_BASE + 0xa8)
#define DDRC_CTL_43_REG          (COMCERTO_APB_DDR_BASE + 0xac)
#define DDRC_CTL_44_REG          (COMCERTO_APB_DDR_BASE + 0xb0)
#define DDRC_CTL_45_REG          (COMCERTO_APB_DDR_BASE + 0xb4)
#define DDRC_CTL_46_REG          (COMCERTO_APB_DDR_BASE + 0xb8)
#define DDRC_CTL_47_REG          (COMCERTO_APB_DDR_BASE + 0xbc)
#define DDRC_CTL_48_REG          (COMCERTO_APB_DDR_BASE + 0xc0)
#define DDRC_CTL_49_REG          (COMCERTO_APB_DDR_BASE + 0xc4)
#define DDRC_CTL_50_REG          (COMCERTO_APB_DDR_BASE + 0xc8)
#define DDRC_CTL_51_REG          (COMCERTO_APB_DDR_BASE + 0xcc)
#define DDRC_CTL_52_REG          (COMCERTO_APB_DDR_BASE + 0xd0)
#define DDRC_CTL_53_REG          (COMCERTO_APB_DDR_BASE + 0xd4)
#define DDRC_CTL_54_REG          (COMCERTO_APB_DDR_BASE + 0xd8)
#define DDRC_CTL_55_REG          (COMCERTO_APB_DDR_BASE + 0xdc)
#define DDRC_CTL_56_REG          (COMCERTO_APB_DDR_BASE + 0xe0)
#define DDRC_CTL_57_REG          (COMCERTO_APB_DDR_BASE + 0xe4)
#define DDRC_CTL_58_REG          (COMCERTO_APB_DDR_BASE + 0xe8)
#define DDRC_CTL_59_REG          (COMCERTO_APB_DDR_BASE + 0xec)
#define DDRC_CTL_60_REG          (COMCERTO_APB_DDR_BASE + 0xf0)
#define DDRC_CTL_61_REG          (COMCERTO_APB_DDR_BASE + 0xf4)
#define DDRC_CTL_62_REG          (COMCERTO_APB_DDR_BASE + 0xf8)
#define DDRC_CTL_63_REG          (COMCERTO_APB_DDR_BASE + 0xfc)
#define DDRC_CTL_64_REG          (COMCERTO_APB_DDR_BASE + 0x100)
#define DDRC_CTL_65_REG          (COMCERTO_APB_DDR_BASE + 0x104)
#define DDRC_CTL_66_REG          (COMCERTO_APB_DDR_BASE + 0x108)
#define DDRC_CTL_67_REG          (COMCERTO_APB_DDR_BASE + 0x10c)
#define DDRC_CTL_68_REG          (COMCERTO_APB_DDR_BASE + 0x110)
#define DDRC_CTL_69_REG          (COMCERTO_APB_DDR_BASE + 0x114)
#define DDRC_CTL_70_REG          (COMCERTO_APB_DDR_BASE + 0x118)
#define DDRC_CTL_71_REG          (COMCERTO_APB_DDR_BASE + 0x11c)
#define DDRC_CTL_72_REG          (COMCERTO_APB_DDR_BASE + 0x120)
#define DDRC_CTL_73_REG          (COMCERTO_APB_DDR_BASE + 0x124)
#define DDRC_CTL_74_REG          (COMCERTO_APB_DDR_BASE + 0x128)
#define DDRC_CTL_75_REG          (COMCERTO_APB_DDR_BASE + 0x12c)
#define DDRC_CTL_76_REG          (COMCERTO_APB_DDR_BASE + 0x130)
#define DDRC_CTL_77_REG          (COMCERTO_APB_DDR_BASE + 0x134)
#define DDRC_CTL_78_REG          (COMCERTO_APB_DDR_BASE + 0x138)
#define DDRC_CTL_79_REG          (COMCERTO_APB_DDR_BASE + 0x13c)
#define DDRC_CTL_80_REG          (COMCERTO_APB_DDR_BASE + 0x140)
#define DDRC_CTL_81_REG          (COMCERTO_APB_DDR_BASE + 0x144)
#define DDRC_CTL_82_REG          (COMCERTO_APB_DDR_BASE + 0x148)
#define DDRC_CTL_83_REG          (COMCERTO_APB_DDR_BASE + 0x14c)
#define DDRC_CTL_84_REG          (COMCERTO_APB_DDR_BASE + 0x150)
#define DDRC_CTL_85_REG          (COMCERTO_APB_DDR_BASE + 0x154)
#define DDRC_CTL_86_REG          (COMCERTO_APB_DDR_BASE + 0x158)
#define DDRC_CTL_87_REG          (COMCERTO_APB_DDR_BASE + 0x15c)
#define DDRC_CTL_88_REG          (COMCERTO_APB_DDR_BASE + 0x160)
#define DDRC_CTL_89_REG          (COMCERTO_APB_DDR_BASE + 0x164)
#define DDRC_CTL_90_REG          (COMCERTO_APB_DDR_BASE + 0x168)
#define DDRC_CTL_91_REG          (COMCERTO_APB_DDR_BASE + 0x16c)
#define DDRC_CTL_92_REG          (COMCERTO_APB_DDR_BASE + 0x170)
#define DDRC_CTL_93_REG          (COMCERTO_APB_DDR_BASE + 0x174)
#define DDRC_CTL_94_REG          (COMCERTO_APB_DDR_BASE + 0x178)
#define DDRC_CTL_95_REG          (COMCERTO_APB_DDR_BASE + 0x17c)
#define DDRC_CTL_96_REG          (COMCERTO_APB_DDR_BASE + 0x180)
#define DDRC_CTL_97_REG          (COMCERTO_APB_DDR_BASE + 0x184)
#define DDRC_CTL_98_REG          (COMCERTO_APB_DDR_BASE + 0x188)
#define DDRC_CTL_99_REG          (COMCERTO_APB_DDR_BASE + 0x18c)
#define DDRC_CTL_100_REG          (COMCERTO_APB_DDR_BASE + 0x190)
#define DDRC_CTL_101_REG          (COMCERTO_APB_DDR_BASE + 0x194)
#define DDRC_CTL_102_REG          (COMCERTO_APB_DDR_BASE + 0x198)
#define DDRC_CTL_103_REG          (COMCERTO_APB_DDR_BASE + 0x19c)
#define DDRC_CTL_104_REG          (COMCERTO_APB_DDR_BASE + 0x1a0)
#define DDRC_CTL_105_REG          (COMCERTO_APB_DDR_BASE + 0x1a4)
#define DDRC_CTL_106_REG          (COMCERTO_APB_DDR_BASE + 0x1a8)
#define DDRC_CTL_107_REG          (COMCERTO_APB_DDR_BASE + 0x1ac)
#define DDRC_CTL_108_REG          (COMCERTO_APB_DDR_BASE + 0x1b0)
#define DDRC_CTL_109_REG          (COMCERTO_APB_DDR_BASE + 0x1b4)
#define DDRC_CTL_110_REG          (COMCERTO_APB_DDR_BASE + 0x1b8)
#define DDRC_CTL_111_REG          (COMCERTO_APB_DDR_BASE + 0x1bc)
#define DDRC_CTL_112_REG          (COMCERTO_APB_DDR_BASE + 0x1c0)
#define DDRC_CTL_113_REG          (COMCERTO_APB_DDR_BASE + 0x1c4)
#define DDRC_CTL_114_REG          (COMCERTO_APB_DDR_BASE + 0x1c8)
#define DDRC_CTL_115_REG          (COMCERTO_APB_DDR_BASE + 0x1cc)
#define DDRC_CTL_116_REG          (COMCERTO_APB_DDR_BASE + 0x1d0)
#define DDRC_CTL_117_REG          (COMCERTO_APB_DDR_BASE + 0x1d4)
#define DDRC_CTL_118_REG          (COMCERTO_APB_DDR_BASE + 0x1d8)
#define DDRC_CTL_119_REG          (COMCERTO_APB_DDR_BASE + 0x1dc)
#define DDRC_CTL_120_REG          (COMCERTO_APB_DDR_BASE + 0x1e0)
#define DDRC_CTL_121_REG          (COMCERTO_APB_DDR_BASE + 0x1e4)
#define DDRC_CTL_122_REG          (COMCERTO_APB_DDR_BASE + 0x1e8)
#define DDRC_CTL_123_REG          (COMCERTO_APB_DDR_BASE + 0x1ec)
#define DDRC_CTL_124_REG          (COMCERTO_APB_DDR_BASE + 0x1f0)
#define DDRC_CTL_125_REG          (COMCERTO_APB_DDR_BASE + 0x1f4)
#define DDRC_CTL_126_REG          (COMCERTO_APB_DDR_BASE + 0x1f8)

/* DDR PHY Registers */
#define DDR_PHY_CTL_00_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x00)
#define DDR_PHY_CTL_01_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x04)
#define DDR_PHY_CTL_02_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x08)
#define DDR_PHY_CTL_03_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x0C)
#define DDR_PHY_CTL_04_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x10)
#define DDR_PHY_CTL_05_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x14)
#define DDR_PHY_CTL_06_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x18)
#define DDR_PHY_CTL_07_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x1C)
#define DDR_PHY_DLL_STAT_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x70)
#define DDR_PHY_ZQ_STAT_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x74)

//DDR2@ 400MHz
#define DDRC_CTL_DDR2_00_VAL_CFG1  0x00000400
//#define DDRC_CTL_DDR2_01_VAL_CFG1 0x00000000
#define DDRC_CTL_DDR2_02_VAL_CFG1  0x00000050
#define DDRC_CTL_DDR2_03_VAL_CFG1  0x00000050
#define DDRC_CTL_DDR2_04_VAL_CFG1  0x000000c8
#define DDRC_CTL_DDR2_05_VAL_CFG1  0x02050c02
#define DDRC_CTL_DDR2_06_VAL_CFG1  0x10160302
#define DDRC_CTL_DDR2_07_VAL_CFG1  0x02030603
#define DDRC_CTL_DDR2_08_VAL_CFG1  0x006d6005
#define DDRC_CTL_DDR2_09_VAL_CFG1  0x00000303
#define DDRC_CTL_DDR2_10_VAL_CFG1  0x06060101
#define DDRC_CTL_DDR2_11_VAL_CFG1  0x0000c80c
#define DDRC_CTL_DDR2_12_VAL_CFG1  0x00a00e02
#define DDRC_CTL_DDR2_13_VAL_CFG1  0x00000007
#define DDRC_CTL_DDR2_14_VAL_CFG1  0x00330100
#define DDRC_CTL_DDR2_15_VAL_CFG1  0x00000c2d
#define DDRC_CTL_DDR2_16_VAL_CFG1  0x000a0003
#define DDRC_CTL_DDR2_17_VAL_CFG1  0x000a0003
#define DDRC_CTL_DDR2_18_VAL_CFG1  0x003700c8
#define DDRC_CTL_DDR2_19_VAL_CFG1  0x00010000
#define DDRC_CTL_DDR2_20_VAL_CFG1  0x00030300
#define DDRC_CTL_DDR2_21_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_22_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_23_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_24_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_25_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_26_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_27_VAL_CFG1  0x000a6200
#define DDRC_CTL_DDR2_28_VAL_CFG1  0x00000004
#define DDRC_CTL_DDR2_29_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_30_VAL_CFG1  0x00040a62
#define DDRC_CTL_DDR2_31_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_32_VAL_CFG1  0x00020000
#define DDRC_CTL_DDR2_33_VAL_CFG1  0x00000000
//#define DDRC_CTL_DDR2_34_VAL_CFG1 0x00000000
//#define DDRC_CTL_DDR2_35_VAL_CFG1 0x00000000
//#define DDRC_CTL_DDR2_36_VAL_CFG1 0x00000000
//#define DDRC_CTL_DDR2_37_VAL_CFG1 0x00000000
//#define DDRC_CTL_DDR2_38_VAL_CFG1 0x00000000
//#define DDRC_CTL_DDR2_39_VAL_CFG1 0x00000000
//#define DDRC_CTL_DDR2_40_VAL_CFG1 0x00000000
//#define DDRC_CTL_DDR2_41_VAL_CFG1 0x00000000
//#define DDRC_CTL_DDR2_42_VAL_CFG1 0x00000000
#define DDRC_CTL_DDR2_43_VAL_CFG1  0x01000200
#define DDRC_CTL_DDR2_44_VAL_CFG1  0x02000040
#define DDRC_CTL_DDR2_45_VAL_CFG1  0x00010040
#define DDRC_CTL_DDR2_46_VAL_CFG1  0xff0a0203
#define DDRC_CTL_DDR2_47_VAL_CFG1  0x010101ff
#define DDRC_CTL_DDR2_48_VAL_CFG1  0x01010101
#define DDRC_CTL_DDR2_49_VAL_CFG1  0x000c0100
#define DDRC_CTL_DDR2_50_VAL_CFG1  0x00010000
//#define DDRC_CTL_DDR2_51_VAL_CFG1 0x00000000
#define DDRC_CTL_DDR2_52_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_53_VAL_CFG1  0x00000000
//#define DDRC_CTL_DDR2_54_VAL_CFG1 0x00000000
//#define DDRC_CTL_DDR2_55_VAL_CFG1 0x00000000
//#define DDRC_CTL_DDR2_56_VAL_CFG1 0x00000000
//#define DDRC_CTL_DDR2_57_VAL_CFG1 0x00000000
//#define DDRC_CTL_DDR2_58_VAL_CFG1 0x00000000
#define DDRC_CTL_DDR2_59_VAL_CFG1  0x01010000
#define DDRC_CTL_DDR2_60_VAL_CFG1  0x00000202
#define DDRC_CTL_DDR2_61_VAL_CFG1  0x02020302
#define DDRC_CTL_DDR2_62_VAL_CFG1  0x01000101
#define DDRC_CTL_DDR2_63_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_64_VAL_CFG1  0x00000000
//#define DDRC_CTL_DDR2_65_VAL_CFG1 0x00000000
#define DDRC_CTL_DDR2_66_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_67_VAL_CFG1  0x00281900
#define DDRC_CTL_DDR2_68_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_69_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_70_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_71_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_72_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_73_VAL_CFG1  0x00000000
//#define DDRC_CTL_DDR2_74_VAL_CFG1 0x00000000
#define DDRC_CTL_DDR2_75_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_76_VAL_CFG1  0x001d1d00
#define DDRC_CTL_DDR2_77_VAL_CFG1  0x00000000
//#define DDRC_CTL_DDR2_78_VAL_CFG1 0x00000000
#define DDRC_CTL_DDR2_79_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_80_VAL_CFG1  0x00001d1d
//#define DDRC_CTL_DDR2_81_VAL_CFG1 0x00000000
#define DDRC_CTL_DDR2_82_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_83_VAL_CFG1  0x001d1d00
#define DDRC_CTL_DDR2_84_VAL_CFG1  0x00000000
//#define DDRC_CTL_DDR2_85_VAL_CFG1 0x00000000
#define DDRC_CTL_DDR2_86_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_87_VAL_CFG1  0x00001d1d
//#define DDRC_CTL_DDR2_88_VAL_CFG1 0x00000000
#define DDRC_CTL_DDR2_89_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_90_VAL_CFG1  0x001d1d00
#define DDRC_CTL_DDR2_91_VAL_CFG1  0xffff0000
#define DDRC_CTL_DDR2_92_VAL_CFG1  0x00000202
#define DDRC_CTL_DDR2_93_VAL_CFG1  0x0101ffff
#define DDRC_CTL_DDR2_94_VAL_CFG1  0x02ffff00
#define DDRC_CTL_DDR2_95_VAL_CFG1  0xffff0002
#define DDRC_CTL_DDR2_96_VAL_CFG1  0x00000202
#define DDRC_CTL_DDR2_97_VAL_CFG1  0x01320300
#define DDRC_CTL_DDR2_98_VAL_CFG1  0x00013200
#define DDRC_CTL_DDR2_99_VAL_CFG1  0x32000132
#define DDRC_CTL_DDR2_100_VAL_CFG1  0x00000001
#define DDRC_CTL_DDR2_101_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_102_VAL_CFG1  0x00000700
#define DDRC_CTL_DDR2_103_VAL_CFG1  0x000c2d00
#define DDRC_CTL_DDR2_104_VAL_CFG1  0x02000200
#define DDRC_CTL_DDR2_105_VAL_CFG1  0x02000200
#define DDRC_CTL_DDR2_106_VAL_CFG1  0x00000c2d
#define DDRC_CTL_DDR2_107_VAL_CFG1  0x00003ce1
#define DDRC_CTL_DDR2_108_VAL_CFG1  0x0002050C
#define DDRC_CTL_DDR2_109_VAL_CFG1  0x03800001
#define DDRC_CTL_DDR2_110_VAL_CFG1  0x00040703
#define DDRC_CTL_DDR2_111_VAL_CFG1  0x0000000a
#define DDRC_CTL_DDR2_112_VAL_CFG1  0x00000c2d
#define DDRC_CTL_DDR2_113_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_114_VAL_CFG1  0x0010ffff
#define DDRC_CTL_DDR2_115_VAL_CFG1  0x11070303
#define DDRC_CTL_DDR2_116_VAL_CFG1  0x0000000f
#define DDRC_CTL_DDR2_117_VAL_CFG1  0x00000c2d
#define DDRC_CTL_DDR2_118_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_119_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_120_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_121_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_122_VAL_CFG1  0x00000c2d
#define DDRC_CTL_DDR2_123_VAL_CFG1  0x00000204
//#define DDRC_CTL_DDR2_124_VAL_CFG1 0x00000000
#define DDRC_CTL_DDR2_125_VAL_CFG1  0x00000000
#define DDRC_CTL_DDR2_126_VAL_CFG1  0x00000001


#define DDRC_DDR2_CFG_400 \
{DDRC_CTL_00_REG, DDRC_CTL_DDR2_00_VAL_CFG1},\
{DDRC_CTL_03_REG, DDRC_CTL_DDR2_03_VAL_CFG1},\
{DDRC_CTL_04_REG, DDRC_CTL_DDR2_04_VAL_CFG1},\
{DDRC_CTL_05_REG, DDRC_CTL_DDR2_05_VAL_CFG1},\
{DDRC_CTL_06_REG, DDRC_CTL_DDR2_06_VAL_CFG1},\
{DDRC_CTL_07_REG, DDRC_CTL_DDR2_07_VAL_CFG1},\
{DDRC_CTL_08_REG, DDRC_CTL_DDR2_08_VAL_CFG1},\
{DDRC_CTL_09_REG, DDRC_CTL_DDR2_09_VAL_CFG1},\
{DDRC_CTL_10_REG, DDRC_CTL_DDR2_10_VAL_CFG1},\
{DDRC_CTL_11_REG, DDRC_CTL_DDR2_11_VAL_CFG1},\
{DDRC_CTL_12_REG, DDRC_CTL_DDR2_12_VAL_CFG1},\
{DDRC_CTL_13_REG, DDRC_CTL_DDR2_13_VAL_CFG1},\
{DDRC_CTL_14_REG, DDRC_CTL_DDR2_14_VAL_CFG1},\
{DDRC_CTL_15_REG, DDRC_CTL_DDR2_15_VAL_CFG1},\
{DDRC_CTL_16_REG, DDRC_CTL_DDR2_16_VAL_CFG1},\
{DDRC_CTL_17_REG, DDRC_CTL_DDR2_17_VAL_CFG1},\
{DDRC_CTL_18_REG, DDRC_CTL_DDR2_18_VAL_CFG1},\
{DDRC_CTL_19_REG, DDRC_CTL_DDR2_19_VAL_CFG1},\
{DDRC_CTL_20_REG, DDRC_CTL_DDR2_20_VAL_CFG1},\
{DDRC_CTL_21_REG, DDRC_CTL_DDR2_21_VAL_CFG1},\
{DDRC_CTL_22_REG, DDRC_CTL_DDR2_22_VAL_CFG1},\
{DDRC_CTL_23_REG, DDRC_CTL_DDR2_23_VAL_CFG1},\
{DDRC_CTL_24_REG, DDRC_CTL_DDR2_24_VAL_CFG1},\
{DDRC_CTL_25_REG, DDRC_CTL_DDR2_25_VAL_CFG1},\
{DDRC_CTL_26_REG, DDRC_CTL_DDR2_26_VAL_CFG1},\
{DDRC_CTL_27_REG, DDRC_CTL_DDR2_27_VAL_CFG1},\
{DDRC_CTL_28_REG, DDRC_CTL_DDR2_28_VAL_CFG1},\
{DDRC_CTL_29_REG, DDRC_CTL_DDR2_29_VAL_CFG1},\
{DDRC_CTL_30_REG, DDRC_CTL_DDR2_30_VAL_CFG1},\
{DDRC_CTL_31_REG, DDRC_CTL_DDR2_31_VAL_CFG1},\
{DDRC_CTL_32_REG, DDRC_CTL_DDR2_32_VAL_CFG1},\
{DDRC_CTL_33_REG, DDRC_CTL_DDR2_33_VAL_CFG1},\
{DDRC_CTL_43_REG, DDRC_CTL_DDR2_43_VAL_CFG1},\
{DDRC_CTL_44_REG, DDRC_CTL_DDR2_44_VAL_CFG1},\
{DDRC_CTL_45_REG, DDRC_CTL_DDR2_45_VAL_CFG1},\
{DDRC_CTL_46_REG, DDRC_CTL_DDR2_46_VAL_CFG1},\
{DDRC_CTL_47_REG, DDRC_CTL_DDR2_47_VAL_CFG1},\
{DDRC_CTL_48_REG, DDRC_CTL_DDR2_48_VAL_CFG1},\
{DDRC_CTL_49_REG, DDRC_CTL_DDR2_49_VAL_CFG1},\
{DDRC_CTL_50_REG, DDRC_CTL_DDR2_50_VAL_CFG1},\
{DDRC_CTL_52_REG, DDRC_CTL_DDR2_52_VAL_CFG1},\
{DDRC_CTL_53_REG, DDRC_CTL_DDR2_53_VAL_CFG1},\
{DDRC_CTL_59_REG, DDRC_CTL_DDR2_59_VAL_CFG1},\
{DDRC_CTL_60_REG, DDRC_CTL_DDR2_60_VAL_CFG1},\
{DDRC_CTL_61_REG, DDRC_CTL_DDR2_61_VAL_CFG1},\
{DDRC_CTL_62_REG, DDRC_CTL_DDR2_62_VAL_CFG1},\
{DDRC_CTL_63_REG, DDRC_CTL_DDR2_63_VAL_CFG1},\
{DDRC_CTL_64_REG, DDRC_CTL_DDR2_64_VAL_CFG1},\
{DDRC_CTL_66_REG, DDRC_CTL_DDR2_66_VAL_CFG1},\
{DDRC_CTL_67_REG, DDRC_CTL_DDR2_67_VAL_CFG1},\
{DDRC_CTL_68_REG, DDRC_CTL_DDR2_68_VAL_CFG1},\
{DDRC_CTL_69_REG, DDRC_CTL_DDR2_69_VAL_CFG1},\
{DDRC_CTL_70_REG, DDRC_CTL_DDR2_70_VAL_CFG1},\
{DDRC_CTL_71_REG, DDRC_CTL_DDR2_71_VAL_CFG1},\
{DDRC_CTL_72_REG, DDRC_CTL_DDR2_72_VAL_CFG1},\
{DDRC_CTL_73_REG, DDRC_CTL_DDR2_73_VAL_CFG1},\
{DDRC_CTL_75_REG, DDRC_CTL_DDR2_75_VAL_CFG1},\
{DDRC_CTL_76_REG, DDRC_CTL_DDR2_76_VAL_CFG1},\
{DDRC_CTL_77_REG, DDRC_CTL_DDR2_77_VAL_CFG1},\
{DDRC_CTL_79_REG, DDRC_CTL_DDR2_79_VAL_CFG1},\
{DDRC_CTL_80_REG, DDRC_CTL_DDR2_80_VAL_CFG1},\
{DDRC_CTL_82_REG, DDRC_CTL_DDR2_82_VAL_CFG1},\
{DDRC_CTL_83_REG, DDRC_CTL_DDR2_83_VAL_CFG1},\
{DDRC_CTL_84_REG, DDRC_CTL_DDR2_84_VAL_CFG1},\
{DDRC_CTL_86_REG, DDRC_CTL_DDR2_86_VAL_CFG1},\
{DDRC_CTL_87_REG, DDRC_CTL_DDR2_87_VAL_CFG1},\
{DDRC_CTL_89_REG, DDRC_CTL_DDR2_89_VAL_CFG1},\
{DDRC_CTL_90_REG, DDRC_CTL_DDR2_90_VAL_CFG1},\
{DDRC_CTL_91_REG, DDRC_CTL_DDR2_91_VAL_CFG1},\
{DDRC_CTL_92_REG, DDRC_CTL_DDR2_92_VAL_CFG1},\
{DDRC_CTL_93_REG, DDRC_CTL_DDR2_93_VAL_CFG1},\
{DDRC_CTL_94_REG, DDRC_CTL_DDR2_94_VAL_CFG1},\
{DDRC_CTL_95_REG, DDRC_CTL_DDR2_95_VAL_CFG1},\
{DDRC_CTL_96_REG, DDRC_CTL_DDR2_96_VAL_CFG1},\
{DDRC_CTL_97_REG, DDRC_CTL_DDR2_97_VAL_CFG1},\
{DDRC_CTL_98_REG, DDRC_CTL_DDR2_98_VAL_CFG1},\
{DDRC_CTL_99_REG, DDRC_CTL_DDR2_99_VAL_CFG1},\
{DDRC_CTL_100_REG, DDRC_CTL_DDR2_100_VAL_CFG1},\
{DDRC_CTL_101_REG, DDRC_CTL_DDR2_101_VAL_CFG1},\
{DDRC_CTL_102_REG, DDRC_CTL_DDR2_102_VAL_CFG1},\
{DDRC_CTL_103_REG, DDRC_CTL_DDR2_103_VAL_CFG1},\
{DDRC_CTL_104_REG, DDRC_CTL_DDR2_104_VAL_CFG1},\
{DDRC_CTL_105_REG, DDRC_CTL_DDR2_105_VAL_CFG1},\
{DDRC_CTL_106_REG, DDRC_CTL_DDR2_106_VAL_CFG1},\
{DDRC_CTL_107_REG, DDRC_CTL_DDR2_107_VAL_CFG1},\
{DDRC_CTL_108_REG, DDRC_CTL_DDR2_108_VAL_CFG1},\
{DDRC_CTL_109_REG, DDRC_CTL_DDR2_109_VAL_CFG1},\
{DDRC_CTL_110_REG, DDRC_CTL_DDR2_110_VAL_CFG1},\
{DDRC_CTL_111_REG, DDRC_CTL_DDR2_111_VAL_CFG1},\
{DDRC_CTL_112_REG, DDRC_CTL_DDR2_112_VAL_CFG1},\
{DDRC_CTL_113_REG, DDRC_CTL_DDR2_113_VAL_CFG1},\
{DDRC_CTL_114_REG, DDRC_CTL_DDR2_114_VAL_CFG1},\
{DDRC_CTL_115_REG, DDRC_CTL_DDR2_115_VAL_CFG1},\
{DDRC_CTL_116_REG, DDRC_CTL_DDR2_116_VAL_CFG1},\
{DDRC_CTL_117_REG, DDRC_CTL_DDR2_117_VAL_CFG1},\
{DDRC_CTL_118_REG, DDRC_CTL_DDR2_118_VAL_CFG1},\
{DDRC_CTL_119_REG, DDRC_CTL_DDR2_119_VAL_CFG1},\
{DDRC_CTL_120_REG, DDRC_CTL_DDR2_120_VAL_CFG1},\
{DDRC_CTL_121_REG, DDRC_CTL_DDR2_121_VAL_CFG1},\
{DDRC_CTL_122_REG, DDRC_CTL_DDR2_122_VAL_CFG1},\
{DDRC_CTL_123_REG, DDRC_CTL_DDR2_123_VAL_CFG1},\
{DDRC_CTL_125_REG, DDRC_CTL_DDR2_125_VAL_CFG1},\
{DDRC_CTL_126_REG, DDRC_CTL_DDR2_126_VAL_CFG1}


/******** DDR3 Controller @400MHz *******/
#define DDRC_CTL_DDR3_000_VAL_CFG1  0x20410600LL
//
#define DDRC_CTL_DDR3_002_VAL_CFG1  0x00000006LL
#define DDRC_CTL_DDR3_003_VAL_CFG1  0x0001388ALL
#define DDRC_CTL_DDR3_004_VAL_CFG1  0x00030D4ALL
#define DDRC_CTL_DDR3_005_VAL_CFG1  0x04060E00LL
#define DDRC_CTL_DDR3_006_VAL_CFG1  0x0F150404LL
#define DDRC_CTL_DDR3_007_VAL_CFG1  0x08040604LL
#define DDRC_CTL_DDR3_008_VAL_CFG1  0x006D9C0CLL
#define DDRC_CTL_DDR3_009_VAL_CFG1  0x00000103LL
#define DDRC_CTL_DDR3_010_VAL_CFG1  0x06060101LL
#define DDRC_CTL_DDR3_011_VAL_CFG1  0x0002000CLL
#define DDRC_CTL_DDR3_012_VAL_CFG1  0x00011403LL
#define DDRC_CTL_DDR3_013_VAL_CFG1  0x00000001LL
#define DDRC_CTL_DDR3_014_VAL_CFG1  0x00400100LL
#define DDRC_CTL_DDR3_015_VAL_CFG1  0x00000C26LL
#define DDRC_CTL_DDR3_016_VAL_CFG1  0x000A0003LL
#define DDRC_CTL_DDR3_017_VAL_CFG1  0x00060002LL
#define DDRC_CTL_DDR3_018_VAL_CFG1  0x00440200LL
#define DDRC_CTL_DDR3_019_VAL_CFG1  0x00000000LL
#define DDRC_CTL_DDR3_020_VAL_CFG1  0x00050500LL
#define DDRC_CTL_DDR3_021_VAL_CFG1  0x00000000LL
#define DDRC_CTL_DDR3_022_VAL_CFG1  0x00000000LL
#define DDRC_CTL_DDR3_023_VAL_CFG1  0x00000000LL
#define DDRC_CTL_DDR3_024_VAL_CFG1  0x00000000LL
#define DDRC_CTL_DDR3_025_VAL_CFG1  0x00000000LL
#define DDRC_CTL_DDR3_026_VAL_CFG1  0x00000000LL
#define DDRC_CTL_DDR3_027_VAL_CFG1  0x00043000LL
#define DDRC_CTL_DDR3_028_VAL_CFG1  0x00080006LL
#define DDRC_CTL_DDR3_029_VAL_CFG1  0x00000000LL
#define DDRC_CTL_DDR3_030_VAL_CFG1  0x00060430LL
#define DDRC_CTL_DDR3_031_VAL_CFG1  0x00000008LL
#define DDRC_CTL_DDR3_032_VAL_CFG1  0x00020000LL
#define DDRC_CTL_DDR3_033_VAL_CFG1  0x00000000LL
//
//
//
//
//
//
//
//
//
#define DDRC_CTL_DDR3_043_VAL_CFG1  0x01400200LL
#define DDRC_CTL_DDR3_044_VAL_CFG1  0x02000040LL
#define DDRC_CTL_DDR3_045_VAL_CFG1  0x01010080LL
#define DDRC_CTL_DDR3_046_VAL_CFG1  0xFF0A0102LL
#define DDRC_CTL_DDR3_047_VAL_CFG1  0x010101FFLL
#define DDRC_CTL_DDR3_048_VAL_CFG1  0x00010001LL
#define DDRC_CTL_DDR3_049_VAL_CFG1  0x000C0100LL
#define DDRC_CTL_DDR3_050_VAL_CFG1  0x00010002LL
//
#define DDRC_CTL_DDR3_052_VAL_CFG1  0x00000000LL
#define DDRC_CTL_DDR3_053_VAL_CFG1  0x007FFFFFLL
//
//
//
//
//
#define DDRC_CTL_DDR3_059_VAL_CFG1  0x01000000LL
#define DDRC_CTL_DDR3_060_VAL_CFG1  0x00020100LL
#define DDRC_CTL_DDR3_061_VAL_CFG1  0x02010202LL
#define DDRC_CTL_DDR3_062_VAL_CFG1  0x02000101LL
#define DDRC_CTL_DDR3_063_VAL_CFG1  0x00000000LL
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
#define DDRC_CTL_DDR3_091_VAL_CFG1  0xFFFF0000LL
#define DDRC_CTL_DDR3_092_VAL_CFG1  0x00000202LL
#define DDRC_CTL_DDR3_093_VAL_CFG1  0x0101FFFFLL
#define DDRC_CTL_DDR3_094_VAL_CFG1  0x03FFFF00LL
#define DDRC_CTL_DDR3_095_VAL_CFG1  0xFFFF0003LL
#define DDRC_CTL_DDR3_096_VAL_CFG1  0x00000303LL
#define DDRC_CTL_DDR3_097_VAL_CFG1  0x01000400LL
#define DDRC_CTL_DDR3_098_VAL_CFG1  0x00016400LL
#define DDRC_CTL_DDR3_099_VAL_CFG1  0x00000100LL
#define DDRC_CTL_DDR3_100_VAL_CFG1  0x00000001LL
//
#define DDRC_CTL_DDR3_102_VAL_CFG1  0x00000800LL
#define DDRC_CTL_DDR3_103_VAL_CFG1  0x00103300LL
#define DDRC_CTL_DDR3_104_VAL_CFG1  0x02000200LL
#define DDRC_CTL_DDR3_105_VAL_CFG1  0x02000200LL
#define DDRC_CTL_DDR3_106_VAL_CFG1  0x00001033LL
#define DDRC_CTL_DDR3_107_VAL_CFG1  0x000050FFLL
#define DDRC_CTL_DDR3_108_VAL_CFG1  0x0002060CLL
#define DDRC_CTL_DDR3_109_VAL_CFG1  0x00000003LL
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
#define DDRC_CTL_DDR3_126_VAL_CFG1  0x00000000LL

/* DDR3 PHY @400 */
#define DDR3_PHY_CTL_00_VAL_CFG1  0x000F1003LL
#define DDR3_PHY_CTL_01_VAL_CFG1  0x18201010LL
#define DDR3_PHY_CTL_02_VAL_CFG1  0x00000006LL
#define DDR3_PHY_CTL_03_VAL_CFG1  0x00000000LL
#define DDR3_PHY_CTL_04_VAL_CFG1  0x00000000LL
#define DDR3_PHY_CTL_05_VAL_CFG1  0x00000000LL
#define DDR3_PHY_CTL_06_VAL_CFG1  0x04300622LL
#define DDR3_PHY_CTL_07_VAL_CFG1  0x00000000LL


#define DDRC_DDR3_CFG_400 \
{DDRC_CTL_00_REG, DDRC_CTL_DDR3_000_VAL_CFG1},\
{DDRC_CTL_02_REG, DDRC_CTL_DDR3_002_VAL_CFG1},\
{DDRC_CTL_03_REG, DDRC_CTL_DDR3_003_VAL_CFG1},\
{DDRC_CTL_04_REG, DDRC_CTL_DDR3_004_VAL_CFG1},\
{DDRC_CTL_05_REG, DDRC_CTL_DDR3_005_VAL_CFG1},\
{DDRC_CTL_06_REG, DDRC_CTL_DDR3_006_VAL_CFG1},\
{DDRC_CTL_07_REG, DDRC_CTL_DDR3_007_VAL_CFG1},\
{DDRC_CTL_08_REG, DDRC_CTL_DDR3_008_VAL_CFG1},\
{DDRC_CTL_09_REG, DDRC_CTL_DDR3_009_VAL_CFG1},\
{DDRC_CTL_10_REG, DDRC_CTL_DDR3_010_VAL_CFG1},\
{DDRC_CTL_11_REG, DDRC_CTL_DDR3_011_VAL_CFG1},\
{DDRC_CTL_12_REG, DDRC_CTL_DDR3_012_VAL_CFG1},\
{DDRC_CTL_13_REG, DDRC_CTL_DDR3_013_VAL_CFG1},\
{DDRC_CTL_14_REG, DDRC_CTL_DDR3_014_VAL_CFG1},\
{DDRC_CTL_15_REG, DDRC_CTL_DDR3_015_VAL_CFG1},\
{DDRC_CTL_16_REG, DDRC_CTL_DDR3_016_VAL_CFG1},\
{DDRC_CTL_17_REG, DDRC_CTL_DDR3_017_VAL_CFG1},\
{DDRC_CTL_18_REG, DDRC_CTL_DDR3_018_VAL_CFG1},\
{DDRC_CTL_19_REG, DDRC_CTL_DDR3_019_VAL_CFG1},\
{DDRC_CTL_20_REG, DDRC_CTL_DDR3_020_VAL_CFG1},\
{DDRC_CTL_21_REG, DDRC_CTL_DDR3_021_VAL_CFG1},\
{DDRC_CTL_22_REG, DDRC_CTL_DDR3_022_VAL_CFG1},\
{DDRC_CTL_23_REG, DDRC_CTL_DDR3_023_VAL_CFG1},\
{DDRC_CTL_24_REG, DDRC_CTL_DDR3_024_VAL_CFG1},\
{DDRC_CTL_25_REG, DDRC_CTL_DDR3_025_VAL_CFG1},\
{DDRC_CTL_26_REG, DDRC_CTL_DDR3_026_VAL_CFG1},\
{DDRC_CTL_27_REG, DDRC_CTL_DDR3_027_VAL_CFG1},\
{DDRC_CTL_28_REG, DDRC_CTL_DDR3_028_VAL_CFG1},\
{DDRC_CTL_29_REG, DDRC_CTL_DDR3_029_VAL_CFG1},\
{DDRC_CTL_30_REG, DDRC_CTL_DDR3_030_VAL_CFG1},\
{DDRC_CTL_31_REG, DDRC_CTL_DDR3_031_VAL_CFG1},\
{DDRC_CTL_32_REG, DDRC_CTL_DDR3_032_VAL_CFG1},\
{DDRC_CTL_33_REG, DDRC_CTL_DDR3_033_VAL_CFG1},\
{DDRC_CTL_43_REG, DDRC_CTL_DDR3_043_VAL_CFG1},\
{DDRC_CTL_44_REG, DDRC_CTL_DDR3_044_VAL_CFG1},\
{DDRC_CTL_45_REG, DDRC_CTL_DDR3_045_VAL_CFG1},\
{DDRC_CTL_46_REG, DDRC_CTL_DDR3_046_VAL_CFG1},\
{DDRC_CTL_47_REG, DDRC_CTL_DDR3_047_VAL_CFG1},\
{DDRC_CTL_48_REG, DDRC_CTL_DDR3_048_VAL_CFG1},\
{DDRC_CTL_49_REG, DDRC_CTL_DDR3_049_VAL_CFG1},\
{DDRC_CTL_50_REG, DDRC_CTL_DDR3_050_VAL_CFG1},\
{DDRC_CTL_52_REG, DDRC_CTL_DDR3_052_VAL_CFG1},\
{DDRC_CTL_53_REG, DDRC_CTL_DDR3_053_VAL_CFG1},\
{DDRC_CTL_59_REG, DDRC_CTL_DDR3_059_VAL_CFG1},\
{DDRC_CTL_60_REG, DDRC_CTL_DDR3_060_VAL_CFG1},\
{DDRC_CTL_61_REG, DDRC_CTL_DDR3_061_VAL_CFG1},\
{DDRC_CTL_62_REG, DDRC_CTL_DDR3_062_VAL_CFG1},\
{DDRC_CTL_63_REG, DDRC_CTL_DDR3_063_VAL_CFG1},\
{DDRC_CTL_91_REG, DDRC_CTL_DDR3_091_VAL_CFG1},\
{DDRC_CTL_92_REG, DDRC_CTL_DDR3_092_VAL_CFG1},\
{DDRC_CTL_93_REG, DDRC_CTL_DDR3_093_VAL_CFG1},\
{DDRC_CTL_94_REG, DDRC_CTL_DDR3_094_VAL_CFG1},\
{DDRC_CTL_95_REG, DDRC_CTL_DDR3_095_VAL_CFG1},\
{DDRC_CTL_96_REG, DDRC_CTL_DDR3_096_VAL_CFG1},\
{DDRC_CTL_97_REG, DDRC_CTL_DDR3_097_VAL_CFG1},\
{DDRC_CTL_98_REG, DDRC_CTL_DDR3_098_VAL_CFG1},\
{DDRC_CTL_99_REG, DDRC_CTL_DDR3_099_VAL_CFG1},\
{DDRC_CTL_100_REG, DDRC_CTL_DDR3_100_VAL_CFG1},\
{DDRC_CTL_102_REG, DDRC_CTL_DDR3_102_VAL_CFG1},\
{DDRC_CTL_103_REG, DDRC_CTL_DDR3_103_VAL_CFG1},\
{DDRC_CTL_104_REG, DDRC_CTL_DDR3_104_VAL_CFG1},\
{DDRC_CTL_105_REG, DDRC_CTL_DDR3_105_VAL_CFG1},\
{DDRC_CTL_106_REG, DDRC_CTL_DDR3_106_VAL_CFG1},\
{DDRC_CTL_107_REG, DDRC_CTL_DDR3_107_VAL_CFG1},\
{DDRC_CTL_108_REG, DDRC_CTL_DDR3_108_VAL_CFG1},\
{DDRC_CTL_109_REG, DDRC_CTL_DDR3_109_VAL_CFG1},\
{DDRC_CTL_126_REG, DDRC_CTL_DDR3_126_VAL_CFG1}

#define DDR_PHY_CFG_400 \
{DDR_PHY_CTL_00_REG, DDR3_PHY_CTL_00_VAL_CFG1},\
{DDR_PHY_CTL_01_REG, DDR3_PHY_CTL_01_VAL_CFG1},\
{DDR_PHY_CTL_01_REG, DDR3_PHY_CTL_02_VAL_CFG1},\
{DDR_PHY_CTL_03_REG, DDR3_PHY_CTL_03_VAL_CFG1},\
{DDR_PHY_CTL_04_REG, DDR3_PHY_CTL_04_VAL_CFG1},\
{DDR_PHY_CTL_05_REG, DDR3_PHY_CTL_05_VAL_CFG1},\
{DDR_PHY_CTL_06_REG, DDR3_PHY_CTL_06_VAL_CFG1},\
{DDR_PHY_CTL_07_REG, DDR3_PHY_CTL_07_VAL_CFG1}

/*****************************/

/* DDR3 Controller @533MHz */
#define DDRC_CTL_DDR3_000_VAL_CFG2  0x20410600LL
//
#define DDRC_CTL_DDR3_002_VAL_CFG2  0x00000006LL
#define DDRC_CTL_DDR3_003_VAL_CFG2  0x0001A07CLL
#define DDRC_CTL_DDR3_004_VAL_CFG2  0x00041127LL
#define DDRC_CTL_DDR3_005_VAL_CFG2  0x04060E00LL
#define DDRC_CTL_DDR3_006_VAL_CFG2  0x141C0604LL
#define DDRC_CTL_DDR3_007_VAL_CFG2  0x08040804LL
#define DDRC_CTL_DDR3_008_VAL_CFG2  0x0092190CLL
#define DDRC_CTL_DDR3_009_VAL_CFG2  0x00000504LL
#define DDRC_CTL_DDR3_010_VAL_CFG2  0x08080101LL
#define DDRC_CTL_DDR3_011_VAL_CFG2  0x00020010LL
#define DDRC_CTL_DDR3_012_VAL_CFG2  0x00011B03LL
#define DDRC_CTL_DDR3_013_VAL_CFG2  0x00000009LL
#define DDRC_CTL_DDR3_014_VAL_CFG2  0x00560100LL
#define DDRC_CTL_DDR3_015_VAL_CFG2  0x00001034LL
#define DDRC_CTL_DDR3_016_VAL_CFG2  0x000D0004LL
#define DDRC_CTL_DDR3_017_VAL_CFG2  0x00060002LL
#define DDRC_CTL_DDR3_018_VAL_CFG2  0x005B0200LL
#define DDRC_CTL_DDR3_019_VAL_CFG2  0x00000000LL
#define DDRC_CTL_DDR3_020_VAL_CFG2  0x00060600LL
#define DDRC_CTL_DDR3_021_VAL_CFG2  0x00000000LL
#define DDRC_CTL_DDR3_022_VAL_CFG2  0x00000000LL
#define DDRC_CTL_DDR3_023_VAL_CFG2  0x00000000LL
#define DDRC_CTL_DDR3_024_VAL_CFG2  0x00000000LL
#define DDRC_CTL_DDR3_025_VAL_CFG2  0x00000000LL
#define DDRC_CTL_DDR3_026_VAL_CFG2  0x00000000LL
#define DDRC_CTL_DDR3_027_VAL_CFG2  0x00083000LL
#define DDRC_CTL_DDR3_028_VAL_CFG2  0x00080006LL
#define DDRC_CTL_DDR3_029_VAL_CFG2  0x00000000LL
#define DDRC_CTL_DDR3_030_VAL_CFG2  0x00060830LL
#define DDRC_CTL_DDR3_031_VAL_CFG2  0x00000008LL
#define DDRC_CTL_DDR3_032_VAL_CFG2  0x00020000LL
#define DDRC_CTL_DDR3_033_VAL_CFG2  0x00000000LL
//
//
//
//
//
//
//
//
//
#define DDRC_CTL_DDR3_043_VAL_CFG2  0x01400200LL
#define DDRC_CTL_DDR3_044_VAL_CFG2  0x02000040LL
#define DDRC_CTL_DDR3_045_VAL_CFG2  0x01010080LL
#define DDRC_CTL_DDR3_046_VAL_CFG2  0xFF0A0102LL
#define DDRC_CTL_DDR3_047_VAL_CFG2  0x010101FFLL
#define DDRC_CTL_DDR3_048_VAL_CFG2  0x00010001LL
#define DDRC_CTL_DDR3_049_VAL_CFG2  0x000C0100LL
#define DDRC_CTL_DDR3_050_VAL_CFG2  0x00010002LL
//
#define DDRC_CTL_DDR3_052_VAL_CFG2  0x00000000LL
#define DDRC_CTL_DDR3_053_VAL_CFG2  0x007FFFFFLL
//
//
//
//
//
#define DDRC_CTL_DDR3_059_VAL_CFG2  0x01000000LL
#define DDRC_CTL_DDR3_060_VAL_CFG2  0x00020100LL
#define DDRC_CTL_DDR3_061_VAL_CFG2  0x02010202LL
#define DDRC_CTL_DDR3_062_VAL_CFG2  0x02000101LL
#define DDRC_CTL_DDR3_063_VAL_CFG2  0x00000000LL
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
#define DDRC_CTL_DDR3_091_VAL_CFG2  0xFFFF0000LL
#define DDRC_CTL_DDR3_092_VAL_CFG2  0x00000202LL
#define DDRC_CTL_DDR3_093_VAL_CFG2  0x0101FFFFLL
#define DDRC_CTL_DDR3_094_VAL_CFG2  0x03FFFF00LL
#define DDRC_CTL_DDR3_095_VAL_CFG2  0xFFFF0003LL
#define DDRC_CTL_DDR3_096_VAL_CFG2  0x00000303LL
#define DDRC_CTL_DDR3_097_VAL_CFG2  0x01000400LL
#define DDRC_CTL_DDR3_098_VAL_CFG2  0x00016400LL
#define DDRC_CTL_DDR3_099_VAL_CFG2  0x00000100LL
#define DDRC_CTL_DDR3_100_VAL_CFG2  0x00000001LL
//
#define DDRC_CTL_DDR3_102_VAL_CFG2  0x00000800LL
#define DDRC_CTL_DDR3_103_VAL_CFG2  0x00103300LL
#define DDRC_CTL_DDR3_104_VAL_CFG2  0x02000200LL
#define DDRC_CTL_DDR3_105_VAL_CFG2  0x02000200LL
#define DDRC_CTL_DDR3_106_VAL_CFG2  0x00001033LL
#define DDRC_CTL_DDR3_107_VAL_CFG2  0x000050FFLL
#define DDRC_CTL_DDR3_108_VAL_CFG2  0x0002060CLL
#define DDRC_CTL_DDR3_109_VAL_CFG2  0x00000003LL
//
//
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//
#define DDRC_CTL_DDR3_126_VAL_CFG2  0x00000000LL


/* DDR3 PHY @533 */
#define DDR3_PHY_CTL_00_VAL_CFG2  0x000F1023LL
#define DDR3_PHY_CTL_01_VAL_CFG2  0x18201010LL
#define DDR3_PHY_CTL_02_VAL_CFG2  0x00000006LL
#define DDR3_PHY_CTL_03_VAL_CFG2  0x09090909LL
#define DDR3_PHY_CTL_04_VAL_CFG2  0x00000009LL
#define DDR3_PHY_CTL_05_VAL_CFG2  0x00000000LL
#define DDR3_PHY_CTL_06_VAL_CFG2  0x04300623LL
#define DDR3_PHY_CTL_07_VAL_CFG2  0x00000000LL


#define DDRC_DDR3_CFG_533 \
{DDRC_CTL_00_REG, DDRC_CTL_DDR3_000_VAL_CFG2},\
{DDRC_CTL_02_REG, DDRC_CTL_DDR3_002_VAL_CFG2},\
{DDRC_CTL_03_REG, DDRC_CTL_DDR3_003_VAL_CFG2},\
{DDRC_CTL_04_REG, DDRC_CTL_DDR3_004_VAL_CFG2},\
{DDRC_CTL_05_REG, DDRC_CTL_DDR3_005_VAL_CFG2},\
{DDRC_CTL_06_REG, DDRC_CTL_DDR3_006_VAL_CFG2},\
{DDRC_CTL_07_REG, DDRC_CTL_DDR3_007_VAL_CFG2},\
{DDRC_CTL_08_REG, DDRC_CTL_DDR3_008_VAL_CFG2},\
{DDRC_CTL_09_REG, DDRC_CTL_DDR3_009_VAL_CFG2},\
{DDRC_CTL_10_REG, DDRC_CTL_DDR3_010_VAL_CFG2},\
{DDRC_CTL_11_REG, DDRC_CTL_DDR3_011_VAL_CFG2},\
{DDRC_CTL_12_REG, DDRC_CTL_DDR3_012_VAL_CFG2},\
{DDRC_CTL_13_REG, DDRC_CTL_DDR3_013_VAL_CFG2},\
{DDRC_CTL_14_REG, DDRC_CTL_DDR3_014_VAL_CFG2},\
{DDRC_CTL_15_REG, DDRC_CTL_DDR3_015_VAL_CFG2},\
{DDRC_CTL_16_REG, DDRC_CTL_DDR3_016_VAL_CFG2},\
{DDRC_CTL_17_REG, DDRC_CTL_DDR3_017_VAL_CFG2},\
{DDRC_CTL_18_REG, DDRC_CTL_DDR3_018_VAL_CFG2},\
{DDRC_CTL_19_REG, DDRC_CTL_DDR3_019_VAL_CFG2},\
{DDRC_CTL_20_REG, DDRC_CTL_DDR3_020_VAL_CFG2},\
{DDRC_CTL_21_REG, DDRC_CTL_DDR3_021_VAL_CFG2},\
{DDRC_CTL_22_REG, DDRC_CTL_DDR3_022_VAL_CFG2},\
{DDRC_CTL_23_REG, DDRC_CTL_DDR3_023_VAL_CFG2},\
{DDRC_CTL_24_REG, DDRC_CTL_DDR3_024_VAL_CFG2},\
{DDRC_CTL_25_REG, DDRC_CTL_DDR3_025_VAL_CFG2},\
{DDRC_CTL_26_REG, DDRC_CTL_DDR3_026_VAL_CFG2},\
{DDRC_CTL_27_REG, DDRC_CTL_DDR3_027_VAL_CFG2},\
{DDRC_CTL_28_REG, DDRC_CTL_DDR3_028_VAL_CFG2},\
{DDRC_CTL_29_REG, DDRC_CTL_DDR3_029_VAL_CFG2},\
{DDRC_CTL_30_REG, DDRC_CTL_DDR3_030_VAL_CFG2},\
{DDRC_CTL_31_REG, DDRC_CTL_DDR3_031_VAL_CFG2},\
{DDRC_CTL_32_REG, DDRC_CTL_DDR3_032_VAL_CFG2},\
{DDRC_CTL_33_REG, DDRC_CTL_DDR3_033_VAL_CFG2},\
{DDRC_CTL_43_REG, DDRC_CTL_DDR3_043_VAL_CFG2},\
{DDRC_CTL_44_REG, DDRC_CTL_DDR3_044_VAL_CFG2},\
{DDRC_CTL_45_REG, DDRC_CTL_DDR3_045_VAL_CFG2},\
{DDRC_CTL_46_REG, DDRC_CTL_DDR3_046_VAL_CFG2},\
{DDRC_CTL_47_REG, DDRC_CTL_DDR3_047_VAL_CFG2},\
{DDRC_CTL_48_REG, DDRC_CTL_DDR3_048_VAL_CFG2},\
{DDRC_CTL_49_REG, DDRC_CTL_DDR3_049_VAL_CFG2},\
{DDRC_CTL_50_REG, DDRC_CTL_DDR3_050_VAL_CFG2},\
{DDRC_CTL_52_REG, DDRC_CTL_DDR3_052_VAL_CFG2},\
{DDRC_CTL_53_REG, DDRC_CTL_DDR3_053_VAL_CFG2},\
{DDRC_CTL_59_REG, DDRC_CTL_DDR3_059_VAL_CFG2},\
{DDRC_CTL_60_REG, DDRC_CTL_DDR3_060_VAL_CFG2},\
{DDRC_CTL_61_REG, DDRC_CTL_DDR3_061_VAL_CFG2},\
{DDRC_CTL_62_REG, DDRC_CTL_DDR3_062_VAL_CFG2},\
{DDRC_CTL_63_REG, DDRC_CTL_DDR3_063_VAL_CFG2},\
{DDRC_CTL_91_REG, DDRC_CTL_DDR3_091_VAL_CFG2},\
{DDRC_CTL_92_REG, DDRC_CTL_DDR3_092_VAL_CFG2},\
{DDRC_CTL_93_REG, DDRC_CTL_DDR3_093_VAL_CFG2},\
{DDRC_CTL_94_REG, DDRC_CTL_DDR3_094_VAL_CFG2},\
{DDRC_CTL_95_REG, DDRC_CTL_DDR3_095_VAL_CFG2},\
{DDRC_CTL_96_REG, DDRC_CTL_DDR3_096_VAL_CFG2},\
{DDRC_CTL_97_REG, DDRC_CTL_DDR3_097_VAL_CFG2},\
{DDRC_CTL_98_REG, DDRC_CTL_DDR3_098_VAL_CFG2},\
{DDRC_CTL_99_REG, DDRC_CTL_DDR3_099_VAL_CFG2},\
{DDRC_CTL_100_REG, DDRC_CTL_DDR3_100_VAL_CFG2},\
{DDRC_CTL_102_REG, DDRC_CTL_DDR3_102_VAL_CFG2},\
{DDRC_CTL_103_REG, DDRC_CTL_DDR3_103_VAL_CFG2},\
{DDRC_CTL_104_REG, DDRC_CTL_DDR3_104_VAL_CFG2},\
{DDRC_CTL_105_REG, DDRC_CTL_DDR3_105_VAL_CFG2},\
{DDRC_CTL_106_REG, DDRC_CTL_DDR3_106_VAL_CFG2},\
{DDRC_CTL_107_REG, DDRC_CTL_DDR3_107_VAL_CFG2},\
{DDRC_CTL_108_REG, DDRC_CTL_DDR3_108_VAL_CFG2},\
{DDRC_CTL_109_REG, DDRC_CTL_DDR3_109_VAL_CFG2},\
{DDRC_CTL_126_REG, DDRC_CTL_DDR3_126_VAL_CFG2}

#define DDR_PHY_CFG_533 \
{DDR_PHY_CTL_00_REG, DDR3_PHY_CTL_00_VAL_CFG2},\
{DDR_PHY_CTL_01_REG, DDR3_PHY_CTL_01_VAL_CFG2},\
{DDR_PHY_CTL_02_REG, DDR3_PHY_CTL_02_VAL_CFG2},\
{DDR_PHY_CTL_03_REG, DDR3_PHY_CTL_03_VAL_CFG2},\
{DDR_PHY_CTL_04_REG, DDR3_PHY_CTL_04_VAL_CFG2},\
{DDR_PHY_CTL_05_REG, DDR3_PHY_CTL_05_VAL_CFG2},\
{DDR_PHY_CTL_06_REG, DDR3_PHY_CTL_06_VAL_CFG2},\
{DDR_PHY_CTL_07_REG, DDR3_PHY_CTL_07_VAL_CFG2}, \

//#define DDRC_CFG	DDRC_DDR3_CFG_533
//#define DDR_PHY_CFG	DDR_PHY_CFG_533
//For Bringup
#define DDRC_CFG	DDRC_DDR3_CFG_533
#define DDR_PHY_CFG	DDR_PHY_CFG_533

struct ddr_reg_val {
        u32 reg;
        u32 val;
};

#define MC_START	0x1
#define MC_INIT_STAT_MASK	0x200

#define CTRL_RESYNC_EN  (1 << 20)
#define CTRL_RESYNC_PLS (1 << 21)