commit 60c2f14fab77ed869f08f4a146127e2e7129e2cf
author Avery Pennarun <apenwarr@gmail.com> Thu May 30 22:45:37 2013 -0400
committer Avery Pennarun <apenwarr@gmail.com> Fri May 31 22:08:53 2013 -0400
tree 189db65a3a63853a1aa45011c258d23c72f4c6b5
parent bdacf6af8432376b12b01176246054fd1e46c7f0

From Mindspeed SDK v2.1: 000-mspd-uboot_c2k_1_00_1.patch

Change-Id: I524f9238ecf930a68a5ee78022ea21f910ddd6d6

MAKEALL

diff --git a/MAKEALL b/MAKEALL
index 879a17f..3fd6eac 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -213,6 +213,14 @@
 "
 
 #########################################################################
+## Mindspeed Comcerto Systems
+#########################################################################
+LIST_COMCERTO100="	\
+        packet-iad      asic           router          ferouter         \
+        moca                                                            \
+"
+
+#########################################################################
 ## Xscale Systems
 #########################################################################
 
@@ -230,6 +238,7 @@
 	${LIST_SA}							\
 	${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM10} ${LIST_ARM11}		\
 	${LIST_pxa} ${LIST_ixp}						\
+        ${LIST_COMCERTO100}                                             \
 "
 
 #########################################################################
@@ -335,7 +344,7 @@
 do
 	case "$arg" in
 	ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
-	arm|SA|ARM7|ARM9|ARM10|ARM11|pxa|ixp| \
+	arm|SA|ARM7|ARM9|ARM10|ARM11|pxa|ixp|COMCERTO100| \
 	microblaze| \
 	mips|mips_el| \
 	nios|nios2| \

Makefile

diff --git a/Makefile b/Makefile
index a282342..9cf7952 100644
--- a/Makefile
+++ b/Makefile
@@ -125,7 +125,7 @@
 CROSS_COMPILE = powerpc-linux-
 endif
 ifeq ($(ARCH),arm)
-CROSS_COMPILE = arm-linux-
+CROSS_COMPILE = arm-openwrt-linux-
 endif
 ifeq ($(ARCH),i386)
 ifeq ($(HOSTARCH),i386)
@@ -206,6 +206,7 @@
 LIBS += drivers/libdrivers.a
 LIBS += drivers/nand/libnand.a
 LIBS += drivers/nand_legacy/libnand_legacy.a
+LIBS += drivers/c2000_eth/libcomcerto_pfe.a
 LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/cpu/libcpu.a
 LIBS += common/libcommon.a
@@ -215,7 +216,11 @@
 .PHONY : $(LIBS)
 
 # Add GCC lib
-PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+#PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`)
+ifneq ($(ARCH),arm)
+PLATFORM_LIBS += -lgcc
+endif
 
 # The "tools" are needed early, so put this first
 # Don't include stuff already done in $(LIBS)
@@ -230,6 +235,27 @@
 U_BOOT_NAND = $(obj)u-boot-nand.bin
 endif
 
+#For c1k ARAM images no need to do address change
+CHANGE_ADDRESS=y
+ifeq ($(BOARD),c1kevm)
+CHANGE_ADDRESS=n
+endif
+ifeq ($(BOARD),c1kasic)
+CHANGE_ADDRESS=n
+endif
+ifeq ($(BOARD),c2kevm)
+CHANGE_ADDRESS=n
+endif
+ifeq ($(BOARD),c2kasic)
+CHANGE_ADDRESS=n
+endif
+ifeq ($(BOARD),c1kmfcn-evm)
+CHANGE_ADDRESS=n
+endif
+ifeq ($(BOARD),c1km83240)
+CHANGE_ADDRESS=n
+endif
+
 __OBJS := $(subst $(obj),,$(OBJS))
 __LIBS := $(subst $(obj),,$(LIBS))
 
@@ -259,6 +285,15 @@
 $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@
 
+
+
+$(obj)u-boot_aram.elf:	$(obj)u-boot
+ifeq ($(CHANGE_ADDRESS),y)
+		$(OBJCOPY) ${OBJCFLAGS} --change-addresses -0x760ffe00 $< $@
+else
+		cp u-boot u-boot_aram.elf
+endif
+
 $(obj)u-boot:		depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
 		UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed  -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
 		cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
@@ -1775,6 +1810,44 @@
 mp2usb_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t mp2usb NULL at91rm9200
 
+tsavo515_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t tsavo515 mindspeed comcerto
+
+tsavo515_nor_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t tsavo515_nor mindspeed comcerto
+
+tsavo530_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t tsavo530 mindspeed comcerto
+
+tsavo530_nor_config     :       unconfig
+	@./mkconfig $(@:_config=) arm arm920t tsavo530_nor mindspeed comcerto
+
+megamombasa515_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t tsavo515 mindspeed comcerto
+
+megamombasa515_sdc1_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t megamombasa515_sdc1 mindspeed comcerto
+
+megamombasa515_256M_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t megamombasa515_256M mindspeed comcerto
+
+malindi_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t malindi mindspeed comcerto
+
+ipots48-800_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t ipots48-800 mindspeed comcerto
+
+ipots48-515_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t ipots48-515 mindspeed comcerto
+
+udev515_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t udev515 mindspeed comcerto
+
+udev800_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t udev800 mindspeed comcerto
+
+nairobi_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t nairobi mindspeed comcerto
 
 ########################################################################
 ## ARM Integrator boards - see doc/README-integrator for more info.
@@ -2037,6 +2110,419 @@
 omap2420h4_config :    unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
 
+supermombasa910_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 supermombasa910 mindspeed comcerto
+
+matisse_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 supermombasa910 mindspeed comcerto
+
+xtract_eb = $(subst -eb,,$(subst _config,,$1))
+
+packet-iad-eb_config \
+packet-iad_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for packet-iad-eb"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 packet-iad mindspeed comcerto
+	@echo "#define CFG_ARM_CLOCK      450000000     /* 450 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+packet-iad-nand-eb_config \
+packet-iad-nand_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for packet-iad-nand-eb"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 packet-iad mindspeed comcerto
+	@echo "#define CFG_ARM_CLOCK      450000000     /* 450 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+packet-iad-c50_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 packet-iad mindspeed comcerto
+
+asic-eb_config \
+asic_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for asic-eb"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 asic mindspeed comcerto
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+router-eb_config \
+router_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for router-eb"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 router mindspeed comcerto
+	@echo "#define CFG_ARM_CLOCK      450000000     /* 450 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+router-nand-eb_config \
+router-nand_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for router-nand-eb"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 router mindspeed comcerto
+	@echo "#define CFG_ARM_CLOCK      450000000     /* 450 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+router-c50_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 router mindspeed comcerto
+
+ferouter_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 ferouter mindspeed comcerto
+
+moca_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 moca mindspeed comcerto
+
+packet-iad-eb_aram_config \
+packet-iad_aram_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for packet-iad-eb_aram"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 packet-iad mindspeed comcerto
+	@echo "#define CFG_ARM_CLOCK      450000000     /* 450 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+asic-eb_aram_config \
+asic_aram_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for asic-eb_aram"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 asic mindspeed comcerto
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+router-eb_aram_config \
+router_aram_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for router-eb_aram"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 router mindspeed comcerto
+	@echo "#define CFG_ARM_CLOCK      450000000     /* 450 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+ferouter_aram_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 ferouter mindspeed comcerto
+
+moca_aram_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 moca mindspeed comcerto
+
+packet-iad-c50_aram_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 packet-iad mindspeed comcerto
+
+router-c50_aram_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 router mindspeed comcerto
+
+M82134G:
+	sed -i '/CFG_ARM_CLOCK/d' $(TOPDIR)/include/config.h
+	echo "#define CFG_ARM_CLOCK      400000000     /* 400 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	echo "#define M82134G            1" >>$(TOPDIR)/include/config.h
+
+packet-iad-eb-M82134G_config : packet-iad-eb_config M82134G
+packet-iad-M82134G_config : packet-iad_config M82134G
+packet-iad-nand-eb-M82134G_config : packet-iad-nand-eb_config M82134G
+packet-iad-nand-M82134G_config : packet-iad-nand_config M82134G
+packet-iad-eb_aram-M82134G_config : packet-iad-eb_aram_config M82134G
+packet-iad_aram-M82134G_config	:  packet-iad_aram_config M82134G
+router-eb-M82134G_config : router-eb_config M82134G
+router-M82134G_config : router_config M82134G
+router-nand-eb-M82134G_config : router-nand-eb_config M82134G
+router-nand-M82134G_config : router-nand_config M82134G
+router-eb_aram-M82134G_config : router-eb_aram_config M82134G
+router_aram-M82134G_config : router_aram_config M82134G
+
+
+M83263G:
+	echo "#include <configs/m8326XG.h>" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83263G\"" >> $(obj)include/config.h;
+
+M83262G:
+	echo "#include <configs/m8326XG.h>" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83262G\"" >> $(obj)include/config.h;
+
+M83261G:
+	echo "#include <configs/m8326XG.h>" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83261G\"" >> $(obj)include/config.h;
+
+M83160G:
+	echo "#include <configs/m8324XG.h>" >> $(obj)include/config.h;
+	echo "#define CFG_CLK CFG_CLK_600_165_330" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83160G\"" >> $(obj)include/config.h;
+
+M83252G:
+	echo "#include <configs/m8325XG.h>" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83252G\"" >> $(obj)include/config.h;
+
+M83251G:
+	echo "#include <configs/m8325XG.h>" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83251G\"" >> $(obj)include/config.h;
+
+M83242G:
+	echo "#include <configs/m8324XG.h>" >> $(obj)include/config.h;
+	echo "#define CFG_CLK CFG_CLK_450_165_330" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83242G\"" >> $(obj)include/config.h;
+
+M83241G:
+	echo "#include <configs/m8324XG.h>" >> $(obj)include/config.h;
+	echo "#define CFG_CLK CFG_CLK_450_165_330" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83241G\"" >> $(obj)include/config.h;
+
+M83240G:
+	echo "#include <configs/m8324XG.h>" >> $(obj)include/config.h;
+	echo "#define CFG_CLK CFG_CLK_400_165_330" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83240G\"" >> $(obj)include/config.h;
+
+nofpp:
+	echo "#define CONFIG_NOFPP_MODE 1" >> $(obj)include/config.h;
+
+eb:
+	@mkdir -p $(obj)include
+	@echo "#define BE8_MODE 1" >> $(obj)include/config.h ;
+	@echo "... configured for c1kevm-eb";
+	@echo "BE8_MODE = y" >> $(obj)include/config.mk ;
+
+_c1kevm_config:
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1kevm/config.mk;
+	@$(MKCONFIG) -a c1kevm arm arm1136 c1kevm mindspeed comcerto
+
+_c1kevm-nand_config:
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1kevm/config.mk;
+	@$(MKCONFIG) -a c1kevm-nand arm arm1136 c1kevm mindspeed comcerto
+
+_c1kevm_aram_config:
+	@echo "TEXT_BASE = 0x0A006000" >$(obj)board/mindspeed/c1kevm/config.mk;
+	@$(MKCONFIG) -a c1kevm_aram arm arm1136 c1kevm mindspeed comcerto
+
+c1kevm_config: unconfig M83263G _c1kevm_config
+c1kevm-M83263G_config: unconfig M83263G _c1kevm_config
+c1kevm-M83262G_config: unconfig M83262G _c1kevm_config
+c1kevm-M83261G_config: unconfig M83261G _c1kevm_config
+c1kevm-M83160G_config: unconfig M83160G _c1kevm_config
+c1kevm-M83252G_config: unconfig M83252G _c1kevm_config
+c1kevm-M83251G_config: unconfig M83251G _c1kevm_config
+c1kevm-M83242G_config: unconfig M83242G _c1kevm_config
+c1kevm-M83241G_config: unconfig M83241G _c1kevm_config
+c1kevm-M83240G_config: unconfig M83240G _c1kevm_config
+
+c1kevm-nand_config: unconfig M83263G _c1kevm-nand_config
+
+c1kevm_aram_config: unconfig M83263G _c1kevm_aram_config
+c1kevm-M83263G_aram_config: unconfig M83263G _c1kevm_aram_config
+c1kevm-M83262G_aram_config: unconfig M83262G _c1kevm_aram_config
+c1kevm-M83261G_aram_config: unconfig M83261G _c1kevm_aram_config
+c1kevm-M83160G_aram_config: unconfig M83160G _c1kevm_aram_config
+c1kevm-M83252G_aram_config: unconfig M83252G _c1kevm_aram_config
+c1kevm-M83251G_aram_config: unconfig M83251G _c1kevm_aram_config
+c1kevm-M83242G_aram_config: unconfig M83242G _c1kevm_aram_config
+c1kevm-M83241G_aram_config: unconfig M83241G _c1kevm_aram_config
+c1kevm-M83240G_aram_config: unconfig M83240G _c1kevm_aram_config
+
+c1kevm-nofpp_config: unconfig M83263G nofpp _c1kevm_config
+c1kevm-M83263G-nofpp_config: unconfig M83263G nofpp _c1kevm_config
+c1kevm-M83262G-nofpp_config: unconfig M83262G nofpp _c1kevm_config
+c1kevm-M83261G-nofpp_config: unconfig M83261G nofpp _c1kevm_config
+c1kevm-M83160G-nofpp_config: unconfig M83160G nofpp _c1kevm_config
+c1kevm-M83252G-nofpp_config: unconfig M83252G nofpp _c1kevm_config
+c1kevm-M83251G-nofpp_config: unconfig M83251G nofpp _c1kevm_config
+c1kevm-M83242G-nofpp_config: unconfig M83242G nofpp _c1kevm_config
+c1kevm-M83241G-nofpp_config: unconfig M83241G nofpp _c1kevm_config
+c1kevm-M83240G-nofpp_config: unconfig M83240G nofpp _c1kevm_config
+
+c1kevm-nand-nofpp_config: unconfig M83263G nofpp _c1kevm-nand_config
+
+c1kevm-eb_config: unconfig M83263G _c1kevm_config eb
+c1kevm-M83263G-eb_config: unconfig M83263G _c1kevm_config eb
+c1kevm-M83262G-eb_config: unconfig M83262G _c1kevm_config eb
+c1kevm-M83261G-eb_config: unconfig M83261G _c1kevm_config eb
+c1kevm-M83160G-eb_config: unconfig M83160G _c1kevm_config eb
+c1kevm-M83252G-eb_config: unconfig M83252G _c1kevm_config eb
+c1kevm-M83251G-eb_config: unconfig M83251G _c1kevm_config eb
+c1kevm-M83242G-eb_config: unconfig M83242G _c1kevm_config eb
+c1kevm-M83241G-eb_config: unconfig M83241G _c1kevm_config eb
+c1kevm-M83240G-eb_config: unconfig M83240G _c1kevm_config eb
+
+c1kevm-eb_aram_config: unconfig M83263G _c1kevm_aram_config eb
+c1kevm-M83263G-eb_aram_config: unconfig M83263G _c1kevm_aram_config eb
+c1kevm-M83262G-eb_aram_config: unconfig M83262G _c1kevm_aram_config eb
+c1kevm-M83261G-eb_aram_config: unconfig M83261G _c1kevm_aram_config eb
+c1kevm-M83160G-eb_aram_config: unconfig M83160G _c1kevm_aram_config eb
+c1kevm-M83252G-eb_aram_config: unconfig M83252G _c1kevm_aram_config eb
+c1kevm-M83251G-eb_aram_config: unconfig M83251G _c1kevm_aram_config eb
+c1kevm-M83242G-eb_aram_config: unconfig M83242G _c1kevm_aram_config eb
+c1kevm-M83241G-eb_aram_config: unconfig M83241G _c1kevm_aram_config eb
+c1kevm-M83240G-eb_aram_config: unconfig M83240G _c1kevm_aram_config eb
+
+c1kevm-nand-eb_config: unconfig M83263G _c1kevm-nand_config eb
+
+c1kasic_config	:	unconfig
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1kasic/config.mk;
+	@$(MKCONFIG) -a c1kasic arm arm1136 c1kasic mindspeed comcerto
+
+c1kasic-nand_config	:	unconfig
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1kasic/config.mk;
+	@$(MKCONFIG) -a c1kasic arm arm1136 c1kasic mindspeed comcerto
+
+c1kasic_aram_config	:	unconfig
+	@echo "TEXT_BASE = 0x0A006000" >$(obj)board/mindspeed/c1kasic/config.mk;
+	@$(MKCONFIG) -a c1kasic arm arm1136 c1kasic mindspeed comcerto
+
+_c1kmfcn-evm_config:
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1kmfcn-evm/config.mk;
+	@$(MKCONFIG) -a c1kmfcn-evm arm arm1136 c1kmfcn-evm mindspeed comcerto
+
+_c1kmfcn-evm-nand_config:
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1kmfcn-evm/config.mk;
+	@$(MKCONFIG) -a c1kmfcn-evm-nand arm arm1136 c1kmfcn-evm mindspeed comcerto
+
+_c1kmfcn-evm_aram_config:
+	@echo "TEXT_BASE = 0x0A006000" >$(obj)board/mindspeed/c1kmfcn-evm/config.mk;
+	@$(MKCONFIG) -a c1kmfcn-evm_aram arm arm1136 c1kmfcn-evm mindspeed comcerto
+
+c1kmfcn-evm_config: unconfig M83263G _c1kmfcn-evm_config
+c1kmfcn-evm-M83263G_config: unconfig M83263G _c1kmfcn-evm_config
+c1kmfcn-evm-M83262G_config: unconfig M83262G _c1kmfcn-evm_config
+c1kmfcn-evm-M83261G_config: unconfig M83261G _c1kmfcn-evm_config
+c1kmfcn-evm-M83160G_config: unconfig M83160G _c1kmfcn-evm_config
+c1kmfcn-evm-M83252G_config: unconfig M83252G _c1kmfcn-evm_config
+c1kmfcn-evm-M83251G_config: unconfig M83251G _c1kmfcn-evm_config
+c1kmfcn-evm-M83242G_config: unconfig M83242G _c1kmfcn-evm_config
+c1kmfcn-evm-M83241G_config: unconfig M83241G _c1kmfcn-evm_config
+c1kmfcn-evm-M83240G_config: unconfig M83240G _c1kmfcn-evm_config
+
+c1kmfcn-evm-nand_config: unconfig M83263G _c1kmfcn-evm-nand_config
+
+c1kmfcn-evm_aram_config: unconfig M83263G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83263G_aram_config: unconfig M83263G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83262G_aram_config: unconfig M83262G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83261G_aram_config: unconfig M83261G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83160G_aram_config: unconfig M83160G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83252G_aram_config: unconfig M83252G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83251G_aram_config: unconfig M83251G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83242G_aram_config: unconfig M83242G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83241G_aram_config: unconfig M83241G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83240G_aram_config: unconfig M83240G _c1kmfcn-evm_aram_config
+
+c1kmfcn-evm-nofpp_config: unconfig M83263G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83263G-nofpp_config: unconfig M83263G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83262G-nofpp_config: unconfig M83262G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83261G-nofpp_config: unconfig M83261G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83160G-nofpp_config: unconfig M83160G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83252G-nofpp_config: unconfig M83252G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83251G-nofpp_config: unconfig M83251G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83242G-nofpp_config: unconfig M83242G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83241G-nofpp_config: unconfig M83241G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83240G-nofpp_config: unconfig M83240G nofpp _c1kmfcn-evm_config
+
+c1kmfcn-evm-eb_config: unconfig M83263G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83263G-eb_config: unconfig M83263G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83262G-eb_config: unconfig M83262G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83261G-eb_config: unconfig M83261G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83160G-eb_config: unconfig M83160G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83252G-eb_config: unconfig M83252G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83251G-eb_config: unconfig M83251G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83242G-eb_config: unconfig M83242G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83241G-eb_config: unconfig M83241G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83240G-eb_config: unconfig M83240G _c1kmfcn-evm_config eb
+
+c1kmfcn-evm-nand-nofpp_config: unconfig M83263G nofpp _c1kmfcn-evm-nand_config
+
+c1kmfcn-evm-eb_aram_config: unconfig M83263G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83263G-eb_aram_config: unconfig M83263G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83262G-eb_aram_config: unconfig M83262G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83261G-eb_aram_config: unconfig M83261G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83160G-eb_aram_config: unconfig M83160G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83252G-eb_aram_config: unconfig M83252G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83251G-eb_aram_config: unconfig M83251G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83242G-eb_aram_config: unconfig M83242G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83241G-eb_aram_config: unconfig M83241G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83240G-eb_aram_config: unconfig M83240G _c1kmfcn-evm_aram_config eb
+
+_c1km83240_config:
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1km83240/config.mk;
+	@$(MKCONFIG) -a c1km83240 arm arm1136 c1km83240 mindspeed comcerto
+
+_c1km83240-nand_config:
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1km83240/config.mk;
+	@$(MKCONFIG) -a c1km83240-nand arm arm1136 c1km83240 mindspeed comcerto
+
+_c1km83240_aram_config:
+	@echo "TEXT_BASE = 0x0A006000" >$(obj)board/mindspeed/c1km83240/config.mk;
+	@$(MKCONFIG) -a c1km83240_aram arm arm1136 c1km83240 mindspeed comcerto
+
+
+c1km83240_config: unconfig M83240G _c1km83240_config
+c1km83240-M83160G_config: unconfig M83160G _c1km83240_config
+c1km83240-M83240G_config: unconfig M83240G _c1km83240_config
+
+c1km83240-nand_config: unconfig M83240G _c1km83240-nand_config
+
+c1km83240-nofpp_config: unconfig M83240G nofpp _c1km83240_config
+c1km83240-M83240G-nofpp_config: unconfig M83240G nofpp _c1km83240_config
+c1km83240-M83160G-nofpp_config: unconfig M83160G nofpp _c1km83240_config
+
+c1km83240-nand-nofpp_config: unconfig M83240G nofpp _c1km83240-nand_config
+
+c1km83240_aram_config: unconfig M83240G _c1km83240_aram_config
+c1km83240-M83160G_aram_config: unconfig M83160G _c1km83240_aram_config
+c1km83240-M83240G_aram_config: unconfig M83240G _c1km83240_aram_config
+
+
+_c2kevm_config:
+	@echo "TEXT_BASE = 0x1000000" >$(obj)board/mindspeed/c2kevm/config.mk;
+	@$(MKCONFIG) -a c2kevm arm arm_cortexa9 c2kevm mindspeed comcerto
+
+c2kevm_config: unconfig _c2kevm_config
+
+_c2kevm-nand_config:
+	@echo "TEXT_BASE = 0x1000000" >$(obj)board/mindspeed/c2kevm/config.mk;
+	@$(MKCONFIG) -a c2kevm-nand arm arm_cortexa9 c2kevm mindspeed comcerto
+
+c2kevm-nand_config: unconfig _c2kevm-nand_config
+
+_c2kasic_config:
+	@echo "TEXT_BASE = 0x1000000" >$(obj)board/mindspeed/c2kasic/config.mk;
+	@$(MKCONFIG) -a c2kasic arm arm_cortexa9 c2kasic mindspeed comcerto
+
+c2kasic_config: unconfig _c2kasic_config
+
+_c2kasic-nand_config:
+	@echo "TEXT_BASE = 0x1000000" >$(obj)board/mindspeed/c2kasic/config.mk;
+	@$(MKCONFIG) -a c2kasic-nand arm arm_cortexa9 c2kasic mindspeed comcerto
+
+c2kasic-nand_config: unconfig _c2kasic-nand_config
+
+
 #========================================================================
 # i386
 #========================================================================

README

diff --git a/README b/README
index b78ea61..9172e7d 100644
--- a/README
+++ b/README
@@ -1,4 +1,4 @@
-#
+#    
 # (C) Copyright 2000 - 2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #

board/mindspeed/asic/Makefile

diff --git a/board/mindspeed/asic/Makefile b/board/mindspeed/asic/Makefile
new file mode 100644
index 0000000..606ed43
--- /dev/null
+++ b/board/mindspeed/asic/Makefile
@@ -0,0 +1,61 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o
+SOBJS	:= 
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mindspeed/asic/board.c

diff --git a/board/mindspeed/asic/board.c b/board/mindspeed/asic/board.c
new file mode 100644
index 0000000..3566c6b
--- /dev/null
+++ b/board/mindspeed/asic/board.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+static int board_detect(void)
+{
+	u32 gpbt;
+	gpbt = (__le32_to_cpu(*(volatile u32*)(GPIO_BOOTSTRAP_REG)) & 0x1C00) >> 10 ;
+	return(gpbt);
+}
+
+u32 get_ddr_size(void)
+{
+	u32 ddr_size = 0;
+	u32 board_config;
+
+	board_config = board_detect();
+
+	switch (board_config) {
+	case BOARD_CFG_1:
+	case BOARD_CFG_6:
+	default:
+		ddr_size = (256 * 1024 * 1024); /* 256MB */
+		break;
+
+	case BOARD_CFG_2:
+	case BOARD_CFG_3:
+		ddr_size = (1024 * 1024 * 1024); /* 1024MB */
+		break;
+	}
+
+	return ddr_size;
+}
+
+void bsp_init(void)
+{
+	u32 board_config;
+
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	SoC_Check_Device();
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	SoC_PLL_init();
+
+	board_config = board_detect();
+	if ((board_config != BOARD_CFG_1) && (board_config != BOARD_CFG_2) && (board_config != BOARD_CFG_3) && (board_config != BOARD_CFG_6)) {
+
+		while(1);
+	}
+
+	icache_enable();
+	SoC_mem_init(board_config);
+//	SoC_nand_init();
+}
+
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ddr_size();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 wr_dqs = 0; 
+	u8 dqs_out = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	wr_dqs = DENALI_WR_DQS; 
+	dqs_out = DENALI_DQS_OUT;
+	dqs_delay0 = DENALI_DQS_DELAY0;
+	dqs_delay1 = DENALI_DQS_DELAY1;
+	dqs_delay2 = DENALI_DQS_DELAY2;
+	dqs_delay3 = DENALI_DQS_DELAY3;
+
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+
+#ifdef NEW_DDR_TRAINING
+	printf("(NEW): ");
+#endif
+
+#else
+	printf("DDR default settings : ");
+#endif	
+	printf("wr_dqs 0x%x dqs_out 0x%x delay0 0x%x delay1 0x%x delay2 0x%x delay3 0x%x\n", wr_dqs,dqs_out,dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+#endif
+	return 0;
+}
+
+#endif

board/mindspeed/asic/config.mk

diff --git a/board/mindspeed/asic/config.mk b/board/mindspeed/asic/config.mk
new file mode 100644
index 0000000..99d1ed8
--- /dev/null
+++ b/board/mindspeed/asic/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x80100000

board/mindspeed/asic/reset.c

diff --git a/board/mindspeed/asic/reset.c b/board/mindspeed/asic/reset.c
new file mode 100644
index 0000000..6766d64
--- /dev/null
+++ b/board/mindspeed/asic/reset.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+void reset_emac0_phy(u32 enable)
+{
+	//nothing to do. There is no reset on the asic board for the lan interface
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	//nothing to do. There is no reset on the asic board for the wan interface
+}
+

board/mindspeed/asic/u-boot.lds

diff --git a/board/mindspeed/asic/u-boot.lds b/board/mindspeed/asic/u-boot.lds
new file mode 100644
index 0000000..895ea2a
--- /dev/null
+++ b/board/mindspeed/asic/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+
+	. = 0x0a000000;
+	__training_data_start = .;
+
+}

board/mindspeed/c1kasic/Makefile

diff --git a/board/mindspeed/c1kasic/Makefile b/board/mindspeed/c1kasic/Makefile
new file mode 100644
index 0000000..51c4325
--- /dev/null
+++ b/board/mindspeed/c1kasic/Makefile
@@ -0,0 +1,63 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/i2c.o ../common/cmd_bootcomcerto.o
+		
+SOBJS	:=
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mindspeed/c1kasic/board.c

diff --git a/board/mindspeed/c1kasic/board.c b/board/mindspeed/c1kasic/board.c
new file mode 100644
index 0000000..f283968
--- /dev/null
+++ b/board/mindspeed/c1kasic/board.c
@@ -0,0 +1,558 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+
+extern void arm_write64(u64 data,volatile u64 *p);
+
+static void config_board1(void)
+{  
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG1);
+	//*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG1);
+	arm_write64(DENALI_CTL_35_VAL_CFG1,DENALI_CTL_35_DATA); //should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG1);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG1 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board2(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG2);
+	//*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG2;
+	arm_write64(DENALI_CTL_35_VAL_CFG2,DENALI_CTL_35_DATA); //should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG2);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = ((u64)DENALI_CTL_11_VAL_CFG2 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40);
+
+}
+
+static void config_board3(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG3);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG3);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG3);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG3);
+	//*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG3);
+	arm_write64(DENALI_CTL_35_VAL_CFG3,DENALI_CTL_35_DATA); //should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG3);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG3);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG3);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG3);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG3 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG3 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board4(void)
+{
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG4);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG4);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG4);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG4);
+	//*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG4);
+	arm_write64(DENALI_CTL_35_VAL_CFG4,DENALI_CTL_35_DATA); //should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG4);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG4);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG4);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG4);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG4 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG4 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void apply_ddr_setting(void)
+{
+	u32 boot_option = __le32_to_cpu(*(volatile u32*)(GPIO_BOOTSTRAP_STATUS_REG)) & 0xC00;
+
+	switch (boot_option) {
+	case 0x000:
+		// rate case 1 ARM pll 650MHz, AHB pll 800, PHY pll 250  => FCLK=650 AHB=200 DDR=325
+		config_board4();
+		break;
+
+	default:
+	case 0x400:
+		// rate case 1 ARM pll 650MHz, AHB pll 750, PHY pll 250  => FCLK=650 AHB=187.5 DDR=375
+		config_board1();
+
+		break;
+
+	case 0x800:
+		// rate case 2 ARM pll 650MHz, AHB pll 800, PHY pll 250  => FCLK=650 AHB=200 DDR=200
+		config_board2();
+		break;
+
+	case 0xC00:
+		// rate case 3 ARM pll 610MHz, AHB pll 744, PHY pll 250  => FCLK=610 AHB=186 DDR=372
+		config_board3();		
+		break;
+	}
+
+#if defined(DDR_TRAINING)
+	/* Do training */
+	start_training();
+#endif
+}
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+
+static void nor_hw_init(void)
+{
+// Reset the exp bus before configuring
+	*(volatile u32 *)EX_SWRST_REG = __cpu_to_le32(0x1);
+
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0xFFF);
+// AHB runs at 187.5MHz , and EXP at 31.25MHz
+	*(volatile u32 *)EX_CLOCK_DIV_REG = __cpu_to_le32(0x6);
+// Optimized settings for the C1kEVM
+	*(volatile u32 *)EX_CS0_TMG1_REG = __cpu_to_le32(0x1A1A401F); 
+        *(volatile u32 *)EX_CS0_TMG2_REG = __cpu_to_le32(0x06060A04);
+}
+
+void bsp_init(void)
+{
+	u32 boot_option;
+	int config;
+
+	/* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	// read bootstrap
+	boot_option = __le32_to_cpu(*(volatile u32*)(GPIO_BOOTSTRAP_STATUS_REG)) & 0xC00;
+	
+	switch (boot_option) {
+	case 0x000:
+		config = CFG_CLK_650_187_325;
+		break;
+
+	default:
+	case 0x400:
+		config = CFG_CLK;
+		break;
+
+	case 0x800:
+		config = CFG_CLK_650_200_200;
+		break;
+
+	case 0xC00:
+		config = CFG_CLK_610_186_372;
+		break;
+	}
+
+	SoC_PLL_init(config);
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	icache_enable();
+
+	//Apply DENALI DDR configuration
+	apply_ddr_setting();
+
+//	SoC_nand_init();
+}
+
+void nand_hw_init(void)
+{
+        SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(31, GPIO_TYPE_OUTPUT);
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 31)|(1 << 30)|(1 << 29)|(1 << 21)|(1 << 20)|(1 << 5)));
+        *(volatile u32 *) GPIO_PIN_SELECT_REG |= __cpu_to_le32(1 << 6);
+}
+
+void i2c_hw_init(void)
+{
+	*(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 19)|(1 << 18)));
+}
+
+int board_init(void)
+{
+	CFG_HZ_CLOCK = HAL_get_ahb_clk();
+
+	/* Call nor_hw_init() only when low level initialization is not done */
+	/* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  != COMCERTO_PART_MAGIC)
+                nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	nand_hw_init();
+#endif
+	i2c_hw_init();
+
+	/* Setup External reset*/
+	SoC_gpio_cfg(17, GPIO_TYPE_OUTPUT);
+	udelay(10);
+	SoC_gpio_set_0(SoC_gpio_mask(17));
+	udelay(10);
+	SoC_gpio_set_1(SoC_gpio_mask(17));
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+        /* Enable ARM0 hardware support for non aligned accesses */
+        *(volatile u32 *) GPIO_UP_ALIGN_ACCESS_LOGIC |= __cpu_to_le32(1);
+
+	*(volatile u32 *) USB_PHY_CONF_REG = __cpu_to_le32(0x002D64C2);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 dll_adj0 = 0;
+	u8 dll_adj1 = 0;
+	u8 dll_adj2 = 0;
+	u8 dll_adj3 = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	dll_adj0 = DENALI_DLL_ADJ1_DS0_L;
+	dll_adj1 = DENALI_DLL_ADJ1_DS1_H;
+	dll_adj2 = DENALI_DLL_ADJ1_DS2_L;
+	dll_adj3 = DENALI_DLL_ADJ1_DS3_H;
+	dqs_delay0 = DENALI_WR_DQS_DELAY0;
+	dqs_delay1 = DENALI_WR_DQS_DELAY1;
+	dqs_delay2 = DENALI_WR_DQS_DELAY2;
+	dqs_delay3 = DENALI_WR_DQS_DELAY3;
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+#else
+	printf("DDR default settings : ");
+#endif
+	printf("\nDLL_ADJ(0,1,2,3): 0x%x,0x%x,0x%x,0x%x\n", dll_adj0,dll_adj1,dll_adj2,dll_adj3);
+	printf("WR_DQS:delay0 0x%x, delay1 0x%x, delay2 0x%x, delay3 0x%x\n", dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+#endif
+
+	return 0;
+}
+
+#endif

board/mindspeed/c1kasic/config.mk

diff --git a/board/mindspeed/c1kasic/config.mk b/board/mindspeed/c1kasic/config.mk
new file mode 100644
index 0000000..bc4e959
--- /dev/null
+++ b/board/mindspeed/c1kasic/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x84000000

board/mindspeed/c1kasic/reset.c

diff --git a/board/mindspeed/c1kasic/reset.c b/board/mindspeed/c1kasic/reset.c
new file mode 100644
index 0000000..e220846
--- /dev/null
+++ b/board/mindspeed/c1kasic/reset.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+void reset_emac0_phy(u32 enable)
+{
+	//nothing to do. There is no reset on the asic board for the lan interface
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	//nothing to do. There is no reset on the asic board for the wan interface
+}
+

board/mindspeed/c1kasic/u-boot.lds

diff --git a/board/mindspeed/c1kasic/u-boot.lds b/board/mindspeed/c1kasic/u-boot.lds
new file mode 100644
index 0000000..1e8319d
--- /dev/null
+++ b/board/mindspeed/c1kasic/u-boot.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/c1kevm/Makefile

diff --git a/board/mindspeed/c1kevm/Makefile b/board/mindspeed/c1kevm/Makefile
new file mode 100644
index 0000000..51c4325
--- /dev/null
+++ b/board/mindspeed/c1kevm/Makefile
@@ -0,0 +1,63 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/i2c.o ../common/cmd_bootcomcerto.o
+		
+SOBJS	:=
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mindspeed/c1kevm/board.c

diff --git a/board/mindspeed/c1kevm/board.c b/board/mindspeed/c1kevm/board.c
new file mode 100644
index 0000000..14fa0f4
--- /dev/null
+++ b/board/mindspeed/c1kevm/board.c
@@ -0,0 +1,361 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void arm_write64(u64 data,volatile u64 *p);
+
+static void config_board1(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG1);
+	//*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG1);
+	arm_write64(DENALI_CTL_35_VAL_CFG1,DENALI_CTL_35_DATA); //should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG1);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG1 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board2(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG2);
+	//*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG2);
+	arm_write64(DENALI_CTL_35_VAL_CFG2,DENALI_CTL_35_DATA); //should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG2);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG2 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+
+
+void apply_ddr_setting(void)
+{
+	switch (CFG_CLK) {
+	default:
+	case CFG_CLK_650_187_375:
+	case CFG_CLK_534_178_330:
+	case CFG_CLK_450_165_330:
+	        config_board1();
+		break;
+
+	case CFG_CLK_650_200_200:
+		config_board2();
+		break;
+	}
+	
+	/* training is required for 375MHz only,
+         * but nice to have for 200MHz also */
+#if defined(DDR_TRAINING)
+		/* Do training */
+		start_training();
+#endif
+}
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+
+static void nor_hw_init(void)
+{
+/* Reset the exp bus before configuring */
+        *(volatile u32 *)EX_SWRST_REG = __cpu_to_le32(0x1);
+/* Setting size */
+        *(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0x7FF);
+/* AHB runs at 200MHz , and EXP at 40MHz */
+        /* *(volatile u32 *)EX_CLOCK_DIV_REG = __cpu_to_le32(0x5); */
+/* AHB runs at 187.5MHz , and EXP at 31.25MHz */
+        *(volatile u32 *)EX_CLOCK_DIV_REG = __cpu_to_le32(0x6);
+/* Optimized settings */
+        *(volatile u32 *)EX_CS0_TMG1_REG = __cpu_to_le32(0x03034007);
+        *(volatile u32 *)EX_CS0_TMG2_REG = __cpu_to_le32(0x04040502);
+}
+
+void bsp_init(void)
+{
+	/* If MAGIC Number is present, low level initialization is done */
+	if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  == COMCERTO_PART_MAGIC)
+		return;
+
+	SoC_PLL_init(CFG_CLK);
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	icache_enable();
+
+	//Apply DENALI DDR configuration
+	apply_ddr_setting();
+//	SoC_nand_init();
+}
+
+void nand_hw_init(void)
+{
+        SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(31, GPIO_TYPE_OUTPUT);
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 31)|(1 << 30)|(1 << 29)|(1 << 21)|(1 << 20)|(1 << 5)));
+        *(volatile u32 *) GPIO_PIN_SELECT_REG |= __cpu_to_le32(1 << 6);
+}
+
+void i2c_hw_init(void)
+{
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 19)|(1 << 18)));
+}
+
+int board_init(void)
+{
+	CFG_HZ_CLOCK = HAL_get_ahb_clk();
+
+	/* Call nor_hw_init() only when low level initialization is not done */
+	/* If MAGIC Number is present, low level initialization is done */
+	if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  != COMCERTO_PART_MAGIC)
+		nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	nand_hw_init();
+#endif
+	i2c_hw_init();
+
+	/* Setup External reset*/
+	SoC_gpio_cfg(17, GPIO_TYPE_OUTPUT);
+	udelay(10);
+	SoC_gpio_set_0(SoC_gpio_mask(17));
+	udelay(10);
+	SoC_gpio_set_1(SoC_gpio_mask(17));
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	/* Enable ARM0 hardware support for non aligned accesses */
+        *(volatile u32 *) GPIO_UP_ALIGN_ACCESS_LOGIC |= __cpu_to_le32(1);
+
+	*(volatile u32 *) USB_PHY_CONF_REG = __cpu_to_le32(0x002D64C2);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 dll_adj0 = 0;
+	u8 dll_adj1 = 0;
+	u8 dll_adj2 = 0;
+	u8 dll_adj3 = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	dll_adj0 = DENALI_DLL_ADJ1_DS0_L;
+	dll_adj1 = DENALI_DLL_ADJ1_DS1_H;
+	dll_adj2 = DENALI_DLL_ADJ1_DS2_L;
+	dll_adj3 = DENALI_DLL_ADJ1_DS3_H;
+	dqs_delay0 = DENALI_WR_DQS_DELAY0;
+	dqs_delay1 = DENALI_WR_DQS_DELAY1;
+	dqs_delay2 = DENALI_WR_DQS_DELAY2;
+	dqs_delay3 = DENALI_WR_DQS_DELAY3;
+
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+#else
+	printf("DDR default settings : ");
+#endif
+
+	printf("\nDLL_ADJ(0,1,2,3): 0x%x,0x%x,0x%x,0x%x\n", dll_adj0,dll_adj1,dll_adj2,dll_adj3);
+	printf("WR_DQS:delay0 0x%x, delay1 0x%x, delay2 0x%x, delay3 0x%x\n", dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+
+#endif
+	return 0;
+}
+
+#endif

board/mindspeed/c1kevm/config.mk

diff --git a/board/mindspeed/c1kevm/config.mk b/board/mindspeed/c1kevm/config.mk
new file mode 100644
index 0000000..bc4e959
--- /dev/null
+++ b/board/mindspeed/c1kevm/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x84000000

board/mindspeed/c1kevm/reset.c

diff --git a/board/mindspeed/c1kevm/reset.c b/board/mindspeed/c1kevm/reset.c
new file mode 100644
index 0000000..769cb01
--- /dev/null
+++ b/board/mindspeed/c1kevm/reset.c
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+void reset_emac0_phy(u32 enable)
+{
+}
+
+void reset_emac1_phy(u32 enable)
+{
+}
+

board/mindspeed/c1kevm/u-boot.lds

diff --git a/board/mindspeed/c1kevm/u-boot.lds b/board/mindspeed/c1kevm/u-boot.lds
new file mode 100644
index 0000000..1e8319d
--- /dev/null
+++ b/board/mindspeed/c1kevm/u-boot.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/c1km83240/Makefile

diff --git a/board/mindspeed/c1km83240/Makefile b/board/mindspeed/c1km83240/Makefile
new file mode 100644
index 0000000..51c4325
--- /dev/null
+++ b/board/mindspeed/c1km83240/Makefile
@@ -0,0 +1,63 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/i2c.o ../common/cmd_bootcomcerto.o
+		
+SOBJS	:=
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mindspeed/c1km83240/board.c

diff --git a/board/mindspeed/c1km83240/board.c b/board/mindspeed/c1km83240/board.c
new file mode 100644
index 0000000..b249fbd
--- /dev/null
+++ b/board/mindspeed/c1km83240/board.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+extern void arm_write64(u64 data,volatile u64 *p);
+
+static void config_board1(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG1);
+#ifdef CFG_DDR_16BIT
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG1 | (1ULL << 24));
+#else
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG1);
+#endif
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG1);
+	arm_write64(DENALI_CTL_35_VAL_CFG1,DENALI_CTL_35_DATA);//should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG1);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG1 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board2(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG2);
+#ifdef CFG_DDR_16BIT
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG2 | (1ULL << 24));
+#else
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG2);
+#endif
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG2);
+	arm_write64(DENALI_CTL_35_VAL_CFG2,DENALI_CTL_35_DATA);//should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG2);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG2 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+
+
+void apply_ddr_setting(void)
+{		
+	switch (CFG_CLK) {
+	default:
+	case CFG_CLK_650_187_375:
+	case CFG_CLK_534_178_330:
+	case CFG_CLK_450_165_330:
+	        config_board1();
+		break;
+
+	case CFG_CLK_650_200_200:
+		config_board2();
+		break;
+	}
+	
+	/* training is required for 375MHz only,
+         * but nice to have for 200MHz also */
+#if defined(DDR_TRAINING)
+		/* Do training */
+		start_training();
+#endif
+}
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+
+static void nor_hw_init(void)
+{
+// Reset the exp bus before configuring
+	*(volatile u32 *)EX_SWRST_REG = __cpu_to_le32(0x1);
+	while (*(volatile u32 *)EX_SWRST_REG) ;
+// Set size
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0xFFF);
+// Force NOR CS to 16 bits bus size (needed for recovery with u-boot_aram in some cases)
+	*(volatile u32 *)EX_CS0_CFG_REG |= (__cpu_to_le32(CSx_CFG_BUS_SZ_16));
+// AHB runs at 187.5MHz , and EXP at 31.25MHz
+	*(volatile u32 *)EX_CLOCK_DIV_REG = __cpu_to_le32(0x6);
+// Optimized settings
+	*(volatile u32 *)EX_CS0_TMG1_REG = __cpu_to_le32(0x03034007);
+        *(volatile u32 *)EX_CS0_TMG2_REG = __cpu_to_le32(0x04040502);
+}
+
+void bsp_init(void)
+{
+        /* If MAGIC Number is present, low level initialization is done 
+ 	*  in eeprom. Just return*/
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	SoC_PLL_init(CFG_CLK);
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	icache_enable();
+
+	//Apply DENALI DDR configuration
+	apply_ddr_setting();
+//	SoC_nand_init();
+}
+
+void nand_hw_init(void)
+{
+        SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(31, GPIO_TYPE_OUTPUT);
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 31)|(1 << 30)|(1 << 29)|(1 << 21)|(1 << 20)|(1 << 5)));
+        *(volatile u32 *) GPIO_PIN_SELECT_REG |= __cpu_to_le32(1 << 6);
+}
+
+void i2c_hw_init(void)
+{
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 19)|(1 << 18)));
+}
+
+void spi_hw_init(void)
+{
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 27)|(1 << 26)|(1 << 25)|(1 << 24)|(1 << 13)|(1 << 12)));
+}
+
+int board_init(void)
+{
+	CFG_HZ_CLOCK = HAL_get_ahb_clk();
+
+        /* Call nor_hw_init() only when low level initialization is not done */
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  != COMCERTO_PART_MAGIC)
+                nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	nand_hw_init();
+#endif
+	i2c_hw_init();
+
+	spi_hw_init();
+
+	/* Setup External reset*/
+	SoC_gpio_cfg(17, GPIO_TYPE_OUTPUT);
+	udelay(10);
+	SoC_gpio_set_0(SoC_gpio_mask(17));
+	udelay(10);
+	SoC_gpio_set_1(SoC_gpio_mask(17));
+
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+        /* Enable ARM0 hardware support for non aligned accesses */
+        *(volatile u32 *) GPIO_UP_ALIGN_ACCESS_LOGIC |= __cpu_to_le32(1);
+
+	*(volatile u32 *) USB_PHY_CONF_REG = __cpu_to_le32(0x002D64C2);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 dll_adj0 = 0;
+	u8 dll_adj1 = 0;
+	u8 dll_adj2 = 0;
+	u8 dll_adj3 = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	dll_adj0 = DENALI_DLL_ADJ1_DS0_L;
+	dll_adj1 = DENALI_DLL_ADJ1_DS1_H;
+	dll_adj2 = DENALI_DLL_ADJ1_DS2_L;
+	dll_adj3 = DENALI_DLL_ADJ1_DS3_H;
+	dqs_delay0 = DENALI_WR_DQS_DELAY0;
+	dqs_delay1 = DENALI_WR_DQS_DELAY1;
+	dqs_delay2 = DENALI_WR_DQS_DELAY2;
+	dqs_delay3 = DENALI_WR_DQS_DELAY3;
+
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+#else
+	printf("DDR default settings : ");
+#endif
+
+	printf("\nDLL_ADJ(0,1,2,3): 0x%x,0x%x,0x%x,0x%x\n", dll_adj0,dll_adj1,dll_adj2,dll_adj3);
+	printf("WR_DQS:delay0 0x%x, delay1 0x%x, delay2 0x%x, delay3 0x%x\n", dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+
+#endif
+	return 0;
+}
+
+#endif

board/mindspeed/c1km83240/config.mk

diff --git a/board/mindspeed/c1km83240/config.mk b/board/mindspeed/c1km83240/config.mk
new file mode 100644
index 0000000..bc4e959
--- /dev/null
+++ b/board/mindspeed/c1km83240/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x84000000

board/mindspeed/c1km83240/reset.c

diff --git a/board/mindspeed/c1km83240/reset.c b/board/mindspeed/c1km83240/reset.c
new file mode 100644
index 0000000..769cb01
--- /dev/null
+++ b/board/mindspeed/c1km83240/reset.c
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+void reset_emac0_phy(u32 enable)
+{
+}
+
+void reset_emac1_phy(u32 enable)
+{
+}
+

board/mindspeed/c1km83240/u-boot.lds

diff --git a/board/mindspeed/c1km83240/u-boot.lds b/board/mindspeed/c1km83240/u-boot.lds
new file mode 100644
index 0000000..1e8319d
--- /dev/null
+++ b/board/mindspeed/c1km83240/u-boot.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/c1kmfcn-evm/Makefile

diff --git a/board/mindspeed/c1kmfcn-evm/Makefile b/board/mindspeed/c1kmfcn-evm/Makefile
new file mode 100644
index 0000000..51c4325
--- /dev/null
+++ b/board/mindspeed/c1kmfcn-evm/Makefile
@@ -0,0 +1,63 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/i2c.o ../common/cmd_bootcomcerto.o
+		
+SOBJS	:=
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mindspeed/c1kmfcn-evm/board.c

diff --git a/board/mindspeed/c1kmfcn-evm/board.c b/board/mindspeed/c1kmfcn-evm/board.c
new file mode 100644
index 0000000..f291582
--- /dev/null
+++ b/board/mindspeed/c1kmfcn-evm/board.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+extern void arm_write64(u64 data,volatile u64 *p);
+
+static void config_board1(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG1);
+	arm_write64(DENALI_CTL_35_VAL_CFG1,DENALI_CTL_35_DATA);//should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG1);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG1 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board2(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG2);
+	arm_write64(DENALI_CTL_35_VAL_CFG2,DENALI_CTL_35_DATA);//should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG2);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG2 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+
+
+void apply_ddr_setting(void)
+{			
+	switch (CFG_CLK) {
+	default:
+	case CFG_CLK_650_187_375:
+	case CFG_CLK_534_178_330:
+	case CFG_CLK_450_165_330:
+	        config_board1();
+		break;
+
+	case CFG_CLK_650_200_200:
+		config_board2();
+		break;
+	}
+	
+	/* training is required for 375MHz only,
+         * but nice to have for 200MHz also */
+#if defined(DDR_TRAINING)
+		/* Do training */
+		start_training();
+#endif
+}
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+
+static void nor_hw_init(void)
+{
+// Reset the exp bus before configuring
+	*(volatile u32 *)EX_SWRST_REG = __cpu_to_le32(0x1);
+	while (*(volatile u32 *)EX_SWRST_REG) ;
+// Set size
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0xFFF);
+// Force NOR CS to 16 bits bus size (needed for recovery with u-boot_aram in some cases)
+	*(volatile u32 *)EX_CS0_CFG_REG |= (__cpu_to_le32(CSx_CFG_BUS_SZ_16));
+// AHB runs at 187.5MHz , and EXP at 31.25MHz
+	*(volatile u32 *)EX_CLOCK_DIV_REG = __cpu_to_le32(0x6);
+// Optimized settings
+	*(volatile u32 *)EX_CS0_TMG1_REG = __cpu_to_le32(0x03034007);
+        *(volatile u32 *)EX_CS0_TMG2_REG = __cpu_to_le32(0x04040502);
+}
+
+void bsp_init(void)
+{
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	SoC_PLL_init(CFG_CLK);
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	icache_enable();
+
+	//Apply DENALI DDR configuration
+	apply_ddr_setting();
+//	SoC_nand_init();
+}
+
+void nand_hw_init(void)
+{
+        SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(31, GPIO_TYPE_OUTPUT);
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 31)|(1 << 30)|(1 << 29)|(1 << 21)|(1 << 20)|(1 << 5)));
+        *(volatile u32 *) GPIO_PIN_SELECT_REG |= __cpu_to_le32((1 << 6));
+}
+
+void i2c_hw_init(void)
+{
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 19)|(1 << 18)));
+}
+
+void spi_hw_init(void)
+{
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 27)|(1 << 26)|(1 << 25)|(1 << 24)|(1 << 13)|(1 << 12)));
+}
+
+int board_init(void)
+{
+	CFG_HZ_CLOCK = HAL_get_ahb_clk();
+
+        /* Call nor_hw_init() only when low level initialization is not done */
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  != COMCERTO_PART_MAGIC)
+                nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	nand_hw_init();
+#endif
+	i2c_hw_init();
+
+	spi_hw_init();
+
+	/* Setup External reset*/
+	SoC_gpio_cfg(17, GPIO_TYPE_OUTPUT);
+	udelay(10);
+	SoC_gpio_set_0(SoC_gpio_mask(17));
+	udelay(10);
+	SoC_gpio_set_1(SoC_gpio_mask(17));
+
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+        /* Enable ARM0 hardware support for non aligned accesses */
+        *(volatile u32 *) GPIO_UP_ALIGN_ACCESS_LOGIC |= __cpu_to_le32(1);
+
+	*(volatile u32 *) USB_PHY_CONF_REG = __cpu_to_le32(0x002D64C2);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 dll_adj0 = 0;
+	u8 dll_adj1 = 0;
+	u8 dll_adj2 = 0;
+	u8 dll_adj3 = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	dll_adj0 = DENALI_DLL_ADJ1_DS0_L;
+	dll_adj1 = DENALI_DLL_ADJ1_DS1_H;
+	dll_adj2 = DENALI_DLL_ADJ1_DS2_L;
+	dll_adj3 = DENALI_DLL_ADJ1_DS3_H;
+	dqs_delay0 = DENALI_WR_DQS_DELAY0;
+	dqs_delay1 = DENALI_WR_DQS_DELAY1;
+	dqs_delay2 = DENALI_WR_DQS_DELAY2;
+	dqs_delay3 = DENALI_WR_DQS_DELAY3;
+
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+#else
+	printf("DDR default settings : ");
+#endif
+
+	printf("\nDLL_ADJ(0,1,2,3): 0x%x,0x%x,0x%x,0x%x\n", dll_adj0,dll_adj1,dll_adj2,dll_adj3);
+	printf("WR_DQS:delay0 0x%x, delay1 0x%x, delay2 0x%x, delay3 0x%x\n", dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+
+#endif
+	return 0;
+}
+
+#endif

board/mindspeed/c1kmfcn-evm/config.mk

diff --git a/board/mindspeed/c1kmfcn-evm/config.mk b/board/mindspeed/c1kmfcn-evm/config.mk
new file mode 100644
index 0000000..bc4e959
--- /dev/null
+++ b/board/mindspeed/c1kmfcn-evm/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x84000000

board/mindspeed/c1kmfcn-evm/reset.c

diff --git a/board/mindspeed/c1kmfcn-evm/reset.c b/board/mindspeed/c1kmfcn-evm/reset.c
new file mode 100644
index 0000000..769cb01
--- /dev/null
+++ b/board/mindspeed/c1kmfcn-evm/reset.c
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+void reset_emac0_phy(u32 enable)
+{
+}
+
+void reset_emac1_phy(u32 enable)
+{
+}
+

board/mindspeed/c1kmfcn-evm/u-boot.lds

diff --git a/board/mindspeed/c1kmfcn-evm/u-boot.lds b/board/mindspeed/c1kmfcn-evm/u-boot.lds
new file mode 100644
index 0000000..1e8319d
--- /dev/null
+++ b/board/mindspeed/c1kmfcn-evm/u-boot.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/c2kasic/Makefile

diff --git a/board/mindspeed/c2kasic/Makefile b/board/mindspeed/c2kasic/Makefile
new file mode 100644
index 0000000..3b38d14
--- /dev/null
+++ b/board/mindspeed/c2kasic/Makefile
@@ -0,0 +1,62 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o pad_config.o ../common/flash.o i2c.o nand.o
+
+SOBJS	:=
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mindspeed/c2kasic/board.c

diff --git a/board/mindspeed/c2kasic/board.c b/board/mindspeed/c2kasic/board.c
new file mode 100644
index 0000000..968442e
--- /dev/null
+++ b/board/mindspeed/c2kasic/board.c
@@ -0,0 +1,91 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio_c2000.h>
+#include <asm/arch/exp-bus_c2000.h>
+#include <asm/arch/clkcore_c2000.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define EXP_CS0_SEG_SIZE_VAL  0x7FFF
+
+#define A9_TIMER_LOAD           0x0
+#define A9_TIMER_COUNTER 0x4
+#define A9_TIMER_CNTRL          0x8
+#define A9_TIMER_ENABLE         (1<<0)
+#define A9_TIMER_RELOAD         (1<<1)
+
+#define MAX_TIMER_COUNT 0xffffffff
+
+void comcerto_pad_config();
+
+void nor_hw_init(void)
+{
+	*(volatile u32*) EXP_CS0_SEG_REG = EXP_CS0_SEG_SIZE_VAL;
+	*(volatile u32*) EXP_CS0_TMG1_REG = 0x03034007;
+	*(volatile u32*) EXP_CS0_TMG2_REG = 0x04040502;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+void nand_hw_init(void)
+{
+        SoC_gpio_cfg(28, GPIO_TYPE_OUTPUT); /* NAND CE */
+        SoC_gpio_cfg(29, GPIO_TYPE_INPUT);  /* NAND BR */
+}
+#endif
+
+
+#if 0
+void a9_timer_init(void)
+{
+	*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_LOAD) = MAX_TIMER_COUNT;
+	*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_COUNTER) = MAX_TIMER_COUNT;
+	*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_CNTRL) = A9_TIMER_ENABLE | A9_TIMER_RELOAD;
+}
+#endif
+
+void bsp_init(void)
+{
+	int val;
+
+	comcerto_pad_config();
+
+	//DDRC ODT Source Select
+	*(volatile u32*) COMCERTO_GPIO_MISC_PIN_SELECT_REG = ( (1 << 6) | (*(volatile u32*) COMCERTO_GPIO_MISC_PIN_SELECT_REG));
+
+	nor_hw_init();
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	SoC_nand_init();
+#endif
+#if 0
+	a9_timer_init();
+#endif
+}
+
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+
+int board_init(void)
+{
+        /* arch number of Mindspeed Comcerto */
+        gd->bd->bi_arch_number = MACH_TYPE_COMCERTO;
+
+        /* adress of boot parameters */
+        gd->bd->bi_boot_params = 0x100;
+
+
+        gd->bd->bi_dram[0].start = 0x0;
+        gd->bd->bi_dram[0].size = 0x20000000; //512 MB
+
+#if 0
+	c2k_zds_init();
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	nand_hw_init();
+#endif
+
+        return 0;
+}
+

board/mindspeed/c2kasic/config.mk

diff --git a/board/mindspeed/c2kasic/config.mk b/board/mindspeed/c2kasic/config.mk
new file mode 100644
index 0000000..99443b1
--- /dev/null
+++ b/board/mindspeed/c2kasic/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x1000000

board/mindspeed/c2kasic/i2c.c

diff --git a/board/mindspeed/c2kasic/i2c.c b/board/mindspeed/c2kasic/i2c.c
new file mode 100644
index 0000000..db029cb
--- /dev/null
+++ b/board/mindspeed/c2kasic/i2c.c
@@ -0,0 +1,562 @@
+/*
+ * (C) Copyright 2007
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+#define COMCERTO_AXI_APB_CFG_BASE       0x90400000
+#define	I2C_BASEADDR	(COMCERTO_AXI_APB_CFG_BASE + 0x09C000)
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#define MAX_I2C_RETRYS	    10
+#define I2C_DELAY	    1000	/* Should be at least the # of MHz of Tclk */
+
+#define I2C_ADDR                        (I2C_BASEADDR + 0x00)
+#define I2C_DATA                        (I2C_BASEADDR + 0x04)
+#define I2C_CNTR                        (I2C_BASEADDR + 0x08)
+#define I2C_STAT                        (I2C_BASEADDR + 0x0c)
+#define I2C_CCRFS                       (I2C_BASEADDR + 0x0c)
+#define I2C_XADDR                       (I2C_BASEADDR + 0x10)
+#define I2C_CCRH                        (I2C_BASEADDR + 0x14)
+#define I2C_SOFT_RESET                  (I2C_BASEADDR + 0x1c)
+
+/* CNTR - Control register bits */
+#define I2C_IEN				(1<<7)
+#define I2C_ENAB			(1<<6)
+#define I2C_STA				(1<<5)
+#define I2C_STP				(1<<4)
+#define I2C_IFLG			(1<<3)
+#define I2C_AAK				(1<<2)
+
+/* STAT - Status codes */
+#define I2C_BUS_ERROR			0x00	/* Bus error in master mode only */
+#define I2C_START_TRANSMIT		0x08	/* Start condition transmitted */
+#define I2C_REPEAT_START_TRANSMIT	0x10	/* Repeated Start condition transmited */
+#define I2C_ADDRESS_W_ACK		0x18	/* Address + Write bit transmitted, ACK received */
+#define I2C_ADDRESS_W_NACK		0x20	/* Address + Write bit transmitted, NACK received */
+#define I2C_DATA_TRANSMIT_ACK		0x28	/* Data byte transmitted in master mode , ACK received */
+#define I2C_DATA_TRANSMIT_NACK		0x30	/* Data byte transmitted in master mode , NACK received */
+#define I2C_ARBIT_LOST			0x38	/* Arbitration lost in address or data byte */
+#define I2C_ADDRESS_R_ACK		0x40	/* Address + Read bit transmitted, ACK received  */
+#define I2C_ADDRESS_R_NACK		0x48	/* Address + Read bit transmitted, NACK received  */
+#define I2C_DATA_RECEIVE_ACK		0x50	/* Data byte received in master mode, ACK transmitted  */
+#define I2C_DATA_RECEIVE_NACK		0x58	/* Data byte received in master mode, NACK transmitted*/
+#define I2C_ARBIT_LOST_ADDRESS		0x68	/* Arbitration lost in address  */
+#define I2C_GENERAL_CALL		0x70	/* General Call, ACK transmitted */
+#define I2C_NO_RELEVANT_INFO		0xF8	/* No relevant status information, IFLF=0 */
+
+#define I2C_READ_REG(reg)	        *(volatile u32*)(reg)
+#define I2C_WRITE_REG(reg, val)	        *(volatile u32*)(reg) = val
+#define RESET_REG_BITS(reg, val)        I2C_WRITE_REG(reg, I2C_READ_REG(reg) & ~(val))
+
+#undef	DEBUG_I2C
+//#define DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int control, status;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CFG_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 1 << n;	/* power = 2^(n) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+        I2C_WRITE_REG(I2C_SOFT_RESET, 0);
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	DP (puts ("set baudrate\n"));
+
+	I2C_WRITE_REG(I2C_STAT, (actualM << 3) | actualN);
+	I2C_WRITE_REG(I2C_CNTR, I2C_AAK | I2C_ENAB);
+
+	udelay (I2C_DELAY * 10);
+
+	DP (puts ("read control, baudrate\n"));
+
+	status = I2C_READ_REG(I2C_STAT);
+	control = I2C_READ_REG(I2C_CNTR);
+}
+
+static uchar i2c_start (void)
+{
+	unsigned int control, status;
+	int count = 0;
+
+	DP (puts ("i2c_start\n"));
+
+	/* Set the start bit */
+
+	control = I2C_READ_REG(I2C_CNTR);
+	control |= I2C_STA;	/* generate the I2C_START_BIT */
+	I2C_WRITE_REG(I2C_CNTR, control);
+
+	status = I2C_READ_REG(I2C_STAT);
+
+	count = 0;
+	while ((status & 0xff) != I2C_START_TRANSMIT) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+
+	return (0);
+}
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	I2C_WRITE_REG(I2C_DATA, data);
+	/* assert the address */
+	RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+	udelay (I2C_DELAY);
+
+	status = I2C_READ_REG(I2C_STAT);
+	count = 0;
+	while (((status & 0xff) != I2C_ADDRESS_R_ACK) && ((status & 0xff) != I2C_ADDRESS_W_ACK)) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status = 0;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		/* Get and return the data */
+
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY * 5);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_RECEIVE_ACK) {
+			udelay (I2C_DELAY);
+			if (count > 2) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return 0;
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		data = I2C_READ_REG(I2C_DATA);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+	}
+	RESET_REG_BITS (I2C_CNTR, I2C_AAK | I2C_IFLG);
+	while ((status & 0xff) != I2C_DATA_RECEIVE_NACK) {
+		udelay (I2C_DELAY);
+		if (count > 200) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+	I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/* stop */
+
+	return (0);
+}
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		temp = (unsigned int) (*temp_ptr);
+		I2C_WRITE_REG(I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_TRANSMIT_ACK) {
+			udelay (I2C_DELAY);
+			if (count > 20) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return (status);
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+	/* set the interrupt bit in the control register */
+	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG);
+	udelay (I2C_DELAY * 10);
+	return (0);
+}
+
+/* created this function to get the i2c_write() */
+/* function working properly. */
+/* function to write bytes out on the i2c bus */
+/* this is identical to the function i2c_write_data() */
+/* except that it requires a buffer that is an */
+/* unsigned character array.  You can't use */
+/* i2c_write_data() to send an array of unsigned characters */
+/* since the byte of interest ends up on the wrong end of the bus */
+/* aah, the joys of big endian versus little endian! */
+/* */
+/* returns 0 = success */
+/*         anything other than zero is failure */
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		I2C_WRITE_REG(I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY*2);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_TRANSMIT_ACK) {
+			udelay (I2C_DELAY*2);
+			if (count > 20) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return (status);
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+/*	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG | I2C_STP);
+	I2C_WRITE_REG(I2C_CNTR, I2C_STP); */
+	/* set the interrupt bit in the control register */
+	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG);
+	udelay (I2C_DELAY * 10);
+
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+/* initialize the table of address offset bytes */
+/* utilized for 2 byte address offsets */
+/* NOTE: the order is high byte first! */
+	table[1] = offset & 0xff;	/* low byte */
+	table[0] = offset / 0x100;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+uchar
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency again */
+
+	status = i2c_start ();
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction restart failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);	/* send the slave address */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Address not acknowledged: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not recieved: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+/* Function to set the I2C stop bit */
+void i2c_stop (void)
+{
+	I2C_WRITE_REG(I2C_CNTR, (0x1 << 4));
+}
+
+/* I2C write function */
+/* dev_addr = device address */
+/* offset = address offset */
+/* alen = length in bytes of the address offset */
+/* data = pointer to buffer to read data into */
+/* len = # of bytes to read */
+/* */
+/* returns 0 = succesful */
+/*         anything but zero is failure */
+uchar
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+	}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+/* function to determine if an I2C device is present */
+/* chip = device address of chip to check for */
+/* */
+/* returns 0 = sucessful, the device exists */
+/*         anything other than zero is failure, no device */
+int i2c_probe (uchar chip)
+{
+
+	/* We are just looking for an <ACK> back. */
+	/* To see if the device/chip is there */
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	i2c_status = I2C_READ_REG(I2C_STAT);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */

board/mindspeed/c2kasic/nand.c

diff --git a/board/mindspeed/c2kasic/nand.c b/board/mindspeed/c2kasic/nand.c
new file mode 100644
index 0000000..fbc6bc4
--- /dev/null
+++ b/board/mindspeed/c2kasic/nand.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <config.h>
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+#include <asm-arm/arch-comcerto/exp-bus_c2000.h>
+#include <asm-arm/io.h>
+
+
+/** Hardware specific access to NAND control-lines
+ **
+ ** @param[in] mtd       MTD device structure
+ ** @param[in] cmd       NAND command to the controller
+ ** @param[in] ctrl      control address/command latch
+ **
+ **/
+static void comcerto_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+                                                unsigned int ctrl)
+{
+        struct nand_chip *chip = mtd->priv;
+
+        if (ctrl & NAND_CTRL_CHANGE) {
+                if (ctrl & NAND_NCE)
+			SoC_gpio_set_0(SoC_gpio_mask(CFG_NAND_CE_GPIO));
+                else
+			SoC_gpio_set_1(SoC_gpio_mask(CFG_NAND_CE_GPIO));
+        }
+
+        if (cmd == NAND_CMD_NONE) {
+	 return;
+        }
+
+	if (ctrl & NAND_CLE)
+		writeb(cmd, chip->IO_ADDR_W + COMCERTO_NAND_CLE);
+        else if (ctrl & NAND_ALE)
+                writeb(cmd,  chip->IO_ADDR_W + COMCERTO_NAND_ALE);
+        else
+		return;
+}
+
+
+int comcerto_nand_ready(struct mtd_info *mtd)
+{
+	return SoC_gpio_read(SoC_gpio_mask(CFG_NAND_BR_GPIO)) ? 1 : 0;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	printf("board_nand_init nand->IO_ADDR_R =%x\n", nand->IO_ADDR_R);
+
+	nand->options = 0;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = comcerto_nand_hwcontrol;
+	nand->dev_ready = comcerto_nand_ready;
+	nand->chip_delay = 20;
+}
+#else
+int board_nand_init(struct nand_chip *nand)
+{
+}
+#endif

board/mindspeed/c2kasic/pad_config.c

diff --git a/board/mindspeed/c2kasic/pad_config.c b/board/mindspeed/c2kasic/pad_config.c
new file mode 100644
index 0000000..16d9104
--- /dev/null
+++ b/board/mindspeed/c2kasic/pad_config.c
@@ -0,0 +1,81 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clkcore_c2000.h>
+#include <asm/arch/ddr_c2000.h>
+#include <asm/arch/gpio_c2000.h>
+
+#define CONFIG_GEM_RGMII_2_5V
+//#define CONFIG_GEM_RGMII_3_3V
+#define CONFIG_HFE_OVERDRIVE
+
+/* Initialize pad config according to C2K_ChipDef_spec_010.doc */
+void comcerto_pad_config()
+{
+	u32 val;
+
+	/* HFE configurations */
+
+	/* Memories EMA Config 1 */
+	val = *(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1);
+	val &= ~((0x3 << 6)|(0x3 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1) = val;
+
+#if defined(CONFIG_GEM_RGMII_3_3V)
+	/*  Driving Strength of IO Pads */
+	/*In case GEMX operates in RMII or RGMII @3.3V mode then need to adjust
+	 *the driving strength of its IO pad (default value is for 2.5V) */
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3);
+	val &= ~((0x3 << 6) | (0x3 << 12));
+	val |= ((0x2 << 6) | (0x2 << 12));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4);
+	val &= ~((0x3 << 6)| (0x3 << 12));
+	val |= ((0x2 << 6) | (0x2 << 12));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5);
+	val &= ~((0x3 << 6) | (0x3 << 12));
+	val |= ((0x2 << 6) | (0x2 << 12));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5) = val;
+
+#elif defined(CONFIG_GEM_RGMII_2_5V)
+	/* RGMII Pad Compensation Logic (Tx side only)*/
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CTRL);
+	val &= ~((0x3 << 22) | (0x3 << 26) | (0x3 << 30));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CTRL) = val;
+#else
+#error "Either CONFIG_GEM_RGMII_3_3V or CONFIG_GEM_RGMII_2_5V should be selected"
+#endif
+	/* Slew Rate Control of IO Pads */
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3);
+	val |= ((0x1 << 11) | (0x1 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4);
+	val |= ((0x1 << 11) | (0x1 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5);
+	val |= ((0x1 << 11) | (0x1 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5) = val;
+
+#if defined (CONFIG_HFE_OVERDRIVE)
+	/* Memory Margin Bit setting */
+	/* In case HFE block operates in overdrive (1.2V) mode then need to
+	* modify few EMA fields related to HFE memories. The configuration
+	* registers are in GPIO block */
+	val = *(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG0);
+	val &= ~(0xFFF << 18);
+	val |= (0x38E << 18);
+	*(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG0) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1);
+	val &= ~(0x3F << 19);
+	val |= (0x8 << 18);
+	*(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1) = val;
+#endif
+
+	/*TODO Add rest of the configurations here*/
+
+}

board/mindspeed/c2kasic/reset.c

diff --git a/board/mindspeed/c2kasic/reset.c b/board/mindspeed/c2kasic/reset.c
new file mode 100644
index 0000000..fdd065f
--- /dev/null
+++ b/board/mindspeed/c2kasic/reset.c
@@ -0,0 +1,10 @@
+#include <common.h>
+
+/*
+ *  * Reset the cpu through the reset controller
+ *   */
+void __noreturn reset_cpu (unsigned long addr)
+{
+        while (1);
+}
+

board/mindspeed/c2kasic/u-boot.lds

diff --git a/board/mindspeed/c2kasic/u-boot.lds b/board/mindspeed/c2kasic/u-boot.lds
new file mode 100644
index 0000000..83b87a0
--- /dev/null
+++ b/board/mindspeed/c2kasic/u-boot.lds
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm_cortexa9/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
+

board/mindspeed/c2kevm/Makefile

diff --git a/board/mindspeed/c2kevm/Makefile b/board/mindspeed/c2kevm/Makefile
new file mode 100644
index 0000000..3b38d14
--- /dev/null
+++ b/board/mindspeed/c2kevm/Makefile
@@ -0,0 +1,62 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o pad_config.o ../common/flash.o i2c.o nand.o
+
+SOBJS	:=
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mindspeed/c2kevm/board.c

diff --git a/board/mindspeed/c2kevm/board.c b/board/mindspeed/c2kevm/board.c
new file mode 100644
index 0000000..fa16b54
--- /dev/null
+++ b/board/mindspeed/c2kevm/board.c
@@ -0,0 +1,90 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio_c2000.h>
+#include <asm/arch/exp-bus_c2000.h>
+#include <asm/arch/clkcore_c2000.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define EXP_CS0_SEG_SIZE_VAL  0x7FFF
+
+#define A9_TIMER_LOAD           0x0
+#define A9_TIMER_COUNTER 0x4
+#define A9_TIMER_CNTRL          0x8
+#define A9_TIMER_ENABLE         (1<<0)
+#define A9_TIMER_RELOAD         (1<<1)
+
+#define MAX_TIMER_COUNT 0xffffffff
+
+void comcerto_pad_config();
+
+void nor_hw_init(void)
+{
+	*(volatile u32*) EXP_CS0_SEG_REG = EXP_CS0_SEG_SIZE_VAL;
+	*(volatile u32*) EXP_CS0_TMG1_REG = 0x03034007;
+	*(volatile u32*) EXP_CS0_TMG2_REG = 0x04040502;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+void nand_hw_init(void)
+{
+        SoC_gpio_cfg(28, GPIO_TYPE_OUTPUT); /* NAND CE */
+        SoC_gpio_cfg(29, GPIO_TYPE_INPUT);  /* NAND BR */
+}
+#endif
+
+#if 0
+void a9_timer_init(void)
+{
+	*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_LOAD) = MAX_TIMER_COUNT;
+	*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_COUNTER) = MAX_TIMER_COUNT;
+	*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_CNTRL) = A9_TIMER_ENABLE | A9_TIMER_RELOAD;
+}
+#endif
+
+void bsp_init(void)
+{
+	int val;
+
+	comcerto_pad_config();
+
+	//DDRC ODT Source Select
+	*(volatile u32*) COMCERTO_GPIO_MISC_PIN_SELECT_REG = ( (1 << 6) | (*(volatile u32*) COMCERTO_GPIO_MISC_PIN_SELECT_REG));
+
+	nor_hw_init();
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	SoC_nand_init();
+#endif
+#if 0
+	a9_timer_init();
+#endif
+}
+
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+
+int board_init(void)
+{
+        /* arch number of Mindspeed Comcerto */
+        gd->bd->bi_arch_number = MACH_TYPE_COMCERTO;
+
+        /* adress of boot parameters */
+        gd->bd->bi_boot_params = 0x100;
+
+
+        gd->bd->bi_dram[0].start = 0x0;
+        gd->bd->bi_dram[0].size = 0x20000000; //512 MB
+
+#if 0
+        c2k_zds_init();
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	nand_hw_init();
+#endif
+
+        return 0;
+}
+

board/mindspeed/c2kevm/config.mk

diff --git a/board/mindspeed/c2kevm/config.mk b/board/mindspeed/c2kevm/config.mk
new file mode 100644
index 0000000..99443b1
--- /dev/null
+++ b/board/mindspeed/c2kevm/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x1000000

board/mindspeed/c2kevm/i2c.c

diff --git a/board/mindspeed/c2kevm/i2c.c b/board/mindspeed/c2kevm/i2c.c
new file mode 100644
index 0000000..db029cb
--- /dev/null
+++ b/board/mindspeed/c2kevm/i2c.c
@@ -0,0 +1,562 @@
+/*
+ * (C) Copyright 2007
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+#define COMCERTO_AXI_APB_CFG_BASE       0x90400000
+#define	I2C_BASEADDR	(COMCERTO_AXI_APB_CFG_BASE + 0x09C000)
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#define MAX_I2C_RETRYS	    10
+#define I2C_DELAY	    1000	/* Should be at least the # of MHz of Tclk */
+
+#define I2C_ADDR                        (I2C_BASEADDR + 0x00)
+#define I2C_DATA                        (I2C_BASEADDR + 0x04)
+#define I2C_CNTR                        (I2C_BASEADDR + 0x08)
+#define I2C_STAT                        (I2C_BASEADDR + 0x0c)
+#define I2C_CCRFS                       (I2C_BASEADDR + 0x0c)
+#define I2C_XADDR                       (I2C_BASEADDR + 0x10)
+#define I2C_CCRH                        (I2C_BASEADDR + 0x14)
+#define I2C_SOFT_RESET                  (I2C_BASEADDR + 0x1c)
+
+/* CNTR - Control register bits */
+#define I2C_IEN				(1<<7)
+#define I2C_ENAB			(1<<6)
+#define I2C_STA				(1<<5)
+#define I2C_STP				(1<<4)
+#define I2C_IFLG			(1<<3)
+#define I2C_AAK				(1<<2)
+
+/* STAT - Status codes */
+#define I2C_BUS_ERROR			0x00	/* Bus error in master mode only */
+#define I2C_START_TRANSMIT		0x08	/* Start condition transmitted */
+#define I2C_REPEAT_START_TRANSMIT	0x10	/* Repeated Start condition transmited */
+#define I2C_ADDRESS_W_ACK		0x18	/* Address + Write bit transmitted, ACK received */
+#define I2C_ADDRESS_W_NACK		0x20	/* Address + Write bit transmitted, NACK received */
+#define I2C_DATA_TRANSMIT_ACK		0x28	/* Data byte transmitted in master mode , ACK received */
+#define I2C_DATA_TRANSMIT_NACK		0x30	/* Data byte transmitted in master mode , NACK received */
+#define I2C_ARBIT_LOST			0x38	/* Arbitration lost in address or data byte */
+#define I2C_ADDRESS_R_ACK		0x40	/* Address + Read bit transmitted, ACK received  */
+#define I2C_ADDRESS_R_NACK		0x48	/* Address + Read bit transmitted, NACK received  */
+#define I2C_DATA_RECEIVE_ACK		0x50	/* Data byte received in master mode, ACK transmitted  */
+#define I2C_DATA_RECEIVE_NACK		0x58	/* Data byte received in master mode, NACK transmitted*/
+#define I2C_ARBIT_LOST_ADDRESS		0x68	/* Arbitration lost in address  */
+#define I2C_GENERAL_CALL		0x70	/* General Call, ACK transmitted */
+#define I2C_NO_RELEVANT_INFO		0xF8	/* No relevant status information, IFLF=0 */
+
+#define I2C_READ_REG(reg)	        *(volatile u32*)(reg)
+#define I2C_WRITE_REG(reg, val)	        *(volatile u32*)(reg) = val
+#define RESET_REG_BITS(reg, val)        I2C_WRITE_REG(reg, I2C_READ_REG(reg) & ~(val))
+
+#undef	DEBUG_I2C
+//#define DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int control, status;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CFG_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 1 << n;	/* power = 2^(n) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+        I2C_WRITE_REG(I2C_SOFT_RESET, 0);
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	DP (puts ("set baudrate\n"));
+
+	I2C_WRITE_REG(I2C_STAT, (actualM << 3) | actualN);
+	I2C_WRITE_REG(I2C_CNTR, I2C_AAK | I2C_ENAB);
+
+	udelay (I2C_DELAY * 10);
+
+	DP (puts ("read control, baudrate\n"));
+
+	status = I2C_READ_REG(I2C_STAT);
+	control = I2C_READ_REG(I2C_CNTR);
+}
+
+static uchar i2c_start (void)
+{
+	unsigned int control, status;
+	int count = 0;
+
+	DP (puts ("i2c_start\n"));
+
+	/* Set the start bit */
+
+	control = I2C_READ_REG(I2C_CNTR);
+	control |= I2C_STA;	/* generate the I2C_START_BIT */
+	I2C_WRITE_REG(I2C_CNTR, control);
+
+	status = I2C_READ_REG(I2C_STAT);
+
+	count = 0;
+	while ((status & 0xff) != I2C_START_TRANSMIT) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+
+	return (0);
+}
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	I2C_WRITE_REG(I2C_DATA, data);
+	/* assert the address */
+	RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+	udelay (I2C_DELAY);
+
+	status = I2C_READ_REG(I2C_STAT);
+	count = 0;
+	while (((status & 0xff) != I2C_ADDRESS_R_ACK) && ((status & 0xff) != I2C_ADDRESS_W_ACK)) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status = 0;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		/* Get and return the data */
+
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY * 5);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_RECEIVE_ACK) {
+			udelay (I2C_DELAY);
+			if (count > 2) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return 0;
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		data = I2C_READ_REG(I2C_DATA);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+	}
+	RESET_REG_BITS (I2C_CNTR, I2C_AAK | I2C_IFLG);
+	while ((status & 0xff) != I2C_DATA_RECEIVE_NACK) {
+		udelay (I2C_DELAY);
+		if (count > 200) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+	I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/* stop */
+
+	return (0);
+}
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		temp = (unsigned int) (*temp_ptr);
+		I2C_WRITE_REG(I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_TRANSMIT_ACK) {
+			udelay (I2C_DELAY);
+			if (count > 20) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return (status);
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+	/* set the interrupt bit in the control register */
+	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG);
+	udelay (I2C_DELAY * 10);
+	return (0);
+}
+
+/* created this function to get the i2c_write() */
+/* function working properly. */
+/* function to write bytes out on the i2c bus */
+/* this is identical to the function i2c_write_data() */
+/* except that it requires a buffer that is an */
+/* unsigned character array.  You can't use */
+/* i2c_write_data() to send an array of unsigned characters */
+/* since the byte of interest ends up on the wrong end of the bus */
+/* aah, the joys of big endian versus little endian! */
+/* */
+/* returns 0 = success */
+/*         anything other than zero is failure */
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		I2C_WRITE_REG(I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY*2);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_TRANSMIT_ACK) {
+			udelay (I2C_DELAY*2);
+			if (count > 20) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return (status);
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+/*	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG | I2C_STP);
+	I2C_WRITE_REG(I2C_CNTR, I2C_STP); */
+	/* set the interrupt bit in the control register */
+	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG);
+	udelay (I2C_DELAY * 10);
+
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+/* initialize the table of address offset bytes */
+/* utilized for 2 byte address offsets */
+/* NOTE: the order is high byte first! */
+	table[1] = offset & 0xff;	/* low byte */
+	table[0] = offset / 0x100;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+uchar
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency again */
+
+	status = i2c_start ();
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction restart failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);	/* send the slave address */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Address not acknowledged: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not recieved: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+/* Function to set the I2C stop bit */
+void i2c_stop (void)
+{
+	I2C_WRITE_REG(I2C_CNTR, (0x1 << 4));
+}
+
+/* I2C write function */
+/* dev_addr = device address */
+/* offset = address offset */
+/* alen = length in bytes of the address offset */
+/* data = pointer to buffer to read data into */
+/* len = # of bytes to read */
+/* */
+/* returns 0 = succesful */
+/*         anything but zero is failure */
+uchar
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+	}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+/* function to determine if an I2C device is present */
+/* chip = device address of chip to check for */
+/* */
+/* returns 0 = sucessful, the device exists */
+/*         anything other than zero is failure, no device */
+int i2c_probe (uchar chip)
+{
+
+	/* We are just looking for an <ACK> back. */
+	/* To see if the device/chip is there */
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	i2c_status = I2C_READ_REG(I2C_STAT);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */

board/mindspeed/c2kevm/nand.c

diff --git a/board/mindspeed/c2kevm/nand.c b/board/mindspeed/c2kevm/nand.c
new file mode 100644
index 0000000..fbc6bc4
--- /dev/null
+++ b/board/mindspeed/c2kevm/nand.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <config.h>
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+#include <asm-arm/arch-comcerto/exp-bus_c2000.h>
+#include <asm-arm/io.h>
+
+
+/** Hardware specific access to NAND control-lines
+ **
+ ** @param[in] mtd       MTD device structure
+ ** @param[in] cmd       NAND command to the controller
+ ** @param[in] ctrl      control address/command latch
+ **
+ **/
+static void comcerto_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+                                                unsigned int ctrl)
+{
+        struct nand_chip *chip = mtd->priv;
+
+        if (ctrl & NAND_CTRL_CHANGE) {
+                if (ctrl & NAND_NCE)
+			SoC_gpio_set_0(SoC_gpio_mask(CFG_NAND_CE_GPIO));
+                else
+			SoC_gpio_set_1(SoC_gpio_mask(CFG_NAND_CE_GPIO));
+        }
+
+        if (cmd == NAND_CMD_NONE) {
+	 return;
+        }
+
+	if (ctrl & NAND_CLE)
+		writeb(cmd, chip->IO_ADDR_W + COMCERTO_NAND_CLE);
+        else if (ctrl & NAND_ALE)
+                writeb(cmd,  chip->IO_ADDR_W + COMCERTO_NAND_ALE);
+        else
+		return;
+}
+
+
+int comcerto_nand_ready(struct mtd_info *mtd)
+{
+	return SoC_gpio_read(SoC_gpio_mask(CFG_NAND_BR_GPIO)) ? 1 : 0;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	printf("board_nand_init nand->IO_ADDR_R =%x\n", nand->IO_ADDR_R);
+
+	nand->options = 0;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = comcerto_nand_hwcontrol;
+	nand->dev_ready = comcerto_nand_ready;
+	nand->chip_delay = 20;
+}
+#else
+int board_nand_init(struct nand_chip *nand)
+{
+}
+#endif

board/mindspeed/c2kevm/pad_config.c

diff --git a/board/mindspeed/c2kevm/pad_config.c b/board/mindspeed/c2kevm/pad_config.c
new file mode 100644
index 0000000..16d9104
--- /dev/null
+++ b/board/mindspeed/c2kevm/pad_config.c
@@ -0,0 +1,81 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clkcore_c2000.h>
+#include <asm/arch/ddr_c2000.h>
+#include <asm/arch/gpio_c2000.h>
+
+#define CONFIG_GEM_RGMII_2_5V
+//#define CONFIG_GEM_RGMII_3_3V
+#define CONFIG_HFE_OVERDRIVE
+
+/* Initialize pad config according to C2K_ChipDef_spec_010.doc */
+void comcerto_pad_config()
+{
+	u32 val;
+
+	/* HFE configurations */
+
+	/* Memories EMA Config 1 */
+	val = *(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1);
+	val &= ~((0x3 << 6)|(0x3 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1) = val;
+
+#if defined(CONFIG_GEM_RGMII_3_3V)
+	/*  Driving Strength of IO Pads */
+	/*In case GEMX operates in RMII or RGMII @3.3V mode then need to adjust
+	 *the driving strength of its IO pad (default value is for 2.5V) */
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3);
+	val &= ~((0x3 << 6) | (0x3 << 12));
+	val |= ((0x2 << 6) | (0x2 << 12));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4);
+	val &= ~((0x3 << 6)| (0x3 << 12));
+	val |= ((0x2 << 6) | (0x2 << 12));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5);
+	val &= ~((0x3 << 6) | (0x3 << 12));
+	val |= ((0x2 << 6) | (0x2 << 12));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5) = val;
+
+#elif defined(CONFIG_GEM_RGMII_2_5V)
+	/* RGMII Pad Compensation Logic (Tx side only)*/
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CTRL);
+	val &= ~((0x3 << 22) | (0x3 << 26) | (0x3 << 30));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CTRL) = val;
+#else
+#error "Either CONFIG_GEM_RGMII_3_3V or CONFIG_GEM_RGMII_2_5V should be selected"
+#endif
+	/* Slew Rate Control of IO Pads */
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3);
+	val |= ((0x1 << 11) | (0x1 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4);
+	val |= ((0x1 << 11) | (0x1 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5);
+	val |= ((0x1 << 11) | (0x1 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5) = val;
+
+#if defined (CONFIG_HFE_OVERDRIVE)
+	/* Memory Margin Bit setting */
+	/* In case HFE block operates in overdrive (1.2V) mode then need to
+	* modify few EMA fields related to HFE memories. The configuration
+	* registers are in GPIO block */
+	val = *(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG0);
+	val &= ~(0xFFF << 18);
+	val |= (0x38E << 18);
+	*(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG0) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1);
+	val &= ~(0x3F << 19);
+	val |= (0x8 << 18);
+	*(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1) = val;
+#endif
+
+	/*TODO Add rest of the configurations here*/
+
+}

board/mindspeed/c2kevm/reset.c

diff --git a/board/mindspeed/c2kevm/reset.c b/board/mindspeed/c2kevm/reset.c
new file mode 100644
index 0000000..fdd065f
--- /dev/null
+++ b/board/mindspeed/c2kevm/reset.c
@@ -0,0 +1,10 @@
+#include <common.h>
+
+/*
+ *  * Reset the cpu through the reset controller
+ *   */
+void __noreturn reset_cpu (unsigned long addr)
+{
+        while (1);
+}
+

board/mindspeed/c2kevm/u-boot.lds

diff --git a/board/mindspeed/c2kevm/u-boot.lds b/board/mindspeed/c2kevm/u-boot.lds
new file mode 100644
index 0000000..83b87a0
--- /dev/null
+++ b/board/mindspeed/c2kevm/u-boot.lds
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm_cortexa9/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
+

board/mindspeed/common/am29lv040b.c

diff --git a/board/mindspeed/common/am29lv040b.c b/board/mindspeed/common/am29lv040b.c
new file mode 100644
index 0000000..4ff2532
--- /dev/null
+++ b/board/mindspeed/common/am29lv040b.c
@@ -0,0 +1,237 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+
+#ifdef CFG_FLASH_AM040_DRIVER
+
+#define AM29LV040B_SIZE		(512 * 1024)
+#define AM29LV040B_SECTOR_SIZE	(64 * 1024)
+
+#define AM29LV040B_SECTORS	(AM29LV040B_SIZE / AM29LV040B_SECTOR_SIZE)
+
+
+/* Am29LV040B Codes */
+#define CMD_RESET		0xF0
+#define CMD_AUTO_SELECT		0x90
+#define CMD_UNLOCK1		0xAA
+#define CMD_UNLOCK2		0x55
+#define CMD_ERASE_SETUP		0x80
+#define CMD_ERASE_CONFIRM	0x30
+#define CMD_PROGRAM		0xA0
+#define CMD_UNLOCK_BYPASS	0x20
+#define CMD_SECTOR_UNLOCK	0x70
+
+#define MEM_FLASH_ADDR1		0x555
+#define MEM_FLASH_ADDR2		0x2AA
+
+#define BIT_ERASE_DONE		0x80
+#define BIT_RDY_MASK		0x80
+
+
+#if defined(CFG_FLASH_PROTECTION)
+int am29lv040b_flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	/* do nothing for now */
+	return ERR_INVAL;
+}
+#endif
+
+int am29lv040b_flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	volatile u8 *base = (u8 *)info->start[0];
+	volatile u8 *addr = base;
+	int flag, erased, prot, sect;
+	ulong start, now, last;
+
+	/* first look for protection bits */
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	erased = 0;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[MEM_FLASH_ADDR1] = CMD_UNLOCK1;
+	base[MEM_FLASH_ADDR2] = CMD_UNLOCK2;
+	base[MEM_FLASH_ADDR1] = CMD_ERASE_SETUP;
+	base[MEM_FLASH_ADDR1] = CMD_UNLOCK1;
+	base[MEM_FLASH_ADDR2] = CMD_UNLOCK2;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			addr = (u8 *)(info->start[sect]);
+
+			addr[0] = CMD_ERASE_CONFIRM;
+			erased++;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 50us - let's wait 100 us */
+	udelay (100);
+
+	if (erased == 0)
+		goto out;
+
+	printf ("Erasing %d sectors... ", erased);
+
+	start = get_timer (0);
+	last = start;
+	while ((addr[0] & BIT_ERASE_DONE) != BIT_ERASE_DONE) {
+		now = get_timer(start);
+		if (now > (erased * CFG_FLASH_ERASE_TOUT)) {
+			printf ("timeout\n");
+			return ERR_TIMOUT;
+		}
+		/* show that we're waiting */
+		if ((now - last) > (1 * CFG_HZ)) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+	printf ("ok\n");
+
+out:
+	/* reset to read mode */
+	base[0] = CMD_RESET;
+
+	return ERR_OK;
+}
+
+int am29lv040b_write_buff(flash_info_t *info, uchar *src, ulong dest, ulong cnt)
+{
+	volatile u8 *base = (u8 *)(info->start[0]);
+	volatile u8 *addr = (u8 *)dest;
+	u8 *wbuf = src;
+	ulong last, now, start;
+
+	last = get_timer(0);
+	for (; (cnt > 0); cnt--, addr++, wbuf++) {
+		if (*addr != *wbuf) {
+			base[MEM_FLASH_ADDR1] = CMD_UNLOCK1;
+			base[MEM_FLASH_ADDR2] = CMD_UNLOCK2;
+			base[MEM_FLASH_ADDR1] = CMD_PROGRAM;
+			*addr = *wbuf;
+
+			start = get_timer (0);
+			while ((*addr & BIT_RDY_MASK) != (*wbuf & BIT_RDY_MASK)) {
+				now = get_timer(0);
+				if ((now - start) > CFG_FLASH_WRITE_TOUT) {
+					printf ("timeout ");
+					break;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > (1 * CFG_HZ)) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			if (*addr != *wbuf) {
+				printf("write failed, address %08lx -> %x(%x)\n",
+						(unsigned long)addr, *wbuf, *addr);
+
+				base[0] = CMD_RESET;   /* Reset */
+
+				return ERR_TIMOUT;
+			}
+		}
+	}
+
+	printf("ok\n");
+
+	return ERR_OK;
+}
+
+
+static ulong am29lv040b_get_size(flash_info_t *info, ulong base_addr)
+{
+	volatile u8 *base = (u8 *)base_addr;
+	volatile u8 *addr;
+	u8 manuf_id, device_id;
+	int i;
+
+	base[MEM_FLASH_ADDR1] = CMD_UNLOCK1;
+	base[MEM_FLASH_ADDR2] = CMD_UNLOCK2;
+	base[MEM_FLASH_ADDR1] = CMD_AUTO_SELECT;
+
+	manuf_id = base[0];
+	device_id = base[1];
+
+	if (manuf_id != (AMD_MANUFACT & 0xff))
+		return 0;
+
+	if (device_id != AMD_ID_LV040B)
+		return 0;
+
+	printf("found AM29LV040B flash at %08X\n", base_addr);
+
+	info->flash_id = FLASH_MAN_AMD | FLASH_AM040;
+	info->size = AM29LV040B_SIZE;
+	info->sector_count = AM29LV040B_SECTORS;
+
+	memset(info->protect, 0, info->sector_count);
+
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base_addr + i * AM29LV040B_SECTOR_SIZE;
+
+		addr = (u8 *)info->start[i];
+		info->protect[i] = addr[2] & 0x1;
+	}
+
+	/* Reset flash */
+	base[0] = CMD_RESET;
+
+	return info->size;
+}
+
+ulong am29lv040b_flash_init(flash_info_t * info)
+{
+	ulong base_addr[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
+	ulong size = 0;
+	int i;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		if (info[i].flash_id == FLASH_UNKNOWN)
+			size += am29lv040b_get_size(&info[i], base_addr[i]);
+	}
+
+	return size;
+}
+#endif

board/mindspeed/common/amlv640u.c

diff --git a/board/mindspeed/common/amlv640u.c b/board/mindspeed/common/amlv640u.c
new file mode 100644
index 0000000..116ac16
--- /dev/null
+++ b/board/mindspeed/common/amlv640u.c
@@ -0,0 +1,249 @@
+/*
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+
+#ifdef CFG_FLASH_AMLV640U_DRIVER
+
+#define AMLV640U_SECTOR_SIZE	0x00010000      /* 64 KB sectors */
+#define AMLV640U_SECTORS	(CFG_FLASH_AMLV640U_SIZE / AMLV640U_SECTOR_SIZE)
+
+#define FTIMEOUT		16000000
+
+/* Functions */
+int amlv640u_flash_erase (flash_info_t *info, int s_first, int s_last);
+int amlv640u_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+
+#if defined(CFG_FLASH_PROTECTION)
+int amlv640u_flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	/* do nothing for now */
+	return ERR_INVAL;
+}
+#endif
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int amlv640u_flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile u16 *base = (u16 *)info->start[0];
+	volatile u16 *addr = base;
+	int flag, prot, sect, erased;
+	ulong start, now, last;
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	erased = 0;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[0x555] = 0xAA;
+	base[0x2AA] = 0x55;
+	base[0x555] = 0x80;
+	base[0x555] = 0xAA;
+	base[0x2AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (u16 *)info->start[sect];
+			addr[0] = 0x30;
+			erased++;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 50us - let's wait 100 us */
+	udelay (100);
+
+	if (erased == 0)
+		goto out;
+
+	printf ("Erasing %d sectors... ", erased);
+
+	start = get_timer (0);
+	last = start;
+	while ((addr[0] & 0x80) != 0x80) {
+		now = get_timer(start);
+		if (now > (erased * CFG_FLASH_ERASE_TOUT)) {
+			printf ("timeout\n");
+			return ERR_TIMOUT;
+		}
+		/* show that we're waiting */
+		if ((now - last) > (1 * CFG_HZ)) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+	printf ("ok\n");
+
+out:
+	/* reset to read mode */
+	base[0] = 0xF0;
+
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int amlv640u_write_buff (flash_info_t *info, uchar *src, ulong dest, ulong cnt)
+{
+	volatile u16 *base = (u16 *)(info->start[0]);
+	volatile u16 *addr = (u16 *)dest;
+	u16 *wbuf = (u16 *)src;
+	ulong last, now, start;
+
+	last = get_timer(0);
+	for (cnt >>= 1; (cnt > 0); cnt--, addr++, wbuf++) {
+		if (*addr != *wbuf) {
+			base[0x555] = 0xAA;
+			base[0x2AA] = 0x55;
+			base[0x555] = 0xA0;
+			*addr = *wbuf;
+
+			start = get_timer (0);
+			while ((*addr & 0x80) != (*wbuf & 0x80)) {
+				now = get_timer(0);
+				if ((now - start) > CFG_FLASH_WRITE_TOUT) {
+					printf ("timeout ");
+					break;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > (1 * CFG_HZ)) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			if (*addr != *wbuf) {
+				printf("write failed, address %08lx -> %x(%x)\n",
+						(unsigned long)addr, *wbuf, *addr);
+
+				base[0] = 0xF0;   /* Reset */
+
+				return ERR_TIMOUT;
+			}
+		}
+	}
+
+	printf("ok\n");
+
+	return ERR_OK;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong amlv640u_get_size (flash_info_t *info, ulong base_addr)
+{
+	volatile u16 *base = (u16 *)base_addr;
+	volatile u16 *addr;
+	u16 manuf_id, device_id1, device_id2, device_id3;
+	int i;
+
+        /* Write auto select command: read Manufacturer ID */
+	base[0x555] = 0xAA;
+        base[0x2AA] = 0x55;
+	base[0x555] = 0x90;
+
+	manuf_id = base[0];
+	device_id1 = base[1];
+	device_id2 = base[14];
+	device_id3 = base[15];
+
+	if (manuf_id != (AMD_MANUFACT & 0xffff))
+		return 0;
+
+	if (device_id1 != (AMD_ID_MIRROR & 0xffff) ||
+	    device_id2 != (AMD_ID_LV640U_2 & 0xffff) ||
+	    device_id3 != (AMD_ID_LV640U_3 & 0xffff))
+		return 0;
+
+	printf("found AMLV640U flash at %08X\n", base_addr);
+
+	info->flash_id = FLASH_MAN_AMD | FLASH_AMLV640U;
+	info->size = CFG_FLASH_AMLV640U_SIZE;
+	info->sector_count = AMLV640U_SECTORS;
+
+	memset (info->protect, 0, info->sector_count);
+
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base_addr + i * AMLV640U_SECTOR_SIZE;
+
+		addr = (u16 *)info->start[i];
+		info->protect[i] = addr[2] & 0x1;
+	}
+
+	/* Reset flash */
+	base[0] = 0xF0;
+
+	return info->size;
+}
+
+
+ulong amlv640u_flash_init (flash_info_t * info)
+{
+	ulong base_addr[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
+	ulong size = 0;
+	int i;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		if (info[i].flash_id == FLASH_UNKNOWN) {
+			size += amlv640u_get_size(&info[i], base_addr[i]);
+		}
+	}
+
+	return size;
+}
+#endif

board/mindspeed/common/arm1_init.S

diff --git a/board/mindspeed/common/arm1_init.S b/board/mindspeed/common/arm1_init.S
new file mode 100644
index 0000000..5eca981
--- /dev/null
+++ b/board/mindspeed/common/arm1_init.S
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This code runs from ARM1 and setups the CPU before jumping to
+the beginning of the ARM1 image (usually a Linux zImage).
+It must be copied to 0x00000000 before releasing ARM1.
+Linker script variables (in u-boot.lds) are used to find the
+start and end address of this bit of code */
+
+.globl _arm1_start_addr
+.globl _arm1_r0
+.globl _arm1_r1
+.globl _arm1_r2
+
+
+	ldr	r0, _arm1_r0
+	ldr	r1, _arm1_r1
+	ldr	r2, _arm1_r2
+	ldr	pc, _arm1_start_addr
+
+_arm1_start_addr:
+	.word 0x00000000
+
+_arm1_r0:
+	.word 0x00000000
+
+_arm1_r1:
+	.word 0x00000000
+
+_arm1_r2:
+	.word 0x00000000
+

board/mindspeed/common/cmd_bootcomcerto.c

diff --git a/board/mindspeed/common/cmd_bootcomcerto.c b/board/mindspeed/common/cmd_bootcomcerto.c
new file mode 100644
index 0000000..6dc1544
--- /dev/null
+++ b/board/mindspeed/common/cmd_bootcomcerto.c
@@ -0,0 +1,595 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/byteorder.h>
+#include <asm/hardware.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+extern int valid_elf_image (unsigned long addr);
+extern unsigned long load_elf_image (unsigned long addr);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct _AIF_HEADER {
+	u32 BL_DecompressCode;
+	u32 BL_SelfRelocCode;
+	u32 BL_DbgInitZeroInit;
+	u32 EntryPointOffset;
+	u32 ProgramExitInstr;
+	u32 ImageReadOnlySize;
+	u32 ImageReadWriteSize;
+	u32 ImageDebugSize;
+	u32 ImageZeroInitSize;
+	u32 ImageDebugType;
+	u32 ImageBase;
+	u32 WorkSpace;
+	u32 AddressMode;
+	u32 DataBase;
+	u32 FirstFatOffset;
+	u32 Reserved2;
+	u32 DebugInitInstr;
+	u32 ZeroInitCode[15];
+};
+
+struct _FAT_AIF_HEADER {
+	u32 NextFatOffset;
+	u32 LoadAddress;
+	u32 Size;
+	u8 region_name[32];
+};
+
+/**
+ * print_axf_hdr -
+ *
+ */
+static void print_axf_hdr(ulong addr)
+{
+	struct _AIF_HEADER *aif_hdr = (struct _AIF_HEADER *)(addr);
+
+	/* we assume that MSP image in memory is not less than the header size (_AIF_HEADER) */
+
+	printf("code_offset=0x80\n");
+	printf("code_base=%lx\n", aif_hdr->ImageBase);
+	printf("data_offset=%lx\n", 0x80 + aif_hdr->ImageReadOnlySize);
+	printf("code_size=%lx\n", aif_hdr->ImageReadOnlySize);
+	printf("data_base=%lx\n", aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize);
+	printf("data_size=%lx\n", aif_hdr->ImageReadWriteSize);
+	printf("zeroinit_base=%lx\n",
+	       aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize + aif_hdr->ImageReadWriteSize);
+	printf("prog_entry=%lx\n", aif_hdr->ImageBase + aif_hdr->EntryPointOffset);
+
+	printf(" \n");
+	printf("AIFHEADER:\n");
+	printf("BL_DecompressCode=%lx\n", aif_hdr->BL_DecompressCode);
+	printf("BL_SelfRelocCode=%lx\n", aif_hdr->BL_SelfRelocCode);
+	printf("BL_DbgInitZeroInit=%lx\n", aif_hdr->BL_DbgInitZeroInit);
+	printf("EntryPointOffset=%lx\n", aif_hdr->EntryPointOffset);
+	printf("ProgramExitInstr=%lx\n", aif_hdr->ProgramExitInstr);
+	printf("ImageReadOnlySize=%lx\n", aif_hdr->ImageReadOnlySize);
+	printf("ImageReadWriteSize=%lx\n", aif_hdr->ImageReadWriteSize);
+	printf("ImageDebugSize=%lx\n", aif_hdr->ImageDebugSize);
+	printf("ImageZeroInitSize=%lx\n", aif_hdr->ImageZeroInitSize);
+	printf("ImageDebugType=%lx\n", aif_hdr->ImageDebugType);
+	printf("ImageBase=%lx\n", aif_hdr->ImageBase);
+	printf("WorkSpace=%lx\n", aif_hdr->WorkSpace);
+	printf("AddressMode=%lx\n", aif_hdr->AddressMode);
+	printf("DataBase=%lx\n", aif_hdr->DataBase);
+	printf("FirstFatOffset=%lx\n", aif_hdr->FirstFatOffset);
+	printf("Reserved2=%lx\n", aif_hdr->Reserved2);
+	printf("DebugInitInstr=%lx\n", aif_hdr->DebugInitInstr);
+	printf("ZeroInitCode[0]=%lx\n", aif_hdr->ZeroInitCode[0]);
+}
+
+/**
+ * check_load_addr -
+ *
+ */
+static int check_load_addr(ulong addr)
+{
+	if ((addr > MSP_BOTTOM_MEMORY_RESERVED_SIZE) &&
+#if defined(CONFIG_COMCERTO_530)
+	    ((addr < ERAM_BASEADDR) || (addr >= IRAM_BASEADDR + IRAM_SIZE))
+#elif defined(CONFIG_COMCERTO_515) || defined(CONFIG_COMCERTO_800)
+	    ((addr < ERAM_BASEADDR) || (addr >= ARAM_BASEADDR + ARAM_SIZE))
+#elif defined(CONFIG_COMCERTO_900)
+	    ((addr < ERAM_BASEADDR) || (addr >= CRAM_BASEADDR + CRAM_SIZE))
+#else
+	    (1)
+#endif
+	)
+		return -1;
+
+	return 0;
+}
+
+/**
+ * load_axf_zero -
+ *
+ */
+static int load_axf_zero(ulong addr)
+{
+	struct _AIF_HEADER *aif_hdr = (struct _AIF_HEADER *)(addr);
+	u32 m_data_base;
+	u32 bytes_to_load;
+
+	if (aif_hdr->DataBase)
+		m_data_base = aif_hdr->DataBase;
+	else
+		m_data_base = aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize;
+
+	m_data_base = m_data_base + aif_hdr->ImageReadWriteSize;
+	bytes_to_load = aif_hdr->ImageZeroInitSize / 2;
+
+	if (check_load_addr(m_data_base + bytes_to_load) < 0) {
+		printf("data section load address %x outside range\n", m_data_base + bytes_to_load);
+		goto err;
+	}
+
+	memset((void *)m_data_base, 0, bytes_to_load);
+
+	return 0;
+
+err:
+	return -1;
+}
+
+/**
+ * load_axf_fat -
+ */
+static int load_axf_fat(ulong addr, ulong size)
+{
+	struct _AIF_HEADER *aif_hdr = (struct _AIF_HEADER *)(addr);
+	struct _FAT_AIF_HEADER *fat_aif_hdr;
+	u32 fat_offset;
+
+	fat_offset = aif_hdr->FirstFatOffset;
+
+	while (fat_offset > 0) {
+
+		if ((fat_offset + sizeof(struct _FAT_AIF_HEADER)) > size) {
+			printf("fat section header at %x outside image %x\n", fat_offset, size);
+			goto err;
+		}
+
+		fat_aif_hdr = (struct _FAT_AIF_HEADER *)(addr + fat_offset);
+
+		if ((fat_offset + sizeof(struct _FAT_AIF_HEADER) + fat_aif_hdr->Size) > size) {
+			printf("fat section size %x bigger than image size %x\n", fat_offset + sizeof(struct _FAT_AIF_HEADER) + fat_aif_hdr->Size, size);
+			goto err;
+		}
+
+		if (check_load_addr(fat_aif_hdr->LoadAddress + fat_aif_hdr->Size) < 0) {
+			printf("fat section load address %x outside range\n", fat_aif_hdr->LoadAddress + fat_aif_hdr->Size);
+			goto err;
+		}
+
+		memcpy((void *)fat_aif_hdr->LoadAddress,
+		       (void *)(addr + fat_offset + sizeof(struct _FAT_AIF_HEADER)), fat_aif_hdr->Size);
+
+		fat_offset = fat_aif_hdr->NextFatOffset;
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
+
+/**
+ * load_axf_data -
+ */
+static int load_axf_data(ulong addr, ulong size)
+{
+	struct _AIF_HEADER *aif_hdr = (struct _AIF_HEADER *)(addr);
+
+	if (aif_hdr->ImageReadWriteSize) {
+
+		if ((sizeof(struct _AIF_HEADER) + aif_hdr->ImageReadOnlySize + aif_hdr->ImageReadWriteSize) > size) {
+			printf("data section size %x bigger than image size %x\n", aif_hdr->ImageReadWriteSize, size);
+			goto err;
+		}
+
+		if (aif_hdr->DataBase == 0) {
+			if (check_load_addr(aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize + aif_hdr->ImageReadWriteSize) < 0) {
+				printf("data section load address %x outside range\n", aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize + aif_hdr->ImageReadWriteSize);
+				goto err;
+			}
+
+			memcpy((void *)(aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize),
+			       (void *)(addr + sizeof(struct _AIF_HEADER) + aif_hdr->ImageReadOnlySize),
+			       aif_hdr->ImageReadWriteSize);
+		} else {
+			if (check_load_addr(aif_hdr->DataBase + aif_hdr->ImageReadWriteSize) < 0) {
+				printf("data section load address %x outside range\n", aif_hdr->DataBase + aif_hdr->ImageReadWriteSize);
+				goto err;
+			}
+
+			memcpy((void *)aif_hdr->DataBase,
+			       (void *)(addr + sizeof(struct _AIF_HEADER) + aif_hdr->ImageReadOnlySize),
+			       aif_hdr->ImageReadWriteSize);
+		}
+
+	} else {
+		printf("data section size 0\n");
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
+
+/**
+ * load_axf_code -
+ *
+ */
+static int load_axf_code(ulong addr, ulong size)
+{
+	struct _AIF_HEADER *aif_hdr = (struct _AIF_HEADER *)(addr);
+
+	if (aif_hdr->ImageReadOnlySize) {
+		if ((sizeof(struct _AIF_HEADER) + aif_hdr->ImageReadOnlySize) > size) {
+			printf("code section size %x bigger than image size %x\n", aif_hdr->ImageReadOnlySize, size);
+			goto err;
+		}
+
+		if (check_load_addr(aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize) < 0) {
+			printf("code section load address %x outside range\n", aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize);
+			goto err;
+		}
+
+		memcpy((void *)aif_hdr->ImageBase, (void *)(addr + sizeof(struct _AIF_HEADER)), aif_hdr->ImageReadOnlySize);
+	} else {
+		printf("code section size 0\n");
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
+/**
+ * load_axf_image -
+ *
+ */
+static ulong load_axf_image(ulong addr, ulong size)
+{
+	struct _AIF_HEADER *aif_hdr = (struct _AIF_HEADER *) addr;
+
+	printf ("## Downloading image at %08lx ...\n", addr);
+
+	if (sizeof (struct _AIF_HEADER) > size) {
+		printf("AXF header %x bigger than image size %x\n", sizeof (struct _AIF_HEADER), size);
+		goto err;
+	}
+
+	print_axf_hdr(addr);
+
+	if (load_axf_code(addr, size)) {
+		printf("download code failed\n");
+		goto err;
+	}
+
+	if (load_axf_data(addr, size)) {
+		printf("download data failed\n");
+		goto err;
+	}
+
+	if (load_axf_fat(addr, size)) {
+		printf("download fat failed\n");
+		goto err;
+	}
+
+	if (load_axf_zero(addr)) {
+		printf("zero init failed\n");
+		goto err;
+	}
+
+//	printf ("## Booting image at %08lx ...\n", aif_hdr->ImageBase + aif_hdr->EntryPointOffset);
+
+	return aif_hdr->ImageBase + aif_hdr->EntryPointOffset;
+
+err:
+	return (ulong)-1;
+}
+
+/**
+ * strtoul_with_check - reads unsigned long hex value from string with checking
+ *
+ * ARGUMENTS:
+ *    str:    the string to scan value from
+ *    pvalue: pointer to the value location (if be NULL just checking will be
+ *            performed)
+ *    label:  optinal label for the typical error message (if NULL no message
+ *            will be printed)
+ *
+ * RETURNS:
+ *    0 success, -1 otherwise
+ */
+static int strtoul_with_check(const char *str, ulong *pvalue, const char *label)
+{
+	ulong value;
+	char *end = NULL;
+
+	value = simple_strtoul(str, &end, 16);
+	if (str == end || *end != 0) {
+		if (label)
+			printf("Invalid %s given, please provide correct hex value.\n", label);
+		return -1;
+	}
+
+	if (pvalue)
+		*pvalue = value;
+
+	return 0;
+}
+
+/**
+ * do_loadmsp - loads MSP image, it may be in either ELF or AXF format. If image
+ *    is successfully loaded, stores MSP entry in "msp_start_addr" env. variable.
+ *
+ * ARGUMENTS:
+ *    standard set of U-Boot command arguments, user must pass image address
+ *    and size (all in hex).
+ *
+ * RETURNS:
+ *    0 - success, -1 otherwise
+ */
+static int do_loadmsp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr, size;
+	char buf[32];
+
+	if (argc < 3) {
+		goto err;
+	}
+
+	if (strtoul_with_check(argv[1], &addr, "image address"))
+		goto err;
+
+	if (strtoul_with_check(argv[2], &size, "image size"))
+		goto err;
+
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+	if (valid_elf_image(addr))
+		addr = load_elf_image(addr);
+	else
+		addr = load_axf_image(addr, size);
+#else
+	addr = load_axf_image(addr, size);
+#endif
+
+	if (addr == (ulong)-1)
+		goto err;
+
+	/* store MSP start addr in environment (we will need it do_bootcomcerto) */
+	sprintf(buf, "%lx", addr);
+	setenv("msp_start_addr", buf);
+	printf("image loaded at %lx\n", addr);
+	return 0;
+
+err:
+	printf("error loading image\n");
+	return -1;
+}
+
+
+U_BOOT_CMD(
+	loadmsp,  3, 0, do_loadmsp,
+	"loadmsp - load MSP image (AXF or ELF format) and save MSP start address\n",
+	"address size\n"
+	"    - 'address' (hex) points to MSP image location.\n"
+	"      'size' (hex) specifies image size.\n"
+	"      See also 'bootcomcerto' command.\n"
+);
+
+
+extern char __arm1_init_start, __arm1_init_end;
+extern u32 _arm1_start_addr, _arm1_r0, _arm1_r1, _arm1_r2;
+
+/**
+ * set_arm1_init - copies ARM1 startup code to reset location and sets CSP
+ *    image startup address
+ *
+ * ARGUMENTS:
+ *    addr:     CSP entry point
+ *    r0,r1,r2: values for the corresponding ARM1 registers
+ */
+static void set_arm1_init(ulong addr, ulong r0, ulong r1, ulong r2)
+{
+	_arm1_start_addr = addr;
+	_arm1_r0 = r0;
+	_arm1_r1 = r1;
+	_arm1_r2 = r2;
+
+	printf("Copying ARM1 startup code from %08x, start address %08x\n",
+		&__arm1_init_start, addr);
+
+	memcpy(0, &__arm1_init_start, &__arm1_init_end - &__arm1_init_start);
+}
+
+#if !defined(CONFIG_COMCERTO_1000) && !defined(CONFIG_COMCERTO_100)
+/* This code only applies to Carrier/Access platforms, where ARM0 is running
+ * the MSP and ARM1 the CSP
+ */
+extern image_header_t header;
+extern void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
+		     ulong addr, ulong *len_ptr, int verify);
+
+#define BOOT_ETH_BASE_ADDRESS	(IRAM_BASEADDR + 0x1250)
+#define MAGIC_NUM_ADDRESS_IRAM	(BOOT_ETH_BASE_ADDRESS + 0x10)
+#define FLAGS_ADDRESS_IRAM	(BOOT_ETH_BASE_ADDRESS + 0x14)
+#define M1_ADDRESS_IRAM		(BOOT_ETH_BASE_ADDRESS + 0x18)
+#define M5_ADDRESS_IRAM		(BOOT_ETH_BASE_ADDRESS + 0x24)
+
+#define MAGIC_NUM_IRAM		0x98765432
+#define ETHADDR_IRAM_MASK	(1 << 0)
+
+static void msp_boot_eth_hdr_setup(bd_t * bd)
+{
+	struct eth_hdr {
+		u8 hostmac[6];
+		u8 mspmac[6];
+		u8 padding;
+		u16 packet_type;
+	} __attribute__((packed)) *hdr;
+
+	/* The MSP expects an ethernet header at this IRAM address */
+	/* at boot time */
+
+	hdr = (struct eth_hdr *)(BOOT_ETH_BASE_ADDRESS + 1);
+	
+	hdr->hostmac[0] = 0x00;
+	hdr->hostmac[1] = 0x11;
+	hdr->hostmac[2] = 0x22;
+	hdr->hostmac[3] = 0x33;
+	hdr->hostmac[4] = 0x44;
+	hdr->hostmac[5] = 0x55;
+
+	hdr->mspmac[0] = 0x00;
+	hdr->mspmac[1] = 0x1a;
+	hdr->mspmac[2] = 0x1b;
+	hdr->mspmac[3] = 0x1c;
+	hdr->mspmac[4] = 0x1d;
+	hdr->mspmac[5] = 0x1e;
+
+	hdr->packet_type = 0x889b;
+}
+
+static void msp_iram_flags_setup(bd_t * bd)
+{
+	int i;
+	ulong reg;
+	char *s, *e;
+	char tmp[64];
+				
+	/* pass miscellaneous params to the MSP via IRAM
+	   Since these are not passed by all boot loaders use a magic number
+	   to tell the MSP that if parameters are present */
+	*(u32 *)MAGIC_NUM_ADDRESS_IRAM = MAGIC_NUM_IRAM;
+
+	/* the next word is a bit-map that tells the MSP which parameters are present,
+           this allows params to be added and different versions of bootloader and MSP
+           to inter-operate */
+
+	/* always have ethaddr; even if user does not specify it (which is an error), we have a default */
+	*(u32 *)FLAGS_ADDRESS_IRAM = ETHADDR_IRAM_MASK;
+
+	/* write ethernet address */
+	memcpy((u8 *)M1_ADDRESS_IRAM, bd->bi_enetaddr, 6);
+
+	i = getenv_r ("eth1addr", tmp, sizeof (tmp));
+	s = (i > 0) ? tmp : NULL;
+	for (reg = 0; reg < 6; ++reg) {
+		*(u8 *) (M5_ADDRESS_IRAM + reg) = s ? simple_strtoul (s, &e, 16) : 0;
+		if (s)
+			s = (*e) ? e + 1 : e;
+	}
+}
+
+/**
+ * do_bootcomcerto - checks if MSP image was loaded, then loads CSP image which
+ *    may be in either binary or ELF format and boots MSP.
+ *
+ * ARGUMENTS:
+ *    standard set of U-Boot command arguments, user must pass CSP image address
+ *
+ * RETURNS:
+ *    doesn't return on success
+ */
+static int do_bootcomcerto (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong csp_start_addr, msp_start_addr;
+	int csp_is_elf = 0;
+	bd_t *bd = gd->bd;
+	char *str;
+
+	if (argc < 2) {
+		return -1;
+	}
+
+	str = getenv("msp_start_addr");
+	if (!str) {
+		printf("MSP start address is not set, see 'loadmsp' command\n");
+		return -1;
+	}
+
+	if (strtoul_with_check(str, &msp_start_addr, NULL)) {
+		printf("Invalid MSP address, aborting\n");
+		return -1;
+	}
+
+	if (strtoul_with_check(argv[1], &csp_start_addr, "image address"))
+		return -1;
+
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+	if ((csp_is_elf = valid_elf_image(csp_start_addr)) != 0)
+		csp_start_addr = load_elf_image(csp_start_addr);
+#endif
+
+	/* Setup MSP boot args in IRAM */
+	msp_boot_eth_hdr_setup(bd);
+	msp_iram_flags_setup(bd);
+
+	if (csp_is_elf == 0) {
+		/* CSP image is in binary format, assuming Linux */
+
+		/* Fake header to keep do_bootm_linux() happy
+		 * No ramdisk support for now
+		 */
+		header.ih_ep = htonl(msp_start_addr);	/* This is actually the MSP entry point */
+		header.ih_type = IH_TYPE_KERNEL;
+#if 0
+		hdr->ih_magic = htonl(IH_MAGIC);
+		hdr->ih_hcrc = htonl(0);	/* FIXME calculate the checksum */
+		hdr->ih_size = htonl(0);
+#endif
+
+		set_arm1_init(csp_start_addr, 0, bd->bi_arch_number, bd->bi_boot_params);
+		do_bootm_linux(cmdtp, 0, argc, argv, 0, NULL, 0);
+	}
+	else {
+		/* CSP image is in ELF, assuming VxWorks */
+
+		set_arm1_init(csp_start_addr, (unsigned int)getenv("bootargs"), 0, 0);
+		((void(*)(void))msp_start_addr)();
+	}
+
+	printf("Unexpected return to bootloader!\n");
+
+	return 0;
+}
+
+
+U_BOOT_CMD(
+	bootcomcerto, 2, 0, do_bootcomcerto,
+	"bootcomcerto - load CSP image (binary or ELF format) and start Comcerto device\n",
+	"address\n"
+	"    - 'address'(hex) points to CSP image location.\n"
+	"      See also 'loadmsp' command, which must be run before this one.\n"
+);
+#endif

board/mindspeed/common/flash.c

diff --git a/board/mindspeed/common/flash.c b/board/mindspeed/common/flash.c
new file mode 100644
index 0000000..dd35783
--- /dev/null
+++ b/board/mindspeed/common/flash.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+#ifdef CFG_FLASH_CFI_DRIVER
+
+#define FLASH_MAN_CFI		0x01000000
+
+#ifdef CFG_FLASH_PROTECTION
+extern int cfi_flash_real_protect(flash_info_t *info, long sector, int prot);
+#endif
+
+extern int cfi_flash_erase(flash_info_t * info, int s_first, int s_last);
+extern int cfi_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+extern void cfi_flash_print_info(flash_info_t *info);
+extern unsigned long cfi_flash_init(void);
+#endif
+
+
+#ifdef CFG_FLASH_AM040_DRIVER
+#ifdef CFG_FLASH_PROTECTION
+int am29lv040b_flash_real_protect(flash_info_t *info, long sector, int prot);
+#endif
+int am29lv040b_flash_erase(flash_info_t * info, int s_first, int s_last);
+int am29lv040b_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+ulong am29lv040b_flash_init(flash_info_t * info);
+#endif
+
+#ifdef CFG_FLASH_AMLV640U_DRIVER
+int amlv640u_flash_erase (flash_info_t *info, int s_first, int s_last);
+int amlv640u_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+ulong amlv640u_flash_init(flash_info_t * info);
+#endif
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+
+	if ((s_first < 0) || (s_first > s_last) || (s_last >= info->sector_count)) {
+		return ERR_INVAL;
+	}
+
+#ifdef CFG_FLASH_CFI_DRIVER
+	if (info->flash_id == FLASH_MAN_CFI)
+		return cfi_flash_erase(info, s_first, s_last);
+#endif
+
+#ifdef CFG_FLASH_AM040_DRIVER
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
+		return am29lv040b_flash_erase(info, s_first, s_last);
+#endif
+
+#ifdef CFG_FLASH_AMLV640U_DRIVER
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV640U)
+		return amlv640u_flash_erase(info, s_first, s_last);
+#endif
+
+	return ERR_UNKNOWN_FLASH_TYPE;
+}
+
+#ifdef CFG_FLASH_PROTECTION
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+
+	if ((sector < 0) || (sector >= info->sector_count)) {
+		return ERR_INVAL;
+	}
+
+#ifdef CFG_FLASH_CFI_DRIVER
+	if (info->flash_id == FLASH_MAN_CFI)
+		return cfi_flash_real_protect(info, sector, prot);
+#endif
+
+#ifdef CFG_FLASH_AM040_DRIVER
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
+		return am29lv040b_flash_real_protect(info, sector, prot);
+#endif
+
+#ifdef CFG_FLASH_AMLV640U_DRIVER
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV640U)
+		return amlv640u_flash_real_protect(info, sector, prot);
+#endif
+
+	return ERR_UNKNOWN_FLASH_TYPE;
+}
+#endif
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+
+#ifdef CFG_FLASH_CFI_DRIVER
+	if (info->flash_id == FLASH_MAN_CFI)
+		return cfi_write_buff(info, src, addr, cnt);
+#endif
+
+#ifdef CFG_FLASH_AM040_DRIVER
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
+		return am29lv040b_write_buff(info, src, addr, cnt);
+#endif
+
+#ifdef CFG_FLASH_AMLV640U_DRIVER
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV640U)
+		return amlv640u_write_buff(info, src, addr, cnt);
+#endif
+
+	return ERR_UNKNOWN_FLASH_TYPE;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+#ifdef CFG_FLASH_CFI_DRIVER
+	if (info->flash_id == FLASH_MAN_CFI) {
+		cfi_flash_print_info(info);
+		return;
+	}
+#endif
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+
+	/* Add other supported flash vendors here */
+
+	default:
+		printf ("Unknown Vendor ");
+		return;
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4Mbit, uniform sector size)\n");
+		break;
+
+	case FLASH_AMLV640U:
+		printf ("AM29LV640ML/S29GL064M (64Mbit, uniform sector size)\n");
+		break;
+
+	default:
+		printf ("Unknown Chip Type\n");
+		return;
+		break;
+	}
+
+	if ((info->size >> 20) > 0)
+		printf ("  Size: %ld MiB in %d Sectors\n", info->size >> 20, info->sector_count);
+	else
+		printf ("  Size: %ld KiB in %d Sectors\n", info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+
+	printf ("\n");
+
+	return;
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long size = 0;
+	int i;
+
+	printf("Comcerto Flash Subsystem Initialization\n");
+
+	/* Init: no Flashes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+#ifdef CFG_FLASH_CFI_DRIVER
+	/* CFI compatible flash detection */
+	/* must be done first */
+	size += cfi_flash_init();
+#endif
+
+#ifdef CFG_FLASH_AM040_DRIVER
+	size += am29lv040b_flash_init(flash_info);
+#endif
+
+#ifdef CFG_FLASH_AMLV640U_DRIVER
+	size += amlv640u_flash_init(flash_info);
+#endif
+
+	return size;
+}

board/mindspeed/common/i2c.c

diff --git a/board/mindspeed/common/i2c.c b/board/mindspeed/common/i2c.c
new file mode 100644
index 0000000..37ac1ed
--- /dev/null
+++ b/board/mindspeed/common/i2c.c
@@ -0,0 +1,559 @@
+/*
+ * (C) Copyright 2007
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#define MAX_I2C_RETRYS	    10
+#define I2C_DELAY	    1000	/* Should be at least the # of MHz of Tclk */
+
+#define I2C_ADDR                        (I2C_BASEADDR + 0x00)
+#define I2C_DATA                        (I2C_BASEADDR + 0x04)
+#define I2C_CNTR                        (I2C_BASEADDR + 0x08)
+#define I2C_STAT                        (I2C_BASEADDR + 0x0c)
+#define I2C_CCRFS                       (I2C_BASEADDR + 0x0c)
+#define I2C_XADDR                       (I2C_BASEADDR + 0x10)
+#define I2C_CCRH                        (I2C_BASEADDR + 0x14)
+#define I2C_SOFT_RESET                  (I2C_BASEADDR + 0x1c)
+
+/* CNTR - Control register bits */
+#define I2C_IEN				(1<<7)
+#define I2C_ENAB			(1<<6)
+#define I2C_STA				(1<<5)
+#define I2C_STP				(1<<4)
+#define I2C_IFLG			(1<<3)
+#define I2C_AAK				(1<<2)
+
+/* STAT - Status codes */
+#define I2C_BUS_ERROR			0x00	/* Bus error in master mode only */
+#define I2C_START_TRANSMIT		0x08	/* Start condition transmitted */
+#define I2C_REPEAT_START_TRANSMIT	0x10	/* Repeated Start condition transmited */
+#define I2C_ADDRESS_W_ACK		0x18	/* Address + Write bit transmitted, ACK received */
+#define I2C_ADDRESS_W_NACK		0x20	/* Address + Write bit transmitted, NACK received */
+#define I2C_DATA_TRANSMIT_ACK		0x28	/* Data byte transmitted in master mode , ACK received */
+#define I2C_DATA_TRANSMIT_NACK		0x30	/* Data byte transmitted in master mode , NACK received */
+#define I2C_ARBIT_LOST			0x38	/* Arbitration lost in address or data byte */
+#define I2C_ADDRESS_R_ACK		0x40	/* Address + Read bit transmitted, ACK received  */
+#define I2C_ADDRESS_R_NACK		0x48	/* Address + Read bit transmitted, NACK received  */
+#define I2C_DATA_RECEIVE_ACK		0x50	/* Data byte received in master mode, ACK transmitted  */
+#define I2C_DATA_RECEIVE_NACK		0x58	/* Data byte received in master mode, NACK transmitted*/
+#define I2C_ARBIT_LOST_ADDRESS		0x68	/* Arbitration lost in address  */
+#define I2C_GENERAL_CALL		0x70	/* General Call, ACK transmitted */
+#define I2C_NO_RELEVANT_INFO		0xF8	/* No relevant status information, IFLF=0 */
+
+#define I2C_READ_REG(reg)	        *(volatile u32*)(reg)
+#define I2C_WRITE_REG(reg, val)	        *(volatile u32*)(reg) = val
+#define RESET_REG_BITS(reg, val)        I2C_WRITE_REG(reg, I2C_READ_REG(reg) & ~(val))
+
+#undef	DEBUG_I2C
+//#define DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int control, status;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CFG_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 1 << n;	/* power = 2^(n) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+        I2C_WRITE_REG(I2C_SOFT_RESET, 0);
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	DP (puts ("set baudrate\n"));
+
+	I2C_WRITE_REG(I2C_STAT, (actualM << 3) | actualN);
+	I2C_WRITE_REG(I2C_CNTR, I2C_AAK | I2C_ENAB);
+
+	udelay (I2C_DELAY * 10);
+
+	DP (puts ("read control, baudrate\n"));
+
+	status = I2C_READ_REG(I2C_STAT);
+	control = I2C_READ_REG(I2C_CNTR);
+}
+
+static uchar i2c_start (void)
+{
+	unsigned int control, status;
+	int count = 0;
+
+	DP (puts ("i2c_start\n"));
+
+	/* Set the start bit */
+
+	control = I2C_READ_REG(I2C_CNTR);
+	control |= I2C_STA;	/* generate the I2C_START_BIT */
+	I2C_WRITE_REG(I2C_CNTR, control);
+
+	status = I2C_READ_REG(I2C_STAT);
+
+	count = 0;
+	while ((status & 0xff) != I2C_START_TRANSMIT) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+
+	return (0);
+}
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	I2C_WRITE_REG(I2C_DATA, data);
+	/* assert the address */
+	RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+	udelay (I2C_DELAY);
+
+	status = I2C_READ_REG(I2C_STAT);
+	count = 0;
+	while (((status & 0xff) != I2C_ADDRESS_R_ACK) && ((status & 0xff) != I2C_ADDRESS_W_ACK)) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status = 0;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		/* Get and return the data */
+
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY * 5);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_RECEIVE_ACK) {
+			udelay (I2C_DELAY);
+			if (count > 2) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return 0;
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		data = I2C_READ_REG(I2C_DATA);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+	}
+	RESET_REG_BITS (I2C_CNTR, I2C_AAK | I2C_IFLG);
+	while ((status & 0xff) != I2C_DATA_RECEIVE_NACK) {
+		udelay (I2C_DELAY);
+		if (count > 200) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+	I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/* stop */
+
+	return (0);
+}
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		temp = (unsigned int) (*temp_ptr);
+		I2C_WRITE_REG(I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_TRANSMIT_ACK) {
+			udelay (I2C_DELAY);
+			if (count > 20) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return (status);
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+	/* set the interrupt bit in the control register */
+	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG);
+	udelay (I2C_DELAY * 10);
+	return (0);
+}
+
+/* created this function to get the i2c_write() */
+/* function working properly. */
+/* function to write bytes out on the i2c bus */
+/* this is identical to the function i2c_write_data() */
+/* except that it requires a buffer that is an */
+/* unsigned character array.  You can't use */
+/* i2c_write_data() to send an array of unsigned characters */
+/* since the byte of interest ends up on the wrong end of the bus */
+/* aah, the joys of big endian versus little endian! */
+/* */
+/* returns 0 = success */
+/*         anything other than zero is failure */
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		I2C_WRITE_REG(I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY*2);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_TRANSMIT_ACK) {
+			udelay (I2C_DELAY*2);
+			if (count > 20) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return (status);
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+/*	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG | I2C_STP);
+	I2C_WRITE_REG(I2C_CNTR, I2C_STP); */
+	/* set the interrupt bit in the control register */
+	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG);
+	udelay (I2C_DELAY * 10);
+
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+/* initialize the table of address offset bytes */
+/* utilized for 2 byte address offsets */
+/* NOTE: the order is high byte first! */
+	table[1] = offset & 0xff;	/* low byte */
+	table[0] = offset / 0x100;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+uchar
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency again */
+
+	status = i2c_start ();
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction restart failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);	/* send the slave address */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Address not acknowledged: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not recieved: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+/* Function to set the I2C stop bit */
+void i2c_stop (void)
+{
+	I2C_WRITE_REG(I2C_CNTR, (0x1 << 4));
+}
+
+/* I2C write function */
+/* dev_addr = device address */
+/* offset = address offset */
+/* alen = length in bytes of the address offset */
+/* data = pointer to buffer to read data into */
+/* len = # of bytes to read */
+/* */
+/* returns 0 = succesful */
+/*         anything but zero is failure */
+uchar
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+	}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+/* function to determine if an I2C device is present */
+/* chip = device address of chip to check for */
+/* */
+/* returns 0 = sucessful, the device exists */
+/*         anything other than zero is failure, no device */
+int i2c_probe (uchar chip)
+{
+
+	/* We are just looking for an <ACK> back. */
+	/* To see if the device/chip is there */
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	i2c_status = I2C_READ_REG(I2C_STAT);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */

board/mindspeed/common/nand.c

diff --git a/board/mindspeed/common/nand.c b/board/mindspeed/common/nand.c
new file mode 100644
index 0000000..655b66d
--- /dev/null
+++ b/board/mindspeed/common/nand.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <config.h>
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+/* 
+ *	hardware specific access to control-lines
+*/
+void comcerto_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		SoC_gpio_set_1(SoC_gpio_mask(CFG_NAND_CLE_GPIO));
+		break;
+
+	case NAND_CTL_CLRCLE:
+		SoC_gpio_set_0(SoC_gpio_mask(CFG_NAND_CLE_GPIO));
+		break;
+
+	case NAND_CTL_SETALE:
+		SoC_gpio_set_1(SoC_gpio_mask(CFG_NAND_ALE_GPIO));
+		break;
+
+	case NAND_CTL_CLRALE:
+		SoC_gpio_set_0(SoC_gpio_mask(CFG_NAND_ALE_GPIO));
+		break;
+
+	case NAND_CTL_SETNCE:
+		SoC_gpio_set_0(SoC_gpio_mask(CFG_NAND_CE_GPIO));
+		break;
+
+	case NAND_CTL_CLRNCE:
+		SoC_gpio_set_1(SoC_gpio_mask(CFG_NAND_CE_GPIO));
+		break;
+	}
+}
+
+int comcerto_nand_ready(struct mtd_info *mtd)
+{
+	return SoC_gpio_read(SoC_gpio_mask(CFG_NAND_BR_GPIO)) ? 1 : 0;
+}
+
+void board_nand_init(struct nand_chip *nand)
+{
+	printf("board_nand_init nand->IO_ADDR_R =%x\n", nand->IO_ADDR_R);
+
+	nand->options = 0;
+	nand->eccmode = NAND_ECC_SOFT;
+	nand->hwcontrol = comcerto_nand_hwcontrol;
+	nand->dev_ready = comcerto_nand_ready;
+	nand->chip_delay = 20;
+}
+#else
+void board_nand_init(struct nand_chip *nand)
+{
+
+}
+#endif

board/mindspeed/common/norboot.S

diff --git a/board/mindspeed/common/norboot.S b/board/mindspeed/common/norboot.S
new file mode 100644
index 0000000..010dba5
--- /dev/null
+++ b/board/mindspeed/common/norboot.S
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This code is used to setup the boot CS to 16bit so that 
+the U-boot image can be read from NOR flash. It is compiled into
+a special section (and format) using the u-boot.lds linker script and
+u16_to_u8.c application */
+
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+.globl _start
+_start:
+	adr	r0, iram_code_start
+	ldr	r1, iram_addr
+	adr	r2, iram_code_end
+
+copy:
+	ldmia	r0!, {r3-r6}	/* copy from source address [r0]    */
+	stmia	r1!, {r3-r6}	/* copy to   target address [r1]    */
+	cmp	r0, r2		/* until source end address [r2]    */
+	ble	copy
+
+	/* Calculate return address, offset is multiplied by 2 */
+	adr     r0, _start
+	add     r1, r2, r2
+	sub     lr, r1, r0
+
+	/* Jump to internal RAM */
+	ldr	pc, iram_addr
+
+iram_addr:
+	.word	IRAM_BASEADDR
+
+
+	/* This codes runs from internal RAM and
+	   sets the boot chip select */
+iram_code_start:
+	ldr	r0, cs_reg
+	ldr	r1, cs_val
+	strh	r1, [r0]
+
+	/* Jump back to flash, now running in 16 bit */
+	mov	pc, lr
+
+cs_reg:
+	.word	SDC0_CSBOOT_CFG
+
+cs_val:
+	.word	0x081E
+
+iram_code_end:

board/mindspeed/common/u16_to_u8.c

diff --git a/board/mindspeed/common/u16_to_u8.c b/board/mindspeed/common/u16_to_u8.c
new file mode 100644
index 0000000..1552fab
--- /dev/null
+++ b/board/mindspeed/common/u16_to_u8.c
@@ -0,0 +1,46 @@
+#include <stdio.h>
+
+int main(int argc, char *argv[])
+{
+	FILE *fpi, *fpo;
+	unsigned char byte;
+	unsigned short word;
+	unsigned int nop; 
+	int count;
+
+	if (argc < 3)
+		goto err0;
+
+	fpi = fopen(argv[1], "r");
+	if (!fpi)
+		goto err0;
+
+	fpo = fopen(argv[2], "w");
+	if (!fpo)
+		goto err1;
+
+	count = 0;
+	while(fread(&byte, 1, sizeof(unsigned char), fpi) == 1) {
+		word = byte << 8 | byte;
+
+		fwrite(&word, 1, sizeof(unsigned short), fpo);
+		count++;
+	}
+
+	/* Align to the next 32bytes boundary with nops */
+	nop = 0xe1a00000;
+	count = (32 - (count * 2) % 32) / 4;
+	while (count--)
+		fwrite(&nop, 1, sizeof(unsigned int), fpo);
+
+	fclose(fpi);
+	fclose(fpo);
+
+	return 0;
+
+err1:
+	fclose(fpi);
+
+err0:
+	return 1;
+}

board/mindspeed/ferouter/Makefile

diff --git a/board/mindspeed/ferouter/Makefile b/board/mindspeed/ferouter/Makefile
new file mode 100644
index 0000000..606ed43
--- /dev/null
+++ b/board/mindspeed/ferouter/Makefile
@@ -0,0 +1,61 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o
+SOBJS	:= 
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mindspeed/ferouter/board.c

diff --git a/board/mindspeed/ferouter/board.c b/board/mindspeed/ferouter/board.c
new file mode 100644
index 0000000..73fe1f6
--- /dev/null
+++ b/board/mindspeed/ferouter/board.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+
+void board_map(flash_info_t *info, unsigned long addr)
+{
+	if ((addr >= (PHYS_FLASH1 + 0x800000)) && (addr < (PHYS_FLASH1 + 0x1000000))) {
+		SoC_gpio_set_0(SoC_gpio_mask(CFG_NOR_FLASH_A22_GPIO));
+	} else {
+		SoC_gpio_set_1(SoC_gpio_mask(CFG_NOR_FLASH_A22_GPIO));
+	}
+}
+#endif
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+static void nor_hw_init(void)
+{
+	/* set NOR_FLASH_A22_GPIO as output */
+	SoC_gpio_cfg(CFG_NOR_FLASH_A22_GPIO, GPIO_TYPE_OUTPUT);
+
+	/* Select upper 8MiB of flash device */
+	SoC_gpio_set_1(SoC_gpio_mask(CFG_NOR_FLASH_A22_GPIO));
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+	*(volatile u32 *)EX_CS0_SEG_REG = 0x7FF;
+#else
+	*(volatile u32 *)EX_CS0_SEG_REG = 0x3FF;
+#endif
+}
+
+void bsp_init(void)
+{
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	SoC_Check_Device();
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	SoC_PLL_init();
+
+	icache_enable();
+	SoC_mem_init(7);
+//	SoC_nand_init();
+}
+
+int board_init(void)
+{
+        /* Call nor_hw_init() only when low level initialization is not done */
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  != COMCERTO_PART_MAGIC)
+                nor_hw_init();
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	/* issue external reset via GPIO17 for 100 msec*/
+	*(volatile u32*) (GPIO_OE_REG) |= 0x20000;
+	*(volatile u32*)(GPIO_OUTPUT_REG) = 0x20000;	
+	udelay(10);
+	*(volatile u32*)(GPIO_OUTPUT_REG) = 0x0;	
+	udelay(100*1000);
+	*(volatile u32*)(GPIO_OUTPUT_REG) = 0x20000;	
+	udelay(100*1000);
+
+	/* enable SPI interface */
+	while (1)
+	{
+	   u32 temp;
+   	   temp = *(volatile u32 *)GPIO_IOCTRL_REG | GPIO_IOCTRL_SPI; 		// enable SPI bus
+   	   *(volatile u32 *)GPIO_LOCK_REG = 0x55555555; 			// remove lock
+   	   *(volatile u32 *)GPIO_IOCTRL_REG = temp;				// write to ctrl reg
+   	   if (*(volatile u32 *)GPIO_IOCTRL_REG == temp)
+		   break;
+	}
+
+       *(volatile u32 *)(GPIO_BASEADDR+0x34) = *(volatile u32 *)(GPIO_BASEADDR+0x34) | 0x4;	// set TDM FSync as output
+       *(volatile u32 *)CLKCORE_TDM_CLK_CNTRL = 0x832d70d7;		// set TDM clock freq to 2MHz
+       *(volatile u32 *)CLKCORE_FSYNC_CNTRL = 0x20FF0001;		// set FSync freq to 8KHz
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ddr_size();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 wr_dqs = 0; 
+	u8 dqs_out = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	wr_dqs = DENALI_WR_DQS; 
+	dqs_out = DENALI_DQS_OUT;
+	dqs_delay0 = DENALI_DQS_DELAY0;
+	dqs_delay1 = DENALI_DQS_DELAY1;
+	dqs_delay2 = DENALI_DQS_DELAY2;
+	dqs_delay3 = DENALI_DQS_DELAY3;
+
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+
+#ifdef NEW_DDR_TRAINING
+	printf("(NEW): ");
+#endif
+
+#else
+	printf("DDR default settings : ");
+#endif	
+
+	printf("wr_dqs 0x%x dqs_out 0x%x delay0 0x%x delay1 0x%x delay2 0x%x delay3 0x%x\n", wr_dqs,dqs_out,dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+#endif
+	return 0;
+}
+
+#endif

board/mindspeed/ferouter/config.mk

diff --git a/board/mindspeed/ferouter/config.mk b/board/mindspeed/ferouter/config.mk
new file mode 100644
index 0000000..99d1ed8
--- /dev/null
+++ b/board/mindspeed/ferouter/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x80100000

board/mindspeed/ferouter/reset.c

diff --git a/board/mindspeed/ferouter/reset.c b/board/mindspeed/ferouter/reset.c
new file mode 100644
index 0000000..f7ab9b8
--- /dev/null
+++ b/board/mindspeed/ferouter/reset.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bits.h>
+
+#define WAN_PHY_BIT	0
+#define LAN_PHY_BIT	1
+static u8 wanlan_reset=0;
+
+/*
+	On the router board, the lan and the wan phy are taken out of reset by the same GPIO pin (17)
+*/
+
+void reset_emac0_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=LAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= BIT17;
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~LAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= ~BIT17;
+		}
+	}
+
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=WAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= BIT17;
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~WAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= ~BIT17;
+		}
+	}
+}
+

board/mindspeed/ferouter/u-boot.lds

diff --git a/board/mindspeed/ferouter/u-boot.lds b/board/mindspeed/ferouter/u-boot.lds
new file mode 100644
index 0000000..895ea2a
--- /dev/null
+++ b/board/mindspeed/ferouter/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+
+	. = 0x0a000000;
+	__training_data_start = .;
+
+}

board/mindspeed/ipots48-515/Makefile

diff --git a/board/mindspeed/ipots48-515/Makefile b/board/mindspeed/ipots48-515/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/ipots48-515/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/ipots48-515/board.c

diff --git a/board/mindspeed/ipots48-515/board.c b/board/mindspeed/ipots48-515/board.c
new file mode 100644
index 0000000..29d2694
--- /dev/null
+++ b/board/mindspeed/ipots48-515/board.c
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if(CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0411,
+		.pwroncnt = 0x3415,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+
+	SoC_cs_cfg(SDR_CSSD0, CS_ENABLE, &cfg);
+
+	SoC_mem_divider_cfg(0x80000000, BELLOW_MEM_SDC1);
+	SoC_high_mem_cfg(SDR_CSSD0);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if(CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif

board/mindspeed/ipots48-515/config.mk

diff --git a/board/mindspeed/ipots48-515/config.mk b/board/mindspeed/ipots48-515/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/ipots48-515/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB

board/mindspeed/ipots48-515/u-boot.lds

diff --git a/board/mindspeed/ipots48-515/u-boot.lds b/board/mindspeed/ipots48-515/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/ipots48-515/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/ipots48-800/Makefile

diff --git a/board/mindspeed/ipots48-800/Makefile b/board/mindspeed/ipots48-800/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/ipots48-800/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/ipots48-800/board.c

diff --git a/board/mindspeed/ipots48-800/board.c b/board/mindspeed/ipots48-800/board.c
new file mode 100644
index 0000000..29d2694
--- /dev/null
+++ b/board/mindspeed/ipots48-800/board.c
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if(CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0411,
+		.pwroncnt = 0x3415,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+
+	SoC_cs_cfg(SDR_CSSD0, CS_ENABLE, &cfg);
+
+	SoC_mem_divider_cfg(0x80000000, BELLOW_MEM_SDC1);
+	SoC_high_mem_cfg(SDR_CSSD0);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if(CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif

board/mindspeed/ipots48-800/config.mk

diff --git a/board/mindspeed/ipots48-800/config.mk b/board/mindspeed/ipots48-800/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/ipots48-800/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB

board/mindspeed/ipots48-800/u-boot.lds

diff --git a/board/mindspeed/ipots48-800/u-boot.lds b/board/mindspeed/ipots48-800/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/ipots48-800/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/malindi/Makefile

diff --git a/board/mindspeed/malindi/Makefile b/board/mindspeed/malindi/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/malindi/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/malindi/board.c

diff --git a/board/mindspeed/malindi/board.c b/board/mindspeed/malindi/board.c
new file mode 100644
index 0000000..7f361e9
--- /dev/null
+++ b/board/mindspeed/malindi/board.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP1, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 4 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+//	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif

board/mindspeed/malindi/config.mk

diff --git a/board/mindspeed/malindi/config.mk b/board/mindspeed/malindi/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/malindi/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB

board/mindspeed/malindi/u-boot.lds

diff --git a/board/mindspeed/malindi/u-boot.lds b/board/mindspeed/malindi/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/malindi/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/megamombasa515_256M/Makefile

diff --git a/board/mindspeed/megamombasa515_256M/Makefile b/board/mindspeed/megamombasa515_256M/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/megamombasa515_256M/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/megamombasa515_256M/board.c

diff --git a/board/mindspeed/megamombasa515_256M/board.c b/board/mindspeed/megamombasa515_256M/board.c
new file mode 100644
index 0000000..099acd1
--- /dev/null
+++ b/board/mindspeed/megamombasa515_256M/board.c
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0411,
+		.pwroncnt = 0x3415,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+
+	cfg.baseaddr = PHYS_SDRAM;
+	cfg.size = PHYS_SDRAM_SIZE;
+
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	cfg.baseaddr = PHYS_SDRAM1;
+	cfg.size = PHYS_SDRAM1_SIZE;
+
+	SoC_cs_cfg(SDR_CSSD0, CS_ENABLE, &cfg);
+	
+	SoC_mem_divider_cfg(PHYS_SDRAM1, BELLOW_MEM_SDC0);
+	SoC_high_mem_cfg(EXP_CSSD0);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM1;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM1_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif

board/mindspeed/megamombasa515_256M/config.mk

diff --git a/board/mindspeed/megamombasa515_256M/config.mk b/board/mindspeed/megamombasa515_256M/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/megamombasa515_256M/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB

board/mindspeed/megamombasa515_256M/u-boot.lds

diff --git a/board/mindspeed/megamombasa515_256M/u-boot.lds b/board/mindspeed/megamombasa515_256M/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/megamombasa515_256M/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/megamombasa515_sdc1/Makefile

diff --git a/board/mindspeed/megamombasa515_sdc1/Makefile b/board/mindspeed/megamombasa515_sdc1/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/megamombasa515_sdc1/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/megamombasa515_sdc1/board.c

diff --git a/board/mindspeed/megamombasa515_sdc1/board.c b/board/mindspeed/megamombasa515_sdc1/board.c
new file mode 100644
index 0000000..9e85130
--- /dev/null
+++ b/board/mindspeed/megamombasa515_sdc1/board.c
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0411,
+		.pwroncnt = 0x3415,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+
+	SoC_cs_cfg(SDR_CSSD0, CS_ENABLE, &cfg);
+	
+	SoC_mem_divider_cfg(0x80000000, BELLOW_MEM_SDC1);
+	SoC_high_mem_cfg(SDR_CSSD0);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif

board/mindspeed/megamombasa515_sdc1/config.mk

diff --git a/board/mindspeed/megamombasa515_sdc1/config.mk b/board/mindspeed/megamombasa515_sdc1/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/megamombasa515_sdc1/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB

board/mindspeed/megamombasa515_sdc1/u-boot.lds

diff --git a/board/mindspeed/megamombasa515_sdc1/u-boot.lds b/board/mindspeed/megamombasa515_sdc1/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/megamombasa515_sdc1/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/moca/Makefile

diff --git a/board/mindspeed/moca/Makefile b/board/mindspeed/moca/Makefile
new file mode 100644
index 0000000..d45c7ad
--- /dev/null
+++ b/board/mindspeed/moca/Makefile
@@ -0,0 +1,61 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o ../common/i2c.o
+SOBJS	:= 
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mindspeed/moca/board.c

diff --git a/board/mindspeed/moca/board.c b/board/mindspeed/moca/board.c
new file mode 100644
index 0000000..4ed75e1
--- /dev/null
+++ b/board/mindspeed/moca/board.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+void board_map(flash_info_t *info, unsigned long addr)
+{
+	if ((addr >= (PHYS_FLASH1 + 0x800000)) && (addr < (PHYS_FLASH1 + 0x1000000))) {
+		SoC_gpio_set_0(SoC_gpio_mask(5));
+	} else {
+		SoC_gpio_set_1(SoC_gpio_mask(5));
+	}
+}
+#endif
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+static void nor_hw_init(void)
+{
+	/* set GPIO5 as output */
+	SoC_gpio_cfg(5, GPIO_TYPE_OUTPUT);
+
+	/* Select upper 8MiB of flash device */
+	SoC_gpio_set_1(SoC_gpio_mask(5));
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+	*(volatile u32 *)EX_CS0_SEG_REG = 0x7FF;
+#else
+	*(volatile u32 *)EX_CS0_SEG_REG = 0x3FF;
+#endif
+
+        /* adjust EXP bus configuration registers */
+        *(volatile u32 *)EX_CLOCK_DIV_REG = 0x5;
+        *(volatile u32 *)EX_CS0_TMG1_REG = 0x03034007;
+        *(volatile u32 *)EX_CS0_TMG2_REG = 0x04040502;
+
+}
+
+void bsp_init(void)
+{
+	SoC_Check_Device();
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	SoC_PLL_init();
+
+	icache_enable();
+	SoC_mem_init(BOARD_CFG_MOCA);
+}
+
+int board_init(void)
+{
+        u32 i, led_mask;
+    
+	nor_hw_init();
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+        /* force WAN Select (GPIO6) to GigE PHY, not MoCA */
+	SoC_gpio_cfg(6, GPIO_TYPE_OUTPUT);
+	SoC_gpio_set_1(SoC_gpio_mask(6));
+        
+        /* configure MoCA PHY reset lines for as GPIO outputs, hold in reset */
+       	SoC_gpio_cfg(22, GPIO_TYPE_OUTPUT);
+       	SoC_gpio_cfg(23, GPIO_TYPE_OUTPUT);
+        SoC_gpio_set_0(SoC_gpio_mask(23) | SoC_gpio_mask(22));
+        
+        /* force external reset via GPIO17 for 100msec */
+       	SoC_gpio_cfg(17, GPIO_TYPE_OUTPUT);
+	SoC_gpio_set_1(SoC_gpio_mask(17));
+        udelay(10);
+	SoC_gpio_set_0(SoC_gpio_mask(17));
+        udelay(100*1000);
+	SoC_gpio_set_1(SoC_gpio_mask(17));
+        udelay(100*1000);
+
+	/* enable I2C interface */
+	while (1)
+	{
+	   u32 temp;
+   	   temp = *(volatile u32 *)GPIO_IOCTRL_REG | GPIO_IOCTRL_I2C; 		// enable I2C bus
+   	   *(volatile u32 *)GPIO_LOCK_REG = 0x55555555; 			// remove lock
+   	   *(volatile u32 *)GPIO_IOCTRL_REG = temp;				// write to ctrl reg
+   	   if (*(volatile u32 *)GPIO_IOCTRL_REG == temp)
+		   break;
+	}
+
+        /* configure WPS and config-reset buttons as inputs */
+        SoC_gpio_cfg(3, GPIO_TYPE_INPUT);
+        SoC_gpio_cfg(4, GPIO_TYPE_INPUT);
+
+        /* configure GPIO-driven LEDs as outputs, flash them */
+       	SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+       	SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+       	SoC_gpio_cfg(15, GPIO_TYPE_OUTPUT);
+       	SoC_gpio_cfg(16, GPIO_TYPE_OUTPUT);
+        led_mask = SoC_gpio_mask(29) | SoC_gpio_mask(30) | SoC_gpio_mask(15) | SoC_gpio_mask(16);
+        for (i = 0; i < 10; i++) {
+            if (i%2) {
+                SoC_gpio_set_1(led_mask);
+            } else {
+                SoC_gpio_set_0(led_mask);
+            }
+            udelay(100*1000);
+        }
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ddr_size();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 wr_dqs = 0; 
+	u8 dqs_out = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	wr_dqs = DENALI_WR_DQS; 
+	dqs_out = DENALI_DQS_OUT;
+	dqs_delay0 = DENALI_DQS_DELAY0;
+	dqs_delay1 = DENALI_DQS_DELAY1;
+	dqs_delay2 = DENALI_DQS_DELAY2;
+	dqs_delay3 = DENALI_DQS_DELAY3;
+	printf("DDR Training : ");
+	printf("wr_dqs 0x%x dqs_out 0x%x delay0 0x%x delay1 0x%x delay2 0x%x delay3 0x%x\n", wr_dqs,dqs_out,dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+#endif
+
+	return 0;
+}
+
+#endif

board/mindspeed/moca/config.mk

diff --git a/board/mindspeed/moca/config.mk b/board/mindspeed/moca/config.mk
new file mode 100644
index 0000000..99d1ed8
--- /dev/null
+++ b/board/mindspeed/moca/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x80100000

board/mindspeed/moca/reset.c

diff --git a/board/mindspeed/moca/reset.c b/board/mindspeed/moca/reset.c
new file mode 100644
index 0000000..6192830
--- /dev/null
+++ b/board/mindspeed/moca/reset.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bits.h>
+
+#define WAN_PHY_BIT	0
+#define LAN_PHY_BIT	1
+static u8 wanlan_reset=0;
+
+/*
+	On the packet-iad board, the lan and the wan phy are taken out of reset by the same GPIO pin (17)
+*/
+
+void reset_emac0_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=LAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= BIT17;
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~LAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= ~BIT17;
+		}
+	}
+
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=WAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= BIT17;
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~WAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= ~BIT17;
+		}
+	}
+}
+

board/mindspeed/moca/u-boot.lds

diff --git a/board/mindspeed/moca/u-boot.lds b/board/mindspeed/moca/u-boot.lds
new file mode 100644
index 0000000..895ea2a
--- /dev/null
+++ b/board/mindspeed/moca/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+
+	. = 0x0a000000;
+	__training_data_start = .;
+
+}

board/mindspeed/nairobi/Makefile

diff --git a/board/mindspeed/nairobi/Makefile b/board/mindspeed/nairobi/Makefile
new file mode 100644
index 0000000..403d839
--- /dev/null
+++ b/board/mindspeed/nairobi/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o
+SOBJS	:= 
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/nairobi/board.c

diff --git a/board/mindspeed/nairobi/board.c b/board/mindspeed/nairobi/board.c
new file mode 100644
index 0000000..07aa8b8
--- /dev/null
+++ b/board/mindspeed/nairobi/board.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_ASYNC, 372000000, CFG_HZ_CLOCK);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif

board/mindspeed/nairobi/config.mk

diff --git a/board/mindspeed/nairobi/config.mk b/board/mindspeed/nairobi/config.mk
new file mode 100644
index 0000000..242dab7
--- /dev/null
+++ b/board/mindspeed/nairobi/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x00100000

board/mindspeed/nairobi/u-boot.lds

diff --git a/board/mindspeed/nairobi/u-boot.lds b/board/mindspeed/nairobi/u-boot.lds
new file mode 100644
index 0000000..db5a529
--- /dev/null
+++ b/board/mindspeed/nairobi/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/packet-iad/Makefile

diff --git a/board/mindspeed/packet-iad/Makefile b/board/mindspeed/packet-iad/Makefile
new file mode 100644
index 0000000..0145d72
--- /dev/null
+++ b/board/mindspeed/packet-iad/Makefile
@@ -0,0 +1,62 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o ../common/i2c.o
+SOBJS	:= 
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mindspeed/packet-iad/board.c

diff --git a/board/mindspeed/packet-iad/board.c b/board/mindspeed/packet-iad/board.c
new file mode 100644
index 0000000..4b02884
--- /dev/null
+++ b/board/mindspeed/packet-iad/board.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+void board_map(flash_info_t *info, unsigned long addr)
+{
+	if ((addr >= (PHYS_FLASH1 + 0x800000)) && (addr < (PHYS_FLASH1 + 0x1000000))) {
+		SoC_gpio_set_0(SoC_gpio_mask(5));
+	} else {
+		SoC_gpio_set_1(SoC_gpio_mask(5));
+	}
+}
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+static void nand_hw_init(void)
+{
+	/* set GPIO5 as output */
+	SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(31, GPIO_TYPE_OUTPUT);
+
+}
+#endif
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+static void nor_hw_init(void)
+{
+	/* set GPIO5 as output */
+	SoC_gpio_cfg(5, GPIO_TYPE_OUTPUT);
+
+	/* Select upper 8MiB of flash device */
+	SoC_gpio_set_1(SoC_gpio_mask(5));
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0x7FF);
+#else
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0x3FF);
+#endif
+
+        /* adjust EXP bus configuration registers */
+        *(volatile u32 *)EX_CLOCK_DIV_REG = __cpu_to_le32(0x5);
+        *(volatile u32 *)EX_CS0_TMG1_REG = __cpu_to_le32(0x03034007);
+        *(volatile u32 *)EX_CS0_TMG2_REG = __cpu_to_le32(0x04040502);
+
+        return;
+}
+
+void bsp_init(void)
+{
+       /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	SoC_Check_Device();
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	SoC_PLL_init();
+
+	icache_enable();
+#if defined(CONFIG_COMCERTO_50)
+	SoC_mem_init(9);
+#else
+	SoC_mem_init(4);
+#endif
+//	SoC_nand_init();
+}
+
+int board_init(void)
+{
+        /* Call nor_hw_init() only when low level initialization is not done */
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  != COMCERTO_PART_MAGIC)
+                nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+       nand_hw_init();
+#endif
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	/* enable I2C interface */
+	while (1)
+	{
+	   u32 temp;
+   	   temp = *(volatile u32 *)GPIO_IOCTRL_REG | __cpu_to_le32(GPIO_IOCTRL_I2C); 		// enable I2C bus
+   	   *(volatile u32 *)GPIO_LOCK_REG = __cpu_to_le32(0x55555555); 			// remove lock
+   	   *(volatile u32 *)GPIO_IOCTRL_REG = temp;				// write to ctrl reg
+   	   if (*(volatile u32 *)GPIO_IOCTRL_REG == temp)
+		   break;
+	}
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ddr_size();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 wr_dqs = 0; 
+	u8 dqs_out = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	wr_dqs = DENALI_WR_DQS; 
+	dqs_out = DENALI_DQS_OUT;
+	dqs_delay0 = DENALI_DQS_DELAY0;
+	dqs_delay1 = DENALI_DQS_DELAY1;
+	dqs_delay2 = DENALI_DQS_DELAY2;
+	dqs_delay3 = DENALI_DQS_DELAY3;
+
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+
+#ifdef NEW_DDR_TRAINING
+	printf("(NEW): ");
+#endif
+
+#else
+	printf("DDR default settings : ");
+#endif
+	printf("wr_dqs 0x%x dqs_out 0x%x delay0 0x%x delay1 0x%x delay2 0x%x delay3 0x%x\n", wr_dqs,dqs_out,dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+#endif
+
+	return 0;
+}
+
+#endif

board/mindspeed/packet-iad/config.mk

diff --git a/board/mindspeed/packet-iad/config.mk b/board/mindspeed/packet-iad/config.mk
new file mode 100644
index 0000000..99d1ed8
--- /dev/null
+++ b/board/mindspeed/packet-iad/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x80100000

board/mindspeed/packet-iad/reset.c

diff --git a/board/mindspeed/packet-iad/reset.c b/board/mindspeed/packet-iad/reset.c
new file mode 100644
index 0000000..6192830
--- /dev/null
+++ b/board/mindspeed/packet-iad/reset.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bits.h>
+
+#define WAN_PHY_BIT	0
+#define LAN_PHY_BIT	1
+static u8 wanlan_reset=0;
+
+/*
+	On the packet-iad board, the lan and the wan phy are taken out of reset by the same GPIO pin (17)
+*/
+
+void reset_emac0_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=LAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= BIT17;
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~LAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= ~BIT17;
+		}
+	}
+
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=WAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= BIT17;
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~WAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= ~BIT17;
+		}
+	}
+}
+

board/mindspeed/packet-iad/u-boot.lds

diff --git a/board/mindspeed/packet-iad/u-boot.lds b/board/mindspeed/packet-iad/u-boot.lds
new file mode 100644
index 0000000..895ea2a
--- /dev/null
+++ b/board/mindspeed/packet-iad/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+
+	. = 0x0a000000;
+	__training_data_start = .;
+
+}

board/mindspeed/router/Makefile

diff --git a/board/mindspeed/router/Makefile b/board/mindspeed/router/Makefile
new file mode 100644
index 0000000..d2a8bd5
--- /dev/null
+++ b/board/mindspeed/router/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o ../common/i2c.o
+SOBJS	:= 
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/mindspeed/router/board.c

diff --git a/board/mindspeed/router/board.c b/board/mindspeed/router/board.c
new file mode 100644
index 0000000..8483d6e
--- /dev/null
+++ b/board/mindspeed/router/board.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+void board_map(flash_info_t *info, unsigned long addr)
+{
+	if ((addr >= (PHYS_FLASH1 + 0x800000)) && (addr < (PHYS_FLASH1 + 0x1000000))) {
+		SoC_gpio_set_0(SoC_gpio_mask(5));
+	} else {
+		SoC_gpio_set_1(SoC_gpio_mask(5));
+	}
+}
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+static void nand_hw_init(void)
+{
+	/* set GPIO5 as output */
+	SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(31, GPIO_TYPE_OUTPUT);
+
+}
+#endif
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+static void nor_hw_init(void)
+{
+	/* set GPIO5 as output */
+	SoC_gpio_cfg(5, GPIO_TYPE_OUTPUT);
+
+	/* Select upper 8MiB of flash device */
+	SoC_gpio_set_1(SoC_gpio_mask(5));
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0x7FF);
+#else
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0x3FF);
+#endif
+}
+
+void bsp_init(void)
+{
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	SoC_Check_Device();
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	SoC_PLL_init();
+
+	icache_enable();
+#if defined(CONFIG_COMCERTO_50)
+	SoC_mem_init(10); /* for C50 */
+#else
+	SoC_mem_init(5); /* for C100 */
+#endif
+//	SoC_nand_init();
+}
+
+int board_init(void)
+{
+        /* Call nor_hw_init() only when low level initialization is not done */
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  != COMCERTO_PART_MAGIC)
+                nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+       nand_hw_init();
+#endif
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+	/* enable I2C interface */
+	while (1)
+	{
+	   u32 temp;
+   	   temp = *(volatile u32 *)GPIO_IOCTRL_REG |  __cpu_to_le32(GPIO_IOCTRL_I2C); 		// enable I2C bus
+   	   *(volatile u32 *)GPIO_LOCK_REG =  __cpu_to_le32(0x55555555); 			// remove lock
+   	   *(volatile u32 *)GPIO_IOCTRL_REG = temp;				// write to ctrl reg
+   	   if (*(volatile u32 *)GPIO_IOCTRL_REG == temp)
+		   break;
+	}
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ddr_size();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 wr_dqs = 0; 
+	u8 dqs_out = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	wr_dqs = DENALI_WR_DQS; 
+	dqs_out = DENALI_DQS_OUT;
+	dqs_delay0 = DENALI_DQS_DELAY0;
+	dqs_delay1 = DENALI_DQS_DELAY1;
+	dqs_delay2 = DENALI_DQS_DELAY2;
+	dqs_delay3 = DENALI_DQS_DELAY3;
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+
+#ifdef NEW_DDR_TRAINING
+	printf("(NEW): ");
+#endif
+
+#else
+	printf("DDR default settings : ");
+#endif	
+	printf("wr_dqs 0x%x dqs_out 0x%x delay0 0x%x delay1 0x%x delay2 0x%x delay3 0x%x\n", wr_dqs,dqs_out,dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+#endif
+	return 0;
+}
+
+#endif

board/mindspeed/router/config.mk

diff --git a/board/mindspeed/router/config.mk b/board/mindspeed/router/config.mk
new file mode 100644
index 0000000..99d1ed8
--- /dev/null
+++ b/board/mindspeed/router/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x80100000

board/mindspeed/router/reset.c

diff --git a/board/mindspeed/router/reset.c b/board/mindspeed/router/reset.c
new file mode 100644
index 0000000..be5d916
--- /dev/null
+++ b/board/mindspeed/router/reset.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bits.h>
+
+#define WAN_PHY_BIT	0
+#define LAN_PHY_BIT	1
+static u8 wanlan_reset=0;
+
+/*
+	On the router board, the lan and the wan phy are taken out of reset by the same GPIO pin (17)
+*/
+
+void reset_emac0_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=LAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= __cpu_to_le32(BIT17);
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= __cpu_to_le32(BIT17);
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~LAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= __cpu_to_le32(BIT17);
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= __cpu_to_le32(~BIT17);
+		}
+	}
+
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=WAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= __cpu_to_le32(BIT17);
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= __cpu_to_le32(BIT17);
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~WAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= __cpu_to_le32(BIT17);
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= __cpu_to_le32(~BIT17);
+		}
+	}
+}
+

board/mindspeed/router/u-boot.lds

diff --git a/board/mindspeed/router/u-boot.lds b/board/mindspeed/router/u-boot.lds
new file mode 100644
index 0000000..895ea2a
--- /dev/null
+++ b/board/mindspeed/router/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+
+	. = 0x0a000000;
+	__training_data_start = .;
+
+}

board/mindspeed/supermombasa910/Makefile

diff --git a/board/mindspeed/supermombasa910/Makefile b/board/mindspeed/supermombasa910/Makefile
new file mode 100644
index 0000000..f99546f
--- /dev/null
+++ b/board/mindspeed/supermombasa910/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o mii.o reset.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o
+SOBJS	:=  
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all:	$(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/supermombasa910/board.c

diff --git a/board/mindspeed/supermombasa910/board.c b/board/mindspeed/supermombasa910/board.c
new file mode 100644
index 0000000..567644f
--- /dev/null
+++ b/board/mindspeed/supermombasa910/board.c
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void SoC_PLL_init(void);
+extern void SoC_mem_init(void);
+//extern void SoC_mem_init(int controller, int base, int length);
+extern void SoC_flash_init(void);
+extern void SoC_nand_init(void);
+
+void bsp_init(void)
+{
+	SoC_Check_Device();
+
+	SoC_PLL_init();
+	//SoC_mem_init(0, PHYS_SDRAM, /*PHYS_SDRAM_SIZE/0x100000*/128);
+	SoC_mem_init();
+	SoC_flash_init();
+	SoC_nand_init();
+	
+	icache_enable();
+}
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+  printf("Reserve MSP memory\n");
+  gd->bd->bi_dram[0].start += (u32)MSP_MEMORY_RESERVED_SIZE;
+  gd->bd->bi_dram[0].size -= (u32)MSP_MEMORY_RESERVED_SIZE;
+  return 0;
+}
+#endif

board/mindspeed/supermombasa910/config.mk

diff --git a/board/mindspeed/supermombasa910/config.mk b/board/mindspeed/supermombasa910/config.mk
new file mode 100644
index 0000000..242dab7
--- /dev/null
+++ b/board/mindspeed/supermombasa910/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x00100000

board/mindspeed/supermombasa910/mii.c

diff --git a/board/mindspeed/supermombasa910/mii.c b/board/mindspeed/supermombasa910/mii.c
new file mode 100644
index 0000000..c94a99d
--- /dev/null
+++ b/board/mindspeed/supermombasa910/mii.c
@@ -0,0 +1,29 @@
+#include <common.h>
+
+#if defined(CONFIG_MII) && (CONFIG_COMMANDS & CFG_CMD_MII)
+extern u16 MDIO_Handle_Read(u16 preamble_sup, u16 phy_addr, u16 reg_addr);
+extern u16 MDIO_Handle_Write(u16 preamble_sup, u16 phy_addr, u16 reg_addr, u16 md_data);
+
+int  comcerto_miiphy_read(char *devname, unsigned char addr,
+		unsigned char reg, unsigned short * value)
+{
+	*value = MDIO_Handle_Read(0, 0, reg);
+	return 0;
+}
+
+int  comcerto_miiphy_write(char *devname, unsigned char addr,
+		unsigned char reg, unsigned short value)
+{
+	MDIO_Handle_Write(0, 0, reg, value);
+	return 0;
+}
+
+#endif	/* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
+
+int comcerto_miiphy_initialize(bd_t *bis)
+{
+#if defined(CONFIG_MII) && (CONFIG_COMMANDS & CFG_CMD_MII)
+	miiphy_register("Comcerto phy", comcerto_miiphy_read, comcerto_miiphy_write);
+#endif
+	return 0;
+}

board/mindspeed/supermombasa910/reset.c

diff --git a/board/mindspeed/supermombasa910/reset.c b/board/mindspeed/supermombasa910/reset.c
new file mode 100644
index 0000000..f3de85c
--- /dev/null
+++ b/board/mindspeed/supermombasa910/reset.c
@@ -0,0 +1,15 @@
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+void reset_emac0_phy(u32 enable)
+{
+	//nothing to do. There is no reset on the supermombassa910 board for the lan interface
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	//nothing to do. There is no reset on the supermombassa910 board for the wan interface
+}
+
+

board/mindspeed/supermombasa910/u-boot.lds

diff --git a/board/mindspeed/supermombasa910/u-boot.lds b/board/mindspeed/supermombasa910/u-boot.lds
new file mode 100644
index 0000000..1f86607
--- /dev/null
+++ b/board/mindspeed/supermombasa910/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/tsavo515/Makefile

diff --git a/board/mindspeed/tsavo515/Makefile b/board/mindspeed/tsavo515/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/tsavo515/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/tsavo515/board.c

diff --git a/board/mindspeed/tsavo515/board.c b/board/mindspeed/tsavo515/board.c
new file mode 100644
index 0000000..69a1810
--- /dev/null
+++ b/board/mindspeed/tsavo515/board.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif

board/mindspeed/tsavo515/config.mk

diff --git a/board/mindspeed/tsavo515/config.mk b/board/mindspeed/tsavo515/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/tsavo515/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB

board/mindspeed/tsavo515/u-boot.lds

diff --git a/board/mindspeed/tsavo515/u-boot.lds b/board/mindspeed/tsavo515/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/tsavo515/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/tsavo515_nor/Makefile

diff --git a/board/mindspeed/tsavo515_nor/Makefile b/board/mindspeed/tsavo515_nor/Makefile
new file mode 100644
index 0000000..b3fc1e5
--- /dev/null
+++ b/board/mindspeed/tsavo515_nor/Makefile
@@ -0,0 +1,65 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB) ../common/u16_to_u8.bin norboot8.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+norboot8.o: ../common/norboot.o
+	$(LD) -Ttext 0x11000000 $< -o norboot.o
+	$(OBJCOPY) -O binary norboot.o norboot16.bin
+	../common/u16_to_u8.bin norboot16.bin norboot8.bin
+	$(OBJCOPY) -Barm -I binary -O elf32-littlearm norboot8.bin $@
+	$(RM) norboot16.bin norboot8.bin
+
+../common/u16_to_u8.bin: ../common/u16_to_u8.c
+	$(HOSTCC) -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) norboot8.o ../common/u16_to_u8.bin ../common/norboot.o
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/tsavo515_nor/board.c

diff --git a/board/mindspeed/tsavo515_nor/board.c b/board/mindspeed/tsavo515_nor/board.c
new file mode 100644
index 0000000..0cdcc18
--- /dev/null
+++ b/board/mindspeed/tsavo515_nor/board.c
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif

board/mindspeed/tsavo515_nor/config.mk

diff --git a/board/mindspeed/tsavo515_nor/config.mk b/board/mindspeed/tsavo515_nor/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/tsavo515_nor/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB

board/mindspeed/tsavo515_nor/u-boot.lds

diff --git a/board/mindspeed/tsavo515_nor/u-boot.lds b/board/mindspeed/tsavo515_nor/u-boot.lds
new file mode 100644
index 0000000..4d51168
--- /dev/null
+++ b/board/mindspeed/tsavo515_nor/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		board/mindspeed/tsavo515_nor/norboot8.o (.data)
+
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/tsavo530/Makefile

diff --git a/board/mindspeed/tsavo530/Makefile b/board/mindspeed/tsavo530/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/tsavo530/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/tsavo530/board.c

diff --git a/board/mindspeed/tsavo530/board.c b/board/mindspeed/tsavo530/board.c
new file mode 100644
index 0000000..9bb02a3
--- /dev/null
+++ b/board/mindspeed/tsavo530/board.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 250000000, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 4 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_CS_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif

board/mindspeed/tsavo530/config.mk

diff --git a/board/mindspeed/tsavo530/config.mk b/board/mindspeed/tsavo530/config.mk
new file mode 100644
index 0000000..091ad4c
--- /dev/null
+++ b/board/mindspeed/tsavo530/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x03E00000	# 62MiB

board/mindspeed/tsavo530/u-boot.lds

diff --git a/board/mindspeed/tsavo530/u-boot.lds b/board/mindspeed/tsavo530/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/tsavo530/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/tsavo530_nor/Makefile

diff --git a/board/mindspeed/tsavo530_nor/Makefile b/board/mindspeed/tsavo530_nor/Makefile
new file mode 100644
index 0000000..b3fc1e5
--- /dev/null
+++ b/board/mindspeed/tsavo530_nor/Makefile
@@ -0,0 +1,65 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB) ../common/u16_to_u8.bin norboot8.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+norboot8.o: ../common/norboot.o
+	$(LD) -Ttext 0x11000000 $< -o norboot.o
+	$(OBJCOPY) -O binary norboot.o norboot16.bin
+	../common/u16_to_u8.bin norboot16.bin norboot8.bin
+	$(OBJCOPY) -Barm -I binary -O elf32-littlearm norboot8.bin $@
+	$(RM) norboot16.bin norboot8.bin
+
+../common/u16_to_u8.bin: ../common/u16_to_u8.c
+	$(HOSTCC) -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) norboot8.o ../common/u16_to_u8.bin ../common/norboot.o
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/tsavo530_nor/board.c

diff --git a/board/mindspeed/tsavo530_nor/board.c b/board/mindspeed/tsavo530_nor/board.c
new file mode 100644
index 0000000..4a09a41
--- /dev/null
+++ b/board/mindspeed/tsavo530_nor/board.c
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 250000000, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif

board/mindspeed/tsavo530_nor/config.mk

diff --git a/board/mindspeed/tsavo530_nor/config.mk b/board/mindspeed/tsavo530_nor/config.mk
new file mode 100644
index 0000000..091ad4c
--- /dev/null
+++ b/board/mindspeed/tsavo530_nor/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x03E00000	# 62MiB

board/mindspeed/tsavo530_nor/u-boot.lds

diff --git a/board/mindspeed/tsavo530_nor/u-boot.lds b/board/mindspeed/tsavo530_nor/u-boot.lds
new file mode 100644
index 0000000..8b1e558
--- /dev/null
+++ b/board/mindspeed/tsavo530_nor/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		board/mindspeed/tsavo530_nor/norboot8.o (.data)
+
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/udev515/Makefile

diff --git a/board/mindspeed/udev515/Makefile b/board/mindspeed/udev515/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/udev515/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/udev515/board.c

diff --git a/board/mindspeed/udev515/board.c b/board/mindspeed/udev515/board.c
new file mode 100644
index 0000000..a7ed641
--- /dev/null
+++ b/board/mindspeed/udev515/board.c
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void exp_csp0_init (void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+}
+
+
+static void nand_hw_init(void)
+{
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+extern spi_chipsel_type spi_chipsel[];
+
+static void ethswitch_init(void)
+{
+	uchar dout[3];
+	int rc;
+
+	*(volatile u8 *)CPLD_RESET_CTRL &= ~ESWITCH_OUT_OF_RESET;	/* reset ESwitch */
+	*(volatile u8 *)CPLD_INTMASK |= ESWITCH_IRQMASK;
+	*(volatile u8 *)CPLD_RESET_CTRL |= ESWITCH_OUT_OF_RESET;	/* Take ESwitch out of reset */
+
+	spi_hw_init();
+
+	/* initialize the SPI write buffer */
+	dout[0] = 0x02;				/* Eswitch write command */
+	dout[1] = 1;				/* address */
+	dout[2] = 1;				/* value */
+	
+	rc = spi_xfer(spi_chipsel[2], 24, dout, NULL);
+	if (rc)
+		printf(" ethswitch_init: can't initialize the SPI bus \n", rc);
+}
+
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	/* CPLD, FPGA and NAND chip select */
+	exp_csp0_init();
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+	ethswitch_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif

board/mindspeed/udev515/config.mk

diff --git a/board/mindspeed/udev515/config.mk b/board/mindspeed/udev515/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/udev515/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB

board/mindspeed/udev515/u-boot.lds

diff --git a/board/mindspeed/udev515/u-boot.lds b/board/mindspeed/udev515/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/udev515/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/mindspeed/udev800/Makefile

diff --git a/board/mindspeed/udev800/Makefile b/board/mindspeed/udev800/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/udev800/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/mindspeed/udev800/board.c

diff --git a/board/mindspeed/udev800/board.c b/board/mindspeed/udev800/board.c
new file mode 100644
index 0000000..a7ed641
--- /dev/null
+++ b/board/mindspeed/udev800/board.c
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void exp_csp0_init (void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+}
+
+
+static void nand_hw_init(void)
+{
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+extern spi_chipsel_type spi_chipsel[];
+
+static void ethswitch_init(void)
+{
+	uchar dout[3];
+	int rc;
+
+	*(volatile u8 *)CPLD_RESET_CTRL &= ~ESWITCH_OUT_OF_RESET;	/* reset ESwitch */
+	*(volatile u8 *)CPLD_INTMASK |= ESWITCH_IRQMASK;
+	*(volatile u8 *)CPLD_RESET_CTRL |= ESWITCH_OUT_OF_RESET;	/* Take ESwitch out of reset */
+
+	spi_hw_init();
+
+	/* initialize the SPI write buffer */
+	dout[0] = 0x02;				/* Eswitch write command */
+	dout[1] = 1;				/* address */
+	dout[2] = 1;				/* value */
+	
+	rc = spi_xfer(spi_chipsel[2], 24, dout, NULL);
+	if (rc)
+		printf(" ethswitch_init: can't initialize the SPI bus \n", rc);
+}
+
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	/* CPLD, FPGA and NAND chip select */
+	exp_csp0_init();
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+	ethswitch_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif

board/mindspeed/udev800/config.mk

diff --git a/board/mindspeed/udev800/config.mk b/board/mindspeed/udev800/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/udev800/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB

board/mindspeed/udev800/u-boot.lds

diff --git a/board/mindspeed/udev800/u-boot.lds b/board/mindspeed/udev800/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/udev800/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

build_all.sh

diff --git a/build_all.sh b/build_all.sh
new file mode 100644
index 0000000..ec28ea4
--- /dev/null
+++ b/build_all.sh
@@ -0,0 +1,24 @@
+#/bin/bash
+
+set -e
+
+export PATH=$PATH:/usr/local/gcc-3.4.5-glibc-2.3.6/arm-softfloat-linux-gnu/bin
+
+rm -f build_all.log
+
+conf_list='tsavo530 tsavo515 tsavo515_nor '\
+'megamombasa515 megamombasa515_256M megamombasa515_sdc1 '\
+'malindi ipots48-515 ipots48-800 udev515 udev800 nairobi supermombasa910 matisse '\
+'asic packet-iad router'
+
+conf_list='asic packet-iad router ferouter'
+
+for conf in ${conf_list}; do
+
+make distclean >> build_all.log 2>&1
+
+echo "building ${conf}"
+make ${conf}_config >> build_all.log 2>&1
+make >> build_all.log 2>&1
+echo "done"
+done;

common/Makefile

diff --git a/common/Makefile b/common/Makefile
index 07ddc95..92e09fa 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -38,7 +38,7 @@
 	  cmd_load.o cmd_log.o \
 	  cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
 	  cmd_nand.o cmd_net.o cmd_nvedit.o \
-	  cmd_pci.o cmd_pcmcia.o cmd_portio.o \
+	  cmd_pci.o cmd_pcmcia.o cmd_phy.o cmd_portio.o \
 	  cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \
 	  cmd_usb.o cmd_vfd.o \
 	  command.o console.o devices.o dlmalloc.o docecc.o \
@@ -51,7 +51,7 @@
 	  memsize.o miiphybb.o miiphyutil.o \
 	  s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
 	  usb.o usb_kbd.o usb_storage.o \
-	  virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o
+	  virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o image.o
 
 SRCS	:= $(AOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS))

common/cmd_bootm.c

diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 3091a58..2052608 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -79,7 +79,9 @@
 # define CHUNKSZ (64 * 1024)
 #endif
 
+#ifndef CONFIG_NO_GZIP
 int  gunzip (void *, int, unsigned char *, unsigned long *);
+#endif
 
 static void *zalloc(void *, unsigned, unsigned);
 static void zfree(void *, void *, unsigned);
@@ -94,6 +96,10 @@
 static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 #endif
 
+#if defined(CONFIG_M8326XG) || defined(CONFIG_M8325XG) || defined(CONFIG_M8324XG)
+static void fixup_comcerto_bootargs(void);
+#endif
+
 static void print_type (image_header_t *hdr);
 
 #ifdef __I386__
@@ -341,6 +347,7 @@
 #endif	/* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
 		}
 		break;
+#ifndef CONFIG_NO_GZIP
 	case IH_COMP_GZIP:
 		printf ("   Uncompressing %s ... ", name);
 		if (gunzip ((void *)ntohl(hdr->ih_load), unc_len,
@@ -350,6 +357,7 @@
 			do_reset (cmdtp, flag, argc, argv);
 		}
 		break;
+#endif /* CONFIG_NO_GZIP */
 #ifdef CONFIG_BZIP2
 	case IH_COMP_BZIP2:
 		printf ("   Uncompressing %s ... ", name);
@@ -409,6 +417,10 @@
 	}
 	SHOW_BOOT_PROGRESS (8);
 
+#if defined(CONFIG_M8326XG) || defined(CONFIG_M8325XG) || defined(CONFIG_M8324XG)
+	fixup_comcerto_bootargs();
+#endif
+
 	switch (hdr->ih_os) {
 	default:			/* handled by (original) Linux case */
 	case IH_OS_LINUX:
@@ -461,6 +473,20 @@
 	return 1;
 }
 
+int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd)
+{
+	const char *ep = getenv("autostart");
+
+	if (ep && !strcmp(ep, "yes")) {
+		char *local_args[2];
+		local_args[0] = (char *)cmd;
+		local_args[1] = NULL;
+		printf("Automatic boot of image at addr 0x%08lX ...\n", load_addr);
+		return do_bootm(cmdtp, 0, 1, local_args);
+	}
+
+	return 0;
+}
 U_BOOT_CMD(
  	bootm,	CFG_MAXARGS,	1,	do_bootm,
  	"bootm   - boot application image from memory\n",
@@ -476,6 +502,42 @@
 #endif
 );
 
+
+#if defined(CONFIG_M8326XG) || defined(CONFIG_M8325XG) || defined(CONFIG_M8324XG)
+extern unsigned char comcerto_part_no[8];
+#define FPP_ENABLED 1 /* Default Mode is FPP Enabled */
+#define FPP_DISABLED 0 /* FPP Enabled */
+
+#if defined(CONFIG_NOFPP_MODE)
+#define FPP_MODE FPP_DISABLED
+#endif
+#if !defined(CONFIG_NOFPP_MODE)
+#define FPP_MODE FPP_ENABLED
+#endif
+
+static void fixup_comcerto_bootargs(void)
+{
+	char buf[256]; 
+	char partno[32]; 
+	char fppmode[32]; 
+	char *cmdline = getenv ("bootargs");
+
+	sprintf (partno, " partno=%s", comcerto_part_no);
+	sprintf (fppmode, " fppmode=%d", FPP_MODE);
+	if (cmdline) {
+		strcpy(buf, cmdline);
+		strcat(buf, partno);
+		strcat(buf, fppmode);
+
+	} else {
+		strcpy(buf, partno);
+		strcat(buf, fppmode);
+	}
+	
+	setenv ("bootargs", buf);
+}
+#endif
+
 #ifdef CONFIG_SILENT_CONSOLE
 static void
 fixup_silent_linux ()
@@ -1429,6 +1491,7 @@
 
 #define DEFLATED	8
 
+#ifndef CONFIG_NO_GZIP
 int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp)
 {
 	z_stream s;
@@ -1483,6 +1546,7 @@
 
 	return (0);
 }
+#endif /* CONFIG_NO_GZIP */
 
 #ifdef CONFIG_BZIP2
 void bz_internal_error(int errcode)

common/cmd_elf.c

diff --git a/common/cmd_elf.c b/common/cmd_elf.c
index 1d92bb3..8df4e8c 100644
--- a/common/cmd_elf.c
+++ b/common/cmd_elf.c
@@ -54,13 +54,14 @@
 	addr = load_elf_image (addr);
 
 	printf ("## Starting application at 0x%08lx ...\n", addr);
-
+#if 0
 	/*
 	 * QNX images require the data cache is disabled.
 	 * Data cache is already flushed, so just turn it off.
 	 */
 	if (dcache_status ())
 		dcache_disable ();
+#endif
 
 	/*
 	 * pass address parameter as argv[0] (aka command name),
@@ -99,8 +100,8 @@
 	if ((tmp = getenv ("loadaddr")) != NULL) {
 		addr = simple_strtoul (tmp, NULL, 16);
 	} else {
-		puts ("No load address provided\n");
-		return 1;
+		addr = 0x81400000;
+		printf("No load address provided, looking @ %x\n", addr);
 	}
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET)
@@ -137,7 +138,7 @@
 	 */
 
 	if ((tmp = getenv ("bootaddr")) == NULL)
-		bootaddr = 0x4200;
+		bootaddr = 0x80800700; /*Default value for C1xx devices */
 	else
 		bootaddr = simple_strtoul (tmp, NULL, 16);
 

common/cmd_jffs2.c

diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c
index 7fd1fa3..32cf48a 100644
--- a/common/cmd_jffs2.c
+++ b/common/cmd_jffs2.c
@@ -107,7 +107,7 @@
 #endif /* !CFG_NAND_LEGACY */
 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
 /* enable/disable debugging messages */
-#define	DEBUG_JFFS
+//#define	DEBUG_JFFS
 #undef	DEBUG_JFFS
 
 #ifdef  DEBUG_JFFS
@@ -1835,6 +1835,60 @@
 /***************************************************/
 /* U-boot commands				   */
 /***************************************************/
+int do_jffs2_uload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    char *fsname;
+    char *filename;
+    int size;
+    struct part_info *part;
+    ulong offset = load_addr;
+
+    /* pre-set Boot file name */
+    if ((filename = getenv("bootfile")) == NULL) {
+        filename = "uImage";
+    }
+
+    if (argc == 2) {
+        filename = argv[1];
+    }
+    if (argc == 3) {
+        offset = simple_strtoul(argv[1], NULL, 16);
+        load_addr = offset;
+        filename = argv[2];
+    }
+
+    /* make sure we are in sync with env variables */
+    if (mtdparts_init() !=0)
+        return 1;
+
+    if ((part = jffs2_part_info(current_dev, current_partnum))){
+
+        /* check partition type for cramfs */
+        fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2");
+        printf("### %s loading '%s' to 0x%lx\n", fsname, filename, offset);
+
+        if (cramfs_check(part)) {
+            size = cramfs_load ((char *) offset, part, filename);
+        } else {
+            /* if this is not cramfs assume jffs2 */
+            size = jffs2_1pass_uload((char *)offset, part, filename);
+        }
+
+        if (size > 0) {
+            char buf[10];
+            printf("### %s load complete: %d bytes loaded to 0x%lx\n",
+                fsname, size, offset);
+            sprintf(buf, "%x", size);
+            setenv("filesize", buf);
+        } else {
+            printf("### %s LOAD ERROR<%x> for %s!\n", fsname, size, filename);
+        }
+
+        return !(size > 0);
+    }
+    return 1;
+}
+
 
 /**
  * Routine implementing fsload u-boot command. This routine tries to load
@@ -2127,6 +2181,15 @@
 
 /***************************************************/
 U_BOOT_CMD(
+    uload, 3,  0,  do_jffs2_uload,
+    "uload\t- load kernel file from a filesystem image\n",
+    "[ off ] [ filename ]\n"
+    "    - load kernel file from flash bank\n"
+    "      with offset 'off'\n"
+);
+
+
+U_BOOT_CMD(
 	fsload,	3,	0,	do_jffs2_fsload,
 	"fsload\t- load binary file from a filesystem image\n",
 	"[ off ] [ filename ]\n"

common/cmd_mem.c

diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index d0fae6b..63884ee 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -438,6 +438,37 @@
 		puts ("done\n");
 		return 0;
 	}
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+        if ( (addr2info(addr) != NULL))
+        {
+                int cfg_gpio = 0;
+                puts ("Copy from Flash... ");
+                board_map(NULL, addr);
+                if((addr < (PHYS_FLASH1 + 0x800000)) && ((addr+(count*size)) >= (PHYS_FLASH1 + 0x800000)))
+                {
+                        cfg_gpio = 1;
+                }
+                while (count-- > 0) {
+                        if((cfg_gpio && (addr >=(PHYS_FLASH1 + 0x800000))))
+                        {
+                                cfg_gpio = 0;
+                                board_map(NULL, addr);
+                        }
+                        if (size == 4)
+                                *((ulong  *)dest) = *((ulong  *)addr);
+                        else if (size == 2)
+                                *((ushort *)dest) = *((ushort *)addr);
+                        else
+                                *((u_char *)dest) = *((u_char *)addr);
+                        addr += size;
+                        dest += size;
+                }
+                puts ("done\n");
+
+                return 0;
+        }
+#endif
+
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_MMC)

common/cmd_nand.c

diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 7286726..486aeae 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -4,173 +4,443 @@
  * (c) 1999 Machine Vision Holdings, Inc.
  * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
  *
+ * Ported 'dynenv' to 'nand env.oob' command
+ * (C) 2010 Nanometrics, Inc.
+ * 'dynenv' -- Dynamic environment offset in NAND OOB
+ * (C) Copyright 2006-2007 OpenMoko, Inc.
  * Added 16-bit nand support
  * (C) 2004 Texas Instruments
+ *
+ * Copyright 2010, 2012 Freescale Semiconductor
+ * The portions of this file whose copyright is held by Freescale and which
+ * are not considered a derived work of GPL v2-only code may be distributed
+ * and/or modified under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
  */
 
 #include <common.h>
-
-
-#ifndef CFG_NAND_LEGACY
-/*
- *
- * New NAND support
- *
- */
-#include <common.h>
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-
+#include <linux/mtd/mtd.h>
 #include <command.h>
 #include <watchdog.h>
 #include <malloc.h>
 #include <asm/byteorder.h>
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# include <status_led.h>
-# define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
 #include <jffs2/jffs2.h>
 #include <nand.h>
+#include <bootstage.h>
+#include <config.h>
 
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
 
-/* parition handling routines */
+#if defined(CONFIG_CMD_MTDPARTS)
+
+/* partition handling routines */
 int mtdparts_init(void);
 int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num);
 int find_dev_and_part(const char *id, struct mtd_device **dev,
-		u8 *part_num, struct part_info **part);
+		      u8 *part_num, struct part_info **part);
 #endif
 
-extern nand_info_t nand_info[];       /* info for NAND chips */
-
-static int nand_dump_oob(nand_info_t *nand, ulong off)
-{
-	return 0;
-}
-
-static int nand_dump(nand_info_t *nand, ulong off)
+static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 {
 	int i;
-	u_char *buf, *p;
+	u_char *datbuf, *oobbuf, *p;
+	static loff_t last;
 
-	buf = malloc(nand->oobblock + nand->oobsize);
-	if (!buf) {
+	if (repeat)
+		off = last + nand->writesize;
+
+	last = off;
+
+	datbuf = malloc(nand->writesize);
+	oobbuf = malloc(nand->oobsize);
+	if (!datbuf || !oobbuf) {
 		puts("No memory for page buffer\n");
 		return 1;
 	}
-	off &= ~(nand->oobblock - 1);
-	i = nand_read_raw(nand, buf, off, nand->oobblock, nand->oobsize);
+	off &= ~(nand->writesize - 1);
+	loff_t addr = (loff_t) off;
+	struct mtd_oob_ops ops;
+	memset(&ops, 0, sizeof(ops));
+	ops.datbuf = datbuf;
+	ops.oobbuf = oobbuf;
+	ops.len = nand->writesize;
+	ops.ooblen = nand->oobsize;
+	ops.mode = MTD_OOB_RAW;
+	i = nand->read_oob(nand, addr, &ops);
 	if (i < 0) {
-		printf("Error (%d) reading page %08x\n", i, off);
-		free(buf);
+		printf("Error (%d) reading page %08lx\n", i, off);
+		free(datbuf);
+		free(oobbuf);
 		return 1;
 	}
-	printf("Page %08x dump:\n", off);
-	i = nand->oobblock >> 4; p = buf;
+	printf("Page %08lx dump:\n", off);
+	i = nand->writesize >> 4;
+	p = datbuf;
+
 	while (i--) {
-		printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x"
-			"  %02x %02x %02x %02x %02x %02x %02x %02x\n",
-			p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
-			p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]);
+		if (!only_oob)
+			printf("\t%02x %02x %02x %02x %02x %02x %02x %02x"
+			       "  %02x %02x %02x %02x %02x %02x %02x %02x\n",
+			       p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
+			       p[8], p[9], p[10], p[11], p[12], p[13], p[14],
+			       p[15]);
 		p += 16;
 	}
 	puts("OOB:\n");
 	i = nand->oobsize >> 3;
+	p = oobbuf;
 	while (i--) {
-		printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
-			p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+		printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
+		       p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
 		p += 8;
 	}
-	free(buf);
+	free(datbuf);
+	free(oobbuf);
 
 	return 0;
 }
 
 /* ------------------------------------------------------------------------- */
 
-static inline int str2long(char *p, ulong *num)
+static int set_dev(int dev)
+{
+	if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
+	    !nand_info[dev].name) {
+		puts("No such device\n");
+		return -1;
+	}
+
+	if (nand_curr_device == dev)
+		return 0;
+
+	printf("Device %d: %s", dev, nand_info[dev].name);
+	puts("... is now current device\n");
+	nand_curr_device = dev;
+
+#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
+	board_nand_select_device(nand_info[dev].priv, dev);
+#endif
+
+	return 0;
+}
+
+static inline int str2off(const char *p, loff_t *num)
+{
+	char *endptr;
+
+	*num = simple_strtoull(p, &endptr, 16);
+	return *p != '\0' && *endptr == '\0';
+}
+
+static inline int str2long(const char *p, ulong *num)
 {
 	char *endptr;
 
 	*num = simple_strtoul(p, &endptr, 16);
-	return (*p != '\0' && *endptr == '\0') ? 1 : 0;
+	return *p != '\0' && *endptr == '\0';
 }
 
-static int
-arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ulong *size)
+static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size)
 {
-	int idx = nand_curr_device;
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+#ifdef CONFIG_CMD_MTDPARTS
 	struct mtd_device *dev;
 	struct part_info *part;
 	u8 pnum;
+	int ret;
 
-	if (argc >= 1 && !(str2long(argv[0], off))) {
-		if ((mtdparts_init() == 0) &&
-		    (find_dev_and_part(argv[0], &dev, &pnum, &part) == 0)) {
-			if (dev->id->type != MTD_DEV_TYPE_NAND) {
-				puts("not a NAND device\n");
-				return -1;
-			}
-			*off = part->offset;
-			if (argc >= 2) {
-				if (!(str2long(argv[1], size))) {
-					printf("'%s' is not a number\n", argv[1]);
-					return -1;
-				}
-				if (*size > part->size)
-					*size = part->size;
-			} else {
-				*size = part->size;
-			}
-			idx = dev->id->num;
-			*nand = nand_info[idx];
-			goto out;
-		}
+	ret = mtdparts_init();
+	if (ret)
+		return ret;
+
+	ret = find_dev_and_part(partname, &dev, &pnum, &part);
+	if (ret)
+		return ret;
+
+	if (dev->id->type != MTD_DEV_TYPE_NAND) {
+		puts("not a NAND device\n");
+		return -1;
 	}
+
+	*off = part->offset;
+	*size = part->size;
+	*idx = dev->id->num;
+
+	ret = set_dev(*idx);
+	if (ret)
+		return ret;
+
+	return 0;
+#else
+	puts("offset is not a number\n");
+	return -1;
 #endif
+}
 
-	if (argc >= 1) {
-		if (!(str2long(argv[0], off))) {
-			printf("'%s' is not a number\n", argv[0]);
-			return -1;
-		}
-	} else {
-		*off = 0;
+static int arg_off(const char *arg, int *idx, loff_t *off, loff_t *maxsize)
+{
+	if (!str2off(arg, off))
+		return get_part(arg, idx, off, maxsize);
+
+	if (*off >= nand_info[*idx].size) {
+		puts("Offset exceeds device limit\n");
+		return -1;
 	}
 
-	if (argc >= 2) {
-		if (!(str2long(argv[1], size))) {
-			printf("'%s' is not a number\n", argv[1]);
-			return -1;
-		}
-	} else {
-		*size = nand->size - *off;
-	}
-
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
-out:
-#endif
-	printf("device %d ", idx);
-	if (*size == nand->size)
-		puts("whole chip\n");
-	else
-		printf("offset 0x%x, size 0x%x\n", *off, *size);
+	*maxsize = nand_info[*idx].size - *off;
 	return 0;
 }
 
-int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int arg_off_size(int argc, char *const argv[], int *idx,
+			loff_t *off, loff_t *size)
 {
-	int i, dev, ret;
-	ulong addr, off, size;
+	int ret;
+	loff_t maxsize = 0;
+
+	if (argc == 0) {
+		*off = 0;
+		*size = nand_info[*idx].size;
+		goto print;
+	}
+
+	ret = arg_off(argv[0], idx, off, &maxsize);
+	if (ret)
+		return ret;
+
+	if (argc == 1) {
+		*size = maxsize;
+		goto print;
+	}
+
+	if (!str2off(argv[1], size)) {
+		printf("'%s' is not a number\n", argv[1]);
+		return -1;
+	}
+
+	if (*size > maxsize) {
+		puts("Size exceeds partition or device limit\n");
+		return -1;
+	}
+
+print:
+	printf("device %d ", *idx);
+	if (*size == nand_info[*idx].size)
+		puts("whole chip\n");
+	else
+		printf("offset 0x%llx, size 0x%llx\n",
+		       (unsigned long long)*off, (unsigned long long)*size);
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
+static void print_status(ulong start, ulong end, ulong erasesize, int status)
+{
+	printf("%08lx - %08lx: %08lx blocks %s%s%s\n",
+		start,
+		end - 1,
+		(end - start) / erasesize,
+		((status & NAND_LOCK_STATUS_TIGHT) ?  "TIGHT " : ""),
+		((status & NAND_LOCK_STATUS_LOCK) ?  "LOCK " : ""),
+		((status & NAND_LOCK_STATUS_UNLOCK) ?  "UNLOCK " : ""));
+}
+
+static void do_nand_status(nand_info_t *nand)
+{
+	ulong block_start = 0;
+	ulong off;
+	int last_status = -1;
+
+	struct nand_chip *nand_chip = nand->priv;
+	/* check the WP bit */
+	nand_chip->cmdfunc(nand, NAND_CMD_STATUS, -1, -1);
+	printf("device is %swrite protected\n",
+		(nand_chip->read_byte(nand) & 0x80 ?
+		"NOT " : ""));
+
+	for (off = 0; off < nand->size; off += nand->erasesize) {
+		int s = nand_get_lock_status(nand, off);
+
+		/* print message only if status has changed */
+		if (s != last_status && off != 0) {
+			print_status(block_start, off, nand->erasesize,
+					last_status);
+			block_start = off;
+		}
+		last_status = s;
+	}
+	/* Print the last block info */
+	print_status(block_start, off, nand->erasesize, last_status);
+}
+#endif
+
+#ifdef CONFIG_ENV_OFFSET_OOB
+unsigned long nand_env_oob_offset;
+
+int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
+{
+	int ret;
+	uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
+	nand_info_t *nand = &nand_info[0];
+	char *cmd = argv[1];
+
+	if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !nand->name) {
+		puts("no devices available\n");
+		return 1;
+	}
+
+	set_dev(0);
+
+	if (!strcmp(cmd, "get")) {
+		ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+		if (ret)
+			return 1;
+
+		printf("0x%08lx\n", nand_env_oob_offset);
+	} else if (!strcmp(cmd, "set")) {
+		loff_t addr;
+		loff_t maxsize;
+		struct mtd_oob_ops ops;
+		int idx = 0;
+
+		if (argc < 3)
+			goto usage;
+
+		if (arg_off(argv[2], &idx, &addr, &maxsize)) {
+			puts("Offset or partition name expected\n");
+			return 1;
+		}
+
+		if (idx != 0) {
+			puts("Partition not on first NAND device\n");
+			return 1;
+		}
+
+		if (nand->oobavail < ENV_OFFSET_SIZE) {
+			printf("Insufficient available OOB bytes:\n"
+			       "%d OOB bytes available but %d required for "
+			       "env.oob support\n",
+			       nand->oobavail, ENV_OFFSET_SIZE);
+			return 1;
+		}
+
+		if ((addr & (nand->erasesize - 1)) != 0) {
+			printf("Environment offset must be block-aligned\n");
+			return 1;
+		}
+
+		ops.datbuf = NULL;
+		ops.mode = MTD_OOB_AUTO;
+		ops.ooboffs = 0;
+		ops.ooblen = ENV_OFFSET_SIZE;
+		ops.oobbuf = (void *) oob_buf;
+
+		oob_buf[0] = ENV_OOB_MARKER;
+		oob_buf[1] = addr / nand->erasesize;
+
+		ret = nand->write_oob(nand, ENV_OFFSET_SIZE, &ops);
+		if (ret) {
+			printf("Error writing OOB block 0\n");
+			return ret;
+		}
+
+		ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+		if (ret) {
+			printf("Error reading env offset in OOB\n");
+			return ret;
+		}
+
+		if (addr != nand_env_oob_offset) {
+			printf("Verification of env offset in OOB failed: "
+			       "0x%08llx expected but got 0x%08lx\n",
+			       (unsigned long long)addr, nand_env_oob_offset);
+			return 1;
+		}
+	} else {
+		goto usage;
+	}
+
+	return ret;
+
+usage:
+	return CMD_RET_USAGE;
+}
+
+#endif
+
+static void nand_print_and_set_info(int idx)
+{
+	nand_info_t *nand = &nand_info[idx];
+	struct nand_chip *chip = nand->priv;
+	const int bufsz = 32;
+	char buf[bufsz];
+
+	printf("Device %d: ", idx);
+	if (chip->numchips > 1)
+		printf("%dx ", chip->numchips);
+	printf("%s, sector size %u KiB\n",
+	       nand->name, nand->erasesize >> 10);
+	printf("  Page size  %8d b\n", nand->writesize);
+	printf("  OOB size   %8d b\n", nand->oobsize);
+	printf("  Erase size %8d b\n", nand->erasesize);
+
+	/* Set geometry info */
+	sprintf(buf, "%x", nand->writesize);
+	setenv("nand_writesize", buf);
+
+	sprintf(buf, "%x", nand->oobsize);
+	setenv("nand_oobsize", buf);
+
+	sprintf(buf, "%x", nand->erasesize);
+	setenv("nand_erasesize", buf);
+}
+
+static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count,
+			int read)
+{
+	int ret = 0;
+
+	while (count--) {
+		/* Raw access */
+		mtd_oob_ops_t ops = {
+			.datbuf = (u8 *)addr,
+			.oobbuf = ((u8 *)addr) + nand->writesize,
+			.len = nand->writesize,
+			.ooblen = nand->oobsize,
+			.mode = MTD_OOB_RAW
+		};
+
+		if (read)
+			ret = nand->read_oob(nand, off, &ops);
+		else
+			ret = nand->write_oob(nand, off, &ops);
+
+		if (ret) {
+			printf("%s: error at offset %llx, ret %d\n",
+				__func__, (long long)off, ret);
+			break;
+		}
+
+		addr += nand->writesize + nand->oobsize;
+		off += nand->writesize;
+	}
+
+	return ret;
+}
+
+int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	int i, ret = 0;
+	ulong addr;
+	loff_t off, size;
 	char *cmd, *s;
 	nand_info_t *nand;
+#ifdef CONFIG_SYS_NAND_QUIET
+	int quiet = CONFIG_SYS_NAND_QUIET;
+#else
 	int quiet = 0;
+#endif
 	const char *quiet_str = getenv("quiet");
+	int dev = nand_curr_device;
+	int repeat = flag & CMD_FLAG_REPEAT;
 
 	/* at least two arguments please */
 	if (argc < 2)
@@ -181,69 +451,60 @@
 
 	cmd = argv[1];
 
+	/* Only "dump" is repeatable. */
+	if (repeat && strcmp(cmd, "dump"))
+		return 0;
+
 	if (strcmp(cmd, "info") == 0) {
 
 		putc('\n');
-		for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
+		for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
 			if (nand_info[i].name)
-				printf("Device %d: %s, sector size %lu KiB\n",
-					i, nand_info[i].name,
-					nand_info[i].erasesize >> 10);
+				nand_print_and_set_info(i);
 		}
 		return 0;
 	}
 
 	if (strcmp(cmd, "device") == 0) {
-
 		if (argc < 3) {
-			if ((nand_curr_device < 0) ||
-			    (nand_curr_device >= CFG_MAX_NAND_DEVICE))
-				puts("\nno devices available\n");
+			putc('\n');
+			if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE)
+				puts("no devices available\n");
 			else
-				printf("\nDevice %d: %s\n", nand_curr_device,
-					nand_info[nand_curr_device].name);
+				nand_print_and_set_info(dev);
 			return 0;
 		}
-		dev = (int)simple_strtoul(argv[2], NULL, 10);
-		if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) {
-			puts("No such device\n");
-			return 1;
-		}
-		printf("Device %d: %s", dev, nand_info[dev].name);
-		puts("... is now current device\n");
-		nand_curr_device = dev;
 
-#ifdef CFG_NAND_SELECT_DEVICE
-		/*
-		 * Select the chip in the board/cpu specific driver
-		 */
-		board_nand_select_device(nand_info[dev].priv, dev);
-#endif
+		dev = (int)simple_strtoul(argv[2], NULL, 10);
+		set_dev(dev);
 
 		return 0;
 	}
 
-	if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 &&
-	    strncmp(cmd, "dump", 4) != 0 &&
-	    strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 &&
-	    strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 &&
-	    strcmp(cmd, "biterr") != 0 &&
-	    strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 )
-		goto usage;
+#ifdef CONFIG_ENV_OFFSET_OOB
+	/* this command operates only on the first nand device */
+	if (strcmp(cmd, "env.oob") == 0)
+		return do_nand_env_oob(cmdtp, argc - 1, argv + 1);
+#endif
 
-	/* the following commands operate on the current device */
-	if (nand_curr_device < 0 || nand_curr_device >= CFG_MAX_NAND_DEVICE ||
-	    !nand_info[nand_curr_device].name) {
+	/* The following commands operate on the current device, unless
+	 * overridden by a partition specifier.  Note that if somehow the
+	 * current device is invalid, it will have to be changed to a valid
+	 * one before these commands can run, even if a partition specifier
+	 * for another device is to be used.
+	 */
+	if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
+	    !nand_info[dev].name) {
 		puts("\nno devices available\n");
 		return 1;
 	}
-	nand = &nand_info[nand_curr_device];
+	nand = &nand_info[dev];
 
 	if (strcmp(cmd, "bad") == 0) {
-		printf("\nDevice %d bad blocks:\n", nand_curr_device);
+		printf("\nDevice %d bad blocks:\n", dev);
 		for (off = 0; off < nand->size; off += nand->erasesize)
 			if (nand_block_isbad(nand, off))
-				printf("  %08x\n", off);
+				printf("  %08llx\n", (unsigned long long)off);
 		return 0;
 	}
 
@@ -252,39 +513,74 @@
 	 *   0    1     2       3    4
 	 *   nand erase [clean] [off size]
 	 */
-	if (strcmp(cmd, "erase") == 0 || strcmp(cmd, "scrub") == 0) {
+	if (strncmp(cmd, "erase", 5) == 0 || strncmp(cmd, "scrub", 5) == 0) {
 		nand_erase_options_t opts;
 		/* "clean" at index 2 means request to write cleanmarker */
 		int clean = argc > 2 && !strcmp("clean", argv[2]);
-		int o = clean ? 3 : 2;
-		int scrub = !strcmp(cmd, "scrub");
+		int scrub_yes = argc > 2 && !strcmp("-y", argv[2]);
+		int o = (clean || scrub_yes) ? 3 : 2;
+		int scrub = !strncmp(cmd, "scrub", 5);
+		int spread = 0;
+		int args = 2;
+		const char *scrub_warn =
+			"Warning: "
+			"scrub option will erase all factory set bad blocks!\n"
+			"         "
+			"There is no reliable way to recover them.\n"
+			"         "
+			"Use this command only for testing purposes if you\n"
+			"         "
+			"are sure of what you are doing!\n"
+			"\nReally scrub this NAND flash? <y/N>\n";
 
-		printf("\nNAND %s: ", scrub ? "scrub" : "erase");
+		if (cmd[5] != 0) {
+			if (!strcmp(&cmd[5], ".spread")) {
+				spread = 1;
+			} else if (!strcmp(&cmd[5], ".part")) {
+				args = 1;
+			} else if (!strcmp(&cmd[5], ".chip")) {
+				args = 0;
+			} else {
+				goto usage;
+			}
+		}
+
+		/*
+		 * Don't allow missing arguments to cause full chip/partition
+		 * erases -- easy to do accidentally, e.g. with a misspelled
+		 * variable name.
+		 */
+		if (argc != o + args)
+			goto usage;
+
+		printf("\nNAND %s: ", cmd);
 		/* skip first two or three arguments, look for offset and size */
-		if (arg_off_size(argc - o, argv + o, nand, &off, &size) != 0)
+		if (arg_off_size(argc - o, argv + o, &dev, &off, &size) != 0)
 			return 1;
 
+		nand = &nand_info[dev];
+
 		memset(&opts, 0, sizeof(opts));
 		opts.offset = off;
 		opts.length = size;
 		opts.jffs2  = clean;
 		opts.quiet  = quiet;
+		opts.spread = spread;
 
 		if (scrub) {
-			puts("Warning: "
-			     "scrub option will erase all factory set "
-			     "bad blocks!\n"
-			     "         "
-			     "There is no reliable way to recover them.\n"
-			     "         "
-			     "Use this command only for testing purposes "
-			     "if you\n"
-			     "         "
-			     "are sure of what you are doing!\n"
-			     "\nReally scrub this NAND flash? <y/N>\n");
+			if (!scrub_yes)
+				puts(scrub_warn);
 
-			if (getc() == 'y' && getc() == '\r') {
+			if (scrub_yes)
 				opts.scrub = 1;
+			else if (getc() == 'y') {
+				puts("y");
+				if (getc() == '\r')
+					opts.scrub = 1;
+				else {
+					puts("scrub aborted\n");
+					return -1;
+				}
 			} else {
 				puts("scrub aborted\n");
 				return -1;
@@ -300,21 +596,17 @@
 		if (argc < 3)
 			goto usage;
 
-		s = strchr(cmd, '.');
 		off = (int)simple_strtoul(argv[2], NULL, 16);
-
-		if (s != NULL && strcmp(s, ".oob") == 0)
-			ret = nand_dump_oob(nand, off);
-		else
-			ret = nand_dump(nand, off);
+		ret = nand_dump(nand, off, !strcmp(&cmd[4], ".oob"), repeat);
 
 		return ret == 0 ? 1 : 0;
-
 	}
 
-	/* read write */
 	if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
+		size_t rwsize;
+		ulong pagecount = 1;
 		int read;
+		int raw;
 
 		if (argc < 4)
 			goto usage;
@@ -323,68 +615,124 @@
 
 		read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
 		printf("\nNAND %s: ", read ? "read" : "write");
-		if (arg_off_size(argc - 3, argv + 3, nand, &off, &size) != 0)
-			return 1;
+
+		nand = &nand_info[dev];
 
 		s = strchr(cmd, '.');
-		if (s != NULL &&
-		    (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) {
-			if (read) {
-				/* read */
-				nand_read_options_t opts;
-				memset(&opts, 0, sizeof(opts));
-				opts.buffer	= (u_char*) addr;
-				opts.length	= size;
-				opts.offset	= off;
-				opts.quiet      = quiet;
-				ret = nand_read_opts(nand, &opts);
-			} else {
-				/* write */
-				nand_write_options_t opts;
-				memset(&opts, 0, sizeof(opts));
-				opts.buffer	= (u_char*) addr;
-				opts.length	= size;
-				opts.offset	= off;
-				/* opts.forcejffs2 = 1; */
-				opts.pad	= 1;
-				opts.blockalign = 1;
-				opts.quiet      = quiet;
-				ret = nand_write_opts(nand, &opts);
+
+		if (s && !strcmp(s, ".raw")) {
+			printf("\n .raw \n");
+			raw = 1;
+
+			if (arg_off(argv[3], &dev, &off, &size))
+				return 1;
+
+			if (argc > 4 && !str2long(argv[4], &pagecount)) {
+				printf("'%s' is not a number\n", argv[4]);
+				return 1;
 			}
+
+			if (pagecount * nand->writesize > size) {
+				puts("Size exceeds partition or device limit\n");
+				return -1;
+			}
+
+			rwsize = pagecount * (nand->writesize + nand->oobsize);
 		} else {
-			if (read)
-				ret = nand_read(nand, off, &size, (u_char *)addr);
-			else
-				ret = nand_write(nand, off, &size, (u_char *)addr);
+			if (arg_off_size(argc - 3, argv + 3, &dev,
+						&off, &size) != 0)
+				return 1;
+
+			rwsize = size;
 		}
 
-		printf(" %d bytes %s: %s\n", size,
+		if (!s || !strcmp(s, ".jffs2") ||
+		    !strcmp(s, ".e") || !strcmp(s, ".i")) {
+			if (read)
+				ret = nand_read_skip_bad(nand, off, &rwsize,
+							 (u_char *)addr);
+			else
+				ret = nand_write_skip_bad(nand, off, &rwsize,
+							  (u_char *)addr, 0);
+#ifdef CONFIG_CMD_NAND_TRIMFFS
+		} else if (!strcmp(s, ".trimffs")) {
+			if (read) {
+				printf("Unknown nand command suffix '%s'\n", s);
+				return 1;
+			}
+			ret = nand_write_skip_bad(nand, off, &rwsize,
+						(u_char *)addr,
+						WITH_DROP_FFS);
+#endif
+#ifdef CONFIG_CMD_NAND_YAFFS
+		} else if (!strcmp(s, ".yaffs")) {
+			if (read) {
+				printf("Unknown nand command suffix '%s'.\n", s);
+				return 1;
+			}
+			ret = nand_write_skip_bad(nand, off, &rwsize,
+						(u_char *)addr,
+						WITH_INLINE_OOB);
+#endif
+		} else if (!strcmp(s, ".oob")) {
+			/* out-of-band data */
+			mtd_oob_ops_t ops = {
+				.oobbuf = (u8 *)addr,
+				.ooblen = rwsize,
+				.mode = MTD_OOB_RAW
+			};
+
+			if (read)
+				ret = nand->read_oob(nand, off, &ops);
+			else
+				ret = nand->write_oob(nand, off, &ops);
+		} else if (raw) {
+			ret = raw_access(nand, addr, off, pagecount, read);
+		} else {
+			printf("Unknown nand command suffix '%s'.\n", s);
+			return 1;
+		}
+
+		printf(" %d bytes %s: %s\n", rwsize,
 		       read ? "read" : "written", ret ? "ERROR" : "OK");
 
 		return ret == 0 ? 0 : 1;
 	}
 
 	if (strcmp(cmd, "markbad") == 0) {
-		addr = (ulong)simple_strtoul(argv[2], NULL, 16);
+		argc -= 2;
+		argv += 2;
 
-		int ret = nand->block_markbad(nand, addr);
-		if (ret == 0) {
-			printf("block 0x%08lx successfully marked as bad\n",
-			       (ulong) addr);
-			return 0;
-		} else {
-			printf("block 0x%08lx NOT marked as bad! ERROR %d\n",
-			       (ulong) addr, ret);
+		if (argc <= 0)
+			goto usage;
+
+		while (argc > 0) {
+			addr = simple_strtoul(*argv, NULL, 16);
+
+			if (nand->block_markbad(nand, addr)) {
+				printf("block 0x%08lx NOT marked "
+					"as bad! ERROR %d\n",
+					addr, ret);
+				ret = 1;
+			} else {
+				printf("block 0x%08lx successfully "
+					"marked as bad\n",
+					addr);
+			}
+			--argc;
+			++argv;
 		}
-		return 1;
+		return ret;
 	}
+
 	if (strcmp(cmd, "biterr") == 0) {
 		/* todo */
 		return 1;
 	}
 
+#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
 	if (strcmp(cmd, "lock") == 0) {
-		int tight  = 0;
+		int tight = 0;
 		int status = 0;
 		if (argc == 3) {
 			if (!strcmp("tight", argv[2]))
@@ -392,39 +740,8 @@
 			if (!strcmp("status", argv[2]))
 				status = 1;
 		}
-
 		if (status) {
-			ulong block_start = 0;
-			ulong off;
-			int last_status = -1;
-
-			struct nand_chip *nand_chip = nand->priv;
-			/* check the WP bit */
-			nand_chip->cmdfunc (nand, NAND_CMD_STATUS, -1, -1);
-			printf("device is %swrite protected\n",
-			       (nand_chip->read_byte(nand) & 0x80 ?
-				"NOT " : "" ) );
-
-			for (off = 0; off < nand->size; off += nand->oobblock) {
-				int s = nand_get_lock_status(nand, off);
-
-				/* print message only if status has changed
-				 * or at end of chip
-				 */
-				if (off == nand->size - nand->oobblock
-				    || (s != last_status && off != 0))	{
-
-					printf("%08x - %08x: %8d pages %s%s%s\n",
-					       block_start,
-					       off-1,
-					       (off-block_start)/nand->oobblock,
-					       ((last_status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""),
-					       ((last_status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""),
-					       ((last_status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : ""));
-				}
-
-				last_status = s;
-		       }
+			do_nand_status(nand);
 		} else {
 			if (!nand_lock(nand, tight)) {
 				puts("NAND flash successfully locked\n");
@@ -437,10 +754,10 @@
 	}
 
 	if (strcmp(cmd, "unlock") == 0) {
-		if (arg_off_size(argc - 2, argv + 2, nand, &off, &size) < 0)
+		if (arg_off_size(argc - 2, argv + 2, &dev, &off, &size) < 0)
 			return 1;
 
-		if (!nand_unlock(nand, off, size)) {
+		if (!nand_unlock(&nand_info[dev], off, size)) {
 			puts("NAND flash successfully unlocked\n");
 		} else {
 			puts("Error unlocking NAND flash, "
@@ -449,92 +766,150 @@
 		}
 		return 0;
 	}
+#endif
 
 usage:
-	printf("Usage:\n%s\n", cmdtp->usage);
-	return 1;
+	return CMD_RET_USAGE;
 }
 
-U_BOOT_CMD(nand, 5, 1, do_nand,
-	"nand    - NAND sub-system\n",
-	"info                  - show available NAND devices\n"
-	"nand device [dev]     - show or set current device\n"
-	"nand read[.jffs2]     - addr off|partition size\n"
-	"nand write[.jffs2]    - addr off|partiton size - read/write `size' bytes starting\n"
-	"    at offset `off' to/from memory address `addr'\n"
-	"nand erase [clean] [off size] - erase `size' bytes from\n"
-	"    offset `off' (entire device if not specified)\n"
+U_BOOT_CMD(
+	nand, CONFIG_SYS_MAXARGS, 1, do_nand,
+	"NAND sub-system",
+	"info - show available NAND devices\n"
+	"nand device [dev] - show or set current device\n"
+	"nand read - addr off|partition size\n"
+	"nand write - addr off|partition size\n"
+	"    read/write 'size' bytes starting at offset 'off'\n"
+	"    to/from memory address 'addr', skipping bad blocks.\n"
+	"nand read.raw - addr off|partition [count]\n"
+	"nand write.raw - addr off|partition [count]\n"
+	"    Use read.raw/write.raw to avoid ECC and access the flash as-is.\n"
+#ifdef CONFIG_CMD_NAND_TRIMFFS
+	"nand write.trimffs - addr off|partition size\n"
+	"    write 'size' bytes starting at offset 'off' from memory address\n"
+	"    'addr', skipping bad blocks and dropping any pages at the end\n"
+	"    of eraseblocks that contain only 0xFF\n"
+#endif
+#ifdef CONFIG_CMD_NAND_YAFFS
+	"nand write.yaffs - addr off|partition size\n"
+	"    write 'size' bytes starting at offset 'off' with yaffs format\n"
+	"    from memory address 'addr', skipping bad blocks.\n"
+#endif
+	"nand erase[.spread] [clean] off size - erase 'size' bytes "
+	"from offset 'off'\n"
+	"    With '.spread', erase enough for given file size, otherwise,\n"
+	"    'size' includes skipped bad blocks.\n"
+	"nand erase.part [clean] partition - erase entire mtd partition'\n"
+	"nand erase.chip [clean] - erase entire chip'\n"
 	"nand bad - show bad blocks\n"
 	"nand dump[.oob] off - dump page\n"
-	"nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n"
-	"nand markbad off - mark bad block at offset (UNSAFE)\n"
-	"nand biterr off - make a bit error at offset (UNSAFE)\n"
-	"nand lock [tight] [status] - bring nand to lock state or display locked pages\n"
-	"nand unlock [offset] [size] - unlock section\n");
+	"nand scrub [-y] off size | scrub.part partition | scrub.chip\n"
+	"    really clean NAND erasing bad blocks (UNSAFE)\n"
+	"nand markbad off [...] - mark bad block(s) at offset (UNSAFE)\n"
+	"nand biterr off - make a bit error at offset (UNSAFE)"
+#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
+	"\n"
+	"nand lock [tight] [status]\n"
+	"    bring nand to lock state or display locked pages\n"
+	"nand unlock [offset] [size] - unlock section"
+#endif
+#ifdef CONFIG_ENV_OFFSET_OOB
+	"\n"
+	"nand env.oob - environment offset in OOB of block 0 of"
+	"    first device.\n"
+	"nand env.oob set off|partition - set enviromnent offset\n"
+	"nand env.oob get - get environment offset"
+#endif
+);
 
 static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
 			   ulong offset, ulong addr, char *cmd)
 {
 	int r;
-	char *ep;
-	ulong cnt;
+	char *s;
+	size_t cnt;
 	image_header_t *hdr;
+#if defined(CONFIG_FIT)
+	const void *fit_hdr = NULL;
+#endif
+
+	s = strchr(cmd, '.');
+	if (s != NULL &&
+	    (strcmp(s, ".jffs2") && strcmp(s, ".e") && strcmp(s, ".i"))) {
+		printf("Unknown nand load suffix '%s'\n", s);
+		bootstage_error(BOOTSTAGE_ID_NAND_SUFFIX);
+		return 1;
+	}
 
 	printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
 
-	cnt = nand->oobblock;
-	r = nand_read(nand, offset, &cnt, (u_char *) addr);
+	cnt = nand->writesize;
+	r = nand_read_skip_bad(nand, offset, &cnt, (u_char *) addr);
 	if (r) {
 		puts("** Read error\n");
-		SHOW_BOOT_PROGRESS(-1);
+		bootstage_error(BOOTSTAGE_ID_NAND_HDR_READ);
 		return 1;
 	}
+	bootstage_mark(BOOTSTAGE_ID_NAND_HDR_READ);
 
-	hdr = (image_header_t *) addr;
+	switch (genimg_get_format ((void *)addr)) {
+	case IMAGE_FORMAT_LEGACY:
+		hdr = (image_header_t *)addr;
 
-	if (ntohl(hdr->ih_magic) != IH_MAGIC) {
-		printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
-		SHOW_BOOT_PROGRESS(-1);
+		bootstage_mark(BOOTSTAGE_ID_NAND_TYPE);
+		image_print_contents (hdr);
+
+		cnt = image_get_image_size (hdr);
+		break;
+#if defined(CONFIG_FIT)
+	case IMAGE_FORMAT_FIT:
+		fit_hdr = (const void *)addr;
+		puts ("Fit image detected...\n");
+
+		cnt = fit_get_size (fit_hdr);
+		break;
+#endif
+	default:
+		bootstage_error(BOOTSTAGE_ID_NAND_TYPE);
+		puts ("** Unknown image type\n");
 		return 1;
 	}
+	bootstage_mark(BOOTSTAGE_ID_NAND_TYPE);
 
-	print_image_hdr(hdr);
-
-	cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t));
-
-	r = nand_read(nand, offset, &cnt, (u_char *) addr);
+	r = nand_read_skip_bad(nand, offset, &cnt, (u_char *) addr);
 	if (r) {
 		puts("** Read error\n");
-		SHOW_BOOT_PROGRESS(-1);
+		bootstage_error(BOOTSTAGE_ID_NAND_READ);
 		return 1;
 	}
+	bootstage_mark(BOOTSTAGE_ID_NAND_READ);
+
+#if defined(CONFIG_FIT)
+	/* This cannot be done earlier, we need complete FIT image in RAM first */
+	if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) {
+		if (!fit_check_format (fit_hdr)) {
+			bootstage_error(BOOTSTAGE_ID_NAND_FIT_READ);
+			puts ("** Bad FIT image format\n");
+			return 1;
+		}
+		bootstage_mark(BOOTSTAGE_ID_NAND_FIT_READ_OK);
+		fit_print_contents (fit_hdr);
+	}
+#endif
 
 	/* Loading ok, update default load address */
 
 	load_addr = addr;
 
-	/* Check if we should attempt an auto-start */
-	if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
-		char *local_args[2];
-		extern int do_bootm(cmd_tbl_t *, int, int, char *[]);
-
-		local_args[0] = cmd;
-		local_args[1] = NULL;
-
-		printf("Automatic boot of image at addr 0x%08lx ...\n", addr);
-
-		do_bootm(cmdtp, 0, 1, local_args);
-		return 1;
-	}
-	return 0;
+	return bootm_maybe_autostart(cmdtp, cmd);
 }
 
-int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
 	char *boot_device = NULL;
 	int idx;
 	ulong addr, offset = 0;
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+#if defined(CONFIG_CMD_MTDPARTS)
 	struct mtd_device *dev;
 	struct part_info *part;
 	u8 pnum;
@@ -550,18 +925,19 @@
 			if (argc > 3)
 				goto usage;
 			if (argc == 3)
-				addr = simple_strtoul(argv[2], NULL, 16);
+				addr = simple_strtoul(argv[1], NULL, 16);
 			else
-				addr = CFG_LOAD_ADDR;
+				addr = CONFIG_SYS_LOAD_ADDR;
 			return nand_load_image(cmdtp, &nand_info[dev->id->num],
 					       part->offset, addr, argv[0]);
 		}
 	}
 #endif
 
+	bootstage_mark(BOOTSTAGE_ID_NAND_PART);
 	switch (argc) {
 	case 1:
-		addr = CFG_LOAD_ADDR;
+		addr = CONFIG_SYS_LOAD_ADDR;
 		boot_device = getenv("bootdevice");
 		break;
 	case 2:
@@ -578,409 +954,34 @@
 		offset = simple_strtoul(argv[3], NULL, 16);
 		break;
 	default:
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+#if defined(CONFIG_CMD_MTDPARTS)
 usage:
 #endif
-		printf("Usage:\n%s\n", cmdtp->usage);
-		SHOW_BOOT_PROGRESS(-1);
-		return 1;
+		bootstage_error(BOOTSTAGE_ID_NAND_SUFFIX);
+		return CMD_RET_USAGE;
 	}
+	bootstage_mark(BOOTSTAGE_ID_NAND_SUFFIX);
 
 	if (!boot_device) {
 		puts("\n** No boot device **\n");
-		SHOW_BOOT_PROGRESS(-1);
+		bootstage_error(BOOTSTAGE_ID_NAND_BOOT_DEVICE);
 		return 1;
 	}
+	bootstage_mark(BOOTSTAGE_ID_NAND_BOOT_DEVICE);
 
 	idx = simple_strtoul(boot_device, NULL, 16);
 
-	if (idx < 0 || idx >= CFG_MAX_NAND_DEVICE || !nand_info[idx].name) {
+	if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx].name) {
 		printf("\n** Device %d not available\n", idx);
-		SHOW_BOOT_PROGRESS(-1);
+		bootstage_error(BOOTSTAGE_ID_NAND_AVAILABLE);
 		return 1;
 	}
+	bootstage_mark(BOOTSTAGE_ID_NAND_AVAILABLE);
 
 	return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]);
 }
 
 U_BOOT_CMD(nboot, 4, 1, do_nandboot,
-	"nboot   - boot from NAND device\n",
-	"[partition] | [[[loadAddr] dev] offset]\n");
-
-#endif				/* (CONFIG_COMMANDS & CFG_CMD_NAND) */
-
-#else /* CFG_NAND_LEGACY */
-/*
- *
- * Legacy NAND support - to be phased out
- *
- */
-#include <command.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <watchdog.h>
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# include <status_led.h>
-# define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-#if 0
-#include <linux/mtd/nand_ids.h>
-#include <jffs2/jffs2.h>
-#endif
-
-#ifdef CONFIG_OMAP1510
-void archflashwp(void *archdata, int wp);
-#endif
-
-#define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
-
-#undef	NAND_DEBUG
-#undef	PSYCHO_DEBUG
-
-/* ****************** WARNING *********************
- * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will
- * erase (or at least attempt to erase) blocks that are marked
- * bad. This can be very handy if you are _sure_ that the block
- * is OK, say because you marked a good block bad to test bad
- * block handling and you are done testing, or if you have
- * accidentally marked blocks bad.
- *
- * Erasing factory marked bad blocks is a _bad_ idea. If the
- * erase succeeds there is no reliable way to find them again,
- * and attempting to program or erase bad blocks can affect
- * the data in _other_ (good) blocks.
- */
-#define	 ALLOW_ERASE_BAD_DEBUG 0
-
-#define CONFIG_MTD_NAND_ECC  /* enable ECC */
-#define CONFIG_MTD_NAND_ECC_JFFS2
-
-/* bits for nand_legacy_rw() `cmd'; or together as needed */
-#define NANDRW_READ	0x01
-#define NANDRW_WRITE	0x00
-#define NANDRW_JFFS2	0x02
-#define NANDRW_JFFS2_SKIP	0x04
-
-/*
- * Imports from nand_legacy.c
- */
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-extern int curr_device;
-extern int nand_legacy_erase(struct nand_chip *nand, size_t ofs,
-			    size_t len, int clean);
-extern int nand_legacy_rw(struct nand_chip *nand, int cmd, size_t start,
-			 size_t len, size_t *retlen, u_char *buf);
-extern void nand_print(struct nand_chip *nand);
-extern void nand_print_bad(struct nand_chip *nand);
-extern int nand_read_oob(struct nand_chip *nand, size_t ofs,
-			       size_t len, size_t *retlen, u_char *buf);
-extern int nand_write_oob(struct nand_chip *nand, size_t ofs,
-				size_t len, size_t *retlen, const u_char *buf);
-
-
-int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-    int rcode = 0;
-
-    switch (argc) {
-    case 0:
-    case 1:
-	printf ("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-    case 2:
-	if (strcmp(argv[1],"info") == 0) {
-		int i;
-
-		putc ('\n');
-
-		for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) {
-			if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN)
-				continue; /* list only known devices */
-			printf ("Device %d: ", i);
-			nand_print(&nand_dev_desc[i]);
-		}
-		return 0;
-
-	} else if (strcmp(argv[1],"device") == 0) {
-		if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
-			puts ("\nno devices available\n");
-			return 1;
-		}
-		printf ("\nDevice %d: ", curr_device);
-		nand_print(&nand_dev_desc[curr_device]);
-		return 0;
-
-	} else if (strcmp(argv[1],"bad") == 0) {
-		if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
-			puts ("\nno devices available\n");
-			return 1;
-		}
-		printf ("\nDevice %d bad blocks:\n", curr_device);
-		nand_print_bad(&nand_dev_desc[curr_device]);
-		return 0;
-
-	}
-	printf ("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-    case 3:
-	if (strcmp(argv[1],"device") == 0) {
-		int dev = (int)simple_strtoul(argv[2], NULL, 10);
-
-		printf ("\nDevice %d: ", dev);
-		if (dev >= CFG_MAX_NAND_DEVICE) {
-			puts ("unknown device\n");
-			return 1;
-		}
-		nand_print(&nand_dev_desc[dev]);
-		/*nand_print (dev);*/
-
-		if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
-			return 1;
-		}
-
-		curr_device = dev;
-
-		puts ("... is now current device\n");
-
-		return 0;
-	}
-	else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) {
-		struct nand_chip* nand = &nand_dev_desc[curr_device];
-		ulong off = 0;
-		ulong size = nand->totlen;
-		int ret;
-
-		printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
-			curr_device, off, size);
-
-		ret = nand_legacy_erase (nand, off, size, 1);
-
-		printf("%s\n", ret ? "ERROR" : "OK");
-
-		return ret;
-	}
-
-	printf ("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-    default:
-	/* at least 4 args */
-
-	if (strncmp(argv[1], "read", 4) == 0 ||
-	    strncmp(argv[1], "write", 5) == 0) {
-		ulong addr = simple_strtoul(argv[2], NULL, 16);
-		ulong off  = simple_strtoul(argv[3], NULL, 16);
-		ulong size = simple_strtoul(argv[4], NULL, 16);
-		int cmd    = (strncmp(argv[1], "read", 4) == 0) ?
-				NANDRW_READ : NANDRW_WRITE;
-		int ret, total;
-		char* cmdtail = strchr(argv[1], '.');
-
-		if (cmdtail && !strncmp(cmdtail, ".oob", 2)) {
-			/* read out-of-band data */
-			if (cmd & NANDRW_READ) {
-				ret = nand_read_oob(nand_dev_desc + curr_device,
-						    off, size, (size_t *)&total,
-						    (u_char*)addr);
-			}
-			else {
-				ret = nand_write_oob(nand_dev_desc + curr_device,
-						     off, size, (size_t *)&total,
-						     (u_char*)addr);
-			}
-			return ret;
-		}
-		else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2))
-			cmd |= NANDRW_JFFS2;	/* skip bad blocks */
-		else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) {
-			cmd |= NANDRW_JFFS2;	/* skip bad blocks (on read too) */
-			if (cmd & NANDRW_READ)
-				cmd |= NANDRW_JFFS2_SKIP;	/* skip bad blocks (on read too) */
-		}
-#ifdef SXNI855T
-		/* need ".e" same as ".j" for compatibility with older units */
-		else if (cmdtail && !strcmp(cmdtail, ".e"))
-			cmd |= NANDRW_JFFS2;	/* skip bad blocks */
-#endif
-#ifdef CFG_NAND_SKIP_BAD_DOT_I
-		/* need ".i" same as ".jffs2s" for compatibility with older units (esd) */
-		/* ".i" for image -> read skips bad block (no 0xff) */
-		else if (cmdtail && !strcmp(cmdtail, ".i")) {
-			cmd |= NANDRW_JFFS2;	/* skip bad blocks (on read too) */
-			if (cmd & NANDRW_READ)
-				cmd |= NANDRW_JFFS2_SKIP;	/* skip bad blocks (on read too) */
-		}
-#endif /* CFG_NAND_SKIP_BAD_DOT_I */
-		else if (cmdtail) {
-			printf ("Usage:\n%s\n", cmdtp->usage);
-			return 1;
-		}
-
-		printf ("\nNAND %s: device %d offset %ld, size %ld ...\n",
-			(cmd & NANDRW_READ) ? "read" : "write",
-			curr_device, off, size);
-
-		ret = nand_legacy_rw(nand_dev_desc + curr_device, cmd, off, size,
-			     (size_t *)&total, (u_char*)addr);
-
-		printf (" %d bytes %s: %s\n", total,
-			(cmd & NANDRW_READ) ? "read" : "written",
-			ret ? "ERROR" : "OK");
-
-		return ret;
-	} else if (strcmp(argv[1],"erase") == 0 &&
-		   (argc == 4 || strcmp("clean", argv[2]) == 0)) {
-		int clean = argc == 5;
-		ulong off = simple_strtoul(argv[2 + clean], NULL, 16);
-		ulong size = simple_strtoul(argv[3 + clean], NULL, 16);
-		int ret;
-
-		printf ("\nNAND erase: device %d offset %ld, size %ld ...\n",
-			curr_device, off, size);
-
-		ret = nand_legacy_erase (nand_dev_desc + curr_device,
-					off, size, clean);
-
-		printf("%s\n", ret ? "ERROR" : "OK");
-
-		return ret;
-	} else {
-		printf ("Usage:\n%s\n", cmdtp->usage);
-		rcode = 1;
-	}
-
-	return rcode;
-    }
-}
-
-U_BOOT_CMD(
-	nand,	5,	1,	do_nand,
-	"nand    - legacy NAND sub-system\n",
-	"info  - show available NAND devices\n"
-	"nand device [dev] - show or set current device\n"
-	"nand read[.jffs2[s]]  addr off size\n"
-	"nand write[.jffs2] addr off size - read/write `size' bytes starting\n"
-	"    at offset `off' to/from memory address `addr'\n"
-	"nand erase [clean] [off size] - erase `size' bytes from\n"
-	"    offset `off' (entire device if not specified)\n"
-	"nand bad - show bad blocks\n"
-	"nand read.oob addr off size - read out-of-band data\n"
-	"nand write.oob addr off size - read out-of-band data\n"
+	"boot from NAND device",
+	"[partition] | [[[loadAddr] dev] offset]"
 );
-
-int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	char *boot_device = NULL;
-	char *ep;
-	int dev;
-	ulong cnt;
-	ulong addr;
-	ulong offset = 0;
-	image_header_t *hdr;
-	int rcode = 0;
-	switch (argc) {
-	case 1:
-		addr = CFG_LOAD_ADDR;
-		boot_device = getenv ("bootdevice");
-		break;
-	case 2:
-		addr = simple_strtoul(argv[1], NULL, 16);
-		boot_device = getenv ("bootdevice");
-		break;
-	case 3:
-		addr = simple_strtoul(argv[1], NULL, 16);
-		boot_device = argv[2];
-		break;
-	case 4:
-		addr = simple_strtoul(argv[1], NULL, 16);
-		boot_device = argv[2];
-		offset = simple_strtoul(argv[3], NULL, 16);
-		break;
-	default:
-		printf ("Usage:\n%s\n", cmdtp->usage);
-		SHOW_BOOT_PROGRESS (-1);
-		return 1;
-	}
-
-	if (!boot_device) {
-		puts ("\n** No boot device **\n");
-		SHOW_BOOT_PROGRESS (-1);
-		return 1;
-	}
-
-	dev = simple_strtoul(boot_device, &ep, 16);
-
-	if ((dev >= CFG_MAX_NAND_DEVICE) ||
-	    (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) {
-		printf ("\n** Device %d not available\n", dev);
-		SHOW_BOOT_PROGRESS (-1);
-		return 1;
-	}
-
-	printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n",
-		dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
-		offset);
-
-	if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset,
-			SECTORSIZE, NULL, (u_char *)addr)) {
-		printf ("** Read error on %d\n", dev);
-		SHOW_BOOT_PROGRESS (-1);
-		return 1;
-	}
-
-	hdr = (image_header_t *)addr;
-
-	if (ntohl(hdr->ih_magic) == IH_MAGIC) {
-
-		print_image_hdr (hdr);
-
-		cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t));
-		cnt -= SECTORSIZE;
-	} else {
-		printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic));
-		SHOW_BOOT_PROGRESS (-1);
-		return 1;
-	}
-
-	if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ,
-			offset + SECTORSIZE, cnt, NULL,
-			(u_char *)(addr+SECTORSIZE))) {
-		printf ("** Read error on %d\n", dev);
-		SHOW_BOOT_PROGRESS (-1);
-		return 1;
-	}
-
-	/* Loading ok, update default load address */
-
-	load_addr = addr;
-
-	/* Check if we should attempt an auto-start */
-	if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
-		char *local_args[2];
-		extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
-
-		local_args[0] = argv[0];
-		local_args[1] = NULL;
-
-		printf ("Automatic boot of image at addr 0x%08lx ...\n", addr);
-
-		do_bootm (cmdtp, 0, 1, local_args);
-		rcode = 1;
-	}
-	return rcode;
-}
-
-U_BOOT_CMD(
-	nboot,	4,	1,	do_nandboot,
-	"nboot   - boot from NAND device\n",
-	"loadAddr dev\n"
-);
-
-#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
-
-#endif /* CFG_NAND_LEGACY */

common/cmd_phy.c

diff --git a/common/cmd_phy.c b/common/cmd_phy.c
new file mode 100644
index 0000000..e3e38ec
--- /dev/null
+++ b/common/cmd_phy.c
@@ -0,0 +1,430 @@
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/types.h>
+
+#ifdef CONFIG_PCIE_PHY
+
+/* PCIe PHY registers */
+#define PCIE_PHY_PARALLEL_CR_CTRL_PORT_ADDR	0x00	/* CR_ADDR */
+#define PCIE_PHY_PARALLEL_CR_CTRL_PORT_DATA	0x04	/* CR_DATA */
+#define PCIE_PHY_POWER_GOOD_STATUS		0x08	/* PG_STS */
+#define PCIE_PHY_MPLL_CTRL			0x0C	/* MPLL_CTL */
+#define PCIE_PHY_TEST_CTRL			0x10	/* TEST_CTL */
+#define PCIE_PHY_TRANSMIT_LEVEL_CTRL		0x14	/* TX_LVL_CTL */
+#define PCIE_PHY_LANE0_TX_CTRL			0x18	/* TX0_CTL */
+#define PCIE_PHY_LANE1_TX_CTRL			0x1C	/* TX1_CTL */
+#define PCIE_PHY_LOS_LEVEL_CTRL			0x20	/* LOS_LVL_CTL */
+#define PCIE_PHY_LANE0_RX_CTRL			0x24	/* RX0_CTL */
+#define PCIE_PHY_LANE1_RX_CTRL			0x28	/* RX1_CTL */
+#define PCIE_PHY_TECHNOLOGY_CTRL		0x2C	/* TECH_CTL */
+#define PCIE_PHY_RESISTOR_TUNE_CTRL		0x30	/* RTUNE_CTL */
+#define PCIE_PHY_PCS_STATUS			0x34	/* PCS_STS */
+#define PCIE_PHY_PCS_CTRL			0x38	/* PCS_CTL */
+
+#define COMCERTO_CLK_DDR_PCIE_CLK_CNTRL		0x100B0018
+#define COMCERTO_CLK_CLK_PWR_DWN		0x100B0040
+#define COMCERTO_BLOCK_RESET_REG		0x100B0100 /* APB_VADDR((COMCERTO_APB_CLK_BASE + 0x100)) */
+
+#define USB_DIV_BYPASS		(1 << 30)
+#define IPSEC1_DIV_BYPASS	(1 << 29)
+#define IPSEC0_DIV_BYPASS	(1 << 28)
+#define PCIE_DIV_BYPASS		(1 << 27)
+#define DDR_DIV_BYPASS		(1 << 26)
+
+#define USB_DIV_VAL_OFFSET	20
+#define USB_DIV_VAL_MASK	(0x3f << USB_DIV_VAL_OFFSET)
+
+#define IPSEC_DIV1_VAL_OFFSET	16
+#define IPSEC_DIV1_VAL_MASK	(0xf << IPSEC_DIV0_VAL_OFFSET)
+
+#define IPSEC_DIV0_VAL_OFFSET	12
+#define IPSEC_DIV0_VAL_MASK	(0xf << IPSEC_DIV1_VAL_OFFSET)
+
+#define PCIE_DIV_VAL_OFFSET	8
+#define PCIE_DIV_VAL_MASK	(0xf << PCIE_DIV_VAL_OFFSET)
+
+#define DDR_DIV_VAL_OFFSET	4
+#define DDR_DIV_VAL_MASK	(0xf << DDR_DIV_VAL_OFFSET)
+
+
+#define USB_REF_RESET_N		(1 << 20)
+#define NO_BAL_DDR_REF_RST	(1 << 19)
+#define IPSEC2_AHB_RST		(1 << 18)
+#define RNG_RST			(1 << 17)
+#define IPSEC_CORE_RST		(1 << 16)
+#define IPSEC_AHB_RST		(1 << 15)
+#define USB_AHB_RESET_N		(1 << 14)
+#define TDM_REF_RST		(1 << 13)
+#define TDM_AHB_RST		(1 << 12)
+#define DDR_REF_RST		(1 << 11)
+#define DDR_AHB_RST		(1 << 10)
+#define PCIE1_REF_RST		(1 << 9)
+#define PCIE0_REF_RST		(1 << 8)
+#define PCIE1_AHB_RST		(1 << 7)
+#define PCIE0_AHB_RST		(1 << 6)
+#define GEMAC1_PHY_RST		(1 << 5)
+#define GEMAC0_PHY_RST		(1 << 4)
+#define GEMAC1_AHB_RST		(1 << 3)
+#define GEMAC0_AHB_RST		(1 << 2)
+#define ARM1_AHB_RST		(1 << 1)
+#define ARM0_AHB_RST		(1 << 0)
+
+#define USB_MUX_SEL		(1 << 3)
+#define IPSEC_MUX_SEL		(1 << 2)
+#define PCIE_MUX_SEL		(1 << 1)
+#define DDR_MUX_SEL		(1 << 0)
+
+
+#define USB_REFCLK_PD		(1 << 24)
+#define USB_AHBCLK_PD		(1 << 19)
+#define PCIE1_AHBCLK_PD		(1 << 15)
+#define PCIE0_AHBCLK_PD		(1 << 14)
+#define PCIE_REFCLK_NP_PD	(1 << 6)
+
+#define writel(val, addr)	*(volatile u32 *)(addr) = (val)
+#define readl(addr) 		*(volatile u32 *)(addr)
+
+void *pcie_phy_baseaddr = (void *)0x10060000;
+
+static u16 pcie_phy_reg_read(u16 addr)
+{
+	writel(addr, pcie_phy_baseaddr + PCIE_PHY_PARALLEL_CR_CTRL_PORT_ADDR);
+	return (u16)(readl(pcie_phy_baseaddr + PCIE_PHY_PARALLEL_CR_CTRL_PORT_DATA) & 0xffff);
+}
+
+static void pcie_phy_reg_write(u16 val, u16 addr)
+{
+	writel(addr, pcie_phy_baseaddr + PCIE_PHY_PARALLEL_CR_CTRL_PORT_ADDR);
+	writel(val, pcie_phy_baseaddr + PCIE_PHY_PARALLEL_CR_CTRL_PORT_DATA);
+}
+
+
+int do_txlvl (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u32 tx_level;
+
+	if (argc < 2)
+		return -1;
+
+	tx_level = simple_strtoul(argv[1], NULL, 16) & 0x1f;
+
+	writel(tx_level, pcie_phy_baseaddr + PCIE_PHY_TRANSMIT_LEVEL_CTRL);
+
+	printf("%x=%x", pcie_phy_baseaddr + PCIE_PHY_TRANSMIT_LEVEL_CTRL, readl(pcie_phy_baseaddr + PCIE_PHY_TRANSMIT_LEVEL_CTRL));
+}
+
+U_BOOT_CMD(
+	txlvl,   2,              0,      do_txlvl,
+	"txlvl    - sets tx level\n",
+);
+
+#if 0
+int do_loopback (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u32 tx_level;
+
+	if (argc < 2)
+		return -1;
+
+
+}
+
+U_BOOT_CMD(
+	txlvl,   2,              0,      do_txlvl,
+	"txlvl    - start phy BERT test\n",
+);
+#endif
+
+
+int do_phytest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int i;
+	u16 type, pat0, val;
+
+	if (argc < 3)
+		return -1;
+
+	type = simple_strtoul(argv[1], NULL, 16) & 0xffff;
+	pat0 = simple_strtoul(argv[2], NULL, 16) & 0xffff;
+
+	printf("type(%x), pat0(%x)\n", type, pat0);
+
+	/* Enable pattern output */
+	pcie_phy_reg_write((type & 0x7) | ((pat0 & 0x3ff) << 4), 0x2110);
+
+	/* Enable pattern matching and sync */
+	pcie_phy_reg_write((type & 0x7) | (1 << 3), 0x2118);
+
+	/* disable sync */
+	pcie_phy_reg_write((type & 0x7), 0x2118);
+
+	pcie_phy_reg_write((type & 0x7) | (1 << 3), 0x2118);
+
+	/* disable sync */
+	pcie_phy_reg_write((type & 0x7), 0x2118);
+
+	for (i = 0; i < 1000; i++) {
+		udelay(1000);
+
+		val = pcie_phy_reg_read(0x2119);
+		if ((val & 0x8000))
+			printf("error count %x\n", (val & 0x7fff) * 128);
+		else
+			printf("error count %x\n", (val & 0x7fff));
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	phytest,   3,              0,      do_phytest,
+	"phytest    - start phy BERT test\n",
+);
+
+int do_initphy (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u32 val;
+
+	u32 ncy = 0x4 & 0x1f;
+	u32 ncy5 = 0x0 & 0x3;
+	u32 prescale = 0x0 & 0x3;
+
+
+	/* Put block into reset */
+	writel(readl(COMCERTO_BLOCK_RESET_REG) & ~(PCIE1_REF_RST | PCIE0_REF_RST | PCIE1_AHB_RST | PCIE0_AHB_RST), COMCERTO_BLOCK_RESET_REG);
+
+	/* Power up clocks */
+	writel(readl(COMCERTO_CLK_CLK_PWR_DWN) & ~(PCIE_REFCLK_NP_PD | PCIE0_AHBCLK_PD | PCIE1_AHBCLK_PD), COMCERTO_CLK_CLK_PWR_DWN);
+
+	/* Set reference clock to 250/4 = 62.5 MHz */
+	val = readl(COMCERTO_CLK_DDR_PCIE_CLK_CNTRL);
+
+	val &= ~(PCIE_DIV_VAL_MASK | PCIE_DIV_BYPASS);
+	val |= 4 << PCIE_DIV_VAL_OFFSET;
+
+	writel(val, COMCERTO_CLK_DDR_PCIE_CLK_CNTRL);
+
+	/* Switch to clock output */
+	writel(val & ~PCIE_MUX_SEL, COMCERTO_CLK_DDR_PCIE_CLK_CNTRL);
+
+	/* Take block out of reset */
+	writel(readl(COMCERTO_BLOCK_RESET_REG) | (PCIE1_REF_RST | PCIE0_REF_RST | PCIE1_AHB_RST | PCIE0_AHB_RST), COMCERTO_BLOCK_RESET_REG);
+
+	udelay(10);
+
+
+#if 0
+	/* Synopsys recommended values */
+	u32 tx_level = 0x6 & 0x1f;
+	u32 tx_boost = 0xa & 0xf;
+	u32 tx_atten = 0x0 & 0x7;
+	u32 tx_edge_rate = 0x0 & 0x3;
+	u32 tx_clk_align = 0x0 & 0x1;
+
+	u32 los_lvl = 0x14 & 0x1f;
+
+	u32 rx_equal_val = 0x2 & 0x7;
+#elif 1
+	/* Default values */
+	u32 tx_level = 0xa & 0x1f;
+	u32 tx_boost = 0xb & 0xf;
+	u32 tx_atten = 0x0 & 0x7;
+	u32 tx_edge_rate = 0x0 & 0x3;
+	u32 tx_clk_align = 0x0 & 0x1;
+
+	u32 los_lvl = 0x11 & 0x1f;
+
+	u32 rx_equal_val = 0x2 & 0x7;
+#else
+	/* Custom values */
+/* 	u32 tx_level = 0xa & 0x1f; */
+ 	u32 tx_level = 0x13 & 0x1f;
+	u32 tx_boost = 0xb & 0xf;
+	u32 tx_atten = 0x0 & 0x7;
+	u32 tx_edge_rate = 0x0 & 0x3;
+	u32 tx_clk_align = 0x0 & 0x1;
+
+	u32 los_lvl = 0x10 & 0x1f;
+
+	u32 rx_equal_val = 0x2 & 0x7;
+#endif
+
+	/* Baud rate = 62.5MHz * MPLL_divisor / 0.5 = 62.5MHz * 20 / 0.5 = 2.5GHz */
+	writel((prescale << 1) | (ncy5 << 3) | (ncy << 5), pcie_phy_baseaddr + PCIE_PHY_MPLL_CTRL);
+
+	writel(tx_level, pcie_phy_baseaddr + PCIE_PHY_TRANSMIT_LEVEL_CTRL);
+#if 0
+	writel(tx_edge_rate | (tx_boost << 2) | (tx_atten << 6) | (tx_clk_align << 9), pcie_phy_baseaddr + PCIE_PHY_LANE0_TX_CTRL);
+
+	writel(tx_edge_rate | (tx_boost << 2) | (tx_atten << 6) | (tx_clk_align << 9), pcie_phy_baseaddr + PCIE_PHY_LANE1_TX_CTRL);
+
+	writel(los_lvl, pcie_phy_baseaddr + PCIE_PHY_LOS_LEVEL_CTRL);
+
+	writel(rx_equal_val, pcie_phy_baseaddr + PCIE_PHY_LANE0_RX_CTRL);
+	writel(rx_equal_val, pcie_phy_baseaddr + PCIE_PHY_LANE1_RX_CTRL);
+#endif
+	writel(0x00000000, pcie_phy_baseaddr + PCIE_PHY_PCS_CTRL);
+#if 1
+	/* Manual calibration of rx resistor */
+	udelay(1000);
+
+	writel(0x1, pcie_phy_baseaddr + PCIE_PHY_RESISTOR_TUNE_CTRL);
+
+	udelay(100);
+
+	writel(0x0, pcie_phy_baseaddr + PCIE_PHY_RESISTOR_TUNE_CTRL);
+#endif
+ 
+#if 0
+ 	/* Set both phys in digital loopback */
+ 	val = pcie_phy_reg_read(0x2030);
+ 	val |= (1 << 4);
+ 	pcie_phy_reg_write(val, 0x2030);
+ 
+ 	printk("lane0.rx_ana.ctrl %x\n", pcie_phy_reg_read(0x2030));
+ 
+ 	val = pcie_phy_reg_read(0x2130);
+ 	val |= (1 << 4);
+ 	pcie_phy_reg_write(val, 0x2130);
+ 
+ 	printk("lane1.rx_ana.ctrl %x\n", pcie_phy_reg_read(0x2130));
+#endif
+ 
+	return 0;
+}
+
+U_BOOT_CMD(
+	initphy,   1,              0,      do_initphy,
+	"initphy    - initialize PCIe phy\n",
+);
+
+
+int do_dumpreg (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u16 val;
+
+ 	printf("clock.rtune_ctl %x\n", pcie_phy_reg_read(0x9));
+ 
+ 	val = pcie_phy_reg_read(0xe);
+ 	printf("clock.freq_stat(%x) prop_ctl(%x) int_ctl(%x) ncy5(%x) ncy(%x) prescale(%x)\n",
+ 			val, (val & 0x7), (val >> 3) & 0x7, (val >> 6) & 0x3, (val >> 8) & 0x1f, (val >> 13) & 0x3);
+ 
+ 	val = pcie_phy_reg_read(0xf);
+ 	printf("clock.ctl_stat(%x) use_refclk_dat(%x) mpll_clk_off(%x) mpll_pwron(%x) mpll_ss_en(%x) cko_alive_con(%x) cko_word_con(%x) rtune_to_tune(%x) wide_xface(%x) vph_is_3p3(%x) vp_is_1p2(%x) fast_tech(%x)\n",
+ 			val, val & 0x1, (val >> 1) & 0x1, (val >> 2) & 0x1, (val >> 3) & 0x1, (val >> 4) & 0x3,
+ 			(val >> 6) & 0x7, (val >> 10) & 0x1, (val >> 11) & 0x1, (val >> 12) & 0x1, (val >> 13) & 0x1,
+ 			(val >> 14) & 0x1);
+ 
+ 	printf("clock.lvl_stat %x\n", pcie_phy_reg_read(0x10));
+ 	printf("clock.ctl_ovrd %x\n", pcie_phy_reg_read(0x13));
+ 	printf("clock.lvl_ovrd %x\n", pcie_phy_reg_read(0x14));
+ 	printf("clock.creg_ovrd %x\n", pcie_phy_reg_read(0x15));
+ 	printf("clock.mpll_ctl %x\n", pcie_phy_reg_read(0x16));
+ 	printf("clock.mpll_tst %x\n", pcie_phy_reg_read(0x17));
+ 
+ 	val = pcie_phy_reg_read(0x2001);
+ 	printf("lane0.tx_stat(%x) tx_cko_en(%x) tx_en(%x) tx_clk_align(%x) tx_boost(%x) tx_atten(%x) tx_edgerate(%x)\n",
+ 				val, val & 0x1, (val >> 1) & 0x7, (val >> 4) & 0x1,
+ 				(val >> 6) & 0xf, (val >> 10) & 0x7, (val >> 13) & 0x3);
+ 
+ 	val = pcie_phy_reg_read(0x2101);
+ 	printf("lane1.tx_stat(%x) tx_cko_en(%x) tx_en(%x) tx_clk_align(%x) tx_boost(%x) tx_atten(%x) tx_edgerate(%x)\n",
+ 				val, val & 0x1, (val >> 1) & 0x7, (val >> 4) & 0x1,
+ 				(val >> 6) & 0xf, (val >> 10) & 0x7, (val >> 13) & 0x3);
+ 
+ 	val = pcie_phy_reg_read(0x2002);
+ 	printf("lane0.rx_stat(%x) half_rate(%x) rx_pll_pwron(%x) rx_en(%x) rx_align_en(%x) rx_term_en(%x) rx_equal_val(%x) rx_dpll_mode(%x) dpll_reset(%x) los_ctl(%x)\n",
+ 				val, val & 0x1, (val >> 1) & 0x1, (val >> 2) & 0x1,
+ 				(val >> 3) & 0x1, (val >> 4) & 0x1, (val >> 5) & 0x7, (val >> 8) & 0x7, (val >> 11) & 0x1,
+ 				(val >> 12) & 0x3);
+ 
+ 	val = pcie_phy_reg_read(0x2102);
+ 	printf("lane1.rx_stat(%x) half_rate(%x) rx_pll_pwron(%x) rx_en(%x) rx_align_en(%x) rx_term_en(%x) rx_equal_val(%x) rx_dpll_mode(%x) dpll_reset(%x) los_ctl(%x)\n",
+ 				val, val & 0x1, (val >> 1) & 0x1, (val >> 2) & 0x1,
+ 				(val >> 3) & 0x1, (val >> 4) & 0x1, (val >> 5) & 0x7, (val >> 8) & 0x7, (val >> 11) & 0x1,
+ 				(val >> 12) & 0x3);
+ 
+ 	val = pcie_phy_reg_read(0x2003);
+ 	printf("lane0.out_stat(%x) rx_valid(%x) rx_pll_state(%x) los(%x) tx_done(%x) tx_rxpres(%x)\n",
+ 				val, val & 0x1, (val >> 1) & 0x1, (val >> 2) & 0x1,
+ 				(val >> 3) & 0x1, (val >> 4) & 0x1);
+ 
+ 	val = pcie_phy_reg_read(0x2103);
+ 	printf("lane1.out_stat(%x) rx_valid(%x) rx_pll_state(%x) los(%x) tx_done(%x) tx_rxpres(%x)\n",
+ 				val, val & 0x1, (val >> 1) & 0x1, (val >> 2) & 0x1,
+ 				(val >> 3) & 0x1, (val >> 4) & 0x1);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	dumpreg,   1,             1,      do_dumpreg,
+	"dumpreg    - dumps all PCIe phy registers\n",
+);
+
+int do_writereg (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u16 val, addr;
+
+	if (argc < 3)
+		return -1;
+
+	val = simple_strtoul(argv[1], NULL, 16) & 0xffff;
+	addr = simple_strtoul(argv[2], NULL, 16) & 0xffff;
+
+	printf("%x=%x\n", addr, val);
+
+	pcie_phy_reg_write(val, addr);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	writereg,   3,              0,      do_writereg,
+	"writereg    - writes PCIe phy reg\n",
+);
+
+int do_readreg (cmd_tbl_t *cmdtp, int flag,
+		 int	argc, char *argv[])
+{
+	u16 addr;
+
+	if (argc < 2)
+		return -1;
+
+	addr = simple_strtoul(argv[1], NULL, 16) & 0xffff;
+
+	printf("%x=%x\n", addr, pcie_phy_reg_read(addr));
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	readreg,   2,             1,      do_readreg,
+	"readreg    - read PCIe phy reg\n",
+);
+
+#endif

common/cmd_spi.c

diff --git a/common/cmd_spi.c b/common/cmd_spi.c
index a6fdf7f..9eaf152 100644
--- a/common/cmd_spi.c
+++ b/common/cmd_spi.c
@@ -31,113 +31,70 @@
 
 #if (CONFIG_COMMANDS & CFG_CMD_SPI)
 
-/*-----------------------------------------------------------------------
- * Definitions
- */
-
 #ifndef MAX_SPI_BYTES
-#   define MAX_SPI_BYTES 32	/* Maximum number of bytes we can handle */
+#   define MAX_SPI_BYTES 32     /* Maximum number of bytes we can handle */
 #endif
-
-/*
- * External table of chip select functions (see the appropriate board
- * support for the actual definition of the table).
- */
-extern spi_chipsel_type spi_chipsel[];
-extern int spi_chipsel_cnt;
-
-/*
- * Values from last command.
- */
-static int   device;
-static int   bitlen;
 static uchar dout[MAX_SPI_BYTES];
 static uchar din[MAX_SPI_BYTES];
 
-/*
- * SPI read/write
- *
- * Syntax:
- *   spi {dev} {num_bits} {dout}
- *     {dev} is the device number for controlling chip select (see TBD)
- *     {num_bits} is the number of bits to send & receive (base 10)
- *     {dout} is a hexadecimal string of data to send
- * The command prints out the hexadecimal string received via SPI.
- */
-
 int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	char  *cp = 0;
-	uchar tmp;
-	int   j;
-	int   rcode = 0;
+        int   rcode = 0;
+        int i;
+	int cs;
+	int len;
 
-	/*
-	 * We use the last specified parameters, unless new ones are
-	 * entered.
-	 */
-
-	if ((flag & CMD_FLAG_REPEAT) == 0)
+        if (argc < 3)
 	{
-		if (argc >= 2)
-			device = simple_strtoul(argv[1], NULL, 10);
-		if (argc >= 3)
-			bitlen = simple_strtoul(argv[2], NULL, 10);
-		if (argc >= 4) {
-			cp = argv[3];
-			for(j = 0; *cp; j++, cp++) {
-				tmp = *cp - '0';
-				if(tmp > 9)
-					tmp -= ('A' - '0') - 10;
-				if(tmp > 15)
-					tmp -= ('a' - 'A');
-				if(tmp > 15) {
-					printf("Hex conversion error on %c, giving up.\n", *cp);
-					return 1;
-				}
-				if((j % 2) == 0)
-					dout[j / 2] = (tmp << 4);
-				else
-					dout[j / 2] |= tmp;
-			}
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (strcmp(argv[1],"read") == 0) {
+		cs = simple_strtoul(argv[2], NULL, 10);
+		if(argc == 4)
+		{		
+			len = simple_strtoul(argv[3], NULL, 16);
 		}
-	}
-
-	if ((device < 0) || (device >=  spi_chipsel_cnt)) {
-		printf("Invalid device %d, giving up.\n", device);
-		return 1;
-	}
-	if ((bitlen < 0) || (bitlen >  (MAX_SPI_BYTES * 8))) {
-		printf("Invalid bitlen %d, giving up.\n", bitlen);
-		return 1;
-	}
-
-	debug ("spi_chipsel[%d] = %08X\n",
-		device, (uint)spi_chipsel[device]);
-
-	if(spi_xfer(spi_chipsel[device], bitlen, dout, din) != 0) {
-		printf("Error with the SPI transaction.\n");
-		rcode = 1;
-	} else {
-		cp = (char *)din;
-		for(j = 0; j < ((bitlen + 7) / 8); j++) {
-			printf("%02X", *cp++);
+		else
+		{
+			printf ("Usage:\n%s\n", cmdtp->usage);
+		}
+		printf("Read cs %d: ",cs);
+		for(i = 0; i < len; i++)
+		{
+			c2k_spi_read(cs, &dout, 1);
+			printf("%02x ",dout[0]);
 		}
 		printf("\n");
 	}
 
-	return rcode;
+	else if (strcmp(argv[1],"write") == 0) {
+		cs = simple_strtoul(argv[2], NULL, 10);
+		
+		printf("Write cs %d: ",cs);
+		for (i = 3; i < argc; i++)
+		{
+			din[0] = simple_strtoul(argv[i], NULL, 16);
+			c2k_spi_write(cs, &din, 1);
+			printf("%02x ",din[0]);
+		}
+		printf("\n");
+	}
+	else
+	{
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+	
 }
 
 /***************************************************/
 
 U_BOOT_CMD(
-	sspi,	5,	1,	do_spi,
-	"sspi    - SPI utility commands\n",
-	"<device> <bit_len> <dout> - Send <bit_len> bits from <dout> out the SPI\n"
-	"<device>  - Identifies the chip select of the device\n"
-	"<bit_len> - Number of bits to send (base 10)\n"
-	"<dout>    - Hexadecimal string that gets sent\n"
+	spi,	32,	1,	do_spi,
+	"spi     - SPI utility commands\n",
+	"spi read chipselect len - Read len number of bytes from the SPI device \n"
+	"spi write chipselect byte0 <byte1> <byte2> ... - Write bytes to the SPI device\n"
 );
-
-#endif	/* CFG_CMD_SPI */
+#endif

common/command.c

diff --git a/common/command.c b/common/command.c
index e917975..7a9b2e9 100644
--- a/common/command.c
+++ b/common/command.c
@@ -27,12 +27,48 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/arch/bsp.h>
+
+#if defined (CONFIG_COMCERTO_1000)
+extern unsigned char comcerto_part_no[8];
+#endif
 
 int
 do_version (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	extern char version_string[];
+	int clk;
+
+	printf ("-----------------------------\n");
 	printf ("\n%s\n", version_string);
+
+#if defined (CONFIG_COMCERTO_1000)
+	clk = HAL_get_arm_pll();
+	printf ("ARM PLL: %0d Hz\n", clk);
+	clk = HAL_get_ahb_pll();
+	printf ("AHB PLL: %0d Hz\n", clk);
+	clk = HAL_get_phy_pll();
+	printf ("PHY PLL: %0d Hz\n\n", clk);
+#endif
+#if 0
+	clk = HAL_get_arm_clk();
+	printf ("ARM Clock: %0d Hz\n", clk);
+	clk = HAL_get_amba_clk();
+	printf ("AHB Clock: %d Hz\n", clk);
+#endif
+#if defined (CONFIG_COMCERTO_1000)
+	clk = HAL_get_ddr_clk();
+	printf ("DDR Clock: %d Hz\n", clk);
+	clk = HAL_get_ipsec_clk();
+	printf ("IPSEC Clock: %d Hz\n", clk);
+#endif
+#if 0
+        printf ("DDR Size : %d MByte\n", get_ddr_size() / (1024 * 1024));
+#endif
+#if defined(CONFIG_M8326XG) || defined(CONFIG_M8325XG) || defined(CONFIG_M8324XG)
+        printf ("Part No: %s\n", comcerto_part_no);
+#endif
+	printf ("-----------------------------\n");
 	return 0;
 }
 

common/env_flash.c

diff --git a/common/env_flash.c b/common/env_flash.c
index 1674b30..4c28da2 100644
--- a/common/env_flash.c
+++ b/common/env_flash.c
@@ -182,6 +182,9 @@
 				up_data);
 			goto Done;
 		}
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+		board_map(NULL, ((long)flash_addr_new + CFG_ENV_SIZE));
+#endif
 		memcpy(saved_data,
 			(void *)((long)flash_addr_new + CFG_ENV_SIZE), up_data);
 		debug ("Data (start 0x%x, len 0x%x) saved at 0x%x\n",
@@ -265,6 +268,11 @@
 	if(flash_probe() == 0)
 		goto bad_flash;
 #endif
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+	board_map(NULL, env_ptr);
+#endif
+
 	if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
 		gd->env_addr  = (ulong)&(env_ptr->data);
 		gd->env_valid = 1;
@@ -302,6 +310,10 @@
 		"sect_addr: %08lX  env_addr: %08lX  offset: %08lX\n",
 		flash_sect_addr, (ulong)flash_addr, flash_offset);
 
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+	board_map(NULL, flash_sect_addr);
+#endif
+
 	/* copy old contents to temporary buffer */
 	memcpy (env_buffer, (void *)flash_sect_addr, CFG_ENV_SECT_SIZE);
 

common/image.c

diff --git a/common/image.c b/common/image.c
new file mode 100644
index 0000000..9ff4c2d
--- /dev/null
+++ b/common/image.c
@@ -0,0 +1,3215 @@
+/*
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USE_HOSTCC
+#include <common.h>
+#include <watchdog.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#include <status_led.h>
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+#endif
+
+#ifdef CONFIG_LOGBUFFER
+#include <logbuff.h>
+#endif
+
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE)
+#include <rtc.h>
+#endif
+
+#include <image.h>
+
+#if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT)
+#include <fdt.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+#if defined(CONFIG_FIT)
+#include <u-boot/md5.h>
+#include <sha1.h>
+
+static int fit_check_ramdisk(const void *fit, int os_noffset,
+		uint8_t arch, int verify);
+#endif
+
+#ifdef CONFIG_CMD_BDI
+extern int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+#endif
+
+#include <bootstage.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
+						int verify);
+#else
+#include "mkimage.h"
+#include <u-boot/md5.h>
+#include <time.h>
+#include <image.h>
+#endif /* !USE_HOSTCC*/
+
+static const table_entry_t uimage_arch[] = {
+	{	IH_ARCH_INVALID,	NULL,		"Invalid ARCH",	},
+	{	IH_ARCH_ALPHA,		"alpha",	"Alpha",	},
+	{	IH_ARCH_ARM,		"arm",		"ARM",		},
+	{	IH_ARCH_I386,		"x86",		"Intel x86",	},
+	{	IH_ARCH_IA64,		"ia64",		"IA64",		},
+	{	IH_ARCH_M68K,		"m68k",		"M68K",		},
+	{	IH_ARCH_MICROBLAZE,	"microblaze",	"MicroBlaze",	},
+	{	IH_ARCH_MIPS,		"mips",		"MIPS",		},
+	{	IH_ARCH_MIPS64,		"mips64",	"MIPS 64 Bit",	},
+	{	IH_ARCH_NIOS2,		"nios2",	"NIOS II",	},
+	{	IH_ARCH_PPC,		"powerpc",	"PowerPC",	},
+	{	IH_ARCH_PPC,		"ppc",		"PowerPC",	},
+	{	IH_ARCH_S390,		"s390",		"IBM S390",	},
+	{	IH_ARCH_SH,		"sh",		"SuperH",	},
+	{	IH_ARCH_SPARC,		"sparc",	"SPARC",	},
+	{	IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
+	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
+	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
+	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
+	{	IH_ARCH_OPENRISC,	"or1k",		"OpenRISC 1000",},
+	{	-1,			"",		"",		},
+};
+
+static const table_entry_t uimage_os[] = {
+	{	IH_OS_INVALID,	NULL,		"Invalid OS",		},
+	{	IH_OS_LINUX,	"linux",	"Linux",		},
+#if defined(CONFIG_LYNXKDI) || defined(USE_HOSTCC)
+	{	IH_OS_LYNXOS,	"lynxos",	"LynxOS",		},
+#endif
+	{	IH_OS_NETBSD,	"netbsd",	"NetBSD",		},
+	{	IH_OS_OSE,	"ose",		"Enea OSE",		},
+	{	IH_OS_RTEMS,	"rtems",	"RTEMS",		},
+	{	IH_OS_U_BOOT,	"u-boot",	"U-Boot",		},
+#if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC)
+	{	IH_OS_QNX,	"qnx",		"QNX",			},
+	{	IH_OS_VXWORKS,	"vxworks",	"VxWorks",		},
+#endif
+#if defined(CONFIG_INTEGRITY) || defined(USE_HOSTCC)
+	{	IH_OS_INTEGRITY,"integrity",	"INTEGRITY",		},
+#endif
+#ifdef USE_HOSTCC
+	{	IH_OS_4_4BSD,	"4_4bsd",	"4_4BSD",		},
+	{	IH_OS_DELL,	"dell",		"Dell",			},
+	{	IH_OS_ESIX,	"esix",		"Esix",			},
+	{	IH_OS_FREEBSD,	"freebsd",	"FreeBSD",		},
+	{	IH_OS_IRIX,	"irix",		"Irix",			},
+	{	IH_OS_NCR,	"ncr",		"NCR",			},
+	{	IH_OS_OPENBSD,	"openbsd",	"OpenBSD",		},
+	{	IH_OS_PSOS,	"psos",		"pSOS",			},
+	{	IH_OS_SCO,	"sco",		"SCO",			},
+	{	IH_OS_SOLARIS,	"solaris",	"Solaris",		},
+	{	IH_OS_SVR4,	"svr4",		"SVR4",			},
+#endif
+	{	-1,		"",		"",			},
+};
+
+static const table_entry_t uimage_type[] = {
+	{	IH_TYPE_AISIMAGE,   "aisimage",   "Davinci AIS image",},
+	{	IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image",	},
+	{	IH_TYPE_FIRMWARE,   "firmware",	  "Firmware",		},
+	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
+	{	IH_TYPE_KERNEL,	    "kernel",	  "Kernel Image",	},
+	{	IH_TYPE_KERNEL_NOLOAD, "kernel_noload",  "Kernel Image (no loading done)", },
+	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
+	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
+	{	IH_TYPE_INVALID,    NULL,	  "Invalid Image",	},
+	{	IH_TYPE_MULTI,	    "multi",	  "Multi-File Image",	},
+	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP SPL With GP CH",},
+	{	IH_TYPE_RAMDISK,    "ramdisk",	  "RAMDisk Image",	},
+	{	IH_TYPE_SCRIPT,     "script",	  "Script",		},
+	{	IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
+	{	IH_TYPE_UBLIMAGE,   "ublimage",   "Davinci UBL image",},
+	{	-1,		    "",		  "",			},
+};
+
+static const table_entry_t uimage_comp[] = {
+	{	IH_COMP_NONE,	"none",		"uncompressed",		},
+	{	IH_COMP_BZIP2,	"bzip2",	"bzip2 compressed",	},
+	{	IH_COMP_GZIP,	"gzip",		"gzip compressed",	},
+	{	IH_COMP_LZMA,	"lzma",		"lzma compressed",	},
+	{	IH_COMP_LZO,	"lzo",		"lzo compressed",	},
+	{	-1,		"",		"",			},
+};
+
+unsigned long crc32(unsigned long, const unsigned char *, uint);
+unsigned long crc32_wd(unsigned long, const unsigned char *, uint, uint);
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
+static void genimg_print_time(time_t timestamp);
+#endif
+
+/*****************************************************************************/
+/* Legacy format routines */
+/*****************************************************************************/
+int image_check_hcrc(const image_header_t *hdr)
+{
+	ulong hcrc;
+	ulong len = image_get_header_size();
+	image_header_t header;
+
+	/* Copy header so we can blank CRC field for re-calculation */
+	memmove(&header, (char *)hdr, image_get_header_size());
+	image_set_hcrc(&header, 0);
+
+	hcrc = crc32(0, (unsigned char *)&header, len);
+
+	return (hcrc == image_get_hcrc(hdr));
+}
+
+int image_check_dcrc(const image_header_t *hdr)
+{
+	ulong data = image_get_data(hdr);
+	ulong len = image_get_data_size(hdr);
+	ulong dcrc = crc32_wd(0, (unsigned char *)data, len, CHUNKSZ_CRC32);
+
+	return (dcrc == image_get_dcrc(hdr));
+}
+
+/**
+ * image_multi_count - get component (sub-image) count
+ * @hdr: pointer to the header of the multi component image
+ *
+ * image_multi_count() returns number of components in a multi
+ * component image.
+ *
+ * Note: no checking of the image type is done, caller must pass
+ * a valid multi component image.
+ *
+ * returns:
+ *     number of components
+ */
+ulong image_multi_count(const image_header_t *hdr)
+{
+	ulong i, count = 0;
+	uint32_t *size;
+
+	/* get start of the image payload, which in case of multi
+	 * component images that points to a table of component sizes */
+	size = (uint32_t *)image_get_data(hdr);
+
+	/* count non empty slots */
+	for (i = 0; size[i]; ++i)
+		count++;
+
+	return count;
+}
+
+/**
+ * image_multi_getimg - get component data address and size
+ * @hdr: pointer to the header of the multi component image
+ * @idx: index of the requested component
+ * @data: pointer to a ulong variable, will hold component data address
+ * @len: pointer to a ulong variable, will hold component size
+ *
+ * image_multi_getimg() returns size and data address for the requested
+ * component in a multi component image.
+ *
+ * Note: no checking of the image type is done, caller must pass
+ * a valid multi component image.
+ *
+ * returns:
+ *     data address and size of the component, if idx is valid
+ *     0 in data and len, if idx is out of range
+ */
+void image_multi_getimg(const image_header_t *hdr, ulong idx,
+			ulong *data, ulong *len)
+{
+	int i;
+	uint32_t *size;
+	ulong offset, count, img_data;
+
+	/* get number of component */
+	count = image_multi_count(hdr);
+
+	/* get start of the image payload, which in case of multi
+	 * component images that points to a table of component sizes */
+	size = (uint32_t *)image_get_data(hdr);
+
+	/* get address of the proper component data start, which means
+	 * skipping sizes table (add 1 for last, null entry) */
+	img_data = image_get_data(hdr) + (count + 1) * sizeof(uint32_t);
+
+	if (idx < count) {
+		*len = uimage_to_cpu(size[idx]);
+		offset = 0;
+
+		/* go over all indices preceding requested component idx */
+		for (i = 0; i < idx; i++) {
+			/* add up i-th component size, rounding up to 4 bytes */
+			offset += (uimage_to_cpu(size[i]) + 3) & ~3 ;
+		}
+
+		/* calculate idx-th component data address */
+		*data = img_data + offset;
+	} else {
+		*len = 0;
+		*data = 0;
+	}
+}
+
+static void image_print_type(const image_header_t *hdr)
+{
+	const char *os, *arch, *type, *comp;
+
+	os = genimg_get_os_name(image_get_os(hdr));
+	arch = genimg_get_arch_name(image_get_arch(hdr));
+	type = genimg_get_type_name(image_get_type(hdr));
+	comp = genimg_get_comp_name(image_get_comp(hdr));
+
+	printf("%s %s %s (%s)\n", arch, os, type, comp);
+}
+
+/**
+ * image_print_contents - prints out the contents of the legacy format image
+ * @ptr: pointer to the legacy format image header
+ * @p: pointer to prefix string
+ *
+ * image_print_contents() formats a multi line legacy image contents description.
+ * The routine prints out all header fields followed by the size/offset data
+ * for MULTI/SCRIPT images.
+ *
+ * returns:
+ *     no returned results
+ */
+void image_print_contents(const void *ptr)
+{
+	const image_header_t *hdr = (const image_header_t *)ptr;
+	const char *p;
+
+#ifdef USE_HOSTCC
+	p = "";
+#else
+	p = "   ";
+#endif
+
+	printf("%sImage Name:   %.*s\n", p, IH_NMLEN, image_get_name(hdr));
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
+	printf("%sCreated:      ", p);
+	genimg_print_time((time_t)image_get_time(hdr));
+#endif
+	printf("%sImage Type:   ", p);
+	image_print_type(hdr);
+	printf("%sData Size:    ", p);
+	genimg_print_size(image_get_data_size(hdr));
+	printf("%sLoad Address: %08x\n", p, image_get_load(hdr));
+	printf("%sEntry Point:  %08x\n", p, image_get_ep(hdr));
+
+	if (image_check_type(hdr, IH_TYPE_MULTI) ||
+			image_check_type(hdr, IH_TYPE_SCRIPT)) {
+		int i;
+		ulong data, len;
+		ulong count = image_multi_count(hdr);
+
+		printf("%sContents:\n", p);
+		for (i = 0; i < count; i++) {
+			image_multi_getimg(hdr, i, &data, &len);
+
+			printf("%s   Image %d: ", p, i);
+			genimg_print_size(len);
+
+			if (image_check_type(hdr, IH_TYPE_SCRIPT) && i > 0) {
+				/*
+				 * the user may need to know offsets
+				 * if planning to do something with
+				 * multiple files
+				 */
+				printf("%s    Offset = 0x%08lx\n", p, data);
+			}
+		}
+	}
+}
+
+
+#ifndef USE_HOSTCC
+/**
+ * image_get_ramdisk - get and verify ramdisk image
+ * @rd_addr: ramdisk image start address
+ * @arch: expected ramdisk architecture
+ * @verify: checksum verification flag
+ *
+ * image_get_ramdisk() returns a pointer to the verified ramdisk image
+ * header. Routine receives image start address and expected architecture
+ * flag. Verification done covers data and header integrity and os/type/arch
+ * fields checking.
+ *
+ * If dataflash support is enabled routine checks for dataflash addresses
+ * and handles required dataflash reads.
+ *
+ * returns:
+ *     pointer to a ramdisk image header, if image was found and valid
+ *     otherwise, return NULL
+ */
+static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
+						int verify)
+{
+	const image_header_t *rd_hdr = (const image_header_t *)rd_addr;
+
+	if (!image_check_magic(rd_hdr)) {
+		puts("Bad Magic Number\n");
+		bootstage_error(BOOTSTAGE_ID_RD_MAGIC);
+		return NULL;
+	}
+
+	if (!image_check_hcrc(rd_hdr)) {
+		puts("Bad Header Checksum\n");
+		bootstage_error(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
+		return NULL;
+	}
+
+	bootstage_mark(BOOTSTAGE_ID_RD_MAGIC);
+	image_print_contents(rd_hdr);
+
+	if (verify) {
+		puts("   Verifying Checksum ... ");
+		if (!image_check_dcrc(rd_hdr)) {
+			puts("Bad Data CRC\n");
+			bootstage_error(BOOTSTAGE_ID_RD_CHECKSUM);
+			return NULL;
+		}
+		puts("OK\n");
+	}
+
+	bootstage_mark(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
+
+	if (!image_check_os(rd_hdr, IH_OS_LINUX) ||
+	    !image_check_arch(rd_hdr, arch) ||
+	    !image_check_type(rd_hdr, IH_TYPE_RAMDISK)) {
+		printf("No Linux %s Ramdisk Image\n",
+				genimg_get_arch_name(arch));
+		bootstage_error(BOOTSTAGE_ID_RAMDISK);
+		return NULL;
+	}
+
+	return rd_hdr;
+}
+#endif /* !USE_HOSTCC */
+
+/*****************************************************************************/
+/* Shared dual-format routines */
+/*****************************************************************************/
+#ifndef USE_HOSTCC
+int getenv_yesno(char *var)
+{
+	char *s = getenv(var);
+	return (s && (*s == 'n')) ? 0 : 1;
+}
+
+ulong getenv_bootm_low(void)
+{
+	char *s = getenv("bootm_low");
+	if (s) {
+		ulong tmp = simple_strtoul(s, NULL, 16);
+		return tmp;
+	}
+
+#if defined(CONFIG_SYS_SDRAM_BASE)
+	return CONFIG_SYS_SDRAM_BASE;
+#elif defined(CONFIG_ARM)
+	return gd->bd->bi_dram[0].start;
+#else
+	return 0;
+#endif
+}
+
+phys_size_t getenv_bootm_size(void)
+{
+	phys_size_t tmp;
+	char *s = getenv("bootm_size");
+	if (s) {
+		tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
+		return tmp;
+	}
+	s = getenv("bootm_low");
+	if (s)
+		tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
+	else
+		tmp = 0;
+
+
+#if defined(CONFIG_ARM)
+	return gd->bd->bi_dram[0].size - tmp;
+#else
+	return gd->bd->bi_memsize - tmp;
+#endif
+}
+
+phys_size_t getenv_bootm_mapsize(void)
+{
+	phys_size_t tmp;
+	char *s = getenv("bootm_mapsize");
+	if (s) {
+		tmp = (phys_size_t)simple_strtoull(s, NULL, 16);
+		return tmp;
+	}
+
+#if defined(CONFIG_SYS_BOOTMAPSZ)
+	return CONFIG_SYS_BOOTMAPSZ;
+#else
+	return getenv_bootm_size();
+#endif
+}
+
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
+{
+	if (to == from)
+		return;
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+	while (len > 0) {
+		size_t tail = (len > chunksz) ? chunksz : len;
+		WATCHDOG_RESET();
+		memmove(to, from, tail);
+		to += tail;
+		from += tail;
+		len -= tail;
+	}
+#else	/* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */
+	memmove(to, from, len);
+#endif	/* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
+}
+#endif /* !USE_HOSTCC */
+
+void genimg_print_size(uint32_t size)
+{
+#ifndef USE_HOSTCC
+	printf("%d Bytes = ", size);
+	print_size(size, "\n");
+#else
+	printf("%d Bytes = %.2f kB = %.2f MB\n",
+			size, (double)size / 1.024e3,
+			(double)size / 1.048576e6);
+#endif
+}
+
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
+static void genimg_print_time(time_t timestamp)
+{
+#ifndef USE_HOSTCC
+	struct rtc_time tm;
+
+	to_tm(timestamp, &tm);
+	printf("%4d-%02d-%02d  %2d:%02d:%02d UTC\n",
+			tm.tm_year, tm.tm_mon, tm.tm_mday,
+			tm.tm_hour, tm.tm_min, tm.tm_sec);
+#else
+	printf("%s", ctime(&timestamp));
+#endif
+}
+#endif /* CONFIG_TIMESTAMP || CONFIG_CMD_DATE || USE_HOSTCC */
+
+/**
+ * get_table_entry_name - translate entry id to long name
+ * @table: pointer to a translation table for entries of a specific type
+ * @msg: message to be returned when translation fails
+ * @id: entry id to be translated
+ *
+ * get_table_entry_name() will go over translation table trying to find
+ * entry that matches given id. If matching entry is found, its long
+ * name is returned to the caller.
+ *
+ * returns:
+ *     long entry name if translation succeeds
+ *     msg otherwise
+ */
+char *get_table_entry_name(const table_entry_t *table, char *msg, int id)
+{
+	for (; table->id >= 0; ++table) {
+		if (table->id == id)
+#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
+			return table->lname;
+#else
+			return table->lname + gd->reloc_off;
+#endif
+	}
+	return (msg);
+}
+
+const char *genimg_get_os_name(uint8_t os)
+{
+	return (get_table_entry_name(uimage_os, "Unknown OS", os));
+}
+
+const char *genimg_get_arch_name(uint8_t arch)
+{
+	return (get_table_entry_name(uimage_arch, "Unknown Architecture",
+					arch));
+}
+
+const char *genimg_get_type_name(uint8_t type)
+{
+	return (get_table_entry_name(uimage_type, "Unknown Image", type));
+}
+
+const char *genimg_get_comp_name(uint8_t comp)
+{
+	return (get_table_entry_name(uimage_comp, "Unknown Compression",
+					comp));
+}
+
+/**
+ * get_table_entry_id - translate short entry name to id
+ * @table: pointer to a translation table for entries of a specific type
+ * @table_name: to be used in case of error
+ * @name: entry short name to be translated
+ *
+ * get_table_entry_id() will go over translation table trying to find
+ * entry that matches given short name. If matching entry is found,
+ * its id returned to the caller.
+ *
+ * returns:
+ *     entry id if translation succeeds
+ *     -1 otherwise
+ */
+int get_table_entry_id(const table_entry_t *table,
+		const char *table_name, const char *name)
+{
+	const table_entry_t *t;
+#ifdef USE_HOSTCC
+	int first = 1;
+
+	for (t = table; t->id >= 0; ++t) {
+		if (t->sname && strcasecmp(t->sname, name) == 0)
+			return(t->id);
+	}
+
+	fprintf(stderr, "\nInvalid %s Type - valid names are", table_name);
+	for (t = table; t->id >= 0; ++t) {
+		if (t->sname == NULL)
+			continue;
+		fprintf(stderr, "%c %s", (first) ? ':' : ',', t->sname);
+		first = 0;
+	}
+	fprintf(stderr, "\n");
+#else
+	for (t = table; t->id >= 0; ++t) {
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+		if (t->sname && strcmp(t->sname + gd->reloc_off, name) == 0)
+#else
+		if (t->sname && strcmp(t->sname, name) == 0)
+#endif
+			return (t->id);
+	}
+	debug("Invalid %s Type: %s\n", table_name, name);
+#endif /* USE_HOSTCC */
+	return (-1);
+}
+
+int genimg_get_os_id(const char *name)
+{
+	return (get_table_entry_id(uimage_os, "OS", name));
+}
+
+int genimg_get_arch_id(const char *name)
+{
+	return (get_table_entry_id(uimage_arch, "CPU", name));
+}
+
+int genimg_get_type_id(const char *name)
+{
+	return (get_table_entry_id(uimage_type, "Image", name));
+}
+
+int genimg_get_comp_id(const char *name)
+{
+	return (get_table_entry_id(uimage_comp, "Compression", name));
+}
+
+#ifndef USE_HOSTCC
+/**
+ * genimg_get_format - get image format type
+ * @img_addr: image start address
+ *
+ * genimg_get_format() checks whether provided address points to a valid
+ * legacy or FIT image.
+ *
+ * New uImage format and FDT blob are based on a libfdt. FDT blob
+ * may be passed directly or embedded in a FIT image. In both situations
+ * genimg_get_format() must be able to dectect libfdt header.
+ *
+ * returns:
+ *     image format type or IMAGE_FORMAT_INVALID if no image is present
+ */
+int genimg_get_format(void *img_addr)
+{
+	ulong format = IMAGE_FORMAT_INVALID;
+	const image_header_t *hdr;
+#if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT)
+	char *fit_hdr;
+#endif
+
+	hdr = (const image_header_t *)img_addr;
+	if (image_check_magic(hdr))
+		format = IMAGE_FORMAT_LEGACY;
+#if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT)
+	else {
+		fit_hdr = (char *)img_addr;
+		if (fdt_check_header(fit_hdr) == 0)
+			format = IMAGE_FORMAT_FIT;
+	}
+#endif
+
+	return format;
+}
+
+/**
+ * genimg_get_image - get image from special storage (if necessary)
+ * @img_addr: image start address
+ *
+ * genimg_get_image() checks if provided image start adddress is located
+ * in a dataflash storage. If so, image is moved to a system RAM memory.
+ *
+ * returns:
+ *     image start address after possible relocation from special storage
+ */
+ulong genimg_get_image(ulong img_addr)
+{
+	ulong ram_addr = img_addr;
+
+#ifdef CONFIG_HAS_DATAFLASH
+	ulong h_size, d_size;
+
+	if (addr_dataflash(img_addr)) {
+		/* ger RAM address */
+		ram_addr = CONFIG_SYS_LOAD_ADDR;
+
+		/* get header size */
+		h_size = image_get_header_size();
+#if defined(CONFIG_FIT)
+		if (sizeof(struct fdt_header) > h_size)
+			h_size = sizeof(struct fdt_header);
+#endif
+
+		/* read in header */
+		debug("   Reading image header from dataflash address "
+			"%08lx to RAM address %08lx\n", img_addr, ram_addr);
+
+		read_dataflash(img_addr, h_size, (char *)ram_addr);
+
+		/* get data size */
+		switch (genimg_get_format((void *)ram_addr)) {
+		case IMAGE_FORMAT_LEGACY:
+			d_size = image_get_data_size(
+					(const image_header_t *)ram_addr);
+			debug("   Legacy format image found at 0x%08lx, "
+					"size 0x%08lx\n",
+					ram_addr, d_size);
+			break;
+#if defined(CONFIG_FIT)
+		case IMAGE_FORMAT_FIT:
+			d_size = fit_get_size((const void *)ram_addr) - h_size;
+			debug("   FIT/FDT format image found at 0x%08lx, "
+					"size 0x%08lx\n",
+					ram_addr, d_size);
+			break;
+#endif
+		default:
+			printf("   No valid image found at 0x%08lx\n",
+				img_addr);
+			return ram_addr;
+		}
+
+		/* read in image data */
+		debug("   Reading image remaining data from dataflash address "
+			"%08lx to RAM address %08lx\n", img_addr + h_size,
+			ram_addr + h_size);
+
+		read_dataflash(img_addr + h_size, d_size,
+				(char *)(ram_addr + h_size));
+
+	}
+#endif /* CONFIG_HAS_DATAFLASH */
+
+	return ram_addr;
+}
+
+/**
+ * fit_has_config - check if there is a valid FIT configuration
+ * @images: pointer to the bootm command headers structure
+ *
+ * fit_has_config() checks if there is a FIT configuration in use
+ * (if FTI support is present).
+ *
+ * returns:
+ *     0, no FIT support or no configuration found
+ *     1, configuration found
+ */
+int genimg_has_config(bootm_headers_t *images)
+{
+#if defined(CONFIG_FIT)
+	if (images->fit_uname_cfg)
+		return 1;
+#endif
+	return 0;
+}
+
+/**
+ * boot_get_ramdisk - main ramdisk handling routine
+ * @argc: command argument count
+ * @argv: command argument list
+ * @images: pointer to the bootm images structure
+ * @arch: expected ramdisk architecture
+ * @rd_start: pointer to a ulong variable, will hold ramdisk start address
+ * @rd_end: pointer to a ulong variable, will hold ramdisk end
+ *
+ * boot_get_ramdisk() is responsible for finding a valid ramdisk image.
+ * Curently supported are the following ramdisk sources:
+ *      - multicomponent kernel/ramdisk image,
+ *      - commandline provided address of decicated ramdisk image.
+ *
+ * returns:
+ *     0, if ramdisk image was found and valid, or skiped
+ *     rd_start and rd_end are set to ramdisk start/end addresses if
+ *     ramdisk image is found and valid
+ *
+ *     1, if ramdisk image is found but corrupted, or invalid
+ *     rd_start and rd_end are set to 0 if no ramdisk exists
+ */
+int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
+		uint8_t arch, ulong *rd_start, ulong *rd_end)
+{
+	ulong rd_addr, rd_load;
+	ulong rd_data, rd_len;
+	const image_header_t *rd_hdr;
+#ifdef CONFIG_SUPPORT_RAW_INITRD
+	char *end;
+#endif
+#if defined(CONFIG_FIT)
+	void		*fit_hdr;
+	const char	*fit_uname_config = NULL;
+	const char	*fit_uname_ramdisk = NULL;
+	ulong		default_addr;
+	int		rd_noffset;
+	int		cfg_noffset;
+	const void	*data;
+	size_t		size;
+#endif
+
+	*rd_start = 0;
+	*rd_end = 0;
+
+	/*
+	 * Look for a '-' which indicates to ignore the
+	 * ramdisk argument
+	 */
+	if ((argc >= 3) && (strcmp(argv[2], "-") ==  0)) {
+		debug("## Skipping init Ramdisk\n");
+		rd_len = rd_data = 0;
+	} else if (argc >= 3 || genimg_has_config(images)) {
+#if defined(CONFIG_FIT)
+		if (argc >= 3) {
+			/*
+			 * If the init ramdisk comes from the FIT image and
+			 * the FIT image address is omitted in the command
+			 * line argument, try to use os FIT image address or
+			 * default load address.
+			 */
+			if (images->fit_uname_os)
+				default_addr = (ulong)images->fit_hdr_os;
+			else
+				default_addr = load_addr;
+
+			if (fit_parse_conf(argv[2], default_addr,
+						&rd_addr, &fit_uname_config)) {
+				debug("*  ramdisk: config '%s' from image at "
+						"0x%08lx\n",
+						fit_uname_config, rd_addr);
+			} else if (fit_parse_subimage(argv[2], default_addr,
+						&rd_addr, &fit_uname_ramdisk)) {
+				debug("*  ramdisk: subimage '%s' from image at "
+						"0x%08lx\n",
+						fit_uname_ramdisk, rd_addr);
+			} else
+#endif
+			{
+				rd_addr = simple_strtoul(argv[2], NULL, 16);
+				debug("*  ramdisk: cmdline image address = "
+						"0x%08lx\n",
+						rd_addr);
+			}
+#if defined(CONFIG_FIT)
+		} else {
+			/* use FIT configuration provided in first bootm
+			 * command argument
+			 */
+			rd_addr = (ulong)images->fit_hdr_os;
+			fit_uname_config = images->fit_uname_cfg;
+			debug("*  ramdisk: using config '%s' from image "
+					"at 0x%08lx\n",
+					fit_uname_config, rd_addr);
+
+			/*
+			 * Check whether configuration has ramdisk defined,
+			 * if not, don't try to use it, quit silently.
+			 */
+			fit_hdr = (void *)rd_addr;
+			cfg_noffset = fit_conf_get_node(fit_hdr,
+							fit_uname_config);
+			if (cfg_noffset < 0) {
+				debug("*  ramdisk: no such config\n");
+				return 1;
+			}
+
+			rd_noffset = fit_conf_get_ramdisk_node(fit_hdr,
+								cfg_noffset);
+			if (rd_noffset < 0) {
+				debug("*  ramdisk: no ramdisk in config\n");
+				return 0;
+			}
+		}
+#endif
+
+		/* copy from dataflash if needed */
+		rd_addr = genimg_get_image(rd_addr);
+
+		/*
+		 * Check if there is an initrd image at the
+		 * address provided in the second bootm argument
+		 * check image type, for FIT images get FIT node.
+		 */
+		switch (genimg_get_format((void *)rd_addr)) {
+		case IMAGE_FORMAT_LEGACY:
+			printf("## Loading init Ramdisk from Legacy "
+					"Image at %08lx ...\n", rd_addr);
+
+			bootstage_mark(BOOTSTAGE_ID_CHECK_RAMDISK);
+			rd_hdr = image_get_ramdisk(rd_addr, arch,
+							images->verify);
+
+			if (rd_hdr == NULL)
+				return 1;
+
+			rd_data = image_get_data(rd_hdr);
+			rd_len = image_get_data_size(rd_hdr);
+			rd_load = image_get_load(rd_hdr);
+			break;
+#if defined(CONFIG_FIT)
+		case IMAGE_FORMAT_FIT:
+			fit_hdr = (void *)rd_addr;
+			printf("## Loading init Ramdisk from FIT "
+					"Image at %08lx ...\n", rd_addr);
+
+			bootstage_mark(BOOTSTAGE_ID_FIT_RD_FORMAT);
+			if (!fit_check_format(fit_hdr)) {
+				puts("Bad FIT ramdisk image format!\n");
+				bootstage_error(
+					BOOTSTAGE_ID_FIT_RD_FORMAT);
+				return 1;
+			}
+			bootstage_mark(BOOTSTAGE_ID_FIT_RD_FORMAT_OK);
+
+			if (!fit_uname_ramdisk) {
+				/*
+				 * no ramdisk image node unit name, try to get config
+				 * node first. If config unit node name is NULL
+				 * fit_conf_get_node() will try to find default config node
+				 */
+				bootstage_mark(
+					BOOTSTAGE_ID_FIT_RD_NO_UNIT_NAME);
+				cfg_noffset = fit_conf_get_node(fit_hdr,
+							fit_uname_config);
+				if (cfg_noffset < 0) {
+					puts("Could not find configuration "
+						"node\n");
+					bootstage_error(
+					BOOTSTAGE_ID_FIT_RD_NO_UNIT_NAME);
+					return 1;
+				}
+				fit_uname_config = fdt_get_name(fit_hdr,
+							cfg_noffset, NULL);
+				printf("   Using '%s' configuration\n",
+					fit_uname_config);
+
+				rd_noffset = fit_conf_get_ramdisk_node(fit_hdr,
+							cfg_noffset);
+				fit_uname_ramdisk = fit_get_name(fit_hdr,
+							rd_noffset, NULL);
+			} else {
+				/* get ramdisk component image node offset */
+				bootstage_mark(
+					BOOTSTAGE_ID_FIT_RD_UNIT_NAME);
+				rd_noffset = fit_image_get_node(fit_hdr,
+						fit_uname_ramdisk);
+			}
+			if (rd_noffset < 0) {
+				puts("Could not find subimage node\n");
+				bootstage_error(BOOTSTAGE_ID_FIT_RD_SUBNODE);
+				return 1;
+			}
+
+			printf("   Trying '%s' ramdisk subimage\n",
+				fit_uname_ramdisk);
+
+			bootstage_mark(BOOTSTAGE_ID_FIT_RD_CHECK);
+			if (!fit_check_ramdisk(fit_hdr, rd_noffset, arch,
+						images->verify))
+				return 1;
+
+			/* get ramdisk image data address and length */
+			if (fit_image_get_data(fit_hdr, rd_noffset, &data,
+						&size)) {
+				puts("Could not find ramdisk subimage data!\n");
+				bootstage_error(BOOTSTAGE_ID_FIT_RD_GET_DATA);
+				return 1;
+			}
+			bootstage_mark(BOOTSTAGE_ID_FIT_RD_GET_DATA_OK);
+
+			rd_data = (ulong)data;
+			rd_len = size;
+
+			if (fit_image_get_load(fit_hdr, rd_noffset, &rd_load)) {
+				puts("Can't get ramdisk subimage load "
+					"address!\n");
+				bootstage_error(BOOTSTAGE_ID_FIT_RD_LOAD);
+				return 1;
+			}
+			bootstage_mark(BOOTSTAGE_ID_FIT_RD_LOAD);
+
+			images->fit_hdr_rd = fit_hdr;
+			images->fit_uname_rd = fit_uname_ramdisk;
+			images->fit_noffset_rd = rd_noffset;
+			break;
+#endif
+		default:
+#ifdef CONFIG_SUPPORT_RAW_INITRD
+			if (argc >= 3 && (end = strchr(argv[2], ':'))) {
+				rd_len = simple_strtoul(++end, NULL, 16);
+				rd_data = rd_addr;
+			} else
+#endif
+			{
+				puts("Wrong Ramdisk Image Format\n");
+				rd_data = rd_len = rd_load = 0;
+				return 1;
+			}
+		}
+	} else if (images->legacy_hdr_valid &&
+			image_check_type(&images->legacy_hdr_os_copy,
+						IH_TYPE_MULTI)) {
+
+		/*
+		 * Now check if we have a legacy mult-component image,
+		 * get second entry data start address and len.
+		 */
+		bootstage_mark(BOOTSTAGE_ID_RAMDISK);
+		printf("## Loading init Ramdisk from multi component "
+				"Legacy Image at %08lx ...\n",
+				(ulong)images->legacy_hdr_os);
+
+		image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len);
+	} else {
+		/*
+		 * no initrd image
+		 */
+		bootstage_mark(BOOTSTAGE_ID_NO_RAMDISK);
+		rd_len = rd_data = 0;
+	}
+
+	if (!rd_data) {
+		debug("## No init Ramdisk\n");
+	} else {
+		*rd_start = rd_data;
+		*rd_end = rd_data + rd_len;
+	}
+	debug("   ramdisk start = 0x%08lx, ramdisk end = 0x%08lx\n",
+			*rd_start, *rd_end);
+
+	return 0;
+}
+
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
+/**
+ * boot_ramdisk_high - relocate init ramdisk
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @rd_data: ramdisk data start address
+ * @rd_len: ramdisk data length
+ * @initrd_start: pointer to a ulong variable, will hold final init ramdisk
+ *      start address (after possible relocation)
+ * @initrd_end: pointer to a ulong variable, will hold final init ramdisk
+ *      end address (after possible relocation)
+ *
+ * boot_ramdisk_high() takes a relocation hint from "initrd_high" environement
+ * variable and if requested ramdisk data is moved to a specified location.
+ *
+ * Initrd_start and initrd_end are set to final (after relocation) ramdisk
+ * start/end addresses if ramdisk image start and len were provided,
+ * otherwise set initrd_start and initrd_end set to zeros.
+ *
+ * returns:
+ *      0 - success
+ *     -1 - failure
+ */
+int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
+		  ulong *initrd_start, ulong *initrd_end)
+{
+	char	*s;
+	ulong	initrd_high;
+	int	initrd_copy_to_ram = 1;
+
+	if ((s = getenv("initrd_high")) != NULL) {
+		/* a value of "no" or a similar string will act like 0,
+		 * turning the "load high" feature off. This is intentional.
+		 */
+		initrd_high = simple_strtoul(s, NULL, 16);
+		if (initrd_high == ~0)
+			initrd_copy_to_ram = 0;
+	} else {
+		/* not set, no restrictions to load high */
+		initrd_high = ~0;
+	}
+
+
+#ifdef CONFIG_LOGBUFFER
+	/* Prevent initrd from overwriting logbuffer */
+	lmb_reserve(lmb, logbuffer_base() - LOGBUFF_OVERHEAD, LOGBUFF_RESERVE);
+#endif
+
+	debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n",
+			initrd_high, initrd_copy_to_ram);
+
+	if (rd_data) {
+		if (!initrd_copy_to_ram) {	/* zero-copy ramdisk support */
+			debug("   in-place initrd\n");
+			*initrd_start = rd_data;
+			*initrd_end = rd_data + rd_len;
+			lmb_reserve(lmb, rd_data, rd_len);
+		} else {
+			if (initrd_high)
+				*initrd_start = (ulong)lmb_alloc_base(lmb,
+						rd_len, 0x1000, initrd_high);
+			else
+				*initrd_start = (ulong)lmb_alloc(lmb, rd_len,
+								 0x1000);
+
+			if (*initrd_start == 0) {
+				puts("ramdisk - allocation error\n");
+				goto error;
+			}
+			bootstage_mark(BOOTSTAGE_ID_COPY_RAMDISK);
+
+			*initrd_end = *initrd_start + rd_len;
+			printf("   Loading Ramdisk to %08lx, end %08lx ... ",
+					*initrd_start, *initrd_end);
+
+			memmove_wd((void *)*initrd_start,
+					(void *)rd_data, rd_len, CHUNKSZ);
+
+#ifdef CONFIG_MP
+			/*
+			 * Ensure the image is flushed to memory to handle
+			 * AMP boot scenarios in which we might not be
+			 * HW cache coherent
+			 */
+			flush_cache((unsigned long)*initrd_start, rd_len);
+#endif
+			puts("OK\n");
+		}
+	} else {
+		*initrd_start = 0;
+		*initrd_end = 0;
+	}
+	debug("   ramdisk load start = 0x%08lx, ramdisk load end = 0x%08lx\n",
+			*initrd_start, *initrd_end);
+
+	return 0;
+
+error:
+	return -1;
+}
+#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
+
+#ifdef CONFIG_OF_LIBFDT
+static void fdt_error(const char *msg)
+{
+	puts("ERROR: ");
+	puts(msg);
+	puts(" - must RESET the board to recover.\n");
+}
+
+static const image_header_t *image_get_fdt(ulong fdt_addr)
+{
+	const image_header_t *fdt_hdr = (const image_header_t *)fdt_addr;
+
+	image_print_contents(fdt_hdr);
+
+	puts("   Verifying Checksum ... ");
+	if (!image_check_hcrc(fdt_hdr)) {
+		fdt_error("fdt header checksum invalid");
+		return NULL;
+	}
+
+	if (!image_check_dcrc(fdt_hdr)) {
+		fdt_error("fdt checksum invalid");
+		return NULL;
+	}
+	puts("OK\n");
+
+	if (!image_check_type(fdt_hdr, IH_TYPE_FLATDT)) {
+		fdt_error("uImage is not a fdt");
+		return NULL;
+	}
+	if (image_get_comp(fdt_hdr) != IH_COMP_NONE) {
+		fdt_error("uImage is compressed");
+		return NULL;
+	}
+	if (fdt_check_header((char *)image_get_data(fdt_hdr)) != 0) {
+		fdt_error("uImage data is not a fdt");
+		return NULL;
+	}
+	return fdt_hdr;
+}
+
+/**
+ * fit_check_fdt - verify FIT format FDT subimage
+ * @fit_hdr: pointer to the FIT  header
+ * fdt_noffset: FDT subimage node offset within FIT image
+ * @verify: data CRC verification flag
+ *
+ * fit_check_fdt() verifies integrity of the FDT subimage and from
+ * specified FIT image.
+ *
+ * returns:
+ *     1, on success
+ *     0, on failure
+ */
+#if defined(CONFIG_FIT)
+static int fit_check_fdt(const void *fit, int fdt_noffset, int verify)
+{
+	fit_image_print(fit, fdt_noffset, "   ");
+
+	if (verify) {
+		puts("   Verifying Hash Integrity ... ");
+		if (!fit_image_check_hashes(fit, fdt_noffset)) {
+			fdt_error("Bad Data Hash");
+			return 0;
+		}
+		puts("OK\n");
+	}
+
+	if (!fit_image_check_type(fit, fdt_noffset, IH_TYPE_FLATDT)) {
+		fdt_error("Not a FDT image");
+		return 0;
+	}
+
+	if (!fit_image_check_comp(fit, fdt_noffset, IH_COMP_NONE)) {
+		fdt_error("FDT image is compressed");
+		return 0;
+	}
+
+	return 1;
+}
+#endif /* CONFIG_FIT */
+
+#ifndef CONFIG_SYS_FDT_PAD
+#define CONFIG_SYS_FDT_PAD 0x3000
+#endif
+
+#if defined(CONFIG_OF_LIBFDT)
+/**
+ * boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @fdt_blob: pointer to fdt blob base address
+ *
+ * Adds the memreserve regions in the dtb to the lmb block.  Adding the
+ * memreserve regions prevents u-boot from using them to store the initrd
+ * or the fdt blob.
+ */
+void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob)
+{
+	uint64_t addr, size;
+	int i, total;
+
+	if (fdt_check_header(fdt_blob) != 0)
+		return;
+
+	total = fdt_num_mem_rsv(fdt_blob);
+	for (i = 0; i < total; i++) {
+		if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
+			continue;
+		printf("   reserving fdt memory region: addr=%llx size=%llx\n",
+			(unsigned long long)addr, (unsigned long long)size);
+		lmb_reserve(lmb, addr, size);
+	}
+}
+
+/**
+ * boot_relocate_fdt - relocate flat device tree
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @of_flat_tree: pointer to a char* variable, will hold fdt start address
+ * @of_size: pointer to a ulong variable, will hold fdt length
+ *
+ * boot_relocate_fdt() allocates a region of memory within the bootmap and
+ * relocates the of_flat_tree into that region, even if the fdt is already in
+ * the bootmap.  It also expands the size of the fdt by CONFIG_SYS_FDT_PAD
+ * bytes.
+ *
+ * of_flat_tree and of_size are set to final (after relocation) values
+ *
+ * returns:
+ *      0 - success
+ *      1 - failure
+ */
+int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size)
+{
+	void	*fdt_blob = *of_flat_tree;
+	void	*of_start = 0;
+	char	*fdt_high;
+	ulong	of_len = 0;
+	int	err;
+	int	disable_relocation = 0;
+
+	/* nothing to do */
+	if (*of_size == 0)
+		return 0;
+
+	if (fdt_check_header(fdt_blob) != 0) {
+		fdt_error("image is not a fdt");
+		goto error;
+	}
+
+	/* position on a 4K boundary before the alloc_current */
+	/* Pad the FDT by a specified amount */
+	of_len = *of_size + CONFIG_SYS_FDT_PAD;
+
+	/* If fdt_high is set use it to select the relocation address */
+	fdt_high = getenv("fdt_high");
+	if (fdt_high) {
+		void *desired_addr = (void *)simple_strtoul(fdt_high, NULL, 16);
+
+		if (((ulong) desired_addr) == ~0UL) {
+			/* All ones means use fdt in place */
+			of_start = fdt_blob;
+			lmb_reserve(lmb, (ulong)of_start, of_len);
+			disable_relocation = 1;
+		} else if (desired_addr) {
+			of_start =
+			    (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
+							   (ulong)desired_addr);
+			if (of_start == 0) {
+				puts("Failed using fdt_high value for Device Tree");
+				goto error;
+			}
+		} else {
+			of_start =
+			    (void *)(ulong) lmb_alloc(lmb, of_len, 0x1000);
+		}
+	} else {
+		of_start =
+		    (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
+						   getenv_bootm_mapsize()
+						   + getenv_bootm_low());
+	}
+
+	if (of_start == 0) {
+		puts("device tree - allocation error\n");
+		goto error;
+	}
+
+	if (disable_relocation) {
+		/* We assume there is space after the existing fdt to use for padding */
+		fdt_set_totalsize(of_start, of_len);
+		printf("   Using Device Tree in place at %p, end %p\n",
+		       of_start, of_start + of_len - 1);
+	} else {
+		debug("## device tree at %p ... %p (len=%ld [0x%lX])\n",
+			fdt_blob, fdt_blob + *of_size - 1, of_len, of_len);
+
+		printf("   Loading Device Tree to %p, end %p ... ",
+			of_start, of_start + of_len - 1);
+
+		err = fdt_open_into(fdt_blob, of_start, of_len);
+		if (err != 0) {
+			fdt_error("fdt move failed");
+			goto error;
+		}
+		puts("OK\n");
+	}
+
+	*of_flat_tree = of_start;
+	*of_size = of_len;
+
+	set_working_fdt_addr(*of_flat_tree);
+	return 0;
+
+error:
+	return 1;
+}
+#endif /* CONFIG_OF_LIBFDT */
+
+/**
+ * boot_get_fdt - main fdt handling routine
+ * @argc: command argument count
+ * @argv: command argument list
+ * @images: pointer to the bootm images structure
+ * @of_flat_tree: pointer to a char* variable, will hold fdt start address
+ * @of_size: pointer to a ulong variable, will hold fdt length
+ *
+ * boot_get_fdt() is responsible for finding a valid flat device tree image.
+ * Curently supported are the following ramdisk sources:
+ *      - multicomponent kernel/ramdisk image,
+ *      - commandline provided address of decicated ramdisk image.
+ *
+ * returns:
+ *     0, if fdt image was found and valid, or skipped
+ *     of_flat_tree and of_size are set to fdt start address and length if
+ *     fdt image is found and valid
+ *
+ *     1, if fdt image is found but corrupted
+ *     of_flat_tree and of_size are set to 0 if no fdt exists
+ */
+int boot_get_fdt(int flag, int argc, char * const argv[],
+		bootm_headers_t *images, char **of_flat_tree, ulong *of_size)
+{
+	const image_header_t *fdt_hdr;
+	ulong		fdt_addr;
+	char		*fdt_blob = NULL;
+	ulong		image_start, image_data, image_end;
+	ulong		load_start, load_end;
+#if defined(CONFIG_FIT)
+	void		*fit_hdr;
+	const char	*fit_uname_config = NULL;
+	const char	*fit_uname_fdt = NULL;
+	ulong		default_addr;
+	int		cfg_noffset;
+	int		fdt_noffset;
+	const void	*data;
+	size_t		size;
+#endif
+
+	*of_flat_tree = NULL;
+	*of_size = 0;
+
+	if (argc > 3 || genimg_has_config(images)) {
+#if defined(CONFIG_FIT)
+		if (argc > 3) {
+			/*
+			 * If the FDT blob comes from the FIT image and the
+			 * FIT image address is omitted in the command line
+			 * argument, try to use ramdisk or os FIT image
+			 * address or default load address.
+			 */
+			if (images->fit_uname_rd)
+				default_addr = (ulong)images->fit_hdr_rd;
+			else if (images->fit_uname_os)
+				default_addr = (ulong)images->fit_hdr_os;
+			else
+				default_addr = load_addr;
+
+			if (fit_parse_conf(argv[3], default_addr,
+						&fdt_addr, &fit_uname_config)) {
+				debug("*  fdt: config '%s' from image at "
+						"0x%08lx\n",
+						fit_uname_config, fdt_addr);
+			} else if (fit_parse_subimage(argv[3], default_addr,
+						&fdt_addr, &fit_uname_fdt)) {
+				debug("*  fdt: subimage '%s' from image at "
+						"0x%08lx\n",
+						fit_uname_fdt, fdt_addr);
+			} else
+#endif
+			{
+				fdt_addr = simple_strtoul(argv[3], NULL, 16);
+				debug("*  fdt: cmdline image address = "
+						"0x%08lx\n",
+						fdt_addr);
+			}
+#if defined(CONFIG_FIT)
+		} else {
+			/* use FIT configuration provided in first bootm
+			 * command argument
+			 */
+			fdt_addr = (ulong)images->fit_hdr_os;
+			fit_uname_config = images->fit_uname_cfg;
+			debug("*  fdt: using config '%s' from image "
+					"at 0x%08lx\n",
+					fit_uname_config, fdt_addr);
+
+			/*
+			 * Check whether configuration has FDT blob defined,
+			 * if not quit silently.
+			 */
+			fit_hdr = (void *)fdt_addr;
+			cfg_noffset = fit_conf_get_node(fit_hdr,
+					fit_uname_config);
+			if (cfg_noffset < 0) {
+				debug("*  fdt: no such config\n");
+				return 0;
+			}
+
+			fdt_noffset = fit_conf_get_fdt_node(fit_hdr,
+					cfg_noffset);
+			if (fdt_noffset < 0) {
+				debug("*  fdt: no fdt in config\n");
+				return 0;
+			}
+		}
+#endif
+
+		debug("## Checking for 'FDT'/'FDT Image' at %08lx\n",
+				fdt_addr);
+
+		/* copy from dataflash if needed */
+		fdt_addr = genimg_get_image(fdt_addr);
+
+		/*
+		 * Check if there is an FDT image at the
+		 * address provided in the second bootm argument
+		 * check image type, for FIT images get a FIT node.
+		 */
+		switch (genimg_get_format((void *)fdt_addr)) {
+		case IMAGE_FORMAT_LEGACY:
+			/* verify fdt_addr points to a valid image header */
+			printf("## Flattened Device Tree from Legacy Image "
+					"at %08lx\n",
+					fdt_addr);
+			fdt_hdr = image_get_fdt(fdt_addr);
+			if (!fdt_hdr)
+				goto error;
+
+			/*
+			 * move image data to the load address,
+			 * make sure we don't overwrite initial image
+			 */
+			image_start = (ulong)fdt_hdr;
+			image_data = (ulong)image_get_data(fdt_hdr);
+			image_end = image_get_image_end(fdt_hdr);
+
+			load_start = image_get_load(fdt_hdr);
+			load_end = load_start + image_get_data_size(fdt_hdr);
+
+			if (load_start == image_start ||
+			    load_start == image_data) {
+				fdt_blob = (char *)image_data;
+				break;
+			}
+
+			if ((load_start < image_end) && (load_end > image_start)) {
+				fdt_error("fdt overwritten");
+				goto error;
+			}
+
+			debug("   Loading FDT from 0x%08lx to 0x%08lx\n",
+					image_data, load_start);
+
+			memmove((void *)load_start,
+					(void *)image_data,
+					image_get_data_size(fdt_hdr));
+
+			fdt_blob = (char *)load_start;
+			break;
+		case IMAGE_FORMAT_FIT:
+			/*
+			 * This case will catch both: new uImage format
+			 * (libfdt based) and raw FDT blob (also libfdt
+			 * based).
+			 */
+#if defined(CONFIG_FIT)
+			/* check FDT blob vs FIT blob */
+			if (fit_check_format((const void *)fdt_addr)) {
+				/*
+				 * FIT image
+				 */
+				fit_hdr = (void *)fdt_addr;
+				printf("## Flattened Device Tree from FIT "
+						"Image at %08lx\n",
+						fdt_addr);
+
+				if (!fit_uname_fdt) {
+					/*
+					 * no FDT blob image node unit name,
+					 * try to get config node first. If
+					 * config unit node name is NULL
+					 * fit_conf_get_node() will try to
+					 * find default config node
+					 */
+					cfg_noffset = fit_conf_get_node(fit_hdr,
+							fit_uname_config);
+
+					if (cfg_noffset < 0) {
+						fdt_error("Could not find "
+							    "configuration "
+							    "node\n");
+						goto error;
+					}
+
+					fit_uname_config = fdt_get_name(fit_hdr,
+							cfg_noffset, NULL);
+					printf("   Using '%s' configuration\n",
+							fit_uname_config);
+
+					fdt_noffset = fit_conf_get_fdt_node(
+							fit_hdr,
+							cfg_noffset);
+					fit_uname_fdt = fit_get_name(fit_hdr,
+							fdt_noffset, NULL);
+				} else {
+					/* get FDT component image node offset */
+					fdt_noffset = fit_image_get_node(
+								fit_hdr,
+								fit_uname_fdt);
+				}
+				if (fdt_noffset < 0) {
+					fdt_error("Could not find subimage "
+							"node\n");
+					goto error;
+				}
+
+				printf("   Trying '%s' FDT blob subimage\n",
+						fit_uname_fdt);
+
+				if (!fit_check_fdt(fit_hdr, fdt_noffset,
+							images->verify))
+					goto error;
+
+				/* get ramdisk image data address and length */
+				if (fit_image_get_data(fit_hdr, fdt_noffset,
+							&data, &size)) {
+					fdt_error("Could not find FDT "
+							"subimage data");
+					goto error;
+				}
+
+				/* verift that image data is a proper FDT blob */
+				if (fdt_check_header((char *)data) != 0) {
+					fdt_error("Subimage data is not a FTD");
+					goto error;
+				}
+
+				/*
+				 * move image data to the load address,
+				 * make sure we don't overwrite initial image
+				 */
+				image_start = (ulong)fit_hdr;
+				image_end = fit_get_end(fit_hdr);
+
+				if (fit_image_get_load(fit_hdr, fdt_noffset,
+							&load_start) == 0) {
+					load_end = load_start + size;
+
+					if ((load_start < image_end) &&
+							(load_end > image_start)) {
+						fdt_error("FDT overwritten");
+						goto error;
+					}
+
+					printf("   Loading FDT from 0x%08lx "
+							"to 0x%08lx\n",
+							(ulong)data,
+							load_start);
+
+					memmove((void *)load_start,
+							(void *)data, size);
+
+					fdt_blob = (char *)load_start;
+				} else {
+					fdt_blob = (char *)data;
+				}
+
+				images->fit_hdr_fdt = fit_hdr;
+				images->fit_uname_fdt = fit_uname_fdt;
+				images->fit_noffset_fdt = fdt_noffset;
+				break;
+			} else
+#endif
+			{
+				/*
+				 * FDT blob
+				 */
+				fdt_blob = (char *)fdt_addr;
+				debug("*  fdt: raw FDT blob\n");
+				printf("## Flattened Device Tree blob at "
+					"%08lx\n", (long)fdt_blob);
+			}
+			break;
+		default:
+			puts("ERROR: Did not find a cmdline Flattened Device "
+				"Tree\n");
+			goto error;
+		}
+
+		printf("   Booting using the fdt blob at 0x%p\n", fdt_blob);
+
+	} else if (images->legacy_hdr_valid &&
+			image_check_type(&images->legacy_hdr_os_copy,
+						IH_TYPE_MULTI)) {
+
+		ulong fdt_data, fdt_len;
+
+		/*
+		 * Now check if we have a legacy multi-component image,
+		 * get second entry data start address and len.
+		 */
+		printf("## Flattened Device Tree from multi "
+			"component Image at %08lX\n",
+			(ulong)images->legacy_hdr_os);
+
+		image_multi_getimg(images->legacy_hdr_os, 2, &fdt_data,
+					&fdt_len);
+		if (fdt_len) {
+
+			fdt_blob = (char *)fdt_data;
+			printf("   Booting using the fdt at 0x%p\n", fdt_blob);
+
+			if (fdt_check_header(fdt_blob) != 0) {
+				fdt_error("image is not a fdt");
+				goto error;
+			}
+
+			if (fdt_totalsize(fdt_blob) != fdt_len) {
+				fdt_error("fdt size != image size");
+				goto error;
+			}
+		} else {
+			debug("## No Flattened Device Tree\n");
+			return 0;
+		}
+	} else {
+		debug("## No Flattened Device Tree\n");
+		return 0;
+	}
+
+	*of_flat_tree = fdt_blob;
+	*of_size = fdt_totalsize(fdt_blob);
+	debug("   of_flat_tree at 0x%08lx size 0x%08lx\n",
+			(ulong)*of_flat_tree, *of_size);
+
+	return 0;
+
+error:
+	*of_flat_tree = 0;
+	*of_size = 0;
+	return 1;
+}
+#endif /* CONFIG_OF_LIBFDT */
+
+#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
+/**
+ * boot_get_cmdline - allocate and initialize kernel cmdline
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @cmd_start: pointer to a ulong variable, will hold cmdline start
+ * @cmd_end: pointer to a ulong variable, will hold cmdline end
+ *
+ * boot_get_cmdline() allocates space for kernel command line below
+ * BOOTMAPSZ + getenv_bootm_low() address. If "bootargs" U-boot environemnt
+ * variable is present its contents is copied to allocated kernel
+ * command line.
+ *
+ * returns:
+ *      0 - success
+ *     -1 - failure
+ */
+int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end)
+{
+	char *cmdline;
+	char *s;
+
+	cmdline = (char *)(ulong)lmb_alloc_base(lmb, CONFIG_SYS_BARGSIZE, 0xf,
+				getenv_bootm_mapsize() + getenv_bootm_low());
+
+	if (cmdline == NULL)
+		return -1;
+
+	if ((s = getenv("bootargs")) == NULL)
+		s = "";
+
+	strcpy(cmdline, s);
+
+	*cmd_start = (ulong) & cmdline[0];
+	*cmd_end = *cmd_start + strlen(cmdline);
+
+	debug("## cmdline at 0x%08lx ... 0x%08lx\n", *cmd_start, *cmd_end);
+
+	return 0;
+}
+#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */
+
+#ifdef CONFIG_SYS_BOOT_GET_KBD
+/**
+ * boot_get_kbd - allocate and initialize kernel copy of board info
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @kbd: double pointer to board info data
+ *
+ * boot_get_kbd() allocates space for kernel copy of board info data below
+ * BOOTMAPSZ + getenv_bootm_low() address and kernel board info is initialized
+ * with the current u-boot board info data.
+ *
+ * returns:
+ *      0 - success
+ *     -1 - failure
+ */
+int boot_get_kbd(struct lmb *lmb, bd_t **kbd)
+{
+	*kbd = (bd_t *)(ulong)lmb_alloc_base(lmb, sizeof(bd_t), 0xf,
+				getenv_bootm_mapsize() + getenv_bootm_low());
+	if (*kbd == NULL)
+		return -1;
+
+	**kbd = *(gd->bd);
+
+	debug("## kernel board info at 0x%08lx\n", (ulong)*kbd);
+
+#if defined(DEBUG) && defined(CONFIG_CMD_BDI)
+	do_bdinfo(NULL, 0, 0, NULL);
+#endif
+
+	return 0;
+}
+#endif /* CONFIG_SYS_BOOT_GET_KBD */
+#endif /* !USE_HOSTCC */
+
+#if defined(CONFIG_FIT)
+/*****************************************************************************/
+/* New uImage format routines */
+/*****************************************************************************/
+#ifndef USE_HOSTCC
+static int fit_parse_spec(const char *spec, char sepc, ulong addr_curr,
+		ulong *addr, const char **name)
+{
+	const char *sep;
+
+	*addr = addr_curr;
+	*name = NULL;
+
+	sep = strchr(spec, sepc);
+	if (sep) {
+		if (sep - spec > 0)
+			*addr = simple_strtoul(spec, NULL, 16);
+
+		*name = sep + 1;
+		return 1;
+	}
+
+	return 0;
+}
+
+/**
+ * fit_parse_conf - parse FIT configuration spec
+ * @spec: input string, containing configuration spec
+ * @add_curr: current image address (to be used as a possible default)
+ * @addr: pointer to a ulong variable, will hold FIT image address of a given
+ * configuration
+ * @conf_name double pointer to a char, will hold pointer to a configuration
+ * unit name
+ *
+ * fit_parse_conf() expects configuration spec in the for of [<addr>]#<conf>,
+ * where <addr> is a FIT image address that contains configuration
+ * with a <conf> unit name.
+ *
+ * Address part is optional, and if omitted default add_curr will
+ * be used instead.
+ *
+ * returns:
+ *     1 if spec is a valid configuration string,
+ *     addr and conf_name are set accordingly
+ *     0 otherwise
+ */
+int fit_parse_conf(const char *spec, ulong addr_curr,
+		ulong *addr, const char **conf_name)
+{
+	return fit_parse_spec(spec, '#', addr_curr, addr, conf_name);
+}
+
+/**
+ * fit_parse_subimage - parse FIT subimage spec
+ * @spec: input string, containing subimage spec
+ * @add_curr: current image address (to be used as a possible default)
+ * @addr: pointer to a ulong variable, will hold FIT image address of a given
+ * subimage
+ * @image_name: double pointer to a char, will hold pointer to a subimage name
+ *
+ * fit_parse_subimage() expects subimage spec in the for of
+ * [<addr>]:<subimage>, where <addr> is a FIT image address that contains
+ * subimage with a <subimg> unit name.
+ *
+ * Address part is optional, and if omitted default add_curr will
+ * be used instead.
+ *
+ * returns:
+ *     1 if spec is a valid subimage string,
+ *     addr and image_name are set accordingly
+ *     0 otherwise
+ */
+int fit_parse_subimage(const char *spec, ulong addr_curr,
+		ulong *addr, const char **image_name)
+{
+	return fit_parse_spec(spec, ':', addr_curr, addr, image_name);
+}
+#endif /* !USE_HOSTCC */
+
+static void fit_get_debug(const void *fit, int noffset,
+		char *prop_name, int err)
+{
+	debug("Can't get '%s' property from FIT 0x%08lx, "
+		"node: offset %d, name %s (%s)\n",
+		prop_name, (ulong)fit, noffset,
+		fit_get_name(fit, noffset, NULL),
+		fdt_strerror(err));
+}
+
+/**
+ * fit_print_contents - prints out the contents of the FIT format image
+ * @fit: pointer to the FIT format image header
+ * @p: pointer to prefix string
+ *
+ * fit_print_contents() formats a multi line FIT image contents description.
+ * The routine prints out FIT image properties (root node level) follwed by
+ * the details of each component image.
+ *
+ * returns:
+ *     no returned results
+ */
+void fit_print_contents(const void *fit)
+{
+	char *desc;
+	char *uname;
+	int images_noffset;
+	int confs_noffset;
+	int noffset;
+	int ndepth;
+	int count = 0;
+	int ret;
+	const char *p;
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
+	time_t timestamp;
+#endif
+
+#ifdef USE_HOSTCC
+	p = "";
+#else
+	p = "   ";
+#endif
+
+	/* Root node properties */
+	ret = fit_get_desc(fit, 0, &desc);
+	printf("%sFIT description: ", p);
+	if (ret)
+		printf("unavailable\n");
+	else
+		printf("%s\n", desc);
+
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
+	ret = fit_get_timestamp(fit, 0, &timestamp);
+	printf("%sCreated:         ", p);
+	if (ret)
+		printf("unavailable\n");
+	else
+		genimg_print_time(timestamp);
+#endif
+
+	/* Find images parent node offset */
+	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (images_noffset < 0) {
+		printf("Can't find images parent node '%s' (%s)\n",
+			FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+		return;
+	}
+
+	/* Process its subnodes, print out component images details */
+	for (ndepth = 0, count = 0,
+		noffset = fdt_next_node(fit, images_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/*
+			 * Direct child node of the images parent node,
+			 * i.e. component image node.
+			 */
+			printf("%s Image %u (%s)\n", p, count++,
+					fit_get_name(fit, noffset, NULL));
+
+			fit_image_print(fit, noffset, p);
+		}
+	}
+
+	/* Find configurations parent node offset */
+	confs_noffset = fdt_path_offset(fit, FIT_CONFS_PATH);
+	if (confs_noffset < 0) {
+		debug("Can't get configurations parent node '%s' (%s)\n",
+			FIT_CONFS_PATH, fdt_strerror(confs_noffset));
+		return;
+	}
+
+	/* get default configuration unit name from default property */
+	uname = (char *)fdt_getprop(fit, noffset, FIT_DEFAULT_PROP, NULL);
+	if (uname)
+		printf("%s Default Configuration: '%s'\n", p, uname);
+
+	/* Process its subnodes, print out configurations details */
+	for (ndepth = 0, count = 0,
+		noffset = fdt_next_node(fit, confs_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/*
+			 * Direct child node of the configurations parent node,
+			 * i.e. configuration node.
+			 */
+			printf("%s Configuration %u (%s)\n", p, count++,
+					fit_get_name(fit, noffset, NULL));
+
+			fit_conf_print(fit, noffset, p);
+		}
+	}
+}
+
+/**
+ * fit_image_print - prints out the FIT component image details
+ * @fit: pointer to the FIT format image header
+ * @image_noffset: offset of the component image node
+ * @p: pointer to prefix string
+ *
+ * fit_image_print() lists all mandatory properies for the processed component
+ * image. If present, hash nodes are printed out as well. Load
+ * address for images of type firmware is also printed out. Since the load
+ * address is not mandatory for firmware images, it will be output as
+ * "unavailable" when not present.
+ *
+ * returns:
+ *     no returned results
+ */
+void fit_image_print(const void *fit, int image_noffset, const char *p)
+{
+	char *desc;
+	uint8_t type, arch, os, comp;
+	size_t size;
+	ulong load, entry;
+	const void *data;
+	int noffset;
+	int ndepth;
+	int ret;
+
+	/* Mandatory properties */
+	ret = fit_get_desc(fit, image_noffset, &desc);
+	printf("%s  Description:  ", p);
+	if (ret)
+		printf("unavailable\n");
+	else
+		printf("%s\n", desc);
+
+	fit_image_get_type(fit, image_noffset, &type);
+	printf("%s  Type:         %s\n", p, genimg_get_type_name(type));
+
+	fit_image_get_comp(fit, image_noffset, &comp);
+	printf("%s  Compression:  %s\n", p, genimg_get_comp_name(comp));
+
+	ret = fit_image_get_data(fit, image_noffset, &data, &size);
+
+#ifndef USE_HOSTCC
+	printf("%s  Data Start:   ", p);
+	if (ret)
+		printf("unavailable\n");
+	else
+		printf("0x%08lx\n", (ulong)data);
+#endif
+
+	printf("%s  Data Size:    ", p);
+	if (ret)
+		printf("unavailable\n");
+	else
+		genimg_print_size(size);
+
+	/* Remaining, type dependent properties */
+	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
+	    (type == IH_TYPE_RAMDISK) || (type == IH_TYPE_FIRMWARE) ||
+	    (type == IH_TYPE_FLATDT)) {
+		fit_image_get_arch(fit, image_noffset, &arch);
+		printf("%s  Architecture: %s\n", p, genimg_get_arch_name(arch));
+	}
+
+	if (type == IH_TYPE_KERNEL) {
+		fit_image_get_os(fit, image_noffset, &os);
+		printf("%s  OS:           %s\n", p, genimg_get_os_name(os));
+	}
+
+	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
+		(type == IH_TYPE_FIRMWARE)) {
+		ret = fit_image_get_load(fit, image_noffset, &load);
+		printf("%s  Load Address: ", p);
+		if (ret)
+			printf("unavailable\n");
+		else
+			printf("0x%08lx\n", load);
+	}
+
+	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE)) {
+		fit_image_get_entry(fit, image_noffset, &entry);
+		printf("%s  Entry Point:  ", p);
+		if (ret)
+			printf("unavailable\n");
+		else
+			printf("0x%08lx\n", entry);
+	}
+
+	/* Process all hash subnodes of the component image node */
+	for (ndepth = 0, noffset = fdt_next_node(fit, image_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/* Direct child node of the component image node */
+			fit_image_print_hash(fit, noffset, p);
+		}
+	}
+}
+
+/**
+ * fit_image_print_hash - prints out the hash node details
+ * @fit: pointer to the FIT format image header
+ * @noffset: offset of the hash node
+ * @p: pointer to prefix string
+ *
+ * fit_image_print_hash() lists properies for the processed hash node
+ *
+ * returns:
+ *     no returned results
+ */
+void fit_image_print_hash(const void *fit, int noffset, const char *p)
+{
+	char *algo;
+	uint8_t *value;
+	int value_len;
+	int i, ret;
+
+	/*
+	 * Check subnode name, must be equal to "hash".
+	 * Multiple hash nodes require unique unit node
+	 * names, e.g. hash@1, hash@2, etc.
+	 */
+	if (strncmp(fit_get_name(fit, noffset, NULL),
+			FIT_HASH_NODENAME,
+			strlen(FIT_HASH_NODENAME)) != 0)
+		return;
+
+	debug("%s  Hash node:    '%s'\n", p,
+			fit_get_name(fit, noffset, NULL));
+
+	printf("%s  Hash algo:    ", p);
+	if (fit_image_hash_get_algo(fit, noffset, &algo)) {
+		printf("invalid/unsupported\n");
+		return;
+	}
+	printf("%s\n", algo);
+
+	ret = fit_image_hash_get_value(fit, noffset, &value,
+					&value_len);
+	printf("%s  Hash value:   ", p);
+	if (ret) {
+		printf("unavailable\n");
+	} else {
+		for (i = 0; i < value_len; i++)
+			printf("%02x", value[i]);
+		printf("\n");
+	}
+
+	debug("%s  Hash len:     %d\n", p, value_len);
+}
+
+/**
+ * fit_get_desc - get node description property
+ * @fit: pointer to the FIT format image header
+ * @noffset: node offset
+ * @desc: double pointer to the char, will hold pointer to the descrption
+ *
+ * fit_get_desc() reads description property from a given node, if
+ * description is found pointer to it is returened in third call argument.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_get_desc(const void *fit, int noffset, char **desc)
+{
+	int len;
+
+	*desc = (char *)fdt_getprop(fit, noffset, FIT_DESC_PROP, &len);
+	if (*desc == NULL) {
+		fit_get_debug(fit, noffset, FIT_DESC_PROP, len);
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * fit_get_timestamp - get node timestamp property
+ * @fit: pointer to the FIT format image header
+ * @noffset: node offset
+ * @timestamp: pointer to the time_t, will hold read timestamp
+ *
+ * fit_get_timestamp() reads timestamp poperty from given node, if timestamp
+ * is found and has a correct size its value is retured in third call
+ * argument.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on property read failure
+ *     -2, on wrong timestamp size
+ */
+int fit_get_timestamp(const void *fit, int noffset, time_t *timestamp)
+{
+	int len;
+	const void *data;
+
+	data = fdt_getprop(fit, noffset, FIT_TIMESTAMP_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_TIMESTAMP_PROP, len);
+		return -1;
+	}
+	if (len != sizeof(uint32_t)) {
+		debug("FIT timestamp with incorrect size of (%u)\n", len);
+		return -2;
+	}
+
+	*timestamp = uimage_to_cpu(*((uint32_t *)data));
+	return 0;
+}
+
+/**
+ * fit_image_get_node - get node offset for component image of a given unit name
+ * @fit: pointer to the FIT format image header
+ * @image_uname: component image node unit name
+ *
+ * fit_image_get_node() finds a component image (withing the '/images'
+ * node) of a provided unit name. If image is found its node offset is
+ * returned to the caller.
+ *
+ * returns:
+ *     image node offset when found (>=0)
+ *     negative number on failure (FDT_ERR_* code)
+ */
+int fit_image_get_node(const void *fit, const char *image_uname)
+{
+	int noffset, images_noffset;
+
+	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (images_noffset < 0) {
+		debug("Can't find images parent node '%s' (%s)\n",
+			FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+		return images_noffset;
+	}
+
+	noffset = fdt_subnode_offset(fit, images_noffset, image_uname);
+	if (noffset < 0) {
+		debug("Can't get node offset for image unit name: '%s' (%s)\n",
+			image_uname, fdt_strerror(noffset));
+	}
+
+	return noffset;
+}
+
+/**
+ * fit_image_get_os - get os id for a given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @os: pointer to the uint8_t, will hold os numeric id
+ *
+ * fit_image_get_os() finds os property in a given component image node.
+ * If the property is found, its (string) value is translated to the numeric
+ * id which is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_os(const void *fit, int noffset, uint8_t *os)
+{
+	int len;
+	const void *data;
+
+	/* Get OS name from property data */
+	data = fdt_getprop(fit, noffset, FIT_OS_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_OS_PROP, len);
+		*os = -1;
+		return -1;
+	}
+
+	/* Translate OS name to id */
+	*os = genimg_get_os_id(data);
+	return 0;
+}
+
+/**
+ * fit_image_get_arch - get arch id for a given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @arch: pointer to the uint8_t, will hold arch numeric id
+ *
+ * fit_image_get_arch() finds arch property in a given component image node.
+ * If the property is found, its (string) value is translated to the numeric
+ * id which is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_arch(const void *fit, int noffset, uint8_t *arch)
+{
+	int len;
+	const void *data;
+
+	/* Get architecture name from property data */
+	data = fdt_getprop(fit, noffset, FIT_ARCH_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_ARCH_PROP, len);
+		*arch = -1;
+		return -1;
+	}
+
+	/* Translate architecture name to id */
+	*arch = genimg_get_arch_id(data);
+	return 0;
+}
+
+/**
+ * fit_image_get_type - get type id for a given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @type: pointer to the uint8_t, will hold type numeric id
+ *
+ * fit_image_get_type() finds type property in a given component image node.
+ * If the property is found, its (string) value is translated to the numeric
+ * id which is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_type(const void *fit, int noffset, uint8_t *type)
+{
+	int len;
+	const void *data;
+
+	/* Get image type name from property data */
+	data = fdt_getprop(fit, noffset, FIT_TYPE_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_TYPE_PROP, len);
+		*type = -1;
+		return -1;
+	}
+
+	/* Translate image type name to id */
+	*type = genimg_get_type_id(data);
+	return 0;
+}
+
+/**
+ * fit_image_get_comp - get comp id for a given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @comp: pointer to the uint8_t, will hold comp numeric id
+ *
+ * fit_image_get_comp() finds comp property in a given component image node.
+ * If the property is found, its (string) value is translated to the numeric
+ * id which is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_comp(const void *fit, int noffset, uint8_t *comp)
+{
+	int len;
+	const void *data;
+
+	/* Get compression name from property data */
+	data = fdt_getprop(fit, noffset, FIT_COMP_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_COMP_PROP, len);
+		*comp = -1;
+		return -1;
+	}
+
+	/* Translate compression name to id */
+	*comp = genimg_get_comp_id(data);
+	return 0;
+}
+
+/**
+ * fit_image_get_load - get load address property for a given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @load: pointer to the uint32_t, will hold load address
+ *
+ * fit_image_get_load() finds load address property in a given component image node.
+ * If the property is found, its value is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_load(const void *fit, int noffset, ulong *load)
+{
+	int len;
+	const uint32_t *data;
+
+	data = fdt_getprop(fit, noffset, FIT_LOAD_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_LOAD_PROP, len);
+		return -1;
+	}
+
+	*load = uimage_to_cpu(*data);
+	return 0;
+}
+
+/**
+ * fit_image_get_entry - get entry point address property for a given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @entry: pointer to the uint32_t, will hold entry point address
+ *
+ * fit_image_get_entry() finds entry point address property in a given component image node.
+ * If the property is found, its value is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_entry(const void *fit, int noffset, ulong *entry)
+{
+	int len;
+	const uint32_t *data;
+
+	data = fdt_getprop(fit, noffset, FIT_ENTRY_PROP, &len);
+	if (data == NULL) {
+		fit_get_debug(fit, noffset, FIT_ENTRY_PROP, len);
+		return -1;
+	}
+
+	*entry = uimage_to_cpu(*data);
+	return 0;
+}
+
+/**
+ * fit_image_get_data - get data property and its size for a given component image node
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @data: double pointer to void, will hold data property's data address
+ * @size: pointer to size_t, will hold data property's data size
+ *
+ * fit_image_get_data() finds data property in a given component image node.
+ * If the property is found its data start address and size are returned to
+ * the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_get_data(const void *fit, int noffset,
+		const void **data, size_t *size)
+{
+	int len;
+
+	*data = fdt_getprop(fit, noffset, FIT_DATA_PROP, &len);
+	if (*data == NULL) {
+		fit_get_debug(fit, noffset, FIT_DATA_PROP, len);
+		*size = 0;
+		return -1;
+	}
+
+	*size = len;
+	return 0;
+}
+
+/**
+ * fit_image_hash_get_algo - get hash algorithm name
+ * @fit: pointer to the FIT format image header
+ * @noffset: hash node offset
+ * @algo: double pointer to char, will hold pointer to the algorithm name
+ *
+ * fit_image_hash_get_algo() finds hash algorithm property in a given hash node.
+ * If the property is found its data start address is returned to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_hash_get_algo(const void *fit, int noffset, char **algo)
+{
+	int len;
+
+	*algo = (char *)fdt_getprop(fit, noffset, FIT_ALGO_PROP, &len);
+	if (*algo == NULL) {
+		fit_get_debug(fit, noffset, FIT_ALGO_PROP, len);
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * fit_image_hash_get_value - get hash value and length
+ * @fit: pointer to the FIT format image header
+ * @noffset: hash node offset
+ * @value: double pointer to uint8_t, will hold address of a hash value data
+ * @value_len: pointer to an int, will hold hash data length
+ *
+ * fit_image_hash_get_value() finds hash value property in a given hash node.
+ * If the property is found its data start address and size are returned to
+ * the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
+				int *value_len)
+{
+	int len;
+
+	*value = (uint8_t *)fdt_getprop(fit, noffset, FIT_VALUE_PROP, &len);
+	if (*value == NULL) {
+		fit_get_debug(fit, noffset, FIT_VALUE_PROP, len);
+		*value_len = 0;
+		return -1;
+	}
+
+	*value_len = len;
+	return 0;
+}
+
+/**
+ * fit_set_timestamp - set node timestamp property
+ * @fit: pointer to the FIT format image header
+ * @noffset: node offset
+ * @timestamp: timestamp value to be set
+ *
+ * fit_set_timestamp() attempts to set timestamp property in the requested
+ * node and returns operation status to the caller.
+ *
+ * returns:
+ *     0, on success
+ *     -1, on property read failure
+ */
+int fit_set_timestamp(void *fit, int noffset, time_t timestamp)
+{
+	uint32_t t;
+	int ret;
+
+	t = cpu_to_uimage(timestamp);
+	ret = fdt_setprop(fit, noffset, FIT_TIMESTAMP_PROP, &t,
+				sizeof(uint32_t));
+	if (ret) {
+		printf("Can't set '%s' property for '%s' node (%s)\n",
+			FIT_TIMESTAMP_PROP, fit_get_name(fit, noffset, NULL),
+			fdt_strerror(ret));
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * calculate_hash - calculate and return hash for provided input data
+ * @data: pointer to the input data
+ * @data_len: data length
+ * @algo: requested hash algorithm
+ * @value: pointer to the char, will hold hash value data (caller must
+ * allocate enough free space)
+ * value_len: length of the calculated hash
+ *
+ * calculate_hash() computes input data hash according to the requested algorithm.
+ * Resulting hash value is placed in caller provided 'value' buffer, length
+ * of the calculated hash is returned via value_len pointer argument.
+ *
+ * returns:
+ *     0, on success
+ *    -1, when algo is unsupported
+ */
+static int calculate_hash(const void *data, int data_len, const char *algo,
+			uint8_t *value, int *value_len)
+{
+	if (strcmp(algo, "crc32") == 0) {
+		*((uint32_t *)value) = crc32_wd(0, data, data_len,
+							CHUNKSZ_CRC32);
+		*((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value));
+		*value_len = 4;
+	} else if (strcmp(algo, "sha1") == 0) {
+		sha1_csum_wd((unsigned char *) data, data_len,
+				(unsigned char *) value, CHUNKSZ_SHA1);
+		*value_len = 20;
+	} else if (strcmp(algo, "md5") == 0) {
+		md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5);
+		*value_len = 16;
+	} else {
+		debug("Unsupported hash alogrithm\n");
+		return -1;
+	}
+	return 0;
+}
+
+#ifdef USE_HOSTCC
+/**
+ * fit_set_hashes - process FIT component image nodes and calculate hashes
+ * @fit: pointer to the FIT format image header
+ *
+ * fit_set_hashes() adds hash values for all component images in the FIT blob.
+ * Hashes are calculated for all component images which have hash subnodes
+ * with algorithm property set to one of the supported hash algorithms.
+ *
+ * returns
+ *     0, on success
+ *     libfdt error code, on failure
+ */
+int fit_set_hashes(void *fit)
+{
+	int images_noffset;
+	int noffset;
+	int ndepth;
+	int ret;
+
+	/* Find images parent node offset */
+	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (images_noffset < 0) {
+		printf("Can't find images parent node '%s' (%s)\n",
+			FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+		return images_noffset;
+	}
+
+	/* Process its subnodes, print out component images details */
+	for (ndepth = 0, noffset = fdt_next_node(fit, images_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/*
+			 * Direct child node of the images parent node,
+			 * i.e. component image node.
+			 */
+			ret = fit_image_set_hashes(fit, noffset);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * fit_image_set_hashes - calculate/set hashes for given component image node
+ * @fit: pointer to the FIT format image header
+ * @image_noffset: requested component image node
+ *
+ * fit_image_set_hashes() adds hash values for an component image node. All
+ * existing hash subnodes are checked, if algorithm property is set to one of
+ * the supported hash algorithms, hash value is computed and corresponding
+ * hash node property is set, for example:
+ *
+ * Input component image node structure:
+ *
+ * o image@1 (at image_noffset)
+ *   | - data = [binary data]
+ *   o hash@1
+ *     |- algo = "sha1"
+ *
+ * Output component image node structure:
+ *
+ * o image@1 (at image_noffset)
+ *   | - data = [binary data]
+ *   o hash@1
+ *     |- algo = "sha1"
+ *     |- value = sha1(data)
+ *
+ * returns:
+ *     0 on sucess
+ *    <0 on failure
+ */
+int fit_image_set_hashes(void *fit, int image_noffset)
+{
+	const void *data;
+	size_t size;
+	char *algo;
+	uint8_t value[FIT_MAX_HASH_LEN];
+	int value_len;
+	int noffset;
+	int ndepth;
+
+	/* Get image data and data length */
+	if (fit_image_get_data(fit, image_noffset, &data, &size)) {
+		printf("Can't get image data/size\n");
+		return -1;
+	}
+
+	/* Process all hash subnodes of the component image node */
+	for (ndepth = 0, noffset = fdt_next_node(fit, image_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/* Direct child node of the component image node */
+
+			/*
+			 * Check subnode name, must be equal to "hash".
+			 * Multiple hash nodes require unique unit node
+			 * names, e.g. hash@1, hash@2, etc.
+			 */
+			if (strncmp(fit_get_name(fit, noffset, NULL),
+						FIT_HASH_NODENAME,
+						strlen(FIT_HASH_NODENAME)) != 0) {
+				/* Not a hash subnode, skip it */
+				continue;
+			}
+
+			if (fit_image_hash_get_algo(fit, noffset, &algo)) {
+				printf("Can't get hash algo property for "
+					"'%s' hash node in '%s' image node\n",
+					fit_get_name(fit, noffset, NULL),
+					fit_get_name(fit, image_noffset, NULL));
+				return -1;
+			}
+
+			if (calculate_hash(data, size, algo, value,
+						&value_len)) {
+				printf("Unsupported hash algorithm (%s) for "
+					"'%s' hash node in '%s' image node\n",
+					algo, fit_get_name(fit, noffset, NULL),
+					fit_get_name(fit, image_noffset,
+							NULL));
+				return -1;
+			}
+
+			if (fit_image_hash_set_value(fit, noffset, value,
+							value_len)) {
+				printf("Can't set hash value for "
+					"'%s' hash node in '%s' image node\n",
+					fit_get_name(fit, noffset, NULL),
+					fit_get_name(fit, image_noffset, NULL));
+				return -1;
+			}
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * fit_image_hash_set_value - set hash value in requested has node
+ * @fit: pointer to the FIT format image header
+ * @noffset: hash node offset
+ * @value: hash value to be set
+ * @value_len: hash value length
+ *
+ * fit_image_hash_set_value() attempts to set hash value in a node at offset
+ * given and returns operation status to the caller.
+ *
+ * returns
+ *     0, on success
+ *     -1, on failure
+ */
+int fit_image_hash_set_value(void *fit, int noffset, uint8_t *value,
+				int value_len)
+{
+	int ret;
+
+	ret = fdt_setprop(fit, noffset, FIT_VALUE_PROP, value, value_len);
+	if (ret) {
+		printf("Can't set hash '%s' property for '%s' node(%s)\n",
+			FIT_VALUE_PROP, fit_get_name(fit, noffset, NULL),
+			fdt_strerror(ret));
+		return -1;
+	}
+
+	return 0;
+}
+#endif /* USE_HOSTCC */
+
+/**
+ * fit_image_check_hashes - verify data intergity
+ * @fit: pointer to the FIT format image header
+ * @image_noffset: component image node offset
+ *
+ * fit_image_check_hashes() goes over component image hash nodes,
+ * re-calculates each data hash and compares with the value stored in hash
+ * node.
+ *
+ * returns:
+ *     1, if all hashes are valid
+ *     0, otherwise (or on error)
+ */
+int fit_image_check_hashes(const void *fit, int image_noffset)
+{
+	const void	*data;
+	size_t		size;
+	char		*algo;
+	uint8_t		*fit_value;
+	int		fit_value_len;
+	uint8_t		value[FIT_MAX_HASH_LEN];
+	int		value_len;
+	int		noffset;
+	int		ndepth;
+	char		*err_msg = "";
+
+	/* Get image data and data length */
+	if (fit_image_get_data(fit, image_noffset, &data, &size)) {
+		printf("Can't get image data/size\n");
+		return 0;
+	}
+
+	/* Process all hash subnodes of the component image node */
+	for (ndepth = 0, noffset = fdt_next_node(fit, image_noffset, &ndepth);
+	     (noffset >= 0) && (ndepth > 0);
+	     noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/* Direct child node of the component image node */
+
+			/*
+			 * Check subnode name, must be equal to "hash".
+			 * Multiple hash nodes require unique unit node
+			 * names, e.g. hash@1, hash@2, etc.
+			 */
+			if (strncmp(fit_get_name(fit, noffset, NULL),
+					FIT_HASH_NODENAME,
+					strlen(FIT_HASH_NODENAME)) != 0)
+				continue;
+
+			if (fit_image_hash_get_algo(fit, noffset, &algo)) {
+				err_msg = " error!\nCan't get hash algo "
+						"property";
+				goto error;
+			}
+			printf("%s", algo);
+
+			if (fit_image_hash_get_value(fit, noffset, &fit_value,
+							&fit_value_len)) {
+				err_msg = " error!\nCan't get hash value "
+						"property";
+				goto error;
+			}
+
+			if (calculate_hash(data, size, algo, value,
+						&value_len)) {
+				err_msg = " error!\n"
+						"Unsupported hash algorithm";
+				goto error;
+			}
+
+			if (value_len != fit_value_len) {
+				err_msg = " error !\nBad hash value len";
+				goto error;
+			} else if (memcmp(value, fit_value, value_len) != 0) {
+				err_msg = " error!\nBad hash value";
+				goto error;
+			}
+			printf("+ ");
+		}
+	}
+
+	return 1;
+
+error:
+	printf("%s for '%s' hash node in '%s' image node\n",
+			err_msg, fit_get_name(fit, noffset, NULL),
+			fit_get_name(fit, image_noffset, NULL));
+	return 0;
+}
+
+/**
+ * fit_all_image_check_hashes - verify data intergity for all images
+ * @fit: pointer to the FIT format image header
+ *
+ * fit_all_image_check_hashes() goes over all images in the FIT and
+ * for every images checks if all it's hashes are valid.
+ *
+ * returns:
+ *     1, if all hashes of all images are valid
+ *     0, otherwise (or on error)
+ */
+int fit_all_image_check_hashes(const void *fit)
+{
+	int images_noffset;
+	int noffset;
+	int ndepth;
+	int count;
+
+	/* Find images parent node offset */
+	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (images_noffset < 0) {
+		printf("Can't find images parent node '%s' (%s)\n",
+			FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+		return 0;
+	}
+
+	/* Process all image subnodes, check hashes for each */
+	printf("## Checking hash(es) for FIT Image at %08lx ...\n",
+		(ulong)fit);
+	for (ndepth = 0, count = 0,
+		noffset = fdt_next_node(fit, images_noffset, &ndepth);
+		(noffset >= 0) && (ndepth > 0);
+		noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/*
+			 * Direct child node of the images parent node,
+			 * i.e. component image node.
+			 */
+			printf("   Hash(es) for Image %u (%s): ", count++,
+					fit_get_name(fit, noffset, NULL));
+
+			if (!fit_image_check_hashes(fit, noffset))
+				return 0;
+			printf("\n");
+		}
+	}
+	return 1;
+}
+
+/**
+ * fit_image_check_os - check whether image node is of a given os type
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @os: requested image os
+ *
+ * fit_image_check_os() reads image os property and compares its numeric
+ * id with the requested os. Comparison result is returned to the caller.
+ *
+ * returns:
+ *     1 if image is of given os type
+ *     0 otherwise (or on error)
+ */
+int fit_image_check_os(const void *fit, int noffset, uint8_t os)
+{
+	uint8_t image_os;
+
+	if (fit_image_get_os(fit, noffset, &image_os))
+		return 0;
+	return (os == image_os);
+}
+
+/**
+ * fit_image_check_arch - check whether image node is of a given arch
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @arch: requested imagearch
+ *
+ * fit_image_check_arch() reads image arch property and compares its numeric
+ * id with the requested arch. Comparison result is returned to the caller.
+ *
+ * returns:
+ *     1 if image is of given arch
+ *     0 otherwise (or on error)
+ */
+int fit_image_check_arch(const void *fit, int noffset, uint8_t arch)
+{
+	uint8_t image_arch;
+
+	if (fit_image_get_arch(fit, noffset, &image_arch))
+		return 0;
+	return (arch == image_arch);
+}
+
+/**
+ * fit_image_check_type - check whether image node is of a given type
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @type: requested image type
+ *
+ * fit_image_check_type() reads image type property and compares its numeric
+ * id with the requested type. Comparison result is returned to the caller.
+ *
+ * returns:
+ *     1 if image is of given type
+ *     0 otherwise (or on error)
+ */
+int fit_image_check_type(const void *fit, int noffset, uint8_t type)
+{
+	uint8_t image_type;
+
+	if (fit_image_get_type(fit, noffset, &image_type))
+		return 0;
+	return (type == image_type);
+}
+
+/**
+ * fit_image_check_comp - check whether image node uses given compression
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @comp: requested image compression type
+ *
+ * fit_image_check_comp() reads image compression property and compares its
+ * numeric id with the requested compression type. Comparison result is
+ * returned to the caller.
+ *
+ * returns:
+ *     1 if image uses requested compression
+ *     0 otherwise (or on error)
+ */
+int fit_image_check_comp(const void *fit, int noffset, uint8_t comp)
+{
+	uint8_t image_comp;
+
+	if (fit_image_get_comp(fit, noffset, &image_comp))
+		return 0;
+	return (comp == image_comp);
+}
+
+/**
+ * fit_check_format - sanity check FIT image format
+ * @fit: pointer to the FIT format image header
+ *
+ * fit_check_format() runs a basic sanity FIT image verification.
+ * Routine checks for mandatory properties, nodes, etc.
+ *
+ * returns:
+ *     1, on success
+ *     0, on failure
+ */
+int fit_check_format(const void *fit)
+{
+	/* mandatory / node 'description' property */
+	if (fdt_getprop(fit, 0, FIT_DESC_PROP, NULL) == NULL) {
+		debug("Wrong FIT format: no description\n");
+		return 0;
+	}
+
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
+	/* mandatory / node 'timestamp' property */
+	if (fdt_getprop(fit, 0, FIT_TIMESTAMP_PROP, NULL) == NULL) {
+		debug("Wrong FIT format: no timestamp\n");
+		return 0;
+	}
+#endif
+
+	/* mandatory subimages parent '/images' node */
+	if (fdt_path_offset(fit, FIT_IMAGES_PATH) < 0) {
+		debug("Wrong FIT format: no images parent node\n");
+		return 0;
+	}
+
+	return 1;
+}
+
+/**
+ * fit_conf_get_node - get node offset for configuration of a given unit name
+ * @fit: pointer to the FIT format image header
+ * @conf_uname: configuration node unit name
+ *
+ * fit_conf_get_node() finds a configuration (withing the '/configurations'
+ * parant node) of a provided unit name. If configuration is found its node offset
+ * is returned to the caller.
+ *
+ * When NULL is provided in second argument fit_conf_get_node() will search
+ * for a default configuration node instead. Default configuration node unit name
+ * is retrived from FIT_DEFAULT_PROP property of the '/configurations' node.
+ *
+ * returns:
+ *     configuration node offset when found (>=0)
+ *     negative number on failure (FDT_ERR_* code)
+ */
+int fit_conf_get_node(const void *fit, const char *conf_uname)
+{
+	int noffset, confs_noffset;
+	int len;
+
+	confs_noffset = fdt_path_offset(fit, FIT_CONFS_PATH);
+	if (confs_noffset < 0) {
+		debug("Can't find configurations parent node '%s' (%s)\n",
+			FIT_CONFS_PATH, fdt_strerror(confs_noffset));
+		return confs_noffset;
+	}
+
+	if (conf_uname == NULL) {
+		/* get configuration unit name from the default property */
+		debug("No configuration specified, trying default...\n");
+		conf_uname = (char *)fdt_getprop(fit, confs_noffset,
+						 FIT_DEFAULT_PROP, &len);
+		if (conf_uname == NULL) {
+			fit_get_debug(fit, confs_noffset, FIT_DEFAULT_PROP,
+					len);
+			return len;
+		}
+		debug("Found default configuration: '%s'\n", conf_uname);
+	}
+
+	noffset = fdt_subnode_offset(fit, confs_noffset, conf_uname);
+	if (noffset < 0) {
+		debug("Can't get node offset for configuration unit name: "
+			"'%s' (%s)\n",
+			conf_uname, fdt_strerror(noffset));
+	}
+
+	return noffset;
+}
+
+static int __fit_conf_get_prop_node(const void *fit, int noffset,
+		const char *prop_name)
+{
+	char *uname;
+	int len;
+
+	/* get kernel image unit name from configuration kernel property */
+	uname = (char *)fdt_getprop(fit, noffset, prop_name, &len);
+	if (uname == NULL)
+		return len;
+
+	return fit_image_get_node(fit, uname);
+}
+
+/**
+ * fit_conf_get_kernel_node - get kernel image node offset that corresponds to
+ * a given configuration
+ * @fit: pointer to the FIT format image header
+ * @noffset: configuration node offset
+ *
+ * fit_conf_get_kernel_node() retrives kernel image node unit name from
+ * configuration FIT_KERNEL_PROP property and translates it to the node
+ * offset.
+ *
+ * returns:
+ *     image node offset when found (>=0)
+ *     negative number on failure (FDT_ERR_* code)
+ */
+int fit_conf_get_kernel_node(const void *fit, int noffset)
+{
+	return __fit_conf_get_prop_node(fit, noffset, FIT_KERNEL_PROP);
+}
+
+/**
+ * fit_conf_get_ramdisk_node - get ramdisk image node offset that corresponds to
+ * a given configuration
+ * @fit: pointer to the FIT format image header
+ * @noffset: configuration node offset
+ *
+ * fit_conf_get_ramdisk_node() retrives ramdisk image node unit name from
+ * configuration FIT_KERNEL_PROP property and translates it to the node
+ * offset.
+ *
+ * returns:
+ *     image node offset when found (>=0)
+ *     negative number on failure (FDT_ERR_* code)
+ */
+int fit_conf_get_ramdisk_node(const void *fit, int noffset)
+{
+	return __fit_conf_get_prop_node(fit, noffset, FIT_RAMDISK_PROP);
+}
+
+/**
+ * fit_conf_get_fdt_node - get fdt image node offset that corresponds to
+ * a given configuration
+ * @fit: pointer to the FIT format image header
+ * @noffset: configuration node offset
+ *
+ * fit_conf_get_fdt_node() retrives fdt image node unit name from
+ * configuration FIT_KERNEL_PROP property and translates it to the node
+ * offset.
+ *
+ * returns:
+ *     image node offset when found (>=0)
+ *     negative number on failure (FDT_ERR_* code)
+ */
+int fit_conf_get_fdt_node(const void *fit, int noffset)
+{
+	return __fit_conf_get_prop_node(fit, noffset, FIT_FDT_PROP);
+}
+
+/**
+ * fit_conf_print - prints out the FIT configuration details
+ * @fit: pointer to the FIT format image header
+ * @noffset: offset of the configuration node
+ * @p: pointer to prefix string
+ *
+ * fit_conf_print() lists all mandatory properies for the processed
+ * configuration node.
+ *
+ * returns:
+ *     no returned results
+ */
+void fit_conf_print(const void *fit, int noffset, const char *p)
+{
+	char *desc;
+	char *uname;
+	int ret;
+
+	/* Mandatory properties */
+	ret = fit_get_desc(fit, noffset, &desc);
+	printf("%s  Description:  ", p);
+	if (ret)
+		printf("unavailable\n");
+	else
+		printf("%s\n", desc);
+
+	uname = (char *)fdt_getprop(fit, noffset, FIT_KERNEL_PROP, NULL);
+	printf("%s  Kernel:       ", p);
+	if (uname == NULL)
+		printf("unavailable\n");
+	else
+		printf("%s\n", uname);
+
+	/* Optional properties */
+	uname = (char *)fdt_getprop(fit, noffset, FIT_RAMDISK_PROP, NULL);
+	if (uname)
+		printf("%s  Init Ramdisk: %s\n", p, uname);
+
+	uname = (char *)fdt_getprop(fit, noffset, FIT_FDT_PROP, NULL);
+	if (uname)
+		printf("%s  FDT:          %s\n", p, uname);
+}
+
+/**
+ * fit_check_ramdisk - verify FIT format ramdisk subimage
+ * @fit_hdr: pointer to the FIT ramdisk header
+ * @rd_noffset: ramdisk subimage node offset within FIT image
+ * @arch: requested ramdisk image architecture type
+ * @verify: data CRC verification flag
+ *
+ * fit_check_ramdisk() verifies integrity of the ramdisk subimage and from
+ * specified FIT image.
+ *
+ * returns:
+ *     1, on success
+ *     0, on failure
+ */
+#ifndef USE_HOSTCC
+static int fit_check_ramdisk(const void *fit, int rd_noffset, uint8_t arch,
+				int verify)
+{
+	fit_image_print(fit, rd_noffset, "   ");
+
+	if (verify) {
+		puts("   Verifying Hash Integrity ... ");
+		if (!fit_image_check_hashes(fit, rd_noffset)) {
+			puts("Bad Data Hash\n");
+			bootstage_error(BOOTSTAGE_ID_FIT_RD_HASH);
+			return 0;
+		}
+		puts("OK\n");
+	}
+
+	bootstage_mark(BOOTSTAGE_ID_FIT_RD_CHECK_ALL);
+	if (!fit_image_check_os(fit, rd_noffset, IH_OS_LINUX) ||
+	    !fit_image_check_arch(fit, rd_noffset, arch) ||
+	    !fit_image_check_type(fit, rd_noffset, IH_TYPE_RAMDISK)) {
+		printf("No Linux %s Ramdisk Image\n",
+				genimg_get_arch_name(arch));
+		bootstage_error(BOOTSTAGE_ID_FIT_RD_CHECK_ALL);
+		return 0;
+	}
+
+	bootstage_mark(BOOTSTAGE_ID_FIT_RD_CHECK_ALL_OK);
+	return 1;
+}
+#endif /* USE_HOSTCC */
+#endif /* CONFIG_FIT */

common/miiphyutil.c

diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index e411e57..a45abb9 100644
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -222,6 +222,57 @@
 	return ((found_dev) ? write_ret : 1);
 }
 
+#define COMCERTO_RGMII_DELAY
+#ifdef COMCERTO_RGMII_DELAY
+/********** MSPD Change ***********/
+
+int miiphy_debug_read(char *devname, unsigned char addr, unsigned char reg)
+{
+	unsigned int value;
+
+	if (miiphy_write (devname, addr, PHY_DEBUG_PORT_ADDRESS, reg) != 0) {
+		puts ("PHY Debug register failed\n");
+	}
+
+	if (miiphy_read (devname, addr, PHY_DEBUG_PORT_DATA, &value) != 0) {
+		puts ("PHY Debug register failed\n");
+	}
+
+	return value;
+}
+
+
+int miiphy_debug_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value)
+{
+	if (miiphy_write (devname, addr, PHY_DEBUG_PORT_ADDRESS, reg) != 0) {
+		puts ("PHY Debug register failed\n");
+	}
+	if (miiphy_write (devname, addr, PHY_DEBUG_PORT_DATA, value) != 0) {
+		puts ("PHY Debug register failed\n");
+	}
+}
+
+void miiphy_enable_rgmii_rx_delay(char *devname, unsigned char addr)
+{
+        uint16_t val;
+        //enable RxClk delay
+        val = miiphy_debug_read(devname, addr, 0x0);
+        val |= 0x8000;
+        miiphy_debug_write(devname, addr, 0x0, val);
+}
+
+void miiphy_enable_rgmii_tx_delay(char *devname, unsigned char addr)
+{
+        uint16_t val;
+        //enable TxClk delay
+        val = miiphy_debug_read(devname, addr, 0x5);
+        val |= 0x100;
+        miiphy_debug_write(devname, addr, 0x5, val);
+}
+/************/
+#endif
+
+
 /*****************************************************************************
  *
  * Print out list of registered MII capable devices.
@@ -345,6 +396,135 @@
 	return (0);
 }
 
+int miiphy_supports_1000base_t (char *devname, unsigned char addr)
+{
+	unsigned short reg;
+
+	if (miiphy_read (devname, addr, PHY_BMSR, &reg)) {
+		puts ("PHY bmsr read failed, assuming no 1000bT support\n");
+		return (0);
+	}
+
+	if (reg & PHY_BMSR_EXT_STAT) {
+		if (miiphy_read (devname, addr, PHY_EXSR, &reg)) {
+			puts ("PHY exsr read failed, assuming no 1000bT support\n");
+			return (0);
+		}
+
+		if (reg & (PHY_EXSR_1000TF | PHY_EXSR_1000TH))
+			return (1);
+	}
+
+	return (0);
+}
+
+int miiphy_wait_autonegotiation_complete (char *devname, unsigned char addr)
+{
+	unsigned short bmsr;
+	int count = 0;
+
+	while (count++ < 50000) {
+		if (miiphy_read (devname, addr, PHY_BMSR, &bmsr)) {
+			puts ("PHY bmsr read failed\n");
+			return (-1);
+		}
+
+		if (bmsr & PHY_BMSR_AUTN_COMP)
+			return 0;
+
+		udelay(100);
+	}
+
+	return (-1);
+}
+
+int miiphy_speed_duplex (char *devname, unsigned char addr, int *speed, int *duplex)
+{
+	unsigned short bmcr, btcr, btsr, anlpar, anar;
+
+	/* Check Basic Management Control Register first. */
+	if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
+		puts ("PHY bmcr read failed\n");
+		return -1;
+	}
+
+	/* Check if auto-negotiation is on. */
+	if (bmcr & PHY_BMCR_AUTON) {
+
+		if (miiphy_wait_autonegotiation_complete(devname, addr)) {
+			puts ("PHY autonegotiation error\n");
+			return -1;
+		}
+
+		if (miiphy_supports_1000base_t(devname, addr)) {
+
+			if (miiphy_read (devname, addr, PHY_1000BTCR, &btcr)) {
+				puts ("PHY btcr read failed\n");
+				return -1;
+			}
+
+			if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
+				puts ("PHY btsr read failed\n");
+				return -1;
+			}
+
+			if ((btcr & PHY_1000BTCR_1000FD) && (btsr & PHY_1000BTSR_1000FD)) {
+				*speed = _1000BASET;
+				*duplex = FULL;
+				return 0;
+			}
+
+ 			if ((btcr & PHY_1000BTCR_1000HD) && (btsr & PHY_1000BTSR_1000HD)) {
+				*speed = _1000BASET;
+				*duplex = HALF;
+				return 0;
+			}
+		}
+
+		/* Get link partner abilities results. */
+		if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
+			puts ("PHY anlpar read failed\n");
+			return -1;
+		}
+
+		/* Get advertised abilities. */
+		if (miiphy_read (devname, addr, PHY_ANAR, &anar)) {
+			puts ("PHY anar register read failed\n");
+			return -1;
+		}
+
+		if ((anlpar & anar & PHY_ANLPAR_TXFD)) {
+			*speed = _100BASET;
+			*duplex = FULL;
+		} else if ((anlpar & anar & PHY_ANLPAR_TX)) {
+			*speed = _100BASET;
+			*duplex = HALF;
+		} else if ((anlpar & anar & PHY_ANLPAR_10FD)) {
+			*speed = _10BASET;
+			*duplex = FULL;
+		} else {
+			*speed = _10BASET;
+			*duplex = HALF;
+		}
+
+		return 0;
+	}
+
+	/* Get speed from basic control settings. */
+	if ((bmcr & PHY_BMCR_SPEED_MASK) == PHY_BMCR_1000_MBPS)
+		*speed = _1000BASET;
+	else if ((bmcr & PHY_BMCR_SPEED_MASK) == PHY_BMCR_100_MBPS)
+		*speed = _100BASET;
+	else
+		*speed = _10BASET;
+
+	if (bmcr & PHY_BMCR_DPLX)
+		*duplex = FULL;
+	else
+		*duplex = HALF;
+
+	return 0;
+}
 
 /*****************************************************************************
  *
@@ -352,45 +532,14 @@
  */
 int miiphy_speed (char *devname, unsigned char addr)
 {
-	unsigned short reg;
+	int speed, duplex;
 
-#if defined(CONFIG_PHY_GIGE)
-	if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
-		printf ("PHY 1000BT Status read failed\n");
-	} else {
-		if (reg != 0xFFFF) {
-			if ((reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) !=0) {
-				return (_1000BASET);
-			}
-		}
-	}
-#endif /* CONFIG_PHY_GIGE */
-
-	/* Check Basic Management Control Register first. */
-	if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
+	if (miiphy_speed_duplex(devname, addr, &speed, &duplex)) {
 		puts ("PHY speed read failed, assuming 10bT\n");
 		return (_10BASET);
 	}
-	/* Check if auto-negotiation is on. */
-	if ((reg & PHY_BMCR_AUTON) != 0) {
-		/* Get auto-negotiation results. */
-		if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
-			puts ("PHY AN speed read failed, assuming 10bT\n");
-			return (_10BASET);
-		}
-		if ((reg & PHY_ANLPAR_100) != 0) {
-			return (_100BASET);
-		} else {
-			return (_10BASET);
-		}
-	}
-	/* Get speed from basic control settings. */
-	else if (reg & PHY_BMCR_100MB) {
-		return (_100BASET);
-	} else {
-		return (_10BASET);
-	}
 
+	return speed;
 }
 
 
@@ -400,49 +549,14 @@
  */
 int miiphy_duplex (char *devname, unsigned char addr)
 {
-	unsigned short reg;
+	int speed, duplex;
 
-#if defined(CONFIG_PHY_GIGE)
-	if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
-		printf ("PHY 1000BT Status read failed\n");
-	} else {
-		if ( (reg != 0xFFFF) &&
-		     (reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) ) {
-			if ((reg & PHY_1000BTSR_1000FD) !=0) {
-				return (FULL);
-			} else {
-				return (HALF);
-			}
-		}
-	}
-#endif /* CONFIG_PHY_GIGE */
-
-	/* Check Basic Management Control Register first. */
-	if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
+	if (miiphy_speed_duplex(devname, addr, &speed, &duplex)) {
 		puts ("PHY duplex read failed, assuming half duplex\n");
-		return (HALF);
-	}
-	/* Check if auto-negotiation is on. */
-	if ((reg & PHY_BMCR_AUTON) != 0) {
-		/* Get auto-negotiation results. */
-		if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
-			puts ("PHY AN duplex read failed, assuming half duplex\n");
-			return (HALF);
-		}
-
-		if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) {
-			return (FULL);
-		} else {
-			return (HALF);
-		}
-	}
-	/* Get speed from basic control settings. */
-	else if (reg & PHY_BMCR_DPLX) {
-		return (FULL);
-	} else {
-		return (HALF);
+		return HALF;
 	}
 
+	return duplex;
 }
 
 #ifdef CFG_FAULT_ECHO_LINK_DOWN

config.mk

diff --git a/config.mk b/config.mk
index 6e280bc..c6e8b1d 100644
--- a/config.mk
+++ b/config.mk
@@ -175,7 +175,7 @@
 
 # $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
 # option to the assembler.
-AFLAGS_DEBUG :=
+AFLAGS_DEBUG := -Wa,-gstabs
 
 # turn jbsr into jsr for m68k
 ifeq ($(ARCH),m68k)

cpu/arm1136/comcerto/Makefile

diff --git a/cpu/arm1136/comcerto/Makefile b/cpu/arm1136/comcerto/Makefile
new file mode 100644
index 0000000..6a741a1
--- /dev/null
+++ b/cpu/arm1136/comcerto/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	= interrupts.o serial.o bsp.o training.o mdma.o
+SOBJS	= lowlevel_init.o
+
+all:	$(obj).depend $(LIB)
+
+training.o: training.c training100.c training100_new.c training1000.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+bsp.o: bsp.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

cpu/arm1136/comcerto/bsp.c

diff --git a/cpu/arm1136/comcerto/bsp.c b/cpu/arm1136/comcerto/bsp.c
new file mode 100644
index 0000000..910e31b
--- /dev/null
+++ b/cpu/arm1136/comcerto/bsp.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+#if defined(CONFIG_COMCERTO_900)
+#include "bsp900.c"
+#elif defined(CONFIG_COMCERTO_100)
+#include "bsp100.c"
+#elif defined(CONFIG_COMCERTO_1000)
+#include "bsp1000.c"
+#else
+#error "No Architecture selected!!@" 
+#endif
+

cpu/arm1136/comcerto/bsp100.c

diff --git a/cpu/arm1136/comcerto/bsp100.c b/cpu/arm1136/comcerto/bsp100.c
new file mode 100644
index 0000000..8a60aca
--- /dev/null
+++ b/cpu/arm1136/comcerto/bsp100.c
@@ -0,0 +1,494 @@
+/*
+ * Copyright (C) 2007 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/hardware.h>
+
+static void config_board1(void);
+static void config_board2(void);
+static void config_board3(void);
+static void config_board4(void);
+static void config_board5(void);
+static void config_board6(void);
+static void config_board7(void);
+static void config_board8(void);
+static void config_board9(void);
+static void config_board10(void);
+
+void SoC_Check_Device(void)
+{
+	// This should run on a M821xx SoC, let's check it
+	u32 devicetype = __le32_to_cpu((*(volatile u32*)(GPIO_DEVID_REG)) & __cpu_to_le32(0xFFFF));
+
+	if (devicetype != 0x150)
+	{
+		//error wrong device
+		// TODO: what should we do?
+	}
+}
+
+void SoC_APB_setup(void)
+{
+	// Setting APB Bus Wait states to 1, set post write
+	(*(volatile u32*)(APB_ACCESS_WS_REG)) = __cpu_to_le32(0x40);
+	
+}
+
+void SoC_ARAM_setup(void)
+{
+	// disable pipeline mode in ARAM 
+        (*(volatile u32*)(MEMCORE_BASEADDR+0x18)) = __cpu_to_le32(1);
+}
+
+
+void SoC_AHB_setup(void)
+{
+	// enable all 6 masters for ARAM
+        (*(volatile u32*)(ASA_ARAM_TC_CR_REG)) = __cpu_to_le32(ASA_TC_REQIDMAEN |  ASA_TC_REQTDMEN |ASA_TC_REQIPSECUSBEN |ASA_TC_REQARM0EN | ASA_TC_REQARM1EN |ASA_TC_REQMDMAEN);
+	// enable all 6 masters for EBUS
+	(*(volatile u32*)(ASA_EBUS_TC_CR_REG)) = __cpu_to_le32(ASA_TC_REQIDMAEN |  ASA_TC_REQTDMEN |ASA_TC_REQIPSECUSBEN |ASA_TC_REQARM0EN | ASA_TC_REQARM1EN |ASA_TC_REQMDMAEN);
+
+}
+
+
+void SoC_PLL_init(void)
+{
+	HAL_set_amba_clk(CFG_HZ_CLOCK);
+	HAL_set_arm_clk(CFG_ARM_CLOCK);
+
+	// set PUI
+	*(volatile u32*)(CLKCORE_CLKDIV_CNTRL) &= __cpu_to_le32(~(0x1F << PUI_CLKDIV_RATIO_SHIFT));
+	*(volatile u32*)(CLKCORE_CLKDIV_CNTRL) |= __cpu_to_le32(((CFG_ARM_CLOCK / 25000000) << PUI_CLKDIV_RATIO_SHIFT));
+	*(volatile u32*)(CLKCORE_CLKDIV_CNTRL) &= __cpu_to_le32(~PUI_CLKDIV_BYPASS);	
+
+	// set pci divider and switch to ref clk
+//	*(volatile u32*)(CLKCORE_CLKDIV_CNTRL) &= ~(0x1F << PCI_CLKDIV_RATIO_SHIFT);/
+//	*(volatile u32*)(CLKCORE_CLKDIV_CNTRL) |= ((CFG_HZ_CLOCK / 33000000) << PCI_CLKDIV_RATIO_SHIFT);
+//	*(volatile u32*)(CLKCORE_CLKDIV_CNTRL) &= ~PCI_CLKDIV_BYPASS;	
+}
+
+static void apply_ddr_setting(u32 board_config)
+{
+	u8 do_training = 0;
+
+	switch (board_config) {
+	case BOARD_CFG_1:
+		config_board1();
+		break;
+	case BOARD_CFG_2:
+	    	config_board2();
+		break;
+	case BOARD_CFG_3:
+	    	config_board3();
+		break;
+	case BOARD_CFG_4:
+	    	config_board4();
+		do_training = 1;
+		break;
+	case BOARD_CFG_5:
+		config_board5();
+		do_training = 1;
+		break;
+	case BOARD_CFG_6:
+	    	config_board6();
+		break;
+	case BOARD_CFG_7:
+	    	config_board7();
+		break;
+	case BOARD_CFG_8:
+	    	config_board8();
+		break;
+	case BOARD_CFG_9:
+		config_board9(); /* Packet IAD C50 */
+		do_training = 1;
+		break;
+	case BOARD_CFG_10:
+		config_board10(); /* Router C50 */
+		break;
+	}
+
+#ifdef DDR_TRAINING
+	if (do_training)
+		start_training();  /* training to find optimal ODT values (run from L1 cache) */
+#endif
+}
+
+
+void SoC_mem_init(u32 board_config)
+{
+	volatile u32 delay_count;
+	u32 ddr_size;
+
+	// Get the right amount of DDR the board is populated with
+	ddr_size = get_ddr_size();
+	// Memory setup register
+	*(volatile u32*)(MEMORY_MAX_ADDR) = __cpu_to_le32((ddr_size - 1) + MEMORY_BASE_ADDR);
+	// disbale ROM remap
+	*(volatile u32*)(MEMORY_CR) = __cpu_to_le32(0);
+	
+	// Take DDR controller out of reset
+	*(volatile u32*)(BLOCK_RESET_REG) |= __cpu_to_le32(DDR_RST);
+	// 20 ops delay
+	delay_count = 20;
+	while(delay_count--);
+
+	//Apply DENALI DDR configuration according to the board 
+	apply_ddr_setting(board_config);
+}
+
+
+void SoC_nand_init(void)
+{
+	// TODO: verify timings
+
+	// Configure CS4 - 8 bits - NAND
+	*(volatile u32*)(EX_CS4_CFG_REG) = __cpu_to_le32(EX_MEM_BUS_8 | EX_NAND_MODE);
+	// timings (CSw = 9, RE WE 9), 
+	*(volatile u32*)(EX_CS4_TMG1_REG) = __cpu_to_le32(9 | 9<<16 | 9<<24) ;
+	*(volatile u32*)(EX_CSEN_REG)  |= __cpu_to_le32(EX_CS4_EN);	
+}
+
+/*
+* SoC_gpio_cfg - configure GPIO pins as input or output pins
+*
+* gpio - gpio pin
+*
+* mode - gpio pin mode
+*	GPIO_TYPE_OUTPUT = output
+*	GPIO_TYPE_INPUT = input
+*
+*/
+int SoC_gpio_cfg(int gpio, int mode)
+{
+	if ((gpio < 0) || (gpio > 31))
+		goto err;
+
+	switch (mode) {
+	case GPIO_TYPE_INPUT:
+	default:
+		*(volatile u32 *) GPIO_OE_REG &= __cpu_to_le32(~(1 << gpio));
+		break;
+
+	case GPIO_TYPE_OUTPUT:
+		*(volatile u32 *) GPIO_OE_REG |= __cpu_to_le32(1 << gpio);
+		break;
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
+static void config_board1(void)
+{
+	u64 wr_dqs_shift = 0x40;
+
+	*(volatile u64*)(DENALI_CTL_00_DATA) =  __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_01_DATA) =  __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_02_DATA) =  __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_03_DATA) =  __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_04_DATA) =  __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_05_DATA) =  __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_06_DATA) =  __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_07_DATA) =  __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_08_DATA) =  __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_09_DATA) =  __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_10_DATA) =  __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_11_DATA) =  __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_12_DATA) =  __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_13_DATA) =  __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_14_DATA) =  __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_15_DATA) =  __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_16_DATA) =  __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_17_DATA) =  __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_18_DATA) =  __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_19_DATA) =  __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_20_DATA) =  __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG1);
+	
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) =  __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( *(volatile u32*)(DENALI_CTL_08_DATA+4) & __cpu_to_le32(0x040000)) == 0);
+
+	*(volatile u64*)(DENALI_CTL_11_DATA) =  __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG1 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+
+static void config_board2(void)
+{
+	u64 wr_dqs_shift = 0x40;
+
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG2);
+	
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( *(volatile u32*)(DENALI_CTL_08_DATA+4) & __cpu_to_le32(0x040000)) == 0);
+
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG2 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+
+static void config_board3(void)
+{
+	u64 wr_dqs_shift = 0x40;
+
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG3);
+	
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG3 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( *(volatile u32*)(DENALI_CTL_08_DATA+4) & __cpu_to_le32(0x040000)) == 0);
+
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG3 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board4(void)
+{
+	u64 wr_dqs_shift = 0x40;
+
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG4);
+	
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG4 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( *(volatile u32*)(DENALI_CTL_08_DATA+4) & __cpu_to_le32(0x040000)) == 0);
+
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG4 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+
+static void config_board5(void)
+{
+	u64 wr_dqs_shift = 0x40;
+
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG5);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG5);
+	
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG5 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( *(volatile u32*)(DENALI_CTL_08_DATA+4) & __cpu_to_le32(0x040000)) == 0);
+
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG5 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board6(void)
+{
+	u64 wr_dqs_shift = 0x40;
+
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG6);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG6);
+	
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG6 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( *(volatile u32*)(DENALI_CTL_08_DATA+4) & __cpu_to_le32(0x040000)) == 0);
+
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG6 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board7(void)
+{
+	config_board5();    /* config 7 is same as config 5 */
+}
+
+static void config_board8(void)
+{
+    /* Dali MoCA EVMs have same memory subsystem as PacketIAD EVM */
+    config_board4();
+}
+
+
+/* Similar to Config #4 (Packet IAD) */
+static void config_board9(void)
+{
+	u64 wr_dqs_shift = 0x40;
+
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG4_C50);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG4_C50);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG4_C50);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG4_C50);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG4_C50);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG4_C50);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG4_C50);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG4_C50);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG4_C50);
+	
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG4 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( *(volatile u32*)(DENALI_CTL_08_DATA+4) & __cpu_to_le32(0x040000)) == 0);
+
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG4_C50 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+/* Board cfg 10 is defined for C50 Router EVM */
+static void config_board10(void)
+{
+        u64 wr_dqs_shift = 0x40;
+
+        *(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG10);
+        *(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG10);
+
+        // start DDRC
+        *(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG10 | (1LL << 32));
+        //wait int_status[2] (DRAM init complete)
+        while(( *(volatile u32*)(DENALI_CTL_08_DATA+4) & __cpu_to_le32(0x040000)) == 0);
+        
+ 	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG10 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+

cpu/arm1136/comcerto/bsp1000.c

diff --git a/cpu/arm1136/comcerto/bsp1000.c b/cpu/arm1136/comcerto/bsp1000.c
new file mode 100644
index 0000000..b1d3800
--- /dev/null
+++ b/cpu/arm1136/comcerto/bsp1000.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2007-2008 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/hardware.h>
+
+u32 CFG_HZ_CLOCK;	/* Allow for AHB clock frequency to be chosen at run time */
+
+
+void SoC_Check_Device(void)
+{
+	// This should run on a M83xxx SoC, let's check it
+	u32 devicetype = __le32_to_cpu((*(volatile u32*)(GPIO_DEVID_REG)) & __cpu_to_le32(0xFFFF));
+
+	if (devicetype != 0x170)
+	{
+		//error wrong device
+		// TODO: what should we do?
+	}
+}
+
+void SoC_APB_setup(void)
+{
+	// Setting APB Bus Wait states to 0, set post write
+	*(volatile u32*)(APB_ACCESS_WS_REG) = __cpu_to_le32(0x40);
+}
+
+void SoC_ARAM_setup(void)
+{
+	// enable ARAM collision detection
+	// read mod write to set bit 2 to enable.  Keep default of 32 byte mask
+	*(volatile u32*)(MEMCORE_BASEADDR+0x4) |= __cpu_to_le32(4);
+	// disable ARAM pipeline mode
+	*(volatile u32*)(MEMCORE_BASEADDR+0x38) = __cpu_to_le32(0);
+	// set ARAM port/fbp priority to 1 
+	*(volatile u32*)(MEMCORE_BASEADDR+0x0C) = __cpu_to_le32(3); 
+}
+
+
+void SoC_AHB_setup(void)
+{
+	// DDR size 512MB, starting from 80000000
+	*(volatile u32*) AHB_HIGHMEM_ADDR_TRANSLATION = __cpu_to_le32(0x9FFF); 	//(AHB_BASEADDR + 0x04)
+	// Disable REMAP (Low Mem region is mapped to DDR base)
+	*(volatile u32*) AHB_LOWMEM_REMAP_CTRL = __cpu_to_le32(0x0);		//(AHB_BASEADDR + 0x00)
+	// 2nd stage level muxs are configured to round-robin
+	*(volatile u32*) AHB_STAGE2_ARBITER_CFG	= __cpu_to_le32(0x0);	//(AHB_BASEADDR + 0x08)
+}
+
+
+void SoC_PLL_init(int cfg)
+{
+	struct c1000_cfg_clk c1000_cfg_clk_table[] =
+	{
+		[CFG_CLK_650_187_375] = {650000000, 3, 4, 750000000, 2, 2, 250000000, 3, 8, 0, 650000000, 0, 187500000, 375000000, 250000000}, /* M8326x, 375MHz */
+		[CFG_CLK_600_165_330] = {600000000, 1, 4, 660000000, 1, 4, 250000000, 3, 8, 0, 600000000, 0, 165000000, 330000000, 110000000}, /* M83160 */
+		[CFG_CLK_534_178_330] = {660000000, 1, 4, 534000000, 1, 4, 250000000, 3, 8, 1, 534000000, 1, 178000000, 330000000, 178000000}, /* M8325x */
+		[CFG_CLK_450_165_330] = {450000000, 1, 4, 660000000, 1, 4, 250000000, 3, 8, 0, 450000000, 0, 165000000, 330000000, 110000000}, /* M8324x */
+		[CFG_CLK_400_165_330] = {400000000, 2, 6, 660000000, 1, 4, 250000000, 3, 8, 0, 400000000, 0, 165000000, 330000000, 110000000}, /* M83240 */
+		[CFG_CLK_650_200_200] = {650000000, 3, 4, 800000000, 3, 2, 250000000, 3, 8, 0, 650000000, 0, 200000000, 200000000, 266666666}, /* M8326x, 200MHz */
+		[CFG_CLK_650_187_325] = {650000000, 3, 4, 750000000, 2, 2, 250000000, 3, 8, 0, 650000000, 1, 187500000, 325000000, 250000000}, /* Asic */
+		[CFG_CLK_610_186_372] = {610000000, 3, 4, 744000000, 2, 2, 250000000, 3, 8, 0, 610000000, 0, 186000000, 372000000, 248000000} /* Asic */
+	};
+	struct c1000_cfg_clk *cfg_clk = &c1000_cfg_clk_table[cfg];
+
+	// *(volatile u32*)(GPIO_ARM_MEMORY_SENSE_REGS) = __cpu_to_le32(0x1B6DB6DB); /* Margin = 3 */
+	//*(volatile u32*)(GPIO_ARM_MEMORY_SENSE_REGS) = __cpu_to_le32(0x24924924); /* Margin = 4 */
+	*(volatile u32*)(GPIO_ARM_MEMORY_SENSE_REGS) = __cpu_to_le32(0x2DB6DB6D);       /* Margin = 5 */
+
+	// Make sure DDR controller is reset
+	*(volatile u32*)(CLKCORE_BLK_RESET) &= __cpu_to_le32(~(BLK_RESET_DDR_REF_RESET_N | BLK_RESET_DDR_AHB_RESET_N));
+
+	HAL_all_pll_bypass();
+
+	// Take DDR controller out of reset
+	*(volatile u32*)(CLKCORE_BLK_RESET) |= __cpu_to_le32(BLK_RESET_DDR_REF_RESET_N | BLK_RESET_DDR_AHB_RESET_N);
+
+	HAL_set_arm_pll(cfg_clk->arm_pll, cfg_clk->arm_pll_nr, cfg_clk->arm_pll_od);
+	HAL_set_ahb_pll(cfg_clk->ahb_pll, cfg_clk->ahb_pll_nr, cfg_clk->ahb_pll_od);
+	HAL_set_phy_pll(cfg_clk->phy_pll, cfg_clk->phy_pll_nr, cfg_clk->phy_pll_od);
+
+	HAL_set_arm_clk(cfg_clk->arm_clk, cfg_clk->arm_clk, cfg_clk->arm_from_sclk2);
+	HAL_set_ahb_ddr_clk(cfg_clk->ahb_clk, cfg_clk->ddr_clk, cfg_clk->ddr_from_fclk);
+	HAL_set_phy_gem_clk(CFG_GEM0_CLOCK, CFG_GEM1_CLOCK, CFG_PHY_CLOCK);
+	HAL_set_ipsec_clk(cfg_clk->ipsec_clk);
+
+	HAL_all_pll_remove_bypass();
+}
+
+void SoC_nand_init(void)
+{
+	// TODO: verify timings
+
+	// Configure CS4 - 8 bits - NAND
+	*(volatile u32*)(EX_CS4_CFG_REG) = __cpu_to_le32(EX_MEM_BUS_8 | EX_NAND_MODE);
+	// timings (CSw = 9, RE WE 9), 
+	*(volatile u32*)(EX_CS4_TMG1_REG) = __cpu_to_le32(9 | 9<<16 | 9<<24) ;
+	*(volatile u32*)(EX_CSEN_REG)  |= __cpu_to_le32(EX_CS4_EN);	
+}
+
+/*
+* SoC_gpio_cfg - configure GPIO pins as input or output pins
+*
+* gpio - gpio pin
+*
+* mode - gpio pin mode
+*	GPIO_TYPE_OUTPUT = output
+*	GPIO_TYPE_INPUT = input
+*
+*/
+int SoC_gpio_cfg(int gpio, int mode)
+{
+	if ((gpio < 0) || (gpio > 31))
+		goto err;
+
+	switch (mode) {
+	case GPIO_TYPE_INPUT:
+	default:
+		*(volatile u32 *) GPIO_OE_REG &= __cpu_to_le32(~(1 << gpio));
+		break;
+
+	case GPIO_TYPE_OUTPUT:
+		*(volatile u32 *) GPIO_OE_REG |= __cpu_to_le32(1 << gpio);
+		break;
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
+void arm_write64(u64 data,volatile u64 *p)
+{
+        int *tptr = &data;
+        register int reg_0 __asm__ ("r3");
+        register int reg_1 __asm__ ("r4");
+
+        __asm__ __volatile__ (
+                "ldmia     %0, {%1,%2}     \n\t"
+                : "+r" (tptr), "=r" (reg_0), "=r" (reg_1)
+        );
+        __asm__ __volatile__ (
+                "stmia     %0, {%1,%2}     \n\t"
+                : "+r" (p), "=r" (reg_0), "=r" (reg_1)
+        );
+}

cpu/arm1136/comcerto/bsp900.c

diff --git a/cpu/arm1136/comcerto/bsp900.c b/cpu/arm1136/comcerto/bsp900.c
new file mode 100644
index 0000000..fec7ade
--- /dev/null
+++ b/cpu/arm1136/comcerto/bsp900.c
@@ -0,0 +1,129 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/scc.h>
+
+
+void SoC_Check_Device(void)
+{
+	// This should run on a M829xx SoC, let's check it
+	u32 devicetype = *(volatile u32*)(0x1008002C);
+	if(devicetype != 0x140)
+	{
+		//error wrong device
+		// TODO: what should we do?
+	}
+}
+void SoC_PLL_init(void)
+{
+	//sys_write_control(CR_M | CR_V | CR_ASYNC);
+	u32 i = 0;//CR_M | CR_V | CR_ASYNC;
+	/* turn off I/D-cache */
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	i |= (CR_ASYNC);
+	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	HAL_set_amba_clk(133000000);
+	HAL_set_arm_clk(450000000);
+}
+
+
+//void SoC_mem_init(int controller, int base, int length)
+void SoC_mem_init(void)
+{
+#if 0
+	//*(volatile u32*)(0x10080010) = 0xD2db;
+	//*(volatile u32*)(0x1008001c) = 0x42;
+	//*(volatile u32*)(0x10080014) = 0xEA;
+	*(volatile u32*)(0x10080010) = 0xD4E3;
+	// Configure SDRAM CFG2
+	*(volatile u32*)(0x10080014) = 0x00EA;
+	//Configure SDRAM REFRESH
+	*(volatile u32*)(0x10080018) = 0x0820;
+	//Configure SDRAM PWRON
+	*(volatile u32*)(0x1008001C) = 0x682B;
+
+	*(volatile u32*)(0x10060000) = 0xF;
+	*(volatile u32*)(0x1006000C) = 5;
+#else
+	if (1)//controller == 0)
+	{
+		//matisse only have one SDRAM controller so the first param is useless
+		// The following settings is based on a SDRAM with clock rate 133 MHz and speed grade -7
+		// Configure SDRAM CFG1
+		*(volatile u32*)(0x10080010) = 0xD4E3;
+		// Configure SDRAM CFG2
+		*(volatile u32*)(0x10080014) = 0x00EA;
+		//Configure SDRAM REFRESH
+		*(volatile u32*)(0x10080018) = 0x0820;
+		//Configure SDRAM PWRON
+		*(volatile u32*)(0x1008001C) = 0x682B;
+		
+		
+		
+	#if 0
+		// The following settings is based on a DDR-SDRAM with clock rate 133 MHz and speed grade -75z
+		// Configure SDRAM CFG1
+		*(volatile u32*)(0x10080010) = 0xD6DA;
+		// Configure SDRAM CFG2
+		*(volatile u32*)(0x10080014) = 0x03EA;
+		//Configure SDRAM REFRESH
+		*(volatile u32*)(0x10080018) = 0x0820;
+		//Configure SDRAM PWRON
+		*(volatile u32*)(0x1008001C) = 0x682B;
+	#endif
+
+
+	if (PHYS_SDRAM > (128*0x100000)) {	// high memory
+		*(volatile u32*)(0x10060000) = (PHYS_SDRAM >>20)<<4;
+		*(volatile u32*)(0x10060010) = (PHYS_SDRAM >>27);			
+	}
+	else {
+		*(volatile u32*)(0x10060000) = (PHYS_SDRAM >>16)<<4;
+	}
+
+		switch (/*length*/PHYS_SDRAM_SIZE/0x100000)
+		{
+			case 8:
+				*(volatile u32*)(0x10060000) |= 0xB;
+				break;
+			case 16:
+				*(volatile u32*)(0x10060000) |= 0xC;
+				break;
+			case 32:
+				*(volatile u32*)(0x10060000) |= 0xD;
+				break;
+			case 64:
+				*(volatile u32*)(0x10060000) |= 0xE;
+				break;
+			case 128:
+				*(volatile u32*)(0x10060000) |= 0xF;
+				break;
+		}			
+		// Enable Chip select 0
+		//*(volatile u32*)(0x1006000C) |= 0x1;
+		//*(volatile u32*)(0x1006000C) = 0xC;
+		if (PHYS_SDRAM > (128*0x100000))	// high memory : do ARAM remap to have memory @0x00000000		
+			*(volatile u32*)(0x1006000C) = 0x115;
+		else
+			*(volatile u32*)(0x1006000C) = 0x05;
+	}
+#endif	
+	
+}
+
+void SoC_flash_init(void)
+{
+	// Configure SDRAM CFG1
+	*(volatile u32*)(0x10060004) = 0x0010000b;
+	//*(volatile u32*)(0x10060014) = 0x10;
+	*(volatile u32*)(0x10060014) = 0;
+	*(volatile u32*)(0x10080004) = 0x0D92;
+	*(volatile u32*)(0x1006000C) |= 2;
+
+}
+
+void SoC_nand_init(void)
+{
+	*(volatile u32*)(0x1008000C) = 0x0492;
+	*(volatile u32*)(0x1006000C) |= 8;
+}
+

cpu/arm1136/comcerto/interrupts.c

diff --git a/cpu/arm1136/comcerto/interrupts.c b/cpu/arm1136/comcerto/interrupts.c
new file mode 100644
index 0000000..cf76a54
--- /dev/null
+++ b/cpu/arm1136/comcerto/interrupts.c
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bsp.h>
+#include <asm/byteorder.h>
+
+#define TIMER_LOAD_VAL		0xffffffff
+#define CLOCK_COUNT_PER_USEC	(CFG_HZ_CLOCK / 1000 / 1000)
+#define USEC_PER_TICK		(1000 * 1000 / CFG_HZ)
+
+#define READ_TIMER		(__le32_to_cpu((*(volatile u32 *)TIMER0_CURR_COUNT)))
+
+
+static ulong ts_count, ts_usec;
+static ulong lastinc;
+
+int interrupt_init (void)
+{
+	*(volatile u32 *)TIMER0_CNTR_REG = __cpu_to_le32(TIMER_LOAD_VAL);
+
+	lastinc = 0;
+	ts_count = 0;
+	ts_usec = 0;
+
+	return (0);
+}
+
+void reset_timer_masked (void)
+{
+	lastinc = READ_TIMER;
+	ts_count = 0;
+	ts_usec = 0;
+}
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+/* Returns usecs since last timer reset */
+ulong get_timer_raw (void)
+{
+	ulong step;
+	ulong now = READ_TIMER;
+
+	if (now > lastinc) {
+		/* normal mode */
+		step = now - lastinc;
+	} else {
+		/* we have an overflow ... */
+		step = (TIMER_LOAD_VAL - lastinc) + now;
+	}
+
+	lastinc = now;
+
+	ts_count += step % CLOCK_COUNT_PER_USEC;
+	ts_usec += step / CLOCK_COUNT_PER_USEC;
+
+	if (ts_count >= CLOCK_COUNT_PER_USEC) {
+		ts_usec += ts_count / CLOCK_COUNT_PER_USEC;
+		ts_count %= CLOCK_COUNT_PER_USEC;
+	}
+
+	return ts_usec;
+}
+
+/* Returns tick count since last timer reset */
+ulong get_timer_masked (void)
+{
+	return get_timer_raw() / USEC_PER_TICK;
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong endtime = get_timer_raw () + usec;
+
+	while (get_timer_raw () < endtime)
+		;
+
+}
+
+void udelay (unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CFG_HZ;
+	return tbclk;
+}
+
+/*
+ *
+ */
+void reset_cpu (ulong ignored)
+{
+	/* set the timeout value */
+	*(volatile u32 *)TIMER_WDT_HIGH_BOUND = __cpu_to_le32(0x1);
+	/* enable watchdog timer */
+	*(volatile u32 *)TIMER_WDT_CONTROL = __cpu_to_le32(0x1);
+
+	while (1) ;
+}
+
+/*
+ * timer without interrupts
+ */
+
+
+void set_timer (ulong t)
+{
+	ts_count = 0;
+	ts_usec = t * USEC_PER_TICK;
+}

cpu/arm1136/comcerto/lowlevel_init.S

diff --git a/cpu/arm1136/comcerto/lowlevel_init.S b/cpu/arm1136/comcerto/lowlevel_init.S
new file mode 100644
index 0000000..c7550b8
--- /dev/null
+++ b/cpu/arm1136/comcerto/lowlevel_init.S
@@ -0,0 +1,40 @@
+/*
+ * SOC specific setup info
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/hardware.h>
+
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp, TMP_STACK /* set up a temporary stack */
+
+	stmdb	sp!, {ip, lr}
+	bl	bsp_init	/* go setup pll, memory */
+	ldmia	sp!, {ip, pc}	/* restore registers and return to caller */
+
+	/* the literal pools origin */
+	.ltorg
+TMP_STACK:
+	.word	CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET

cpu/arm1136/comcerto/mdma.c

diff --git a/cpu/arm1136/comcerto/mdma.c b/cpu/arm1136/comcerto/mdma.c
new file mode 100644
index 0000000..fd7b277
--- /dev/null
+++ b/cpu/arm1136/comcerto/mdma.c
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+#if defined(CONFIG_COMCERTO_1000)
+
+#define MDMA_GBL_CTRL_CFG           *((volatile u32 *)(MDMA_BASEADDR + 0x0))
+#define MDMA_TX1_PATH_HEAD          *((volatile u32 *)(MDMA_BASEADDR + 0x4))
+#define MDMA_TX1_PATH_CTR           *((volatile u32 *)(MDMA_BASEADDR + 0x8))
+#define MDMA_RX1_PATH_HEAD          *((volatile u32 *)(MDMA_BASEADDR + 0x14))
+#define MDMA_RX1_PATH_CTR           *((volatile u32 *)(MDMA_BASEADDR + 0x18))
+#define MDMA_INT_MASK_REG           *((volatile u32 *)(MDMA_BASEADDR + 0x28))
+#define MDMA_INT_STATUS_REG0        *((volatile u32 *)(MDMA_BASEADDR + 0x2c))
+#define MDMA_INT_STATUS_REG1        *((volatile u32 *)(MDMA_BASEADDR + 0x30))
+
+typedef struct mdma_desc_s
+{
+  u32 dataBufAddr;
+  u32 control;
+  u32 msg1;
+  u32 msg2;
+} mdma_desc_t;
+
+/*****************************************************************************
+ * Function: mdma_memcpy
+ * Desction:
+ *   Implemenation of memcpy function using MDMA.
+ *   No CRC mechanism supported in C1K.
+ * Paramters:
+ *   src: Source address
+ *   dst: Destination address
+ *   len: length of the data to be copied.
+ *   crc: Not used
+ *****************************************************************************/
+int mdma_memcpy(void *src, void *dst, int len, unsigned int *crc)
+{
+  u32 stat;
+  int i;
+  unsigned char temp1[64];
+  unsigned char temp2[64];
+
+  //descriptor memset to zero
+  for(i=0; i < 64; i++)
+  {
+	temp1[i] = 0;
+ 	temp2[i] = 0;
+  }
+
+  len = len - (len % 8);
+  
+  //Disable MDMA
+  MDMA_GBL_CTRL_CFG = __cpu_to_le32(0);
+
+  //Make it 16byte align
+  mdma_desc_t *txDesc = (mdma_desc_t *)(((u32)(temp1 + 16)) & ~0xf);
+  mdma_desc_t *rxDesc = (mdma_desc_t *)(((u32)(temp2 + 16)) & ~0xf);
+
+  txDesc->dataBufAddr = __cpu_to_le32((u32)src);
+  txDesc->control = __cpu_to_le32((u32)(0x41002000 | (len & 0x1fff)));
+  txDesc->msg1 = txDesc->msg2 = __cpu_to_le32(0);
+  MDMA_TX1_PATH_HEAD = __cpu_to_le32((u32)txDesc);
+  MDMA_TX1_PATH_CTR = __cpu_to_le32(1);
+
+  rxDesc->dataBufAddr = __cpu_to_le32((u32)dst);
+  rxDesc->control = __cpu_to_le32((u32)(0x41002000 | (len & 0x1fff))); 
+  rxDesc->msg1 = rxDesc->msg2 = __cpu_to_le32(0);
+  MDMA_RX1_PATH_HEAD = __cpu_to_le32((u32)rxDesc);
+  MDMA_RX1_PATH_CTR = __cpu_to_le32(1);
+
+  MDMA_INT_MASK_REG = __cpu_to_le32(0);
+  MDMA_GBL_CTRL_CFG = __cpu_to_le32(1);  //Enable MDMA 
+
+  /* wait until dma done */
+  while((stat = __le32_to_cpu(MDMA_RX1_PATH_CTR)) != 0);
+
+  //Memcpy done, disable MDMA
+  MDMA_GBL_CTRL_CFG = __cpu_to_le32(0);
+
+  return 0;
+}
+
+#elif defined(CONFIG_COMCERTO_100)
+
+#define MDMA_MMFIFO_START           *((volatile u32 *)(MDMA_BASEADDR + 0x100))
+#define MDMA_MMFIFO_HEADPTR         *((volatile u32 *)(MDMA_BASEADDR + 0x104))
+#define MDMA_MMFIFO_LOCK_TSFR_SIZE  *((volatile u32 *)(MDMA_BASEADDR + 0x108))
+#define MDMA_MMFIFO_SOFT_RESET      *((volatile u32 *)(MDMA_BASEADDR + 0x120))
+
+#define MDMA_FIFOMM_START           *((volatile u32 *)(MDMA_BASEADDR + 0x180))
+#define MDMA_FIFOMM_HEADPTR         *((volatile u32 *)(MDMA_BASEADDR + 0x184)) 
+#define MDMA_FIFOMM_LOCK_TSFR_SIZE  *((volatile u32 *)(MDMA_BASEADDR + 0x188))
+#define MDMA_FIFOMM_SOFT_RESET      *((volatile u32 *)(MDMA_BASEADDR + 0x1A0))
+
+typedef struct mdma_bPtr_s
+{
+  u32 Bpointer;
+  u32 Bcontrol;
+}mdma_bPtr_t;
+
+typedef struct mdma_Fdesc_s
+{
+  u32 Fnext;
+  u32 Fsystem;
+  u32 Fstatus;
+  u32 Fcontrol;
+
+  mdma_bPtr_t Bdesc;
+
+}mdma_Fdesc_t;
+
+
+int mdma_memcpy(void *src, void *dst, int len, unsigned int *crc)
+{
+  unsigned char temp1[64];
+  unsigned char temp2[64];
+  volatile unsigned int val;
+  int i;
+
+  //Make it 16byte align
+  mdma_Fdesc_t *mmfifo = (mdma_Fdesc_t *)(((u32)(temp1 + 16)) & ~0xf);
+  mdma_Fdesc_t *fifomm = (mdma_Fdesc_t *)(((u32)(temp2 + 16)) & ~0xf);
+
+  //descriptor memset to zero
+  for(i=0; i < 64; i++)
+  {
+	temp1[i] = 0;
+ 	temp2[i] = 0;
+  }
+
+  /* memory to FIFO */
+  mmfifo->Fnext = __cpu_to_le32(0x0);
+  mmfifo->Fsystem = __cpu_to_le32(0);
+  mmfifo->Fstatus = __cpu_to_le32(0);
+  mmfifo->Fcontrol = __cpu_to_le32(0x83);
+  mmfifo->Bdesc.Bpointer = __cpu_to_le32((u32)src);
+  mmfifo->Bdesc.Bcontrol = __cpu_to_le32((0x10000 | (len & 0xffff)));
+
+  /* FIFO to memory */
+  fifomm->Fnext = __cpu_to_le32(0x0);
+  fifomm->Fsystem = __cpu_to_le32(0x0);
+  fifomm->Fstatus = __cpu_to_le32(0x0);
+  fifomm->Fcontrol = __cpu_to_le32(0x83);
+  fifomm->Bdesc.Bpointer = __cpu_to_le32((u32)dst);
+  fifomm->Bdesc.Bcontrol = __cpu_to_le32(len & 0xffff);
+
+  MDMA_MMFIFO_SOFT_RESET = __cpu_to_le32(1);
+  MDMA_FIFOMM_SOFT_RESET = __cpu_to_le32(1);
+
+  MDMA_MMFIFO_HEADPTR = __cpu_to_le32((u32)mmfifo);
+  MDMA_MMFIFO_LOCK_TSFR_SIZE = __cpu_to_le32(64);
+
+  MDMA_FIFOMM_HEADPTR = __cpu_to_le32((u32)fifomm);
+  MDMA_FIFOMM_LOCK_TSFR_SIZE = __cpu_to_le32(64);
+
+  MDMA_MMFIFO_START = __cpu_to_le32(0x1);
+  MDMA_FIFOMM_START = __cpu_to_le32(0x1);
+
+  while ((val = __le32_to_cpu(mmfifo->Fstatus)) == 0);
+  while ((val = __le32_to_cpu(fifomm->Fstatus)) == 0);
+
+  /* Return the CRC value */
+  *crc = __le32_to_cpu(fifomm->Fsystem);
+
+  return 0;
+}
+#endif

cpu/arm1136/comcerto/serial.c

diff --git a/cpu/arm1136/comcerto/serial.c b/cpu/arm1136/comcerto/serial.c
new file mode 100644
index 0000000..c39332b
--- /dev/null
+++ b/cpu/arm1136/comcerto/serial.c
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bsp.h>
+#include <asm/byteorder.h>
+
+
+#if !defined(CONFIG_UART0) && !defined(CONFIG_UART1)
+#error must define one of CONFIG_UART0 or CONFIG_UART1
+#endif
+
+
+typedef struct tagUART16550REGS {
+	volatile u32 data;	// Receive/Transmit data register
+	volatile u32 ier;	// Interrupt Enable register
+	volatile u32 iir_fcr;// Interrupt Identity register / FIFO Control register
+	volatile u32 lcr;	// Line Control register
+	volatile u32 mcr;	// Modem Control register
+	volatile u32 lsr;	// Line Status register
+	volatile u32 msr;	// Modem Status register
+	volatile u32 sr;		// Scratch register
+} UART16550REGS, *PUART16550REGS;
+
+typedef struct tagUART16550DLREGS {
+	volatile u32 dll;	// Divisor Latch (Low)
+	volatile u32 dlh;	// Divisor Latch (High)
+} UART16550DLREGS, *PUART16550DLREGS;
+
+#define LCR_CHAR_LEN_5		0x00	  /* default */
+#define LCR_CHAR_LEN_6		0x01
+#define LCR_CHAR_LEN_7		0x02
+#define LCR_CHAR_LEN_8		0x03
+#define LCR_ONE_STOP		0x00	  /* One stop bit! - default */
+#define LCR_TWO_STOP		0x04	  /* Two stop bit! */
+#define LCR_PEN				0x08	  /* Parity Enable */
+#define LCR_PARITY_NONE		0x00
+#define LCR_EPS				0x10	  /* Even Parity Select */
+#define LCR_PS				0x20	  /* Enable Parity  Stuff */
+#define LCR_SBRK				0x40  /* Start Break */
+#define LCR_PSB				0x80	  /* Parity Stuff Bit */
+#define LCR_DLAB				0x80  /* UART 16550 Divisor Latch Assess */
+
+#define LSR_FIFOE		(1 << 7)	/* FIFO Error Status */
+#define LSR_TEMT			(1 << 6)	/* Transmitter Empty */
+#define LSR_TDRQ			(1 << 5)	/* Transmit Data Request */
+#define LSR_BI			(1 << 4)	/* Break Interrupt */
+#define LSR_FE			(1 << 3)	/* Framing Error */
+#define LSR_PE			(1 << 2)	/* Parity Error */
+#define LSR_OE			(1 << 1)	/* Overrun Error */
+#define LSR_DR			(1 << 0)	/* Data Ready */
+
+
+#define IER_DMAE			(1 << 7)	/* DMA Requests Enable */
+#define IER_UUE			(1 << 6)	/* UART Unit Enable */
+#define IER_NRZE			(1 << 5)	/* NRZ coding Enable */
+#define IER_RTIOE			(1 << 4)	/* Receiver Time Out Interrupt Enable */
+#define IER_MIE			(1 << 3)	/* Modem Interrupt Enable */
+#define IER_RLSE			(1 << 2)	/* Receiver Line Status Interrupt Enable */
+#define IER_TIE			(1 << 1)	/* Transmit Data request Interrupt Enable */
+#define IER_RAVIE			(1 << 0)	/* Receiver Data Available Interrupt Enable */
+
+#define IIR_FIFOES1		(1 << 7)	/* FIFO Mode Enable Status */
+#define IIR_FIFOES0		(1 << 6)	/* FIFO Mode Enable Status */
+#define IIR_TOD			(1 << 3)	/* Time Out Detected */
+#define IIR_IID2			(1 << 2)	/* Interrupt Source Encoded */
+#define IIR_IID1			(1 << 1)	/* Interrupt Source Encoded */
+#define IIR_IP				(1 << 0)	/* Interrupt Pending (active low) */
+
+/* UART 16550 FIFO Control Register */
+#define FCR_FIFOEN			0x01
+#define FCR_RCVRRES			0x02
+#define FCR_XMITRES			0x04
+
+/* Interrupt Enable Register */
+// UART 16550
+#define IER_RXTH			0x01	// Enable Received Data Available Interrupt
+#define IER_TXTH			0x02	// Enable Transmitter Empty Interrupt
+
+#ifdef CONFIG_UART0
+#if defined(CONFIG_COMCERTO_100)
+static void EnableUART0(void)
+{
+	u32 temp;
+	do {    
+   	   temp = *(volatile u32 *)GPIO_IOCTRL_REG | __cpu_to_le32(GPIO_IOCTRL_UART0); 	// enable UART0
+   	   *(volatile u32 *)GPIO_LOCK_REG = __cpu_to_le32(0x55555555); 				// remove lock
+   	   *(volatile u32 *)GPIO_IOCTRL_REG = temp;				// write to ctrl reg
+   	} while (*(volatile u32 *)GPIO_IOCTRL_REG != temp);
+}
+#endif
+#else
+#if defined(CONFIG_COMCERTO_100)
+static void EnableUART1(void)
+{
+	u32 temp;
+
+	do {
+   	   temp = *(volatile u32 *)GPIO_IOCTRL_REG | __cpu_to_le32(GPIO_IOCTRL_UART1); 	// enable UART1
+		*(volatile u32 *)GPIO_LOCK_REG = __cpu_to_le32(0x55555555); 				// remove lock
+		*(volatile u32 *)GPIO_IOCTRL_REG = temp;				// write to ctrl reg
+	} while (*(volatile u32 *)GPIO_IOCTRL_REG != temp);
+}
+#else
+static void EnableUART1(void)
+{
+	*(volatile u32 *)GPIO_PIN_SELECT_REG |= __cpu_to_le32(GPIO_PIN_SELECT_UART1); 		// enable UART1
+}
+#endif
+#endif
+
+void serial_setbrg (void)
+{
+	int baudrate = CONFIG_BAUDRATE;
+	unsigned int reg = 0;
+	unsigned int clk = HAL_get_amba_clk();
+#ifdef CONFIG_UART0 
+	PUART16550REGS uart = (PUART16550REGS) UART0_BASEADDR;
+	PUART16550DLREGS uart_dl = (PUART16550DLREGS) UART0_BASEADDR;
+#else
+	PUART16550REGS uart = (PUART16550REGS) UART1_BASEADDR;
+	PUART16550DLREGS uart_dl = (PUART16550DLREGS) UART1_BASEADDR;
+#endif
+
+	//if ((baudrate = gd->baudrate) <= 0)
+	//	baudrate = CONFIG_BAUDRATE;
+
+	reg = clk / (baudrate * 16);
+	uart->lcr |= __cpu_to_le32(LCR_DLAB); // Enable Divisor Latch access
+	uart_dl->dll = __cpu_to_le32(reg & 0xFF); // Set Divisor Latch Low
+	uart_dl->dlh = __cpu_to_le32((reg >> 8) & 0xFF); // Set Divisor Latch high
+	uart->lcr &= __cpu_to_le32(~LCR_DLAB); // Disable Divisor Latch access
+}
+
+int serial_init (void)
+{
+#ifdef CONFIG_UART0 
+	PUART16550REGS uart = (PUART16550REGS) UART0_BASEADDR;
+#else
+	PUART16550REGS uart = (PUART16550REGS) UART1_BASEADDR;
+#endif
+
+#ifdef CONFIG_UART1
+	EnableUART1();
+#elif defined(CONFIG_COMCERTO_100)
+	EnableUART0();
+#endif
+
+	serial_setbrg ();
+	
+	uart->lcr = __cpu_to_le32(LCR_ONE_STOP | LCR_CHAR_LEN_8);
+	uart->iir_fcr = __cpu_to_le32(FCR_XMITRES | FCR_RCVRRES | FCR_FIFOEN); // Reset, FIFO
+	uart->ier = __cpu_to_le32(IER_UUE);		/* Enable FFUART */
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+#ifdef CONFIG_UART0 
+	PUART16550REGS uart = (PUART16550REGS) UART0_BASEADDR;
+#else
+	PUART16550REGS uart = (PUART16550REGS) UART1_BASEADDR;
+#endif
+
+	/* wait for room in the tx FIFO on FFUART */
+	while ((uart->lsr & __cpu_to_le32(LSR_TEMT))==0) ;
+	uart->data = __cpu_to_le32(c);
+	if (c == '\n')
+		serial_putc ('\r');
+}
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+int serial_getc (void)
+{
+#ifdef CONFIG_UART0 
+	PUART16550REGS uart = (PUART16550REGS) UART0_BASEADDR;
+#else
+	PUART16550REGS uart = (PUART16550REGS) UART1_BASEADDR;
+#endif
+
+	while ((uart->lsr & __cpu_to_le32(LSR_DR)) == 0);
+	return (char)__le32_to_cpu(uart->data & __cpu_to_le32(0xff));	
+}
+
+int serial_tstc (void)
+{
+#ifdef CONFIG_UART0 
+	PUART16550REGS uart = (PUART16550REGS) UART0_BASEADDR;
+#else
+	PUART16550REGS uart = (PUART16550REGS) UART1_BASEADDR;
+#endif
+
+	return __le32_to_cpu(uart->lsr & __cpu_to_le32(LSR_DR));
+}

cpu/arm1136/comcerto/training.c

diff --git a/cpu/arm1136/comcerto/training.c b/cpu/arm1136/comcerto/training.c
new file mode 100644
index 0000000..938fdb9
--- /dev/null
+++ b/cpu/arm1136/comcerto/training.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+#if defined(CONFIG_COMCERTO_100)
+
+#if defined(NEW_DDR_TRAINING)
+#include "training100_new.c" /* new ddr training */
+#else
+#include "training100.c" /* old ddr training */
+#endif
+
+#elif defined(CONFIG_COMCERTO_1000)
+#include "training1000.c"
+#else
+#error "No Architecture selected!!@" 
+#endif

cpu/arm1136/comcerto/training100.c

diff --git a/cpu/arm1136/comcerto/training100.c b/cpu/arm1136/comcerto/training100.c
new file mode 100644
index 0000000..ac7e404
--- /dev/null
+++ b/cpu/arm1136/comcerto/training100.c
@@ -0,0 +1,744 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/hardware.h>
+
+extern u32*  __training_data_start;
+
+typedef struct {
+	unsigned char rd0;
+	unsigned char rd1;
+	unsigned char rd2;
+	unsigned char rd3;
+} dll_rd;
+
+
+u32 wr_loop(u8 dqs_index, u32 find_median);
+dll_rd DLL_check(u8 dqs_index, u8 wr_index, u32 find_median);
+u32 wr_rd_transaction(u32 transaction_size, u32 i,  u8 dqs_index, u8 wr_index,u8 rd_index, u32 mask);
+u32 actual_transaction(u32 transaction_size, u32 i,  u32 mask, u32 ddr_addr, u32 dll_num);
+u32 get_dll(u32 i);
+u32 get_max_addr_space_bit(void);
+void training_gbl_init(void);
+u32 find_best(void);
+
+
+u32 ddr_addr_offset;
+u32 max_addr_space_bit;
+u8 byte_list[16];
+u16 half_word_list[16];
+u32 word_list[16];
+u64 dword_list[16];
+u32 byte_mask[4];
+u32 max_addr_bit_list[15];
+
+
+#define SZ_1K	0x400
+#define SZ_1M	0x100000
+#define SZ_4K	SZ_1K * 4
+#define SZ_8K	SZ_1K * 8
+#define SZ_16K	SZ_1K * 16
+#define SZ_32K	SZ_1K * 32
+#define SZ_64K	SZ_1K * 64
+#define SZ_128K	SZ_1K * 128
+#define SZ_8M	SZ_1M * 8
+#define SZ_16M	SZ_1M * 16
+#define SZ_32M	SZ_1M * 32
+#define SZ_64M	SZ_1M * 64
+
+#define ADDR_JUMP_SIZE	SZ_128K
+
+
+void start_training(void)
+{
+	//initialize global data
+	training_gbl_init();
+
+	//start DDR training
+	find_best();
+}
+
+void training_gbl_init(void)
+{
+	u8 i = 0;
+	u8 __byte_list[16] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x19, 0x2a, 0x3b, 0x4c, 0x5d, 0x6e, 0x7f};
+	u16 __half_word_list[16] = {0x0000, 0x1111, 0x2222, 0x3333, 0x4444, 0x5555, 0x6666, 0x7777, 0x0888, 0x1999, 0x2aaa, 0x3bbb, 0x4ccc, 0x5ddd, 0x6eee, 0x7fff};
+	u32 __word_list[16] = {0x00000000, 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x08888888, 0x19999999, 0x2aaaaaaa, 0x3bbbbbbb, 0x4ccccccc, 0x5ddddddd, 0x6eeeeeee, 0x7fffffff};
+	u64 __dword_list[16] = {0x0000000000000000LL, 0x1111111111111111LL, 0x2222222222222222LL, 0x3333333333333333LL, 0x4444444444444444LL, 0x5555555555555555LL, 0x6666666666666666LL, 0x7777777777777777LL, 0x0888888888888888LL, 0x1999999999999999LL, 0x2aaaaaaaaaaaaaaaLL, 0x3bbbbbbbbbbbbbbbLL, 0x4cccccccccccccccLL, 0x5dddddddddddddddLL, 0x6eeeeeeeeeeeeeeeLL, 0x7fffffffffffffffLL};
+	u32 __byte_mask[4]  = {0xff,0xff00,0xff0000,0xff000000}; 
+	u32 __max_addr_bit_list[15] = {0x00100000, 0x00200000, 0x00400000, 0x00800000, 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, 0x20000000, 0x40000000};
+	u32 __ddr_addr_offset = 0;
+	u32 __max_addr_space_bit = 0;
+
+	// remap global data to internal memory
+	ddr_addr_offset = (u32)&__training_data_start;
+	max_addr_space_bit = (u32)(&__training_data_start + sizeof(ddr_addr_offset));
+	byte_list[i] = (u8)(&__training_data_start + sizeof(max_addr_space_bit));
+	half_word_list[i] = (u16)(&__training_data_start + sizeof(byte_list));
+	word_list[i] = (u32)(&__training_data_start + sizeof(half_word_list));
+	dword_list[i] = (u64)(&__training_data_start + sizeof(word_list));
+
+
+	ddr_addr_offset = __ddr_addr_offset;
+	max_addr_space_bit = __max_addr_space_bit;
+
+	for (i = 0; i < 16; i++)
+	{
+		byte_list[i] = __byte_list[i];
+		half_word_list[i] = __half_word_list[i];
+		word_list[i] = __word_list[i];
+		dword_list[i] = __dword_list[i];
+	}
+
+	for (i = 0; i < 4; i++)
+		byte_mask[i]  = __byte_mask[i]; 
+	
+	for (i = 0; i < 15; i++)
+		max_addr_bit_list[i] = __max_addr_bit_list[i];
+
+}
+
+u32 find_best(void)
+{
+	u8 dqs_ind = FAILURE; // dqs indication initialize to failure
+	u8 dqs_min_val = UNSET, dqs_max_val = UNSET, dqs_median = UNSET; 
+	u8 dqs_index;
+	u8 wr_median_val, rd_median, rslt= FAILURE;
+	u32 i;
+	u32 wr_rslt = FAILURE;
+	u32 dll_num; 
+	register int reg_0 __asm__ ("r3");
+	register int reg_1 __asm__ ("r4");
+	u32 max_mem_reg;
+	u64 *dst, *src;
+	dll_rd rd;
+
+  	ddr_addr_offset = 0; // init
+  	if ((__le64_to_cpu(*(&CS_MAP)) & 0x3) == 3) {
+  		max_addr_space_bit = get_max_addr_space_bit();
+  	}
+
+	for(dqs_index = LOW_DQS_OUT; dqs_index <= HIGH_DQS_OUT; dqs_index++) {// DQS loop
+		wr_rslt = wr_loop(dqs_index, 0);
+		// set min/max values;
+		if (wr_rslt  == FAILURE) {
+			if ((dqs_min_val != UNSET) && (dqs_min_val==(dqs_index-1))) {
+				dqs_min_val = UNSET;
+			}
+			if ((dqs_min_val!=UNSET) && (dqs_max_val==UNSET)){
+				dqs_max_val = dqs_index-1; 
+				break;
+			}
+		} else { // SUCCESS
+			if (dqs_min_val==UNSET) {
+				dqs_min_val = dqs_index; 
+				dqs_ind = SUCCESS;
+			}
+		} 
+	} 
+
+	if (dqs_ind == FAILURE) {
+		wr_median_val = HIGH_DQS_OUT;
+		dqs_median    = HIGH_WR_DQS;
+		rd.rd0        = HIGH_RD0;
+		rd.rd1        = HIGH_RD1;
+		rd.rd2        = HIGH_RD2;
+		rd.rd3        = HIGH_RD3;
+		DENALI_WR_DQS  = wr_median_val;
+		DENALI_DQS_OUT = dqs_median;
+		DENALI_DQS_DELAY0 = rd.rd0;
+		DENALI_DQS_DELAY1 = rd.rd1;
+		DENALI_DQS_DELAY2 = rd.rd2;
+		DENALI_DQS_DELAY3 = rd.rd3;
+		return 0xffff;
+	} else { //SUCCESS
+		if ((dqs_min_val!=UNSET) && (dqs_max_val==UNSET)){
+			dqs_max_val = dqs_index-1;
+		}
+		dqs_median = (dqs_min_val + dqs_max_val)/2;
+	}
+
+	// end procedure
+	wr_median_val = wr_loop(dqs_median,1);
+	rd = DLL_check(dqs_median,wr_median_val,1);
+	if ((rd.rd0==0) || (rd.rd1==0) || (rd.rd2==0) || (rd.rd3==0)) {
+		wr_median_val = HIGH_DQS_OUT;
+		dqs_median    = HIGH_WR_DQS;
+		rd.rd0        = HIGH_RD0;
+		rd.rd1        = HIGH_RD1;
+		rd.rd2        = HIGH_RD2;
+		rd.rd3        = HIGH_RD3;
+		DENALI_WR_DQS  = wr_median_val;
+		DENALI_DQS_OUT = dqs_median;
+		DENALI_DQS_DELAY0 = rd.rd0;
+		DENALI_DQS_DELAY1 = rd.rd1;
+		DENALI_DQS_DELAY2 = rd.rd2;
+		DENALI_DQS_DELAY3 = rd.rd3;
+		return 0xffff; // failure
+	}
+
+	//configure median values
+	DENALI_WR_DQS  = wr_median_val;
+	DENALI_DQS_OUT = dqs_median;
+	DENALI_DQS_DELAY0 = rd.rd0;
+	DENALI_DQS_DELAY1 = rd.rd1;
+	DENALI_DQS_DELAY2 = rd.rd2;
+	DENALI_DQS_DELAY3 = rd.rd3;
+
+
+	max_mem_reg = __le64_to_cpu(*(&AHB_MAX_MEM_REG)) & (0x80000000 - ADDR_JUMP_SIZE);
+	i=0;
+	while (ddr_addr_offset<max_mem_reg) {
+		i+=1;
+		if ((i&0xc)==0) {
+			rd_median = rd.rd0;
+			dll_num=0;
+		} else if ((i&0xc)==1) { 
+			rd_median = rd.rd1;
+			dll_num=1;
+		} else if ((i&0xc)==2) { 
+			rd_median = rd.rd2;
+			dll_num=2;
+		} else {
+			rd_median = rd.rd3;
+			dll_num=3;
+		}
+		if ((__le64_to_cpu(*(&REDUC)&0x1)==1) && ((dll_num==2) || (dll_num==3)))  {
+			//REDUC 
+			//half datapath mode in which DLL2 and 3 are not used.
+			continue;
+		}
+
+		switch (i & 0x3) {
+			case 0: 
+				rslt = wr_rd_transaction(BYTE_SZ, dll_num, dqs_median, wr_median_val, rd_median,0);
+				break;
+			case 1: 
+				rslt = wr_rd_transaction(HALF_WORD, dll_num, dqs_median, wr_median_val, rd_median,0);
+				break;
+			case 2: 
+				rslt = wr_rd_transaction(WORD, dll_num, dqs_median, wr_median_val, rd_median,0);
+				break;
+			case 3: 
+				rslt = wr_rd_transaction(DOUBLE_WORD, dll_num, dqs_median, wr_median_val, rd_median,0);
+				break;
+		};
+
+		if (rslt == FAILURE) {
+			wr_median_val = HIGH_DQS_OUT;
+			dqs_median    = HIGH_WR_DQS;
+			rd.rd0        = HIGH_RD0;
+			rd.rd1        = HIGH_RD1;
+			rd.rd2        = HIGH_RD2;
+			rd.rd3        = HIGH_RD3;
+			DENALI_WR_DQS  = wr_median_val;
+			DENALI_DQS_OUT = dqs_median;
+			DENALI_DQS_DELAY0 = rd.rd0;
+			DENALI_DQS_DELAY1 = rd.rd1;
+			DENALI_DQS_DELAY2 = rd.rd2;
+			DENALI_DQS_DELAY3 = rd.rd3;
+			return 0xffff;
+		}
+	};
+
+
+
+	//*** burst ***
+	for (i=0;i<16;i++) {
+		src = &dword_list[i];
+		dst = 0;
+		 __asm__ __volatile__ ("ldmia %0, {%1,%2}" \
+	        	  : "+r" (src), "=r" (reg_0), "=r" (reg_1) \
+        	  );
+
+		 __asm__ __volatile__ ("stmia %0, {%1,%2}" \
+		          : "+r" (dst), "=r" (reg_0), "=r" (reg_1) \
+	          );
+
+		if (*src!=*dst)  {
+			wr_median_val = HIGH_DQS_OUT;
+			dqs_median    = HIGH_WR_DQS;
+			rd.rd0        = HIGH_RD0;
+			rd.rd1        = HIGH_RD1;
+			rd.rd2        = HIGH_RD2;
+			rd.rd3        = HIGH_RD3;
+			DENALI_WR_DQS  = wr_median_val;
+			DENALI_DQS_OUT = dqs_median;
+			DENALI_DQS_DELAY0 = rd.rd0;
+			DENALI_DQS_DELAY1 = rd.rd1;
+			DENALI_DQS_DELAY2 = rd.rd2;
+			DENALI_DQS_DELAY3 = rd.rd3;
+			return 0xffff; //failure
+		}
+	}
+
+	return SUCCESS;
+}
+
+
+u32 get_max_addr_space_bit(void) {
+	u32 max_mem_reg;
+	max_mem_reg = __le32_to_cpu(*(&AHB_MAX_MEM_REG));
+	
+	if ((max_mem_reg & 0x40000000) != 0) {
+		return 31;
+	} else if ((max_mem_reg & 0x20000000) != 0) {
+		return 30;
+	} else if ((max_mem_reg & 0x10000000) != 0) {
+		return 29;
+	} else if ((max_mem_reg & 0x08000000) != 0) {
+		return 28;
+	} else if ((max_mem_reg & 0x04000000) != 0) {
+		return 27;
+	} else if ((max_mem_reg & 0x02000000) != 0) {
+		return 26;
+	} else if ((max_mem_reg & 0x01000000) != 0) {
+		return 25;
+	} else if ((max_mem_reg & 0x00800000) != 0) {
+		return 24;
+	} else if ((max_mem_reg & 0x00400000) != 0) {
+		return 23;
+	} else if ((max_mem_reg & 0x00200000) != 0) {
+		return 22;
+	} else if ((max_mem_reg & 0x00100000) != 0) {
+		return 21;
+	};
+	return 0;
+}
+
+u32 wr_loop(u8 dqs_index, u32 find_median) {
+	u8 wr_index;
+	u32 rd_rslt = FAILURE; //  rd indication initialize to failure: Failure or Success
+	u8 wr_min_val = UNSET , wr_max_val = UNSET;
+	u8 wr_median_val = FAILURE;
+	dll_rd rd;
+
+	for(wr_index = LOW_WR_DQS; wr_index <= HIGH_WR_DQS; wr_index++) { /* WR loop */
+		rd = DLL_check(dqs_index, wr_index,find_median);
+		rd_rslt = ((rd.rd0>0) && (rd.rd1>0) && (rd.rd2>0) && (rd.rd3>0)) ? SUCCESS : FAILURE;
+
+		if (rd_rslt == FAILURE) {
+			if (find_median == 1) {
+				if ((wr_min_val != UNSET) && (wr_min_val==(wr_index-1))) {
+					wr_min_val = UNSET;
+				}
+				if ((wr_min_val!=UNSET) && (wr_max_val==UNSET)) {
+					wr_max_val = wr_index-1;
+				}
+				if ((wr_min_val!=UNSET) && (wr_max_val!=UNSET)) {
+					wr_median_val = (wr_min_val+wr_max_val)/2;
+					return wr_median_val;
+				}
+			}
+		} else { // SUCCESS
+			if (find_median == 1) {
+				if (wr_min_val==UNSET) {
+					wr_min_val = wr_index;
+				}
+			} else {
+				return SUCCESS;
+			}
+		}	 
+	}
+	
+	if (find_median == 1) {
+		if ((wr_min_val!=UNSET) && (wr_max_val==UNSET)) {
+			wr_max_val = wr_index-1;
+			wr_median_val = (wr_min_val+wr_max_val)/2;
+		}
+	};
+
+	return wr_median_val;
+}
+
+dll_rd DLL_check(u8 dqs_index, u8 wr_index, u32 find_median) {
+	u32 transaction_size;
+	u32 rslt = FAILURE, dll0_rslt = FAILURE, dll1_rslt = FAILURE, dll2_rslt = FAILURE, dll3_rslt = FAILURE;
+	u8 rd_index;
+	u32 i;
+	dll_rd rd;
+	u8 rd0_min_val=UNSET, rd1_min_val=UNSET, rd2_min_val=UNSET, rd3_min_val=UNSET;
+	u8 rd0_max_val=UNSET, rd1_max_val=UNSET, rd2_max_val=UNSET, rd3_max_val=UNSET;
+	u8 rd0_median=UNSET, rd1_median=UNSET, rd2_median=UNSET, rd3_median=UNSET;
+	
+	// byte order per DLL
+	///////////////////////
+	//  0     1     2     3
+	//  4     5     6     7
+	// DLL0  DLL1  DLL2  DLL4
+	/////////// DLL0 //////////////
+	for (rd_index = LOW_RD0; rd_index <= HIGH_RD0; rd_index++) {
+		transaction_size = BYTE_SZ;   // byte (8 bits) 
+		for(i = 0; i <= 15; i=i+4){ 
+			rslt = wr_rd_transaction(transaction_size, i, dqs_index,wr_index,rd_index,1);
+			if (rslt == FAILURE) continue;
+			else if (rslt == SUCCESS) break;
+		}
+		if (rslt == SUCCESS) { // only for SUCCESS continue checking for the next transaction width	       
+			transaction_size = DOUBLE_WORD;   // double-word (64 bits) 
+			for(i = 0; i <= 15; i=i+16){ 
+				rslt = wr_rd_transaction(transaction_size, i, dqs_index,wr_index,rd_index,1);
+				if (rslt == FAILURE) continue;
+				else if (rslt == SUCCESS) break;
+			}// end of transaction_size DOUBLE_WORD
+		} // end of transaction_size BYTE_SZ
+ 
+		// find results of dll run
+		if (find_median == 1) { 
+			if (rslt == FAILURE) {
+				if ((rd0_min_val != UNSET) && (rd0_min_val==(rd_index-1))) {
+					rd0_min_val = UNSET;
+				}
+				if ((rd0_min_val != UNSET)  && (rd0_max_val == UNSET)) {
+					rd0_max_val = rd_index-1;
+					dll0_rslt = SUCCESS;
+					break;
+				}
+				} else if (rslt == SUCCESS) {
+					if (rd0_min_val == UNSET) {
+						rd0_min_val = rd_index;
+					}
+				}
+		} else {
+			if (rslt == FAILURE) continue;
+			else if (rslt == SUCCESS) break;// one SUCCESS is enough when no median calculation is needed
+		} // dll0 median
+	} // DLL0
+
+	if (rslt == SUCCESS) dll0_rslt = SUCCESS;
+	
+	if (find_median == 1) { 
+		if ((rd0_min_val != UNSET)  && (rd0_max_val == UNSET)) {
+			rd0_max_val = rd_index-1;
+		}
+		rd0_median = (rd0_min_val + rd0_max_val)/2;
+	}
+
+	/////////// DLL1 //////////////
+	for (rd_index = LOW_RD1; rd_index <= HIGH_RD1; rd_index++) {
+		transaction_size = BYTE_SZ;   // byte (8 bits) 
+		for(i = 1; i <= 15; i=i+4){ 
+			rslt = wr_rd_transaction(transaction_size, i, dqs_index,wr_index,rd_index,1);
+			if (rslt == FAILURE) continue;
+			else if (rslt == SUCCESS) break;
+		}
+		if (rslt == SUCCESS) { // only for SUCCESS continue checking for the next transaction width
+			transaction_size = DOUBLE_WORD;   // double-word (64 bits) 
+			for(i = 1; i <= 15; i=i+16){ 
+				rslt = wr_rd_transaction(transaction_size, i, dqs_index,wr_index,rd_index,1);
+				if (rslt == FAILURE) continue;
+				else if (rslt == SUCCESS) break;
+			}// end of transaction_size DOUBLE_WORD
+		} // end of transaction_size BYTE_SZ
+	 
+		// find results of dll run
+		if (find_median == 1) { 
+			if (rslt == FAILURE) {
+				if ((rd1_min_val != UNSET) && (rd1_min_val==(rd_index-1))) {
+					rd1_min_val = UNSET;
+				}
+				if ((rd1_min_val != UNSET)  && (rd1_max_val == UNSET)) {
+					rd1_max_val = rd_index-1;
+					dll1_rslt = SUCCESS;
+					break;
+				}
+			} else if (rslt == SUCCESS) {
+				if (rd1_min_val == UNSET) {
+					rd1_min_val = rd_index;
+				}
+			}
+		} else {
+			if (rslt == FAILURE) continue;
+			else if (rslt == SUCCESS) break;// one SUCCESS is enough when no median calculation is needed
+		} // dll1 median
+	} // DLL1
+
+
+	if (rslt == SUCCESS) dll1_rslt = SUCCESS;
+
+	if (find_median == 1) { 
+		if ((rd1_min_val != UNSET)  && (rd1_max_val == UNSET)) {
+			rd1_max_val = rd_index-1;
+		}
+		rd1_median = (rd1_min_val + rd1_max_val)/2;
+	}
+
+	if ((__le64_to_cpu(*(&REDUC))&0x1)==1)  {
+		dll2_rslt = SUCCESS;
+		dll3_rslt = SUCCESS;
+	} else {
+		/////////// DLL2 //////////////
+		for (rd_index = LOW_RD2; rd_index <= HIGH_RD2; rd_index++) {
+			transaction_size = BYTE_SZ;   // byte (8 bits) 
+			for(i = 2; i <= 15; i=i+4){ 
+				rslt = wr_rd_transaction(transaction_size, i, dqs_index,wr_index,rd_index,1);
+				if (rslt == FAILURE) continue;
+				else if (rslt == SUCCESS) break;
+			}
+			if (rslt == SUCCESS) { // only for SUCCESS continue checking for the next transaction width
+				transaction_size = DOUBLE_WORD;   // double-word (64 bits) 
+				for(i = 2; i <= 15; i=i+16){ 
+					rslt = wr_rd_transaction(transaction_size, i, dqs_index,wr_index,rd_index,1);
+					if (rslt == FAILURE) continue;
+					else if (rslt == SUCCESS) break;
+				}// end of transaction_size DOUBLE_WORD
+			} // end of transaction_size BYTE_SZ
+		
+			// find results of dll run
+			if (find_median == 1) { 
+				if (rslt == FAILURE) {
+					if ((rd2_min_val != UNSET) && (rd2_min_val==(rd_index-1))) {
+						rd2_min_val = UNSET;
+					}
+					if ((rd2_min_val != UNSET)  && (rd2_max_val == UNSET)) {
+						rd2_max_val = rd_index-1;
+						dll2_rslt = SUCCESS;
+						break;
+					}
+				} else if (rslt == SUCCESS) {
+					if (rd2_min_val == UNSET) {
+						rd2_min_val = rd_index;
+					}
+				}
+			} else {
+				if (rslt == FAILURE) continue;
+				else if (rslt == SUCCESS) break;// one SUCCESS is enough when no median calculation is needed
+			} // dll2 median
+		} // DLL2
+		
+		if (rslt == SUCCESS) dll2_rslt = SUCCESS;
+		
+		if (find_median == 1) { 
+			if ((rd2_min_val != UNSET)  && (rd2_max_val == UNSET)) {
+				rd2_max_val = rd_index-1;
+			}
+			rd2_median = (rd2_min_val + rd2_max_val)/2;
+		}
+		
+		/////////// DLL3 //////////////
+		for (rd_index = LOW_RD3; rd_index <= HIGH_RD3; rd_index++) {
+			transaction_size = BYTE_SZ;   // byte (8 bits) 
+			for(i = 3; i <= 15; i=i+4){ 
+				rslt = wr_rd_transaction(transaction_size, i, dqs_index,wr_index,rd_index,1);
+				if (rslt == FAILURE) continue;
+				else if (rslt == SUCCESS) break;
+			}
+			if (rslt == SUCCESS) { // only for SUCCESS continue checking for the next transaction width
+				transaction_size = DOUBLE_WORD;   // double-word (64 bits) 
+				for(i = 3; i <= 15; i=i+16){ 
+					rslt = wr_rd_transaction(transaction_size, i, dqs_index,wr_index,rd_index,1);
+					if (rslt == FAILURE) continue;
+					else if (rslt == SUCCESS) break;
+				}// end of transaction_size DOUBLE_WORD
+			} // end of transaction_size BYTE_SZ
+		
+			// find results of dll run
+			if (find_median == 1) { 
+				if (rslt == FAILURE) {
+					if ((rd3_min_val != UNSET) && (rd3_min_val==(rd_index-1))) {
+						rd3_min_val = UNSET;
+					}
+				if ((rd3_min_val != UNSET)  && (rd3_max_val == UNSET)) {
+					rd3_max_val = rd_index-1;
+					dll3_rslt = SUCCESS;
+					break;
+				}
+				} else if (rslt == SUCCESS) {
+					if (rd3_min_val == UNSET) {
+						rd3_min_val = rd_index;
+					}
+				}
+			} else {
+				if (rslt == FAILURE) continue;
+				else if (rslt == SUCCESS) break;// one SUCCESS is enough when no median calculation is needed
+			} // dll3 median
+		} // DLL3
+		if (rslt == SUCCESS) dll3_rslt = SUCCESS;
+		if (find_median == 1) { 
+			if ((rd3_min_val != UNSET)  && (rd3_max_val == UNSET)) {
+				rd3_max_val = rd_index-1;
+			}
+			rd3_median = (rd3_min_val + rd3_max_val)/2;
+		}
+	}; // REDUC
+
+	// all dll found a success values for current dqs and wr values.
+	// For initialization: 0s indicates Failure
+	rd.rd0 = 0;
+	rd.rd1 = 0;
+	rd.rd2 = 0;
+	rd.rd3 = 0;
+	if ((dll0_rslt & dll1_rslt & dll2_rslt & dll3_rslt & 0x1) == 1) {//return SUCCESS;
+		if (find_median == 1) {
+			rd.rd0 = rd0_median;
+			rd.rd1 = rd1_median;
+			rd.rd2 = rd2_median;
+			rd.rd3 = rd3_median;
+		} else {
+			// 1s indicates Success
+			rd.rd0 = 1;
+			rd.rd1 = 1;
+			rd.rd2 = 1;
+			rd.rd3 = 1;
+		}
+	} 
+	
+	return rd; // 0s indicate Failure
+}
+
+u32 wr_rd_transaction(u32 transaction_size, u32 i, u8 dqs_index, u8 wr_index, u8 rd_index, u32 mask) {
+	u32 dll_num;
+	u32 ddr_addr, limit_addr;
+
+ 	// set values for current transaction
+	DENALI_WR_DQS  = wr_index;
+ 	DENALI_DQS_OUT = dqs_index;
+	dll_num = get_dll(i);
+ 	switch (dll_num) {
+ 		case 0:DENALI_DQS_DELAY0 = rd_index;break;
+ 		case 1:DENALI_DQS_DELAY1 = rd_index;break;
+ 		case 2:DENALI_DQS_DELAY2 = rd_index;break;
+ 		case 3:DENALI_DQS_DELAY3 = rd_index;break;
+ 	};
+	
+	limit_addr = __le64_to_cpu(*(&AHB_MAX_MEM_REG)) & 0x7fffffff;
+	ddr_addr_offset = (ddr_addr_offset + ADDR_JUMP_SIZE) & limit_addr; // limit the address space to ahb configured value.
+	
+	// the address is shifted by 8 to ensure 64 byte transaction in region.
+	// 0x80000000 + dll_num + offset *2^ (0 for byte, 1 for half word , 2 for word, 3 for double word.) 
+
+	if ((__le64_to_cpu(*(&CS_MAP)) & 0x3) == 3) {
+		ddr_addr = ddr_addr_offset;
+		// default cs#0
+		ddr_addr &= (~(max_addr_bit_list[max_addr_space_bit-21]));
+ 		if (actual_transaction(transaction_size, i, mask, ddr_addr, dll_num) == SUCCESS) {
+			// set cs#1
+			ddr_addr |= max_addr_bit_list[max_addr_space_bit-21];
+			return actual_transaction(transaction_size, i, mask, ddr_addr, dll_num);
+		} else {
+			return FAILURE;
+		}
+	} else {
+		return actual_transaction(transaction_size, i, mask, ddr_addr_offset, dll_num);
+	} 
+}
+
+u32 get_dll(u32 i) {
+	u32 rslt=0;
+	switch (i) {
+		case 0: case 4: case 8: case 12 : rslt = 0;break;
+		case 1: case 5: case 9: case 13 : rslt = 1;break;
+		case 2: case 6: case 10: case 14: rslt = 2;break;
+		case 3: case 7: case 11: case 15: rslt = 3;break;
+	};
+	return rslt;
+}
+
+u32 actual_transaction(u32 transaction_size, u32 i, u32 mask, u32 ddr_addr, u32 dll_num) {
+	u32 rslt = FAILURE;
+
+	// per transaction width, write and read transaction.
+	switch (transaction_size) {
+	
+	case BYTE_SZ: 
+	if (mask == 1) {
+		*(&WRITE_VAL_U8+i+ddr_addr) = 0x00;
+		*(&WRITE_VAL_U8+i+0x10+ddr_addr) = 0xaa;
+		*(&WRITE_VAL_U8+i+0x20+ddr_addr) = 0x55;
+		if (((*(&WRITE_VAL_U8+i+ddr_addr)) & 0xff)==0x00) {
+			if (((*(&WRITE_VAL_U8+i+0x10+ddr_addr)) & 0xff)==0xaa) {
+				if (((*(&WRITE_VAL_U8+i+0x20+ddr_addr)) & 0xff)==0x55) {
+					rslt = SUCCESS; // per dll
+				}
+			}
+		}
+		*(&WRITE_VAL_U8+i+ddr_addr) = 0;//clear
+		*(&WRITE_VAL_U8+i+0x10+ddr_addr) = 0;//clear
+		*(&WRITE_VAL_U8+i+0x20+ddr_addr) = 0;//clear
+	} else {
+		*(&WRITE_VAL_U8+ddr_addr) = 0x00;
+		*(&WRITE_VAL_U8+0x10+ddr_addr) = 0xaa;
+		*(&WRITE_VAL_U8+0x20+ddr_addr) = 0x55;
+		if (*(&WRITE_VAL_U8+ddr_addr) == 0x00) {
+			if (*(&WRITE_VAL_U8+0x10+ddr_addr) == 0xaa) {
+				if (*(&WRITE_VAL_U8+0x20+ddr_addr) == 0x55) {
+					rslt = SUCCESS;
+				}
+			}
+		}
+		*(&WRITE_VAL_U8+ddr_addr) = 0; //clear
+		*(&WRITE_VAL_U8+i+0x10+ddr_addr) = 0;//clear
+		*(&WRITE_VAL_U8+i+0x20+ddr_addr) = 0;//clear
+	}
+	break;
+	
+	case HALF_WORD:  // no masking option
+	*(&WRITE_VAL_U16+ddr_addr) = __cpu_to_le16(0x0000);
+	*(&WRITE_VAL_U16+0x10+ddr_addr) = __cpu_to_le16(0xaaaa);
+	*(&WRITE_VAL_U16+0x20+ddr_addr) = __cpu_to_le16(0x5555);
+	if (__le16_to_cpu(*(&WRITE_VAL_U16+ddr_addr)) == 0x0000) {
+		if (__le16_to_cpu(*(&WRITE_VAL_U16+0x10+ddr_addr)) == 0xaaaa) {
+			if (__le16_to_cpu(*(&WRITE_VAL_U16+0x20+ddr_addr)) == 0x5555) {
+				rslt = SUCCESS;
+			}
+		}
+	}
+	*(&WRITE_VAL_U16+ddr_addr) = __cpu_to_le16(0); //clear
+	*(&WRITE_VAL_U16+i+0x10+ddr_addr) = __cpu_to_le16(0);//clear
+	*(&WRITE_VAL_U16+i+0x20+ddr_addr) = __cpu_to_le16(0);//clear
+	break;
+	
+	case WORD:// no masking option
+	*(&WRITE_VAL_U32+ddr_addr) = __cpu_to_le32(0x00000000);
+	*(&WRITE_VAL_U32+0x10+ddr_addr) = __cpu_to_le32(0xaaaaaaaa);
+	*(&WRITE_VAL_U32+0x20+ddr_addr) = __cpu_to_le32(0x55555555);
+	if (__le32_to_cpu(*(&WRITE_VAL_U32+ddr_addr)) == 0x00000000) {
+		if (__le32_to_cpu(*(&WRITE_VAL_U32+0x10+ddr_addr)) == 0xaaaaaaaa) {
+			if (__le32_to_cpu(*(&WRITE_VAL_U32+0x20+ddr_addr)) == 0x55555555) {
+				rslt = SUCCESS;
+			}
+		}
+	}
+	*(&WRITE_VAL_U32+ddr_addr) = __cpu_to_le32(0); //clear
+	*(&WRITE_VAL_U32+0x10+ddr_addr) = __cpu_to_le32(0); //clear
+	*(&WRITE_VAL_U32+0x20+ddr_addr) = __cpu_to_le32(0); //clear
+	break;
+	
+	case DOUBLE_WORD: // no masking : full 64 bits
+	*(&WRITE_VAL_U64+ddr_addr) = __cpu_to_le64(0x0000000000000000LL);
+	*(&WRITE_VAL_U64+0x10+ddr_addr) = __cpu_to_le64(0x2aaaaaaaaaaaaaaaLL);
+	*(&WRITE_VAL_U64+0x20+ddr_addr) = __cpu_to_le64(0x5555555555555555LL);
+	if (__le64_to_cpu(*(&WRITE_VAL_U64+ddr_addr)) == 0x0000000000000000LL) {
+		if (__le64_to_cpu(*(&WRITE_VAL_U64+0x10+ddr_addr)) == 0x2aaaaaaaaaaaaaaaLL) {
+			if (__le64_to_cpu(*(&WRITE_VAL_U64+0x20+ddr_addr)) == 0x5555555555555555LL) {
+				rslt = SUCCESS;
+			}
+		}
+	}
+	*(&WRITE_VAL_U64+ddr_addr) = __cpu_to_le64(0); //clear
+	*(&WRITE_VAL_U64+0x10+ddr_addr) = __cpu_to_le64(0); //clear
+	*(&WRITE_VAL_U64+0x20+ddr_addr) = __cpu_to_le64(0); //clear
+	break;
+	
+	}; // switch transaction_size
+
+	return rslt;
+}
+
+

cpu/arm1136/comcerto/training1000.c

diff --git a/cpu/arm1136/comcerto/training1000.c b/cpu/arm1136/comcerto/training1000.c
new file mode 100644
index 0000000..a37bc1a
--- /dev/null
+++ b/cpu/arm1136/comcerto/training1000.c
@@ -0,0 +1,786 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+//#define DDR_TRAINING_MODE_DEBUG_PRINTS  1
+#undef  DDR_TRAINING_MODE_DEBUG_PRINTS
+
+#define SZ_1K	        0x400
+#define SZ_128K         (SZ_1K * 128)
+#define ADDR_JUMP_SIZE  SZ_128K
+
+#define MT_ADDR1_DST  (DDR_BASEADDR + 0xff00)
+#define MT_ADDR2_DST  (DDR_BASEADDR + (PHYS_SDRAM_SIZE >> 1) + 0xff00) 
+
+/* Controller register defines used in training */
+#define DENALI_WR_DQS_DELAY0		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x11B))
+#define DENALI_WR_DQS_DELAY1		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x11C))
+#define DENALI_WR_DQS_DELAY2		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x11D))
+#define DENALI_WR_DQS_DELAY3		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x11E))
+
+#define DENALI_SW_LEVELING_START	*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x278))
+#define DENALI_SW_LEVELING_MODE		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x279))
+#define DENALI_SW_LEVELING_LOAD		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x276))
+
+#define DENALI_DLL_MADJ0		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x148))
+#define DENALI_DLL_ADJ0		        *((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x149))
+
+#define DENALI_DLL_ADJ1_DS0		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x14A))
+#define DENALI_DLL_ADJ1_DS1		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x14E))
+#define DENALI_DLL_ADJ1_DS2		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x152))
+#define DENALI_DLL_ADJ1_DS3		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x156))
+
+#define DENALI_DLL_ADJ0_DS0             *((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x149))
+#define DENALI_DLL_ADJ0_DS1             *((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x14D))
+#define DENALI_DLL_ADJ0_DS2             *((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x151))
+#define DENALI_DLL_ADJ0_DS3             *((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x155))
+
+#define DENALI_DLL_ADJ3_DS0             *((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x159))
+#define DENALI_DLL_ADJ3_DS1             *((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x15D))
+#define DENALI_DLL_ADJ3_DS2             *((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x161))
+#define DENALI_DLL_ADJ3_DS3             *((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x165))
+
+static u8 do_wr_rd_transaction(u32 ddr_addr_offset, u64*, u32*, u16 mode);
+static int mdma_test(u64 *);
+
+extern void arm_write64(u64 data,volatile u64 *p);
+extern int mdma_memcpy(void *src, void *dst, int len, unsigned int *crc);
+
+extern int serial_init(void);
+extern void serial_puts(const char *s);
+extern void serial_putc(const char c);
+
+typedef struct adj2_ds_s
+{
+  u8 win_start;
+  u8 win_end;
+  u8 win;
+
+  u8 gWin;
+  u8 gWin_start;
+  u8 gWin_end;
+  u8 inx; 
+}adj2_ds_t;
+
+typedef struct adj2_val_s
+{
+  adj2_ds_t ds0;
+  adj2_ds_t ds1;
+  adj2_ds_t ds2;
+  adj2_ds_t ds3;
+}adj2_val_t;
+
+#ifdef DDR_TRAINING_MODE_DEBUG_PRINTS
+/* use to print only byte */
+static char *simple_itoa1(unsigned int i, char *s)
+{
+    char local[5];
+    char *p = &local[4];
+    *p-- = '\0';
+	 i = i & 0xff;
+    do {
+        *p-- = '0' + i % 10;
+        i /= 10;
+    } while (i > 0);
+    memcpy(s, p+1, 4);
+    return s;
+}
+#endif
+
+static void adj2_dsx_calculate_window(u8 result, u8 dll_val, u8 dqs_index, adj2_ds_t *adj2)
+{
+	u8 win;
+#ifdef  DDR_TRAINING_MODE_DEBUG_PRINTS
+	char s[5];
+	u8 dsx = 0;
+#endif
+
+	if (!result) /* success */ 
+	{
+	  	/* its first time success, start counting from here */
+		if (adj2->win_start == 0)
+		{
+			adj2->win_start = adj2->win_end = dll_val;
+		}
+		else  {
+			adj2->win_end++;
+			/* close the window, if we reach the end point of adj1 range */
+			if (dll_val == ADJ1_MAX_VAL)  {
+				win = (adj2->win_end - adj2->win_start) + 1;
+			        if (adj2->win < win)
+					adj2->win = win;
+
+				/* is this window bigger than the previous one, then take it */
+				if (adj2->gWin < win)
+				{
+					adj2->gWin = win;
+					adj2->gWin_start = adj2->win_start;
+					adj2->gWin_end = adj2->win_end;
+					adj2->inx = dqs_index; 
+				}
+			}
+		}
+	}
+	else /* failure */
+	{
+		if (adj2->win_start == 0)
+		{
+			//window not yet started, so nothing to do 
+		}
+		else
+		{
+			//this window ends here,calculate window size
+			win = (adj2->win_end - adj2->win_start) + 1;
+
+#ifdef  DDR_TRAINING_MODE_DEBUG_PRINTS
+	    		serial_putc('\n');
+			if (result & 0x1)
+				dsx = 0;
+			else if (result & 0x2)
+				dsx = 1;
+			else if (result & 0x4)
+				dsx = 2;
+			else if (result & 0x8)
+				dsx = 3;
+	    		serial_putc('[');
+			serial_puts("ds");
+	    		serial_puts(simple_itoa1(dsx,s));
+	    		serial_putc(':');
+	    		serial_puts(simple_itoa1(adj2->win_start,s));
+	    		serial_putc('-');
+	    		serial_puts(simple_itoa1(adj2->win_end,s));
+	    		serial_putc('=');
+	    		serial_puts(simple_itoa1(win,s));
+	    		serial_putc(']');
+#endif
+
+			if (adj2->win < win)
+			{
+				adj2->win = win;
+			}
+
+			//is this window bigger than the previous one, then take it
+			if (adj2->gWin < win)
+			{
+				adj2->gWin = win;
+				adj2->gWin_start = adj2->win_start;
+				adj2->gWin_end = adj2->win_end;
+				adj2->inx = dqs_index; 
+			}
+
+			/* reset window pointer to measure next window */
+			adj2->win_start = adj2->win_end = 0;
+		}
+	} /* failure */
+
+	return;
+}	
+
+/* for basing on adj2 min value logic support */
+static int get_adj2_adjusted_value(unsigned int *adj2_dsx, adj2_val_t *adj2, u16 ddr16bit_mode)
+{
+  u8 i, adj2_val;
+  u16 ds, shift;
+  u8 win_start, win_end, win;
+  u8 gwin_start, gwin_end, gwin;
+#ifdef  DDR_TRAINING_MODE_DEBUG_PRINTS
+  unsigned char s[5];
+#endif
+
+  for(ds=0; ds < 4; ds++) {
+
+    if ((ds == 2) && (ddr16bit_mode))
+      goto done;
+
+    shift = ds * 8;
+
+    win_start = win_end = win = 0;
+    gwin_start = gwin_end = gwin = 0;
+
+#ifdef  DDR_TRAINING_MODE_DEBUG_PRINTS
+    serial_puts("ds");
+    serial_puts(simple_itoa1(ds, s));
+    serial_putc('\n');
+#endif
+
+    for(i=ADJ2_MIN_VAL; i <= ADJ2_MAX_VAL; i++) {
+
+       adj2_val = (u8)((adj2_dsx[i] >> shift) & 0xff);
+
+        /* if, adj2 val is accepted */
+       if (adj2_val >= ADJ1_MIN_ACCEPTED_WINDOW)  {
+          if (win_start == 0)  {
+	    win_start = win_end = i;
+          }
+          else {
+	    win_end++;
+	    /* close the window, if we reach the end of adj2 range */
+	    if (i == ADJ2_MAX_VAL)  {
+              win = win_end - win_start + 1;
+	      if (gwin < win) {
+	        gwin = win;
+	        gwin_start = win_start;
+	        gwin_end = win_end;
+	      }
+
+#ifdef  DDR_TRAINING_MODE_DEBUG_PRINTS
+    	     serial_puts(simple_itoa1(win_start, s));
+             serial_putc('-');
+    	     serial_puts(simple_itoa1(win_end, s));
+             serial_putc('=');
+    	     serial_puts(simple_itoa1(win, s));
+    	     serial_putc('\n');
+#endif
+
+	  }
+        }
+      }
+      else  {
+        /* if (win_start == 0) do nothing */
+        if (win_start != 0)  {
+	  win = win_end - win_start + 1;
+	  if (gwin < win) {
+	    gwin = win;
+	    gwin_start = win_start;
+	    gwin_end = win_end;
+	  }
+
+#ifdef  DDR_TRAINING_MODE_DEBUG_PRINTS
+    	  serial_puts(simple_itoa1(win_start, s));
+          serial_putc('-');
+    	  serial_puts(simple_itoa1(win_end, s));
+          serial_putc('=');
+    	  serial_puts(simple_itoa1(win, s));
+    	  serial_putc('\n');
+#endif
+
+	  win_start = win_end = 0;
+        }
+      }
+    } /* end of for (adj2 for a given ds) */
+
+    /* check for adj2 range size */
+    if (gwin < ADJ2_MIN_ACCEPTED_RANGE)  {
+	return -1;
+    }
+    else if (gwin < ADJ2_ACCEPTED_RANGE) {
+        serial_puts("\nWARNING - DDR Training results may be Marginal\n");
+    }
+
+    switch (ds) {
+      case 0 :
+        adj2->ds0.inx = (gwin_start + gwin_end) >> 1;
+        adj2->ds0.gWin = adj2_dsx[adj2->ds0.inx] & 0xff;
+	break;
+      case 1 : 
+        adj2->ds1.inx = (gwin_start + gwin_end) >> 1;
+        adj2->ds1.gWin = (adj2_dsx[adj2->ds1.inx] & 0xff00) >> 8;
+	break;
+      case 2 :
+        adj2->ds2.inx = (gwin_start + gwin_end) >> 1;
+        adj2->ds2.gWin = (adj2_dsx[adj2->ds2.inx] & 0xff0000) >> 16;
+	break;
+      case 3:
+        adj2->ds3.inx = (gwin_start + gwin_end) >> 1;
+        adj2->ds3.gWin = (adj2_dsx[adj2->ds3.inx] & 0xff000000) >> 24;
+      default:
+	break;
+    }
+  } /* end of for(ds) */
+
+done:
+  if (ddr16bit_mode)  {
+     if ((adj2->ds0.gWin < ADJ1_ACCEPTED_WINDOW) || (adj2->ds1.gWin < ADJ1_ACCEPTED_WINDOW))   {
+       goto warning;
+     }
+  }
+  else {
+     if ((adj2->ds0.gWin < ADJ1_ACCEPTED_WINDOW) || (adj2->ds1.gWin < ADJ1_ACCEPTED_WINDOW) ||
+         (adj2->ds2.gWin < ADJ1_ACCEPTED_WINDOW) || (adj2->ds3.gWin < ADJ1_ACCEPTED_WINDOW))   {
+       goto warning;
+     }
+  }
+  return 0;
+
+warning:
+  serial_puts("\nWARNING - DDR Training results may be Marginal\n");
+  return 0;
+}
+
+
+/* re-calculate the win_start and win_end values for the choosen adj2 */
+void recalculate_adj1_window(u8 ddr16bit_mode, adj2_val_t *adj2,
+			   u64 *dword_list, u32 *word_list)
+{
+  u8 dll_val;
+  u8 ds;
+  u32 result;
+  u32 dqs_index;
+  u32 ddr_addr_offset = 0;
+  u64 dqs_value;
+  
+  /* Reset window pointers */
+  adj2->ds0.win_start = adj2->ds0.win_end = 0;
+  adj2->ds1.win_start = adj2->ds1.win_end = 0;
+  adj2->ds2.win_start = adj2->ds2.win_end = 0;
+  adj2->ds3.win_start = adj2->ds3.win_end = 0;
+
+  adj2->ds0.win = 0;
+  adj2->ds1.win = 0;
+  adj2->ds2.win = 0;
+  adj2->ds3.win = 0;
+
+  adj2->ds0.gWin = 0;
+  adj2->ds1.gWin = 0;
+  adj2->ds2.gWin = 0;
+  adj2->ds3.gWin = 0;
+
+  for(ds = 0; ds < 4; ds++) {
+    
+    if ((ds == 2) && (ddr16bit_mode))
+       return;
+
+    if (ds == 0)
+       dqs_index = adj2->ds0.inx;
+    else if (ds == 1)
+       dqs_index = adj2->ds1.inx;
+    else if (ds == 2)
+       dqs_index = adj2->ds2.inx;
+    else if (ds == 3)
+       dqs_index = adj2->ds3.inx;
+
+    /* Configure the WRLVL_DELAY_X values */
+    if (ddr16bit_mode) {
+      dqs_value = __le64_to_cpu((*(volatile u64*)(DENALI_CTL_35_DATA))) & 0xffffff0000ffffffULL;
+      dqs_value |= (u64)(((u64)dqs_index << 24) | ((u64)dqs_index << 32) );
+    }
+    else {
+      dqs_value = __le64_to_cpu((*(volatile u64*)(DENALI_CTL_35_DATA))) & 0xff00000000ffffffULL;
+      dqs_value |= (u64)(((u64)dqs_index << 24) | ((u64)dqs_index << 32) | ((u64)dqs_index << 40) | ((u64)dqs_index << 48));
+    }
+    arm_write64(dqs_value, (volatile u64 *)DENALI_CTL_35_DATA); //should be 64bit write
+
+    //set sw leveling mode
+    *(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1 | (1LL << 8));
+    //sw leveling load
+    *(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG1 | (1LL << 48));
+    //reset sw leveling mode
+    *(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1);
+
+    /* Looping through ADJ_1 range */
+    for (dll_val = ADJ1_MIN_VAL; dll_val <= ADJ1_MAX_VAL; dll_val++)
+    {
+      /* Configure dll write click adj-1 values */
+      DENALI_DLL_ADJ1_DS0 = (u8)dll_val;
+      DENALI_DLL_ADJ1_DS1 = (u8)dll_val;
+      if (!ddr16bit_mode)  {
+        DENALI_DLL_ADJ1_DS2 = (u8)dll_val;
+        DENALI_DLL_ADJ1_DS3 = (u8)dll_val;
+      }
+
+      result = do_wr_rd_transaction(ddr_addr_offset,dword_list,word_list, ddr16bit_mode);
+      ddr_addr_offset = (ddr_addr_offset + ADDR_JUMP_SIZE) & (PHYS_SDRAM_SIZE -1);
+
+      if (ds == 0)
+        adj2_dsx_calculate_window((result & 0x1), dll_val, adj2->ds0.inx, &adj2->ds0);
+      else if (ds == 1)
+        adj2_dsx_calculate_window((result & 0x2), dll_val, adj2->ds1.inx, &adj2->ds1);
+      else if (ds == 2)	
+          adj2_dsx_calculate_window((result & 0x4), dll_val, adj2->ds2.inx, &adj2->ds2);
+      else if (ds == 3)
+          adj2_dsx_calculate_window((result & 0x8), dll_val, adj2->ds3.inx, &adj2->ds3);
+    } /* for loop from dll min to max (ADJ_1) */ 
+
+  } /* for each ds */
+
+  return;
+}
+
+/* find the a bigger dll clk window for the given dqs value */
+/* find a dll wr clk window for a given dqs_index,
+ * this function updates the global dll and dqs values, if its finds any bigger window
+ * than previous window, and then finally it configures the identified dqs and dll values
+ * to DDR controller  */
+void start_training(void)
+{
+  u32 word_list[16]  = { 0xffffffff, 0x00000000, 0x12345678, 0x9abcdef0,
+			 0xf7f70202, 0xdfdf2020, 0x80407fbf, 0x08040204,
+                         0x8080fdfd, 0x0808dfdf, 0xa5a55a5a, 0x5a5aa5a5,
+			 0xaaaa5555, 0x5555aaaa, 0x0000ffff, 0x0000ffff};
+
+  u64 dword_list[16]  = {0xffffffff00000000ULL, 0xffffffff00000000ULL, 
+                         0x1234567876543210ULL, 0x0123456789abcdefULL,
+			 0xf7f7f7f702020202ULL, 0xdfdfdfdf20202020ULL,
+ 		         0x804020107fbfdfefULL, 0x0804020110204080ULL,
+                         0x80808080fdfdfdfdULL, 0x08080808dfdfdfdfULL,
+			 0xa5a5a5a55a5a5a5aULL, 0x5a5a5a5aa5a5a5a5ULL,
+			 0xaaaaaaaa55555555ULL, 0x55555555aaaaaaaaULL,
+			 0x00000000ffffffffULL, 0x00000000ffffffffULL
+                        };
+
+  u8 dll_val;
+  u8 result;
+  u8 dqs_index;
+  u32 ddr_addr_offset = 0;
+  u64 dqs_value;
+  adj2_val_t adj2;
+  u16 ddr16bit_mode = 0;
+
+  unsigned char sb[] = "\nDDR Training";
+  unsigned char sd[] = "Done";
+  unsigned char sf[] = "Fail";
+
+#ifdef DDR_TRAINING_MODE_DEBUG_PRINTS
+  unsigned char adj2_s[] = "\nAdj2:";
+  char s[5];
+  u8 i; 
+#endif
+
+  unsigned int adj2_dsx[256];
+
+  /* Init of UART will be done later through main init sequence,
+   * so doing init twice does it make any harm????, I think NO */
+  serial_init();
+
+  serial_puts(sb);
+
+  /* check for 16bit mode */
+  if(__le64_to_cpu(*(volatile u64*)(DENALI_CTL_18_DATA)) & 0x0000000001000000ULL)
+    ddr16bit_mode = 1;
+
+  adj2.ds0.gWin = 0;
+  adj2.ds1.gWin = 0;
+  adj2.ds2.gWin = 0;
+  adj2.ds3.gWin = 0;
+
+    /* Looping through ADJ_2 range */
+    for(dqs_index = ADJ2_MIN_VAL; dqs_index <= ADJ2_MAX_VAL; dqs_index++)
+    {
+#ifdef  DDR_TRAINING_MODE_DEBUG_PRINTS
+      serial_puts(adj2_s);
+      serial_puts(simple_itoa1(dqs_index, s));
+      serial_putc(':');
+#endif
+      serial_putc('.');
+
+      /* Configure the WRLVL_DELAY_X values */
+      if (ddr16bit_mode) {
+        dqs_value = __le64_to_cpu((*(volatile u64*)(DENALI_CTL_35_DATA))) & 0xffffff0000ffffffULL;
+        dqs_value |= (u64)(((u64)dqs_index << 24) | ((u64)dqs_index << 32) );
+      }
+      else {
+        dqs_value = __le64_to_cpu((*(volatile u64*)(DENALI_CTL_35_DATA))) & 0xff00000000ffffffULL;
+        dqs_value |= (u64)(((u64)dqs_index << 24) | ((u64)dqs_index << 32) | ((u64)dqs_index << 40) | ((u64)dqs_index << 48));
+      }
+      arm_write64(dqs_value, (volatile u64 *)DENALI_CTL_35_DATA); //should be 64bit write
+
+      //set sw leveling mode
+      *(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1 | (1LL << 8));
+      //sw leveling load
+      *(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG1 | (1LL << 48));
+      //reset sw leveling mode
+      *(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1);
+
+      /* Reset window pointers */
+      adj2.ds0.win_start = adj2.ds0.win_end = 0;
+      adj2.ds1.win_start = adj2.ds1.win_end = 0;
+      adj2.ds2.win_start = adj2.ds2.win_end = 0;
+      adj2.ds3.win_start = adj2.ds3.win_end = 0;
+      adj2.ds0.win = 0;
+      adj2.ds1.win = 0;
+      adj2.ds2.win = 0;
+      adj2.ds3.win = 0;
+
+      /* Looping through ADJ_1 range */
+      for (dll_val = ADJ1_MIN_VAL; dll_val <= ADJ1_MAX_VAL; dll_val++)
+      {
+        /* Configure dll write click adj-1 values */
+        DENALI_DLL_ADJ1_DS0 = (u8)dll_val;
+        DENALI_DLL_ADJ1_DS1 = (u8)dll_val;
+	if (!ddr16bit_mode)  {
+          DENALI_DLL_ADJ1_DS2 = (u8)dll_val;
+          DENALI_DLL_ADJ1_DS3 = (u8)dll_val;
+	}
+
+        result = do_wr_rd_transaction(ddr_addr_offset,dword_list,word_list, ddr16bit_mode);
+        ddr_addr_offset = (ddr_addr_offset + ADDR_JUMP_SIZE) & (PHYS_SDRAM_SIZE -1);
+
+	adj2_dsx_calculate_window((result & 0x1), dll_val, dqs_index, &adj2.ds0);
+	adj2_dsx_calculate_window((result & 0x2), dll_val, dqs_index, &adj2.ds1);
+	if (!ddr16bit_mode)  {
+	  adj2_dsx_calculate_window((result & 0x4), dll_val, dqs_index, &adj2.ds2);
+	  adj2_dsx_calculate_window((result & 0x8), dll_val, dqs_index, &adj2.ds3);
+	}
+      } /* for loop from dll min to max (ADJ_1) */ 
+
+      /* store the adj2 win values */
+      if (ddr16bit_mode)
+        adj2_dsx[dqs_index] = (adj2.ds1.win << 8) | (adj2.ds0.win);
+      else
+        adj2_dsx[dqs_index] = (adj2.ds3.win << 24) | (adj2.ds2.win << 16) | (adj2.ds1.win << 8) | (adj2.ds0.win);
+
+    } //End of ADJ_2
+
+#ifdef DDR_TRAINING_MODE_DEBUG_PRINTS
+  serial_putc('\n');
+  serial_puts(simple_itoa1(adj2.ds0.gWin,s));
+  serial_putc('-');
+  serial_puts(simple_itoa1(adj2.ds0.inx,s));
+  serial_putc('\n');
+  serial_puts(simple_itoa1(adj2.ds1.gWin,s));
+  serial_putc('-');
+  serial_puts(simple_itoa1(adj2.ds1.inx,s));
+  serial_putc('\n');
+  if (!ddr16bit_mode)  {
+    serial_puts(simple_itoa1(adj2.ds2.gWin,s));
+    serial_putc('-');
+    serial_puts(simple_itoa1(adj2.ds2.inx,s));
+    serial_putc('\n');
+    serial_puts(simple_itoa1(adj2.ds3.gWin,s));
+    serial_putc('-');
+    serial_puts(simple_itoa1(adj2.ds3.inx,s));
+    serial_putc('-');
+  }
+
+  serial_putc('\n');
+  /* ds0 */
+  for (i=ADJ2_MIN_VAL; i <= ADJ2_MAX_VAL; i++) {
+  	serial_puts(simple_itoa1((adj2_dsx[i] & 0xff),s));
+  	serial_putc(',');
+  }
+  serial_putc('\n');
+
+  /* ds1 */
+  serial_putc('\n');
+  for (i=ADJ2_MIN_VAL; i <= ADJ2_MAX_VAL; i++) {
+  	serial_puts(simple_itoa1((adj2_dsx[i] & 0xff00) >> 8,s));
+  	serial_putc(',');
+  }
+  serial_putc('\n');
+
+  if (!ddr16bit_mode)  {
+    /* ds2 */
+    serial_putc('\n');
+    for (i=ADJ2_MIN_VAL; i <= ADJ2_MAX_VAL; i++) {
+  	serial_puts(simple_itoa1((adj2_dsx[i] & 0xff0000) >> 16,s));
+  	serial_putc(',');
+    }
+    serial_putc('\n');
+
+    /* ds3 */
+    serial_putc('\n');
+    for (i=ADJ2_MIN_VAL; i <= ADJ2_MAX_VAL; i++) {
+  	serial_puts(simple_itoa1((adj2_dsx[i] & 0xff000000) >> 24,s));
+  	serial_putc(',');
+    }
+    serial_putc('\n');
+  }
+#endif
+
+  if (get_adj2_adjusted_value(adj2_dsx, &adj2, ddr16bit_mode) < 0)
+     goto error;
+
+#ifdef DDR_TRAINING_MODE_DEBUG_PRINTS
+  serial_puts(simple_itoa1(adj2.ds0.gWin,s));
+  serial_putc('-');
+  serial_puts(simple_itoa1(adj2.ds0.inx,s));
+  serial_putc('\n');
+  serial_puts(simple_itoa1(adj2.ds1.gWin,s));
+  serial_putc('-');
+  serial_puts(simple_itoa1(adj2.ds1.inx,s));
+  serial_putc('\n');
+  if (!ddr16bit_mode) {
+    serial_puts(simple_itoa1(adj2.ds2.gWin,s));
+    serial_putc('-');
+    serial_puts(simple_itoa1(adj2.ds2.inx,s));
+    serial_putc('\n');
+    serial_puts(simple_itoa1(adj2.ds3.gWin,s));
+    serial_putc('-');
+    serial_puts(simple_itoa1(adj2.ds3.inx,s));
+    serial_putc('-');
+  }
+#endif
+
+  recalculate_adj1_window(ddr16bit_mode, &adj2, dword_list, word_list);
+
+  /* Configure the WRLVL_DELAY_X values (ADJ_2) */
+  if (ddr16bit_mode) {
+    dqs_value = __le64_to_cpu((*(volatile u64*)(DENALI_CTL_35_DATA))) & 0xffffff0000ffffffULL;
+    dqs_value |= (u64)(((u64)(adj2.ds0.inx) << 24) | 
+		     ((u64)(adj2.ds1.inx) << 32));
+  }
+  else {
+    dqs_value = __le64_to_cpu((*(volatile u64*)(DENALI_CTL_35_DATA))) & 0xff00000000ffffffULL;
+    dqs_value |= (u64)(((u64)(adj2.ds0.inx) << 24) | 
+		     ((u64)(adj2.ds1.inx) << 32) | 
+		     ((u64)(adj2.ds2.inx) << 40) | 
+		     ((u64)(adj2.ds3.inx) << 48));
+  }
+  arm_write64(dqs_value, (volatile u64 *)DENALI_CTL_35_DATA); //should be 64bit write
+
+  //set sw leveling mode
+  *(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1 | (1LL << 8));
+  //sw leveling load
+  *(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG1 | (1LL << 48));
+  //reset sw leveling mode
+  *(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1);
+
+  /* Configure wr_clk ADJ_1 */
+  DENALI_DLL_ADJ1_DS0 = (u8)((adj2.ds0.gWin_start + adj2.ds0.gWin_end) >> 1);
+  DENALI_DLL_ADJ1_DS1 = (u8)((adj2.ds1.gWin_start + adj2.ds1.gWin_end) >> 1);
+  if (!ddr16bit_mode)  {
+    DENALI_DLL_ADJ1_DS2 = (u8)((adj2.ds2.gWin_start + adj2.ds2.gWin_end) >> 1);
+    DENALI_DLL_ADJ1_DS3 = (u8)((adj2.ds3.gWin_start + adj2.ds3.gWin_end) >> 1);
+  }
+
+  /* training verification using MDMA transfers */
+  if (mdma_test(dword_list))
+  {
+    goto error;
+  }
+
+  serial_puts(sd);
+  return;
+
+error:
+  serial_puts(sf);
+  //watch dog reset
+  //*(volatile unsigned int *)TIMER_WDT_HIGH_BOUND = 1;
+  //*(volatile unsigned int *)TIMER_WDT_CONTROL = 1;
+  while(1);
+
+  return;
+}
+
+static u8 do_wr_rd_transaction(u32 ddr_address_offset, u64 *dword_list, u32 *word, u16 ddr16bit_mode)
+{
+  u8 j;
+  register int reg_0 __asm__ ("r3");
+  register int reg_1 __asm__ ("r4");
+  u64 *src, *dst;
+  u32 read_val;
+  u8 ret_val = 0;
+
+  ddr_address_offset &= ~0x3;
+
+    /* Do 64bit wr+rd */
+    dst = (u64 *)(DDR_BASEADDR+ddr_address_offset);
+    src = dword_list;
+    for(j=0; j < 16; j++)
+    {
+      __asm__ __volatile__ ("ldmia %0, {%1,%2}" \
+          : "+r" (src), "=r" (reg_0), "=r" (reg_1) \
+	  );
+
+      __asm__ __volatile__ ("stmia %0, {%1,%2}" \
+          : "+r" (dst), "=r" (reg_0), "=r" (reg_1) \
+	  );
+
+      if ((*src & 0x000000ff000000ffLL) != (*dst & 0x000000ff000000ffLL))
+      {
+        ret_val |= 1;
+      }
+      if ((*src & 0x0000ff000000ff00LL) != (*dst & 0x0000ff000000ff00LL))
+      {
+        ret_val |= 1 << 1;
+      }
+
+      if (!ddr16bit_mode)  {
+        if ((*src & 0x00ff000000ff0000LL) != (*dst & 0x00ff000000ff0000LL))
+        {
+          ret_val |= 1 << 2;
+        }
+        if ((*src & 0xff000000ff000000LL) != (*dst & 0xff000000ff000000LL))
+        {
+          ret_val |= 1 << 3;
+        }
+      }
+      *dst = __cpu_to_le64(0); //clear location
+
+      dst++; 
+      src++;
+    }
+
+    /* Do 32bit wr+rd */
+    for (j=0; j < 16; j++)
+    {
+      *(((volatile u32 *)(DDR_BASEADDR+ddr_address_offset)) + j) = __cpu_to_le32(*word);
+
+      read_val = __le32_to_cpu(*(((volatile u32 *)(DDR_BASEADDR+ddr_address_offset)) + j));
+      if ((read_val & 0x000000FF) != (*word & 0x000000ff))
+      {
+	      ret_val |= 1;
+      }
+      if ((read_val & 0x0000ff00) != (*word & 0x0000ff00))
+      {
+	      ret_val |= 1 << 1;
+      }
+      if (!ddr16bit_mode)  {
+        if ((read_val & 0x00ff0000) != (*word & 0x00ff0000))
+        {
+	      ret_val |= 1 << 2;
+        }
+        if ((read_val & 0xff000000) != (*word & 0xff000000))
+        {
+	      ret_val |= 1 << 3;
+        }
+      }
+
+      *(((volatile u32 *)(DDR_BASEADDR+ddr_address_offset)) + j) = __cpu_to_le32(0); //clear location
+      word++;
+      ddr_address_offset = (ddr_address_offset + ADDR_JUMP_SIZE) & (PHYS_SDRAM_SIZE -1);
+    }
+
+    return ret_val;
+}
+
+/*
+ * On success returns 0 
+ */ 
+static int mdma_test(u64 *dword_list)
+{
+  int ii,j;
+  unsigned int *mdma_data = (u32 *)0x81000000;
+  unsigned int *ddr_dst;
+  unsigned int data_len[] = {1024, 1032, 1048, 1064};
+
+  /* init mdma data, at this point we are sure that 32bit wr/rd operations are good */
+  u32 *dataPtr = (u32 *)dword_list;
+  for(j=0; j < 9; j++)
+  {
+    for(ii=0; ii < 32; ii++)
+      mdma_data[32*j + ii] = __cpu_to_le32(dataPtr[ii]);
+  }
+
+  for(j=0; j < 4; j++)
+  {
+      ddr_dst = (unsigned int *)((j % 2) ? MT_ADDR1_DST : MT_ADDR2_DST);
+      dataPtr = mdma_data;
+
+      mdma_memcpy((void *)mdma_data, (void *)ddr_dst, data_len[j], NULL);
+
+      for(ii=0; ii < data_len[j] >> 2; ii++)
+        if (__le32_to_cpu(*dataPtr++) != __le32_to_cpu(*ddr_dst++))
+	  return 1;
+  }
+
+  return 0; //MDMA test pass
+}

cpu/arm1136/comcerto/training100_new.c

diff --git a/cpu/arm1136/comcerto/training100_new.c b/cpu/arm1136/comcerto/training100_new.c
new file mode 100644
index 0000000..1a02782
--- /dev/null
+++ b/cpu/arm1136/comcerto/training100_new.c
@@ -0,0 +1,423 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+#define SZ_1K	0x400
+#define SZ_128K  (SZ_1K * 128)
+#define ADDR_JUMP_SIZE  SZ_128K
+#define MIN_VALID_WINDOW_SIZE 5
+
+#define NO_OF_PATTERNS   16 
+
+#define WQS_START  0x30 
+#define WQS_END    0x60
+#define DOS_START  0x55
+#define DOS_END    0x75
+#define DDD_START  0x9
+#define DDD_END    0x30
+
+static int do_wr_rd_verify(u64 *);
+
+u32 do_wr_rd_transaction(u32, u32*, u64*);
+u32 do_wr_rd_transaction64(u32 ddr_address_offset, u64*);
+
+extern int serial_init(void);
+extern void serial_puts(const char *s);
+extern void serial_putc(const char c);
+
+#if 0
+/* belongs in utility.c */
+static char *simple_itoa(unsigned int i)
+{
+    /* 21 digits plus null terminator, good for 64-bit or smaller ints */
+    static char local[22];
+    char *p = &local[21];
+    *p-- = '\0';
+    do {
+        *p-- = '0' + i % 10;
+        i /= 10;
+    } while (i > 0);
+    return p + 1;
+}
+#endif
+
+
+extern int mdma_memcpy(void *src, void *dst, int len, unsigned int *crc);
+/*
+ * On success returns 0 
+ */ 
+static int mdma_test(u64 *dword_list)
+{
+  int ii,j;
+  unsigned int *mdma_data = (u32 *)0x81000000;
+  unsigned int ddr_tmp = 0x80002000;
+  unsigned int ddr_dst;
+  unsigned int crc1, crc2;
+  unsigned short data_len[] = {1024, 1032, 1048, 1064};
+
+  /* init mdma data, at this point we are sure that 32bit wr/rd operations are good */
+  u32 *dataPtr = (u32 *)dword_list;
+  for(j=0; j < 9; j++)
+  {
+    for(ii=0; ii < 32; ii++)
+      mdma_data[32*j + ii] = __cpu_to_le32(dataPtr[ii]);
+  }
+
+  for(ii=0; ii < 4; ii++)
+  {
+      ddr_dst = (ii % 2) ? 0x8000ff00 : 0x8300ff00;
+
+      //CRC for write
+      mdma_memcpy((void *)mdma_data, (void *)ddr_dst, data_len[ii], &crc1);
+
+      //CRC for read
+      mdma_memcpy((void *)ddr_dst, (void *)ddr_tmp, data_len[ii], &crc2);
+
+      if(crc1 != crc2)
+       return 1;
+  }
+
+  return 0; //MDMA test pass
+}
+
+
+/************************************************************************
+ * Function: start_training
+ * Description:
+ *   Do the DDR training and configures the best values.
+ * No return value
+ ************************************************************************/
+void start_training(void)
+{
+
+  u32 word_list[NO_OF_PATTERNS]  = { 0xffffffff, 0x00000000, 0x12345678, 0x9abcdef0,
+			 0xf7f70202, 0xdfdf2020, 0x80407fbf, 0x08040204,
+                         0x8080fdfd, 0x0808dfdf, 0xa5a55a5a, 0x5a5aa5a5,
+			 0xaaaa5555, 0x5555aaaa, 0x0000ffff, 0x0000ffff};
+
+
+  u64 dword_list[NO_OF_PATTERNS]  = {0xffffffff00000000ULL, 0xffffffff00000000ULL, 
+                         0x1234567876543210ULL, 0x0123456789abcdefULL,
+			 0xf7f7f7f702020202ULL, 0xdfdfdfdf20202020ULL,
+ 		         0x804020107fbfdfefULL, 0x0804020110204080ULL,
+                         0x80808080fdfdfdfdULL, 0x08080808dfdfdfdfULL,
+			 0xa5a5a5a55a5a5a5aULL, 0x5a5a5a5aa5a5a5a5ULL,
+			 0xaaaaaaaa55555555ULL, 0x55555555aaaaaaaaULL,
+			 0x00000000ffffffffULL, 0x00000000ffffffffULL
+                        };
+
+  unsigned char gbl_wqs_Vstart, gbl_wqs_Vend, cfg_wqs_Vstart, cfg_wqs_Vend, wqs_inx, wqs_Vstart;
+  unsigned char gbl_dos,cfg_dos, dos_inx;
+  unsigned char gbl_ddd_Vstart,gbl_ddd_Vend, ddd_Vstart, ddd_inx,ddd_median;
+  int result;
+  u32 ddr_addr_offset = 0xff00;
+  unsigned char sb[] = "DDR Training";
+  unsigned char sf[] = "Fail";
+  unsigned char sd[] = "Done";
+  unsigned char ch = '.';
+
+  /* Init of UART will be done later through main init sequence,
+   * so doing init twice does it make any harm????, I think NO */
+  serial_init();
+
+  serial_puts(sb);
+
+  gbl_ddd_Vstart = gbl_ddd_Vend = ddd_Vstart = 0;
+  cfg_wqs_Vstart = cfg_wqs_Vend = 0;
+  gbl_dos = cfg_dos = 0;
+
+  for(ddd_inx = DDD_START; ddd_inx <= DDD_END; ddd_inx++)  
+  {
+    serial_putc(ch);
+
+    gbl_wqs_Vend = gbl_wqs_Vstart = 0;
+
+    /* Configure DDD value */
+    DENALI_DQS_DELAY0 = ddd_inx;
+    DENALI_DQS_DELAY1 = ddd_inx;
+    DENALI_DQS_DELAY2 = ddd_inx;
+    DENALI_DQS_DELAY3 = ddd_inx;
+
+    for (dos_inx = DOS_START; dos_inx <= DOS_END; dos_inx++)  
+    {
+      /* configure DOS value */
+      DENALI_DQS_OUT  = dos_inx;
+
+      wqs_Vstart = 0;
+      for (wqs_inx = WQS_START; wqs_inx <= WQS_END; wqs_inx++) 
+      {
+        /* Configure WQS value */
+	DENALI_WR_DQS   = wqs_inx;
+
+	result =  do_wr_rd_transaction(ddr_addr_offset,word_list, dword_list);
+
+        ddr_addr_offset = (ddr_addr_offset + ADDR_JUMP_SIZE) & (PHYS_SDRAM_SIZE - 1);
+
+	if (result) 
+        {  //result == FAIL 
+	  /* check is this a window closing */
+	  if (wqs_Vstart == 0)  
+          { //No valid window started 
+	    //Do nothing
+	  }
+	  else  
+          {  //end of a valid window 
+             if ((wqs_inx - wqs_Vstart) > (gbl_wqs_Vend - gbl_wqs_Vstart))  
+             {
+	       gbl_wqs_Vstart = wqs_Vstart;
+	       gbl_wqs_Vend   = wqs_inx;
+	       gbl_dos = dos_inx;
+	     }
+	     //else  Do nothing
+             //{
+             //}
+	     wqs_Vstart = 0;
+          }
+	}
+        else  
+        { //results == SUCCESS
+          if (wqs_Vstart == 0) 
+          { //check is this a begining of valid window
+	    wqs_Vstart = wqs_inx;
+	  }
+	  //else 
+          //{ 
+	    //Do nothing
+	  //}
+	}
+      } //wqs_loop end
+
+    } //dos_loop end
+
+    if ((gbl_wqs_Vend - gbl_wqs_Vstart) > MIN_VALID_WINDOW_SIZE)  
+    { //accepted window range 
+      if (ddd_Vstart == 0) 
+      {  //valid ddd window not yet started
+	ddd_Vstart = ddd_inx;
+      }
+      //else 
+      //{
+        //do nothing
+      //}
+    }
+    else 
+    {
+      if (ddd_Vstart == 0) 
+      { //no accepted window range & no accepted window started till now
+	//Do nothing
+      }
+      else 
+      {
+        if ((gbl_ddd_Vend - gbl_ddd_Vstart) < (ddd_inx - ddd_Vstart)) 
+        {
+	  gbl_ddd_Vend = ddd_inx;
+	  gbl_ddd_Vstart = ddd_Vstart;
+	}
+	//else 
+        //{
+	  //Do nothing
+	//}
+	ddd_Vstart = 0;
+      }
+    }
+
+    if ( (gbl_wqs_Vend - gbl_wqs_Vstart) > (cfg_wqs_Vend - cfg_wqs_Vstart)) 
+    {
+      cfg_wqs_Vend = gbl_wqs_Vend;
+      cfg_wqs_Vstart = gbl_wqs_Vstart;
+      cfg_dos      = gbl_dos;
+    }
+  } //ddd_loop end
+
+
+  if ((cfg_wqs_Vend - cfg_wqs_Vstart) < MIN_VALID_WINDOW_SIZE)
+  {
+    serial_puts(sf);
+    while(1);
+  }
+
+  ddd_median = (gbl_ddd_Vend + gbl_ddd_Vstart) >> 1;
+  DENALI_DQS_DELAY0 = ddd_median;
+  DENALI_DQS_DELAY1 = ddd_median;
+  DENALI_DQS_DELAY2 = ddd_median;
+  DENALI_DQS_DELAY3 = ddd_median;
+
+  DENALI_DQS_OUT  = cfg_dos;
+  DENALI_WR_DQS   = (cfg_wqs_Vend + cfg_wqs_Vstart) >> 1;
+
+  /* Do verify the training values */
+  /* 8Bit,16bit,32bit,64bit wr/rd */
+  result = do_wr_rd_verify(dword_list);
+
+  /* MDMA wr/rd */ 
+  if (!result)
+    result = mdma_test(dword_list);
+
+  if (result)
+  {
+    serial_puts(sf);
+    while(1);
+  }
+
+  serial_puts(sd);
+  return;
+}
+
+u32 do_wr_rd_transaction(u32 ddr_addr_offset, u32 *word, u64 *dword_list)
+{
+    u32 i;
+
+    /* Do 64bit wr+rd */
+    if (do_wr_rd_transaction64(ddr_addr_offset,dword_list))
+	    return 1; //failure
+
+    /* Do 32bit wr+rd */
+    for (i=0; i < NO_OF_PATTERNS; i++)
+    {
+      *((volatile u32 *)(DDR_BASEADDR + ddr_addr_offset) + i) = __cpu_to_le32(*word);
+
+      if (__le32_to_cpu(*((volatile u32 *)(DDR_BASEADDR + ddr_addr_offset) + i)) != *word)
+      {
+        //reassign to zero 
+        *((volatile u32 *)(DDR_BASEADDR + ddr_addr_offset) + i) = __cpu_to_le32(0);
+
+	return 1; //failure
+      }
+      word++;
+
+      //reassign to zero 
+      *((volatile u32 *)(DDR_BASEADDR + ddr_addr_offset) + i) = __cpu_to_le32(0);
+    }
+
+    return 0; //success
+}
+
+u32 do_wr_rd_transaction64(u32 ddr_address_offset, u64 *dword_list)
+{
+  u8 j;
+  register int reg_0 __asm__ ("r3");
+  register int reg_1 __asm__ ("r4");
+  u64 *src,*dst,*dval;
+  u64 dword_store[NO_OF_PATTERNS];
+
+  /* 64bit burst write */
+  dst = ((volatile u64 *) (DDR_BASEADDR + ddr_address_offset));
+  src = dword_list;
+  for(j=0; j < NO_OF_PATTERNS; j++)
+  {
+    __asm__ __volatile__ ("ldmia %0, {%1,%2}" \
+          : "+r" (src), "=r" (reg_0), "=r" (reg_1) \
+	  );
+
+    __asm__ __volatile__ ("stmia %0, {%1,%2}" \
+          : "+r" (dst), "=r" (reg_0), "=r" (reg_1) \
+	  );
+
+    if (*src != (*dst))
+      return 0x1;
+
+    src++;
+    dst++;
+  }
+
+  /* 64bit burst read 16 times */
+  src = ((u64 *)(DDR_BASEADDR + ddr_address_offset));
+  dst = dword_store;
+  dval = dword_list;
+  for(j=0; j < NO_OF_PATTERNS; j++)
+  {
+    __asm__ __volatile__ ("ldmia %0, {%1,%2}" \
+          : "+r" (src), "=r" (reg_0), "=r" (reg_1) \
+	  );
+
+    __asm__ __volatile__ ("stmia %0, {%1,%2}" \
+          : "+r" (dst), "=r" (reg_0), "=r" (reg_1) \
+	  );
+
+    if (*dval != *dst)
+    {
+      //reassign to zero
+      *src = __cpu_to_le64(0x0ULL);
+
+      return 0x1;
+    }
+
+    //reassign to zero
+    *src = __cpu_to_le64(0x0ULL);
+
+    src++;
+    dst++;
+    dval++;
+  }
+
+  return 0;
+}
+
+static int do_wr_rd_verify(u64 *dword_list)
+{
+  u8 i;
+  u32 ddr_addr_offset = 0xffff00;
+  u8 *list8 = (u8 *)dword_list;
+  u16 *list16 = (u16 *)dword_list;
+  u32 *list32 = (u32 *)dword_list;
+  u64 *src_aram, *dst_ddr;
+  register int reg_0 __asm__ ("r3");
+  register int reg_1 __asm__ ("r4");
+
+  src_aram = dword_list;
+  dst_ddr = ((u64 *)(DDR_BASEADDR + ddr_addr_offset));
+  for (i=0; i < NO_OF_PATTERNS; i++)
+  {
+    //8bit
+    *((volatile u8 *)(DDR_BASEADDR + ddr_addr_offset) + i) = *(list8+i);
+    if (*((volatile u8 *)(DDR_BASEADDR + ddr_addr_offset) + i) != *(list8+i))
+      return 0x1;
+
+    //16bit
+    *((volatile u16 *)(DDR_BASEADDR + ddr_addr_offset) + i) = __cpu_to_le16(*(list16+i));
+    if (__le16_to_cpu(*((volatile u16 *)(DDR_BASEADDR + ddr_addr_offset) + i)) != *(list16+i))
+      return 0x1;
+
+    //32bit
+    *((volatile u32 *)(DDR_BASEADDR + ddr_addr_offset) + i) = __cpu_to_le32(*(list32+i));
+    if (__le32_to_cpu(*((volatile u32 *)(DDR_BASEADDR + ddr_addr_offset) + i)) != *(list32+i))
+      return 0x1;
+
+    //64bit
+    __asm__ __volatile__ ("ldmia %0, {%1,%2}" \
+          : "+r" (src_aram), "=r" (reg_0), "=r" (reg_1) \
+	  );
+
+    __asm__ __volatile__ ("stmia %0, {%1,%2}" \
+          : "+r" (dst_ddr), "=r" (reg_0), "=r" (reg_1) \
+	  );
+
+    if (*src_aram != (*dst_ddr))
+      return 0x1;
+
+    dst_ddr++;
+    src_aram++;
+
+    ddr_addr_offset = (ddr_addr_offset + ADDR_JUMP_SIZE) & (PHYS_SDRAM_SIZE - 1);
+  }
+  return 0;
+}
+

cpu/arm1136/config.mk

diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk
index e39e774..ebdf70b 100644
--- a/cpu/arm1136/config.mk
+++ b/cpu/arm1136/config.mk
@@ -20,11 +20,26 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+
+include $(TOPDIR)/include/config.mk
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 
+
+ifdef BE8_MODE
+PLATFORM_RELFLAGS += -mbig-endian -O4 -DBE8_MODE
+else
+PLATFORM_RELFLAGS += -msoft-float
+endif
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5
+#PLATFORM_CPPFLAGS += -march=armv5
+PLATFORM_CPPFLAGS += -march=armv6j 
+
+ifdef BE8_MODE
+PLATFORM_CPPFLAGS += -mbig-endian
+PLATFORM_LDFLAGS += --be8 -EB
+endif
+
 # =========================================================================
 #
 # Supply options according to compiler version

cpu/arm1136/cpu.c

diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
index fa78eaa..438c64c 100644
--- a/cpu/arm1136/cpu.c
+++ b/cpu/arm1136/cpu.c
@@ -33,7 +33,7 @@
 
 #include <common.h>
 #include <command.h>
-#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) && !defined(CONFIG_COMCERTO_900) && !defined(CONFIG_COMCERTO_100) && !defined(CONFIG_COMCERTO_1000)
 #include <asm/arch/omap2420.h>
 #endif
 
@@ -163,3 +163,26 @@
 {
 	return(read_p15_c1 () & C1_IC) != 0;
 }
+
+void dcache_enable (void)
+{
+	ulong reg;
+
+	reg = read_p15_c1 ();	/* get control reg. */
+	cp_delay ();
+	write_p15_c1 (reg | C1_DC);
+}
+
+void dcache_disable (void)
+{
+	ulong reg;
+
+	reg = read_p15_c1 ();
+	cp_delay ();
+	write_p15_c1 (reg & ~C1_DC);
+}
+
+int dcache_status (void)
+{
+	return(read_p15_c1 () & C1_DC) != 0;
+}

cpu/arm1136/interrupts.c

diff --git a/cpu/arm1136/interrupts.c b/cpu/arm1136/interrupts.c
index 1dc36d0..a9bdda7 100644
--- a/cpu/arm1136/interrupts.c
+++ b/cpu/arm1136/interrupts.c
@@ -33,16 +33,17 @@
 #include <common.h>
 #include <asm/arch/bits.h>
 
-#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) && ! defined (CONFIG_COMCERTO_900) && ! defined (CONFIG_COMCERTO_100) && ! defined (CONFIG_COMCERTO_1000)
 # include <asm/arch/omap2420.h>
 #endif
 
 #include <asm/proc-armv/ptrace.h>
-
+#if  !defined(CONFIG_COMCERTO_900) && ! defined (CONFIG_COMCERTO_100) && ! defined (CONFIG_COMCERTO_1000)
 #define TIMER_LOAD_VAL 0
 
 /* macro to read the 32 bit timer */
 #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR))
+#endif
 
 #ifdef CONFIG_USE_IRQ
 /* enable IRQ interrupts */
@@ -176,7 +177,7 @@
 	bad_mode ();
 }
 
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
+#if (defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)) || defined(CONFIG_COMCERTO_900)  || defined(CONFIG_COMCERTO_100) || defined(CONFIG_COMCERTO_1000)
 /* Use the IntegratorCP function from board/integratorcp.c */
 #else
 

cpu/arm1136/start.S

diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S
index 17c7a83..b869af6 100644
--- a/cpu/arm1136/start.S
+++ b/cpu/arm1136/start.S
@@ -30,9 +30,21 @@
 
 #include <config.h>
 #include <version.h>
-#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) && ! defined (CONFIG_COMCERTO_900) && !defined (CONFIG_COMCERTO_100) && !defined (CONFIG_COMCERTO_1000)
 #include <asm/arch/omap2420.h>
+#elif  defined (CONFIG_COMCERTO_900)  || defined (CONFIG_COMCERTO_100) || defined (CONFIG_COMCERTO_100) || defined (CONFIG_COMCERTO_1000)
+#include <asm/hardware.h>
 #endif
+
+	/* Reverse endian*/
+	.macro REV_ENDIAN dst, src
+#if defined(BE8_MODE)
+	rev  \dst, \src
+#else
+	nop
+#endif
+	.endm
+
 .globl _start
 _start: b	reset
 	ldr	pc, _undefined_instruction
@@ -103,6 +115,60 @@
  */
 
 reset:
+#if defined(CONFIG_COMCERTO_100)
+#if defined(BE8_MODE)
+	setend	be
+#endif
+/*
+	remove lock
+*/
+	ldr	r2, =GPIO_LOCK_REG
+	ldr	r3, =GPIO_IOCTRL_VAL
+	str	r3, [r2]
+	ldr	r2, =GPIO_IOCTRL_REG
+	ldr	r3, [r2]
+#if defined(BE8_MODE)
+	REV_ENDIAN	r3, r3
+#endif
+/*
+	enable address line A15-A21
+*/
+	orr	r3, r3, #0xF
+#if defined(BE8_MODE)
+	REV_ENDIAN	r3, r3
+#endif
+#endif
+
+#if defined(CONFIG_COMCERTO_1000)
+#if defined(BE8_MODE)
+	setend	be
+#endif
+/*
+	enable address line A13-A21
+*/
+	ldr	r2, =GPIO_PIN_SELECT_REG
+	ldr	r3, [r2]
+#if defined(BE8_MODE)
+	REV_ENDIAN	r3, r3
+#endif
+        bic	r3, r3, #0x40           @ clear bits 6
+        bic	r3, r3, #0x4F00         @ clear bits 14,11:8
+        bic	r3, r3, #0xE0000000     @ clear bits 31:29
+#if defined(BE8_MODE)
+	REV_ENDIAN	r3, r3
+#endif
+#endif
+	str	r3, [r2]
+
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+#ifndef CONFIG_UBOOT_LOADED_IN_ARAM
+	/* We were running from offset 0x0, now jump to Boot FLASH address,
+           so that we can configure SDRAM */
+       ldr pc, = EXP_CS0_BASEADDR  + rom_second_loc - TEXT_BASE
+#endif
+#endif
+rom_second_loc:
+
 	/*
 	 * set the cpu to SVC32 mode
 	 */
@@ -196,6 +262,12 @@
 	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
 	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
 
+#if defined(BE8_MODE)
+	mrc	p15, 0, r0, c1, c0, 0   /* read control reg */
+	orr	r0, r0, #(1 << 25)      /* enable be-8 mode */
+	mcr	p15, 0, r0, c1, c0, 0   /* write control reg */
+#endif //BE8_MODE
+
 	/*
 	 * disable MMU stuff and caches
 	 */
@@ -204,6 +276,7 @@
 	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
 	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+	orr	r0, r0, #0x00400000	@ set bit 22 (U) 
 	mcr	p15, 0, r0, c1, c0, 0
 
 	/*
@@ -398,7 +471,7 @@
 		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
 		mov	pc, lr			@ back to caller
 
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
+#if (defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)) || defined (CONFIG_COMCERTO_900) || defined (CONFIG_COMCERTO_100) || defined (CONFIG_COMCERTO_1000)
 /* Use the IntegratorCP function from board/integratorcp/platform.S */
 #else
 

cpu/arm920t/comcerto/Makefile

diff --git a/cpu/arm920t/comcerto/Makefile b/cpu/arm920t/comcerto/Makefile
new file mode 100644
index 0000000..60d0137
--- /dev/null
+++ b/cpu/arm920t/comcerto/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(SOC).a
+
+OBJS	= emac.o interrupts.o serial.o bsp.o spi.o
+SOBJS	= lowlevel_init.o
+
+all: .depend $(LIB)
+
+$(LIB): $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+bsp.o: bsp.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+interrupts.c: interrupts530.c interrupts800.c
+
+serial.c: serial-16550.c serial530.c
+
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+	$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

cpu/arm920t/comcerto/bsp.c

diff --git a/cpu/arm920t/comcerto/bsp.c b/cpu/arm920t/comcerto/bsp.c
new file mode 100644
index 0000000..8a5b36e
--- /dev/null
+++ b/cpu/arm920t/comcerto/bsp.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_COMCERTO_530)
+#include "bsp_530.c"
+#endif
+
+#if defined(CONFIG_COMCERTO_515) || defined(CONFIG_COMCERTO_800)
+#include "bsp_515.c"
+#endif

cpu/arm920t/comcerto/bsp_515.c

diff --git a/cpu/arm920t/comcerto/bsp_515.c b/cpu/arm920t/comcerto/bsp_515.c
new file mode 100644
index 0000000..6e1085e
--- /dev/null
+++ b/cpu/arm920t/comcerto/bsp_515.c
@@ -0,0 +1,558 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bsp.h>
+
+/*
+* SoC_cs_cfg - configure Chip Select settings
+*
+* cs - chip select id
+*
+* enable - enable or disable the CS
+*	1 = enable
+*	0 = disable
+*
+* cfg - chip select configuration, ignored if enable = 0
+*
+*/
+int SoC_cs_cfg(int cs, int enable, struct cs_cfg *cfg)
+{
+	u32 segment_size = 0;
+	u32 baseaddr = 0; 
+	u32 ext_baseaddr = 0;
+
+	if ((cs != EXP_CSSD0) && (cs != EXP_CSSD1) && (cs != EXP_CSBOOT) &&
+	    (cs != EXP_CSP0) && (cs != EXP_CSP1) && (cs != EXP_CSP2) &&
+	    (cs != SDR_CSSD0) && (cs != SDR_CSSD1))
+		goto err;
+
+	if (enable == CS_DISABLE) {
+		/* Disable the CS and exit */
+		*(volatile u32 *) ASD_CSE &= ~(1 << cs);
+		goto out;
+	}
+
+	if (cfg->memtype == CS_MEMTYPE_SDRAM) {
+		/* Other CS don't support SDRAM */
+		if ((cs != EXP_CSSD0) && (cs != SDR_CSSD0))
+			goto err;
+	}
+
+	if ((cs == EXP_CSSD0) || (cs == EXP_CSSD1) || (cs == SDR_CSSD0) || (cs == SDR_CSSD1)) {
+		baseaddr = cfg->baseaddr & 0x07FFFFFF;
+		ext_baseaddr = cfg->baseaddr & 0xF8000000;
+
+		if (ext_baseaddr) {
+			/* Extended Memory */
+
+			if ((ext_baseaddr & 0xc0000000) != 0x80000000)
+				goto out;
+
+			switch (cfg->size) {
+			case 0x100000: segment_size = 0x8; /* 1MB */
+				break;	
+
+			case 0x200000: segment_size = 0x9; /* 2MB */
+				break;	
+
+			case 0x400000: segment_size = 0xa; /* 4MB */
+				break;	
+
+			case 0x800000: segment_size = 0xb;/* 8MB */
+				break;	
+
+			case 0x1000000: segment_size = 0xc;/* 16MB */
+				break;	
+
+			case 0x2000000: segment_size = 0xd; /* 32MB */
+				break;	
+
+			default:
+				cfg->size = 0x4000000;
+			case 0x4000000:
+				segment_size = 0xe; /* 64MB */
+				
+				break;	
+
+			case 0x8000000: segment_size = 0xf; /* 128MB */
+				break;	
+
+			case 0x10000000: segment_size = 0x0; /* 256MB */
+				break;	
+
+			case 0x20000000: segment_size = 0x1; /* 512MB */
+				break;	
+
+			case 0x40000000: segment_size = 0x2; /* 1Gb */
+				break;	
+			}
+
+			/* Make sure the base address is aligned on size boundary */
+			baseaddr &= ~(cfg->size - 1);
+
+		} else {
+			/* Low Memory */
+
+			switch (cfg->size) {
+			case 0x10000: segment_size = 0x0; /* 64KB */
+				break;	
+
+			case 0x20000: segment_size = 0x5; /* 128KB */
+				break;	
+
+			case 0x40000: segment_size = 0x6; /* 256KB */
+				break;	
+
+			case 0x80000: segment_size = 0x7; /* 512KB */
+				break;	
+
+			case 0x100000: segment_size = 0x8; /* 1MB */
+				break;	
+
+			case 0x200000: segment_size = 0x9; /* 2MB */
+				break;	
+
+			case 0x400000: segment_size = 0xa; /* 4MB */
+				break;	
+
+			case 0x800000: segment_size = 0xb; /* 8MB */
+				break;	
+
+			case 0x1000000: segment_size = 0xc; /* 16MB */
+				break;	
+
+			case 0x2000000: segment_size = 0xd; /* 32MB */
+				break;	
+
+			default:
+			case 0x4000000:
+				segment_size = 0xe; /* 64MB */
+				cfg->size = 0x40000000;
+				break;	
+
+			case 0x8000000: segment_size = 0xf; /* 128MB */
+				break;
+			}
+
+			/* Make sure the base address is aligned on size boundary */
+			baseaddr &= ~(cfg->size - 1);
+		}
+	}
+	
+	switch (cs) {
+	case EXP_CSSD0:
+
+		*(volatile u32 *) ASD_MBA_EXP_CSSD0 = ((baseaddr >> 16) << 4) | segment_size;
+		*(volatile u32 *) ASD_EXA_EXP_CSSD0 = (ext_baseaddr >> 27);
+
+		if (cfg->memtype == CS_MEMTYPE_SDRAM) {
+			*(volatile u32 *) SDC0_CSSD0_CFG = (((u32)cfg->memtype & 0x1) << 9);
+
+			*(volatile u32 *) SDC0_SDRAM_CFG1 = (((u32)cfg->tras & 0x7) << 13) |
+						(((u32)cfg->trc & 0xf) << 9) |
+						(((u32)cfg->trcd & 0x7) << 6) |
+						(((u32)cfg->trp & 0x7) << 3) |
+						((u32)cfg->cl & 0x7);
+
+			*(volatile u32 *) SDC0_SDRAM_REFRESH = (u32)cfg->refcnt & 0xfff;
+
+			*(volatile u32 *) SDC0_SDRAM_POWERON = (u32)cfg->pwroncnt & 0xffff;
+
+			*(volatile u32 *) SDC0_SDRAM_CFG2 = (((u32)cfg->memchip_dtype & 0x3) << 11) |
+						(((u32)cfg->twr & 0x3) << 8) |
+						(1 << 7) |
+						(1 << 6) |
+						(((u32)cfg->buswidth & 0x1) << 5) |
+						(((u32)cfg->tmrd & 0x7) << 2) |
+						((u32)cfg->trrd & 0x3);
+		} else {
+			*(volatile u32 *) SDC0_CSSD0_CFG = (((u32)cfg->buswidth & 0x3) << 11) |
+					((((u32)cfg->addrsetup >> 2) & 0x1) << 10) |
+					(((u32)cfg->memtype & 0x1) << 9) |
+					(((u32)cfg->addrsetup & 0x3) << 7) |
+					(((u32)cfg->level & 0x1) << 6) |
+					(((u32)cfg->dqm_mode & 0x1) << 5) |
+					(((u32)cfg->cmdwidth & 0xf) << 1);
+		}
+
+		*(volatile u32 *) ASD_CSE |= (1 << EXP_CSSD0);
+
+		break;
+
+	case EXP_CSSD1: 
+		*(volatile u32 *) ASD_MBA_EXP_CSSD1 = ((baseaddr >> 16) << 4) | segment_size;
+		*(volatile u32 *) ASD_EXA_EXP_CSSD1 = (ext_baseaddr >> 27);
+
+		*(volatile u32 *) SDC0_CSSD1_CFG = (((u32)cfg->buswidth & 0x3) << 11) |
+					((((u32)cfg->addrsetup >> 2) & 0x1) << 10) |
+					(((u32)cfg->memtype & 0x1) << 9) |
+					(((u32)cfg->addrsetup & 0x3) << 7) |
+					(((u32)cfg->level & 0x1) << 6) |
+					(((u32)cfg->dqm_mode & 0x1) << 5) |
+					(((u32)cfg->cmdwidth & 0xf) << 1);
+
+		*(volatile u32 *) ASD_CSE |= (1 << EXP_CSSD1);
+	
+		break;
+
+	case EXP_CSBOOT:
+		*(volatile u32 *)SDC0_CSBOOT_CFG = (((u32)cfg->buswidth & 0x3) << 11) |
+					((((u32)cfg->addrsetup >> 2) & 0x1) << 10) |
+					(((u32)cfg->memtype & 0x1) << 9) |
+					(((u32)cfg->addrsetup & 0x3) << 7) |
+					(((u32)cfg->level & 0x1) << 6) |
+					(((u32)cfg->dqm_mode & 0x1) << 5) |
+					(((u32)cfg->cmdwidth & 0xf) << 1);
+		
+		*(volatile u32 *)ASD_CSE |= (1 << EXP_CSBOOT);
+		
+		break;
+
+	case EXP_CSP0:
+		*(volatile u32 *)SDC0_CSP0_CFG = (((u32)cfg->buswidth & 0x3) << 11) |
+					((((u32)cfg->addrsetup >> 2) & 0x1) << 10) |
+					(((u32)cfg->memtype & 0x1) << 9) |
+					(((u32)cfg->addrsetup & 0x3) << 7) |
+					(((u32)cfg->level & 0x1) << 6) |
+					(((u32)cfg->dqm_mode & 0x1) << 5) |
+					(((u32)cfg->cmdwidth & 0xf) << 1);
+		
+		*(volatile u32 *)ASD_CSE |= (1 << EXP_CSP0);
+
+		break;
+
+	case EXP_CSP1:
+		*(volatile u32 *)SDC0_CSP1_CFG = (((u32)cfg->buswidth & 0x3) << 11) |
+					((((u32)cfg->addrsetup >> 2) & 0x1) << 10) |
+					(((u32)cfg->memtype & 0x1) << 9) |
+					(((u32)cfg->addrsetup & 0x3) << 7) |
+					(((u32)cfg->level & 0x1) << 6) |
+					(((u32)cfg->dqm_mode & 0x1) << 5) |
+					(((u32)cfg->cmdwidth & 0xf) << 1);
+
+		*(volatile u32 *)ASD_CSE |= (1 << EXP_CSP1);
+		
+		break;
+
+	case EXP_CSP2:
+		*(volatile u32 *)SDC0_CSP2_CFG = (((u32)cfg->buswidth & 0x3) << 11) |
+					((((u32)cfg->addrsetup >> 2) & 0x1) << 10) |
+					(((u32)cfg->memtype & 0x1) << 9) |
+					(((u32)cfg->addrsetup & 0x3) << 7) |
+					(((u32)cfg->level & 0x1) << 6) |
+					(((u32)cfg->dqm_mode & 0x1) << 5) |
+					(((u32)cfg->cmdwidth & 0xf) << 1);
+
+		*(volatile u32 *)ASD_CSE |= (1 << EXP_CSP2);
+		
+		break;
+	
+	case SDR_CSSD0:
+		*(volatile u32 *) ASD_MBA_SDR_CSSD0 = ((baseaddr >> 16) << 4) | segment_size;
+		*(volatile u32 *) ASD_EXA_SDR_CSSD0 = (ext_baseaddr >> 27);
+
+		if (cfg->memtype == CS_MEMTYPE_SDRAM) {
+
+			*(volatile u32 *) SDC1_CSSD0_CFG = (((u32)cfg->memtype & 0x1) << 9);
+
+			*(volatile u32 *) SDC1_SDRAM_CFG1 = (((u32)cfg->tras & 0x7) << 13) |
+						(((u32)cfg->trc & 0xf) << 9) |
+						(((u32)cfg->trcd & 0x7) << 6) |
+						(((u32)cfg->trp & 0x7) << 3) |
+						((u32)cfg->cl & 0x7);
+
+			*(volatile u32 *) SDC1_SDRAM_REFRESH = (u32)cfg->refcnt & 0xfff;
+
+			*(volatile u32 *) SDC1_SDRAM_POWERON = (u32)cfg->pwroncnt & 0xffff;
+
+			*(volatile u32 *) SDC1_SDRAM_CFG2 = (((u32)cfg->memchip_dtype & 0x3) << 11) |
+						(((u32)cfg->twr & 0x3) << 8) |
+						(1 << 7) |
+						(1 << 6) |
+						(((u32)cfg->buswidth & 0x1) << 5) |
+						(((u32)cfg->tmrd & 0x7) << 2) |
+						((u32)cfg->trrd & 0x3);
+		} else {
+			*(volatile u32 *) SDC1_CSSD0_CFG = (((u32)cfg->buswidth & 0x3) << 11) |
+					((((u32)cfg->addrsetup >> 2) & 0x1) << 10) |
+					(((u32)cfg->memtype & 0x1) << 9) |
+					(((u32)cfg->addrsetup & 0x3) << 7) |
+					(((u32)cfg->level & 0x1) << 6) |
+					(((u32)cfg->dqm_mode & 0x1) << 5) |
+					(((u32)cfg->cmdwidth & 0xf) << 1);
+		}
+
+		*(volatile u32 *)ASD_CSE |= (1 << SDR_CSSD0);
+
+		break;
+
+	case SDR_CSSD1:
+		*(volatile u32 *) ASD_MBA_SDR_CSSD1 = ((baseaddr >> 16) << 4) | segment_size;
+		*(volatile u32 *) ASD_EXA_SDR_CSSD1 = (ext_baseaddr >> 27);
+
+		*(volatile u32 *) SDC1_CSSD1_CFG = (((u32)cfg->buswidth & 0x3) << 11) |
+					((((u32)cfg->addrsetup >> 2) & 0x1) << 10) |
+					(((u32)cfg->memtype & 0x1) << 9) |
+					(((u32)cfg->addrsetup & 0x3) << 7) |
+					(((u32)cfg->level & 0x1) << 6) |
+					(((u32)cfg->dqm_mode & 0x1) << 5) |
+					(((u32)cfg->cmdwidth & 0xf) << 1);
+
+		*(volatile u32 *)ASD_CSE |= (1 << SDR_CSSD1);
+	
+		break;
+	}
+
+out:
+	return 0;
+
+err:
+	return -1;
+}
+
+
+int SoC_high_mem_cfg (int cs)
+{
+	switch (cs) {
+	case EXP_CSSD0:
+		*(volatile u32 *)ASD_CSE &= ~((1 << 7) | (1 << 11));
+
+		break;
+
+	case EXP_CSSD1:
+		*(volatile u32 *)ASD_CSE |= (1 << 7);
+		*(volatile u32 *)ASD_CSE &= ~(1 << 11);
+
+		break;
+
+	case SDR_CSSD0:
+		*(volatile u32 *)ASD_CSE &= ~(1 << 7);
+		*(volatile u32 *)ASD_CSE |= (1 << 11);
+
+		break;
+
+	case SDR_CSSD1:
+		*(volatile u32 *)ASD_CSE |= (1 << 7) | (1 << 11);
+
+		break;
+
+	default:
+		goto err;
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
+
+int SoC_mem_divider_cfg (u32 address, int sdc)
+{
+	switch (sdc) {
+	case BELLOW_MEM_SDC0:
+		*(volatile u32 *)ASD_CSE &= ~(1 << 12);
+
+		break;
+
+	case BELLOW_MEM_SDC1:
+		*(volatile u32 *)ASD_CSE |= (1 << 12);
+		break;
+
+	default:
+		goto err;
+	}
+
+	*(volatile u32 *)ASD_MEM_DIVIDER = (address & 0xFF800000) >> 16;
+
+	return 0;
+
+err:
+	return -1;
+}
+
+/*
+* SoC_pll_cfg - used to configure ARM and AMBA bus clock frequencies
+*
+* mode - ARM clock mode,
+*	1 = async, independent ARM and AMBA bus clock frequencies (PLL2 used for bus clock).
+*	0 = sync, AMBA bus clock half ARM clock frequency (PLL2 not used)
+*
+* arm_clk - ARM clock frequency in Hz
+*
+* bus_clk - AMBA BUS clock frequency in Hz
+*
+*/
+int SoC_pll_cfg (int mode, unsigned int arm_clk, unsigned int bus_clk)
+{
+	volatile u32 delay_count;
+	u32 clkf;
+	u32 i;
+
+	if (mode == CLK_MODE_ASYNC) {
+		/* set ARM async clock mode */
+		asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+		i |= 0xC0000000;
+		asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+		/* async mode */
+		clkf = (4 * bus_clk) / CFG_REFCLKFREQ;
+
+		/* bus setup */
+		/* set PLL into BYPASS mode */
+		*(volatile u32 *)CLKCORE_AMBA_PLL |= PLL_BYPASS;
+
+		/* wait 500us for PLL to lock */
+		delay_count = 1000;
+		while (delay_count--);
+
+		/* Disable the PLL, by writing PLL Control Register bit 25 = 1. */
+		*(volatile u32 *)CLKCORE_AMBA_PLL |= PLL_POWER; 
+	
+		/* Program the PLL to the desired value and enable the PLL, by writing PLL Control Register fields W, X, and Y,  */
+		*(volatile u32 *)CLKCORE_AMBA_PLL = PLL_BYPASS | PLL_POWER | (clkf & 0x7f);
+
+		/* and writing bit 25 = 0. */
+		*(volatile u32 *)CLKCORE_AMBA_PLL = PLL_MUXSEL | (clkf & 0x7f);
+	} else {
+		/* set ARM sync clock mode */
+		asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+		i |= 0x40000000;
+		asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	}
+
+	/* ARM setup */
+	clkf = (2 * arm_clk) / CFG_REFCLKFREQ;
+	
+	/* set PLL into BYPASS mode */
+	*(volatile u32 *)CLKCORE_ARM_PLL |= PLL_BYPASS;
+
+	/* wait 500us for PLL to lock */
+	delay_count = 1000;
+	while (delay_count--);
+
+	/* Disable the PLL, by writing PLL Control Register bit 25 = 1. */
+	*(volatile u32 *)CLKCORE_ARM_PLL |= PLL_POWER; 
+	
+	/* Program the PLL to the desired value and enable the PLL, by writing PLL Control Register fields W, X, and Y */
+	*(volatile u32 *)CLKCORE_ARM_PLL = PLL_BYPASS | PLL_POWER | (clkf & 0x7f); 
+
+	/*and writing bit 25 = 0. */
+	*(volatile u32 *)CLKCORE_ARM_PLL &= ~PLL_POWER; 
+
+	/* Take the PLL out of bypass mode, by writing PLL Control Register bit 24 = 0. */
+	*(volatile u32 *)CLKCORE_ARM_PLL &= ~PLL_BYPASS;
+
+	// Ref: 
+	// 1) PLL Initialization Procedure  (82XXX-ERR-001-A.pdf )
+	// 2) M825xx PLL Registers chapter.pdf
+
+	return 0;
+}
+
+/*
+* SoC_gpio_cfg - configure GPIO pins as input or output pins
+*
+* gpio - gpio pin
+*
+* mode - gpio pin mode
+*	GPIO_TYPE_OUTPUT = output
+*	GPIO_TYPE_INPUT = input
+*
+*/
+int SoC_gpio_cfg(int gpio, int mode)
+{
+
+	if ((gpio < 0) || (gpio > 31))
+		goto err;
+
+	switch (mode) {
+	case GPIO_TYPE_INPUT:
+		*(volatile u32 *) GPIO_OUTPUT_ENABLE &= ~(1 << gpio);
+
+		break;
+
+	case GPIO_TYPE_OUTPUT:
+		if ((gpio == 18) || (gpio == 19))
+			goto err;
+
+		*(volatile u32 *) GPIO_OUTPUT_ENABLE |= 1 << gpio;
+
+		break;
+
+	default:
+		goto err;
+		break;
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
+int SoC_ioctrl_cfg(int resource, int enable)
+{
+	u32 bitmask;
+	u32 val;
+
+	switch (resource) {
+	case IOCTRL_SPI_BUS:
+		bitmask = (0x3 << 4);
+		break;
+
+	case IOCTRL_UART0:
+		bitmask = (0x3 << 12);
+		break;
+
+	case IOCTRL_UART1:
+		bitmask = (0x3 << 14);
+		break;
+
+	case IOCTRL_EXPA21_A22:
+		bitmask = (0x3 << 24);
+		break;
+
+	default:
+		goto err;
+	}
+
+	if (enable) {
+		do {
+			val = *(volatile u32 *)GPIO_IOCTRL | bitmask;
+			*(volatile u32 *)GPIO_LOCK = 0x55555555;	/* remove lock */
+			*(volatile u32 *)GPIO_IOCTRL = val;
+		} while ((*(volatile u32 *)GPIO_IOCTRL & bitmask) != bitmask);
+	} else {
+		do {
+			val = *(volatile u32 *)GPIO_IOCTRL & ~bitmask;
+			*(volatile u32 *)GPIO_LOCK = 0x55555555;	/* remove lock */
+			*(volatile u32 *)GPIO_IOCTRL = val;
+		} while ((*(volatile u32 *)GPIO_IOCTRL & bitmask));
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+

cpu/arm920t/comcerto/bsp_530.c

diff --git a/cpu/arm920t/comcerto/bsp_530.c b/cpu/arm920t/comcerto/bsp_530.c
new file mode 100644
index 0000000..6ec9c49
--- /dev/null
+++ b/cpu/arm920t/comcerto/bsp_530.c
@@ -0,0 +1,330 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bsp.h>
+
+/*
+* SoC_cs_cfg - configure Chip Select settings
+*
+* cs - chip select id
+*
+* enable - enable or disable the CS
+*	1 = enable
+*	0 = disable
+*
+* cfg - chip select configuration, ignored if enable = 0
+*
+*/
+int SoC_cs_cfg(int cs, int enable, struct cs_cfg *cfg)
+{
+	u32 segment_size = 0;
+	u32 baseaddr = 0; 
+
+	if ((cs != EXP_CSSD0) && (cs != EXP_CSSD1) && (cs != EXP_CSBOOT) &&
+	    (cs != EXP_CSP0))
+		goto err;
+
+	if (enable == CS_DISABLE) {
+		/* Disable the CS and exit */
+		*(volatile u32 *) ASD_CSE &= ~(1 << cs);
+		goto out;
+	}
+
+	if (cfg->memtype == CS_MEMTYPE_SDRAM) {
+		/* Other CS don't support SDRAM */
+		if (cs != EXP_CSSD0)
+			goto err;
+	}
+
+	if ((cs == EXP_CSSD0) || (cs == EXP_CSSD1)) {
+		baseaddr = cfg->baseaddr & 0x07FFFFFF;
+
+		switch (cfg->size) {
+		case 0x10000: segment_size = 0x0; /* 64KB */
+			break;	
+
+		case 0x20000: segment_size = 0x5; /* 128KB */
+			break;	
+
+		case 0x40000: segment_size = 0x6; /* 256KB */
+			break;	
+
+		case 0x80000: segment_size = 0x7; /* 512KB */
+			break;	
+
+		case 0x100000: segment_size = 0x8; /* 1MB */
+			break;	
+
+		case 0x200000: segment_size = 0x9; /* 2MB */
+			break;	
+
+		case 0x400000: segment_size = 0xa; /* 4MB */
+			break;	
+
+		case 0x800000: segment_size = 0xb; /* 8MB */
+			break;	
+
+		case 0x1000000: segment_size = 0xc; /* 16MB */
+			break;	
+
+		case 0x2000000: segment_size = 0xd; /* 32MB */
+			break;	
+
+		default:
+		case 0x4000000:
+			segment_size = 0xe; /* 64MB */
+			cfg->size = 0x4000000;
+			break;	
+		}
+
+		/* Make sure the base address is aligned on size boundary */
+		baseaddr &= ~(cfg->size - 1);
+	}
+	
+	switch (cs) {
+	case EXP_CSSD0:
+
+		*(volatile u32 *) ASD_MBA_EXP_CSSD0 = ((baseaddr >> 16) << 4) | segment_size;
+
+		if (cfg->memtype == CS_MEMTYPE_SDRAM) {
+			*(volatile u32 *) SDC0_CSSD0_CFG = (((u32)cfg->memtype & 0x1) << 9);
+
+			*(volatile u32 *) SDC0_SDRAM_CFG1 = (((u32)cfg->tras & 0x7) << 13) |
+						(((u32)cfg->trc & 0xf) << 9) |
+						(((u32)cfg->trcd & 0x7) << 6) |
+						(((u32)cfg->trp & 0x7) << 3) |
+						((u32)cfg->cl & 0x7);
+
+			*(volatile u32 *) SDC0_SDRAM_REFRESH = (u32)cfg->refcnt & 0xfff;
+
+			*(volatile u32 *) SDC0_SDRAM_POWERON = (u32)cfg->pwroncnt & 0xffff;
+
+			*(volatile u32 *) SDC0_SDRAM_CFG2 = (((u32)cfg->memchip_dtype & 0x3) << 11) |
+						(((u32)cfg->twr & 0x3) << 8) |
+						(1 << 7) |
+						(1 << 6) |
+						(((u32)cfg->buswidth & 0x1) << 5) |
+						(((u32)cfg->tmrd & 0x7) << 2) |
+						((u32)cfg->trrd & 0x3);
+		} else {
+			*(volatile u32 *) SDC0_CSSD0_CFG = (((u32)cfg->buswidth & 0x3) << 11) |
+					((((u32)cfg->addrsetup >> 2) & 0x1) << 10) |
+					(((u32)cfg->memtype & 0x1) << 9) |
+					(((u32)cfg->addrsetup & 0x3) << 7) |
+					(((u32)cfg->level & 0x1) << 6) |
+					(((u32)cfg->dqm_mode & 0x1) << 5) |
+					(((u32)cfg->cmdwidth & 0xf) << 1);
+		}
+
+		*(volatile u32 *) ASD_CSE |= (1 << EXP_CSSD0);
+
+		break;
+
+	case EXP_CSSD1: 
+		*(volatile u32 *) ASD_MBA_EXP_CSSD1 = ((baseaddr >> 16) << 4) | segment_size;
+
+		*(volatile u32 *) SDC0_CSSD1_CFG = (((u32)cfg->buswidth & 0x3) << 11) |
+					((((u32)cfg->addrsetup >> 2) & 0x1) << 10) |
+					(((u32)cfg->memtype & 0x1) << 9) |
+					(((u32)cfg->addrsetup & 0x3) << 7) |
+					(((u32)cfg->level & 0x1) << 6) |
+					(((u32)cfg->dqm_mode & 0x1) << 5) |
+					(((u32)cfg->cmdwidth & 0xf) << 1);
+
+		*(volatile u32 *) ASD_CSE |= (1 << EXP_CSSD1);
+	
+		break;
+
+	case EXP_CSBOOT:
+		*(volatile u32 *)SDC0_CSBOOT_CFG = (((u32)cfg->buswidth & 0x3) << 11) |
+					((((u32)cfg->addrsetup >> 2) & 0x1) << 10) |
+					(((u32)cfg->memtype & 0x1) << 9) |
+					(((u32)cfg->addrsetup & 0x3) << 7) |
+					(((u32)cfg->level & 0x1) << 6) |
+					(((u32)cfg->dqm_mode & 0x1) << 5) |
+					(((u32)cfg->cmdwidth & 0xf) << 1);
+		
+		*(volatile u32 *)ASD_CSE |= (1 << EXP_CSBOOT);
+		
+		break;
+
+	case EXP_CSP0:
+		*(volatile u32 *)SDC0_CSP0_CFG = (((u32)cfg->buswidth & 0x3) << 11) |
+					((((u32)cfg->addrsetup >> 2) & 0x1) << 10) |
+					(((u32)cfg->memtype & 0x1) << 9) |
+					(((u32)cfg->addrsetup & 0x3) << 7) |
+					(((u32)cfg->level & 0x1) << 6) |
+					(((u32)cfg->dqm_mode & 0x1) << 5) |
+					(((u32)cfg->cmdwidth & 0xf) << 1);
+		
+		*(volatile u32 *)ASD_CSE |= (1 << EXP_CSP0);
+
+		break;
+	}
+
+out:
+	return 0;
+
+err:
+	return -1;
+}
+
+
+int SoC_high_mem_cfg (int cs)
+{
+	switch (cs) {
+	case EXP_CSSD0:
+		*(volatile u32 *)ASD_CSE &= ~(1 << 7);
+
+		break;
+
+	case EXP_CSSD1:
+		*(volatile u32 *)ASD_CSE |= (1 << 7);
+
+		break;
+
+	default:
+		goto err;
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
+/*
+* SoC_pll_cfg - used to configure ARM and AMBA bus clock frequencies
+*
+* mode - ARM clock mode,
+*	1 = async, independent ARM and AMBA bus clock frequencies (PLL2 used for bus clock).
+*	0 = sync, AMBA bus clock half ARM clock frequency (PLL2 not used)
+*
+* arm_clk - ARM clock frequency in Hz
+*
+* bus_clk - AMBA BUS clock frequency in Hz
+*
+*/
+int SoC_pll_cfg (int mode, unsigned int arm_clk, unsigned int bus_clk)
+{
+	volatile u32 delay_count;
+	u32 clkf;
+	u32 i;
+
+	if (mode == CLK_MODE_ASYNC) {
+		/* set ARM async clock mode */
+		asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+		i |= 0xC0000000;
+		asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+		/* async mode */
+		clkf = (4 * bus_clk) / CFG_REFCLKFREQ;
+
+		/* bus setup */
+		/* set PLL into BYPASS mode */
+		*(volatile u32 *)CLKCORE_AMBA_PLL |= PLL_BYPASS;
+
+		/* wait 500us for PLL to lock */
+		delay_count = 1000;
+		while (delay_count--);
+
+		/* Disable the PLL, by writing PLL Control Register bit 25 = 1. */
+		*(volatile u32 *)CLKCORE_AMBA_PLL |= PLL_POWER; 
+	
+		/* Program the PLL to the desired value and enable the PLL, by writing PLL Control Register fields W, X, and Y,  */
+		*(volatile u32 *)CLKCORE_AMBA_PLL = PLL_BYPASS | PLL_POWER | (clkf & 0x7f);
+
+		/* and writing bit 25 = 0. */
+		*(volatile u32 *)CLKCORE_AMBA_PLL = PLL_MUXSEL | (clkf & 0x7f);
+	} else {
+		/* set ARM sync clock mode */
+		asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+		i |= 0x40000000;
+		asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	}
+
+	/* ARM setup */
+	clkf = (2 * arm_clk) / CFG_REFCLKFREQ;
+	
+	/* set PLL into BYPASS mode */
+	*(volatile u32 *)CLKCORE_ARM_PLL |= PLL_BYPASS;
+
+	/* wait 500us for PLL to lock */
+	delay_count = 1000;
+	while (delay_count--);
+
+	/* Disable the PLL, by writing PLL Control Register bit 25 = 1. */
+	*(volatile u32 *)CLKCORE_ARM_PLL |= PLL_POWER; 
+	
+	/* Program the PLL to the desired value and enable the PLL, by writing PLL Control Register fields W, X, and Y */
+	*(volatile u32 *)CLKCORE_ARM_PLL = PLL_BYPASS | PLL_POWER | (clkf & 0x7f); 
+
+	/*and writing bit 25 = 0. */
+	*(volatile u32 *)CLKCORE_ARM_PLL &= ~PLL_POWER; 
+
+	/* Take the PLL out of bypass mode, by writing PLL Control Register bit 24 = 0. */
+	*(volatile u32 *)CLKCORE_ARM_PLL &= ~PLL_BYPASS;
+
+	// Ref: 
+	// 1) PLL Initialization Procedure  (82XXX-ERR-001-A.pdf )
+	// 2) M825xx PLL Registers chapter.pdf
+
+	return 0;
+}
+
+/*
+* SoC_gpio_cfg - configure GPIO pins as input or output pins
+*
+* gpio - gpio pin
+*
+* mode - gpio pin mode
+*	GPIO_TYPE_OUTPUT = output
+*	GPIO_TYPE_INPUT = input
+*
+*/
+int SoC_gpio_cfg(int gpio, int mode)
+{
+
+	if ((gpio < 0) || (gpio > 7))
+		goto err;
+
+	switch (mode) {
+	case GPIO_TYPE_INPUT:
+		*(volatile u32 *) GPIO_OUTPUT_ENABLE &= ~(1 << gpio);
+
+		break;
+
+	case GPIO_TYPE_OUTPUT:
+		*(volatile u32 *) GPIO_OUTPUT_ENABLE |= 1 << gpio;
+
+		break;
+
+	default:
+		goto err;
+		break;
+	}
+
+	return 0;
+
+err:
+	return -1;
+}

cpu/arm920t/comcerto/emac.c

diff --git a/cpu/arm920t/comcerto/emac.c b/cpu/arm920t/comcerto/emac.c
new file mode 100644
index 0000000..06f062e
--- /dev/null
+++ b/cpu/arm920t/comcerto/emac.c
@@ -0,0 +1,730 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_COMCERTO_EMAC)
+
+#if !defined(CONFIG_EMAC0) && !defined(CONFIG_EMAC1)
+#error must define one of CONFIG_EMAC0 or CONFIG_EMAC1
+#endif
+
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <net.h>
+
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#include <miiphy.h>
+#endif
+
+#define MAX_DEVNAME_SIZE	8
+
+struct bdesc {
+	volatile u8 *bptr;
+	volatile u32 bcontrol;
+	u32 dummy1;
+	u32 dummy2;
+};
+
+struct fdesc {
+	/* Hardware mapped fields */
+	void *next;		/* 4 bytes */
+	volatile u32 system;	/* 4 bytes */
+	volatile u32 fstatus;	/* 4 bytes */
+	volatile u32 fcontrol;	/* 4 bytes */
+	struct bdesc bdesc;	/* 16 bytes */
+};
+
+
+struct emac_dev {
+	char devname[MAX_DEVNAME_SIZE];
+
+	u32 baseaddr;
+	u32 idma_baseaddr;
+
+	s8 miifdl;
+	s8 mii100l;
+
+	unsigned int md_clk;
+	u8 phy_addr;
+
+	u8 mii_mode;
+	u8 phyctrldis;
+	u8 mii_link_pol;
+};
+
+
+static struct emac_dev emac0 = {
+	.devname = "emac0",
+	.baseaddr = EMAC0_BASEADDR,
+	.idma_baseaddr = IDMA_EMAC0_BASEADDR,
+
+#ifdef CONFIG_EMAC0_MIIFDL
+	.miifdl = CONFIG_EMAC0_MIIFDL,
+#else
+	.miifdl = -1,
+#endif
+
+#ifdef CONFIG_EMAC0_MII100L
+	.mii100l = CONFIG_EMAC0_MII100L,
+#else
+	.mii100l = -1,
+#endif
+
+#ifdef CONFIG_EMAC0_MII_MODE
+	.mii_mode = CONFIG_EMAC0_MII_MODE,
+#else
+	.mii_mode = EMAC_RMII_SMII_MODE,
+#endif
+
+#ifdef CONFIG_EMAC0_PHYCTRLDIS
+	.phyctrldis = CONFIG_EMAC0_PHYCTRLDIS,
+#else
+	.phyctrldis = 0x1,
+#endif
+
+#if CONFIG_EMAC0_MII_LINK_POL
+	.mii_link_pol = CONFIG_EMAC0_MII_LINK_POL,
+#else
+	.mii_link_pol = 0x0,
+#endif
+
+#ifdef CONFIG_EMAC0_MDCLOCK
+	.md_clk = CONFIG_EMAC0_MDCLOCK,
+#else
+	.md_clk = 2500000,
+#endif
+
+#ifdef CONFIG_EMAC0_PHY_ADDR
+	.phy_addr = CONFIG_EMAC0_PHY_ADDR,
+#else
+	.phy_addr = 0x00,
+#endif
+};
+
+#ifdef CONFIG_COMCERTO_800
+static struct emac_dev emac1 = {
+	.devname = "emac1",
+	.baseaddr = EMAC1_BASEADDR,
+	.idma_baseaddr = IDMA_EMAC1_BASEADDR,
+
+#ifdef CONFIG_EMAC1_MIIFDL
+	.miifdl = CONFIG_EMAC1_MIIFDL,
+#else
+	.miifdl = -1,
+#endif
+
+#ifdef CONFIG_EMAC1_MII100L
+	.mii100l = CONFIG_EMAC1_MII100L,
+#else
+	.mii100l = -1,
+#endif
+
+#ifdef CONFIG_EMAC1_MII_MODE
+	.mii_mode = CONFIG_EMAC1_MII_MODE,
+#else
+	.mii_mode = EMAC_RMII_SMII_MODE,
+#endif
+
+#ifdef CONFIG_EMAC1_PHYCTRLDIS
+	.phyctrldis = CONFIG_EMAC1_PHYCTRLDIS,
+#else
+	.phyctrldis = 0x1,
+#endif
+
+#if CONFIG_EMAC1_MII_LINK_POL
+	.mii_link_pol = CONFIG_EMAC1_MII_LINK_POL,
+#else
+	.mii_link_pol = 0x0,
+#endif
+
+#ifdef CONFIG_EMAC1_MDCLOCK
+	.md_clk = CONFIG_EMAC1_MDCLOCK,
+#else
+	.md_clk = 2500000,
+#endif
+
+#ifdef CONFIG_EMAC1_PHY_ADDR
+	.phy_addr = CONFIG_EMAC1_PHY_ADDR,
+#else
+	.phy_addr = 0x00,
+#endif
+};
+#endif /* CONFIG_COMCERTO_800 */
+
+#ifdef CONFIG_EMAC0
+static struct emac_dev *emac = &emac0;
+#else
+static struct emac_dev *emac = &emac1;
+#endif
+
+#define NUM_RX_DESC		16
+#define MAX_RX_BUFF_SIZE	2048
+
+static u32 rx_next;
+static u8 rx_ring_data_buff[NUM_RX_DESC * MAX_RX_BUFF_SIZE];
+
+static struct fdesc buff_aligned[NUM_RX_DESC] __attribute((aligned(16)));
+
+static struct fdesc tx_fdesc __attribute((aligned(16)));
+
+static struct fdesc *rx_ring;
+
+#define EMAC_disable_rx(emac)\
+	*(volatile u32 *)((emac)->baseaddr + EMAC_RXCTRL) &= ~RX_EN
+
+#define EMAC_disable_tx(emac)\
+	*(volatile u32 *)((emac)->baseaddr + EMAC_TXCTRL) &= ~TX_EN
+
+#define EMAC_enable_rx(emac)\
+	*(volatile u32 *)((emac)->baseaddr + EMAC_RXCTRL) |= RX_EN
+
+#define EMAC_enable_tx(emac)\
+	*(volatile u32 *)((emac)->baseaddr + EMAC_TXCTRL) |= TX_EN
+
+
+static int get_mdcckse(int md_clk)
+{
+	unsigned int div = CFG_HZ_CLOCK / md_clk;
+
+	if (div > 60)
+		return 0x3;
+	else if (div > 28)
+		return 0x2;
+	else if (div > 16)
+		return 0x1;
+	else
+		return 0x0;
+}
+
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+
+static int comcerto_miiphy_write(char *devname, unsigned char addr,
+			unsigned char reg, unsigned short value)
+{
+	struct emac_dev *emac;
+
+	if ((addr > 31) || (reg > 31))
+		return 1;
+
+	if (!strcmp(devname, emac0.devname))
+		emac = &emac0;
+#ifdef CONFIG_COMCERTO_800
+	else if (!strcmp(devname, emac1.devname))
+		emac = &emac1;
+#endif
+	else
+		return -1;
+
+	if (*(volatile u32 *)(emac->baseaddr + EMAC_MDCA) & EMAC_MDIO_BUSY)
+		return 1;
+
+	/* start a write */
+	*(volatile u32 *)(emac->baseaddr + EMAC_MDDATA) = value;
+	*(volatile u32 *)(emac->baseaddr + EMAC_MDCA) = (reg | (addr << 5) | EMAC_MDIO_WRITE | EMAC_MDIO_BUSY);
+
+	while (*(volatile u32 *)(emac->baseaddr + EMAC_MDCA) & EMAC_MDIO_BUSY) ;
+
+	return 0;
+}
+
+
+static int comcerto_miiphy_read(char *devname, unsigned char addr,
+			unsigned char reg, unsigned short *value)
+{
+	struct emac_dev *emac;
+
+	if ((addr > 31) || (reg > 31))
+		return 1;
+
+	if (!strcmp(devname, emac0.devname))
+		emac = &emac0;
+#ifdef CONFIG_COMCERTO_800
+	else if (!strcmp(devname, emac1.devname))
+		emac = &emac1;
+#endif
+	else
+		return -1;
+
+	if (*(volatile u32 *)(emac->baseaddr + EMAC_MDCA) & EMAC_MDIO_BUSY)
+		return 1;
+
+	*(volatile u32 *)(emac->baseaddr + EMAC_MDCA) = (reg | (addr << 5) | EMAC_MDIO_BUSY);
+
+	while (*(volatile u32 *)(emac->baseaddr + EMAC_MDCA) & EMAC_MDIO_BUSY) ;
+
+	*value = *(volatile u32 *)(emac->baseaddr + EMAC_MDDATA);
+
+	return 0;
+}
+
+
+static u32 get_ocr_mii_cfg(struct emac_dev *emac, u32 ocr)
+{
+	unsigned short tmp;
+
+	miiphy_read(emac->devname, emac->phy_addr, PHY_BMSR, &tmp);
+
+#ifdef CFG_FAULT_ECHO_LINK_DOWN
+	if (miiphy_link(emac->devname, emac->phy_addr))
+		ocr &= ~EMAC_OCR_MII100L;
+	else
+		ocr |= EMAC_OCR_MII100L;
+#else
+	ocr &= ~EMAC_OCR_MII100L;
+#endif /* CFG_FAULT_ECHO_LINK_DOWN */
+	if (emac->miifdl < 0) {
+		/* get link duplex from phy */
+		if (miiphy_duplex(emac->devname, emac->phy_addr) == HALF)
+			ocr |= EMAC_OCR_MIIFDL;
+		else
+			ocr &= ~EMAC_OCR_MIIFDL;
+	} else {
+		/* force link duplex */
+		if (emac->miifdl)
+			ocr |= EMAC_OCR_MIIFDL;
+		else
+			ocr &= ~EMAC_OCR_MIIFDL;
+	}
+
+	if (emac->mii100l < 0) {
+		/* get link speed from phy */
+		if (miiphy_speed(emac->devname, emac->phy_addr) == _10BASET)
+			ocr |= EMAC_OCR_MII100L;
+		else
+			ocr &= ~EMAC_OCR_MII100L;
+	} else {
+		/* force link speed */
+		if (emac->mii100l)
+			ocr |= EMAC_OCR_MII100L;
+		else
+			ocr &= ~EMAC_OCR_MII100L;
+	}
+
+	return ocr;
+}
+
+#else
+
+static u32 get_ocr_mii_cfg(struct emac_dev *emac, u32 ocr)
+{
+	ocr &= ~EMAC_OCR_MII100L;
+
+	if (emac->miifdl < 0) {
+		ocr &= ~EMAC_OCR_MIIFDL;
+	} else {
+		/* force link duplex */
+		if (emac->miifdl)
+			ocr |= EMAC_OCR_MIIFDL;
+		else
+			ocr &= ~EMAC_OCR_MIIFDL;
+	}
+
+	if (emac->mii100l < 0) {
+		ocr &= ~EMAC_OCR_MII100L;
+	} else {
+		/* force link speed */
+		if (emac->mii100l)
+			ocr |= EMAC_OCR_MII100L;
+		else
+			ocr &= ~EMAC_OCR_MII100L;
+	}
+
+	return ocr;
+}
+#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
+
+
+#ifdef CONFIG_NET_MULTI
+
+#else
+int comcerto_miiphy_initialize(bd_t *bis)
+{
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+	u32 ocr;
+
+#ifdef CONFIG_EMAC0
+	ocr = *(volatile u32 *)(emac0.baseaddr + EMAC_OCR);
+	ocr &= ~(0x3 << 2);
+	*(volatile u32 *)(emac0.baseaddr + EMAC_OCR) = ocr | (get_mdcckse(emac0.md_clk) << 2);
+	miiphy_register(emac0.devname, comcerto_miiphy_read, comcerto_miiphy_write);
+#endif
+
+#ifdef CONFIG_EMAC1
+	ocr = *(volatile u32 *)(emac1.baseaddr + EMAC_OCR);
+	ocr &= ~(0x3 << 2);
+	*(volatile u32 *)(emac1.baseaddr + EMAC_OCR) = ocr | (get_mdcckse(emac1.md_clk) << 2);
+	miiphy_register(emac1.devname, comcerto_miiphy_read, comcerto_miiphy_write);
+#endif
+
+#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
+
+	return 0;
+}
+#endif /* CONFIG_NET_MULTI */
+
+static int emac_arc_add(struct emac_dev *emac, u8 *mac_addr)
+{
+	u32 temp;
+	u8 offset = 0;
+
+	/* we are in boot loader, even though this EMAC handles more than 20 entries,
+	   we only gonna use one (Entry 0) */
+
+	temp = *mac_addr++;
+	temp <<= 8;
+	temp |= *mac_addr++;
+	temp <<= 8;
+	temp |= *mac_addr++;
+	temp <<= 8;
+	temp |= *mac_addr++;
+	*(volatile u32 *)(emac->baseaddr + EMAC_ARC_TABLE + offset) = temp;
+	offset += 4;
+	temp = *mac_addr++;
+	temp <<= 8;
+	temp |= *mac_addr++;
+	temp <<= 16;
+	*(volatile u32 *)(emac->baseaddr + EMAC_ARC_TABLE + offset) = ((*(volatile u32 *)(emac->baseaddr + EMAC_ARC_TABLE + offset)) & 0x0000FFFF) | temp;
+
+	*(volatile u32 *)(emac->baseaddr + EMAC_ARCENA) |= 1;
+	*(volatile u32 *)(emac->baseaddr + EMAC_ARCCTRL) |= ARC_COMPENA;
+
+	return 1;
+}
+
+
+static void emac_rx_ring_init(void)
+{
+	u32 i;
+	u8 *pU8;
+
+	pU8 = rx_ring_data_buff;
+	rx_ring = buff_aligned;
+
+	for (i = 0; i < NUM_RX_DESC - 1; i++) {
+		rx_ring[i].next = &rx_ring[i + 1];
+		rx_ring[i].system = i;
+		rx_ring[i].fstatus = 0;
+		rx_ring[i].fcontrol = IDMA_FCONTROL_FREADY;
+		rx_ring[i].bdesc.bptr = pU8;
+		rx_ring[i].bdesc.bcontrol = 0;
+		pU8 += MAX_RX_BUFF_SIZE;
+	}
+
+	rx_ring[i].next = &rx_ring[0];
+	rx_ring[i].system = i;
+	rx_ring[i].fstatus = 0;
+	rx_ring[i].fcontrol = 0;
+	rx_ring[i].bdesc.bptr = pU8;
+	rx_ring[i].bdesc.bcontrol = 0;
+
+	rx_next = 0;
+}
+
+static void emac_ip_init(struct emac_dev *emac)
+{
+	u32 i;
+
+	/* EMAC_MACCTRL register : set FullDup (as MII_Conn is high), Conn as Force MII, and Soft reset */
+	*(volatile u32 *)(emac->baseaddr + EMAC_MACCTRL) = MAC_FULLDUP | MAC_MIIRATE | MAC_RESET;
+
+	/* wait reset done */
+	while (*(volatile u32 *)(emac->baseaddr + EMAC_MACCTRL) & MAC_RESET) ;
+
+	/* EMAC_ARC_TABLE init */
+	for (i = 0; i < (6 * MAX_ARC_ENTRIES); i += 4)
+		*(volatile u32 *)((emac->baseaddr + EMAC_ARC_TABLE) + i) = 0;
+
+	/* EMAC_ARCENA : set to 0 as no ARC entry yet */
+	*(volatile u32 *)(emac->baseaddr + EMAC_ARCENA) = 0;
+
+	/* EMAC_ARCCTRL : accept BroadCast only (Local MAC address no yet defined) */
+	*(volatile u32 *)(emac->baseaddr + EMAC_ARCCTRL) = ARC_BROADACC;
+
+	/* EMAC_TXCTRL  : set Tx_en */
+	*(volatile u32 *)(emac->baseaddr + EMAC_TXCTRL) = TX_EN;
+
+	/* EMAC_RXCTRL  : set Rx_en, Strip CRC, ShortEn, */
+	*(volatile u32 *)(emac->baseaddr + EMAC_RXCTRL) = RX_EN | RX_STRIPCRC | RX_SHORTEN;
+}
+
+
+static void emac_ipif_init(struct emac_dev *emac)
+{
+	u32 ocr, icr;
+
+#ifdef CONFIG_COMCERTO_530
+	ocr = 0x00200200 | (get_mdcckse(emac->md_clk) << 2);	/* force 100Mbit, full duplex, link up */
+	icr = 0x00000000;
+
+	ocr = get_ocr_mii_cfg(emac, ocr);
+#else
+	ocr = 0x00200200 | (get_mdcckse(emac->md_clk) << 2);	/* force 100Mbit, full duplex, link up */
+	icr = 0x00008000;					/* use software settings */
+
+	switch (emac->mii_mode) {
+	case EMAC_MII_MODE:
+		ocr |= EMAC_OCR_SEL_MII_MODE;
+		break;
+
+	case EMAC_FORCE_RMII_MODE:
+		ocr &= ~EMAC_OCR_SEL_MII_MODE;
+		ocr |= EMAC_OCR_SW_SMII_OVRD;
+		ocr &= ~EMAC_OCR_SW_SMII_MODE;
+		break;
+
+	case EMAC_FORCE_SMII_MODE:
+		ocr &= ~EMAC_OCR_SEL_MII_MODE;
+		ocr |= EMAC_OCR_SW_SMII_OVRD;
+		ocr |= EMAC_OCR_SW_SMII_MODE;
+		break;
+
+	case EMAC_RMII_SMII_MODE:
+	default:
+		ocr &= ~EMAC_OCR_SEL_MII_MODE;
+		ocr &= ~EMAC_OCR_SW_SMII_OVRD;
+		break;
+	}
+
+	switch (emac->mii_mode) {
+	case EMAC_MII_MODE:
+		ocr = get_ocr_mii_cfg(emac, ocr);
+		break;
+
+	case EMAC_FORCE_RMII_MODE:
+	case EMAC_FORCE_SMII_MODE:
+	case EMAC_RMII_SMII_MODE:
+	default:
+		if (emac->phyctrldis) {
+			icr |= EMAC_ICR_PHYCTRLDIS;
+
+			ocr = get_ocr_mii_cfg(emac, ocr);
+
+		} else {
+			icr &= ~EMAC_ICR_PHYCTRLDIS;
+			icr &= ~(EMAC_ICR_MII100L_POL | EMAC_ICR_MIIFDL_POL | EMAC_ICR_MIILINK_POL);
+			icr |= (emac->mii_link_pol & 0x7) << 8;
+		}
+
+		break;
+	}
+#endif
+
+	/* Init EMAC Operation Controlling Register */
+	*(volatile u32 *)(emac->baseaddr + EMAC_OCR) = ocr;
+	*(volatile u32 *)(emac->baseaddr + EMAC_ICR) = icr;
+
+	/* init DMA TX/RX Data FIFO Config Registers */
+	*(volatile u32 *)(emac->baseaddr + EMAC_HOST_FIFO_CONTROL) = EMAC_HOST_HBTXRQ_EN | EMAC_HOST_RXFF_EN | EMAC_HOST_HBTXRQ_EN | EMAC_HOST_TXFF_EN;
+
+	/* TX threshold  Host =EMAC */
+	*(volatile u32 *)(emac->baseaddr + EMAC_HOST_FIFO_TXHIGH) = 0x000F3;
+
+	*(volatile u32 *)(emac->baseaddr + EMAC_HOST_FIFO_TXLOW) = 0x00F0;
+
+	/* RX threshold */
+	*(volatile u32 *)(emac->baseaddr + EMAC_HOST_FIFO_RXHIGH) = 0x0013;
+	*(volatile u32 *)(emac->baseaddr + EMAC_HOST_FIFO_RXLOW) = 0x0012;
+
+	/* arm side */
+
+	*(volatile u32 *)(emac->baseaddr + EMAC_ARM_FIFO_TXHIGH) = 0x00C0;
+	*(volatile u32 *)(emac->baseaddr + EMAC_ARM_FIFO_TXLOW) = 0x0020;
+
+	/* RX threshold */
+	*(volatile u32 *)(emac->baseaddr + EMAC_ARM_FIFO_RXHIGH) = 0x00E0;
+	*(volatile u32 *)(emac->baseaddr + EMAC_ARM_FIFO_RXLOW) = 0x0040;
+	*(volatile u32 *)(emac->baseaddr + EMAC_ARM_FIFO_CONTROL) = EMAC_ARM_RXDREQWE | EMAC_ARM_TXDREQRE;
+
+	*(volatile u32 *)ASA_TERMINAL_COUNT_CFG |= ASA_TC_REQIDMAEN;
+
+}
+
+
+static void emac_dma_init(struct emac_dev *emac)
+{
+	/* Init IDMA */
+	/* Memory to EMAC (Tx) */
+	*(volatile u32 *)(emac->idma_baseaddr + MMEM_BURST) = (IDMA_BURST_MASK & 0xFF) | (IDMA_PRTY_MASK & 0x0200);	/* burst size 255, priority 1 */
+	*(volatile u32 *)(emac->idma_baseaddr + MMEM_START) = 0;
+
+	/* EMAC to Memory (Rx) */
+	*(volatile u32 *)(emac->idma_baseaddr + EMMM_BURST) = (IDMA_BURST_MASK & 0xFF) | (IDMA_PRTY_MASK & 0x0100);	/* burst size 255, priority 1 */  
+	*(volatile u32 *)(emac->idma_baseaddr + EMMM_START) = 0;
+}
+
+
+static int emac_init(struct emac_dev *emac, u8 *mac_addr)
+{
+	*(volatile u32 *)(emac->idma_baseaddr + EMMM_SOFT_RESET) = 0x1;
+	*(volatile u32 *)(emac->idma_baseaddr + MMEM_SOFT_RESET) = 0x1;
+
+	*(volatile u32 *)(emac->baseaddr + EMAC_OCR) |= EMAC_OCR_IP_HRESET;
+	udelay(100);
+	*(volatile u32 *)(emac->baseaddr + EMAC_OCR) &= ~EMAC_OCR_IP_HRESET;
+
+	emac_ipif_init(emac);
+	emac_ip_init(emac);
+	emac_dma_init(emac);
+
+	/* Add Mac Address in the ARC table */
+	emac_arc_add(emac, mac_addr);
+
+	/* Init Ehternet buffers */
+	emac_rx_ring_init();
+
+	/* Start Rx EDMA */
+	*(volatile u32 *)(emac->idma_baseaddr + EMMM_HEAD) = (u32) &rx_ring[rx_next];
+	*(volatile u32 *)(emac->idma_baseaddr + EMMM_START) |= IDMA_START;
+
+	return 0;
+}
+
+
+static int emac_send(struct emac_dev *emac, volatile void *packet, int length)
+{
+	int i;
+
+	memset(&tx_fdesc, 0, sizeof(struct fdesc));
+
+	/* build the tx frame descriptor here */
+	tx_fdesc.fcontrol = IDMA_FCONTROL_FREADY | IDMA_FCONTROL_FLAST;
+	tx_fdesc.fstatus = 0;
+	tx_fdesc.bdesc.bptr = packet;
+	tx_fdesc.bdesc.bcontrol = length | IDMA_BCONTROL_BLAST;
+
+	/* Check if DMA Stopped */
+	if (!(*(volatile u32 *)(emac->idma_baseaddr + MMEM_START) & IDMA_START)) {
+		*(volatile u32 *)(emac->idma_baseaddr + MMEM_HEAD) = (u32) &tx_fdesc;
+		*(volatile u32 *)(emac->idma_baseaddr + MMEM_START) |= IDMA_START;
+	} else {
+		printf("Emac: tx EDMA busy!\n");
+		return (-1);
+	}
+
+	i = 0;
+	while ((tx_fdesc.fstatus & IDMA_FSTATUS_FRAME_DONE_MASK) == 0) {
+		udelay(100);
+		i++;
+		if (i == 50000) {
+			printf("Emac: tx timed out! %x\n", tx_fdesc.fstatus);
+			return (-1);
+		}
+	}
+
+	if (*(volatile u32 *)(emac->idma_baseaddr + MMEM_START) & IDMA_START) {
+		printf("Emac: tx did not stop after sending a packet!\n");
+	}
+
+	return (length);
+}
+
+
+static int emac_rx(struct emac_dev *emac)
+{
+	int rx_prev;
+	int length;
+	int total_length = 0;
+
+	/* loop thru rx FDescs */
+	while (1) {
+		if ((rx_ring[rx_next].fstatus & IDMA_FSTATUS_FRAME_DONE_MASK) == 0)
+			break;
+
+		/* mark rx_next not usable */
+		rx_ring[rx_next].fcontrol = 0;
+
+		if (rx_ring[rx_next].fstatus & (1 << 10)) {
+
+			length = rx_ring[rx_next].bdesc.bcontrol & IDMA_BCONTROL_BLEN_MASK;
+			if (length > MAX_RX_BUFF_SIZE) {
+				printf("Emac: frame too big (%d bytes)!\n", length);
+				length = MAX_RX_BUFF_SIZE;
+			}
+
+			/* Pass the packet up to the protocol layers. */
+			NetReceive(rx_ring[rx_next].bdesc.bptr, length);
+			total_length += length;
+		}
+
+		/* rx_prev can be used now */
+		if (rx_next == 0)
+			rx_prev = NUM_RX_DESC - 1;
+		else
+			rx_prev = rx_next - 1;
+
+		rx_ring[rx_prev].fstatus = 0;
+		rx_ring[rx_prev].fcontrol = IDMA_FCONTROL_FREADY;
+
+		rx_next++;
+		if (rx_next == NUM_RX_DESC)
+			rx_next = 0;
+	}
+
+	/* Check if DMA Stopped, if RX is stopped, restart */
+	if (!(*(volatile u32 *)(emac->idma_baseaddr + EMMM_START) & IDMA_START)) {
+		*(volatile u32 *)(emac->idma_baseaddr + EMMM_HEAD) = (u32) &rx_ring[rx_next];
+		*(volatile u32 *)(emac->idma_baseaddr + EMMM_START) |= IDMA_START;
+	}
+
+	return (total_length);
+}
+
+
+static void emac_halt(struct emac_dev *emac)
+{
+	/* stop EMAC */
+	EMAC_disable_rx(emac);
+	EMAC_disable_tx(emac);
+
+	*(volatile u32 *)(emac->idma_baseaddr + EMMM_SOFT_RESET) = 0x1;
+	*(volatile u32 *)(emac->idma_baseaddr + MMEM_SOFT_RESET) = 0x1;
+}
+
+#ifdef CONFIG_NET_MULTI
+
+#else
+int eth_send(volatile void *packet, int length)
+{
+	if (length <= 0) {
+		printf("Emac: bad packet size: %d\n", length);
+		return (-1);
+	}
+
+	return emac_send(emac, packet, length);
+}
+
+int eth_init(bd_t * bd)
+{
+	return emac_init(emac, bd->bi_enetaddr);
+}
+
+
+int eth_rx(void)
+{
+	return emac_rx(emac);
+}
+
+void eth_halt(void)
+{
+	emac_halt(emac);
+}
+
+#endif /* CONFIG_NET_MULTI */
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_COMCERTO_EMAC) */

cpu/arm920t/comcerto/interrupts.c

diff --git a/cpu/arm920t/comcerto/interrupts.c b/cpu/arm920t/comcerto/interrupts.c
new file mode 100644
index 0000000..103adcf
--- /dev/null
+++ b/cpu/arm920t/comcerto/interrupts.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_COMCERTO_530
+
+#include "interrupts530.c"
+
+#else
+
+#include "interrupts800.c"
+
+#endif

cpu/arm920t/comcerto/interrupts530.c

diff --git a/cpu/arm920t/comcerto/interrupts530.c b/cpu/arm920t/comcerto/interrupts530.c
new file mode 100644
index 0000000..dc11226
--- /dev/null
+++ b/cpu/arm920t/comcerto/interrupts530.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+
+#define TIMER_LOAD_VAL		0x00ffffff
+#define CLOCK_COUNT_PER_USEC	(CFG_HZ_CLOCK / 1000 / 1000)
+#define USEC_PER_TICK		(1000 * 1000 / CFG_HZ)
+
+#define READ_TIMER SoC_timer0_get()
+
+
+static ulong ts_count, ts_usec;
+static ulong lastdec;
+
+int interrupt_init (void)
+{
+	SoC_timer0_set(TIMER_LOAD_VAL);
+
+	lastdec = TIMER_LOAD_VAL;
+	ts_count = 0;
+	ts_usec = 0;
+
+	return (0);
+}
+
+void reset_timer_masked (void)
+{
+	lastdec = READ_TIMER;
+	ts_count = 0;
+	ts_usec = 0;
+}
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+/* Returns usecs since last timer reset */
+ulong get_timer_raw (void)
+{
+	ulong step;
+	ulong now = READ_TIMER;
+
+	if (now < lastdec) {
+		/* normal mode */
+		step = lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		step = (TIMER_LOAD_VAL - now) + lastdec;
+	}
+
+	lastdec = now;
+
+	ts_count += step % CLOCK_COUNT_PER_USEC;
+	ts_usec += step / CLOCK_COUNT_PER_USEC;
+
+	if (ts_count >= CLOCK_COUNT_PER_USEC) {
+		ts_usec += ts_count / CLOCK_COUNT_PER_USEC;
+		ts_count %= CLOCK_COUNT_PER_USEC;
+	}
+
+	return ts_usec;
+}
+
+/* Returns tick count since last timer reset */
+ulong get_timer_masked (void)
+{
+	return get_timer_raw() / USEC_PER_TICK;
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong endtime = get_timer_raw () + usec;
+
+	while (get_timer_raw () < endtime)
+		;
+
+}
+
+void udelay (unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CFG_HZ;
+	return tbclk;
+}
+
+/*
+ *
+ */
+void reset_cpu (ulong ignored)
+{
+	while (1);
+	/* Never reached */
+}
+
+/*
+ * timer without interrupts
+ */
+
+
+void set_timer (ulong t)
+{
+	ts_count = 0;
+	ts_usec = t * USEC_PER_TICK;
+}

cpu/arm920t/comcerto/interrupts800.c

diff --git a/cpu/arm920t/comcerto/interrupts800.c b/cpu/arm920t/comcerto/interrupts800.c
new file mode 100644
index 0000000..cca343f
--- /dev/null
+++ b/cpu/arm920t/comcerto/interrupts800.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+
+#define TIMER_LOAD_VAL		0xffffffff
+#define CLOCK_COUNT_PER_USEC	(CFG_HZ_CLOCK / 1000 / 1000)
+#define USEC_PER_TICK		(1000 * 1000 / CFG_HZ)
+
+#define READ_TIMER SoC_timer0_get()
+
+
+static ulong ts_count, ts_usec;
+static ulong lastinc;
+
+int interrupt_init (void)
+{
+	SoC_timer0_set(TIMER_LOAD_VAL);
+
+	lastinc = 0;
+	ts_count = 0;
+	ts_usec = 0;
+
+	return (0);
+}
+
+void reset_timer_masked (void)
+{
+	lastinc = READ_TIMER;
+	ts_count = 0;
+	ts_usec = 0;
+}
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+/* Returns usecs since last timer reset */
+ulong get_timer_raw (void)
+{
+	ulong step;
+	ulong now = READ_TIMER;
+
+	if (now > lastinc) {
+		/* normal mode */
+		step = now - lastinc;
+	} else {
+		/* we have an overflow ... */
+		step = (TIMER_LOAD_VAL - lastinc) + now;
+	}
+
+	lastinc = now;
+
+	ts_count += step % CLOCK_COUNT_PER_USEC;
+	ts_usec += step / CLOCK_COUNT_PER_USEC;
+
+	if (ts_count >= CLOCK_COUNT_PER_USEC) {
+		ts_usec += ts_count / CLOCK_COUNT_PER_USEC;
+		ts_count %= CLOCK_COUNT_PER_USEC;
+	}
+
+	return ts_usec;
+}
+
+/* Returns tick count since last timer reset */
+ulong get_timer_masked (void)
+{
+	return get_timer_raw() / USEC_PER_TICK;
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong endtime = get_timer_raw () + usec;
+
+	while (get_timer_raw () < endtime)
+		;
+
+}
+
+void udelay (unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CFG_HZ;
+	return tbclk;
+}
+
+/*
+ *
+ */
+void reset_cpu (ulong ignored)
+{
+	while (1);
+	/* Never reached */
+}
+
+/*
+ * timer without interrupts
+ */
+
+
+void set_timer (ulong t)
+{
+	ts_count = 0;
+	ts_usec = t * USEC_PER_TICK;
+}

cpu/arm920t/comcerto/lowlevel_init.S

diff --git a/cpu/arm920t/comcerto/lowlevel_init.S b/cpu/arm920t/comcerto/lowlevel_init.S
new file mode 100644
index 0000000..c7550b8
--- /dev/null
+++ b/cpu/arm920t/comcerto/lowlevel_init.S
@@ -0,0 +1,40 @@
+/*
+ * SOC specific setup info
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/hardware.h>
+
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp, TMP_STACK /* set up a temporary stack */
+
+	stmdb	sp!, {ip, lr}
+	bl	bsp_init	/* go setup pll, memory */
+	ldmia	sp!, {ip, pc}	/* restore registers and return to caller */
+
+	/* the literal pools origin */
+	.ltorg
+TMP_STACK:
+	.word	CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET

cpu/arm920t/comcerto/serial-16550.c

diff --git a/cpu/arm920t/comcerto/serial-16550.c b/cpu/arm920t/comcerto/serial-16550.c
new file mode 100644
index 0000000..8be634d
--- /dev/null
+++ b/cpu/arm920t/comcerto/serial-16550.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_UART0) && !defined(CONFIG_UART1)
+#error must define one of CONFIG_UART0 or CONFIG_UART1
+#endif
+
+
+struct uart_regs {
+	volatile u32 data;	/* Receive/Transmit data register */
+	volatile u32 ier;	/* Interrupt Enable register */
+	volatile u32 iir_fcr;	/* Interrupt Identity register / FIFO Control register */
+	volatile u32 lcr;	/* Line Control register */
+	volatile u32 mcr;	/* Modem Control register */
+	volatile u32 lsr;	/* Line Status register */
+	volatile u32 msr;	/* Modem Status register */
+	volatile u32 sr;	/* Scratch register */
+};
+
+struct uart_dl_regs {
+	volatile u32 dll;	/* Divisor Latch (Low) */
+	volatile u32 dlh;	/* Divisor Latch (High) */
+};
+
+
+/* Interrupt Enable Register */
+/* UART 16550 */
+#define IER_RDI			(1 << 0)	/* Enable Received Data Available Interrupt */
+#define IER_THRI		(1 << 1)	/* Enable Transmitter holding register Interrupt */
+#define IER_RLSI		(1 << 2)	/* Enable receiver line status Interrupt */
+#define IER_MSI			(1 << 3)	/* Enable Modem status Interrupt */
+
+#define IIR_FIFOES1		(1 << 7)	/* FIFO Mode Enable Status */
+#define IIR_FIFOES0		(1 << 6)	/* FIFO Mode Enable Status */
+#define IIR_TOD			(1 << 3)	/* Time Out Detected */
+#define IIR_IID2			(1 << 2)	/* Interrupt Source Encoded */
+#define IIR_IID1			(1 << 1)	/* Interrupt Source Encoded */
+#define IIR_IP				(1 << 0)	/* Interrupt Pending (active low) */
+
+/* UART 16550 FIFO Control Register */
+#define FCR_FIFOEN			(1 << 0)
+#define FCR_RCVRRES			(1 << 1)
+#define FCR_XMITRES			(1 << 2)
+
+#define LCR_CHAR_LEN_5		0x00	  /* default */
+#define LCR_CHAR_LEN_6		0x01
+#define LCR_CHAR_LEN_7		0x02
+#define LCR_CHAR_LEN_8		0x03
+#define LCR_TWO_STOP		(1 << 2)  /* Two stop bit! */
+#define LCR_PEN			(1 << 3)  /* Parity Enable */
+#define LCR_EPS			(1 << 4)  /* Even Parity Select */
+#define LCR_PS			(1 << 5)  /* Enable Parity  Stuff */
+#define LCR_SBRK		(1 << 6)  /* Start Break */
+#define LCR_PSB			(1 << 7)  /* Parity Stuff Bit */
+#define LCR_DLAB		(1 << 7)  /* UART 16550 Divisor Latch Assess */
+
+#define LSR_RXFIFO_ERROR		(1 << 7)	/* FIFO Error Status */
+#define LSR_TEMT			(1 << 6)	/* Transmitter Empty */
+#define LSR_THRE			(1 << 5)	/* Transmit Data Request */
+#define LSR_BI			(1 << 4)	/* Break Interrupt */
+#define LSR_FE			(1 << 3)	/* Framing Error */
+#define LSR_PE			(1 << 2)	/* Parity Error */
+#define LSR_OE			(1 << 1)	/* Overrun Error */
+#define LSR_DR			(1 << 0)	/* Data Ready */
+
+#ifdef CONFIG_UART0
+struct uart_regs *uart = (struct uart_regs *) UART0_BASEADDR;
+struct uart_dl_regs *uart_dl = (struct uart_dl_regs *) UART0_BASEADDR;
+#else
+struct uart_regs * uart = (struct uart_regs *) UART1_BASEADDR;
+struct uart_dl_regs * uart_dl = (struct uart_dl_regs *) UART1_BASEADDR;
+#endif
+
+void serial_setbrg (void)
+{
+	int baudrate;
+	unsigned int reg;
+	unsigned int clk = SoC_clk_amba_get();
+
+	if ((baudrate = gd->baudrate) <= 0)
+		baudrate = CONFIG_BAUDRATE;
+
+	reg = clk / (baudrate * 16);
+	uart->lcr |= LCR_DLAB;			/* Enable Divisor Latch access */
+	uart_dl->dll = reg & 0xFF;		/* Set Divisor Latch Low */
+	uart_dl->dlh = (reg >> 8) & 0xFF;	/* Set Divisor Latch high */
+	uart->lcr &= ~LCR_DLAB;			/* Disable Divisor Latch access */
+}
+
+int serial_init (void)
+{
+#ifdef CONFIG_UART1
+	SoC_ioctrl_cfg(IOCTRL_UART1, 1);
+	SoC_ioctrl_cfg(IOCTRL_UART0, 0);
+#endif
+
+	uart->ier = 0x00;
+	uart->iir_fcr = 0x00;
+	uart->lcr = LCR_CHAR_LEN_8;
+
+	serial_setbrg ();
+
+	uart->data = 0;
+	uart->iir_fcr = FCR_RCVRRES | FCR_XMITRES | FCR_FIFOEN;
+
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	/* wait for room in the tx FIFO */
+	while ((uart->lsr & LSR_THRE) == 0) ;
+	uart->data = c;
+	if (c == '\n')
+		serial_putc ('\r');
+}
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+int serial_getc (void)
+{
+	while ((uart->lsr & LSR_DR) == 0);
+		return (char)uart->data & 0xff;
+}
+
+int serial_tstc (void)
+{
+	return uart->lsr & LSR_DR;
+}

cpu/arm920t/comcerto/serial.c

diff --git a/cpu/arm920t/comcerto/serial.c b/cpu/arm920t/comcerto/serial.c
new file mode 100644
index 0000000..54f7d84
--- /dev/null
+++ b/cpu/arm920t/comcerto/serial.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_COMCERTO_530
+
+#include "serial530.c"
+
+#else
+
+#include "serial-16550.c"
+
+#endif

cpu/arm920t/comcerto/serial530.c

diff --git a/cpu/arm920t/comcerto/serial530.c b/cpu/arm920t/comcerto/serial530.c
new file mode 100644
index 0000000..09596a1
--- /dev/null
+++ b/cpu/arm920t/comcerto/serial530.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+#if defined(CONFIG_UART0)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MCR_RXD_ENABLE		0x80
+#define MCR_TXD_ENABLE		0x40
+#define MCR_TIMER_SOURCE	0x20
+
+#define LCR_WLEN8		0x03	/* Wordlength: 8 bits */
+
+#define SSR_DR			0x01	/* Receiver data ready */
+#define SSR_THRE		0x20	/* Transmit-hold-register empty */
+
+#define FCR_TIMER_DIV_BYPASS	0x04
+
+void serial_setbrg (void)
+{
+	int baudrate;
+	unsigned int reg;
+	unsigned int clk = SoC_clk_amba_get();
+
+	if ((baudrate = gd->baudrate) <= 0)
+		baudrate = CONFIG_BAUDRATE;
+
+	reg = clk / (baudrate * 16);
+
+	(*(volatile u8 *)UART_RXD) = 0x0F;
+	(*(volatile u8 *)UART_TXD) = 0x0F;
+
+	SoC_timer1_set(reg);
+}
+
+int serial_init (void)
+{
+	serial_setbrg ();
+
+	(*(volatile u8 *)UART_FCR) = FCR_TIMER_DIV_BYPASS;
+	(*(volatile u8 *)UART_MCR) = MCR_RXD_ENABLE | MCR_TXD_ENABLE | MCR_TIMER_SOURCE;
+	(*(volatile u8 *)UART_LCR) = LCR_WLEN8;
+	(*(volatile u8 *)UART_IER) = 0x00;
+
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	/* wait for transmitter to empty */
+	while (!((*(volatile u8 *)UART_SSR) & SSR_THRE)) ;
+
+	(*(volatile u8 *)UART_THR) = c;
+
+	if (c == '\n')
+		serial_putc ('\r');
+}
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+int serial_getc (void)
+{
+	while (!((*(volatile u8 *)UART_SSR) & SSR_DR)) ;
+
+	return ((*(volatile u8 *)UART_RBR) & 0xff);
+}
+
+int serial_tstc (void)
+{
+	return ((*(volatile u8 *)UART_SSR) & SSR_DR);
+}
+
+#endif

cpu/arm920t/comcerto/spi.c

diff --git a/cpu/arm920t/comcerto/spi.c b/cpu/arm920t/comcerto/spi.c
new file mode 100644
index 0000000..20835a6
--- /dev/null
+++ b/cpu/arm920t/comcerto/spi.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2007
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Revision 0.3  2007/04/28 	Iurii.Golovach
+ */
+
+#include <common.h>
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+
+#include <spi.h>
+#include <asm/arch/bsp.h>
+#include <asm/arch/spi.h>
+
+spi_chipsel_type spi_chipsel[] = {
+	(spi_chipsel_type)1,
+	(spi_chipsel_type)2,
+	(spi_chipsel_type)4,
+	(spi_chipsel_type)8
+};
+
+int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
+
+void spi_hw_init(void)
+{
+	volatile u32 delay_count;
+
+	/* enable native SPI (disabled by default) */	
+	SoC_ioctrl_cfg(IOCTRL_SPI_BUS, 1);
+
+	/* wait 2 ms SPI to process the data. DON'T REMOVE THIS OTHERWISE SPI WILL NOT BE INITIALIZED */
+	delay_count = 4000;
+	while (delay_count--)
+		;
+}
+
+int  spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
+{
+	uchar j;
+	u32 tsmode;
+
+	if (bitlen < 1)
+		return 1;
+
+	/* checking the din and dout params */
+	if (!din && !dout)
+		return 2;
+
+	if (!chipsel)
+		return 3;
+
+	if (!din) {
+		/* transmit only */
+		tsmode = 0x1;
+	} else if (!dout) {
+		/* receive only */
+		tsmode = 0x2;
+	} else {
+		/* transmit & receive */
+		tsmode = 0x0;
+	}
+
+	/* disable SPI */
+	*(volatile u32 *) SPI_SSIENR = 0x0;
+
+	/* select the target chip */
+	*(volatile u32 *) SPI_SER = (volatile u32) *chipsel;
+
+	*(volatile u32 *) SPI_CTRLR0 = (((tsmode & 0x3) << 8) |
+					((CFG_SPI_CLOCK_POLARITY & 0x1) << 7) |
+					((CFG_SPI_CLOCK_PHASE & 0x1) << 6) |
+					((CFG_SPI_FRAMESIZE - 1) & 0xf));
+
+	/* set up the ssi_clk divider value */
+	*(volatile u32 *) SPI_BAUDR = (CFG_HZ_CLOCK / CFG_SPI_CLOCK_SPEED) & 0xFFFF;
+
+	/* disable SPI interrupts */
+	*(volatile u32 *) SPI_IMR = 0x0;
+
+	/* enable SPI */
+	*(volatile u32 *) SPI_SSIENR = 0x1;
+
+	switch (tsmode) {
+	case 0x1:
+		/* transmit only */
+
+		for (j = 0; j < bitlen / CFG_SPI_FRAMESIZE; j++) {
+			/* transmit fifo not full */
+			while(!((*(volatile u32 *) SPI_SR) & TFNF))
+				;
+
+			*(volatile u32 *) SPI_DR = *dout++;
+		}
+
+		/* waits while the data will be written (while TX FIFO isn't empty)  */
+		while(!((*(volatile u32 *) SPI_SR) & TFE))
+			;
+
+		break;
+
+	case 0x2:
+		/* receive only */
+
+		/* writing one dummy data word into the transmit FIFO */
+		*(volatile u32 *)SPI_DR = 0x00;
+
+		for (j = 0; j < bitlen / CFG_SPI_FRAMESIZE; j++)
+		{
+			/* check that there is data in the fifo */
+			while(!((*(volatile u32 *) SPI_SR) & RFNE))
+				;
+
+			*din++ = *(volatile u32 *) SPI_DR;
+		}
+
+		break;
+
+	default:
+		/* transmit & receive */
+
+		for (j = 0; j < bitlen / CFG_SPI_FRAMESIZE; j++) 
+		{
+			/* transmit fifo not full */
+			while(!((*(volatile u32 *) SPI_SR) & TFNF))
+				;
+
+			*(volatile u32 *) SPI_DR = *dout++;
+
+			/* check that there is data in the fifo */
+			while(!((*(volatile u32 *) SPI_SR) & RFNE))
+				;
+
+			*din++ = *(volatile u32 *) SPI_DR;
+		}
+
+		/* waits while the data will be written (while TX FIFO isn't empty)  */
+		while(!((*(volatile u32 *) SPI_SR) & TFE))
+			;
+
+		break;
+	}
+
+	return 0;
+}
+#endif /* (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI) */

cpu/arm920t/comcerto/usb_ohci.c

diff --git a/cpu/arm920t/comcerto/usb_ohci.c b/cpu/arm920t/comcerto/usb_ohci.c
new file mode 100644
index 0000000..dcb50ac
--- /dev/null
+++ b/cpu/arm920t/comcerto/usb_ohci.c
@@ -0,0 +1,1634 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200.
+ *
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
+ *
+ * Note: Much of this code has been derived from Linux 2.4
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell
+ *
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com - based on s3c24x0's driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/*
+ * IMPORTANT NOTES
+ * 1 - you MUST define LITTLEENDIAN in the configuration file for the
+ *     board or this driver will NOT work!
+ * 2 - this driver is intended for use with USB Mass Storage Devices
+ *     (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
+ * 3 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
+ *     to activate workaround for bug #41 or this driver will NOT work!
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_USB_OHCI
+
+#include <asm/arch/hardware.h>
+
+#include <malloc.h>
+#include <usb.h>
+#include "usb_ohci.h"
+
+#define OHCI_USE_NPS		/* force NoPowerSwitching mode */
+#undef OHCI_VERBOSE_DEBUG	/* not always helpful */
+
+/* For initializing controller (mask in an HCFS mode too) */
+#define OHCI_CONTROL_INIT \
+	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
+
+#define readl(a) (*((vu_long *)(a)))
+#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
+
+#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+
+#undef DEBUG
+#ifdef DEBUG
+#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
+#else
+#define dbg(format, arg...) do {} while(0)
+#endif /* DEBUG */
+#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
+#undef SHOW_INFO
+#ifdef SHOW_INFO
+#define info(format, arg...) printf("INFO: " format "\n", ## arg)
+#else
+#define info(format, arg...) do {} while(0)
+#endif
+
+#define m16_swap(x) swap_16(x)
+#define m32_swap(x) swap_32(x)
+
+/* global ohci_t */
+static ohci_t gohci;
+/* this must be aligned to a 256 byte boundary */
+struct ohci_hcca ghcca[1];
+/* a pointer to the aligned storage */
+struct ohci_hcca *phcca;
+/* this allocates EDs for all possible endpoints */
+struct ohci_device ohci_dev;
+/* urb_priv */
+urb_priv_t urb_priv;
+/* RHSC flag */
+int got_rhsc;
+/* device which was disconnected */
+struct usb_device *devgone;
+
+/*-------------------------------------------------------------------------*/
+
+/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
+ * The erratum (#4) description is incorrect.  AMD's workaround waits
+ * till some bits (mostly reserved) are clear; ok for all revs.
+ */
+#define OHCI_QUIRK_AMD756 0xabcd
+#define read_roothub(hc, register, mask) ({ \
+	u32 temp = readl (&hc->regs->roothub.register); \
+	if (hc->flags & OHCI_QUIRK_AMD756) \
+		while (temp & mask) \
+			temp = readl (&hc->regs->roothub.register); \
+	temp; })
+
+static u32 roothub_a (struct ohci *hc)
+	{ return read_roothub (hc, a, 0xfc0fe000); }
+static inline u32 roothub_b (struct ohci *hc)
+	{ return readl (&hc->regs->roothub.b); }
+static inline u32 roothub_status (struct ohci *hc)
+	{ return readl (&hc->regs->roothub.status); }
+static u32 roothub_portstatus (struct ohci *hc, int i)
+	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+
+
+/* forward declaration */
+static int hc_interrupt (void);
+static void
+td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
+	int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
+
+/*-------------------------------------------------------------------------*
+ * URB support functions
+ *-------------------------------------------------------------------------*/
+
+/* free HCD-private data associated with this URB */
+
+static void urb_free_priv (urb_priv_t * urb)
+{
+	int		i;
+	int		last;
+	struct td	* td;
+
+	last = urb->length - 1;
+	if (last >= 0) {
+		for (i = 0; i <= last; i++) {
+			td = urb->td[i];
+			if (td) {
+				td->usb_dev = NULL;
+				urb->td[i] = NULL;
+			}
+		}
+	}
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+static int sohci_get_current_frame_number (struct usb_device * dev);
+
+/* debug| print the main components of an URB
+ * small: 0) header + data packets 1) just header */
+
+static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
+	int transfer_len, struct devrequest * setup, char * str, int small)
+{
+	urb_priv_t * purb = &urb_priv;
+
+	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
+			str,
+			sohci_get_current_frame_number (dev),
+			usb_pipedevice (pipe),
+			usb_pipeendpoint (pipe),
+			usb_pipeout (pipe)? 'O': 'I',
+			usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
+				(usb_pipecontrol (pipe)? "CTRL": "BULK"),
+			purb->actual_length,
+			transfer_len, dev->status);
+#ifdef	OHCI_VERBOSE_DEBUG
+	if (!small) {
+		int i, len;
+
+		if (usb_pipecontrol (pipe)) {
+			printf (__FILE__ ": cmd(8):");
+			for (i = 0; i < 8 ; i++)
+				printf (" %02x", ((__u8 *) setup) [i]);
+			printf ("\n");
+		}
+		if (transfer_len > 0 && buffer) {
+			printf (__FILE__ ": data(%d/%d):",
+				purb->actual_length,
+				transfer_len);
+			len = usb_pipeout (pipe)?
+					transfer_len: purb->actual_length;
+			for (i = 0; i < 16 && i < len; i++)
+				printf (" %02x", ((__u8 *) buffer) [i]);
+			printf ("%s\n", i < len? "...": "");
+		}
+	}
+#endif
+}
+
+/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
+void ep_print_int_eds (ohci_t *ohci, char * str) {
+	int i, j;
+	 __u32 * ed_p;
+	for (i= 0; i < 32; i++) {
+		j = 5;
+		ed_p = &(ohci->hcca->int_table [i]);
+		if (*ed_p == 0)
+		    continue;
+		printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
+		while (*ed_p != 0 && j--) {
+			ed_t *ed = (ed_t *)m32_swap(ed_p);
+			printf (" ed: %4x;", ed->hwINFO);
+			ed_p = &ed->hwNextED;
+		}
+		printf ("\n");
+	}
+}
+
+static void ohci_dump_intr_mask (char *label, __u32 mask)
+{
+	dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
+		label,
+		mask,
+		(mask & OHCI_INTR_MIE) ? " MIE" : "",
+		(mask & OHCI_INTR_OC) ? " OC" : "",
+		(mask & OHCI_INTR_RHSC) ? " RHSC" : "",
+		(mask & OHCI_INTR_FNO) ? " FNO" : "",
+		(mask & OHCI_INTR_UE) ? " UE" : "",
+		(mask & OHCI_INTR_RD) ? " RD" : "",
+		(mask & OHCI_INTR_SF) ? " SF" : "",
+		(mask & OHCI_INTR_WDH) ? " WDH" : "",
+		(mask & OHCI_INTR_SO) ? " SO" : ""
+		);
+}
+
+static void maybe_print_eds (char *label, __u32 value)
+{
+	ed_t *edp = (ed_t *)value;
+
+	if (value) {
+		dbg ("%s %08x", label, value);
+		dbg ("%08x", edp->hwINFO);
+		dbg ("%08x", edp->hwTailP);
+		dbg ("%08x", edp->hwHeadP);
+		dbg ("%08x", edp->hwNextED);
+	}
+}
+
+static char * hcfs2string (int state)
+{
+	switch (state) {
+		case OHCI_USB_RESET:	return "reset";
+		case OHCI_USB_RESUME:	return "resume";
+		case OHCI_USB_OPER:	return "operational";
+		case OHCI_USB_SUSPEND:	return "suspend";
+	}
+	return "?";
+}
+
+/* dump control and status registers */
+static void ohci_dump_status (ohci_t *controller)
+{
+	struct ohci_regs	*regs = controller->regs;
+	__u32			temp;
+
+	temp = readl (&regs->revision) & 0xff;
+	if (temp != 0x10)
+		dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
+
+	temp = readl (&regs->control);
+	dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
+		(temp & OHCI_CTRL_RWE) ? " RWE" : "",
+		(temp & OHCI_CTRL_RWC) ? " RWC" : "",
+		(temp & OHCI_CTRL_IR) ? " IR" : "",
+		hcfs2string (temp & OHCI_CTRL_HCFS),
+		(temp & OHCI_CTRL_BLE) ? " BLE" : "",
+		(temp & OHCI_CTRL_CLE) ? " CLE" : "",
+		(temp & OHCI_CTRL_IE) ? " IE" : "",
+		(temp & OHCI_CTRL_PLE) ? " PLE" : "",
+		temp & OHCI_CTRL_CBSR
+		);
+
+	temp = readl (&regs->cmdstatus);
+	dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
+		(temp & OHCI_SOC) >> 16,
+		(temp & OHCI_OCR) ? " OCR" : "",
+		(temp & OHCI_BLF) ? " BLF" : "",
+		(temp & OHCI_CLF) ? " CLF" : "",
+		(temp & OHCI_HCR) ? " HCR" : ""
+		);
+
+	ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
+	ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
+
+	maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
+
+	maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
+	maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
+
+	maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
+	maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
+
+	maybe_print_eds ("donehead", readl (&regs->donehead));
+}
+
+static void ohci_dump_roothub (ohci_t *controller, int verbose)
+{
+	__u32			temp, ndp, i;
+
+	temp = roothub_a (controller);
+	ndp = (temp & RH_A_NDP);
+#ifdef CONFIG_AT91C_PQFP_UHPBUG
+	ndp = (ndp == 2) ? 1:0;
+#endif
+	if (verbose) {
+		dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
+			((temp & RH_A_POTPGT) >> 24) & 0xff,
+			(temp & RH_A_NOCP) ? " NOCP" : "",
+			(temp & RH_A_OCPM) ? " OCPM" : "",
+			(temp & RH_A_DT) ? " DT" : "",
+			(temp & RH_A_NPS) ? " NPS" : "",
+			(temp & RH_A_PSM) ? " PSM" : "",
+			ndp
+			);
+		temp = roothub_b (controller);
+		dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
+			temp,
+			(temp & RH_B_PPCM) >> 16,
+			(temp & RH_B_DR)
+			);
+		temp = roothub_status (controller);
+		dbg ("roothub.status: %08x%s%s%s%s%s%s",
+			temp,
+			(temp & RH_HS_CRWE) ? " CRWE" : "",
+			(temp & RH_HS_OCIC) ? " OCIC" : "",
+			(temp & RH_HS_LPSC) ? " LPSC" : "",
+			(temp & RH_HS_DRWE) ? " DRWE" : "",
+			(temp & RH_HS_OCI) ? " OCI" : "",
+			(temp & RH_HS_LPS) ? " LPS" : ""
+			);
+	}
+
+	for (i = 0; i < ndp; i++) {
+		temp = roothub_portstatus (controller, i);
+		dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
+			i,
+			temp,
+			(temp & RH_PS_PRSC) ? " PRSC" : "",
+			(temp & RH_PS_OCIC) ? " OCIC" : "",
+			(temp & RH_PS_PSSC) ? " PSSC" : "",
+			(temp & RH_PS_PESC) ? " PESC" : "",
+			(temp & RH_PS_CSC) ? " CSC" : "",
+
+			(temp & RH_PS_LSDA) ? " LSDA" : "",
+			(temp & RH_PS_PPS) ? " PPS" : "",
+			(temp & RH_PS_PRS) ? " PRS" : "",
+			(temp & RH_PS_POCI) ? " POCI" : "",
+			(temp & RH_PS_PSS) ? " PSS" : "",
+
+			(temp & RH_PS_PES) ? " PES" : "",
+			(temp & RH_PS_CCS) ? " CCS" : ""
+			);
+	}
+}
+
+static void ohci_dump (ohci_t *controller, int verbose)
+{
+	dbg ("OHCI controller usb-%s state", controller->slot_name);
+
+	/* dumps some of the state we know about */
+	ohci_dump_status (controller);
+	if (verbose)
+		ep_print_int_eds (controller, "hcca");
+	dbg ("hcca frame #%04x", controller->hcca->frame_no);
+	ohci_dump_roothub (controller, 1);
+}
+
+
+#endif /* DEBUG */
+
+/*-------------------------------------------------------------------------*
+ * Interface functions (URB)
+ *-------------------------------------------------------------------------*/
+
+/* get a transfer request */
+
+int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
+		int transfer_len, struct devrequest *setup, int interval)
+{
+	ohci_t *ohci;
+	ed_t * ed;
+	urb_priv_t *purb_priv;
+	int i, size = 0;
+
+	ohci = &gohci;
+
+	/* when controller's hung, permit only roothub cleanup attempts
+	 * such as powering down ports */
+	if (ohci->disabled) {
+		err("sohci_submit_job: EPIPE");
+		return -1;
+	}
+
+	/* every endpoint has a ed, locate and fill it */
+	if (!(ed = ep_add_ed (dev, pipe))) {
+		err("sohci_submit_job: ENOMEM");
+		return -1;
+	}
+
+	/* for the private part of the URB we need the number of TDs (size) */
+	switch (usb_pipetype (pipe)) {
+		case PIPE_BULK: /* one TD for every 4096 Byte */
+			size = (transfer_len - 1) / 4096 + 1;
+			break;
+		case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
+			size = (transfer_len == 0)? 2:
+						(transfer_len - 1) / 4096 + 3;
+			break;
+	}
+
+	if (size >= (N_URB_TD - 1)) {
+		err("need %d TDs, only have %d", size, N_URB_TD);
+		return -1;
+	}
+	purb_priv = &urb_priv;
+	purb_priv->pipe = pipe;
+
+	/* fill the private part of the URB */
+	purb_priv->length = size;
+	purb_priv->ed = ed;
+	purb_priv->actual_length = 0;
+
+	/* allocate the TDs */
+	/* note that td[0] was allocated in ep_add_ed */
+	for (i = 0; i < size; i++) {
+		purb_priv->td[i] = td_alloc (dev);
+		if (!purb_priv->td[i]) {
+			purb_priv->length = i;
+			urb_free_priv (purb_priv);
+			err("sohci_submit_job: ENOMEM");
+			return -1;
+		}
+	}
+
+	if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
+		urb_free_priv (purb_priv);
+		err("sohci_submit_job: EINVAL");
+		return -1;
+	}
+
+	/* link the ed into a chain if is not already */
+	if (ed->state != ED_OPER)
+		ep_link (ohci, ed);
+
+	/* fill the TDs and link it to the ed */
+	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
+
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+/* tell us the current USB frame number */
+
+static int sohci_get_current_frame_number (struct usb_device *usb_dev)
+{
+	ohci_t *ohci = &gohci;
+
+	return m16_swap (ohci->hcca->frame_no);
+}
+#endif
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* link an ed into one of the HC chains */
+
+static int ep_link (ohci_t *ohci, ed_t *edi)
+{
+	volatile ed_t *ed = edi;
+
+	ed->state = ED_OPER;
+
+	switch (ed->type) {
+	case PIPE_CONTROL:
+		ed->hwNextED = 0;
+		if (ohci->ed_controltail == NULL) {
+			writel (ed, &ohci->regs->ed_controlhead);
+		} else {
+			ohci->ed_controltail->hwNextED = m32_swap (ed);
+		}
+		ed->ed_prev = ohci->ed_controltail;
+		if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
+			!ohci->ed_rm_list[1] && !ohci->sleeping) {
+			ohci->hc_control |= OHCI_CTRL_CLE;
+			writel (ohci->hc_control, &ohci->regs->control);
+		}
+		ohci->ed_controltail = edi;
+		break;
+
+	case PIPE_BULK:
+		ed->hwNextED = 0;
+		if (ohci->ed_bulktail == NULL) {
+			writel (ed, &ohci->regs->ed_bulkhead);
+		} else {
+			ohci->ed_bulktail->hwNextED = m32_swap (ed);
+		}
+		ed->ed_prev = ohci->ed_bulktail;
+		if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
+			!ohci->ed_rm_list[1] && !ohci->sleeping) {
+			ohci->hc_control |= OHCI_CTRL_BLE;
+			writel (ohci->hc_control, &ohci->regs->control);
+		}
+		ohci->ed_bulktail = edi;
+		break;
+	}
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* unlink an ed from one of the HC chains.
+ * just the link to the ed is unlinked.
+ * the link from the ed still points to another operational ed or 0
+ * so the HC can eventually finish the processing of the unlinked ed */
+
+static int ep_unlink (ohci_t *ohci, ed_t *ed)
+{
+	ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
+
+	switch (ed->type) {
+	case PIPE_CONTROL:
+		if (ed->ed_prev == NULL) {
+			if (!ed->hwNextED) {
+				ohci->hc_control &= ~OHCI_CTRL_CLE;
+				writel (ohci->hc_control, &ohci->regs->control);
+			}
+			writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
+		} else {
+			ed->ed_prev->hwNextED = ed->hwNextED;
+		}
+		if (ohci->ed_controltail == ed) {
+			ohci->ed_controltail = ed->ed_prev;
+		} else {
+			((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+		}
+		break;
+
+	case PIPE_BULK:
+		if (ed->ed_prev == NULL) {
+			if (!ed->hwNextED) {
+				ohci->hc_control &= ~OHCI_CTRL_BLE;
+				writel (ohci->hc_control, &ohci->regs->control);
+			}
+			writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
+		} else {
+			ed->ed_prev->hwNextED = ed->hwNextED;
+		}
+		if (ohci->ed_bulktail == ed) {
+			ohci->ed_bulktail = ed->ed_prev;
+		} else {
+			((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+		}
+		break;
+	}
+	ed->state = ED_UNLINK;
+	return 0;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
+ * but the USB stack is a little bit stateless	so we do it at every transaction
+ * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
+ * in all other cases the state is left unchanged
+ * the ed info fields are setted anyway even though most of them should not change */
+
+static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
+{
+	td_t *td;
+	ed_t *ed_ret;
+	volatile ed_t *ed;
+
+	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
+			(usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
+
+	if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
+		err("ep_add_ed: pending delete");
+		/* pending delete request */
+		return NULL;
+	}
+
+	if (ed->state == ED_NEW) {
+		ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
+		/* dummy td; end of td list for ed */
+		td = td_alloc (usb_dev);
+		ed->hwTailP = m32_swap (td);
+		ed->hwHeadP = ed->hwTailP;
+		ed->state = ED_UNLINK;
+		ed->type = usb_pipetype (pipe);
+		ohci_dev.ed_cnt++;
+	}
+
+	ed->hwINFO = m32_swap (usb_pipedevice (pipe)
+			| usb_pipeendpoint (pipe) << 7
+			| (usb_pipeisoc (pipe)? 0x8000: 0)
+			| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
+			| usb_pipeslow (pipe) << 13
+			| usb_maxpacket (usb_dev, pipe) << 16);
+
+	return ed_ret;
+}
+
+/*-------------------------------------------------------------------------*
+ * TD handling functions
+ *-------------------------------------------------------------------------*/
+
+/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
+
+static void td_fill (ohci_t *ohci, unsigned int info,
+	void *data, int len,
+	struct usb_device *dev, int index, urb_priv_t *urb_priv)
+{
+	volatile td_t  *td, *td_pt;
+#ifdef OHCI_FILL_TRACE
+	int i;
+#endif
+
+	if (index > urb_priv->length) {
+		err("index > length");
+		return;
+	}
+	/* use this td as the next dummy */
+	td_pt = urb_priv->td [index];
+	td_pt->hwNextTD = 0;
+
+	/* fill the old dummy TD */
+	td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
+
+	td->ed = urb_priv->ed;
+	td->next_dl_td = NULL;
+	td->index = index;
+	td->data = (__u32)data;
+#ifdef OHCI_FILL_TRACE
+	if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
+		for (i = 0; i < len; i++)
+		printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
+		printf("\n");
+	}
+#endif
+	if (!len)
+		data = 0;
+
+	td->hwINFO = m32_swap (info);
+	td->hwCBP = m32_swap (data);
+	if (data)
+		td->hwBE = m32_swap (data + len - 1);
+	else
+		td->hwBE = 0;
+	td->hwNextTD = m32_swap (td_pt);
+	td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
+
+	/* append to queue */
+	td->ed->hwTailP = td->hwNextTD;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* prepare all TDs of a transfer */
+
+static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
+	int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
+{
+	ohci_t *ohci = &gohci;
+	int data_len = transfer_len;
+	void *data;
+	int cnt = 0;
+	__u32 info = 0;
+	unsigned int toggle = 0;
+
+	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
+	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+		toggle = TD_T_TOGGLE;
+	} else {
+		toggle = TD_T_DATA0;
+		usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
+	}
+	urb->td_cnt = 0;
+	if (data_len)
+		data = buffer;
+	else
+		data = 0;
+
+	switch (usb_pipetype (pipe)) {
+	case PIPE_BULK:
+		info = usb_pipeout (pipe)?
+			TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
+		while(data_len > 4096) {
+			td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
+			data += 4096; data_len -= 4096; cnt++;
+		}
+		info = usb_pipeout (pipe)?
+			TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
+		td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
+		cnt++;
+
+		if (!ohci->sleeping)
+			writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
+		break;
+
+	case PIPE_CONTROL:
+		info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
+		td_fill (ohci, info, setup, 8, dev, cnt++, urb);
+		if (data_len > 0) {
+			info = usb_pipeout (pipe)?
+				TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
+			/* NOTE:  mishandles transfers >8K, some >4K */
+			td_fill (ohci, info, data, data_len, dev, cnt++, urb);
+		}
+		info = usb_pipeout (pipe)?
+			TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
+		td_fill (ohci, info, data, 0, dev, cnt++, urb);
+		if (!ohci->sleeping)
+			writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
+		break;
+	}
+	if (urb->length != cnt)
+		dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
+}
+
+/*-------------------------------------------------------------------------*
+ * Done List handling functions
+ *-------------------------------------------------------------------------*/
+
+
+/* calculate the transfer length and update the urb */
+
+static void dl_transfer_length(td_t * td)
+{
+	__u32 tdINFO, tdBE, tdCBP;
+	urb_priv_t *lurb_priv = &urb_priv;
+
+	tdINFO = m32_swap (td->hwINFO);
+	tdBE   = m32_swap (td->hwBE);
+	tdCBP  = m32_swap (td->hwCBP);
+
+
+	if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
+	    ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
+		if (tdBE != 0) {
+			if (td->hwCBP == 0)
+				lurb_priv->actual_length += tdBE - td->data + 1;
+			else
+				lurb_priv->actual_length += tdCBP - td->data;
+		}
+	}
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* replies to the request have to be on a FIFO basis so
+ * we reverse the reversed done-list */
+
+static td_t * dl_reverse_done_list (ohci_t *ohci)
+{
+	__u32 td_list_hc;
+	td_t *td_rev = NULL;
+	td_t *td_list = NULL;
+	urb_priv_t *lurb_priv = NULL;
+
+	td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
+	ohci->hcca->done_head = 0;
+
+	while (td_list_hc) {
+		td_list = (td_t *)td_list_hc;
+
+		if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
+			lurb_priv = &urb_priv;
+			dbg(" USB-error/status: %x : %p",
+					TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
+			if (td_list->ed->hwHeadP & m32_swap (0x1)) {
+				if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
+					td_list->ed->hwHeadP =
+						(lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
+									(td_list->ed->hwHeadP & m32_swap (0x2));
+					lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
+				} else
+					td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
+			}
+		}
+
+		td_list->next_dl_td = td_rev;
+		td_rev = td_list;
+		td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
+	}
+	return td_list;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* td done list */
+static int dl_done_list (ohci_t *ohci, td_t *td_list)
+{
+	td_t *td_list_next = NULL;
+	ed_t *ed;
+	int cc = 0;
+	int stat = 0;
+	/* urb_t *urb; */
+	urb_priv_t *lurb_priv;
+	__u32 tdINFO, edHeadP, edTailP;
+
+	while (td_list) {
+		td_list_next = td_list->next_dl_td;
+
+		lurb_priv = &urb_priv;
+		tdINFO = m32_swap (td_list->hwINFO);
+
+		ed = td_list->ed;
+
+		dl_transfer_length(td_list);
+
+		/* error code of transfer */
+		cc = TD_CC_GET (tdINFO);
+		if (cc != 0) {
+			dbg("ConditionCode %#x", cc);
+			stat = cc_to_error[cc];
+		}
+
+		if (ed->state != ED_NEW) {
+			edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
+			edTailP = m32_swap (ed->hwTailP);
+
+			/* unlink eds if they are not busy */
+			if ((edHeadP == edTailP) && (ed->state == ED_OPER))
+				ep_unlink (ohci, ed);
+		}
+
+		td_list = td_list_next;
+	}
+	return stat;
+}
+
+/*-------------------------------------------------------------------------*
+ * Virtual Root Hub
+ *-------------------------------------------------------------------------*/
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] =
+{
+	0x12,	    /*	__u8  bLength; */
+	0x01,	    /*	__u8  bDescriptorType; Device */
+	0x10,	    /*	__u16 bcdUSB; v1.1 */
+	0x01,
+	0x09,	    /*	__u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,	    /*	__u8  bDeviceSubClass; */
+	0x00,	    /*	__u8  bDeviceProtocol; */
+	0x08,	    /*	__u8  bMaxPacketSize0; 8 Bytes */
+	0x00,	    /*	__u16 idVendor; */
+	0x00,
+	0x00,	    /*	__u16 idProduct; */
+	0x00,
+	0x00,	    /*	__u16 bcdDevice; */
+	0x00,
+	0x00,	    /*	__u8  iManufacturer; */
+	0x01,	    /*	__u8  iProduct; */
+	0x00,	    /*	__u8  iSerialNumber; */
+	0x01	    /*	__u8  bNumConfigurations; */
+};
+
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] =
+{
+	0x09,	    /*	__u8  bLength; */
+	0x02,	    /*	__u8  bDescriptorType; Configuration */
+	0x19,	    /*	__u16 wTotalLength; */
+	0x00,
+	0x01,	    /*	__u8  bNumInterfaces; */
+	0x01,	    /*	__u8  bConfigurationValue; */
+	0x00,	    /*	__u8  iConfiguration; */
+	0x40,	    /*	__u8  bmAttributes;
+		 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+	0x00,	    /*	__u8  MaxPower; */
+
+	/* interface */
+	0x09,	    /*	__u8  if_bLength; */
+	0x04,	    /*	__u8  if_bDescriptorType; Interface */
+	0x00,	    /*	__u8  if_bInterfaceNumber; */
+	0x00,	    /*	__u8  if_bAlternateSetting; */
+	0x01,	    /*	__u8  if_bNumEndpoints; */
+	0x09,	    /*	__u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,	    /*	__u8  if_bInterfaceSubClass; */
+	0x00,	    /*	__u8  if_bInterfaceProtocol; */
+	0x00,	    /*	__u8  if_iInterface; */
+
+	/* endpoint */
+	0x07,	    /*	__u8  ep_bLength; */
+	0x05,	    /*	__u8  ep_bDescriptorType; Endpoint */
+	0x81,	    /*	__u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,	    /*	__u8  ep_bmAttributes; Interrupt */
+	0x02,	    /*	__u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+	0x00,
+	0xff	    /*	__u8  ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+	0x04,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	0x09,			/*  __u8  lang ID */
+	0x04,			/*  __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+	28,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	'O',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'C',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'I',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'R',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	't',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'u',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'b',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+};
+
+/* Hub class-specific descriptor is constructed dynamically */
+
+
+/*-------------------------------------------------------------------------*/
+
+#define OK(x)			len = (x); break
+#ifdef DEBUG
+#define WR_RH_STAT(x)		{info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
+#define WR_RH_PORTSTAT(x)	{info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
+#else
+#define WR_RH_STAT(x)		writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x)	writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
+#endif
+#define RD_RH_STAT		roothub_status(&gohci)
+#define RD_RH_PORTSTAT		roothub_portstatus(&gohci,wIndex-1)
+
+/* request to virtual root hub */
+
+int rh_check_port_status(ohci_t *controller)
+{
+	__u32 temp, ndp, i;
+	int res;
+
+	res = -1;
+	temp = roothub_a (controller);
+	ndp = (temp & RH_A_NDP);
+#ifdef CONFIG_AT91C_PQFP_UHPBUG
+	ndp = (ndp == 2) ? 1:0;
+#endif
+
+	for (i = 0; i < ndp; i++) {
+		temp = roothub_portstatus (controller, i);
+		/* check for a device disconnect */
+		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+			(RH_PS_PESC | RH_PS_CSC)) &&
+			((temp & RH_PS_CCS) == 0)) {
+			res = i;
+			break;
+		}
+	}
+	return res;
+}
+
+static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+		void *buffer, int transfer_len, struct devrequest *cmd)
+{
+	void * data = buffer;
+	int leni = transfer_len;
+	int len = 0;
+	int stat = 0;
+	__u32 datab[4];
+	__u8 *data_buf = (__u8 *)datab;
+	__u16 bmRType_bReq;
+	__u16 wValue;
+	__u16 wIndex;
+	__u16 wLength;
+
+#ifdef DEBUG
+urb_priv.actual_length = 0;
+pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
+#else
+	wait_ms(1);
+#endif
+	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+		info("Root-Hub submit IRQ: NOT implemented");
+		return 0;
+	}
+
+	bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
+	wValue	      = m16_swap (cmd->value);
+	wIndex	      = m16_swap (cmd->index);
+	wLength	      = m16_swap (cmd->length);
+
+	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
+		dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
+
+	switch (bmRType_bReq) {
+	/* Request Destination:
+	   without flags: Device,
+	   RH_INTERFACE: interface,
+	   RH_ENDPOINT: endpoint,
+	   RH_CLASS means HUB here,
+	   RH_OTHER | RH_CLASS	almost ever means HUB_PORT here
+	*/
+
+	case RH_GET_STATUS:
+			*(__u16 *) data_buf = m16_swap (1); OK (2);
+	case RH_GET_STATUS | RH_INTERFACE:
+			*(__u16 *) data_buf = m16_swap (0); OK (2);
+	case RH_GET_STATUS | RH_ENDPOINT:
+			*(__u16 *) data_buf = m16_swap (0); OK (2);
+	case RH_GET_STATUS | RH_CLASS:
+			*(__u32 *) data_buf = m32_swap (
+				RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
+			OK (4);
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+			*(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
+
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		switch (wValue) {
+			case (RH_ENDPOINT_STALL): OK (0);
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		switch (wValue) {
+			case RH_C_HUB_LOCAL_POWER:
+				OK(0);
+			case (RH_C_HUB_OVER_CURRENT):
+					WR_RH_STAT(RH_HS_OCIC); OK (0);
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		switch (wValue) {
+			case (RH_PORT_ENABLE):
+					WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
+			case (RH_PORT_SUSPEND):
+					WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
+			case (RH_PORT_POWER):
+					WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
+			case (RH_C_PORT_CONNECTION):
+					WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
+			case (RH_C_PORT_ENABLE):
+					WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
+			case (RH_C_PORT_SUSPEND):
+					WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
+			case (RH_C_PORT_OVER_CURRENT):
+					WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
+			case (RH_C_PORT_RESET):
+					WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
+		}
+		break;
+
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		switch (wValue) {
+			case (RH_PORT_SUSPEND):
+					WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
+			case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
+					if (RD_RH_PORTSTAT & RH_PS_CCS)
+					    WR_RH_PORTSTAT (RH_PS_PRS);
+					OK (0);
+			case (RH_PORT_POWER):
+					WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
+			case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
+					if (RD_RH_PORTSTAT & RH_PS_CCS)
+					    WR_RH_PORTSTAT (RH_PS_PES );
+					OK (0);
+		}
+		break;
+
+	case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
+
+	case RH_GET_DESCRIPTOR:
+		switch ((wValue & 0xff00) >> 8) {
+			case (0x01): /* device descriptor */
+				len = min_t(unsigned int,
+					  leni,
+					  min_t(unsigned int,
+					      sizeof (root_hub_dev_des),
+					      wLength));
+				data_buf = root_hub_dev_des; OK(len);
+			case (0x02): /* configuration descriptor */
+				len = min_t(unsigned int,
+					  leni,
+					  min_t(unsigned int,
+					      sizeof (root_hub_config_des),
+					      wLength));
+				data_buf = root_hub_config_des; OK(len);
+			case (0x03): /* string descriptors */
+				if(wValue==0x0300) {
+					len = min_t(unsigned int,
+						  leni,
+						  min_t(unsigned int,
+						      sizeof (root_hub_str_index0),
+						      wLength));
+					data_buf = root_hub_str_index0;
+					OK(len);
+				}
+				if(wValue==0x0301) {
+					len = min_t(unsigned int,
+						  leni,
+						  min_t(unsigned int,
+						      sizeof (root_hub_str_index1),
+						      wLength));
+					data_buf = root_hub_str_index1;
+					OK(len);
+			}
+			default:
+				stat = USB_ST_STALLED;
+		}
+		break;
+
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+	{
+		__u32 temp = roothub_a (&gohci);
+
+		data_buf [0] = 9;		/* min length; */
+		data_buf [1] = 0x29;
+		data_buf [2] = temp & RH_A_NDP;
+#ifdef CONFIG_AT91C_PQFP_UHPBUG
+		data_buf [2] = (data_buf [2] == 2) ? 1:0;
+#endif
+		data_buf [3] = 0;
+		if (temp & RH_A_PSM)	/* per-port power switching? */
+			data_buf [3] |= 0x1;
+		if (temp & RH_A_NOCP)	/* no overcurrent reporting? */
+			data_buf [3] |= 0x10;
+		else if (temp & RH_A_OCPM)	/* per-port overcurrent reporting? */
+			data_buf [3] |= 0x8;
+
+		/* corresponds to data_buf[4-7] */
+		datab [1] = 0;
+		data_buf [5] = (temp & RH_A_POTPGT) >> 24;
+		temp = roothub_b (&gohci);
+		data_buf [7] = temp & RH_B_DR;
+		if (data_buf [2] < 7) {
+			data_buf [8] = 0xff;
+		} else {
+			data_buf [0] += 2;
+			data_buf [8] = (temp & RH_B_DR) >> 8;
+			data_buf [10] = data_buf [9] = 0xff;
+		}
+
+		len = min_t(unsigned int, leni,
+		min_t(unsigned int, data_buf [0], wLength));
+		OK (len);
+	}
+
+	case RH_GET_CONFIGURATION:	*(__u8 *) data_buf = 0x01; OK (1);
+
+	case RH_SET_CONFIGURATION:	WR_RH_STAT (0x10000); OK (0);
+
+	default:
+		dbg ("unsupported root hub command");
+		stat = USB_ST_STALLED;
+	}
+
+#ifdef	DEBUG
+	ohci_dump_roothub (&gohci, 1);
+#else
+	wait_ms(1);
+#endif
+
+	len = min_t(int, len, leni);
+	if (data != data_buf)
+	    memcpy (data, data_buf, len);
+	dev->act_len = len;
+	dev->status = stat;
+
+#ifdef DEBUG
+	if (transfer_len)
+		urb_priv.actual_length = transfer_len;
+	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
+#else
+	wait_ms(1);
+#endif
+
+	return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* common code for handling submit messages - used for all but root hub */
+/* accesses. */
+int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		int transfer_len, struct devrequest *setup, int interval)
+{
+	int stat = 0;
+	int maxsize = usb_maxpacket(dev, pipe);
+	int timeout;
+
+	/* device pulled? Shortcut the action. */
+	if (devgone == dev) {
+		dev->status = USB_ST_CRC_ERR;
+		return 0;
+	}
+
+#ifdef DEBUG
+	urb_priv.actual_length = 0;
+	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+	wait_ms(1);
+#endif
+	if (!maxsize) {
+		err("submit_common_message: pipesize for pipe %lx is zero",
+			pipe);
+		return -1;
+	}
+
+	if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
+		err("sohci_submit_job failed");
+		return -1;
+	}
+
+	wait_ms(10);
+	/* ohci_dump_status(&gohci); */
+
+	/* allow more time for a BULK device to react - some are slow */
+#define BULK_TO	 5000	/* timeout in milliseconds */
+	if (usb_pipetype (pipe) == PIPE_BULK)
+		timeout = BULK_TO;
+	else
+		timeout = 100;
+
+	/* wait for it to complete */
+	for (;;) {
+		/* check whether the controller is done */
+		stat = hc_interrupt();
+		if (stat < 0) {
+			stat = USB_ST_CRC_ERR;
+			break;
+		}
+		if (stat >= 0 && stat != 0xff) {
+			/* 0xff is returned for an SF-interrupt */
+			break;
+		}
+		if (--timeout) {
+			wait_ms(1);
+		} else {
+			err("CTL:TIMEOUT ");
+			stat = USB_ST_CRC_ERR;
+			break;
+		}
+	}
+	/* we got an Root Hub Status Change interrupt */
+	if (got_rhsc) {
+#ifdef DEBUG
+		ohci_dump_roothub (&gohci, 1);
+#endif
+		got_rhsc = 0;
+		/* abuse timeout */
+		timeout = rh_check_port_status(&gohci);
+		if (timeout >= 0) {
+#if 0 /* this does nothing useful, but leave it here in case that changes */
+			/* the called routine adds 1 to the passed value */
+			usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
+#endif
+			/*
+			 * XXX
+			 * This is potentially dangerous because it assumes
+			 * that only one device is ever plugged in!
+			 */
+			devgone = dev;
+		}
+	}
+
+	dev->status = stat;
+	dev->act_len = transfer_len;
+
+#ifdef DEBUG
+	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
+#else
+	wait_ms(1);
+#endif
+
+	/* free TDs in urb_priv */
+	urb_free_priv (&urb_priv);
+	return 0;
+}
+
+/* submit routines called from usb.c */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		int transfer_len)
+{
+	info("submit_bulk_msg");
+	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		int transfer_len, struct devrequest *setup)
+{
+	int maxsize = usb_maxpacket(dev, pipe);
+
+	info("submit_control_msg");
+#ifdef DEBUG
+	urb_priv.actual_length = 0;
+	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+	wait_ms(1);
+#endif
+	if (!maxsize) {
+		err("submit_control_message: pipesize for pipe %lx is zero",
+			pipe);
+		return -1;
+	}
+	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
+		gohci.rh.dev = dev;
+		/* root hub - redirect */
+		return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
+			setup);
+	}
+
+	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
+}
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		int transfer_len, int interval)
+{
+	info("submit_int_msg");
+	return -1;
+}
+
+/*-------------------------------------------------------------------------*
+ * HC functions
+ *-------------------------------------------------------------------------*/
+
+/* reset the HC and BUS */
+
+static int hc_reset (ohci_t *ohci)
+{
+	int timeout = 30;
+	int smm_timeout = 50; /* 0,5 sec */
+
+	dbg("%s\n", __FUNCTION__);
+
+	if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
+		writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
+		info("USB HC TakeOver from SMM");
+		while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
+			wait_ms (10);
+			if (--smm_timeout == 0) {
+				err("USB HC TakeOver failed!");
+				return -1;
+			}
+		}
+	}
+
+	/* Disable HC interrupts */
+	writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
+
+	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
+		ohci->slot_name,
+		readl(&ohci->regs->control));
+
+	/* Reset USB (needed by some controllers) */
+	writel (0, &ohci->regs->control);
+
+	/* HC Reset requires max 10 us delay */
+	writel (OHCI_HCR,  &ohci->regs->cmdstatus);
+	while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
+		if (--timeout == 0) {
+			err("USB HC reset timed out!");
+			return -1;
+		}
+		udelay (1);
+	}
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Start an OHCI controller, set the BUS operational
+ * enable interrupts
+ * connect the virtual root hub */
+
+static int hc_start (ohci_t * ohci)
+{
+	__u32 mask;
+	unsigned int fminterval;
+
+	ohci->disabled = 1;
+
+	/* Tell the controller where the control and bulk lists are
+	 * The lists are empty now. */
+
+	writel (0, &ohci->regs->ed_controlhead);
+	writel (0, &ohci->regs->ed_bulkhead);
+
+	writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
+
+	fminterval = 0x2edf;
+	writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
+	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
+	writel (fminterval, &ohci->regs->fminterval);
+	writel (0x628, &ohci->regs->lsthresh);
+
+	/* start controller operations */
+	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+	ohci->disabled = 0;
+	writel (ohci->hc_control, &ohci->regs->control);
+
+	/* disable all interrupts */
+	mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
+			OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
+			OHCI_INTR_OC | OHCI_INTR_MIE);
+	writel (mask, &ohci->regs->intrdisable);
+	/* clear all interrupts */
+	mask &= ~OHCI_INTR_MIE;
+	writel (mask, &ohci->regs->intrstatus);
+	/* Choose the interrupts we care about now  - but w/o MIE */
+	mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
+	writel (mask, &ohci->regs->intrenable);
+
+#ifdef	OHCI_USE_NPS
+	/* required for AMD-756 and some Mac platforms */
+	writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
+		&ohci->regs->roothub.a);
+	writel (RH_HS_LPSC, &ohci->regs->roothub.status);
+#endif	/* OHCI_USE_NPS */
+
+#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
+	/* POTPGT delay is bits 24-31, in 2 ms units. */
+	mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
+
+	/* connect the virtual root hub */
+	ohci->rh.devnum = 0;
+
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* an interrupt happens */
+
+static int
+hc_interrupt (void)
+{
+	ohci_t *ohci = &gohci;
+	struct ohci_regs *regs = ohci->regs;
+	int ints;
+	int stat = -1;
+
+	if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
+		ints =	OHCI_INTR_WDH;
+	} else {
+		ints = readl (&regs->intrstatus);
+	}
+
+	/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
+
+	if (ints & OHCI_INTR_RHSC) {
+		got_rhsc = 1;
+	}
+
+	if (ints & OHCI_INTR_UE) {
+		ohci->disabled++;
+		err ("OHCI Unrecoverable Error, controller usb-%s disabled",
+			ohci->slot_name);
+		/* e.g. due to PCI Master/Target Abort */
+
+#ifdef	DEBUG
+		ohci_dump (ohci, 1);
+#else
+	wait_ms(1);
+#endif
+		/* FIXME: be optimistic, hope that bug won't repeat often. */
+		/* Make some non-interrupt context restart the controller. */
+		/* Count and limit the retries though; either hardware or */
+		/* software errors can go forever... */
+		hc_reset (ohci);
+		return -1;
+	}
+
+	if (ints & OHCI_INTR_WDH) {
+		wait_ms(1);
+		writel (OHCI_INTR_WDH, &regs->intrdisable);
+		stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
+		writel (OHCI_INTR_WDH, &regs->intrenable);
+	}
+
+	if (ints & OHCI_INTR_SO) {
+		dbg("USB Schedule overrun\n");
+		writel (OHCI_INTR_SO, &regs->intrenable);
+		stat = -1;
+	}
+
+	/* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
+	if (ints & OHCI_INTR_SF) {
+		unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
+		wait_ms(1);
+		writel (OHCI_INTR_SF, &regs->intrdisable);
+		if (ohci->ed_rm_list[frame] != NULL)
+			writel (OHCI_INTR_SF, &regs->intrenable);
+		stat = 0xff;
+	}
+
+	writel (ints, &regs->intrstatus);
+	return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------*/
+
+/* De-allocate all resources.. */
+
+static void hc_release_ohci (ohci_t *ohci)
+{
+	dbg ("USB HC release ohci usb-%s", ohci->slot_name);
+
+	if (!ohci->disabled)
+		hc_reset (ohci);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * low level initalisation routine, called from usb.c
+ */
+static char ohci_inited = 0;
+
+int usb_lowlevel_init(void)
+{
+	/*
+	 * Enable USB host clock.
+	 */
+	*AT91C_PMC_SCER = AT91C_PMC_UHP;	/* 48MHz clock enabled for UHP */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_UHP;	/* Peripheral Clock Enable Register */
+
+	memset (&gohci, 0, sizeof (ohci_t));
+	memset (&urb_priv, 0, sizeof (urb_priv_t));
+
+	/* align the storage */
+	if ((__u32)&ghcca[0] & 0xff) {
+		err("HCCA not aligned!!");
+		return -1;
+	}
+	phcca = &ghcca[0];
+	info("aligned ghcca %p", phcca);
+	memset(&ohci_dev, 0, sizeof(struct ohci_device));
+	if ((__u32)&ohci_dev.ed[0] & 0x7) {
+		err("EDs not aligned!!");
+		return -1;
+	}
+	memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
+	if ((__u32)gtd & 0x7) {
+		err("TDs not aligned!!");
+		return -1;
+	}
+	ptd = gtd;
+	gohci.hcca = phcca;
+	memset (phcca, 0, sizeof (struct ohci_hcca));
+
+	gohci.disabled = 1;
+	gohci.sleeping = 0;
+	gohci.irq = -1;
+	gohci.regs = (struct ohci_regs *)AT91_USB_HOST_BASE;
+
+	gohci.flags = 0;
+	gohci.slot_name = "at91rm9200";
+
+	if (hc_reset (&gohci) < 0) {
+		hc_release_ohci (&gohci);
+		/* Initialization failed */
+		*AT91C_PMC_PCER = AT91C_ID_UHP;
+		*AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP;	/* 48MHz clock disabled for UHP */
+		return -1;
+	}
+
+	/* FIXME this is a second HC reset; why?? */
+/*	writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
+	wait_ms (10);*/
+
+	if (hc_start (&gohci) < 0) {
+		err ("can't start usb-%s", gohci.slot_name);
+		hc_release_ohci (&gohci);
+		/* Initialization failed */
+		*AT91C_PMC_PCER = AT91C_ID_UHP;
+		*AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP;	/* 48MHz clock disabled for UHP */
+		return -1;
+	}
+
+#ifdef	DEBUG
+	ohci_dump (&gohci, 1);
+#else
+	wait_ms(1);
+#endif
+	ohci_inited = 1;
+	return 0;
+}
+
+int usb_lowlevel_stop(void)
+{
+	/* this gets called really early - before the controller has */
+	/* even been initialized! */
+	if (!ohci_inited)
+		return 0;
+	/* TODO release any interrupts, etc. */
+	/* call hc_release_ohci() here ? */
+	hc_reset (&gohci);
+	/* may not want to do this */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_UHP;
+	*AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP;	/* 48MHz clock disabled for UHP */
+	return 0;
+}
+
+#endif /* CONFIG_USB_OHCI */

cpu/arm920t/comcerto/usb_ohci.h

diff --git a/cpu/arm920t/comcerto/usb_ohci.h b/cpu/arm920t/comcerto/usb_ohci.h
new file mode 100644
index 0000000..ecb4e93
--- /dev/null
+++ b/cpu/arm920t/comcerto/usb_ohci.h
@@ -0,0 +1,419 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+	/* No  Error  */	       0,
+	/* CRC Error  */	       USB_ST_CRC_ERR,
+	/* Bit Stuff  */	       USB_ST_BIT_ERR,
+	/* Data Togg  */	       USB_ST_CRC_ERR,
+	/* Stall      */	       USB_ST_STALLED,
+	/* DevNotResp */	       -1,
+	/* PIDCheck   */	       USB_ST_BIT_ERR,
+	/* UnExpPID   */	       USB_ST_BIT_ERR,
+	/* DataOver   */	       USB_ST_BUF_ERR,
+	/* DataUnder  */	       USB_ST_BUF_ERR,
+	/* reservd    */	       -1,
+	/* reservd    */	       -1,
+	/* BufferOver */	       USB_ST_BUF_ERR,
+	/* BuffUnder  */	       USB_ST_BUF_ERR,
+	/* Not Access */	       -1,
+	/* Not Access */	       -1
+};
+
+/* ED States */
+
+#define ED_NEW		0x00
+#define ED_UNLINK	0x01
+#define ED_OPER		0x02
+#define ED_DEL		0x04
+#define ED_URB_DEL	0x08
+
+/* usb_ohci_ed */
+struct ed {
+	__u32 hwINFO;
+	__u32 hwTailP;
+	__u32 hwHeadP;
+	__u32 hwNextED;
+
+	struct ed *ed_prev;
+	__u8 int_period;
+	__u8 int_branch;
+	__u8 int_load;
+	__u8 int_interval;
+	__u8 state;
+	__u8 type;
+	__u16 last_iso;
+	struct ed *ed_rm_list;
+
+	struct usb_device *usb_dev;
+	__u32 unused[3];
+} __attribute((aligned(16)));
+typedef struct ed ed_t;
+
+
+/* TD info field */
+#define TD_CC	    0xf0000000
+#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC	    0x0C000000
+#define TD_T	    0x03000000
+#define TD_T_DATA0  0x02000000
+#define TD_T_DATA1  0x03000000
+#define TD_T_TOGGLE 0x00000000
+#define TD_R	    0x00040000
+#define TD_DI	    0x00E00000
+#define TD_DI_SET(X) (((X) & 0x07)<< 21)
+#define TD_DP	    0x00180000
+#define TD_DP_SETUP 0x00000000
+#define TD_DP_IN    0x00100000
+#define TD_DP_OUT   0x00080000
+
+#define TD_ISO	    0x00010000
+#define TD_DEL	    0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR	   0x00
+#define TD_CC_CRC	   0x01
+#define TD_CC_BITSTUFFING  0x02
+#define TD_CC_DATATOGGLEM  0x03
+#define TD_CC_STALL	   0x04
+#define TD_DEVNOTRESP	   0x05
+#define TD_PIDCHECKFAIL	   0x06
+#define TD_UNEXPECTEDPID   0x07
+#define TD_DATAOVERRUN	   0x08
+#define TD_DATAUNDERRUN	   0x09
+#define TD_BUFFEROVERRUN   0x0C
+#define TD_BUFFERUNDERRUN  0x0D
+#define TD_NOTACCESSED	   0x0F
+
+
+#define MAXPSW 1
+
+struct td {
+	__u32 hwINFO;
+	__u32 hwCBP;		/* Current Buffer Pointer */
+	__u32 hwNextTD;		/* Next TD Pointer */
+	__u32 hwBE;		/* Memory Buffer End Pointer */
+
+	__u16 hwPSW[MAXPSW];
+	__u8 unused;
+	__u8 index;
+	struct ed *ed;
+	struct td *next_dl_td;
+	struct usb_device *usb_dev;
+	int transfer_len;
+	__u32 data;
+
+	__u32 unused2[2];
+} __attribute((aligned(32)));
+typedef struct td td_t;
+
+#define OHCI_ED_SKIP	(1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of.  It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32	/* part of the OHCI standard */
+struct ohci_hcca {
+	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
+	__u16	frame_no;		/* current frame number */
+	__u16	pad1;			/* set to 0 on each frame_no change */
+	__u32	done_head;		/* info returned for an interrupt */
+	u8		reserved_for_hc[116];
+} __attribute((aligned(256)));
+
+
+/*
+ * Maximum number of root hub ports.
+ */
+#define MAX_ROOT_PORTS	15	/* maximum OHCI root hub ports */
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region.  This is Memory Mapped I/O.	You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+	/* control and status registers */
+	__u32	revision;
+	__u32	control;
+	__u32	cmdstatus;
+	__u32	intrstatus;
+	__u32	intrenable;
+	__u32	intrdisable;
+	/* memory pointers */
+	__u32	hcca;
+	__u32	ed_periodcurrent;
+	__u32	ed_controlhead;
+	__u32	ed_controlcurrent;
+	__u32	ed_bulkhead;
+	__u32	ed_bulkcurrent;
+	__u32	donehead;
+	/* frame counters */
+	__u32	fminterval;
+	__u32	fmremaining;
+	__u32	fmnumber;
+	__u32	periodicstart;
+	__u32	lsthresh;
+	/* Root hub ports */
+	struct	ohci_roothub_regs {
+		__u32	a;
+		__u32	b;
+		__u32	status;
+		__u32	portstatus[MAX_ROOT_PORTS];
+	} roothub;
+} __attribute((aligned(32)));
+
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
+#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
+#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
+#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
+#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
+#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
+#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
+#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
+#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+#	define OHCI_USB_RESET	(0 << 6)
+#	define OHCI_USB_RESUME	(1 << 6)
+#	define OHCI_USB_OPER	(2 << 6)
+#	define OHCI_USB_SUSPEND (3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR	(1 << 0)	/* host controller reset */
+#define OHCI_CLF	(1 << 1)	/* control list filled */
+#define OHCI_BLF	(1 << 2)	/* bulk list filled */
+#define OHCI_OCR	(1 << 3)	/* ownership change request */
+#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
+#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
+#define OHCI_INTR_SF	(1 << 2)	/* start frame */
+#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
+#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
+#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
+#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
+#define OHCI_INTR_OC	(1 << 30)	/* ownership change */
+#define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */
+
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+	int devnum; /* Address of Root Hub endpoint */
+	void *dev;  /* was urb */
+	void *int_addr;
+	int send;
+	int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE		   0x01
+#define RH_ENDPOINT		   0x02
+#define RH_OTHER		   0x03
+
+#define RH_CLASS		   0x20
+#define RH_VENDOR		   0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS		0x0080
+#define RH_CLEAR_FEATURE	0x0100
+#define RH_SET_FEATURE		0x0300
+#define RH_SET_ADDRESS		0x0500
+#define RH_GET_DESCRIPTOR	0x0680
+#define RH_SET_DESCRIPTOR	0x0700
+#define RH_GET_CONFIGURATION	0x0880
+#define RH_SET_CONFIGURATION	0x0900
+#define RH_GET_STATE		0x0280
+#define RH_GET_INTERFACE	0x0A80
+#define RH_SET_INTERFACE	0x0B00
+#define RH_SYNC_FRAME		0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP		0x2000
+
+
+/* Hub port features */
+#define RH_PORT_CONNECTION	   0x00
+#define RH_PORT_ENABLE		   0x01
+#define RH_PORT_SUSPEND		   0x02
+#define RH_PORT_OVER_CURRENT	   0x03
+#define RH_PORT_RESET		   0x04
+#define RH_PORT_POWER		   0x08
+#define RH_PORT_LOW_SPEED	   0x09
+
+#define RH_C_PORT_CONNECTION	   0x10
+#define RH_C_PORT_ENABLE	   0x11
+#define RH_C_PORT_SUSPEND	   0x12
+#define RH_C_PORT_OVER_CURRENT	   0x13
+#define RH_C_PORT_RESET		   0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER	   0x00
+#define RH_C_HUB_OVER_CURRENT	   0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP	   0x00
+#define RH_ENDPOINT_STALL	   0x01
+
+#define RH_ACK			   0x01
+#define RH_REQ_ERR		   -1
+#define RH_NACK			   0x00
+
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS	     0x00000001		/* current connect status */
+#define RH_PS_PES	     0x00000002		/* port enable status*/
+#define RH_PS_PSS	     0x00000004		/* port suspend status */
+#define RH_PS_POCI	     0x00000008		/* port over current indicator */
+#define RH_PS_PRS	     0x00000010		/* port reset status */
+#define RH_PS_PPS	     0x00000100		/* port power status */
+#define RH_PS_LSDA	     0x00000200		/* low speed device attached */
+#define RH_PS_CSC	     0x00010000		/* connect status change */
+#define RH_PS_PESC	     0x00020000		/* port enable status change */
+#define RH_PS_PSSC	     0x00040000		/* port suspend status change */
+#define RH_PS_OCIC	     0x00080000		/* over current indicator change */
+#define RH_PS_PRSC	     0x00100000		/* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS	     0x00000001		/* local power status */
+#define RH_HS_OCI	     0x00000002		/* over current indicator */
+#define RH_HS_DRWE	     0x00008000		/* device remote wakeup enable */
+#define RH_HS_LPSC	     0x00010000		/* local power status change */
+#define RH_HS_OCIC	     0x00020000		/* over current indicator change */
+#define RH_HS_CRWE	     0x80000000		/* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR		0x0000ffff		/* device removable flags */
+#define RH_B_PPCM	0xffff0000		/* port power control mask */
+
+/* roothub.a masks */
+#define RH_A_NDP	(0xff << 0)		/* number of downstream ports */
+#define RH_A_PSM	(1 << 8)		/* power switching mode */
+#define RH_A_NPS	(1 << 9)		/* no power switching */
+#define RH_A_DT		(1 << 10)		/* device type (mbz) */
+#define RH_A_OCPM	(1 << 11)		/* over current protection mode */
+#define RH_A_NOCP	(1 << 12)		/* no over current protection */
+#define RH_A_POTPGT	(0xff << 24)		/* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+typedef struct
+{
+	ed_t *ed;
+	__u16 length;	/* number of tds associated with this request */
+	__u16 td_cnt;	/* number of tds already serviced */
+	int   state;
+	unsigned long pipe;
+	int actual_length;
+	td_t *td[N_URB_TD];	/* list pointer to all corresponding TDs associated with this request */
+} urb_priv_t;
+#define URB_DEL 1
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+
+typedef struct ohci {
+	struct ohci_hcca *hcca;		/* hcca */
+	/*dma_addr_t hcca_dma;*/
+
+	int irq;
+	int disabled;			/* e.g. got a UE, we're hung */
+	int sleeping;
+	unsigned long flags;		/* for HC bugs */
+
+	struct ohci_regs *regs; /* OHCI controller's memory */
+
+	ed_t *ed_rm_list[2];	 /* lists of all endpoints to be removed */
+	ed_t *ed_bulktail;	 /* last endpoint of bulk list */
+	ed_t *ed_controltail;	 /* last endpoint of control list */
+	int intrstatus;
+	__u32 hc_control;		/* copy of the hc control reg */
+	struct usb_device *dev[32];
+	struct virt_root_hub rh;
+
+	const char	*slot_name;
+} ohci_t;
+
+#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+	ed_t	ed[NUM_EDS];
+	int ed_cnt;
+};
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* +1 so we can align the storage */
+td_t gtd[NUM_TD+1];
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *
+td_alloc (struct usb_device *usb_dev)
+{
+	int i;
+	struct td	*td;
+
+	td = NULL;
+	for (i = 0; i < NUM_TD; i++)
+	{
+		if (ptd[i].usb_dev == NULL)
+		{
+			td = &ptd[i];
+			td->usb_dev = usb_dev;
+			break;
+		}
+	}
+
+	return td;
+}
+
+static inline void
+ed_free (struct ed *ed)
+{
+	ed->usb_dev = NULL;
+}

cpu/arm920t/start.S

diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 346f0d0..96822e2 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -28,6 +28,9 @@
 #include <config.h>
 #include <version.h>
 
+#if defined(CONFIG_COMCERTO)
+#include <asm/hardware.h>
+#endif
 
 /*
  *************************************************************************
@@ -73,7 +76,11 @@
  */
 
 _TEXT_BASE:
+#if defined(CONFIG_COMCERTO)
+	.word	_start	
+#else
 	.word	TEXT_BASE
+#endif
 
 .globl _armboot_start
 _armboot_start:
@@ -108,6 +115,25 @@
  */
 
 reset:
+
+#if defined(CONFIG_COMCERTO)
+
+	/* test if we run from flash or RAM, don't reloc during debug */
+	adr	r0, _start              /* r0 <- current position of code   */
+	ldr	r1, _TEXT_BASE
+	cmp	r0, r1 
+	beq	cpu_init
+
+	/* We were running from offset 0x0, now jump to Boot FLASH address,
+           so that we can configure SDRAM */
+	ldr	pc, = EXP_CSBOOT_BASEADDR + rom_second_loc - TEXT_BASE
+rom_second_loc:
+	/* Disable low SDRAM remapping */
+	ldr	r2, = ASD_CSE
+	mov	r3, #CSE_BOOT
+	strh	r3, [r2]
+cpu_init:
+#endif
 	/*
 	 * set the cpu to SVC32 mode
 	 */

cpu/arm_cortexa9/Makefile

diff --git a/cpu/arm_cortexa9/Makefile b/cpu/arm_cortexa9/Makefile
new file mode 100644
index 0000000..b8efc4e
--- /dev/null
+++ b/cpu/arm_cortexa9/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).a
+
+START	:= start.o
+COBJS	:= cpu.o
+
+SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

cpu/arm_cortexa9/comcerto/Makefile

diff --git a/cpu/arm_cortexa9/comcerto/Makefile b/cpu/arm_cortexa9/comcerto/Makefile
new file mode 100644
index 0000000..5a9ae47
--- /dev/null
+++ b/cpu/arm_cortexa9/comcerto/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	= interrupts.o serial.o spi.o bsp2000.o
+SOBJS	= lowlevel_init.o
+
+all:	$(obj).depend $(LIB)
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

cpu/arm_cortexa9/comcerto/bsp2000.c

diff --git a/cpu/arm_cortexa9/comcerto/bsp2000.c b/cpu/arm_cortexa9/comcerto/bsp2000.c
new file mode 100644
index 0000000..4552a6f
--- /dev/null
+++ b/cpu/arm_cortexa9/comcerto/bsp2000.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2011-2012 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm-arm/arch-comcerto/exp-bus_c2000.h>
+#include <asm-arm/arch-comcerto/bsp.h>
+#include <asm/io.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+void SoC_nand_init(void)
+{
+	/* IBR, when booting from NOR, is changing expansion bus CS0 Mem Segment size to 1MiB
+	instead of the default reset value of 128MiB. Put back the reset default value */
+	writel(EXP_CS0_SEG_END_VAL, EXP_CS0_SEG_REG);
+
+	writel(EXP_CS1_BASE_VAL, EXP_CS1_BASE_REG);
+	writel(EXP_CS1_SEG_END_VAL, EXP_CS1_SEG_REG);
+
+	writel(EXP_CS2_BASE_VAL, EXP_CS2_BASE_REG);
+	writel(EXP_CS2_SEG_END_VAL, EXP_CS2_SEG_REG);
+
+	writel(EXP_CS3_BASE_VAL, EXP_CS3_BASE_REG);
+	writel(EXP_CS3_SEG_END_VAL, EXP_CS3_SEG_REG);
+
+	writel(EXP_CS4_BASE_VAL, EXP_CS4_BASE_REG);
+	writel(EXP_CS4_SEG_END_VAL, EXP_CS4_SEG_REG);
+
+#ifdef CONFIG_NAND_TYPE_SLC
+        //SLC NAND on ASIC is 16-bit. Enable 16-bit bus
+        writel(readl(EXP_CS4_CFG_REG) | 0x2, EXP_CS4_CFG_REG);
+#else
+        //MLC NAND on ASIC is 8-bit. Enable 8-bit bus
+        writel((readl(EXP_CS4_CFG_REG) & (~0x6)), EXP_CS4_CFG_REG);
+#endif
+
+}
+
+/*
+* SoC_gpio_cfg - configure GPIO pins as input or output pins
+*
+* gpio - gpio pin
+*
+* mode - gpio pin mode
+*	GPIO_TYPE_OUTPUT = output
+*	GPIO_TYPE_INPUT = input
+*
+*/
+int SoC_gpio_cfg(int gpio, int mode)
+{
+	if ((gpio < 0) || (gpio > 31))
+		goto err;
+
+	switch (mode) {
+	case GPIO_TYPE_INPUT:
+	default:
+		*(volatile u32 *) COMCERTO_GPIO_OE_REG &= __cpu_to_le32(~(1 << gpio));
+		break;
+
+	case GPIO_TYPE_OUTPUT:
+		*(volatile u32 *) COMCERTO_GPIO_OE_REG |= __cpu_to_le32(1 << gpio);
+		break;
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
+#endif /* CFG_CMD_NAND */

cpu/arm_cortexa9/comcerto/interrupts.c

diff --git a/cpu/arm_cortexa9/comcerto/interrupts.c b/cpu/arm_cortexa9/comcerto/interrupts.c
new file mode 100644
index 0000000..f14de06
--- /dev/null
+++ b/cpu/arm_cortexa9/comcerto/interrupts.c
@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bsp.h>
+#include <asm/byteorder.h>
+
+#define TIMER_LOAD_VAL		0xffffffff
+#define CLOCK_COUNT_PER_USEC	(CFG_HZ_CLOCK / 1000 / 1000)
+#define USEC_PER_TICK		(1000 * 1000 / CFG_HZ)
+
+#define A9_TIMER_LOAD           0x0
+#define A9_TIMER_COUNTER        0x4
+#define A9_TIMER_CNTRL          0x8
+#define A9_TIMER_INT_STAT       0xC
+
+#define A9_TIMER_ENABLE         (1<<0)
+#define A9_TIMER_RELOAD         (1<<1)
+#define A9_TIMER_IRQ_EN         (1<<2)
+
+#define COMCERTO_A9_PERIPH_BASE     0xFFF00000
+#define COMCERTO_A9_TIMER_BASE          (COMCERTO_A9_PERIPH_BASE + 0x600)
+#define READ_TIMER      (TIMER_LOAD_VAL - readl(COMCERTO_A9_TIMER_BASE + A9_TIMER_COUNTER))
+
+
+static ulong ts_count, ts_usec;
+static ulong lastinc;
+
+int interrupt_init (void)
+{
+	int i;
+        writel(TIMER_LOAD_VAL, COMCERTO_A9_TIMER_BASE + A9_TIMER_LOAD);
+        writel(TIMER_LOAD_VAL, COMCERTO_A9_TIMER_BASE + A9_TIMER_COUNTER);
+        writel(A9_TIMER_ENABLE | A9_TIMER_RELOAD, COMCERTO_A9_TIMER_BASE + A9_TIMER_CNTRL);
+
+	lastinc = 0;
+	ts_count = 0;
+	ts_usec = 0;
+
+	return (0);
+}
+
+void reset_timer_masked (void)
+{
+	lastinc = READ_TIMER;
+	ts_count = 0;
+	ts_usec = 0;
+}
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+/* Returns usecs since last timer reset */
+ulong get_timer_raw (void)
+{
+	ulong step;
+	ulong now = READ_TIMER;
+
+	if (now > lastinc) {
+		/* normal mode */
+		step = now - lastinc;
+	} else {
+		/* we have an overflow ... */
+		step = (TIMER_LOAD_VAL - lastinc) + now;
+	}
+
+	lastinc = now;
+
+	ts_count += step % CLOCK_COUNT_PER_USEC;
+	ts_usec += step / CLOCK_COUNT_PER_USEC;
+
+	if (ts_count >= CLOCK_COUNT_PER_USEC) {
+		ts_usec += ts_count / CLOCK_COUNT_PER_USEC;
+		ts_count %= CLOCK_COUNT_PER_USEC;
+	}
+
+	return ts_usec;
+}
+
+/* Returns tick count since last timer reset */
+ulong get_timer_masked (void)
+{
+	return get_timer_raw() / USEC_PER_TICK;
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong endtime = get_timer_raw () + usec;
+
+	while (get_timer_raw () < endtime)
+		;
+
+}
+
+void udelay (unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CFG_HZ;
+	return tbclk;
+}
+
+/*
+ *
+ */
+void reset_cpu (ulong ignored)
+{
+	/* set the timeout value */
+//	*(volatile u32 *)TIMER_WDT_HIGH_BOUND = __cpu_to_le32(0x1);
+	/* enable watchdog timer */
+//	*(volatile u32 *)TIMER_WDT_CONTROL = __cpu_to_le32(0x1);
+
+	while (1) ;
+}
+
+/*
+ * timer without interrupts
+ */
+
+
+void set_timer (ulong t)
+{
+	ts_count = 0;
+	ts_usec = t * USEC_PER_TICK;
+}

cpu/arm_cortexa9/comcerto/lowlevel_init.S

diff --git a/cpu/arm_cortexa9/comcerto/lowlevel_init.S b/cpu/arm_cortexa9/comcerto/lowlevel_init.S
new file mode 100644
index 0000000..1c89690
--- /dev/null
+++ b/cpu/arm_cortexa9/comcerto/lowlevel_init.S
@@ -0,0 +1,40 @@
+/*
+ * SOC specific setup info
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/hardware.h>
+
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp, TMP_STACK /* set up a temporary stack */
+
+	stmdb	sp!, {ip, lr}
+	bl	bsp_init	/* go setup pll, memory */
+	ldmia	sp!, {ip, pc}	/* restore registers and return to caller */
+
+	/* the literal pools origin */
+	.ltorg
+TMP_STACK:
+	.word	CFG_INIT_RAM_ADDR  + CFG_INIT_SP_OFFSET

cpu/arm_cortexa9/comcerto/serial.c

diff --git a/cpu/arm_cortexa9/comcerto/serial.c b/cpu/arm_cortexa9/comcerto/serial.c
new file mode 100644
index 0000000..a069547
--- /dev/null
+++ b/cpu/arm_cortexa9/comcerto/serial.c
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bsp.h>
+#include <asm/byteorder.h>
+
+#define COMCERTO_UART0_BASE             0x96400000
+
+#if !defined(CONFIG_UART0) && !defined(CONFIG_UART1)
+#error must define one of CONFIG_UART0 or CONFIG_UART1
+#endif
+
+
+typedef struct tagUART16550REGS {
+	volatile u32 data;	// Receive/Transmit data register
+	volatile u32 ier;	// Interrupt Enable register
+	volatile u32 iir_fcr;// Interrupt Identity register / FIFO Control register
+	volatile u32 lcr;	// Line Control register
+	volatile u32 mcr;	// Modem Control register
+	volatile u32 lsr;	// Line Status register
+	volatile u32 msr;	// Modem Status register
+	volatile u32 sr;		// Scratch register
+} UART16550REGS, *PUART16550REGS;
+
+typedef struct tagUART16550DLREGS {
+	volatile u32 dll;	// Divisor Latch (Low)
+	volatile u32 dlh;	// Divisor Latch (High)
+} UART16550DLREGS, *PUART16550DLREGS;
+
+#define LCR_CHAR_LEN_5		0x00	  /* default */
+#define LCR_CHAR_LEN_6		0x01
+#define LCR_CHAR_LEN_7		0x02
+#define LCR_CHAR_LEN_8		0x03
+#define LCR_ONE_STOP		0x00	  /* One stop bit! - default */
+#define LCR_TWO_STOP		0x04	  /* Two stop bit! */
+#define LCR_PEN				0x08	  /* Parity Enable */
+#define LCR_PARITY_NONE		0x00
+#define LCR_EPS				0x10	  /* Even Parity Select */
+#define LCR_PS				0x20	  /* Enable Parity  Stuff */
+#define LCR_SBRK				0x40  /* Start Break */
+#define LCR_PSB				0x80	  /* Parity Stuff Bit */
+#define LCR_DLAB				0x80  /* UART 16550 Divisor Latch Assess */
+
+#define LSR_FIFOE		(1 << 7)	/* FIFO Error Status */
+#define LSR_TEMT			(1 << 6)	/* Transmitter Empty */
+#define LSR_TDRQ			(1 << 5)	/* Transmit Data Request */
+#define LSR_BI			(1 << 4)	/* Break Interrupt */
+#define LSR_FE			(1 << 3)	/* Framing Error */
+#define LSR_PE			(1 << 2)	/* Parity Error */
+#define LSR_OE			(1 << 1)	/* Overrun Error */
+#define LSR_DR			(1 << 0)	/* Data Ready */
+
+
+#define IER_DMAE			(1 << 7)	/* DMA Requests Enable */
+#define IER_UUE			(1 << 6)	/* UART Unit Enable */
+#define IER_NRZE			(1 << 5)	/* NRZ coding Enable */
+#define IER_RTIOE			(1 << 4)	/* Receiver Time Out Interrupt Enable */
+#define IER_MIE			(1 << 3)	/* Modem Interrupt Enable */
+#define IER_RLSE			(1 << 2)	/* Receiver Line Status Interrupt Enable */
+#define IER_TIE			(1 << 1)	/* Transmit Data request Interrupt Enable */
+#define IER_RAVIE			(1 << 0)	/* Receiver Data Available Interrupt Enable */
+
+#define IIR_FIFOES1		(1 << 7)	/* FIFO Mode Enable Status */
+#define IIR_FIFOES0		(1 << 6)	/* FIFO Mode Enable Status */
+#define IIR_TOD			(1 << 3)	/* Time Out Detected */
+#define IIR_IID2			(1 << 2)	/* Interrupt Source Encoded */
+#define IIR_IID1			(1 << 1)	/* Interrupt Source Encoded */
+#define IIR_IP				(1 << 0)	/* Interrupt Pending (active low) */
+
+/* UART 16550 FIFO Control Register */
+#define FCR_FIFOEN			0x01
+#define FCR_RCVRRES			0x02
+#define FCR_XMITRES			0x04
+
+/* Interrupt Enable Register */
+// UART 16550
+#define IER_RXTH			0x01	// Enable Received Data Available Interrupt
+#define IER_TXTH			0x02	// Enable Transmitter Empty Interrupt
+
+void serial_setbrg (void)
+{
+	int baudrate = 115200;
+	unsigned int div;
+	unsigned int clk = 200000000;
+#ifdef CONFIG_UART0
+	PUART16550REGS uart = (PUART16550REGS) COMCERTO_UART0_BASE;
+	PUART16550DLREGS uart_dl = (PUART16550DLREGS) COMCERTO_UART0_BASE;
+#else
+	PUART16550REGS uart = (PUART16550REGS) UART1_BASEADDR;
+	PUART16550DLREGS uart_dl = (PUART16550DLREGS) UART1_BASEADDR;
+#endif
+
+	div = (clk + 8 * baudrate) / (16 * baudrate);
+	uart->lcr |= __cpu_to_le32(LCR_DLAB); // Enable Divisor Latch access
+	uart_dl->dll = __cpu_to_le32(div & 0xFF); // Set Divisor Latch Low
+	uart_dl->dlh = __cpu_to_le32((div >> 8) & 0xFF); // Set Divisor Latch high
+	uart->lcr &= __cpu_to_le32(~LCR_DLAB); // Disable Divisor Latch access
+
+}
+
+int serial_init (void)
+{
+#ifdef CONFIG_UART0
+	PUART16550REGS uart = (PUART16550REGS) COMCERTO_UART0_BASE;
+#else
+	PUART16550REGS uart = (PUART16550REGS) UART1_BASEADDR;
+#endif
+
+#ifdef CONFIG_UART1
+	EnableUART1();
+#endif
+
+	serial_setbrg ();
+
+	uart->lcr = __cpu_to_le32(LCR_ONE_STOP | LCR_CHAR_LEN_8);
+	uart->iir_fcr = __cpu_to_le32(FCR_XMITRES | FCR_RCVRRES | FCR_FIFOEN); // Reset, FIFO
+	uart->ier = __cpu_to_le32(IER_UUE);		/* Enable FFUART */
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+#ifdef CONFIG_UART0
+	PUART16550REGS uart = (PUART16550REGS) COMCERTO_UART0_BASE;
+#else
+	PUART16550REGS uart = (PUART16550REGS) UART1_BASEADDR;
+#endif
+
+	/* wait for room in the tx FIFO on FFUART */
+	while ((uart->lsr & __cpu_to_le32(LSR_TDRQ))==0) ;
+	uart->data = __cpu_to_le32(c);
+	if (c == '\n')
+		serial_putc ('\r');
+}
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+int serial_getc (void)
+{
+#ifdef CONFIG_UART0
+	PUART16550REGS uart = (PUART16550REGS) COMCERTO_UART0_BASE;
+#else
+	PUART16550REGS uart = (PUART16550REGS) UART1_BASEADDR;
+#endif
+
+	while ((uart->lsr & __cpu_to_le32(LSR_DR)) == 0);
+	return (char)__le32_to_cpu(uart->data & __cpu_to_le32(0xff));
+}
+
+int serial_tstc (void)
+{
+#ifdef CONFIG_UART0
+	PUART16550REGS uart = (PUART16550REGS) COMCERTO_UART0_BASE;
+#else
+	PUART16550REGS uart = (PUART16550REGS) UART1_BASEADDR;
+#endif
+
+	return __le32_to_cpu(uart->lsr & __cpu_to_le32(LSR_DR));
+}

cpu/arm_cortexa9/comcerto/spi.c

diff --git a/cpu/arm_cortexa9/comcerto/spi.c b/cpu/arm_cortexa9/comcerto/spi.c
new file mode 100644
index 0000000..2ec7a1c
--- /dev/null
+++ b/cpu/arm_cortexa9/comcerto/spi.c
@@ -0,0 +1,449 @@
+#include <asm/types.h>
+#include <asm/io.h>
+#include <linux/types.h>
+
+#include <linux/byteorder/generic.h>
+#include <linux/byteorder/little_endian.h>
+
+#define COMCERTO_AXI_APB_CFG_BASE       0x90400000
+#define SPI_BASEADDR                    (COMCERTO_AXI_APB_CFG_BASE + 0x098000)
+
+#define COMCERTO_SPI_CTRLR0               0x00
+#define COMCERTO_SPI_CTRLR1               0x04
+#define COMCERTO_SPI_SSIENR               0x08
+#define COMCERTO_SPI_MWCR                 0x0C
+#define COMCERTO_SPI_SER                  0x10
+#define COMCERTO_SPI_BAUDR                0x14
+#define COMCERTO_SPI_TXFTLR               0x18
+#define COMCERTO_SPI_RXFTLR               0x1C
+#define COMCERTO_SPI_TXFLR                0x20
+#define COMCERTO_SPI_RXFLR                0x24
+#define COMCERTO_SPI_SR                   0x28
+#define COMCERTO_SPI_IMR                  0x2C
+#define COMCERTO_SPI_ISR                  0x30
+#define COMCERTO_SPI_RISR                 0x34
+#define COMCERTO_SPI_TXOICR               0x38
+#define COMCERTO_SPI_RXOICR               0x3C
+#define COMCERTO_SPI_RXUICR               0x40
+#define COMCERTO_SPI_MSTICR               0x44
+#define COMCERTO_SPI_ICR                  0x48
+#define COMCERTO_SPI_DMACR                0x4C
+#define COMCERTO_SPI_DMATDLR              0x50
+#define COMCERTO_SPI_DMARDLR              0x54
+#define COMCERTO_SPI_IDR                  0x58
+#define COMCERTO_SPI_DR                   0x60
+
+/* SR - status register bits */
+#define BUSY            (1<<0)  /* SSI busy flag, serial transfer in progress */
+#define TFNF            (1<<1)  /* Transmit FIFO not full */
+#define TFE             (1<<2)  /* Transmit FIFO empty */
+#define RFNE            (1<<3)  /* Receive FIFO not empty */
+#define RFF             (1<<4)  /* Receive FIFO full */
+#define TXE             (1<<5)  /* Transmission error */
+#define DCOL            (1<<6)  /* Data collision error */
+
+/* Interrupt status after being masked */
+#define TXEIS           (1<<0)  /* Transmit FIFO empty interrupt status */
+#define TXOIS           (1<<1)  /* Transmit FIFO overflow interrupt status */
+#define RXUIS           (1<<2)  /* Receive FIFO underflow interrupt status */
+#define RXOIS           (1<<3)  /* Receive FIFO overflow interrupt status */
+#define RXFIS           (1<<4)  /* Receive FIFO full interrupt status */
+#define MSTIS           (1<<5)  /* Multi-Master contention interrupt status */
+
+/* Interrupt status before being masked */
+#define TXEIR           (1<<0)  /* Transmit FIFO empty interrupt status */
+#define TXOIR           (1<<1)  /* Transmit FIFO overflow interrupt status */
+#define RXUIR           (1<<2)  /* Receive FIFO underflow interrupt status */
+#define RXOIR           (1<<3)  /* Receive FIFO overflow interrupt status */
+#define RXFIR           (1<<4)  /* Receive FIFO full interrupt status */
+#define MSTIR           (1<<5)  /* Multi-Master contention interrupt status */
+
+
+/* Interrupt mask register */
+#define TXEIM           (1<<0)  /* Transmit FIFO empty interrupt status */
+#define TXOIM           (1<<1)  /* Transmit FIFO overflow interrupt status */
+#define RXUIM           (1<<2)  /* Receive FIFO underflow interrupt status */
+#define RXOIM           (1<<3)  /* Receive FIFO overflow interrupt status */
+#define RXFIM           (1<<4)  /* Receive FIFO full interrupt status */
+#define MSTIM           (1<<5)  /* Multi-Master contention interrupt status */
+
+
+#define SPI_TRANSFER_MODE_WRITE_ONLY    0x01
+#define SPI_TRANSFER_MODE_READ_ONLY     0x02
+#define SPI_TRANSFER_MODE_WRITE_READ    0x03
+#define SPI_TRANSFER_MODE_EEPROM_READ   0x04
+
+#define SPI_CTRLR0_SCPOL        (1 << 7)
+#define SPI_CTRLR0_SCPH         (1 << 6)
+
+#define COMCERTO_DEFAULTAXICLK          250000000 /* Hz */
+
+unsigned int spi_base = SPI_BASEADDR;
+
+struct spi_transfer {
+        const void      *tx_buf;
+        void            *rx_buf;
+        unsigned        len;
+        int             mode;
+};
+
+
+int do_eeprom_read(u8 fs, u8 *wbuf, u32 *wlen, u8 *rbuf, u32 *ndf)
+{
+        u32 sr, dr;
+        u32 wlen_now = 0, rlen_now = 0;
+        int rc = 0;
+
+        while (wlen_now < *wlen) {
+                sr = readl(spi_base + COMCERTO_SPI_SR);
+
+                if (sr & TFNF) {
+                        if (wlen_now < *wlen) {
+                                writew(cpu_to_le16((u16) *wbuf), spi_base + COMCERTO_SPI_DR);
+                                wbuf++;
+                                wlen_now++;
+                        }
+                }
+        }
+
+        while (rlen_now < *ndf) {
+                sr = readl(spi_base + COMCERTO_SPI_SR);
+
+                if (sr & (RFF | DCOL)) {
+                        /* read overrun, data collision */
+                        rc = -1;
+                        goto out;
+                }
+
+                if (sr & RFNE) {
+                        dr = readw(spi_base + COMCERTO_SPI_DR);
+                        if (rlen_now < *ndf) {
+                                *rbuf = (u8) (le16_to_cpu(dr) & 0xff);
+                                rbuf++;
+                                rlen_now++;
+                        } else {
+                                /* read overflow */
+                                rc = -1;
+                                goto out;
+                        }
+                }
+        }
+
+out:
+        *ndf = rlen_now;
+        *wlen = wlen_now;
+
+        return rc;
+}
+
+
+/**
+ * do_write_read_transfer -
+ *
+ *
+ */
+int do_write_read_transfer(u8 fs, u8 *wbuf, u32 *wlen, u8 *rbuf, u32 *rlen)
+{
+        u32 sr, dr;
+        u32 wlen_now = 0, rlen_now = 0;
+        int rc = 0;
+
+        while (wlen_now < *wlen) {
+                sr = readl(spi_base + COMCERTO_SPI_SR);
+
+                if (sr & TFNF) {
+                        if (wlen_now < *wlen) {
+                                writew(cpu_to_le16((u16) *wbuf), spi_base + COMCERTO_SPI_DR);
+                                wbuf++;
+                                wlen_now++;
+                        }
+                }
+        }
+
+        while (rlen_now < *rlen) {
+                sr = readl(spi_base + COMCERTO_SPI_SR);
+
+                if (sr & (RFF | DCOL)) {
+                        /* read overrun, data collision */
+                        printf ("%s: sr=0x%x: Read Overrun.\n", __func__, sr);
+                        rc = -1;
+                        goto out;
+                }
+
+                if (sr & RFNE) {
+                        dr = readw(spi_base + COMCERTO_SPI_DR);
+                        if (rlen_now < *rlen) {
+                                *rbuf = (u8) (le16_to_cpu(dr) & 0xff);
+                                rbuf++;
+                                rlen_now++;
+                        } else {
+                                printf ("%s: Read Overflow.\n", __func__);
+                                /* read overflow */
+
+                                rc = -1;
+                                goto out;
+                        }
+                }
+        }
+
+      out:
+        *rlen = rlen_now;
+        *wlen = wlen_now;
+
+        return rc;
+}
+
+
+/**
+ * do_write_only_transfer8 -
+ *
+ *
+ */
+int do_write_only_transfer8(u8 *buf, u32 *len)
+{
+        u32 len_now;
+        int rc = 0;
+        u32 tmp = *len;
+        u32 dr = spi_base + COMCERTO_SPI_DR;
+        u32 txflr = spi_base + COMCERTO_SPI_TXFLR;
+
+        while (tmp)
+        {
+                len_now = 8 - readl(txflr);
+                if (len_now > tmp)
+                        len_now = tmp;
+
+                tmp -= len_now;
+
+                /* warm-up write fifo to avoid underruns */
+                while (len_now--)
+                {
+                        writew(cpu_to_le16((u16) *buf++), dr);
+                }
+        }
+
+        *len -= tmp;
+
+        return rc;
+}
+
+/**
+ * do_write_only_transfer -
+ *
+ *
+ */
+int do_write_only_transfer16(u16 *buf, u32 *len)
+{
+        u32 len_now;
+        int rc = 0;
+        u32 tmp = *len;
+        u32 dr = spi_base + COMCERTO_SPI_DR;
+        u32 txflr = spi_base + COMCERTO_SPI_TXFLR;
+
+        while (tmp)
+        {
+                len_now = 8 - readl(txflr);
+                if (len_now > tmp)
+                        len_now = tmp;
+
+                tmp -= len_now;
+
+                /* warm-up write fifo to avoid underruns */
+                while (len_now--)
+                        writew(cpu_to_le16(*buf++), dr);
+        }
+
+        *len -= tmp;
+
+        return rc;
+}
+
+
+/**
+ * do_read_only_transfer -
+ *
+ *
+ */
+int do_read_only_transfer8(u8 *buf, u32 *len)
+{
+        u32 len_now;
+        int rc = 0;
+        u32 tmp = *len;
+        u32 dr = spi_base + COMCERTO_SPI_DR;
+        u32 rxflr = spi_base + COMCERTO_SPI_RXFLR;
+
+        /* start the serial clock */
+        writew(0, dr);
+
+        while (tmp)
+        {
+                len_now = readl(rxflr);
+                if (len_now > tmp)
+                        len_now = tmp;
+
+                tmp -= len_now;
+
+                while (len_now--) {
+                        *buf = (u8) (le16_to_cpu(readw(dr)) & 0xff);
+                        buf++;
+                }
+        }
+
+        *len -= tmp;
+
+        return rc;
+}
+
+/**
+ * do_read_only_transfer -
+ *
+ *
+ */
+int do_read_only_transfer16(u16 *buf, u32 *len)
+{
+        u32 len_now;
+        int rc = 0;
+        u32 tmp = *len;
+        u32 dr = spi_base + COMCERTO_SPI_DR;
+        u32 rxflr = spi_base + COMCERTO_SPI_RXFLR;
+
+        /* start the serial clock */
+        writew(0, dr);
+
+        while (tmp)
+        {
+                len_now = readl(rxflr);
+                if (len_now > tmp)
+                        len_now = tmp;
+
+                tmp -= len_now;
+
+                while (len_now--) {
+                        *buf = le16_to_cpu(readw(dr));
+                        buf++;
+                }
+        }
+
+        *len -= tmp;
+
+        return rc;
+}
+
+static int c2k_spi_transfer(u8 chip_select,struct spi_transfer *t)
+{
+	unsigned int  op = t->mode & 0xff; 
+        u32 ctrlr0 = 0;
+        u32 baudr  = 0;
+        u32 ser    = 0;
+	u8 bits_per_word = 8;
+	u32 max_speed_hz = 4000000;
+        u32 hz;
+	u8 *txbuf;
+	u8 *rxbuf;
+	int spi_udelay;
+
+	ctrlr0 |= SPI_CTRLR0_SCPOL;
+	ctrlr0 |= SPI_CTRLR0_SCPH;
+	ctrlr0 |= (bits_per_word - 1) & 0xf;
+
+	hz = COMCERTO_DEFAULTAXICLK;
+	baudr = hz / max_speed_hz;
+	ser = (1 << chip_select) ;
+
+	spi_udelay = 1 + ((1000000 * bits_per_word) / max_speed_hz);
+
+        while(readl(spi_base + COMCERTO_SPI_SR) & BUSY);
+
+	writel(0, spi_base + COMCERTO_SPI_SSIENR);
+
+	txbuf = t->tx_buf;
+	rxbuf = t->rx_buf;
+
+	switch(op) {
+		case SPI_TRANSFER_MODE_WRITE_ONLY:
+
+			ctrlr0 |= (0x0001 << 8);
+			writel(ctrlr0, spi_base + COMCERTO_SPI_CTRLR0);
+			writel(baudr, spi_base + COMCERTO_SPI_BAUDR);
+			writel(ser, spi_base + COMCERTO_SPI_SER);
+			writel(8, spi_base + COMCERTO_SPI_RXFTLR);
+			writel(0, spi_base + COMCERTO_SPI_TXFTLR);
+			writel(0, spi_base + COMCERTO_SPI_IMR);
+			writel(1, spi_base + COMCERTO_SPI_SSIENR);
+
+			if (bits_per_word <= 8)
+				do_write_only_transfer8(txbuf, &t->len);
+			else
+				do_write_only_transfer16((u16*)txbuf, &t->len);
+
+			break;
+
+		case SPI_TRANSFER_MODE_READ_ONLY:
+
+			ctrlr0 |= (0x0002 << 8);
+			writel(ctrlr0, spi_base + COMCERTO_SPI_CTRLR0);
+			writel(baudr, spi_base + COMCERTO_SPI_BAUDR);
+			writel(ser, spi_base + COMCERTO_SPI_SER);
+			writel(8, spi_base + COMCERTO_SPI_RXFTLR);
+			writel(0, spi_base + COMCERTO_SPI_TXFTLR);
+			writel(0, spi_base + COMCERTO_SPI_IMR);
+			writel(1, spi_base + COMCERTO_SPI_SSIENR);
+
+			if (bits_per_word <= 8)
+				do_read_only_transfer8(rxbuf, &t->len);
+			else
+				do_read_only_transfer16((u16 *)rxbuf, &t->len);
+
+			break;
+
+		case SPI_TRANSFER_MODE_WRITE_READ:
+
+			ctrlr0 |= (0x0000 << 8);
+			writel(ctrlr0, spi_base + COMCERTO_SPI_CTRLR0);
+			writel(baudr, spi_base + COMCERTO_SPI_BAUDR);
+			writel(ser, spi_base + COMCERTO_SPI_SER);
+			writel(8, spi_base + COMCERTO_SPI_RXFTLR);
+			writel(0, spi_base + COMCERTO_SPI_TXFTLR);
+			writel(0, spi_base + COMCERTO_SPI_IMR);
+			writel(1, spi_base + COMCERTO_SPI_SSIENR);
+
+			do_write_read_transfer(bits_per_word, txbuf, &t->len, rxbuf, &t->len);
+
+                                break;
+
+                        default:
+                                printf ("Transfer mode not supported.\n");
+				return -1;
+                };
+
+                /* deassert the chip select at least for this long */
+                udelay (spi_udelay);
+
+        return 0;
+
+
+}
+
+
+int c2k_spi_write(u8 cs, const void *buf, size_t len)
+{
+        struct spi_transfer     t = {
+                        .tx_buf         = buf,
+                        .len            = len,
+			.mode		= SPI_TRANSFER_MODE_WRITE_ONLY,
+                };
+
+	c2k_spi_transfer(cs, &t);
+}
+
+int c2k_spi_read(u8 cs, void *buf, size_t len)
+{
+        struct spi_transfer     t = {
+                        .rx_buf         = buf,
+                        .len            = len,
+			.mode		= SPI_TRANSFER_MODE_READ_ONLY,
+                };
+
+	c2k_spi_transfer(cs, &t);
+}
+

cpu/arm_cortexa9/comcerto/zds.c

diff --git a/cpu/arm_cortexa9/comcerto/zds.c b/cpu/arm_cortexa9/comcerto/zds.c
new file mode 100644
index 0000000..4101849
--- /dev/null
+++ b/cpu/arm_cortexa9/comcerto/zds.c
@@ -0,0 +1,182 @@
+#include <config.h>
+#include <common.h>
+#include <asm/arch/gpio_c2000.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clkcore_c2000.h>
+
+#define TDMNTG_REG_RST          (1 << 0)
+#define FSYNC_FALL_EDGE         (1 << 1)
+#define NTG_DIV_RST_N           (1 << 5)
+#define NTG_EN                  (1 << 0)
+
+#define TDMNTG_ADDR_SPACE_BASEADDR       (COMCERTO_APB_CLK_BASE + 0x280)
+#define TDM_NTG_CLK_CTRL        (TDMNTG_ADDR_SPACE_BASEADDR + 0x00)
+#define TDM_NTG_INCR            (TDMNTG_ADDR_SPACE_BASEADDR + 0x04)
+#define TDM_FSYNC_GEN_CTRL      (TDMNTG_ADDR_SPACE_BASEADDR + 0x08)
+#define TDM_FSYNC_LOW           (TDMNTG_ADDR_SPACE_BASEADDR + 0x0C)
+#define TDM_FSYNC_HIGH          (TDMNTG_ADDR_SPACE_BASEADDR + 0x10)
+
+#define TDMNTG_DEFAULT_REF_CLK 500000000
+
+/* TDM Divider value to 24 */
+#define NTG_TDM_CLK_DIV 24
+
+
+struct comcerto_tdm_data {
+        u8 fsoutput; /* Generic Pad Control and Version ID Register[2] */
+        u8 fspolarity; /*  28 FSYNC_FALL(RISE)_EDGE */
+        u16 fshwidth; /* High_Phase_Width[10:0] */
+        u16 fslwidth; /* Low_Phase_Width[26:16]] */
+        u32 clockhz; /* INC_VALUE[29:0] According to the desired TDM clock output frequency, this field should be configured */
+        u8 clockout; /* IO Control Register[21]  hardware or software control selection  IO Control Register[20] pads are input (output) */
+        u8 tdmmux;
+        u32 tdmck;
+        u32 tdmfs;
+        u32 tdmdx;
+        u32 tdmdr;
+};
+
+//Legerity
+static struct comcerto_tdm_data comcerto_tdm_pdata = {
+        .fsoutput = 1, /* Generic Pad Control and Version ID Register[2] */
+        .fspolarity = 0, /* 28 FSYNC_FALL(RISE)_EDGE */
+        .fshwidth = 1, /* High_Phase_Width[10:0] */
+        .fslwidth = 0xFF, /* Low_Phase_Width[10:0] */
+        .clockhz = 2048000, /* INC_VALUE[29:0] According to the desired TDM clock output frequency, this field should be configured */
+        .clockout = 1, /* 0 -> set bit 21, clear bit 20 in COMCERTO_GPIO_IOCTRL_REG
+                          (software control, clock input)
+                          1 -> set bit 21 and 20 in COMCERTO_GPIO_IOCTRL_REG
+                          (software control, clock output)
+                          2 -> clear bit 21 in COMCERTO_GPIO_IOCTRL_REG (hardware control) */
+                /* TDM interface Muxing:0x0 - TDM block, 0x1 - ZDS block,
+                0x2 - GPIO[63:60] signals and 0x3 - MSIF block is selected */
+        .tdmmux = 0x1,
+};
+
+static void fsync_output_set(unsigned int fsoutput)
+{
+        if (fsoutput)
+        {
+                *(volatile u32*)COMCERTO_GPIO_TDM_MUX = (*(volatile u32*)(COMCERTO_GPIO_TDM_MUX) | (1 << 0));
+                *(volatile u32*)TDM_FSYNC_GEN_CTRL = (*(volatile u32*)(TDM_FSYNC_GEN_CTRL) | (1 << 0));
+        }
+        else
+        {
+                *(volatile u32*)COMCERTO_GPIO_TDM_MUX = (*(volatile u32*)(COMCERTO_GPIO_TDM_MUX) & ~(1 << 0));
+                *(volatile u32*)TDM_FSYNC_GEN_CTRL = (*(volatile u32*)(TDM_FSYNC_GEN_CTRL) & ~(1 << 0));
+        }
+}
+
+static void fsync_polarity_set(unsigned int fspolarity)
+{
+        /* 28 FSYNC_FALL(RISE)_EDGE */
+        if (fspolarity)
+                *(volatile u32*)TDM_FSYNC_GEN_CTRL = (*(volatile u32*)(TDM_FSYNC_GEN_CTRL) | FSYNC_FALL_EDGE);
+        else
+                *(volatile u32*)TDM_FSYNC_GEN_CTRL = (*(volatile u32*)(TDM_FSYNC_GEN_CTRL) & ~FSYNC_FALL_EDGE);
+}
+
+static void fsync_lphase_set(u32 fslwidth)
+{
+        /* Low_Phase_Width 7ff- maximum */
+        if (fslwidth > 0x7FF) {
+                printf("%s: Low Phase width value is out of range %#x > 0x7FF", __func__, fslwidth);
+                return;
+        }
+
+        *(volatile u32*)TDM_FSYNC_LOW = fslwidth;
+}
+
+static void fsync_hphase_set(u32 fshwidth)
+{
+        /* High_Phase_Width 7ff- maximum */
+        if (fshwidth > 0x7FF) {
+                printf("%s: High Phase width value is out of range %#x > 0x7FF", __func__, fshwidth);
+                return;
+        }
+
+        *(volatile u32*)TDM_FSYNC_HIGH = fshwidth;
+}
+
+static void clock_frequency_set(unsigned long clockhz)
+{
+        /* ntg_incr = 0x192A7371 for 49.152 MHz */
+        *(volatile u32*)TDM_NTG_INCR = 0x192A7371;
+}
+
+static void clock_output_set(unsigned long clockout)
+{
+        switch (clockout) {
+        case 0:
+                *(volatile u32*)COMCERTO_GPIO_BOOTSTRAP_OVERRIDE = ((0x2 << 12) | (*(volatile u32*)(COMCERTO_GPIO_BOOTSTRAP_OVERRIDE) & ~(0x3 << 12)));
+                break;
+        case 1:
+                *(volatile u32*)COMCERTO_GPIO_BOOTSTRAP_OVERRIDE = ((0x3 << 12) | (*(volatile u32*)(COMCERTO_GPIO_BOOTSTRAP_OVERRIDE) & ~(0x3 << 12)));
+                break;
+        case 2:
+                *(volatile u32*)COMCERTO_GPIO_BOOTSTRAP_OVERRIDE = ((0x0 << 12) | (*(volatile u32*)(COMCERTO_GPIO_BOOTSTRAP_OVERRIDE) & ~(0x3 << 12)));
+                break;
+        default:
+                printf("%s: Unknown clock output value\n", __func__);
+        }
+}
+
+static void tdm_mux_set(u32 tdmmux)
+{
+        switch (tdmmux){
+        case 0:
+                // TDM block selected
+                *(volatile u32*)COMCERTO_GPIO_MISC_PIN_SELECT_REG = ((0x0 << 4) | (*(volatile u32*)(COMCERTO_GPIO_MISC_PIN_SELECT_REG) & ~(0x3 << 4)));
+                break;
+
+        case 1:
+                // ZDS (Zarlink) block selected
+                *(volatile u32*)COMCERTO_GPIO_MISC_PIN_SELECT_REG = ((0x1 << 4) | (*(volatile u32*)(COMCERTO_GPIO_MISC_PIN_SELECT_REG) & ~(0x3 << 4)));
+                break;
+
+        case 2:
+                // GPIO[63:60] signals selected
+                *(volatile u32*)COMCERTO_GPIO_MISC_PIN_SELECT_REG = ((0x2 << 4) | (*(volatile u32*)(COMCERTO_GPIO_MISC_PIN_SELECT_REG) & ~(0x3 << 4)));
+                break;
+
+        case 3:
+                // MSIF (SiLabs) selected
+                *(volatile u32*)COMCERTO_GPIO_MISC_PIN_SELECT_REG = ((0x3 << 4) | (*(volatile u32*)(COMCERTO_GPIO_MISC_PIN_SELECT_REG) & ~(0x3 << 4)));
+                break;
+
+        default:
+                printf("%s: Unknown TDM MUX value\n", __func__);
+        }
+}
+
+void c2k_zds_init(void)
+{
+        printf("Initializing ZDS/NTG..\n");
+
+        // Take TDM NTG out of reset
+        *(volatile u32*)TDMNTG_RESET = (*(volatile u32*)(TDMNTG_RESET) & ~TDMNTG_REG_RST);
+
+	//PLL2
+	*(volatile u32*)TDMNTG_REF_CLK_CNTRL = (*(volatile u32*)(TDMNTG_REF_CLK_CNTRL) | ((1 << 2) | (1 << 0)));
+
+        // NTG REF CLK is derived from PLL2
+        *(volatile u32*)TDMNTG_REF_CLK_DIV_CNTRL = 0x3;
+        *(volatile u32*)TDM_NTG_CLK_CTRL = (NTG_DIV_RST_N | NTG_EN);
+        *(volatile u32*)TDM_CLK_CNTRL = 0x80; /* NTG = 24 x TDM */
+
+        /* Inital configuration of tdm bus */
+        fsync_polarity_set(comcerto_tdm_pdata.fspolarity);
+        fsync_lphase_set(comcerto_tdm_pdata.fslwidth);
+        fsync_hphase_set(comcerto_tdm_pdata.fshwidth);
+        clock_frequency_set(comcerto_tdm_pdata.clockhz);
+        clock_output_set(comcerto_tdm_pdata.clockout);
+        fsync_output_set(comcerto_tdm_pdata.fsoutput);
+        tdm_mux_set(comcerto_tdm_pdata.tdmmux);
+
+        *(volatile u32*)TDM_CLK_CNTRL = 0x18; //remove out of reset
+
+#define COMCERTO_GPIO1_OUTPUT_REG                       ((COMCERTO_APB_GPIO_BASE + 0xd0))
+        *(volatile u32*)COMCERTO_GPIO1_OUTPUT_REG = (0x1 << 30);
+
+}
+

cpu/arm_cortexa9/config.mk

diff --git a/cpu/arm_cortexa9/config.mk b/cpu/arm_cortexa9/config.mk
new file mode 100644
index 0000000..c883ce2
--- /dev/null
+++ b/cpu/arm_cortexa9/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+		     -msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v7a.
+#PLATFORM_CPPFLAGS += -march=armv7
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
+		    $(call cc-option,-malignment-traps,))

cpu/arm_cortexa9/cpu.c

diff --git a/cpu/arm_cortexa9/cpu.c b/cpu/arm_cortexa9/cpu.c
new file mode 100644
index 0000000..a29f7e2
--- /dev/null
+++ b/cpu/arm_cortexa9/cpu.c
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2008 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/system_c2000.h>
+#include <asm/arch/cache_c2000.h>
+#ifndef CONFIG_L2_OFF
+#include <asm/arch/sys_proto.h>
+#endif
+
+static void cache_flush(void);
+
+int cleanup_before_linux(void)
+{
+	unsigned int i;
+
+#if 0
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+	disable_interrupts();
+
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* invalidate I-cache */
+	cache_flush();
+
+#ifndef CONFIG_L2_OFF
+	/* turn off L2 cache */
+	l2_cache_disable();
+	/* invalidate L2 cache also */
+	v7_flush_dcache_all(get_device_type());
+#endif
+	i = 0;
+	/* mem barrier to sync up things */
+	asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
+
+#ifndef CONFIG_L2_OFF
+	l2_cache_enable();
+#endif
+#endif
+	return 0;
+}
+
+static void cache_flush(void)
+{
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	disable_interrupts();
+	reset_cpu (0);
+	return(0);
+}
+

cpu/arm_cortexa9/start.S

diff --git a/cpu/arm_cortexa9/start.S b/cpu/arm_cortexa9/start.S
new file mode 100644
index 0000000..55e03ac
--- /dev/null
+++ b/cpu/arm_cortexa9/start.S
@@ -0,0 +1,446 @@
+/*
+ * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
+ *
+ * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
+ *
+ * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+.globl _start
+_start: b	reset
+
+/*************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************/
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+	.word _start
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
+
+/*
+ * the actual reset code
+ */
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0, cpsr
+	bic	r0, r0, #0x1f
+	orr	r0, r0, #0xd3
+	msr	cpsr,r0
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl	cpu_init_crit
+#endif
+
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+relocate:				@ relocate U-Boot to RAM
+	adr	r0, _start		@ r0 <- current position of code
+	ldr	r1, _TEXT_BASE		@ test if we run from flash or RAM
+	cmp	r0, r1			@ don't reloc during debug
+	beq	stack_setup
+
+	ldr	r2, _armboot_start
+	ldr	r3, _bss_start
+	sub	r2, r3, r2		@ r2 <- size of armboot
+	add	r2, r0, r2		@ r2 <- source end address
+
+copy_loop:				@ copy 32 bytes at a time
+	ldmia	r0!, {r3 - r10}		@ copy from source address [r0]
+	stmia	r1!, {r3 - r10}		@ copy to   target address [r1]
+	cmp	r0, r2			@ until source end addreee [r2]
+	ble	copy_loop
+#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
+
+	/* Set up the stack */
+stack_setup:
+	ldr	r0, _TEXT_BASE		@ upper 128 KiB: relocated uboot
+	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
+	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
+#ifdef CONFIG_USE_IRQ
+	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
+#endif
+	sub	sp, r0, #12		@ leave 3 words for abort-stack
+	and	sp, sp, #~7		@ 8 byte alinged for (ldr/str)d
+
+	/* Clear BSS (if any). Is below tx (watch load addr - need space) */
+clear_bss:
+	ldr	r0, _bss_start		@ find start of bss segment
+	ldr	r1, _bss_end		@ stop here
+	mov	r2, #0x00000000		@ clear value
+clbss_l:
+	str	r2, [r0]		@ clear BSS location
+	cmp	r0, r1			@ are we at the end yet
+	add	r0, r0, #4		@ increment clear index pointer
+	bne	clbss_l			@ keep clearing till at end
+
+	ldr	pc, _start_armboot	@ jump to C code
+
+_start_armboot: .word start_armboot
+
+/*************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************/
+cpu_init_crit:
+	/*
+	 * Invalidate L1 I/D
+	 */
+	mov	r0, #0			@ set up for MCR
+	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
+	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
+	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
+	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
+	orr	r0, r0, #0x00000800	@ set bit 12 (Z---) BTB
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Jump to board specific initialization...
+	 * The Mask ROM will have already initialized
+	 * basic memory. Go here to bump up clock rate and handle
+	 * wake up conditions.
+	 */
+	mov	ip, lr			@ persevere link reg across call
+	bl	lowlevel_init		@ go setup pll,mux,memory
+	mov	lr, ip			@ restore link
+	mov	pc, lr			@ back to my caller
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current
+						@ user stack
+	stmia	sp, {r0 - r12}			@ Save user registers (now in
+						@ svc mode) r0-r12
+
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
+	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8)	@ set base 2 words into abort
+						@ stack
+	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc
+						@ and cpsr (into parm regs)
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp				@ save current stack into r0
+						@ (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC			@ !! R8 NEEDS to be saved !!
+						@ a reserved stack spot would
+						@ be good.
+	stmdb	r8, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r8, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]			@ Save CPSR
+	str	r0, [r8, #8]			@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into
+						@ cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, _armboot_start		@ setup our mode stack (enter
+						@ in banked mode)
+	sub	r13, r13, #(CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
+	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple
+						@ spots for abort stack
+
+	str	lr, [r13]			@ save caller lr in position 0
+						@ of saved stack
+	mrs	lr, spsr			@ get the spsr
+	str	lr, [r13, #4]			@ save spsr in position 1 of
+						@ saved stack
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13			@ switch modes, make sure
+						@ moves will execute
+	mov	lr, pc				@ capture return pc
+	movs	pc, lr				@ jump to next instruction &
+						@ switch modes.
+	.endm
+
+	.macro get_bad_stack_swi
+	sub	r13, r13, #4			@ space on current stack for
+						@ scratch reg.
+	str	r0, [r13]			@ save R0's value.
+	ldr	r0, _armboot_start		@ get data regions start
+	sub	r0, r0, #(CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
+	sub	r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)	@ move past gbl and a couple
+						@ spots for abort stack
+	str	lr, [r0]			@ save caller lr in position 0
+						@ of saved stack
+	mrs	r0, spsr			@ get the spsr
+	str	lr, [r0, #4]			@ save spsr in position 1 of
+						@ saved stack
+	ldr	r0, [r13]			@ restore r0
+	add	r13, r13, #4			@ pop stack entry
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack_swi
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effective fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+
+/*
+ *	v7_flush_dcache_all()
+ *
+ *	Flush the whole D-cache.
+ *
+ *	Corrupted registers: r0-r5, r7, r9-r11
+ *
+ *	- mm	- mm_struct describing address space
+ */
+	.align 5
+.global v7_flush_dcache_all
+v7_flush_dcache_all:
+	stmfd	r13!, {r0 - r5, r7, r9 - r12, r14}
+
+	mov	r7, r0				@ take a backup of device type
+	cmp	r0, #0x3			@ check if the device type is
+						@ GP
+	moveq r12, #0x1				@ set up to invalide L2
+smi:	.word 0x01600070			@ Call SMI monitor (smieq)
+	cmp	r7, #0x3			@ compare again in case its
+						@ lost
+	beq	finished_inval			@ if GP device, inval done
+						@ above
+
+	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
+	ands	r3, r0, #0x7000000		@ extract loc from clidr
+	mov	r3, r3, lsr #23			@ left align loc bit field
+	beq	finished_inval			@ if loc is 0, then no need to
+						@ clean
+	mov	r10, #0				@ start clean at cache level 0
+inval_loop1:
+	add	r2, r10, r10, lsr #1		@ work out 3x current cache
+						@ level
+	mov	r1, r0, lsr r2			@ extract cache type bits from
+						@ clidr
+	and	r1, r1, #7			@ mask of the bits for current
+						@ cache only
+	cmp	r1, #2				@ see what cache we have at
+						@ this level
+	blt	skip_inval			@ skip if no cache, or just
+						@ i-cache
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
+						@ in cssr
+	mov	r2, #0				@ operand for mcr SBZ
+	mcr	p15, 0, r2, c7, c5, 4		@ flush prefetch buffer to
+						@ sych the new cssr&csidr,
+						@ with armv7 this is 'isb',
+						@ but we compile with armv5
+	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
+	and	r2, r1, #7			@ extract the length of the
+						@ cache lines
+	add	r2, r2, #4			@ add 4 (line length offset)
+	ldr	r4, =0x3ff
+	ands	r4, r4, r1, lsr #3		@ find maximum number on the
+						@ way size
+	clz	r5, r4				@ find bit position of way
+						@ size increment
+	ldr	r7, =0x7fff
+	ands	r7, r7, r1, lsr #13		@ extract max number of the
+						@ index size
+inval_loop2:
+	mov	r9, r4				@ create working copy of max
+						@ way size
+inval_loop3:
+	orr	r11, r10, r9, lsl r5		@ factor way and cache number
+						@ into r11
+	orr	r11, r11, r7, lsl r2		@ factor index number into r11
+	mcr	p15, 0, r11, c7, c6, 2		@ invalidate by set/way
+	subs	r9, r9, #1			@ decrement the way
+	bge	inval_loop3
+	subs	r7, r7, #1			@ decrement the index
+	bge	inval_loop2
+skip_inval:
+	add	r10, r10, #2			@ increment cache number
+	cmp	r3, r10
+	bgt	inval_loop1
+finished_inval:
+	mov	r10, #0				@ swith back to cache level 0
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
+						@ in cssr
+	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
+						@ with armv7 this is 'isb',
+						@ but we compile with armv5
+
+	ldmfd	r13!, {r0 - r5, r7, r9 - r12, pc}

drivers/Makefile

diff --git a/drivers/Makefile b/drivers/Makefile
index 5a369df..c016728 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -49,6 +49,7 @@
 	  usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
 	  videomodes.o w83c553f.o \
 	  ks8695eth.o \
+	  comcerto_gem.o comcerto_gem_AL.o \
 	  pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o	\
 	  rpx_pcmcia.o \
 	  fsl_i2c.o

drivers/c2000_eth/Makefile

diff --git a/drivers/c2000_eth/Makefile b/drivers/c2000_eth/Makefile
new file mode 100644
index 0000000..36e343e
--- /dev/null
+++ b/drivers/c2000_eth/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB 	:= $(obj)libcomcerto_pfe.a
+
+COBJS 	:= c2000_ethernet.o pfe_firmware.o pfe.o pfe_driver.o ar8328.o
+
+SRCS 	:= $(COBJS:.o=.c)
+OBJS 	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

drivers/c2000_eth/ar8328.c

diff --git a/drivers/c2000_eth/ar8328.c b/drivers/c2000_eth/ar8328.c
new file mode 100644
index 0000000..7b4249a
--- /dev/null
+++ b/drivers/c2000_eth/ar8328.c
@@ -0,0 +1,459 @@
+#include <common.h>
+#include <miiphy.h>
+#include "ar8328.h"
+
+#define S17_LAN_PORT_VLAN          1
+#define S17_WAN_PORT_VLAN          2
+
+#define ENET_UNIT_GE1 1  
+#define ENET_UNIT_GE0 0 /* Connected to the switch */
+
+#define TRUE    1
+#define FALSE   0
+
+#define S17_PHY0_ADDR   0x0
+#define S17_PHY1_ADDR   0x1
+#define S17_PHY2_ADDR   0x2
+#define S17_PHY3_ADDR   0x3
+#define S17_PHY4_ADDR   0x4
+#define S17_IND_PHY 4
+
+/*
+ * Track per-PHY port information.
+ */
+typedef struct {
+    BOOL   isEnetPort;       /* normal enet port */
+    BOOL   isPhyAlive;       /* last known state of link */
+    int    ethUnit;          /* MAC associated with this phy port */
+    uint32_t phyBase;
+    uint32_t phyAddr;          /* PHY registers associated with this phy port */
+    uint32_t VLANTableSetting; /* Value to be written to VLAN table */
+} athrPhyInfo_t;
+
+/*
+ * Per-PHY information, indexed by PHY unit number
+ * MAC port 0 - CPU port 0x100
+ * All ports are connected to GE0 of the SoC MAC
+ * LAN/WAN seperation by VLAN tags (port 0-3 with VLANID 1; port 4 with VLANID 2
+ */
+static athrPhyInfo_t athrPhyInfo[] = {
+    {TRUE,   /* phy port 0 -- MAC port 1 0x200 */
+     FALSE,
+     ENET_UNIT_GE0,
+     0,
+     S17_PHY0_ADDR,
+     S17_LAN_PORT_VLAN
+    },
+
+    {TRUE,   /* phy port 1 -- MAC port 2 0x300 */
+     FALSE,
+     ENET_UNIT_GE0,
+     0,
+     S17_PHY1_ADDR,
+     S17_LAN_PORT_VLAN
+    },
+
+    {TRUE,   /* phy port 2 -- MAC port 3 0x400 */
+     FALSE,
+     ENET_UNIT_GE0,
+     0,
+     S17_PHY2_ADDR, 
+     S17_LAN_PORT_VLAN
+    },
+
+    {TRUE,   /* phy port 3 -- MAC port 4 0x500 */
+     FALSE,
+     ENET_UNIT_GE0,
+     0,
+     S17_PHY3_ADDR, 
+     S17_LAN_PORT_VLAN
+    },
+
+    {TRUE,   /* phy port 4 -- WAN port or MAC port 5 0x600 */
+     FALSE,
+     ENET_UNIT_GE1,
+     0,
+     S17_PHY4_ADDR, 
+     S17_WAN_PORT_VLAN   /* set as WAN port */
+    },
+    
+    {FALSE,  /* phy port 5 -- CPU port (no RJ45 connector) */
+     TRUE,
+     ENET_UNIT_GE0,
+     0,
+     0x00, 
+     S17_LAN_PORT_VLAN    /* Send to all ports */
+    },
+};
+
+#define S17_PHY_MAX 5
+
+/* Range of valid PHY IDs is [MIN..MAX] */
+#define S17_ID_MIN 0
+#define S17_ID_MAX (S17_PHY_MAX-1)
+
+/* Convenience macros to access myPhyInfo */
+#define S17_IS_ENET_PORT(phyUnit) (athrPhyInfo[phyUnit].isEnetPort)
+#define S17_IS_PHY_ALIVE(phyUnit) (athrPhyInfo[phyUnit].isPhyAlive)
+#define S17_ETHUNIT(phyUnit) (athrPhyInfo[phyUnit].ethUnit)
+#define S17_PHYBASE(phyUnit) (athrPhyInfo[phyUnit].phyBase)
+#define S17_PHYADDR(phyUnit) (athrPhyInfo[phyUnit].phyAddr)
+#define S17_VLAN_TABLE_SETTING(phyUnit) (athrPhyInfo[phyUnit].VLANTableSetting)
+
+int athrs17_init(char *devname)
+{
+	int phy_addr; 
+	unsigned int dummy;
+	
+	//configure the RGMII
+	/* FIXME Configure broadcast ports: the configuration below
+	 * will broadcast on ports 0-5 of the switch.
+	 */
+	athrs17_reg_write(devname, S17_GLOFW_CTRL1_REG, \
+			S17_BROAD_DPALL | S17_MULTI_FLOOD_DPALL | S17_UNI_FLOOD_DPALL);
+	/* FIXME bit 30 of the PWS_REG is marked as reserved in the datasheet. */
+	athrs17_reg_write(devname, S17_PWS_REG, S17_PWS_CHIP_AR8327);
+
+	/* Set delays for MAC0 */
+	athrs17_reg_write(devname, S17_P0PAD_MODE_REG, S17_MAC0_RGMII_EN | S17_MAC0_RGMII_TXCLK_DELAY | \
+			S17_MAC0_RGMII_RXCLK_DELAY | (1 << S17_MAC0_RGMII_TXCLK_SHIFT) | \
+			(1 << S17_MAC0_RGMII_RXCLK_SHIFT));
+	/* Set bit 24 to enable MAC0 RGMII delay; set MAC6 as PHY mode (PHY4), QCA */
+	athrs17_reg_write(devname, S17_P6PAD_MODE_REG, S17_PHY4_RGMII_EN | S17_MAC6_RGMII_RXCLK_DELAY | \
+			(0 << S17_MAC6_RGMII_RXCLK_SHIFT));
+	/* Disable MAC5 and MAC6 (due to PHY4), QCA */
+	athrs17_reg_write(devname, S17_P5STATUS_REG, 0);
+	athrs17_reg_write(devname, S17_P6STATUS_REG, 0);
+	
+	athrs17_reg_write(devname, S17_P0STATUS_REG, S17_PORT_STATUS_DEFAULT);
+
+	/* AR8327/AR8328 v1.0 fixup */
+	if ((athrs17_reg_read(devname, S17_MASK_CTRL_REG) & 0xffff) == S17_CHIPID_V1_0)
+	{
+		for (phy_addr = 0x0; phy_addr <= S17_PHY_MAX; phy_addr++)
+		{
+			/* For 100M waveform */
+			miiphy_debug_write(devname, phy_addr, 0x0, 0x02ea);
+			/* Turn On Gigabit Clock */
+			miiphy_debug_write(devname, phy_addr, 0x3d, 0x68a0);
+		}
+	}
+	/* Set delays for PHY4 (connected to MAC5)
+	*/
+	dummy = miiphy_debug_read(devname, S17_PHY4_ADDR, 0x0);
+	dummy |= (1 << 15); // Enable RGMII Rx clock delay
+	miiphy_debug_write(devname, S17_PHY4_ADDR, 0x0, dummy);
+	dummy = miiphy_debug_read(devname, S17_PHY4_ADDR, 0x5);
+	dummy |= (1 << 8); // Enable RGMII Tx clock delay
+	miiphy_debug_write(devname, S17_PHY4_ADDR, 0x5, dummy);
+
+
+	/* enable HOL by default */
+	for (phy_addr = 0; phy_addr < S17_MAC_MAX; phy_addr++)
+	{
+		switch (phy_addr) {
+			case 0:
+			case 5:
+			case 6:
+				athrs17_reg_write(devname, S17_PORT0_HOL_CTRL0 + phy_addr * 8, \
+						S17_HOL_CTRL0_WAN);
+				break;
+
+			default:
+				athrs17_reg_write(devname, S17_PORT0_HOL_CTRL0 + phy_addr * 8, \
+						S17_HOL_CTRL0_LAN);
+				break;
+		}
+
+		athrs17_reg_write(devname, S17_PORT0_HOL_CTRL1 + phy_addr * 8, \
+				S17_HOL_CTRL1_DEFAULT);
+	}
+
+	/* LED control */
+	athrs17_reg_write(devname, S17_LED_CTRL0_REG, 0xffb7ffb7);
+	athrs17_reg_write(devname, S17_LED_CTRL1_REG, 0xffb7ffb7);
+	athrs17_reg_write(devname, S17_LED_CTRL2_REG, 0xffb7ffb7);
+
+	printf ("%s:done\n",__func__);
+
+	return 0;
+
+}
+
+/******************************************************************************
+*
+* athrs17_phy_is_link_alive - test to see if the specified link is alive
+*
+* RETURNS:
+*    TRUE  --> link is alive
+*    FALSE --> link is down
+*/
+BOOL
+athrs17_phy_is_link_alive(char *devname,int phyUnit)
+{
+    uint16_t phyHwStatus;
+    uint32_t phyAddr;
+
+    phyAddr = S17_PHYADDR(phyUnit);
+ 
+    miiphy_read (devname, phyAddr, S17_PHY_SPEC_STATUS, &phyHwStatus);	
+
+    if (phyHwStatus & S17_STATUS_LINK_PASS)
+        return TRUE;
+
+    printf("phy%d link down\n",phyUnit);	
+    return FALSE;
+}
+
+/******************************************************************************
+*
+* athrs17_phy_stat 
+*
+*/
+
+int
+athrs17_phy_stat(char *devname)
+{
+    uint16_t  phyHwStatus;
+    uint32_t  phyAddr;
+    int       phyUnit;	
+    int       ii = 200;
+
+    for (phyUnit=0; phyUnit < S17_PHY_MAX; phyUnit++) {
+
+        phyAddr = S17_PHYADDR(phyUnit);
+
+        if (athrs17_phy_is_link_alive(devname, phyUnit)) {
+
+            do {
+		miiphy_read (devname, phyAddr, S17_PHY_SPEC_STATUS, &phyHwStatus);
+		        if(phyHwStatus & S17_STATUS_RESOLVED)
+			        break;
+                udelay(10*1000);
+            }while(--ii);
+            
+            phyHwStatus = ((phyHwStatus & S17_STATUS_LINK_MASK) >>
+                           S17_STATUS_LINK_SHIFT);
+
+	    printf("phy%d phyhwstat:%x\n",phyUnit,phyHwStatus);
+        } 
+
+    }
+    return 0;
+}
+
+/******************************************************************************
+*
+* athrs17_phy_init - reset and setup the PHY associated 
+*
+* Resets the associated PHY port.
+*
+* RETURNS:
+*    TRUE  --> associated PHY is alive
+*    FALSE --> no LINKs on this ethernet unit
+*/
+
+int
+athrs17_phy_init(char *devname, int phyUnit)
+{
+	uint16_t  phyHwStatus;
+	uint16_t  timeout;
+	int       liveLinks = 0;
+	uint32_t  phyBase = 0;
+	uint32_t  phyAddr = 0;
+
+	printf("athrs17_phy_init %d\n", phyUnit);
+
+	phyBase = S17_PHYBASE(phyUnit);
+	phyAddr = S17_PHYADDR(phyUnit);
+
+	miiphy_write(devname, phyAddr, S17_AUTONEG_ADVERT,
+			S17_ADVERTISE_ALL);
+
+	miiphy_write(devname, phyAddr, S17_1000BASET_CONTROL,
+			S17_ADVERTISE_1000FULL);
+
+	/* Reset PHYs*/
+	miiphy_write(devname, phyAddr, S17_PHY_CONTROL,
+			S17_CTRL_AUTONEGOTIATION_ENABLE 
+			| S17_CTRL_SOFTWARE_RESET);
+
+	/*
+	 * After the phy is reset, it takes a little while before
+	 * it can respond properly.
+	 */
+	//FIXME: Now since this function is called multiple time for each LAN PHY the overrall delay
+	//will also increase. Maybe this is not required as the phy status is being check 
+	//So this is subjected to change during the bringup
+	udelay(1000*1000);
+
+
+	/*
+	 * Wait up to 3 seconds for ALL associated PHYs to finish
+	 * autonegotiation.  The only way we get out of here sooner is
+	 * if ALL PHYs are connected AND finish autonegotiation.
+	 */
+
+	timeout=20;
+	for (;;) {
+		miiphy_read (devname, phyAddr, S17_PHY_CONTROL, &phyHwStatus);
+
+		if (S17_RESET_DONE(phyHwStatus)) {
+			printf(
+					("Port %d, Neg Success\n", phyUnit));
+
+			break;
+		}
+		if (timeout == 0) {
+			printf("Port %d, Negogiation timeout\n", phyUnit);
+			break;
+		}
+		if (--timeout == 0) {
+			printf("Port %d, Negogiation timeout\n", phyUnit);
+			break;
+		}
+
+		udelay(150*1000);
+	}
+
+	/*
+	 * The PHY have had adequate time to autonegotiate.
+	 * Now initialize software status.
+	 *
+	 * It's possible that some ports may take a bit longer
+	 * to autonegotiate; but we can't wait forever.  They'll
+	 * get noticed by mv_phyCheckStatusChange during regular
+	 * polling activities.
+	 */
+
+	/* fine-tune PHY 0 and PHY 1*/
+	if ((phyUnit == 0) || (phyUnit == 1))
+	{
+		miiphy_write(devname, S17_PHYADDR(phyUnit), S17_MMD_CTRL_REG, 0x3);
+		miiphy_write(devname, S17_PHYADDR(phyUnit), S17_MMD_DATA_REG, 0x8007);
+		miiphy_write(devname, S17_PHYADDR(phyUnit), S17_MMD_CTRL_REG, 0x4003);
+		miiphy_write(devname, S17_PHYADDR(phyUnit), S17_MMD_DATA_REG, 0x8315);
+	}
+
+	/* fine-tune PHYs */
+	miiphy_write(devname, S17_PHYADDR(phyUnit), S17_MMD_CTRL_REG, 0x3);
+	miiphy_write(devname, S17_PHYADDR(phyUnit), S17_MMD_DATA_REG, 0x800d);
+	miiphy_write(devname, S17_PHYADDR(phyUnit), S17_MMD_CTRL_REG, 0x4003);
+	miiphy_write(devname, S17_PHYADDR(phyUnit), S17_MMD_DATA_REG, 0x103f);
+
+	miiphy_debug_write(devname, S17_PHYADDR(phyUnit), 0x3d, 0x6860);
+	
+	/* for PHY4, QCA */
+	if (phyUnit == S17_PHY4_ADDR)
+	{
+		miiphy_debug_write(devname, S17_PHYADDR(phyUnit), 0x12, 0x4c0c);
+		miiphy_debug_write(devname, S17_PHYADDR(phyUnit), 0x0, 0x82ee);
+		miiphy_debug_write(devname, S17_PHYADDR(phyUnit), 0x5, 0x3d46);
+		miiphy_debug_write(devname, S17_PHYADDR(phyUnit), 0xb, 0xbc20);
+	}
+
+	if (athrs17_phy_is_link_alive(devname, phyUnit)) {
+		liveLinks++;
+		S17_IS_PHY_ALIVE(phyUnit) = TRUE;
+	} else {
+		S17_IS_PHY_ALIVE(phyUnit) = FALSE;
+	}
+
+//	printf("eth%d: Phy Specific Status=%4.4x\n", mdev->read(mdev, S17_PHYADDR(phyUnit),S17_PHY_SPEC_STATUS));
+//	printk("Phy setup Complete\n"); 
+
+
+}
+
+int
+athrs17_phy_setup(char *devname, int phyUnit)
+{
+	int i;
+
+        if(phyUnit == S17_PHY4_ADDR)
+        {//WAN PHY
+                athrs17_phy_init(devname, phyUnit);
+        }
+        else if(phyUnit < S17_PHY4_ADDR)
+        {//LAN PHYs
+                for(i = 0 ; i <S17_PHY4_ADDR; i++)
+                {
+                        athrs17_phy_init(devname, i);
+                }
+        }
+}
+
+
+unsigned int athrs17_reg_read(char *devname, unsigned int reg_addr)
+{
+	uint32_t reg_word_addr;
+	uint32_t phy_addr, tmp_val, reg_val;
+	uint16_t phy_val;
+	uint8_t phy_reg;
+
+	/* change reg_addr to 16-bit word address, 32-bit aligned */
+	reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+	/* configure register high address */
+	phy_addr = 0x18;
+	phy_reg = 0x0;
+	phy_val = (uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+	miiphy_write (devname, phy_addr, phy_reg, phy_val);	
+
+	/* For some registers such as MIBs, since it is read/clear, we should */
+	/* read the lower 16-bit register then the higher one */
+
+	/* read register in lower address */
+	phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+	phy_reg = (uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+	miiphy_read (devname, phy_addr, phy_reg, &reg_val);
+
+	/* read register in higher address */
+	reg_word_addr++;
+	phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+	phy_reg = (uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+	miiphy_read (devname, phy_addr, phy_reg, &tmp_val);
+	reg_val |= (tmp_val << 16);
+
+//	printf("%s: reg 0x%x val 0x%x\n",__func__, reg_addr, reg_val);
+
+	return reg_val;   
+}
+
+void athrs17_reg_write(char *devname, unsigned int reg_addr, unsigned int reg_val)
+{
+	uint32_t reg_word_addr;
+	uint32_t phy_addr;
+	uint16_t phy_val;
+	uint8_t phy_reg;
+
+//	printf("%s: reg 0x%x val 0x%x\n",__func__, reg_addr, reg_val);
+
+	/* change reg_addr to 16-bit word address, 32-bit aligned */
+	reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+	/* configure register high address */
+    phy_addr = 0x18;
+    phy_reg = 0x0;
+    phy_val = (uint16_t) ((reg_word_addr >> 8) & 0x3ff);  /* bit16-8 of reg address */
+    miiphy_write (devname, phy_addr, phy_reg, phy_val);	
+
+    /* For S17 registers such as ARL and VLAN, since they include BUSY bit */
+    /* in higher address, we should write the lower 16-bit register then the */
+    /* higher one */
+
+    /* write register in lower address */
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (uint16_t) (reg_val & 0xffff);
+    miiphy_write (devname, phy_addr, phy_reg, phy_val);	
+    
+    /* read register in higher address */
+    reg_word_addr++;
+    phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+    phy_reg = (uint8_t) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+    phy_val = (uint16_t) ((reg_val >> 16) & 0xffff);
+    miiphy_write (devname, phy_addr, phy_reg, phy_val);	
+
+}
+

drivers/c2000_eth/ar8328.h

diff --git a/drivers/c2000_eth/ar8328.h b/drivers/c2000_eth/ar8328.h
new file mode 100644
index 0000000..93e91b4
--- /dev/null
+++ b/drivers/c2000_eth/ar8328.h
@@ -0,0 +1,499 @@
+#ifndef _ATHRS17_PHY_H
+#define _ATHRS17_PHY_H
+
+/*****************/
+/* PHY Registers */
+/*****************/
+#define S17_PHY_CONTROL                 0
+#define S17_PHY_STATUS                  1
+#define S17_PHY_ID1                     2
+#define S17_PHY_ID2                     3
+#define S17_AUTONEG_ADVERT              4
+#define S17_LINK_PARTNER_ABILITY        5
+#define S17_AUTONEG_EXPANSION           6
+#define S17_NEXT_PAGE_TRANSMIT          7
+#define S17_LINK_PARTNER_NEXT_PAGE      8
+#define S17_1000BASET_CONTROL           9
+#define S17_1000BASET_STATUS            10
+#define S17_MMD_CTRL_REG		13
+#define S17_MMD_DATA_REG    	        14
+#define S17_PHY_SPEC_CONTROL            16
+#define S17_PHY_SPEC_STATUS             17
+#define S17_PHY_INTR_ENABLE             18
+#define S17_PHY_INTR_STATUS             19
+#define S17_DEBUG_PORT_ADDRESS          29
+#define S17_DEBUG_PORT_DATA             30
+
+/* S17 CSR Registers */
+#define S17_MASK_CTRL_REG               0x0000
+#define S17_P0PAD_MODE_REG              0x0004
+#define S17_P5PAD_MODE_REG              0x0008
+#define S17_P6PAD_MODE_REG              0x000c
+#define S17_PWS_REG                     0x0010
+#define S17_GLOBAL_INT0_REG             0x0020
+#define S17_GLOBAL_INT1_REG             0x0024
+#define S17_GLOBAL_INTMASK0             0x0028
+#define S17_GLOBAL_INTMASK1             0x002c
+#define S17_MODULE_EN_REG               0x0030
+#define S17_MIB_REG                     0x0034
+#define S17_INTF_HIADDR_REG             0x0038
+#define S17_MDIO_CTRL_REG               0x003c
+#define S17_BIST_CTRL_REG               0x0040
+#define S17_BIST_REC_REG                0x0044
+#define S17_SERVICE_REG                 0x0048
+#define S17_LED_CTRL0_REG               0x0050
+#define S17_LED_CTRL1_REG               0x0054
+#define S17_LED_CTRL2_REG               0x0058
+#define S17_LED_CTRL3_REG               0x005c
+#define S17_MACADDR0_REG                0x0060
+#define S17_MACADDR1_REG                0x0064
+#define S17_MAX_FRAME_SIZE_REG          0x0078
+#define S17_P0STATUS_REG                0x007c
+#define S17_P1STATUS_REG                0x0080
+#define S17_P2STATUS_REG                0x0084
+#define S17_P3STATUS_REG                0x0088
+#define S17_P4STATUS_REG                0x008c
+#define S17_P5STATUS_REG                0x0090
+#define S17_P6STATUS_REG                0x0094
+#define S17_HDRCTRL_REG                 0x0098
+#define S17_P0HDRCTRL_REG               0x009c
+#define S17_P1HDRCTRL_REG               0x00A0
+#define S17_P2HDRCTRL_REG               0x00a4
+#define S17_P3HDRCTRL_REG               0x00a8
+#define S17_P4HDRCTRL_REG               0x00ac
+#define S17_P5HDRCTRL_REG               0x00b0
+#define S17_P6HDRCTRL_REG               0x00b4
+#define S17_SGMII_CTRL_REG              0x00e0
+#define S17_EEE_CTRL_REG		0x0100
+
+/* ACL Registers */
+#define S17_ACL_FUNC0_REG               0x0400
+#define S17_ACL_FUNC1_REG               0x0404
+#define S17_ACL_FUNC2_REG               0x0408
+#define S17_ACL_FUNC3_REG               0x040c
+#define S17_ACL_FUNC4_REG               0x0410
+#define S17_ACL_FUNC5_REG               0x0414
+#define S17_PRIVATE_IP_REG              0x0418
+#define S17_P0VLAN_CTRL0_REG            0x0420
+#define S17_P0VLAN_CTRL1_REG            0x0424
+#define S17_P1VLAN_CTRL0_REG            0x0428
+#define S17_P1VLAN_CTRL1_REG            0x042c
+#define S17_P2VLAN_CTRL0_REG            0x0430
+#define S17_P2VLAN_CTRL1_REG            0x0434
+#define S17_P3VLAN_CTRL0_REG            0x0438
+#define S17_P3VLAN_CTRL1_REG            0x043c
+#define S17_P4VLAN_CTRL0_REG            0x0440
+#define S17_P4VLAN_CTRL1_REG            0x0444
+#define S17_P5VLAN_CTRL0_REG            0x0448
+#define S17_P5VLAN_CTRL1_REG            0x044c
+#define S17_P6VLAN_CTRL0_REG            0x0450
+#define S17_P6VLAN_CTRL1_REG            0x0454
+
+/* Table Lookup Registers */
+#define S17_ATU_DATA0_REG               0x0600
+#define S17_ATU_DATA1_REG               0x0604
+#define S17_ATU_DATA2_REG               0x0608
+#define S17_ATU_FUNC_REG                0x060C
+#define S17_VTU_FUNC0_REG               0x0610
+#define S17_VTU_FUNC1_REG               0x0614
+#define S17_ARL_CTRL_REG                0x0618
+#define S17_GLOFW_CTRL0_REG             0x0620
+#define S17_GLOFW_CTRL1_REG             0x0624
+#define S17_GLOLEARN_LIMIT_REG          0x0628
+#define S17_TOS_PRIMAP_REG0             0x0630
+#define S17_TOS_PRIMAP_REG1             0x0634
+#define S17_TOS_PRIMAP_REG2             0x0638
+#define S17_TOS_PRIMAP_REG3             0x063c
+#define S17_TOS_PRIMAP_REG4             0x0640
+#define S17_TOS_PRIMAP_REG5             0x0644
+#define S17_TOS_PRIMAP_REG6             0x0648
+#define S17_TOS_PRIMAP_REG7             0x064c
+#define S17_VLAN_PRIMAP_REG0            0x0650
+#define S17_LOOP_CHECK_REG              0x0654
+#define S17_P0LOOKUP_CTRL_REG           0x0660
+#define S17_P0PRI_CTRL_REG              0x0664
+#define S17_P0LEARN_LMT_REG             0x0668
+#define S17_P1LOOKUP_CTRL_REG           0x066c
+#define S17_P1PRI_CTRL_REG              0x0670
+#define S17_P1LEARN_LMT_REG             0x0674
+#define S17_P2LOOKUP_CTRL_REG           0x0678
+#define S17_P2PRI_CTRL_REG              0x067c
+#define S17_P2LEARN_LMT_REG             0x0680
+#define S17_P3LOOKUP_CTRL_REG           0x0684
+#define S17_P3PRI_CTRL_REG              0x0688
+#define S17_P3LEARN_LMT_REG             0x068c
+#define S17_P4LOOKUP_CTRL_REG           0x0690
+#define S17_P4PRI_CTRL_REG              0x0694
+#define S17_P4LEARN_LMT_REG             0x0698
+#define S17_P5LOOKUP_CTRL_REG           0x069c
+#define S17_P5PRI_CTRL_REG              0x06a0
+#define S17_P5LEARN_LMT_REG             0x06a4
+#define S17_P6LOOKUP_CTRL_REG           0x06a8
+#define S17_P6PRI_CTRL_REG              0x06ac
+#define S17_P6LEARN_LMT_REG             0x06b0
+#define S17_GLO_TRUNK_CTRL0_REG         0x0700
+#define S17_GLO_TRUNK_CTRL1_REG         0x0704
+#define S17_GLO_TRUNK_CTRL2_REG         0x0708
+
+/* Queue Management Registers */
+#define S17_PORT0_HOL_CTRL0		0x0970
+#define S17_PORT0_HOL_CTRL1		0x0974
+#define S17_PORT1_HOL_CTRL0		0x0978
+#define S17_PORT1_HOL_CTRL1		0x097c
+#define S17_PORT2_HOL_CTRL0		0x0980
+#define S17_PORT2_HOL_CTRL1		0x0984
+#define S17_PORT3_HOL_CTRL0		0x0988
+#define S17_PORT3_HOL_CTRL1		0x098c
+#define S17_PORT4_HOL_CTRL0		0x0990
+#define S17_PORT4_HOL_CTRL1		0x0994
+#define S17_PORT5_HOL_CTRL0		0x0998
+#define S17_PORT5_HOL_CTRL1		0x099c
+#define S17_PORT6_HOL_CTRL0		0x09a0
+#define S17_PORT6_HOL_CTRL1		0x09a4
+
+/* Port flow control registers */
+#define S17_P0_FLCTL_REG		0x09b0
+#define S17_P1_FLCTL_REG		0x09b4
+#define S17_P2_FLCTL_REG		0x09b8
+#define S17_P3_FLCTL_REG		0x09bc
+#define S17_P4_FLCTL_REG		0x09c0
+#define S17_P5_FLCTL_REG		0x09c4
+
+/* Packet Edit registers */
+#define S17_PKT_EDIT_CTRL		0x0c00
+#define S17_P0Q_REMAP_REG0		0x0c40
+#define S17_P0Q_REMAP_REG1		0x0c44
+#define S17_P1Q_REMAP_REG0		0x0c48
+#define S17_P2Q_REMAP_REG0		0x0c4c
+#define S17_P3Q_REMAP_REG0		0x0c50
+#define S17_P4Q_REMAP_REG0		0x0c54
+#define S17_P5Q_REMAP_REG0		0x0c58
+#define S17_P5Q_REMAP_REG1		0x0c5c
+#define S17_P6Q_REMAP_REG0		0x0c60
+#define S17_P6Q_REMAP_REG1		0x0c64
+#define S17_ROUTER_VID0			0x0c70
+#define S17_ROUTER_VID1			0x0c74
+#define S17_ROUTER_VID2			0x0c78
+#define S17_ROUTER_VID3			0x0c7c
+#define S17_ROUTER_EG_VLAN_MODE		0x0c80
+
+/* L3 Registers */
+#define S17_HROUTER_CTRL_REG            0x0e00
+#define S17_HROUTER_PBCTRL0_REG         0x0e04
+#define S17_HROUTER_PBCTRL1_REG         0x0e08
+#define S17_HROUTER_PBCTRL2_REG         0x0e0c
+#define S17_WCMP_HASH_TABLE0_REG        0x0e10
+#define S17_WCMP_HASH_TABLE1_REG        0x0e14
+#define S17_WCMP_HASH_TABLE2_REG        0x0e18
+#define S17_WCMP_HASH_TABLE3_REG        0x0e1c
+#define S17_WCMP_NHOP_TABLE0_REG        0x0e20
+#define S17_WCMP_NHOP_TABLE1_REG        0x0e24
+#define S17_WCMP_NHOP_TABLE2_REG        0x0e28
+#define S17_WCMP_NHOP_TABLE3_REG        0x0e2c
+#define S17_ARP_ENTRY_CTRL_REG          0x0e30
+#define S17_ARP_USECNT_REG              0x0e34
+#define S17_HNAT_CTRL_REG               0x0e38
+#define S17_NAPT_ENTRY_CTRL0_REG        0x0e3c
+#define S17_NAPT_ENTRY_CTRL1_REG        0x0e40
+#define S17_NAPT_USECNT_REG             0x0e44
+#define S17_ENTRY_EDIT_DATA0_REG        0x0e48
+#define S17_ENTRY_EDIT_DATA1_REG        0x0e4c
+#define S17_ENTRY_EDIT_DATA2_REG        0x0e50
+#define S17_ENTRY_EDIT_DATA3_REG        0x0e54
+#define S17_ENTRY_EDIT_CTRL_REG         0x0e58
+#define S17_HNAT_PRIVATE_IP_REG         0x0e5c
+
+/* MIB counters */
+#define S17_MIB_PORT0			0x1000
+#define S17_MIB_PORT1			0x1100
+#define S17_MIB_PORT2			0x1200
+#define S17_MIB_PORT3			0x1300
+#define S17_MIB_PORT4			0x1400
+#define S17_MIB_PORT5			0x1500
+#define S17_MIB_PORT6			0x1600
+
+#define S17_MIB_RXBROAD			0x0
+#define S17_MIB_RXPAUSE			0x4
+#define S17_MIB_RXMULTI			0x8
+#define S17_MIB_RXFCSERR		0xC
+#define S17_MIB_RXALIGNERR		0x10
+#define S17_MIB_RXUNDERSIZE		0x14
+#define S17_MIB_RXFRAG			0x18
+#define S17_MIB_RX64B			0x1C
+#define S17_MIB_RX128B			0x20
+#define S17_MIB_RX256B			0x24
+#define S17_MIB_RX512B			0x28
+#define S17_MIB_RX1024B			0x2C
+#define S17_MIB_RX1518B			0x30
+#define S17_MIB_RXMAXB			0x34
+#define S17_MIB_RXTOOLONG		0x38
+#define S17_MIB_RXBYTE1			0x3C
+#define S17_MIB_RXBYTE2			0x40
+#define S17_MIB_RXOVERFLOW		0x4C
+#define S17_MIB_FILTERED		0x50
+#define S17_MIB_TXBROAD			0x54
+#define S17_MIB_TXPAUSE			0x58
+#define S17_MIB_TXMULTI			0x5C
+#define S17_MIB_TXUNDERRUN		0x60
+#define S17_MIB_TX64B			0x64
+#define S17_MIB_TX128B			0x68
+#define S17_MIB_TX256B			0x6c
+#define S17_MIB_TX512B			0x70
+#define S17_MIB_TX1024B			0x74
+#define S17_MIB_TX1518B			0x78
+#define S17_MIB_TXMAXB			0x7C
+#define S17_MIB_TXOVERSIZE		0x80
+#define S17_MIB_TXBYTE1			0x84
+#define S17_MIB_TXBYTE2			0x88
+#define S17_MIB_TXCOL			0x8C
+#define S17_MIB_TXABORTCOL		0x90
+#define S17_MIB_TXMULTICOL		0x94
+#define S17_MIB_TXSINGLECOL		0x98
+#define S17_MIB_TXEXCDEFER		0x9C
+#define S17_MIB_TXDEFER			0xA0
+#define S17_MIB_TXLATECOL		0xA4
+
+/* Register fields */
+#define S17_CHIPID_V1_0			0x1201
+#define S17_CHIPID_V1_1			0x1202
+
+#define S17_MAC0_MAC_MII_RXCLK_SEL	(1 << 0)
+#define S17_MAC0_MAC_MII_TXCLK_SEL	(1 << 1)
+#define S17_MAC0_MAC_MII_EN		(1 << 2)
+#define S17_MAC0_MAC_GMII_RXCLK_SEL	(1 << 4)
+#define S17_MAC0_MAC_GMII_TXCLK_SEL	(1 << 5)
+#define S17_MAC0_MAC_GMII_EN		(1 << 6)
+#define S17_MAC0_SGMII_EN		(1 << 7)
+#define S17_MAC0_PHY_MII_RXCLK_SEL	(1 << 8)
+#define S17_MAC0_PHY_MII_TXCLK_SEL	(1 << 9)
+#define S17_MAC0_PHY_MII_EN		(1 << 10)
+#define S17_MAC0_PHY_MII_PIPE_SEL	(1 << 11)
+#define S17_MAC0_PHY_GMII_RXCLK_SEL	(1 << 12)
+#define S17_MAC0_PHY_GMII_TXCLK_SEL	(1 << 13)
+#define S17_MAC0_PHY_GMII_EN		(1 << 14)
+#define S17_MAC0_RGMII_RXCLK_SHIFT	20
+#define S17_MAC0_RGMII_TXCLK_SHIFT	22
+#define S17_MAC0_RGMII_RXCLK_DELAY	(1 << 24)
+#define S17_MAC0_RGMII_TXCLK_DELAY	(1 << 25)
+#define S17_MAC0_RGMII_EN		(1 << 26)
+
+#define S17_MAC5_MAC_MII_RXCLK_SEL	(1 << 0)
+#define S17_MAC5_MAC_MII_TXCLK_SEL	(1 << 1)
+#define S17_MAC5_MAC_MII_EN		(1 << 2)
+#define S17_MAC5_PHY_MII_RXCLK_SEL	(1 << 8)
+#define S17_MAC5_PHY_MII_TXCLK_SEL	(1 << 9)
+#define S17_MAC5_PHY_MII_EN		(1 << 10)
+#define S17_MAC5_PHY_MII_PIPE_SEL	(1 << 11)
+#define S17_MAC5_RGMII_RXCLK_SHIFT	20
+#define S17_MAC5_RGMII_TXCLK_SHIFT	22
+#define S17_MAC5_RGMII_RXCLK_DELAY	(1 << 24)
+#define S17_MAC5_RGMII_TXCLK_DELAY	(1 << 25)
+#define S17_MAC5_RGMII_EN		(1 << 26)
+
+#define S17_MAC6_MAC_MII_RXCLK_SEL	(1 << 0)
+#define S17_MAC6_MAC_MII_TXCLK_SEL	(1 << 1)
+#define S17_MAC6_MAC_MII_EN		(1 << 2)
+#define S17_MAC6_MAC_GMII_RXCLK_SEL	(1 << 4)
+#define S17_MAC6_MAC_GMII_TXCLK_SEL	(1 << 5)
+#define S17_MAC6_MAC_GMII_EN		(1 << 6)
+#define S17_MAC6_SGMII_EN		(1 << 7)
+#define S17_MAC6_PHY_MII_RXCLK_SEL	(1 << 8)
+#define S17_MAC6_PHY_MII_TXCLK_SEL	(1 << 9)
+#define S17_MAC6_PHY_MII_EN		(1 << 10)
+#define S17_MAC6_PHY_MII_PIPE_SEL	(1 << 11)
+#define S17_MAC6_PHY_GMII_RXCLK_SEL	(1 << 12)
+#define S17_MAC6_PHY_GMII_TXCLK_SEL	(1 << 13)
+#define S17_MAC6_PHY_GMII_EN		(1 << 14)
+#define S17_PHY4_GMII_EN		(1 << 16)
+#define S17_PHY4_RGMII_EN		(1 << 17)
+#define S17_PHY4_MII_EN			(1 << 18)
+#define S17_MAC6_RGMII_RXCLK_SHIFT	20
+#define S17_MAC6_RGMII_TXCLK_SHIFT	22
+#define S17_MAC6_RGMII_RXCLK_DELAY	(1 << 24)
+#define S17_MAC6_RGMII_TXCLK_DELAY	(1 << 25)
+#define S17_MAC6_RGMII_EN		(1 << 26)
+
+#define S17_SPEED_10M			(0 << 0)
+#define S17_SPEED_100M			(1 << 0)
+#define S17_SPEED_1000M			(2 << 0)
+#define S17_TXMAC_EN			(1 << 2)
+#define S17_RXMAC_EN			(1 << 3)
+#define S17_TX_FLOW_EN			(1 << 4)
+#define S17_RX_FLOW_EN			(1 << 5)
+#define S17_DUPLEX_FULL			(1 << 6)
+#define S17_DUPLEX_HALF			(0 << 6)
+#define S17_TX_HALF_FLOW_EN		(1 << 7)
+#define S17_LINK_EN			(1 << 9)
+#define S17_FLOW_LINK_EN		(1 << 12)
+#define S17_PORT_STATUS_DEFAULT		(S17_SPEED_1000M | S17_TXMAC_EN | \
+                                        S17_RXMAC_EN | S17_TX_FLOW_EN | \
+                                        S17_RX_FLOW_EN | S17_DUPLEX_FULL | \
+                                        S17_TX_HALF_FLOW_EN)
+
+#define S17_PORT_STATUS_AZ_DEFAULT	(S17_SPEED_1000M | S17_TXMAC_EN | \
+                                        S17_RXMAC_EN | S17_TX_FLOW_EN | \
+                                        S17_RX_FLOW_EN | S17_DUPLEX_FULL)
+
+
+#define S17_HDRLENGTH_SEL		(1 << 16)
+#define S17_HDR_VALUE			0xAAAA
+
+#define S17_TXHDR_MODE_NO		0
+#define S17_TXHDR_MODE_MGM		1
+#define S17_TXHDR_MODE_ALL		2
+#define S17_RXHDR_MODE_NO		(0 << 2)
+#define S17_RXHDR_MODE_MGM		(1 << 2)
+#define S17_RXHDR_MODE_ALL		(2 << 2)
+
+#define S17_CPU_PORT_EN			(1 << 10)
+#define S17_PPPOE_REDIR_EN		(1 << 8)
+#define S17_MIRROR_PORT_SHIFT		4
+#define S17_IGMP_COPY_EN		(1 << 3)
+#define S17_RIP_COPY_EN			(1 << 2)
+#define S17_EAPOL_REDIR_EN		(1 << 0)
+
+#define S17_IGMP_JOIN_LEAVE_DP_SHIFT	24
+#define S17_BROAD_DP_SHIFT		16
+#define S17_MULTI_FLOOD_DP_SHIFT	8
+#define S17_UNI_FLOOD_DP_SHIFT		0
+#define S17_IGMP_JOIN_LEAVE_DPALL	(0x3f << S17_IGMP_JOIN_LEAVE_DP_SHIFT)
+#define S17_BROAD_DPALL			(0x3f << S17_BROAD_DP_SHIFT)
+#define S17_MULTI_FLOOD_DPALL		(0x3f << S17_MULTI_FLOOD_DP_SHIFT)
+#define S17_UNI_FLOOD_DPALL		(0x3f << S17_UNI_FLOOD_DP_SHIFT)
+
+#define S17_PWS_CHIP_AR8327             (1 << 30)
+
+/* S17_PHY_CONTROL fields */
+#define S17_CTRL_SOFTWARE_RESET                    0x8000
+#define S17_CTRL_SPEED_LSB                         0x2000
+#define S17_CTRL_AUTONEGOTIATION_ENABLE            0x1000
+#define S17_CTRL_RESTART_AUTONEGOTIATION           0x0200
+#define S17_CTRL_SPEED_FULL_DUPLEX                 0x0100
+#define S17_CTRL_SPEED_MSB                         0x0040
+
+/* For EEE_CTRL_REG */
+#define S17_LPI_DISABLE_P1		     (1 << 4)
+#define S17_LPI_DISABLE_P2		     (1 << 6)
+#define S17_LPI_DISABLE_P3		     (1 << 8)
+#define S17_LPI_DISABLE_P4		     (1 << 10)
+#define S17_LPI_DISABLE_P5		     (1 << 12)
+#define S17_LPI_DISABLE_ALL		     0x1550
+
+/* For MMD register control */
+#define S17_MMD_FUNC_ADDR			(0 << 14)
+#define S17_MMD_FUNC_DATA			(1 << 14)
+#define S17_MMD_FUNC_DATA_2			(2 << 14)
+#define S17_MMD_FUNC_DATA_3			(3 << 14)
+
+/* For phyInfo_t azFeature */
+#define S17_8023AZ_PHY_ENABLED			(1 << 0)
+#define S17_8023AZ_PHY_LINKED                   (1 << 1)
+
+/* Queue Management registe fields */
+#define S17_HOL_CTRL0_LAN		0x2a008888 /* egress priority 8, eg_portq = 0x2a */
+#define S17_HOL_CTRL0_WAN		0x2a666666 /* egress priority 6, eg_portq = 0x2a */
+#define S17_HOL_CTRL1_DEFAULT		0xc6	   /* enable HOL control */
+
+/* Packet Edit register fields */
+#define S17_ROUTER_EG_UNMOD		0x0	/* unmodified */
+#define S17_ROUTER_EG_WOVLAN		0x1	/* without VLAN */
+#define S17_ROUTER_EG_WVLAN		0x2	/* with VLAN */
+#define S17_ROUTER_EG_UNTOUCH		0x3	/* untouched */
+#define S17_ROUTER_EG_MODE_DEFAULT	0x01111111 /* all ports without VLAN */
+
+#define S17_RESET_DONE(phy_control)                   \
+    (((phy_control) & (S17_CTRL_SOFTWARE_RESET)) == 0)
+    
+/* Phy status fields */
+#define S17_STATUS_AUTO_NEG_DONE                   0x0020
+
+#define S17_AUTONEG_DONE(ip_phy_status)                   \
+    (((ip_phy_status) &                                  \
+        (S17_STATUS_AUTO_NEG_DONE)) ==                    \
+        (S17_STATUS_AUTO_NEG_DONE))
+
+/* Link Partner ability */
+#define S17_LINK_100BASETX_FULL_DUPLEX       0x0100
+#define S17_LINK_100BASETX                   0x0080
+#define S17_LINK_10BASETX_FULL_DUPLEX        0x0040
+#define S17_LINK_10BASETX                    0x0020
+
+/* Advertisement register. */
+#define S17_ADVERTISE_NEXT_PAGE              0x8000
+#define S17_ADVERTISE_ASYM_PAUSE             0x0800
+#define S17_ADVERTISE_PAUSE                  0x0400
+#define S17_ADVERTISE_100FULL                0x0100
+#define S17_ADVERTISE_100HALF                0x0080  
+#define S17_ADVERTISE_10FULL                 0x0040  
+#define S17_ADVERTISE_10HALF                 0x0020  
+
+#define S17_ADVERTISE_ALL (S17_ADVERTISE_ASYM_PAUSE | S17_ADVERTISE_PAUSE | \
+                            S17_ADVERTISE_10HALF | S17_ADVERTISE_10FULL | \
+                            S17_ADVERTISE_100HALF | S17_ADVERTISE_100FULL)
+                       
+/* 1000BASET_CONTROL */
+#define S17_ADVERTISE_1000FULL               0x0200
+
+/* Phy Specific status fields */
+#define S17_STATUS_LINK_MASK                0xC000
+#define S17_STATUS_LINK_SHIFT               14
+#define S17_STATUS_FULL_DEPLEX              0x2000
+#define S17_STATUS_LINK_PASS                 0x0400 
+#define S17_STATUS_RESOLVED                  0x0800
+#define S17_STATUS_LINK_10M			 0
+#define S17_STATUS_LINK_100M			 1
+#define S17_STATUS_LINK_1000M			 2
+
+#define S17_GLOBAL_INT_PHYMASK	 	     (1 << 15)
+
+#define S17_PHY_LINK_UP 		     0x400
+#define S17_PHY_LINK_DOWN 		     0x800
+#define S17_PHY_LINK_DUPLEX_CHANGE 	     0x2000
+#define S17_PHY_LINK_SPEED_CHANGE	     0x4000
+#define S17_PHY_LINK_INTRS		     (S17_PHY_LINK_UP | S17_PHY_LINK_DOWN \
+                                              | S17_PHY_LINK_DUPLEX_CHANGE | S17_PHY_LINK_SPEED_CHANGE)
+
+/* For Port flow control registers */
+#define S17_PORT_FLCTL_XON_DEFAULT		(0x3a << 16)
+#define S17_PORT_FLCTL_XOFF_DEFAULT		(0x4a)
+
+/* Module enable Register */
+#define S17_MODULE_L3_EN		(1 << 2)
+#define S17_MODULE_ACL_EN		(1 << 1)
+#define S17_MODULE_MIB_EN		(1 << 0)
+
+/* MIB Function Register 1 */
+#define S17_MIB_FUNC_ALL		(3 << 24)
+#define S17_MIB_CPU_KEEP		(1 << 20)
+#define S17_MIB_BUSY			(1 << 17)
+#define S17_MIB_AT_HALF_EN		(1 << 16)
+#define S17_MIB_TIMER_DEFAULT		0x100
+
+#define S17_MAC_MAX			7
+
+/* enable 802.3az */
+#define S17_8023AZ_FEATURE
+
+#ifndef BOOL
+#define BOOL    int
+#endif
+
+/*add feature define here*/
+/* To enable the SSDK full feature set */
+//#define S17_FULL_FEATURE
+/* AR8327/8328N HNAT feature */
+//#define CONFIG_ATHRS17_HNAT
+/* dump MIB counters */
+#define S17_DUMP_MIB
+
+int athrs17_init(char *devname);
+int athrs17_phy_setup(char *devname, int phyUnit);
+unsigned int athrs17_reg_read(char *devname, unsigned int reg_addr);
+void athrs17_reg_write(char *devname, unsigned int reg_addr, unsigned int reg_val);
+unsigned int athrs17_phy_debug_read(char *devname, unsigned int phy_addr, unsigned int reg_addr);
+void athrs17_phy_debug_write(char *devname, unsigned int phy_addr, unsigned int reg_addr, unsigned int reg_val);
+
+#endif
+
+
+

drivers/c2000_eth/c2000_eth.h

diff --git a/drivers/c2000_eth/c2000_eth.h b/drivers/c2000_eth/c2000_eth.h
new file mode 100644
index 0000000..b191dce
--- /dev/null
+++ b/drivers/c2000_eth/c2000_eth.h
@@ -0,0 +1,175 @@
+/*
+ *  (C) Copyright 2011
+ *  Author : Mindspeed Technologes
+ *  
+ *  See file CREDITS for list of people who contributed to this
+ *  project.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License as
+ *  published by the Free Software Foundation; either version 2 of
+ *  the License, or (at your option) any later version.
+ *  
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *  
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ *  MA 02111-1307 USA
+ * */
+
+#ifndef _C2000_ETH_H_
+#define _C2000_ETH_H_
+
+
+#include "pfe_driver.h"
+
+#ifndef SZ_1K
+#define SZ_1K 1024
+#endif
+
+#ifndef SZ_1M
+#define SZ_1M (1024 * 1024)
+#endif
+
+#define BMU2_DDR_BASEADDR	0
+#define BMU2_BUF_COUNT		(3 * SZ_1K)
+#define BMU2_DDR_SIZE		(DDR_BUF_SIZE * BMU2_BUF_COUNT)
+
+#define TMU_LLM_BASEADDR	(BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
+#define TMU_LLM_QUEUE_LEN	(16 * 256)			/**< Must be power of two and at least 16 * 8 = 128 bytes */
+#define TMU_LLM_SIZE		(4 * 16 * TMU_LLM_QUEUE_LEN)	/**< (4 TMU's x 16 queues x queue_len) */
+
+#define HIF_RX_PKT_DDR_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
+#define HIF_RX_PKT_DDR_SIZE     (HIF_RX_DESC_NT * DDR_BUF_SIZE)
+#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
+#define HIF_TX_PKT_DDR_SIZE     (HIF_TX_DESC_NT * DDR_BUF_SIZE)
+
+#define HIF_DESC_BASEADDR       (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
+#define HIF_RX_DESC_SIZE        (16*HIF_RX_DESC_NT)
+#define HIF_TX_DESC_SIZE        (16*HIF_TX_DESC_NT)
+#define HIF_DESC_SIZE           (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
+
+//#define FPPDIAG_CTL_BASE_ADDR	(HIF_DESC_BASEADDR + HIF_DESC_SIZE)
+#define FPPDIAG_CTL_BASE_ADDR	0x700000
+#define FPPDIAG_CTL_SIZE		256	/**< Must be at least 11*8 bytes */
+#define FPPDIAG_PAGE_BASE_ADDR	(FPPDIAG_CTL_BASE_ADDR + FPPDIAG_CTL_SIZE)
+#define FPPDIAG_PAGE_TOTAL_SIZE	(11 * 256) /**< 256 bytes per PE, 11 PEs */
+
+//#define UTIL_CODE_BASEADDR	(FPPDIAG_PAGE_BASE_ADDR + FPPDIAG_PAGE_TOTAL_SIZE)
+#define UTIL_CODE_BASEADDR	0x780000
+#define UTIL_CODE_SIZE		(128 * SZ_1K)
+
+#define UTIL_DDR_DATA_BASEADDR	(UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
+#define UTIL_DDR_DATA_SIZE	(64 * SZ_1K)
+
+#define CLASS_DDR_DATA_BASEADDR	(UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
+#define CLASS_DDR_DATA_SIZE	(32 * SZ_1K)
+
+#define TMU_DDR_DATA_BASEADDR	(CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
+#define TMU_DDR_DATA_SIZE	(32 * SZ_1K)
+
+//#define ROUTE_TABLE_BASEADDR	(TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
+#define ROUTE_TABLE_BASEADDR	0x800000
+#define ROUTE_TABLE_HASH_BITS_MAX	15	/**< 32K entries */
+#define ROUTE_TABLE_HASH_BITS	8	/**< 256 entries */
+#define ROUTE_TABLE_SIZE	((1 << ROUTE_TABLE_HASH_BITS_MAX) * CLASS_ROUTE_SIZE)
+
+#define	PFE_TOTAL_DATA_SIZE	(ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
+
+#if PFE_TOTAL_DATA_SIZE > (12 * SZ_1M)
+#error DDR mapping above 12MiB
+#endif
+
+/* LMEM Mapping */
+#define BMU1_LMEM_BASEADDR	0
+#define BMU1_BUF_COUNT		256
+#define BMU1_LMEM_SIZE		(LMEM_BUF_SIZE * BMU1_BUF_COUNT)
+
+
+#define CONFIG_DDR_PHYS_BASEADDR 0x03800000
+#define CONFIG_DDR_BASEADDR      CONFIG_DDR_PHYS_BASEADDR
+
+#if 0
+
+#define RX_PKT_DDR_BASEADDR  0x300000   //4 pkts of each 2k size
+#define TX_PKT_DDR_BASEADDR  0x302000  //4 pkts of each 2K size
+
+#define RX_BD_BASEADDR       0x214000 
+#define TX_BD_BASEADDR       0x214200 
+
+#define BMU1_LMEM_BASEADDR   0
+#define BMU1_BUF_COUNT       32
+
+#define BMU2_BUF_COUNT       32
+#define BMU2_DDR_BASEADDR    0x200000
+
+
+#define ROUTE_TABLE_BASEADDR	0x215000 
+#define ROUTE_TABLE_HASH_BITS	2	/**< 2 entries */
+
+#define TMU_LLM_BASEADDR   0x216000 
+#define TMU_LLM_QUEUE_LEN  (16 * 256)
+
+#endif
+
+#define GEMAC_NO_PHY 		1
+#define GEMAC_HAVE_SWITCH_PHY     2
+#define GEMAC_HAVE_SWITCH       	4
+
+
+typedef struct gemac_s {
+
+	void *gemac_base; 
+	void *egpi_base;
+
+	/* GEMAC config */
+	int gemac_mode;
+	int gemac_speed;
+	int gemac_duplex;
+        int flags;
+	/* phy iface */
+	int phy_reg_index;
+	int phy_address;
+
+} gemac_t;
+
+struct pfe {
+	unsigned long ddr_phys_baseaddr;
+	void *ddr_baseaddr;
+	void *cbus_baseaddr;
+};
+
+
+typedef struct c2000_eth_dev {
+
+	int gemac_port;
+	void *phyregisters;
+
+	struct gemac_s *gem;
+	struct pfe      pfe;
+
+        struct eth_device *dev;
+
+} c2000_eth_dev_t;
+
+
+struct firmware {
+	u8 *data;
+};
+
+
+int pfe_probe(struct pfe *pfe);
+int pfe_remove(struct pfe *pfe);
+
+
+//#define dprint(fmt, arg...)	pr_info(fmt, ##arg)
+#define dprint(fmt, arg...)
+//#define dprint	printf
+
+
+#endif //_C2000_ETH_H_
+

drivers/c2000_eth/c2000_ethernet.c

diff --git a/drivers/c2000_eth/c2000_ethernet.c b/drivers/c2000_eth/c2000_ethernet.c
new file mode 100644
index 0000000..3f0f970
--- /dev/null
+++ b/drivers/c2000_eth/c2000_ethernet.c
@@ -0,0 +1,539 @@
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+#include <asm/byteorder.h>
+//#include <malloc.h>
+#include <net.h>
+#include <command.h>
+#include <miiphy.h>
+#include <asm/arch/clkcore_c2000.h>
+#include <asm/arch/gpio_c2000.h>
+#include "c2000_eth.h"
+#ifdef CONFIG_AR8328_SWITCH
+#include "ar8328.h"
+#endif
+
+struct gemac_s gem_info[] = {
+        /* PORT_0 configuration */
+        {
+                /* GEMAC config */
+                .gemac_mode = RGMII,
+                .gemac_speed = SPEED_1000M,
+                .gemac_duplex = DUPLEX_FULL,
+                .flags = EMAC0_FLAGS,
+
+                /* phy iface */
+                .phy_reg_index = EMAC_PORT_0,
+                .phy_address = EMAC0_PHY_ADDR,
+        },
+        /* PORT_1 configuration */
+        {
+                /* GEMAC config */
+                .gemac_mode = RGMII,
+                .gemac_speed = SPEED_1000M,
+                .gemac_duplex = DUPLEX_FULL,
+                .flags = EMAC1_FLAGS,
+
+                /* phy iface */
+                .phy_reg_index = EMAC_PORT_0,
+                .phy_address = EMAC1_PHY_ADDR,
+        },
+
+        /* PORT_2 configuration */
+        {
+                /* GEMAC config */
+                .gemac_mode = RGMII,
+                .gemac_speed = SPEED_1000M,
+                .gemac_duplex = DUPLEX_FULL,
+                .flags = EMAC2_FLAGS,
+
+                /* phy iface */
+                .phy_reg_index = EMAC_PORT_0,
+                .phy_address = 0,
+        },
+};
+
+#define MAX_GEMACS      3
+
+static struct c2000_eth_dev *gemac_list[MAX_GEMACS];
+
+/********************************************************************
+ * Helper functions for phy read/write
+ *******************************************************************/
+
+/* Max MII register/address (we support) */
+#define MII_REGISTER_MAX  31
+#define MII_ADDRESS_MAX   31
+
+#define MDIO_TIMEOUT    5000
+
+/********************************************************************
+ * gem_phy_man_rd :
+ *      Performs phy management read operation.
+ *******************************************************************/
+static int gem_phy_man_rd(struct c2000_eth_dev *priv, u32 phy_addr, u32 phy_reg)
+{
+        u32 write_data;
+
+        write_data = 0x60020000 | ( (phy_addr & (u32) 0x1f) << 23) | ( (phy_reg & (u32) 0x1f) << 18); // read_op
+        writel(write_data, priv->phyregisters + EMAC_PHY_MANAGEMENT);
+
+        return 0;
+}
+
+static int gem_phy_man_wr(struct c2000_eth_dev *priv, u32 phy_addr, u32 phy_reg, u32 val)
+{
+        u32 write_data;
+
+        write_data =  0x50020000 | ( (phy_addr & (u32) 0x1f) << 23) | ( (phy_reg & (u32) 0x1f) << 18) | (val & (u32) 0xffff); // write_op
+        writel(write_data, priv->phyregisters + EMAC_PHY_MANAGEMENT);
+
+        return 0;
+}
+
+/** gem_phy_man_data
+ *      Read the data section of phy management register.
+ *    After a successful read opeeration the data will be stored in
+ *    in this register in lower 16bits.
+ */
+static u32 gem_phy_man_data(struct c2000_eth_dev *priv)
+{
+        u32 value;
+
+        value = readl(priv->phyregisters + EMAC_PHY_MANAGEMENT) & 0xFFFF;
+        return value;
+}
+
+#define EMAC_PHY_IDLE   (1 << 2)
+
+static int gem_phy_man_idle(struct c2000_eth_dev *priv)
+{
+        u32 value;
+
+        value = readl(priv->phyregisters + EMAC_NETWORK_STATUS);
+        return ((value & EMAC_PHY_IDLE) == EMAC_PHY_IDLE);
+}
+
+static int gem_phy_timeout(struct c2000_eth_dev *priv, int timeout)
+{
+        while(!gem_phy_man_idle(priv)) {
+
+                if (timeout-- <= 0) {
+                        printf("Phy MDIO read/write timeout\n");
+                        return -1;
+                }
+
+                //udelay(1);
+        }
+        return 0;
+}
+
+static struct c2000_eth_dev* get_gemac(char *devname)
+{
+        int i;
+
+        for (i = 0; i < MAX_GEMACS; i++) {
+                if (!strcmp(gemac_list[i]->dev->name, devname))
+                        return gemac_list[i];
+        }
+
+        return NULL;
+}
+
+
+/** PHY read function
+ * Reads a 16bit value from a MII register
+ *
+ * @param[in] mdev              Pointer to MII device structure
+ * @param[in] phy_addr
+ * @param[in] phy_reg
+ *
+ * @return  16bit value on success, a negivie value (-1) on error
+ */
+static int c2000_phy_read(char *devname, unsigned char phy_addr, unsigned char phy_reg, unsigned short *value)
+{
+        struct c2000_eth_dev *priv = get_gemac(devname);
+
+        if (!priv) {
+                printf("Unknown device %s\n", devname);
+                return -1;
+        }
+
+        if ((phy_addr > MII_ADDRESS_MAX) || (phy_reg > MII_REGISTER_MAX))
+                return -1;
+
+        gem_phy_man_rd(priv, phy_addr, phy_reg);
+        if (gem_phy_timeout(priv, MDIO_TIMEOUT))
+                return -1;
+
+        *value = gem_phy_man_data(priv);
+
+        dprint("%s: Addr: %d, Reg: %d, Val: 0x%x\n",
+                                              __func__, phy_addr, phy_reg, *value);
+
+        return 0;
+}
+
+/** PHY write function
+ * Writes a 16bit value to a MII register
+ *
+ * @param[in] mdev              Pointer to MII device structure
+ * @param[in] phy_addr
+ * @param[in] phy_reg
+ * @param[in] value     Value to be written to Phy
+ *
+ * @return              On success returns 0, a negative value (-1) on error
+ */
+static int c2000_phy_write(char *devname, unsigned char phy_addr, unsigned char phy_reg, unsigned short value)
+{
+        struct c2000_eth_dev *priv = get_gemac(devname);
+
+        if (!priv) {
+                printf("Unknown device %s\n", devname);
+                return -1;
+        }
+        if ((phy_addr > MII_ADDRESS_MAX) || (phy_reg > MII_REGISTER_MAX))
+                return -1;
+
+        gem_phy_man_wr(priv, phy_addr, phy_reg, value);
+        if (gem_phy_timeout(priv, MDIO_TIMEOUT))
+                return -1;
+
+        dprint("%s: Addr: %d, Reg: %d, Val: 0x%x\n",
+                                              __func__, phy_addr, phy_reg, value);
+
+        return 0;
+}
+
+/** MAC Address converter
+ * Convert standard byte style ethernet address to format compatible with MAC.
+ *
+ * @param[in] enet_byte_addr    Pointer to the mac address in byte format
+ * @param[out] Pointer to MAC_ADDR structure
+ *
+ * @return      0 on success, -1 on failure
+ */
+int gemac_enet_addr_byte_mac(u8 *enet_byte_addr, MAC_ADDR *enet_addr)
+{
+    if ((enet_byte_addr == NULL) || (enet_addr == NULL))
+    {
+        return -1;
+    }
+    else
+    {
+        enet_addr->bottom = enet_byte_addr[0] |
+                            (enet_byte_addr[1] << 8) |
+                            (enet_byte_addr[2] << 16) |
+                            (enet_byte_addr[3] << 24);
+        enet_addr->top = enet_byte_addr[4] |
+                         (enet_byte_addr[5] << 8);
+        return 0;
+    }
+}
+
+/** Configures ethernet address to GEMAC ADDR1 location.
+ *
+ * @param[in] edev      Pointer to the eth device structure
+ * @param[in] addr      Pointer to ethernet address in byte order
+ *
+ * @return  0 on success (always success)
+ */
+static int c2000_set_ethaddr(struct eth_device *dev, u8 *enet_byte_addr)
+{
+        struct c2000_eth_dev *priv = (struct c2000_eth_dev *)dev->priv;
+        MAC_ADDR enet_address = {0x0, 0x0};
+
+
+        gemac_enet_addr_byte_mac(enet_byte_addr, &enet_address);
+        gemac_set_laddr1(priv->gem->gemac_base, &enet_address);
+
+        return 0;
+}
+
+/** Get/Read configured ethernet mac address from GEMAC.
+ *
+ * @param[in] edev      Pointer to eth device structure
+ * @param[out] addr     Pointer to ethernet address to be copied
+ *
+ * @return      0 on success, always success.
+ */
+static int c2000_get_ethaddr(struct eth_device *edev, unsigned char *addr)
+{
+        struct c2000_eth_dev *priv = (struct c2000_eth_dev *)edev->priv;
+        MAC_ADDR enet_address = {0x0, 0x0};
+        u16 *p = (u16 *)addr;
+
+        enet_address = gem_get_laddr1(priv->gem->gemac_base);
+        p[0] = enet_address.bottom & 0xffff;
+        p[1] = (enet_address.bottom >> 16) & 0xffff;
+        p[2] = enet_address.top & 0xffff;
+
+        return 0;
+}
+
+
+/** Stops or Disables GEMAC pointing to this eth iface.
+ *
+ * @param[in]   edev    Pointer to eth device structure.
+ *
+ * @return      none
+ */
+static void c2000_eth_halt(struct eth_device *edev)
+{
+        struct c2000_eth_dev *priv = (struct c2000_eth_dev *)edev->priv;
+
+//        printf("%s:\n",__func__);
+
+        gemac_disable(priv->gem->gemac_base);
+
+        gpi_disable(priv->gem->egpi_base);
+
+        return;
+}
+
+#ifdef CONFIG_BOARD_C2KASIC
+int c2000_eth_board_init(char *devname, int eth_port)
+{
+        //eth0 port is chosen as criteria for bringingup out of reset because
+        //all MDIO access can happen through EMAC0 and without bringing eth0 first
+        //no PHY configuration can happen and no point in removing reset without eth0
+        if(eth_port != 0)
+                return 0;
+
+//        printf("%s: Bringing PHY out of reset\n",__func__);
+        //Bring all PHYs out of reset. The correct way is to assert, deassert and re-assert the GPIO reset signal
+        //with delay in between
+        writel(readl(COMCERTO_GPIO_OE_REG) | GPIO_3, COMCERTO_GPIO_OE_REG);
+
+        writel(readl(COMCERTO_GPIO_OUTPUT_REG) | GPIO_3, COMCERTO_GPIO_OUTPUT_REG);
+        udelay(100000);
+        writel(readl(COMCERTO_GPIO_OUTPUT_REG) & ~GPIO_3, COMCERTO_GPIO_OUTPUT_REG);
+        udelay(100000);
+        writel(readl(COMCERTO_GPIO_OUTPUT_REG) | GPIO_3, COMCERTO_GPIO_OUTPUT_REG);
+        udelay(100000);
+
+}
+#else
+int c2000_eth_board_init(char *devname, int eth_port)
+{
+        //eth0 port is chosen as criteria for bringingup out of reset because
+        //all MDIO access can happen through EMAC0 and without bringing eth0 first
+        //no Switch/PHY configuration can happen and no point in removing reset without eth0
+        if(eth_port == 0)
+        {
+
+                //Bring AR8327 switch out of reset. Toggle reset
+                writel(readl(COMCERTO_GPIO_OE_REG) | GPIO_27, COMCERTO_GPIO_OE_REG);
+                writel(readl(COMCERTO_GPIO_OUTPUT_REG) | GPIO_27, COMCERTO_GPIO_OUTPUT_REG);
+                udelay(10000);
+                writel(readl(COMCERTO_GPIO_OUTPUT_REG) & ~GPIO_27, COMCERTO_GPIO_OUTPUT_REG);
+                udelay(10000);
+                writel(readl(COMCERTO_GPIO_OUTPUT_REG) | GPIO_27, COMCERTO_GPIO_OUTPUT_REG);
+                udelay(10000);
+
+
+                //AR8327 Switch init
+                athrs17_init(devname);
+
+                //AR8327 WAN PHY4 init
+                athrs17_phy_setup(devname,EMAC0_PHY_ADDR);
+        }
+        else
+        {
+                //AR8327 LAN PHYs init
+                athrs17_phy_setup(devname,EMAC1_PHY_ADDR);
+        }
+
+}
+#endif
+
+static int c2000_eth_init(struct eth_device *dev, bd_t * bd)
+{
+        struct c2000_eth_dev *priv = (struct c2000_eth_dev *)dev->priv;
+        struct gemac_s *gem = priv->gem;
+	u32 phyaddr;
+
+//	printf("## %s\n",__func__);
+
+        /* GEMAC init */
+        pfe_gemac_init(gem->gemac_base, gem->gemac_mode, gem->gemac_speed, gem->gemac_duplex);
+
+        /* set ethernet mac address */
+        c2000_set_ethaddr(dev, dev->enetaddr);
+
+	phyaddr = gem_info[priv->gemac_port].phy_address;
+
+        if (!(gem->flags & GEMAC_NO_PHY) && (gem->gemac_mode == RGMII) )
+        {
+                miiphy_enable_rgmii_rx_delay(dev->name, phyaddr);
+                miiphy_enable_rgmii_tx_delay(dev->name, phyaddr);
+        }
+
+
+        /* Re-negotiate speed and duplex */
+        if (!(gem->flags & GEMAC_NO_PHY))
+        {
+                int speed = gem->gemac_speed;
+                int duplex = gem->gemac_duplex;
+
+		miiphy_speed_duplex(dev->name, phyaddr, &speed, &duplex);
+
+                switch (speed)
+                {
+                        case _10BASET:
+                                speed = SPEED_10M;
+                                break;
+
+                        case _100BASET:
+                                speed = SPEED_100M;
+                                break;
+
+                        case _1000BASET:
+                                speed = SPEED_1000M;
+                                break;
+                }
+
+                duplex = (duplex == HALF) ? DUPLEX_HALF:DUPLEX_FULL;
+                gemac_set_speed(gem->gemac_base, speed);
+                gemac_set_duplex(gem->gemac_base, duplex);
+        }
+
+        /* Enable GPI */
+        gpi_enable(priv->gem->egpi_base);
+
+        /* Enable GEMAC for tx and rx */
+        gemac_enable(priv->gem->gemac_base);
+	
+        return 0;
+}
+
+static int c2000_eth_send(struct eth_device *dev, volatile void *data, int length)
+{
+        struct c2000_eth_dev *priv = (struct c2000_eth_dev *)dev->priv;
+
+        int rc;
+        uint64_t tx_tmo;
+	int i;
+
+        rc = pfe_send(priv->gemac_port, data, length);
+
+        if (rc < 0) {
+                printf("Tx Q full\n");
+                return 0;
+        }
+
+        while (1) {
+                rc = pfe_tx_done();
+                if (rc == 0)
+                        break;
+		
+		udelay(100);
+		i++;
+		if(i == 30000)
+			printf("Tx timeout, send failed\n");
+			break;
+
+	}
+
+	return 0;
+}
+
+static int c2000_eth_recv(struct eth_device *dev)
+{
+        struct c2000_eth_dev *priv = (struct c2000_eth_dev *)dev->priv;
+        u32 pkt_buf;
+        int len;
+        int phy_port;
+
+        len = pfe_recv(&pkt_buf, &phy_port);
+
+        if (len < 0)
+                return 0; //no packet in rx
+
+        dprint("Rx pkt: pkt_buf(%08x), phy_port(%d), len(%d)\n", pkt_buf, phy_port, len);
+        if (phy_port != priv->gemac_port)  {
+                printf("Rx pkt not on expected port\n");
+                return 0;
+        }
+
+	// Pass the packet up to the protocol layers.
+	NetReceive((unsigned char *)pkt_buf, len);
+
+
+	return 0;
+}
+
+int c2000_gemac_initialize(bd_t * bis, int index, char *devname)
+{
+        struct eth_device *dev;
+        struct c2000_eth_dev *priv;
+        struct pfe *pfe;
+	int i;
+	
+        //Bring HFE and GEMTX out of reset
+        writel(0x0, HFE_RESET);
+        writel(0x0, GEMTX_RESET);
+
+        dev = (struct eth_device *)malloc(sizeof(struct eth_device));
+        if (!dev)
+                return -1;
+
+        memset(dev, 0, sizeof(struct eth_device));
+
+        priv = (struct c2000_eth_dev *)malloc(sizeof(struct c2000_eth_dev));
+        if (!priv)
+                return -1;
+
+        gemac_list[index] = priv;
+	priv->gemac_port = index;
+        priv->gem = &gem_info[priv->gemac_port];
+        priv->dev = dev;
+
+        pfe = &priv->pfe;
+
+        pfe->cbus_baseaddr = (void *)COMCERTO_AXI_HFE_CFG_BASE;
+        pfe->ddr_baseaddr = (void *)CONFIG_DDR_BASEADDR;
+        pfe->ddr_phys_baseaddr = (unsigned long)CONFIG_DDR_PHYS_BASEADDR;
+
+	sprintf(dev->name, devname);
+        dev->priv = priv;
+        dev->init = c2000_eth_init;
+        dev->halt = c2000_eth_halt;
+        dev->send = c2000_eth_send;
+        dev->recv = c2000_eth_recv;
+
+        /* Tell u-boot to get the addr from the env */
+        for (i = 0; i < 6; i++)
+                dev->enetaddr[i] = 0;
+
+
+        switch(priv->gemac_port)  {
+                case EMAC_PORT_0:
+                default:
+                        priv->gem->gemac_base = EMAC1_BASE_ADDR;
+                        priv->gem->egpi_base = EGPI1_BASE_ADDR;
+                break;
+                case EMAC_PORT_1:
+                        priv->gem->gemac_base = EMAC2_BASE_ADDR;
+                        priv->gem->egpi_base = EGPI2_BASE_ADDR;
+                break;
+                case EMAC_PORT_2:
+                        priv->gem->gemac_base = EMAC3_BASE_ADDR;
+                        priv->gem->egpi_base = EGPI3_BASE_ADDR;
+                break;
+        }
+
+        pfe_probe(pfe);
+        priv->phyregisters = (void *)gem_info[gem_info[priv->gemac_port].phy_reg_index].gemac_base;
+
+        if(priv->gemac_port == 0)
+        {
+                gemac_set_mdc_div(priv->gem->gemac_base, MDC_DIV_96);
+                gemac_enable_mdio(priv->gem->gemac_base);
+                miiphy_register(dev->name, c2000_phy_read, c2000_phy_write);
+        }
+
+	c2000_eth_board_init(dev->name, priv->gemac_port);
+	
+        eth_register(dev);
+}

drivers/c2000_eth/class_sbl_c2000_elf.fw

diff --git a/drivers/c2000_eth/class_sbl_c2000_elf.fw b/drivers/c2000_eth/class_sbl_c2000_elf.fw
new file mode 100644
index 0000000..0a871dd
--- /dev/null
+++ b/drivers/c2000_eth/class_sbl_c2000_elf.fw
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\ No newline at end of file

drivers/c2000_eth/hal.h

diff --git a/drivers/c2000_eth/hal.h b/drivers/c2000_eth/hal.h
new file mode 100644
index 0000000..a8541f2
--- /dev/null
+++ b/drivers/c2000_eth/hal.h
@@ -0,0 +1,65 @@
+/*
+ *  (C) Copyright 2011
+ *  Author : Mindspeed Technologes
+ *  
+ *  See file CREDITS for list of people who contributed to this
+ *  project.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License as
+ *  published by the Free Software Foundation; either version 2 of
+ *  the License, or (at your option) any later version.
+ *  
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *  
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ *  MA 02111-1307 USA
+ * */
+
+#ifndef _HAL_H_
+#define _HAL_H_
+
+#if defined(CONFIG_PLATFORM_PCI)  
+/* For ChipIT */
+
+#include <linux/types.h>
+#include <linux/elf.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+#include <linux/slab.h>
+#include <linux/firmware.h>
+
+#include "pfe_mod.h"
+
+#define free(x)  kfree(x)
+#define xzalloc(x)  kmalloc(x, GFP_DMA)
+#define printf  printk
+
+//#define dprint(fmt, arg...)	printk(fmt, ##arg)
+#define dprint(fmt, arg...)	
+
+#else
+
+#include <linux/types.h>
+#include <elf.h>
+#include <common.h>
+//#include <errno.h>
+#include <asm/byteorder.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include <asm/io.h>
+
+
+#include "c2000_eth.h"
+
+#endif
+
+
+#endif /* _HAL_H_ */
+

drivers/c2000_eth/pfe.c

diff --git a/drivers/c2000_eth/pfe.c b/drivers/c2000_eth/pfe.c
new file mode 100644
index 0000000..e8937f7
--- /dev/null
+++ b/drivers/c2000_eth/pfe.c
@@ -0,0 +1,1474 @@
+#include "hal.h"
+#include "pfe/pfe.h"
+
+void *cbus_base_addr;
+void *ddr_base_addr;
+unsigned long ddr_phys_base_addr;
+
+static struct pe_info pe[MAX_PE];
+
+/** Initializes the PFE library.
+* Must be called before using any of the library functions.
+*
+* @param[in] cbus_base		CBUS virtual base address (as mapped in the host CPU address space)
+* @param[in] ddr_base		DDR virtual base address (as mapped in the host CPU address space)
+* @param[in] ddr_phys_base	DDR physical base address (as mapped in platform)
+*/
+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base)
+{
+	cbus_base_addr = cbus_base;
+	ddr_base_addr = ddr_base;
+	ddr_phys_base_addr = ddr_phys_base;
+
+	pe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0);
+	pe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0);
+	pe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE;
+	pe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
+	pe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
+	pe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
+
+	pe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1);
+	pe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1);
+	pe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE;
+	pe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
+	pe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
+	pe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
+
+	pe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2);
+	pe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2);
+	pe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE;
+	pe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
+	pe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
+	pe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
+
+	pe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3);
+	pe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3);
+	pe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE;
+	pe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
+	pe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
+	pe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
+
+#if !defined(CONFIG_PLATFORM_PCI)
+	pe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4);
+	pe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4);
+	pe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE;
+	pe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
+	pe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
+	pe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
+
+	pe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5);
+	pe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5);
+	pe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE;
+	pe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
+	pe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
+	pe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
+#endif
+	pe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0);
+	pe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0);
+	pe[TMU0_ID].pmem_size = TMU_IMEM_SIZE;
+	pe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
+	pe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
+	pe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
+
+#if !defined(CONFIG_TMU_DUMMY)
+	pe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1);
+	pe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1);
+	pe[TMU1_ID].pmem_size = TMU_IMEM_SIZE;
+	pe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
+	pe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
+	pe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
+
+	pe[TMU2_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(2);
+	pe[TMU2_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(2);
+	pe[TMU2_ID].pmem_size = TMU_IMEM_SIZE;
+	pe[TMU2_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
+	pe[TMU2_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
+	pe[TMU2_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
+
+	pe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3);
+	pe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3);
+	pe[TMU3_ID].pmem_size = TMU_IMEM_SIZE;
+	pe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
+	pe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
+	pe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
+#endif
+
+#if !defined(CONFIG_UTIL_PE_DISABLED)
+	pe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR;
+	pe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA;
+	pe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR;
+	pe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA;
+#endif
+}
+
+
+/** Writes a buffer to PE internal memory from the host
+ * through indirect access registers.
+ *
+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
+ * @param[in] src		Buffer source address
+ * @param[in] mem_access_addr	DMEM destination address (must be 32bit aligned)
+ * @param[in] len		Number of bytes to copy
+ */
+void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned int len)
+{
+	u32 offset = 0, val, addr;
+	unsigned int len32 = len >> 2;
+	int i;
+
+	addr = mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
+
+	for (i = 0; i < len32; i++, offset += 4, src += 4) {
+		val = *(u32 *)src;
+		writel(cpu_to_be32(val), pe[id].mem_access_wdata);
+		writel(addr + offset, pe[id].mem_access_addr);
+	}
+
+	if ((len = (len & 0x3))) {
+		val = 0;
+
+		addr = (mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
+
+		for (i = 0; i < len; i++, src++)
+			val |= (*(u8 *)src) << (8 * i);
+
+		writel(cpu_to_be32(val), pe[id].mem_access_wdata);
+		writel(addr, pe[id].mem_access_addr);
+	}
+}
+
+/** Writes a buffer to PE internal data memory (DMEM) from the host
+ * through indirect access registers.
+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
+ * @param[in] src		Buffer source address
+ * @param[in] dst		DMEM destination address (must be 32bit aligned)
+ * @param[in] len		Number of bytes to copy
+ */
+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
+{
+	pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | PE_MEM_ACCESS_DMEM, src, len);
+}
+
+
+/** Writes a buffer to PE internal program memory (PMEM) from the host
+ * through indirect access registers.
+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
+ * @param[in] src		Buffer source address
+ * @param[in] dst		PMEM destination address (must be 32bit aligned)
+ * @param[in] len		Number of bytes to copy
+ */
+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
+{
+	pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_IMEM, src, len);
+}
+
+
+/** Reads PE internal program memory (IMEM) from the host
+ * through indirect access registers.
+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
+ * @param[in] addr		PMEM read address (must be aligned on size)
+ * @param[in] size		Number of bytes to read (maximum 4, must not cross 32bit boundaries)
+ * @return			the data read (in PE endianess, i.e BE).
+ */
+u32 pe_pmem_read(int id, u32 addr, u8 size)
+{
+	u32 offset = addr & 0x3;
+	u32 mask = 0xffffffff >> ((4 - size) << 3);
+	u32 val;
+
+	addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+	writel(addr, pe[id].mem_access_addr);
+	val = be32_to_cpu(readl(pe[id].mem_access_rdata));
+
+	return (val >> (offset << 3)) & mask;
+}
+
+
+/** Writes PE internal data memory (DMEM) from the host
+ * through indirect access registers.
+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
+ * @param[in] addr		DMEM write address (must be aligned on size)
+ * @param[in] val		Value to write (in PE endianess, i.e BE)
+ * @param[in] size		Number of bytes to write (maximum 4, must not cross 32bit boundaries)
+ */
+void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
+{
+	u32 offset = addr & 0x3;
+
+	addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+	/* Indirect access interface is byte swapping data being written */
+	writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
+	writel(addr, pe[id].mem_access_addr);
+}
+
+
+/** Reads PE internal data memory (DMEM) from the host
+ * through indirect access registers.
+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
+ * @param[in] addr		DMEM read address (must be aligned on size)
+ * @param[in] size		Number of bytes to read (maximum 4, must not cross 32bit boundaries)
+ * @return			the data read (in PE endianess, i.e BE).
+ */
+u32 pe_dmem_read(int id, u32 addr, u8 size)
+{
+	u32 offset = addr & 0x3;
+	u32 mask = 0xffffffff >> ((4 - size) << 3);
+	u32 val;
+
+	addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+	writel(addr, pe[id].mem_access_addr);
+
+	/* Indirect access interface is byte swapping data being read */
+	val = be32_to_cpu(readl(pe[id].mem_access_rdata));
+
+	return (val >> (offset << 3)) & mask;
+}
+
+
+/** Writes UTIL program memory (DDR) from the host.
+ *
+ * @param[in] addr	Address to write (virtual, must be aligned on size)
+ * @param[in] val		Value to write (in PE endianess, i.e BE)
+ * @param[in] size		Number of bytes to write (2 or 4)
+ */
+static void util_pmem_write(u32 val, void *addr, u8 size)
+{
+	void *addr64 = (void *)((unsigned long)addr & ~0x7);
+	unsigned long off = 8 - ((unsigned long)addr & 0x7) - size;
+	
+	//IMEM should  be loaded as a 64bit swapped value in a 64bit aligned location
+	if (size == 4)
+		writel(be32_to_cpu(val), addr64 + off);
+	else
+		writew(be16_to_cpu((u16)val), addr64 + off);
+}
+
+
+/** Writes a buffer to UTIL program memory (DDR) from the host.
+ *
+ * @param[in] dst	Address to write (virtual, must be at least 16bit aligned)
+ * @param[in] src	Buffer to write (in PE endianess, i.e BE, must have same alignment as dst)
+ * @param[in] len	Number of bytes to write (must be at least 16bit aligned)
+ */
+static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
+{
+	unsigned int len32;
+	int i;
+
+	if ((unsigned long)src & 0x2) {
+		util_pmem_write(*(u16 *)src, dst, 2);
+		src += 2;
+		dst += 2;
+		len -= 2;
+	}
+
+	len32 = len >> 2;
+
+	for (i = 0; i < len32; i++, dst += 4, src += 4)
+		util_pmem_write(*(u32 *)src, dst, 4);
+
+	if (len & 0x2)
+		util_pmem_write(*(u16 *)src, dst, len & 0x2);
+}
+
+
+/** Loads an elf section into pmem
+ * Code needs to be at least 16bit aligned and only PROGBITS sections are supported
+ *
+ * @param[in] id	PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
+ * @param[in] data	pointer to the elf firmware
+ * @param[in] shdr	pointer to the elf section header
+ *
+ */
+static int pe_load_pmem_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+	u32 offset = be32_to_cpu(shdr->sh_offset);
+	u32 addr = be32_to_cpu(shdr->sh_addr);
+	u32 size = be32_to_cpu(shdr->sh_size);
+	u32 type = be32_to_cpu(shdr->sh_type);
+
+#if !defined(CONFIG_UTIL_PE_DISABLED)
+	if (id == UTIL_ID)
+	{
+		printf("%s: unsuported pmem section for UTIL\n", __func__);
+		return -1;
+	}
+#endif
+
+	if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
+	{
+		printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+			__func__, addr, (unsigned long) data + offset);
+
+		return -1;
+	}
+
+	if (addr & 0x1)
+	{
+		printf("%s: load address(%x) is not 16bit aligned\n", __func__, addr);
+		return -1;
+	}
+
+	if (size & 0x1)
+	{
+		printf("%s: load size(%x) is not 16bit aligned\n", __func__, size);
+		return -1;
+	}
+
+	switch (type)
+        {
+        case SHT_PROGBITS:
+		pe_pmem_memcpy_to32(id, addr, data + offset, size);
+		break;
+
+	default:
+		printf("%s: unsuported section type(%x)\n", __func__, type);
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+
+/** Loads an elf section into dmem
+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
+ *
+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
+ * @param[in] data		pointer to the elf firmware
+ * @param[in] shdr		pointer to the elf section header
+ *
+ */
+static int pe_load_dmem_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+	u32 offset = be32_to_cpu(shdr->sh_offset);
+	u32 addr = be32_to_cpu(shdr->sh_addr);
+	u32 size = be32_to_cpu(shdr->sh_size);
+	u32 type = be32_to_cpu(shdr->sh_type);
+	u32 size32 = size >> 2;
+	int i;
+
+	if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
+	{
+		printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+			__func__, addr, (unsigned long)data + offset);
+
+		return -1;
+	}
+
+	if (addr & 0x3)
+	{
+		printf("%s: load address(%x) is not 32bit aligned\n", __func__, addr);
+		return -1;
+	}
+
+	switch (type)
+        {
+        case SHT_PROGBITS:
+		pe_dmem_memcpy_to32(id, addr, data + offset, size);
+		break;
+
+	case SHT_NOBITS:
+		for (i = 0; i < size32; i++, addr += 4)
+			pe_dmem_write(id, 0, addr, 4);
+
+		if (size & 0x3)
+			pe_dmem_write(id, 0, addr, size & 0x3);
+
+		break;
+
+	default:
+		printf("%s: unsuported section type(%x)\n", __func__, type);
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+
+/** Loads an elf section into DDR
+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
+ *
+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
+ * @param[in] data		pointer to the elf firmware
+ * @param[in] shdr		pointer to the elf section header
+ *
+ */
+static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+	u32 offset = be32_to_cpu(shdr->sh_offset);
+	u32 addr = be32_to_cpu(shdr->sh_addr);
+	u32 size = be32_to_cpu(shdr->sh_size);
+	u32 type = be32_to_cpu(shdr->sh_type);
+	u32 flags = be32_to_cpu(shdr->sh_flags);
+	u32 size32 = size >> 2;
+	int i;
+
+	switch (type)
+	{
+	case SHT_PROGBITS:
+		if (flags & SHF_EXECINSTR)
+		{
+#if !defined(CONFIG_UTIL_PE_DISABLED)
+			if (id == UTIL_ID)
+			{
+				if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
+				{
+					printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+								__func__, addr, (unsigned long)data + offset);
+
+					return -1;
+				}
+
+				if (addr & 0x1)
+				{
+					printf("%s: load address(%x) is not 16bit aligned\n", __func__, addr);
+					return -1;
+				}
+
+				if (size & 0x1)
+				{
+					printf("%s: load length(%x) is not 16bit aligned\n", __func__, size);
+					return -1;
+				}
+
+				util_pmem_memcpy(DDR_PHYS_TO_VIRT(addr), data + offset, size);
+			}
+			else
+#endif
+			{
+				printf("%s: unsuported ddr section type(%x) for PE(%d)\n", __func__, type, id);
+				return -1;
+			}
+
+		}
+		else
+		{
+			memcpy(DDR_PHYS_TO_VIRT(addr), data + offset, size);
+		}
+
+		break;
+
+	case SHT_NOBITS:
+		memset(DDR_PHYS_TO_VIRT(addr), 0, size);
+
+		break;
+
+	default:
+		printf("%s: unsuported section type(%x)\n", __func__, type);
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+
+/** Loads an elf section into a PE
+ * For now only supports loading a section to dmem (all PE's), pmem (class and tmu PE's),
+ * DDDR (util PE code)
+ *
+ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
+ * @param[in] data		pointer to the elf firmware
+ * @param[in] shdr		pointer to the elf section header
+ *
+ */
+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+	u32 addr = be32_to_cpu(shdr->sh_addr);
+	u32 size = be32_to_cpu(shdr->sh_size);
+
+	if (IS_DMEM(addr, size))
+		return pe_load_dmem_section(id, data, shdr);
+	else if (IS_PMEM(addr, size))
+		return pe_load_pmem_section(id, data, shdr);
+	else if (IS_PFE_LMEM(addr, size))
+		return 0; /* FIXME */
+	else if (IS_PHYS_DDR(addr, size))
+		return pe_load_ddr_section(id, data, shdr);
+	else if (IS_PE_LMEM(addr, size))
+		return 0; /* FIXME */
+	else {
+		printf("%s: unsuported memory range(%x)\n", __func__, addr);
+//		return -1;
+	}
+
+	return 0;
+}
+
+/** This function is used to write to UTIL internal bus peripherals from the host
+* through indirect access registers.
+* @param[in]	val	32bits value to write
+* @param[in]	addr	Address to write to
+* @param[in]	size	Number of bytes to write
+*
+*/
+void util_bus_write(u32 val, u32 addr, u8 size)
+{
+	u32 offset = addr & 0x3;
+	u32 access_addr;
+
+	access_addr = ((addr & ~0x3) & CLASS_BUS_ACCESS_ADDR_MASK) | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+//	writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
+
+	writel(cpu_to_be32(val << (offset << 3)), UTIL_BUS_ACCESS_WDATA);
+	writel(access_addr, UTIL_BUS_ACCESS_ADDR);
+}
+
+
+/** Reads from UTIL internal bus peripherals from the host
+* through indirect access registers.
+* @param[in] addr	Address to read from
+* @param[in] size	Number of bytes to read
+* @return		the read data
+*
+*/
+u32 util_bus_read(u32 addr, u8 size)
+{
+	u32 offset = addr & 0x3;
+	u32 mask = 0xffffffff >> ((4 - size) << 3);
+	u32 access_addr, val;
+
+	access_addr = ((addr & ~0x3) & CLASS_BUS_ACCESS_ADDR_MASK) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+//	writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
+
+	writel(access_addr, UTIL_BUS_ACCESS_ADDR);
+	val = be32_to_cpu(readl(UTIL_BUS_ACCESS_RDATA));
+
+	return (val >> (offset << 3)) & mask;
+}
+
+/** This function is used to write to CLASS internal bus peripherals (ccu, pe-lem) from the host
+* through indirect access registers.
+* @param[in]	val	32bits value to write
+* @param[in]	addr	Address to write to
+* @param[in]	size	Number of bytes to write
+*
+*/
+void class_bus_write(u32 val, u32 addr, u8 size)
+{
+	u32 offset = addr & 0x3;
+	u32 access_addr;
+
+	access_addr = ((addr & ~0x3) & CLASS_BUS_ACCESS_ADDR_MASK) | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+	writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
+
+	writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
+	writel(access_addr, CLASS_BUS_ACCESS_ADDR);
+}
+
+
+/** Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
+* through indirect access registers.
+* @param[in] addr	Address to read from
+* @param[in] size	Number of bytes to read
+* @return		the read data
+*
+*/
+u32 class_bus_read(u32 addr, u8 size)
+{
+	u32 offset = addr & 0x3;
+	u32 mask = 0xffffffff >> ((4 - size) << 3);
+	u32 access_addr, val;
+	
+	access_addr = ((addr & ~0x3) & CLASS_BUS_ACCESS_ADDR_MASK) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+	writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
+
+	writel(access_addr, CLASS_BUS_ACCESS_ADDR);
+	val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
+
+	return (val >> (offset << 3)) & mask;
+}
+
+
+/** Reads data from the cluster memory (PE_LMEM)
+* @param[out] dst		pointer to the source buffer data are copied to
+* @param[in] len		length in bytes of the amount of data to read from cluster memory
+* @param[in] offset	offset in bytes in the cluster memory where data are read from
+*/
+void pe_lmem_read(u32 *dst, u32 len, u32 offset)
+{
+	u32 len32 = len >> 2;
+	int i = 0;
+
+	for (i = 0; i < len32; dst++, i++, offset += 4)
+		*dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, 4);
+
+	/* FIXME we may have an out of bounds access on dst */
+	if (len & 0x03)
+		*dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, (len & 0x03));
+}
+
+/** Writes data to the cluster memory (PE_LMEM)
+* @param[in] src	pointer to the source buffer data are copied from
+* @param[in] len	length in bytes of the amount of data to write to the cluster memory
+* @param[in] offset	offset in bytes in the cluster memory where data are written to
+*/
+void pe_lmem_write(u32 *src, u32 len, u32 offset)
+{
+	u32 len32 = len >> 2;
+	int i = 0;
+
+	for (i = 0; i < len32; src++, i++, offset += 4)
+		class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, 4);
+
+	/* FIXME we may have an out of bounds access on src */
+	if (len & 0x03)
+		class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len & 0x03));
+}
+
+/**************************** BMU ***************************/
+
+/** Initializes a BMU block.
+* @param[in] base	BMU block base address
+* @param[in] cfg	BMU configuration
+*/
+void bmu_init(void *base, BMU_CFG *cfg)
+{
+	bmu_reset(base);
+
+	bmu_disable(base);
+
+	bmu_set_config(base, cfg);
+}
+
+/** Resets a BMU block.
+* @param[in] base	BMU block base address
+*/
+void bmu_reset(void *base)
+{
+	writel(CORE_SW_RESET, base + BMU_CTRL);
+}
+
+/** Enabled a BMU block.
+* @param[in] base	BMU block base address
+*/
+void bmu_enable(void *base)
+{
+	writel (CORE_ENABLE, base + BMU_CTRL);
+}
+
+/** Disables a BMU block.
+* @param[in] base	BMU block base address
+*/
+void bmu_disable(void *base)
+{
+	writel (CORE_DISABLE, base + BMU_CTRL);
+}
+
+/** Sets the configuration of a BMU block.
+* @param[in] base	BMU block base address
+* @param[in] cfg	BMU configuration
+*/
+void bmu_set_config(void *base, BMU_CFG *cfg)
+{	
+	writel (cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);
+	writel (cfg->count & 0xffff, base + BMU_UCAST_CONFIG);
+	writel (cfg->size & 0xffff, base + BMU_BUF_SIZE);
+//	writel (BMU1_THRES_CNT, base + BMU_THRES);
+
+	/* Interrupts are never used */
+//	writel (0x0, base + BMU_INT_SRC);
+	writel (0x0, base + BMU_INT_ENABLE);
+}
+
+/**************************** GEMAC ***************************/
+
+/** GEMAC block initialization.
+* @param[in] base	GEMAC base address (GEMAC0, GEMAC1, GEMAC2)
+* @param[in] cfg	GEMAC configuration
+*/
+void gemac_init(void *base, void *cfg)
+{
+	gemac_set_config(base, cfg);
+	gemac_set_bus_width(base, 64);
+}
+
+/** GEMAC set speed.
+* @param[in] base	GEMAC base address
+* @param[in] speed	GEMAC speed (10, 100 or 1000 Mbps)
+*/
+void gemac_set_speed(void *base, MAC_SPEED gem_speed)
+{
+	u32 val = readl(base + EMAC_NETWORK_CONFIG);
+
+	val = val & ~EMAC_SPEED_MASK;
+
+	switch (gem_speed)
+	{
+		case SPEED_10M:
+			val &= (~EMAC_PCS_ENABLE);
+			break;
+
+		case SPEED_100M:
+			val = val | EMAC_SPEED_100;
+			val &= (~EMAC_PCS_ENABLE);
+			break;
+
+		case SPEED_1000M:
+			val = val | EMAC_SPEED_1000;
+			val &= (~EMAC_PCS_ENABLE);
+			break;
+
+		case SPEED_1000M_PCS:
+			val = val | EMAC_SPEED_1000;
+			val |= EMAC_PCS_ENABLE;
+			break;
+
+		default:
+			val = val | EMAC_SPEED_100;
+			val &= (~EMAC_PCS_ENABLE);
+		break;
+	}
+	
+	writel (val, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC set duplex.
+* @param[in] base	GEMAC base address
+* @param[in] duplex	GEMAC duplex mode (Full, Half)
+*/
+void gemac_set_duplex(void *base, int duplex)
+{
+	u32 val = readl(base + EMAC_NETWORK_CONFIG);
+
+	if (duplex == DUPLEX_HALF)
+		val = (val & ~EMAC_DUPLEX_MASK) | EMAC_HALF_DUP;
+	else
+		val = (val & ~EMAC_DUPLEX_MASK) | EMAC_FULL_DUP;
+  
+	writel (val, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC set mode.
+* @param[in] base	GEMAC base address
+* @param[in] mode	GEMAC operation mode (MII, RMII, RGMII, SGMII)
+*/
+void gemac_set_mode(void *base, int mode)
+{
+	switch (mode)
+	{
+	case GMII:
+		writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_GMII_MODE_ENABLE, base + EMAC_CONTROL);
+		writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
+		break;
+
+	case RGMII:
+		writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_RGMII_MODE_ENABLE, base + EMAC_CONTROL);
+		writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
+		break;
+
+	case RMII:
+		writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_RMII_MODE_ENABLE, base + EMAC_CONTROL);
+		writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
+		break;
+
+	case MII:
+		writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_MII_MODE_ENABLE, base + EMAC_CONTROL);
+		writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
+		break;
+
+	case SGMII:
+		writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | (EMAC_RMII_MODE_DISABLE | EMAC_RGMII_MODE_DISABLE), base + EMAC_CONTROL);
+		writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_SGMII_MODE_ENABLE, base + EMAC_NETWORK_CONFIG);
+		break;
+
+	default:
+		writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_MII_MODE_ENABLE, base + EMAC_CONTROL);
+		writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
+		break;
+	}
+}
+
+/** GEMAC Enable MDIO: Activate the Management interface.  This is required to program the PHY
+ * @param[in] base       GEMAC base address
+ */
+void gemac_enable_mdio(void *base)
+{
+        u32 data;
+
+        data = readl(base + EMAC_NETWORK_CONTROL);
+        data |= EMAC_MDIO_EN;
+        writel(data, base + EMAC_NETWORK_CONTROL);
+}
+
+/** GEMAC Disable MDIO: Disable the Management interface.
+ * @param[in] base       GEMAC base address
+ */
+void gemac_disable_mdio(void *base)
+{
+        u32 data;
+
+        data = readl(base + EMAC_NETWORK_CONTROL);
+        data &= ~EMAC_MDIO_EN;
+        writel(data, base + EMAC_NETWORK_CONTROL);
+}
+
+/** GEMAC Set MDC clock division
+ * @param[in] base       GEMAC base address
+ * @param[in] base       MDC divider value
+ */
+void gemac_set_mdc_div(void *base, MAC_MDC_DIV gem_mdcdiv)
+{
+        u32 data;
+
+        data = readl(base + EMAC_NETWORK_CONFIG);
+	data &= ~(MDC_DIV_MASK << MDC_DIV_SHIFT);
+        data |= (gem_mdcdiv & MDC_DIV_MASK) << MDC_DIV_SHIFT;
+        writel(data, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC reset function.
+* @param[in] base	GEMAC base address
+*/
+void gemac_reset(void *base)
+{  
+}
+
+/** GEMAC enable function.
+* @param[in] base	GEMAC base address
+*/
+void gemac_enable(void *base)
+{  
+	writel (readl(base + EMAC_NETWORK_CONTROL) | EMAC_TX_ENABLE | EMAC_RX_ENABLE, base + EMAC_NETWORK_CONTROL);
+}
+
+/** GEMAC disable function.
+* @param[in] base	GEMAC base address
+*/
+void gemac_disable(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONTROL) & ~(EMAC_TX_ENABLE | EMAC_RX_ENABLE), base + EMAC_NETWORK_CONTROL);
+}
+
+/** GEMAC set mac address configuration.
+* @param[in] base	GEMAC base address
+* @param[in] addr	MAC address to be configured
+*/
+void gemac_set_address(void *base, SPEC_ADDR *addr)
+{ 
+	writel(addr->one.bottom,	base + EMAC_SPEC1_ADD_BOT);
+	writel(addr->one.top,		base + EMAC_SPEC1_ADD_TOP); 
+	writel(addr->two.bottom,	base + EMAC_SPEC2_ADD_BOT);
+	writel(addr->two.top,		base + EMAC_SPEC2_ADD_TOP);
+	writel(addr->three.bottom,	base + EMAC_SPEC3_ADD_BOT);
+	writel(addr->three.top,		base + EMAC_SPEC3_ADD_TOP);
+	writel(addr->four.bottom,	base + EMAC_SPEC4_ADD_BOT);
+	writel(addr->four.top,		base + EMAC_SPEC4_ADD_TOP);
+} 
+
+/** GEMAC get mac address configuration.
+* @param[in] base	GEMAC base address
+*
+* @return		MAC addresses configured
+*/
+SPEC_ADDR gemac_get_address(void *base)
+{
+	SPEC_ADDR addr;
+	
+	addr.one.bottom = 	readl(base + EMAC_SPEC1_ADD_BOT);
+	addr.one.top = 		readl(base + EMAC_SPEC1_ADD_TOP); 
+	addr.two.bottom =	readl(base + EMAC_SPEC2_ADD_BOT);
+	addr.two.top =		readl(base + EMAC_SPEC2_ADD_TOP);
+	addr.three.bottom =	readl(base + EMAC_SPEC3_ADD_BOT);
+	addr.three.top =	readl(base + EMAC_SPEC3_ADD_TOP);
+	addr.four.bottom =	readl(base + EMAC_SPEC4_ADD_BOT);
+	addr.four.top =		readl(base + EMAC_SPEC4_ADD_TOP);
+	
+	return addr;
+}
+
+/** GEMAC set specific local addresses of the MAC.
+* Rather than setting up all four specific addresses, this function sets them up individually.
+*
+* @param[in] base	GEMAC base address
+* @param[in] addr	MAC address to be configured
+*/
+void gemac_set_laddr1(void *base, MAC_ADDR *address)
+{
+	writel(address->bottom,		base + EMAC_SPEC1_ADD_BOT);
+	writel(address->top,		base + EMAC_SPEC1_ADD_TOP); 
+}
+
+
+void gemac_set_laddr2(void *base, MAC_ADDR *address)
+{
+	writel(address->bottom,		base + EMAC_SPEC2_ADD_BOT);
+	writel(address->top,		base + EMAC_SPEC2_ADD_TOP); 
+}
+
+
+void gemac_set_laddr3(void *base, MAC_ADDR *address)
+{
+	writel(address->bottom,		base + EMAC_SPEC3_ADD_BOT);
+	writel(address->top,		base + EMAC_SPEC3_ADD_TOP); 
+}
+
+
+void gemac_set_laddr4(void *base, MAC_ADDR *address)
+{
+	writel(address->bottom,		base + EMAC_SPEC4_ADD_BOT);
+	writel(address->top,		base + EMAC_SPEC4_ADD_TOP); 
+}
+
+void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index)
+{
+	if (entry_index < 5)
+	{	
+		writel(address->bottom,		base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT);
+		writel(address->top,		base + (entry_index * 8) + EMAC_SPEC1_ADD_TOP);
+	} 
+	else 
+	{
+		writel(address->bottom,		base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_BOT);
+		writel(address->top,		base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_TOP);
+	}
+}
+
+/** Get specific local addresses of the MAC.
+* This allows returning of a single specific address stored in the MAC.
+* @param[in] base	GEMAC base address
+*
+* @return		Specific MAC address 1
+* 
+*/
+MAC_ADDR gem_get_laddr1(void *base)
+{
+	MAC_ADDR addr;
+	addr.bottom = readl(base + EMAC_SPEC1_ADD_BOT);
+	addr.top = readl(base + EMAC_SPEC1_ADD_TOP);
+	return addr;
+}
+
+
+MAC_ADDR gem_get_laddr2(void *base)
+{
+	MAC_ADDR addr;
+	addr.bottom = readl(base + EMAC_SPEC2_ADD_BOT);
+	addr.top = readl(base + EMAC_SPEC2_ADD_TOP);
+	return addr;
+}
+
+
+MAC_ADDR gem_get_laddr3(void *base)
+{
+	MAC_ADDR addr;
+	addr.bottom = readl(base + EMAC_SPEC3_ADD_BOT);
+	addr.top = readl(base + EMAC_SPEC3_ADD_TOP);
+	return addr;
+}
+
+
+MAC_ADDR gem_get_laddr4(void *base)
+{
+	MAC_ADDR addr;
+	addr.bottom = readl(base + EMAC_SPEC4_ADD_BOT);
+	addr.top = readl(base + EMAC_SPEC4_ADD_TOP);
+	return addr;
+}
+
+
+MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index)
+{
+	MAC_ADDR addr;
+
+	if (entry_index < 5)
+	{
+		addr.bottom = readl(base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT);
+		addr.top = readl(base + (entry_index * 8) + EMAC_SPEC1_ADD_TOP);
+	}
+	else
+	{
+		addr.bottom = readl(base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_BOT);
+		addr.top = readl(base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_TOP);
+	}
+
+	return addr;
+}
+
+/** GEMAC allow frames
+* @param[in] base	GEMAC base address
+*/
+void gemac_enable_copy_all(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) & EMAC_ENABLE_COPY_ALL, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC do not allow frames
+* @param[in] base	GEMAC base address
+*/
+void gemac_disable_copy_all(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_COPY_ALL, base + EMAC_NETWORK_CONFIG);
+}
+
+
+
+/** GEMAC allow broadcast function.
+* @param[in] base	GEMAC base address
+*/
+void gemac_allow_broadcast(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_NO_BROADCAST, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC no broadcast function.
+* @param[in] base	GEMAC base address
+*/
+void gemac_no_broadcast(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_NO_BROADCAST, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC enable unicast function.
+* @param[in] base	GEMAC base address
+*/
+void gemac_enable_unicast(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_UNICAST, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC disable unicast function.
+* @param[in] base	GEMAC base address
+*/
+void gemac_disable_unicast(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_UNICAST, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC enable multicast function.
+* @param[in] base	GEMAC base address
+*/
+void gemac_enable_multicast(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_MULTICAST, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC disable multicast function.
+* @param[in]	base	GEMAC base address
+*/
+void gemac_disable_multicast(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_MULTICAST, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC enable fcs rx function.
+* @param[in]	base	GEMAC base address
+*/
+void gemac_enable_fcs_rx(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_FCS_RX, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC disable fcs rx function.
+* @param[in]	base	GEMAC base address
+*/
+void gemac_disable_fcs_rx(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_FCS_RX, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC enable 1536 rx function.
+* @param[in]	base	GEMAC base address
+*/
+void gemac_enable_1536_rx(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_1536_RX, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC disable 1536 rx function.
+* @param[in]	base	GEMAC base address
+*/
+void gemac_disable_1536_rx(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_1536_RX, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC enable pause rx function.
+* @param[in] base	GEMAC base address
+*/
+void gemac_enable_pause_rx(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_PAUSE_RX, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC disable pause rx function.
+* @param[in] base	GEMAC base address
+*/
+void gemac_disable_pause_rx(void *base)
+{
+	writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_PAUSE_RX, base + EMAC_NETWORK_CONFIG);
+}
+
+/** GEMAC enable rx checksum offload function.
+* @param[in] base	GEMAC base address
+*/
+void gemac_enable_rx_checksum_offload(void *base)
+{
+	writel(readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_CHKSUM_RX, base + EMAC_NETWORK_CONFIG);
+	writel(readl(CLASS_L4_CHKSUM_ADDR) | IPV4_CHKSUM_DROP, CLASS_L4_CHKSUM_ADDR);
+}
+
+/** GEMAC disable rx checksum offload function.
+* @param[in] base	GEMAC base address
+*/
+void gemac_disable_rx_checksum_offload(void *base)
+{
+	writel(readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_CHKSUM_RX, base + EMAC_NETWORK_CONFIG);
+	writel(readl(CLASS_L4_CHKSUM_ADDR) & ~IPV4_CHKSUM_DROP, CLASS_L4_CHKSUM_ADDR);
+}
+
+/** Sets Gemac bus width to 64bit
+ * @param[in] base       GEMAC base address
+ * @param[in] width	gemac bus width to be set possible values are 32/64/128
+ * */
+void gemac_set_bus_width(void *base, int width)
+{
+	u32 val = readl(base + EMAC_NETWORK_CONFIG);
+	switch(width) 
+	{
+	case 32:
+		val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_32;
+	case 128:
+		val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_128;
+	case 64:
+	default:
+		val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_64;
+
+	}
+	writel (val, base + EMAC_NETWORK_CONFIG);
+}
+
+/** Sets Gemac configuration.
+* @param[in] base	GEMAC base address
+* @param[in] cfg	GEMAC configuration
+*/
+void gemac_set_config(void *base, GEMAC_CFG *cfg)
+{
+	gemac_set_mode(base, cfg->mode);
+
+	gemac_set_speed(base, cfg->speed);
+
+	gemac_set_duplex(base,cfg->duplex);
+}
+
+
+/**************************** GPI ***************************/
+
+/** Initializes a GPI block.
+* @param[in] base	GPI base address
+* @param[in] cfg	GPI configuration
+*/
+void gpi_init(void *base, GPI_CFG *cfg)
+{ 
+	gpi_reset(base);
+	
+	gpi_disable(base);
+	
+	gpi_set_config(base, cfg);
+}
+
+/** Resets a GPI block.
+* @param[in] base	GPI base address
+*/
+void gpi_reset(void *base)
+{
+	writel (CORE_SW_RESET, base + GPI_CTRL);
+}
+
+/** Enables a GPI block.
+* @param[in] base	GPI base address
+*/
+void gpi_enable(void *base)
+{
+	writel (CORE_ENABLE, base + GPI_CTRL);
+}
+
+/** Disables a GPI block.
+* @param[in] base	GPI base address
+*/
+void gpi_disable(void *base)
+{
+	writel (CORE_DISABLE, base + GPI_CTRL);
+}
+
+
+/** Sets the configuration of a GPI block.
+* @param[in] base	GPI base address
+* @param[in] cfg	GPI configuration
+*/
+void gpi_set_config(void *base, GPI_CFG *cfg)
+{  
+	writel (CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL),	base + GPI_LMEM_ALLOC_ADDR);
+	writel (CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL),	base + GPI_LMEM_FREE_ADDR);
+	writel (CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL),	base + GPI_DDR_ALLOC_ADDR);
+	writel (CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),	base + GPI_DDR_FREE_ADDR);
+	writel (CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR),			base + GPI_CLASS_ADDR);
+ 	writel (DDR_HDR_SIZE,						base + GPI_DDR_DATA_OFFSET);
+	writel (LMEM_HDR_SIZE,						base + GPI_LMEM_DATA_OFFSET);
+	writel (0,							base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
+	writel (0,							base + GPI_DDR_SEC_BUF_DATA_OFFSET);
+	writel ((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE,			base + GPI_HDR_SIZE);
+	writel ((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE,			base + GPI_BUF_SIZE);
+	
+	writel (((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) | GPI_LMEM_BUF_EN),	base + GPI_RX_CONFIG);
+	writel (cfg->tmlf_txthres,					base + GPI_TMLF_TX);
+	writel (cfg->aseq_len,						base + GPI_DTX_ASEQ);
+}
+
+/**************************** CLASSIFIER ***************************/
+
+/** Initializes CLASSIFIER block.
+* @param[in] cfg	CLASSIFIER configuration
+*/
+void class_init(CLASS_CFG *cfg)
+{
+	class_reset();
+	
+	class_disable();
+	
+	class_set_config(cfg);
+}
+
+/** Resets CLASSIFIER block.
+*
+*/
+void class_reset(void)
+{
+	writel(CORE_SW_RESET, CLASS_TX_CTRL);
+}
+
+/** Enables all CLASS-PE's cores.
+*
+*/
+void class_enable(void)
+{
+	writel(CORE_ENABLE, CLASS_TX_CTRL);
+}
+
+/** Disables all CLASS-PE's cores.
+*
+*/
+void class_disable(void)
+{
+	writel(CORE_DISABLE, CLASS_TX_CTRL); 
+}
+
+/** Sets the configuration of the CLASSIFIER block.
+* @param[in] cfg	CLASSIFIER configuration
+*/
+void class_set_config(CLASS_CFG *cfg)
+{
+	if (PLL_CLK_EN == 0)
+		writel(0x0,     CLASS_PE_SYS_CLK_RATIO);        // Clock ratio: for 1:1 the value is 0
+	else
+		writel(0x1,     CLASS_PE_SYS_CLK_RATIO);        // Clock ratio: for 1:2 the value is 1
+
+	writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE,	CLASS_HDR_SIZE);
+	writel(LMEM_BUF_SIZE,				CLASS_LMEM_BUF_SIZE);
+	writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) | CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits),	CLASS_ROUTE_HASH_ENTRY_SIZE);
+	writel(HASH_CRC_PORT_IP | QB2BUS_LE, CLASS_ROUTE_MULTI);
+
+	writel(cfg->route_table_baseaddr,		CLASS_ROUTE_TABLE_BASE);
+	memset(cfg->route_table_baseaddr, 0, ROUTE_TABLE_SIZE);
+
+	writel(CLASS_PE0_RO_DM_ADDR0_VAL,		CLASS_PE0_RO_DM_ADDR0);
+	writel(CLASS_PE0_RO_DM_ADDR1_VAL,		CLASS_PE0_RO_DM_ADDR1);
+	writel(CLASS_PE0_QB_DM_ADDR0_VAL,		CLASS_PE0_QB_DM_ADDR0);
+	writel(CLASS_PE0_QB_DM_ADDR1_VAL,		CLASS_PE0_QB_DM_ADDR1);
+	writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR),	CLASS_TM_INQ_ADDR);
+
+	writel(31, CLASS_AFULL_THRES);
+	writel(31, CLASS_TSQ_FIFO_THRES);
+}
+
+/**************************** TMU ***************************/
+
+/** Initializes TMU block.
+* @param[in] cfg	TMU configuration
+*/
+void tmu_init(TMU_CFG *cfg)
+{
+	int q, phyno;
+	writel(0x3,						TMU_SYS_GENERIC_CONTROL);
+	writel(750,						TMU_INQ_WATERMARK);
+	writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + GPI_INQ_PKTPTR),	TMU_PHY0_INQ_ADDR);
+	writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + GPI_INQ_PKTPTR),	TMU_PHY1_INQ_ADDR);
+	writel(CBUS_VIRT_TO_PFE(EGPI3_BASE_ADDR + GPI_INQ_PKTPTR),	TMU_PHY2_INQ_ADDR);
+	writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + GPI_INQ_PKTPTR),	TMU_PHY3_INQ_ADDR);
+	writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR),		TMU_PHY4_INQ_ADDR);
+	writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR),			TMU_PHY5_INQ_ADDR);
+	writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), 	TMU_BMU_INQ_ADDR);
+
+	writel(0x3FF,	TMU_TDQ0_SCH_CTRL);	// enabling all 10 schedulers [9:0] of each TDQ 
+	writel(0x3FF,	TMU_TDQ1_SCH_CTRL);
+	writel(0x3FF,	TMU_TDQ2_SCH_CTRL);
+	writel(0x3FF,	TMU_TDQ3_SCH_CTRL);
+	
+	if (PLL_CLK_EN == 0)
+		writel(0x0,	TMU_PE_SYS_CLK_RATIO);	// Clock ratio: for 1:1 the value is 0
+	else
+		writel(0x1,	TMU_PE_SYS_CLK_RATIO);	// Clock ratio: for 1:2 the value is 1
+	
+	writel(cfg->llm_base_addr,	TMU_LLM_BASE_ADDR);	// Extra packet pointers will be stored from this address onwards
+	
+	writel(cfg->llm_queue_len,	TMU_LLM_QUE_LEN);
+	writel(0x100,			TMU_CTRL);
+	writel(5,			TMU_TDQ_IIFG_CFG);
+	writel(DDR_BUF_SIZE,		TMU_BMU_BUF_SIZE);
+
+	// set up each queue for tail drop
+	for (phyno = 0; phyno < 4; phyno++)
+	{
+		for (q = 0; q < 16; q++)
+		{
+			u32 qmax;
+			writel((phyno << 8) | q, TMU_TEQ_CTRL);
+			writel(1 << 22, TMU_TEQ_QCFG);
+			qmax = ((phyno == 3) || (q < 8)) ? 255 : 127;
+			writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
+			writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
+		}
+	}
+	writel(0x05, TMU_TEQ_DISABLE_DROPCHK);
+}
+
+/** Enables TMU-PE cores.
+* @param[in] pe_mask	TMU PE mask
+*/
+void tmu_enable(u32 pe_mask)
+{
+	writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);
+}
+
+/** Disables TMU cores.
+* @param[in] pe_mask	TMU PE mask
+*/
+void tmu_disable(u32 pe_mask)
+{
+	writel(readl(TMU_TX_CTRL) & ((~pe_mask) & 0xF), TMU_TX_CTRL);
+}
+
+/**************************** UTIL ***************************/
+
+/** Resets UTIL block.
+*/
+void util_reset(void)
+{
+	writel(CORE_SW_RESET, UTIL_TX_CTRL);
+}
+
+/** Initializes UTIL block.
+* @param[in] cfg	UTIL configuration
+*/
+void util_init(UTIL_CFG *cfg)
+{
+
+	if (PLL_CLK_EN == 0)
+		writel(0x0,     UTIL_PE_SYS_CLK_RATIO);        // Clock ratio: for 1:1 the value is 0
+	else
+		writel(0x1,     UTIL_PE_SYS_CLK_RATIO);        // Clock ratio: for 1:2 the value is 1
+}
+
+/** Enables UTIL-PE core.
+*
+*/
+void util_enable(void)
+{
+	writel(CORE_ENABLE, UTIL_TX_CTRL);
+}
+
+/** Disables UTIL-PE core.
+*
+*/
+void util_disable(void)
+{
+	writel(CORE_DISABLE, UTIL_TX_CTRL);
+}
+
+/** GEMAC PHY Statistics - This function return address of the first statistics register
+* @param[in]	base	GEMAC base address 
+*/
+unsigned int * gemac_get_stats(void *base)
+{
+	return (unsigned int *)(base + EMAC_OCT_TX_BOT);
+}
+
+/**************************** HIF ***************************/
+
+/** Initializes HIF no copy block.
+*
+*/
+void hif_nocpy_init(void)
+{
+	writel(4,							HIF_NOCPY_TX_PORT_NO);
+	writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL),		HIF_NOCPY_LMEM_ALLOC_ADDR);
+	writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR),	HIF_NOCPY_CLASS_ADDR);
+	writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR),	HIF_NOCPY_TMU_PORT0_ADDR);
+}
+
+/** Initializes HIF copy block.
+*
+*/
+void hif_init(void)
+{
+	/*Initialize HIF registers*/
+	writel(HIF_RX_POLL_CTRL_CYCLE<<16|HIF_TX_POLL_CTRL_CYCLE, HIF_POLL_CTRL); 
+}
+
+/** Enable hif tx DMA and interrupt
+*
+*/
+void hif_tx_enable(void)
+{
+	/*TODO not sure poll_cntrl_en is required or not */
+	writel( HIF_CTRL_DMA_EN, HIF_TX_CTRL);
+	//writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), HIF_INT_ENABLE);
+}
+
+/** Disable hif tx DMA and interrupt
+*
+*/
+void hif_tx_disable(void)
+{
+	u32	hif_int;
+
+	writel(0, HIF_TX_CTRL);
+
+	hif_int = readl(HIF_INT_ENABLE);
+	hif_int &= HIF_TXPKT_INT_EN;
+	writel(hif_int, HIF_INT_ENABLE);
+}
+
+/** Enable hif rx DMA and interrupt
+*
+*/
+void hif_rx_enable(void)
+{
+	/*TODO not sure poll_cntrl_en is required or not */
+	writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+	//writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), HIF_INT_ENABLE);
+}
+
+/** Disable hif rx DMA and interrupt
+*
+*/
+void hif_rx_disable(void)
+{
+	u32	hif_int;
+
+	writel(0, HIF_RX_CTRL);
+
+	hif_int = readl(HIF_INT_ENABLE);
+	hif_int &= HIF_RXPKT_INT_EN;
+	writel(hif_int, HIF_INT_ENABLE);
+
+}

drivers/c2000_eth/pfe/cbus.h

diff --git a/drivers/c2000_eth/pfe/cbus.h b/drivers/c2000_eth/pfe/cbus.h
new file mode 100644
index 0000000..8ee2ef7
--- /dev/null
+++ b/drivers/c2000_eth/pfe/cbus.h
@@ -0,0 +1,72 @@
+#ifndef _CBUS_H_
+#define _CBUS_H_
+
+#define EMAC1_BASE_ADDR		(CBUS_BASE_ADDR + 0x200000)
+#define EGPI1_BASE_ADDR		(CBUS_BASE_ADDR + 0x210000)
+#define EMAC2_BASE_ADDR		(CBUS_BASE_ADDR + 0x220000)
+#define EGPI2_BASE_ADDR		(CBUS_BASE_ADDR + 0x230000)
+#define BMU1_BASE_ADDR		(CBUS_BASE_ADDR + 0x240000)
+#define BMU2_BASE_ADDR		(CBUS_BASE_ADDR + 0x250000)
+#define ARB_BASE_ADDR		(CBUS_BASE_ADDR + 0x260000) /* FIXME not documented */
+#define DDR_CONFIG_BASE_ADDR	(CBUS_BASE_ADDR + 0x270000) /* FIXME not documented */
+#define HIF_BASE_ADDR		(CBUS_BASE_ADDR + 0x280000)
+#define HGPI_BASE_ADDR		(CBUS_BASE_ADDR + 0x290000)
+#define LMEM_BASE_ADDR		(CBUS_BASE_ADDR + 0x300000)
+#define LMEM_SIZE		0x10000
+#define LMEM_END		(LMEM_BASE_ADDR + LMEM_SIZE)
+#define TMU_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x310000)
+#define CLASS_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x320000)
+#define EMAC3_BASE_ADDR		(CBUS_BASE_ADDR + 0x330000)
+#define EGPI3_BASE_ADDR		(CBUS_BASE_ADDR + 0x340000)
+#define HIF_NOCPY_BASE_ADDR	(CBUS_BASE_ADDR + 0x350000)
+#define UTIL_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x360000)
+#define CBUS_GPT_BASE_ADDR	(CBUS_BASE_ADDR + 0x370000)
+
+#define IS_LMEM(addr, len)	(((unsigned long)(addr) >= LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= LMEM_END))
+
+/** 
+* \defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR 
+* XXX_MEM_ACCESS_ADDR register bit definitions. 
+* @{
+*/
+#define PE_MEM_ACCESS_WRITE		(1<<31)			/**< Internal Memory Write. */
+#define PE_MEM_ACCESS_READ		(0<<31)			/**< Internal Memory Read. */
+#define PE_MEM_ACCESS_IMEM		(1<<15)
+#define PE_MEM_ACCESS_DMEM		(1<<16)
+#define PE_MEM_ACCESS_BYTE_ENABLE(offset,size)	(((((1 << (size)) - 1) << (4 - (offset) - (size))) & 0xf) << 24)	/**< Byte Enables of the Internal memory access. These are interpred in BE */
+// @}
+#include "cbus/emac.h"
+#include "cbus/gpi.h"
+#include "cbus/bmu.h"
+#include "cbus/hif.h"
+#include "cbus/tmu_csr.h"
+#include "cbus/class_csr.h"
+#include "cbus/hif_nocpy.h"
+#include "cbus/util_csr.h"
+#include "cbus/gpt.h"
+
+
+/* PFE cores states */
+#define CORE_DISABLE	0x00000000 
+#define CORE_ENABLE	0x00000001
+#define CORE_SW_RESET	0x00000002
+
+/* LMEM defines */
+#define LMEM_HDR_SIZE		0x0010
+#define LMEM_BUF_SIZE_LN2	0x7
+#define LMEM_BUF_SIZE		(1 << LMEM_BUF_SIZE_LN2)
+
+/* DDR defines */
+#define DDR_HDR_SIZE		0x0100
+#define DDR_BUF_SIZE_LN2	0xb
+#define DDR_BUF_SIZE		(1 << DDR_BUF_SIZE_LN2)
+
+
+/* Clock generation through PLL */
+#if defined(CONFIG_PLATFORM_PCI)
+#define PLL_CLK_EN	0
+#else
+#define PLL_CLK_EN	1
+#endif
+
+#endif /* _CBUS_H_ */

drivers/c2000_eth/pfe/cbus/bmu.h

diff --git a/drivers/c2000_eth/pfe/cbus/bmu.h b/drivers/c2000_eth/pfe/cbus/bmu.h
new file mode 100644
index 0000000..f3e5e6d
--- /dev/null
+++ b/drivers/c2000_eth/pfe/cbus/bmu.h
@@ -0,0 +1,37 @@
+#ifndef _BMU_H_
+#define _BMU_H_
+
+#define BMU_VERSION		0x000
+#define BMU_CTRL		0x004
+#define BMU_UCAST_CONFIG	0x008
+#define BMU_UCAST_BASE_ADDR	0x00c
+#define BMU_BUF_SIZE		0x010
+#define BMU_BUF_CNT		0x014
+#define BMU_THRES		0x018
+#define BMU_INT_SRC		0x020
+#define BMU_INT_ENABLE		0x024
+#define BMU_ALLOC_CTRL		0x030
+#define BMU_FREE_CTRL		0x034
+#define BMU_FREE_ERR_ADDR	0x038
+#define BMU_CURR_BUF_CNT	0x03c
+#define BMU_MCAST_CNT		0x040
+#define BMU_MCAST_ALLOC_CTRL	0x044
+#define BMU_REM_BUF_CNT		0x048
+#define BMU_LOW_WATERMARK	0x050
+#define BMU_HIGH_WATERMARK	0x054
+#define BMU_INT_MEM_ACCESS	0x100
+
+typedef struct {
+	u32 baseaddr;
+	u32 count;
+	u32 size;
+} BMU_CFG;
+
+
+#define BMU1_BUF_SIZE	LMEM_BUF_SIZE_LN2
+#define BMU2_BUF_SIZE	DDR_BUF_SIZE_LN2
+
+#define BMU2_MCAST_ALLOC_CTRL	BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL
+
+#endif /* _BMU_H_ */
+

drivers/c2000_eth/pfe/cbus/class_csr.h

diff --git a/drivers/c2000_eth/pfe/cbus/class_csr.h b/drivers/c2000_eth/pfe/cbus/class_csr.h
new file mode 100644
index 0000000..f3151ec
--- /dev/null
+++ b/drivers/c2000_eth/pfe/cbus/class_csr.h
@@ -0,0 +1,206 @@
+#ifndef _CLASS_CSR_H_
+#define _CLASS_CSR_H_
+
+/** @file class_csr.h.
+ * class_csr - block containing all the classifier control and status register. Mapped on CBUS and accessible from all PE's and ARM.
+ */
+
+
+#define CLASS_VERSION			(CLASS_CSR_BASE_ADDR + 0x000)
+#define CLASS_TX_CTRL			(CLASS_CSR_BASE_ADDR + 0x004)
+#define CLASS_INQ_PKTPTR		(CLASS_CSR_BASE_ADDR + 0x010)
+#define CLASS_HDR_SIZE			(CLASS_CSR_BASE_ADDR + 0x014)	/**< (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
+#define CLASS_HDR_SIZE_LMEM(off)	((off) & 0x3f)			/**< LMEM header size for the Classifier block.\ Data in the LMEM is written from this offset. */
+#define CLASS_HDR_SIZE_DDR(off)		(((off) & 0x1ff) << 16)		/**< DDR header size for the Classifier block.\ Data in the DDR is written from this offset. */
+
+#define CLASS_PE0_QB_DM_ADDR0		(CLASS_CSR_BASE_ADDR + 0x020)	/**< DMEM address of first [15:0] and second [31:16] buffers on QB side. */
+#define CLASS_PE0_QB_DM_ADDR1		(CLASS_CSR_BASE_ADDR + 0x024)	/**< DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
+
+#define CLASS_PE0_RO_DM_ADDR0		(CLASS_CSR_BASE_ADDR + 0x060)	/**< DMEM address of first [15:0] and second [31:16] buffers on RO side. */
+#define CLASS_PE0_RO_DM_ADDR1		(CLASS_CSR_BASE_ADDR + 0x064)	/**< DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
+
+/** @name Class PE memory access. Allows external PE's and HOST to read/write PMEM/DMEM memory ranges for each classifier PE.
+ */
+//@{
+#define CLASS_MEM_ACCESS_ADDR		(CLASS_CSR_BASE_ADDR + 0x100)	/**< {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]}, See \ref XXX_MEM_ACCESS_ADDR for details. */ 
+#define CLASS_MEM_ACCESS_WDATA		(CLASS_CSR_BASE_ADDR + 0x104)	/**< Internal Memory Access Write Data [31:0] */
+#define CLASS_MEM_ACCESS_RDATA		(CLASS_CSR_BASE_ADDR + 0x108)	/**< Internal Memory Access Read Data [31:0] */
+//@}
+#define CLASS_TM_INQ_ADDR		(CLASS_CSR_BASE_ADDR + 0x114)
+#define CLASS_PE_STATUS			(CLASS_CSR_BASE_ADDR + 0x118)
+
+#define CLASS_PHY1_RX_PKTS		(CLASS_CSR_BASE_ADDR + 0x11c)
+#define CLASS_PHY1_TX_PKTS		(CLASS_CSR_BASE_ADDR + 0x120)
+#define CLASS_PHY1_LP_FAIL_PKTS		(CLASS_CSR_BASE_ADDR + 0x124)
+#define CLASS_PHY1_INTF_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x128)
+#define CLASS_PHY1_INTF_MATCH_PKTS	(CLASS_CSR_BASE_ADDR + 0x12c)
+#define CLASS_PHY1_L3_FAIL_PKTS		(CLASS_CSR_BASE_ADDR + 0x130)
+#define CLASS_PHY1_V4_PKTS		(CLASS_CSR_BASE_ADDR + 0x134)
+#define CLASS_PHY1_V6_PKTS		(CLASS_CSR_BASE_ADDR + 0x138)
+#define CLASS_PHY1_CHKSUM_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x13c)
+#define CLASS_PHY1_TTL_ERR_PKTS		(CLASS_CSR_BASE_ADDR + 0x140)
+#define CLASS_PHY2_RX_PKTS		(CLASS_CSR_BASE_ADDR + 0x144)
+#define CLASS_PHY2_TX_PKTS		(CLASS_CSR_BASE_ADDR + 0x148)
+#define CLASS_PHY2_LP_FAIL_PKTS		(CLASS_CSR_BASE_ADDR + 0x14c)
+#define CLASS_PHY2_INTF_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x150)
+#define CLASS_PHY2_INTF_MATCH_PKTS	(CLASS_CSR_BASE_ADDR + 0x154)
+#define CLASS_PHY2_L3_FAIL_PKTS		(CLASS_CSR_BASE_ADDR + 0x158)
+#define CLASS_PHY2_V4_PKTS		(CLASS_CSR_BASE_ADDR + 0x15c)
+#define CLASS_PHY2_V6_PKTS		(CLASS_CSR_BASE_ADDR + 0x160)
+#define CLASS_PHY2_CHKSUM_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x164)
+#define CLASS_PHY2_TTL_ERR_PKTS		(CLASS_CSR_BASE_ADDR + 0x168)
+#define CLASS_PHY3_RX_PKTS		(CLASS_CSR_BASE_ADDR + 0x16c)
+#define CLASS_PHY3_TX_PKTS		(CLASS_CSR_BASE_ADDR + 0x170)
+#define CLASS_PHY3_LP_FAIL_PKTS		(CLASS_CSR_BASE_ADDR + 0x174)
+#define CLASS_PHY3_INTF_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x178)
+#define CLASS_PHY3_INTF_MATCH_PKTS	(CLASS_CSR_BASE_ADDR + 0x17c)
+#define CLASS_PHY3_L3_FAIL_PKTS		(CLASS_CSR_BASE_ADDR + 0x180)
+#define CLASS_PHY3_V4_PKTS		(CLASS_CSR_BASE_ADDR + 0x184)
+#define CLASS_PHY3_V6_PKTS		(CLASS_CSR_BASE_ADDR + 0x188)
+#define CLASS_PHY3_CHKSUM_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x18c)
+#define CLASS_PHY3_TTL_ERR_PKTS		(CLASS_CSR_BASE_ADDR + 0x190)
+#define CLASS_PHY1_ICMP_PKTS		(CLASS_CSR_BASE_ADDR + 0x194)
+#define CLASS_PHY1_IGMP_PKTS		(CLASS_CSR_BASE_ADDR + 0x198)
+#define CLASS_PHY1_TCP_PKTS		(CLASS_CSR_BASE_ADDR + 0x19c)
+#define CLASS_PHY1_UDP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1a0)
+#define CLASS_PHY2_ICMP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1a4)
+#define CLASS_PHY2_IGMP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1a8)
+#define CLASS_PHY2_TCP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1ac)
+#define CLASS_PHY2_UDP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1b0)
+#define CLASS_PHY3_ICMP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1b4)
+#define CLASS_PHY3_IGMP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1b8)
+#define CLASS_PHY3_TCP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1bc)
+#define CLASS_PHY3_UDP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1c0)
+#define CLASS_PHY4_ICMP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1c4)
+#define CLASS_PHY4_IGMP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1c8)
+#define CLASS_PHY4_TCP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1cc)
+#define CLASS_PHY4_UDP_PKTS		(CLASS_CSR_BASE_ADDR + 0x1d0)
+#define CLASS_PHY4_RX_PKTS		(CLASS_CSR_BASE_ADDR + 0x1d4)
+#define CLASS_PHY4_TX_PKTS		(CLASS_CSR_BASE_ADDR + 0x1d8)
+#define CLASS_PHY4_LP_FAIL_PKTS		(CLASS_CSR_BASE_ADDR + 0x1dc)
+#define CLASS_PHY4_INTF_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x1e0)
+#define CLASS_PHY4_INTF_MATCH_PKTS	(CLASS_CSR_BASE_ADDR + 0x1e4)
+#define CLASS_PHY4_L3_FAIL_PKTS		(CLASS_CSR_BASE_ADDR + 0x1e8)
+#define CLASS_PHY4_V4_PKTS		(CLASS_CSR_BASE_ADDR + 0x1ec)
+#define CLASS_PHY4_V6_PKTS		(CLASS_CSR_BASE_ADDR + 0x1f0)
+#define CLASS_PHY4_CHKSUM_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x1f4)
+#define CLASS_PHY4_TTL_ERR_PKTS		(CLASS_CSR_BASE_ADDR + 0x1f8)
+
+#define CLASS_PE_SYS_CLK_RATIO		(CLASS_CSR_BASE_ADDR + 0x200)
+#define CLASS_AFULL_THRES		(CLASS_CSR_BASE_ADDR + 0x204)
+#define CLASS_GAP_BETWEEN_READS		(CLASS_CSR_BASE_ADDR + 0x208)
+#define CLASS_MAX_BUF_CNT		(CLASS_CSR_BASE_ADDR + 0x20c)
+#define CLASS_TSQ_FIFO_THRES		(CLASS_CSR_BASE_ADDR + 0x210)
+#define CLASS_TSQ_MAX_CNT		(CLASS_CSR_BASE_ADDR + 0x214)
+#define CLASS_IRAM_DATA_0		(CLASS_CSR_BASE_ADDR + 0x218)
+#define CLASS_IRAM_DATA_1		(CLASS_CSR_BASE_ADDR + 0x21c)
+#define CLASS_IRAM_DATA_2		(CLASS_CSR_BASE_ADDR + 0x220)
+#define CLASS_IRAM_DATA_3		(CLASS_CSR_BASE_ADDR + 0x224)
+
+#define CLASS_BUS_ACCESS_ADDR		(CLASS_CSR_BASE_ADDR + 0x228)
+#define CLASS_BUS_ACCESS_ADDR_MASK	(0x0001FFFF)	//bit 23:0 of PE peripheral address are stored in CLASS_BUS_ACCESS_ADDR
+
+#define CLASS_BUS_ACCESS_WDATA		(CLASS_CSR_BASE_ADDR + 0x22c)
+#define CLASS_BUS_ACCESS_RDATA		(CLASS_CSR_BASE_ADDR + 0x230)
+
+#define CLASS_ROUTE_HASH_ENTRY_SIZE	(CLASS_CSR_BASE_ADDR + 0x234)		/**< (route_entry_size[9:0], route_hash_size[23:16] (this is actually ln2(size))) */
+#define CLASS_ROUTE_ENTRY_SIZE(size)	 ((size) & 0x1ff)
+#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
+
+#define CLASS_ROUTE_TABLE_BASE		(CLASS_CSR_BASE_ADDR + 0x238)
+
+#define CLASS_ROUTE_MULTI		(CLASS_CSR_BASE_ADDR + 0x23c)
+#define CLASS_SMEM_OFFSET		(CLASS_CSR_BASE_ADDR + 0x240)
+#define CLASS_LMEM_BUF_SIZE		(CLASS_CSR_BASE_ADDR + 0x244)
+#define CLASS_VLAN_ID			(CLASS_CSR_BASE_ADDR + 0x248)
+#define CLASS_BMU1_BUF_FREE		(CLASS_CSR_BASE_ADDR + 0x24c)
+#define CLASS_USE_TMU_INQ		(CLASS_CSR_BASE_ADDR + 0x250)
+#define CLASS_VLAN_ID1			(CLASS_CSR_BASE_ADDR + 0x254)
+
+#define CLASS_BUS_ACCESS_BASE		(CLASS_CSR_BASE_ADDR + 0x258)
+#define CLASS_BUS_ACCESS_BASE_MASK	(0xFF000000)	//bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE
+
+#define CLASS_HIF_PARSE			(CLASS_CSR_BASE_ADDR + 0x25c)
+
+#define CLASS_HOST_PE0_GP		(CLASS_CSR_BASE_ADDR + 0x260)
+#define CLASS_PE0_GP			(CLASS_CSR_BASE_ADDR + 0x264)
+#define CLASS_HOST_PE1_GP		(CLASS_CSR_BASE_ADDR + 0x268)
+#define CLASS_PE1_GP			(CLASS_CSR_BASE_ADDR + 0x26c)
+#define CLASS_HOST_PE2_GP		(CLASS_CSR_BASE_ADDR + 0x270)
+#define CLASS_PE2_GP			(CLASS_CSR_BASE_ADDR + 0x274)
+#define CLASS_HOST_PE3_GP		(CLASS_CSR_BASE_ADDR + 0x278)
+#define CLASS_PE3_GP			(CLASS_CSR_BASE_ADDR + 0x27c)
+#define CLASS_HOST_PE4_GP		(CLASS_CSR_BASE_ADDR + 0x280)
+#define CLASS_PE4_GP			(CLASS_CSR_BASE_ADDR + 0x284)
+#define CLASS_HOST_PE5_GP		(CLASS_CSR_BASE_ADDR + 0x288)
+#define CLASS_PE5_GP			(CLASS_CSR_BASE_ADDR + 0x28c)
+
+#define CLASS_PE_INT_SRC		(CLASS_CSR_BASE_ADDR + 0x290)
+#define CLASS_PE_INT_ENABLE		(CLASS_CSR_BASE_ADDR + 0x294)
+
+#define CLASS_TPID0_TPID1		(CLASS_CSR_BASE_ADDR + 0x298)
+#define CLASS_TPID2			(CLASS_CSR_BASE_ADDR + 0x29c)
+
+#define CLASS_L4_CHKSUM_ADDR		(CLASS_CSR_BASE_ADDR + 0x2a0)
+
+#define CLASS_PE0_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2a4)
+#define CLASS_PE1_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2a8)
+#define CLASS_PE2_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2ac)
+#define CLASS_PE3_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2b0)
+#define CLASS_PE4_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2b4)
+#define CLASS_PE5_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2b8)
+
+#define CLASS_STATE			(CLASS_CSR_BASE_ADDR + 0x2bc)
+
+/* CLASS defines */
+#define CLASS_PBUF_SIZE			0x100	/* Fixed by hardware */
+#define CLASS_PBUF_HEADER_OFFSET	0x80	/* Can be configured */
+
+#define CLASS_PBUF0_BASE_ADDR		0x000						/* Can be configured */
+#define CLASS_PBUF1_BASE_ADDR		(CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)	/* Can be configured */
+#define CLASS_PBUF2_BASE_ADDR		(CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)	/* Can be configured */
+#define CLASS_PBUF3_BASE_ADDR		(CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)	/* Can be configured */
+
+#define CLASS_PBUF0_HEADER_BASE_ADDR	(CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF1_HEADER_BASE_ADDR	(CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF2_HEADER_BASE_ADDR	(CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF3_HEADER_BASE_ADDR	(CLASS_PBUF3_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
+
+#define CLASS_PE0_RO_DM_ADDR0_VAL	((CLASS_PBUF1_BASE_ADDR << 16) | CLASS_PBUF0_BASE_ADDR)
+#define CLASS_PE0_RO_DM_ADDR1_VAL	((CLASS_PBUF3_BASE_ADDR << 16) | CLASS_PBUF2_BASE_ADDR)
+
+#define CLASS_PE0_QB_DM_ADDR0_VAL	((CLASS_PBUF1_HEADER_BASE_ADDR << 16) | CLASS_PBUF0_HEADER_BASE_ADDR)
+#define CLASS_PE0_QB_DM_ADDR1_VAL	((CLASS_PBUF3_HEADER_BASE_ADDR << 16) | CLASS_PBUF2_HEADER_BASE_ADDR)
+
+#define CLASS_ROUTE_SIZE		128
+#define CLASS_ROUTE_HASH_BITS		20
+#define CLASS_ROUTE_HASH_MASK		((1 << CLASS_ROUTE_HASH_BITS) - 1)
+
+#define	CLASS_ROUTE0_BASE_ADDR	0x400						/* Can be configured */
+#define CLASS_ROUTE1_BASE_ADDR	(CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE)	/* Can be configured */
+#define CLASS_ROUTE2_BASE_ADDR	(CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE)	/* Can be configured */
+#define CLASS_ROUTE3_BASE_ADDR	(CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE)	/* Can be configured */
+
+#define TWO_LEVEL_ROUTE		(1 << 0)
+#define PHYNO_IN_HASH		(1 << 1)
+#define HW_ROUTE_FETCH		(1 << 3)
+#define HW_BRIDGE_FETCH		(1 << 5)
+#define IP_ALIGNED		(1 << 6)
+#define ARC_HIT_CHECK_EN	(1 << 7)
+#define CLASS_TOE		(1 << 11)
+#define HASH_NORMAL		(0 << 12)
+#define HASH_CRC_PORT		(1 << 12)
+#define HASH_CRC_IP		(2 << 12)
+#define HASH_CRC_PORT_IP	(3 << 12)
+#define QB2BUS_LE		(1 << 15)
+
+#define	TCP_CHKSUM_DROP		(1 << 0)
+#define	UDP_CHKSUM_DROP		(1 << 1)
+#define	IPV4_CHKSUM_DROP	(1 << 9)
+
+typedef struct {
+	u32 route_table_baseaddr;
+	u32 route_table_hash_bits;
+} CLASS_CFG;
+
+#endif /* _CLASS_CSR_H_ */

drivers/c2000_eth/pfe/cbus/emac.h

diff --git a/drivers/c2000_eth/pfe/cbus/emac.h b/drivers/c2000_eth/pfe/cbus/emac.h
new file mode 100644
index 0000000..5c0caa2
--- /dev/null
+++ b/drivers/c2000_eth/pfe/cbus/emac.h
@@ -0,0 +1,246 @@
+#ifndef _EMAC_H_
+#define _EMAC_H_
+
+#define EMAC_NETWORK_CONTROL		0x000
+#define EMAC_NETWORK_CONFIG		0x004
+#define EMAC_NETWORK_STATUS		0x008
+
+#define EMAC_PHY_MANAGEMENT		0x034
+
+#define EMAC_SPEC1_ADD_BOT		0x088
+#define EMAC_SPEC1_ADD_TOP		0x08c
+#define EMAC_SPEC2_ADD_BOT		0x090
+#define EMAC_SPEC2_ADD_TOP		0x094
+#define EMAC_SPEC3_ADD_BOT		0x098
+#define EMAC_SPEC3_ADD_TOP		0x09c
+#define EMAC_SPEC4_ADD_BOT		0x0a0
+#define EMAC_SPEC4_ADD_TOP		0x0a4
+
+#define EMAC_SPEC1_ADD_MASK_BOT		0x0c8
+#define EMAC_SPEC1_ADD_MASK_TOP		0x0cc
+
+#define EMAC_OCT_TX_BOT			0x100
+#define EMAC_OCT_TX_TOP			0x104
+#define EMAC_STATS_FRAMES_TX		0x108
+#define EMAC_BROADCAST_TX		0x10C
+#define EMAC_MULTICAST_TX		0x110
+#define EMAC_STATS_PAUSE_TX		0x114
+#define EMAC_FRAME64_TX			0x118
+#define EMAC_FRAME65_TX			0x11C
+#define EMAC_FRAME128_TX		0x120
+#define EMAC_FRAME256_TX		0x124
+#define EMAC_FRAME512_TX		0x128
+#define EMAC_FRAME1024_TX		0x12C
+#define EMAC_FRAME1519_TX		0x130
+#define EMAC_STATS_TX_URUN		0x134
+#define EMAC_STATS_SINGLE_COL		0x138
+#define EMAC_STATS_MULTI_COL		0x13C
+#define EMAC_STATS_EXCESS_COL		0x140
+#define EMAC_STATS_LATE_COL		0x144
+#define EMAC_STATS_DEF_TX		0x148
+#define EMAC_STATS_CRS_ERRORS		0x14C
+#define EMAC_OCT_RX_BOT			0x150
+#define EMAC_OCT_RX_TOP			0x154
+#define EMAC_STATS_FRAMES_RX		0x158
+#define EMAC_BROADCAST_RX		0x15C
+#define EMAC_MULTICAST_RX		0x160
+#define EMAC_STATS_PAUSE_RX		0x164
+#define EMAC_FRAME64_RX			0x168
+#define EMAC_FRAME65_RX			0x16C
+#define EMAC_FRAME128_RX		0x170
+#define EMAC_FRAME256_RX		0x174
+#define EMAC_FRAME512_RX		0x178
+#define EMAC_FRAME1024_RX		0x17C
+#define EMAC_FRAME1519_RX		0x180
+#define EMAC_STATS_USIZE_FRAMES		0x184
+#define EMAC_STATS_EXCESS_LEN		0x188
+#define EMAC_STATS_JABBERS		0x18C
+#define EMAC_STATS_FCS_ERRORS		0x190
+#define EMAC_STATS_LENGTH_ERRORS	0x194
+#define EMAC_STATS_RX_SYM_ERR		0x198
+#define EMAC_STATS_ALIGN_ERRORS		0x19C
+#define EMAC_STATS_RX_RES_ERR		0x1a0
+#define EMAC_STATS_RX_ORUN		0x1a4
+
+#define EMAC_SPEC5_ADD_BOT		0x300
+#define EMAC_SPEC5_ADD_TOP		0x304
+#define EMAC_SPEC6_ADD_BOT		0x308
+#define EMAC_SPEC6_ADD_TOP		0x30c
+#define EMAC_SPEC7_ADD_BOT		0x310
+#define EMAC_SPEC7_ADD_TOP		0x314
+#define EMAC_SPEC8_ADD_BOT		0x318
+#define EMAC_SPEC8_ADD_TOP		0x31c
+#define EMAC_SPEC9_ADD_BOT		0x320
+#define EMAC_SPEC9_ADD_TOP		0x324
+#define EMAC_SPEC10_ADD_BOT		0x328
+#define EMAC_SPEC10_ADD_TOP		0x32c
+#define EMAC_SPEC11_ADD_BOT		0x330
+#define EMAC_SPEC11_ADD_TOP		0x334
+#define EMAC_SPEC12_ADD_BOT		0x338
+#define EMAC_SPEC12_ADD_TOP		0x33c
+#define EMAC_SPEC13_ADD_BOT		0x340
+#define EMAC_SPEC13_ADD_TOP		0x344
+#define EMAC_SPEC14_ADD_BOT		0x348
+#define EMAC_SPEC14_ADD_TOP		0x34c
+#define EMAC_SPEC15_ADD_BOT		0x350
+#define EMAC_SPEC15_ADD_TOP		0x354
+#define EMAC_SPEC16_ADD_BOT		0x358
+#define EMAC_SPEC16_ADD_TOP		0x35c
+#define EMAC_SPEC17_ADD_BOT		0x360
+#define EMAC_SPEC17_ADD_TOP		0x364
+#define EMAC_SPEC18_ADD_BOT		0x368
+#define EMAC_SPEC18_ADD_TOP		0x36c
+#define EMAC_SPEC19_ADD_BOT		0x370
+#define EMAC_SPEC19_ADD_TOP		0x374
+#define EMAC_SPEC20_ADD_BOT		0x378
+#define EMAC_SPEC20_ADD_TOP		0x37c
+#define EMAC_SPEC21_ADD_BOT		0x380
+#define EMAC_SPEC21_ADD_TOP		0x384
+#define EMAC_SPEC22_ADD_BOT		0x388
+#define EMAC_SPEC22_ADD_TOP		0x38c
+#define EMAC_SPEC23_ADD_BOT		0x390
+#define EMAC_SPEC23_ADD_TOP		0x394
+#define EMAC_SPEC24_ADD_BOT		0x398
+#define EMAC_SPEC24_ADD_TOP		0x39c
+#define EMAC_SPEC25_ADD_BOT		0x3a0
+#define EMAC_SPEC25_ADD_TOP		0x3a4
+#define EMAC_SPEC26_ADD_BOT		0x3a8
+#define EMAC_SPEC26_ADD_TOP		0x3ac
+#define EMAC_SPEC27_ADD_BOT		0x3b0
+#define EMAC_SPEC27_ADD_TOP		0x3b4
+#define EMAC_SPEC28_ADD_BOT		0x3b8
+#define EMAC_SPEC28_ADD_TOP		0x3bc
+#define EMAC_SPEC29_ADD_BOT		0x3c0
+#define EMAC_SPEC29_ADD_TOP		0x3c4
+#define EMAC_SPEC30_ADD_BOT		0x3c8
+#define EMAC_SPEC30_ADD_TOP		0x3cc
+#define EMAC_SPEC31_ADD_BOT		0x3d0
+#define EMAC_SPEC31_ADD_TOP		0x3d4
+#define EMAC_SPEC32_ADD_BOT		0x3d8
+#define EMAC_SPEC32_ADD_TOP		0x3dc
+
+#define EMAC_CONTROL			0x7a0
+
+
+/* GEMAC definitions and settings */
+
+#define EMAC_PORT_0			0
+#define EMAC_PORT_1			1
+#define EMAC_PORT_2			2
+
+/* The possible operating speeds of the MAC, currently supporting 10, 100 and
+ * 1000Mb modes.
+ */
+typedef enum {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS} MAC_SPEED;
+
+#define GMII	1
+#define MII	2
+#define RMII	3
+#define RGMII	4
+#define SGMII	5
+
+#define DUPLEX_HALF	0x00
+#define DUPLEX_FULL	0x01
+
+/* EMAC_NETWORK_CONTROL bits definition */
+#define EMAC_RX_ENABLE			(1 << 2)
+#define EMAC_TX_ENABLE			(1 << 3)
+#define EMAC_MDIO_EN                    (1 << 4)
+
+
+/* EMAC_NETWORK_CONFIG bits definition */
+#define EMAC_SPEED_100		(1 << 0)
+#define EMAC_HALF_DUP		(0 << 1)
+#define EMAC_FULL_DUP		(1 << 1)
+#define EMAC_DUPLEX_MASK	(1 << 1)
+#define EMAC_ENABLE_JUMBO_FRAME (1 << 3)
+#define EMAC_ENABLE_COPY_ALL	(1 << 4)	
+#define EMAC_NO_BROADCAST	(1 << 5)
+#define EMAC_ENABLE_MULTICAST	(1 << 6)
+#define EMAC_ENABLE_UNICAST	(1 << 7)
+#define EMAC_ENABLE_1536_RX	(1 << 8)
+#define EMAC_SPEED_1000		(1 << 10)
+#define EMAC_PCS_ENABLE		(1 << 11)
+#define EMAC_ENABLE_PAUSE_RX	(1 << 13)
+#define EMAC_REMOVE_FCS		(1 << 17)
+#define EMAC_ENABLE_CHKSUM_RX	(1 << 24)
+#define EMAC_ENABLE_FCS_RX	(1 << 26)
+#define EMAC_SGMII_MODE_ENABLE	(1 << 27)
+#define EMAC_DATA_BUS_WIDTH_SHIFT	21
+#define EMAC_DATA_BUS_WIDTH_MASK (0x3 << EMAC_DATA_BUS_WIDTH_SHIFT)
+#define EMAC_DATA_BUS_WIDTH_32	(0x00 << EMAC_DATA_BUS_WIDTH_SHIFT)
+#define EMAC_DATA_BUS_WIDTH_64	(0x01 << EMAC_DATA_BUS_WIDTH_SHIFT)
+#define EMAC_DATA_BUS_WIDTH_128	(0x10 << EMAC_DATA_BUS_WIDTH_SHIFT)
+
+#define EMAC_SPEED_MASK		(EMAC_SPEED_100 | EMAC_SPEED_1000)
+
+/* EMAC_CONTROL bits definition */
+#define EMAC_TWO_BYTES_IP_ALIGN		(1 << 0) // two bytes IP alignement
+
+//RMII enable – bit 1 / RGMII enable – bit 2
+#define EMAC_RMII_MODE_ENABLE		((1 << 1) | (0 << 2))
+#define EMAC_RMII_MODE_DISABLE		(0 << 1)
+#define EMAC_RGMII_MODE_ENABLE		((0 << 1) | (1 << 2))
+#define EMAC_RGMII_MODE_DISABLE		(0 << 2)
+#define EMAC_MII_MODE_ENABLE		(EMAC_RMII_MODE_DISABLE | EMAC_RGMII_MODE_DISABLE)
+#define EMAC_GMII_MODE_ENABLE		(EMAC_RMII_MODE_DISABLE | EMAC_RGMII_MODE_DISABLE)
+#define EMAC_MODE_MASK			(0x3 << 1)
+
+/* Default configuration */
+#define EMAC0_DEFAULT_DUPLEX_MODE	FULLDUPLEX 
+#define EMAC0_DEFAULT_EMAC_MODE		RGMII      
+#define EMAC0_DEFAULT_EMAC_SPEED	SPEED_1000M   
+
+#define EMAC1_DEFAULT_DUPLEX_MODE	FULLDUPLEX 
+#define EMAC1_DEFAULT_EMAC_MODE		RGMII      
+#define EMAC1_DEFAULT_EMAC_SPEED	SPEED_1000M   
+
+#define EMAC2_DEFAULT_DUPLEX_MODE	FULLDUPLEX 
+#define EMAC2_DEFAULT_EMAC_MODE		RGMII      
+#define EMAC2_DEFAULT_EMAC_SPEED	SPEED_1000M   
+
+/* The possible MDC clock division of the MAC, currently supporting 8, 16 , 32,
+ * 48, 64, 96, 128, 224.
+ */
+typedef enum { MDC_DIV_8, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, MDC_DIV_64,
+        MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} MAC_MDC_DIV;
+
+#define MDC_DIV_MASK    0x7
+#define MDC_DIV_SHIFT   18
+
+/* The Address organisation for the MAC device.  All addresses are split into
+ * two 32-bit register fields.  The first one (bottom) is the lower 32-bits of
+ * the address and the other field are the high order bits - this may be 16-bits
+ * in the case of MAC addresses, or 32-bits for the hash address.
+ * In terms of memory storage, the first item (bottom) is assumed to be at a
+ * lower address location than 'top'. i.e. top should be at address location of
+ * 'bottom' + 4 bytes.
+ */
+typedef struct {
+	u32 bottom;     /* Lower 32-bits of address. */
+	u32 top;        /* Upper 32-bits of address. */
+} MAC_ADDR;
+
+
+/* The following is the organisation of the address filters section of the MAC
+ * registers.  The Cadence MAC contains four possible specific address match
+ * addresses, if an incoming frame corresponds to any one of these four
+ * addresses then the frame will be copied to memory.
+ * It is not necessary for all four of the address match registers to be
+ * programmed, this is application dependant.
+ */
+typedef struct {
+	MAC_ADDR one;        /* Specific address register 1. */
+	MAC_ADDR two;        /* Specific address register 2. */
+	MAC_ADDR three;      /* Specific address register 3. */
+	MAC_ADDR four;       /* Specific address register 4. */
+} SPEC_ADDR;
+
+typedef struct {
+	u32 mode; 
+	u32 speed;
+	u32 duplex;
+} GEMAC_CFG;
+
+#endif /* _EMAC_H_ */

drivers/c2000_eth/pfe/cbus/gpi.h

diff --git a/drivers/c2000_eth/pfe/cbus/gpi.h b/drivers/c2000_eth/pfe/cbus/gpi.h
new file mode 100644
index 0000000..b97da27
--- /dev/null
+++ b/drivers/c2000_eth/pfe/cbus/gpi.h
@@ -0,0 +1,58 @@
+#ifndef _GPI_H_
+#define _GPI_H_
+
+#define GPI_VERSION			0x00
+#define GPI_CTRL			0x04
+#define GPI_RX_CONFIG			0x08
+#define GPI_HDR_SIZE			0x0c
+#define GPI_BUF_SIZE			0x10
+#define GPI_LMEM_ALLOC_ADDR		0x14
+#define GPI_LMEM_FREE_ADDR		0x18
+#define GPI_DDR_ALLOC_ADDR		0x1c
+#define GPI_DDR_FREE_ADDR		0x20
+#define GPI_CLASS_ADDR			0x24
+#define GPI_DRX_FIFO			0x28
+#define GPI_TRX_FIFO			0x2c
+#define GPI_INQ_PKTPTR			0x30
+#define GPI_DDR_DATA_OFFSET		0x34
+#define GPI_LMEM_DATA_OFFSET		0x38
+#define GPI_TMLF_TX			0x4c
+#define GPI_DTX_ASEQ			0x50
+#define GPI_FIFO_STATUS_ADDR		0x54
+#define GPI_FIFO_DEBUG			0x58
+#define GPI_TX_PAUSE_TIME		0x5c
+#define GPI_LMEM_SEC_BUF_DATA_OFFSET	0x60
+#define GPI_DDR_SEC_BUF_DATA_OFFSET	0x64
+
+typedef struct {
+	u32 lmem_rtry_cnt;
+	u32 tmlf_txthres;
+	u32 aseq_len;
+} GPI_CFG;
+
+
+/* GPI commons defines */ 
+#define GPI_LMEM_BUF_EN		0x1
+#define GPI_DDR_BUF_EN		0x1
+
+/* EGPI 1 defines */ 
+#define EGPI1_LMEM_RTRY_CNT	0x40
+#define EGPI1_TMLF_TXTHRES	0xBC
+#define EGPI1_ASEQ_LEN		0x50
+
+/* EGPI 2 defines */ 
+#define EGPI2_LMEM_RTRY_CNT	0x40
+#define EGPI2_TMLF_TXTHRES	0xBC
+#define EGPI2_ASEQ_LEN		0x40
+
+/* EGPI 3 defines */ 
+#define EGPI3_LMEM_RTRY_CNT	0x40
+#define EGPI3_TMLF_TXTHRES	0xBC
+#define EGPI3_ASEQ_LEN		0x40
+
+/* HGPI defines */ 
+#define HGPI_LMEM_RTRY_CNT	0x40
+#define HGPI_TMLF_TXTHRES	0xBC
+#define HGPI_ASEQ_LEN		0x40
+
+#endif /* _GPI_H_ */

drivers/c2000_eth/pfe/cbus/gpt.h

diff --git a/drivers/c2000_eth/pfe/cbus/gpt.h b/drivers/c2000_eth/pfe/cbus/gpt.h
new file mode 100644
index 0000000..f8c114b
--- /dev/null
+++ b/drivers/c2000_eth/pfe/cbus/gpt.h
@@ -0,0 +1,11 @@
+#ifndef _CBUS_GPT_H_
+#define _CBUS_GPT_H_
+
+#define CBUS_GPT_VERSION	 (CBUS_GPT_BASE_ADDR + 0x00)
+#define CBUS_GPT_STATUS		 (CBUS_GPT_BASE_ADDR + 0x04)
+#define CBUS_GPT_CONFIG		 (CBUS_GPT_BASE_ADDR + 0x08)
+#define CBUS_GPT_COUNTER	 (CBUS_GPT_BASE_ADDR + 0x0c)
+#define CBUS_GPT_PERIOD		 (CBUS_GPT_BASE_ADDR + 0x10)
+#define CBUS_GPT_WIDTH		 (CBUS_GPT_BASE_ADDR + 0x14)
+
+#endif /* _CBUS_GPT_H_ */

drivers/c2000_eth/pfe/cbus/hif.h

diff --git a/drivers/c2000_eth/pfe/cbus/hif.h b/drivers/c2000_eth/pfe/cbus/hif.h
new file mode 100644
index 0000000..a4dd7c2
--- /dev/null
+++ b/drivers/c2000_eth/pfe/cbus/hif.h
@@ -0,0 +1,62 @@
+#ifndef _HIF_H_
+#define _HIF_H_
+
+/** @file hif.h.
+ * hif - PFE hif block control and status register. Mapped on CBUS and accessible from all PE's and ARM.
+ */
+#define HIF_VERSION		(HIF_BASE_ADDR + 0x00)
+#define HIF_TX_CTRL		(HIF_BASE_ADDR + 0x04)
+#define HIF_TX_CURR_BD_ADDR	(HIF_BASE_ADDR + 0x08)
+#define HIF_TX_ALLOC		(HIF_BASE_ADDR + 0x0c)
+#define HIF_TX_BDP_ADDR		(HIF_BASE_ADDR + 0x10)
+#define HIF_TX_STATUS		(HIF_BASE_ADDR + 0x14)
+#define HIF_RX_CTRL		(HIF_BASE_ADDR + 0x20)
+#define HIF_RX_BDP_ADDR		(HIF_BASE_ADDR + 0x24)
+#define HIF_RX_STATUS		(HIF_BASE_ADDR + 0x30)
+#define HIF_INT_SRC		(HIF_BASE_ADDR + 0x34)
+#define HIF_INT_ENABLE		(HIF_BASE_ADDR + 0x38)
+#define HIF_POLL_CTRL		(HIF_BASE_ADDR + 0x3c)
+#define HIF_RX_CURR_BD_ADDR	(HIF_BASE_ADDR + 0x40)
+#define HIF_RX_ALLOC		(HIF_BASE_ADDR + 0x44)
+#define HIF_TX_DMA_STATUS	(HIF_BASE_ADDR + 0x48)
+#define HIF_RX_DMA_STATUS	(HIF_BASE_ADDR + 0x4c)
+#define HIF_INT_COAL		(HIF_BASE_ADDR + 0x50)
+
+/*HIF_INT_SRC/ HIF_INT_ENABLE control bits */
+#define HIF_INT        		(1 << 0)
+#define HIF_RXBD_INT   		(1 << 1)
+#define HIF_RXPKT_INT  		(1 << 2)
+#define HIF_TXBD_INT   		(1 << 3)
+#define HIF_TXPKT_INT  		(1 << 4)
+
+/*HIF_TX_CTRL bits */
+#define HIF_CTRL_DMA_EN			(1<<0)
+#define HIF_CTRL_BDP_POLL_CTRL_EN	(1<<1)
+#define HIF_CTRL_BDP_CH_START_WSTB	(1<<2)
+
+/*HIF_INT_ENABLE bits */
+#define HIF_INT_EN		(1 << 0)
+#define HIF_RXBD_INT_EN		(1 << 1)
+#define HIF_RXPKT_INT_EN	(1 << 2)
+#define HIF_TXBD_INT_EN		(1 << 3)
+#define HIF_TXPKT_INT_EN	(1 << 4)
+
+/*HIF_POLL_CTRL bits*/
+#define HIF_RX_POLL_CTRL_CYCLE	0x0400
+#define HIF_TX_POLL_CTRL_CYCLE	0x0400
+
+/*Buffer descriptor control bits */
+#define BD_CTRL_BUFLEN_MASK	(0xffff)
+#define BD_BUF_LEN(x)		(x & BD_CTRL_BUFLEN_MASK)
+#define BD_CTRL_CBD_INT_EN	(1 << 16)
+#define BD_CTRL_PKT_INT_EN	(1 << 17)
+#define BD_CTRL_LIFM		(1 << 18)
+#define BD_CTRL_LAST_BD		(1 << 19)
+#define BD_CTRL_DIR		(1 << 20)
+#define BD_CTRL_PKT_XFER	(1 << 24)
+#define BD_CTRL_DESC_EN		(1 << 31)
+#define BD_CTRL_PARSE_DISABLE	(1 << 25)
+#define BD_CTRL_BRFETCH_DISABLE	(1 << 26)
+#define BD_CTRL_RTFETCH_DISABLE	(1 << 27)
+
+#endif /* _HIF_H_ */

drivers/c2000_eth/pfe/cbus/hif_nocpy.h

diff --git a/drivers/c2000_eth/pfe/cbus/hif_nocpy.h b/drivers/c2000_eth/pfe/cbus/hif_nocpy.h
new file mode 100644
index 0000000..93cb946
--- /dev/null
+++ b/drivers/c2000_eth/pfe/cbus/hif_nocpy.h
@@ -0,0 +1,33 @@
+#ifndef _HIF_NOCPY_H_
+#define _HIF_NOCPY_H_
+
+#define HIF_NOCPY_VERSION		(HIF_NOCPY_BASE_ADDR + 0x00)
+#define HIF_NOCPY_TX_CTRL		(HIF_NOCPY_BASE_ADDR + 0x04)
+#define HIF_NOCPY_TX_CURR_BD_ADDR	(HIF_NOCPY_BASE_ADDR + 0x08)
+#define HIF_NOCPY_TX_ALLOC		(HIF_NOCPY_BASE_ADDR + 0x0c)
+#define HIF_NOCPY_TX_BDP_ADDR		(HIF_NOCPY_BASE_ADDR + 0x10)
+#define HIF_NOCPY_TX_STATUS		(HIF_NOCPY_BASE_ADDR + 0x14)
+#define HIF_NOCPY_RX_CTRL		(HIF_NOCPY_BASE_ADDR + 0x20)
+#define HIF_NOCPY_RX_BDP_ADDR		(HIF_NOCPY_BASE_ADDR + 0x24)
+#define HIF_NOCPY_RX_STATUS		(HIF_NOCPY_BASE_ADDR + 0x30)
+#define HIF_NOCPY_INT_SRC		(HIF_NOCPY_BASE_ADDR + 0x34)
+#define HIF_NOCPY_INT_ENABLE		(HIF_NOCPY_BASE_ADDR + 0x38)
+#define HIF_NOCPY_POLL_CTRL		(HIF_NOCPY_BASE_ADDR + 0x3c)
+#define HIF_NOCPY_RX_CURR_BD_ADDR	(HIF_NOCPY_BASE_ADDR + 0x40)
+#define HIF_NOCPY_RX_ALLOC		(HIF_NOCPY_BASE_ADDR + 0x44)
+#define HIF_NOCPY_TX_DMA_STATUS		(HIF_NOCPY_BASE_ADDR + 0x48)
+#define HIF_NOCPY_RX_DMA_STATUS		(HIF_NOCPY_BASE_ADDR + 0x4c)
+#define HIF_NOCPY_RX_INQ0_PKTPTR	(HIF_NOCPY_BASE_ADDR + 0x50)
+#define HIF_NOCPY_RX_INQ1_PKTPTR	(HIF_NOCPY_BASE_ADDR + 0x54)
+#define HIF_NOCPY_TX_PORT_NO		(HIF_NOCPY_BASE_ADDR + 0x60)
+#define HIF_NOCPY_LMEM_ALLOC_ADDR	(HIF_NOCPY_BASE_ADDR + 0x64)
+#define HIF_NOCPY_CLASS_ADDR		(HIF_NOCPY_BASE_ADDR + 0x68)
+#define HIF_NOCPY_TMU_PORT0_ADDR	(HIF_NOCPY_BASE_ADDR + 0x70)
+#define HIF_NOCPY_TMU_PORT1_ADDR	(HIF_NOCPY_BASE_ADDR + 0x74)
+#define HIF_NOCPY_TMU_PORT2_ADDR	(HIF_NOCPY_BASE_ADDR + 0x7c)
+#define HIF_NOCPY_TMU_PORT3_ADDR	(HIF_NOCPY_BASE_ADDR + 0x80)
+#define HIF_NOCPY_TMU_PORT4_ADDR	(HIF_NOCPY_BASE_ADDR + 0x84)
+#define HIF_NOCPY_INT_COAL		(HIF_NOCPY_BASE_ADDR + 0x90)
+
+
+#endif /* _HIF_NOCPY_H_ */

drivers/c2000_eth/pfe/cbus/tmu_csr.h

diff --git a/drivers/c2000_eth/pfe/cbus/tmu_csr.h b/drivers/c2000_eth/pfe/cbus/tmu_csr.h
new file mode 100644
index 0000000..5d1d7be
--- /dev/null
+++ b/drivers/c2000_eth/pfe/cbus/tmu_csr.h
@@ -0,0 +1,93 @@
+#ifndef _TMU_CSR_H_
+#define _TMU_CSR_H_
+
+#define TMU_VERSION			(TMU_CSR_BASE_ADDR + 0x000)
+#define TMU_INQ_WATERMARK		(TMU_CSR_BASE_ADDR + 0x004)
+#define TMU_PHY_INQ_PKTPTR		(TMU_CSR_BASE_ADDR + 0x008)
+#define TMU_PHY_INQ_PKTINFO		(TMU_CSR_BASE_ADDR + 0x00c)
+#define TMU_PHY_INQ_FIFO_CNT		(TMU_CSR_BASE_ADDR + 0x010)
+#define TMU_SYS_GENERIC_CONTROL		(TMU_CSR_BASE_ADDR + 0x014)
+#define TMU_SYS_GENERIC_STATUS		(TMU_CSR_BASE_ADDR + 0x018)
+#define TMU_SYS_GEN_CON0		(TMU_CSR_BASE_ADDR + 0x01c)
+#define TMU_SYS_GEN_CON1		(TMU_CSR_BASE_ADDR + 0x020)
+#define TMU_SYS_GEN_CON2		(TMU_CSR_BASE_ADDR + 0x024)
+#define TMU_SYS_GEN_CON3		(TMU_CSR_BASE_ADDR + 0x028)
+#define TMU_SYS_GEN_CON4		(TMU_CSR_BASE_ADDR + 0x02c)
+#define TMU_TEQ_DISABLE_DROPCHK		(TMU_CSR_BASE_ADDR + 0x030)
+#define TMU_TEQ_CTRL			(TMU_CSR_BASE_ADDR + 0x034)
+#define TMU_TEQ_QCFG			(TMU_CSR_BASE_ADDR + 0x038)
+#define TMU_TEQ_QCUR			(TMU_CSR_BASE_ADDR + 0x03c)
+#define TMU_TEQ_QAVG			(TMU_CSR_BASE_ADDR + 0x040)
+#define TMU_TEQ_WREG_PROB		(TMU_CSR_BASE_ADDR + 0x044)
+#define TMU_TEQ_QAVG_WGT		(TMU_CSR_BASE_ADDR + 0x048)
+#define TMU_TEQ_HW_PROB_CFG0		(TMU_CSR_BASE_ADDR + 0x04c)
+#define TMU_TEQ_HW_PROB_CFG1		(TMU_CSR_BASE_ADDR + 0x050)
+#define TMU_TEQ_HW_PROB_CFG2		(TMU_CSR_BASE_ADDR + 0x054)
+#define TMU_TEQ_HW_PROB_CFG3		(TMU_CSR_BASE_ADDR + 0x058)
+#define TMU_TEQ_HW_PROB_CFG4		(TMU_CSR_BASE_ADDR + 0x05c)
+#define TMU_TEQ_HW_PROB_CFG5		(TMU_CSR_BASE_ADDR + 0x060)
+#define TMU_TEQ_HW_PROB_CFG6		(TMU_CSR_BASE_ADDR + 0x064)
+#define TMU_TEQ_HW_PROB_CFG7		(TMU_CSR_BASE_ADDR + 0x068)
+#define TMU_TEQ_HW_PROB_CFG8		(TMU_CSR_BASE_ADDR + 0x06c)
+#define TMU_TEQ_HW_PROB_CFG9		(TMU_CSR_BASE_ADDR + 0x070)
+#define TMU_TEQ_HW_PROB_CFG10		(TMU_CSR_BASE_ADDR + 0x074)
+#define TMU_TEQ_HW_PROB_CFG11		(TMU_CSR_BASE_ADDR + 0x078)
+#define TMU_TEQ_HW_PROB_CFG12		(TMU_CSR_BASE_ADDR + 0x07c)
+#define TMU_TEQ_HW_PROB_CFG13		(TMU_CSR_BASE_ADDR + 0x080)
+#define TMU_TEQ_HW_PROB_CFG14		(TMU_CSR_BASE_ADDR + 0x084)
+#define TMU_TEQ_HW_PROB_CFG15		(TMU_CSR_BASE_ADDR + 0x088)
+#define TMU_TEQ_HW_PROB_CFG16		(TMU_CSR_BASE_ADDR + 0x08c)
+#define TMU_TEQ_HW_PROB_CFG17		(TMU_CSR_BASE_ADDR + 0x090)
+#define TMU_TEQ_HW_PROB_CFG18		(TMU_CSR_BASE_ADDR + 0x094)
+#define TMU_TEQ_HW_PROB_CFG19		(TMU_CSR_BASE_ADDR + 0x098)
+#define TMU_TEQ_HW_PROB_CFG20		(TMU_CSR_BASE_ADDR + 0x09c)
+#define TMU_TEQ_HW_PROB_CFG21		(TMU_CSR_BASE_ADDR + 0x0a0)
+#define TMU_TEQ_HW_PROB_CFG22		(TMU_CSR_BASE_ADDR + 0x0a4)
+#define TMU_TEQ_HW_PROB_CFG23		(TMU_CSR_BASE_ADDR + 0x0a8)
+#define TMU_TEQ_HW_PROB_CFG24		(TMU_CSR_BASE_ADDR + 0x0ac)
+#define TMU_TEQ_HW_PROB_CFG25		(TMU_CSR_BASE_ADDR + 0x0b0)
+#define TMU_TDQ_IIFG_CFG		(TMU_CSR_BASE_ADDR + 0x0b4)
+#define TMU_TDQ0_SCH_CTRL		(TMU_CSR_BASE_ADDR + 0x0b8)	/**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY0 */
+#define TMU_LLM_CTRL			(TMU_CSR_BASE_ADDR + 0x0bc)
+#define TMU_LLM_BASE_ADDR		(TMU_CSR_BASE_ADDR + 0x0c0)
+#define TMU_LLM_QUE_LEN			(TMU_CSR_BASE_ADDR + 0x0c4)
+#define TMU_LLM_QUE_HEADPTR		(TMU_CSR_BASE_ADDR + 0x0c8)
+#define TMU_LLM_QUE_TAILPTR		(TMU_CSR_BASE_ADDR + 0x0cc)
+#define TMU_LLM_QUE_DROPCNT		(TMU_CSR_BASE_ADDR + 0x0d0)
+#define TMU_INT_EN			(TMU_CSR_BASE_ADDR + 0x0d4)
+#define TMU_INT_SRC			(TMU_CSR_BASE_ADDR + 0x0d8)
+#define TMU_INQ_STAT			(TMU_CSR_BASE_ADDR + 0x0dc)
+#define TMU_CTRL			(TMU_CSR_BASE_ADDR + 0x0e0)
+
+#define TMU_MEM_ACCESS_ADDR		(TMU_CSR_BASE_ADDR + 0x0e4)	/**< [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory Write [27:24] Byte Enables of the Internal memory access [23:0] Address of the internal memory. This address is used to access both the PM and DM of all the PE's */
+#define TMU_MEM_ACCESS_WDATA		(TMU_CSR_BASE_ADDR + 0x0e8)	/**< Internal Memory Access Write Data */
+#define TMU_MEM_ACCESS_RDATA		(TMU_CSR_BASE_ADDR + 0x0ec)	/**< Internal Memory Access Read Data. The commands are blocked at the mem_access only */
+
+#define TMU_PHY0_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x0f0)	/**< [31:0] PHY0 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
+#define TMU_PHY1_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x0f4)	/**< [31:0] PHY1 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
+#define TMU_PHY2_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x0f8)	/**< [31:0] PHY2 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
+#define TMU_PHY3_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x0fc)	/**< [31:0] PHY3 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
+#define TMU_BMU_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x100)
+#define TMU_TX_CTRL			(TMU_CSR_BASE_ADDR + 0x104)
+
+#define TMU_BUS_ACCESS_WDATA		(TMU_CSR_BASE_ADDR + 0x108)
+#define TMU_BUS_ACCESS			(TMU_CSR_BASE_ADDR + 0x10c)
+#define TMU_BUS_ACCESS_RDATA		(TMU_CSR_BASE_ADDR + 0x110)
+
+#define TMU_PE_SYS_CLK_RATIO		(TMU_CSR_BASE_ADDR + 0x114)
+#define TMU_PE_STATUS			(TMU_CSR_BASE_ADDR + 0x118)
+#define TMU_TEQ_MAX_THRESHOLD		(TMU_CSR_BASE_ADDR + 0x11c)
+#define TMU_PHY4_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x134)	/**< [31:0] PHY4 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
+#define TMU_TDQ1_SCH_CTRL		(TMU_CSR_BASE_ADDR + 0x138)	/**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY1 */
+#define TMU_TDQ2_SCH_CTRL		(TMU_CSR_BASE_ADDR + 0x13c)	/**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY2 */
+#define TMU_TDQ3_SCH_CTRL		(TMU_CSR_BASE_ADDR + 0x140)	/**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY3 */
+#define TMU_BMU_BUF_SIZE		(TMU_CSR_BASE_ADDR + 0x144)
+#define TMU_PHY5_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x148)	/**< [31:0] PHY5 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
+
+
+typedef struct {
+	u32 llm_base_addr;
+	u32 llm_queue_len;
+} TMU_CFG;
+
+#endif /* _TMU_CSR_H_ */

drivers/c2000_eth/pfe/cbus/util_csr.h

diff --git a/drivers/c2000_eth/pfe/cbus/util_csr.h b/drivers/c2000_eth/pfe/cbus/util_csr.h
new file mode 100644
index 0000000..1b0f773
--- /dev/null
+++ b/drivers/c2000_eth/pfe/cbus/util_csr.h
@@ -0,0 +1,42 @@
+#ifndef _UTIL_CSR_H_
+#define _UTIL_CSR_H_
+
+#define UTIL_VERSION			(UTIL_CSR_BASE_ADDR + 0x000)
+#define UTIL_TX_CTRL			(UTIL_CSR_BASE_ADDR + 0x004)
+#define UTIL_INQ_PKTPTR			(UTIL_CSR_BASE_ADDR + 0x010)
+
+#define UTIL_HDR_SIZE			(UTIL_CSR_BASE_ADDR + 0x014)
+
+#define UTIL_PE0_QB_DM_ADDR0		(UTIL_CSR_BASE_ADDR + 0x020)
+#define UTIL_PE0_QB_DM_ADDR1		(UTIL_CSR_BASE_ADDR + 0x024)
+#define UTIL_PE0_RO_DM_ADDR0		(UTIL_CSR_BASE_ADDR + 0x060)
+#define UTIL_PE0_RO_DM_ADDR1		(UTIL_CSR_BASE_ADDR + 0x064)
+
+#define UTIL_MEM_ACCESS_ADDR		(UTIL_CSR_BASE_ADDR + 0x100)
+#define UTIL_MEM_ACCESS_WDATA		(UTIL_CSR_BASE_ADDR + 0x104)
+#define UTIL_MEM_ACCESS_RDATA		(UTIL_CSR_BASE_ADDR + 0x108)
+
+#define UTIL_TM_INQ_ADDR		(UTIL_CSR_BASE_ADDR + 0x114)
+#define UTIL_PE_STATUS			(UTIL_CSR_BASE_ADDR + 0x118)
+
+#define UTIL_PE_SYS_CLK_RATIO		(UTIL_CSR_BASE_ADDR + 0x200)
+#define UTIL_AFULL_THRES		(UTIL_CSR_BASE_ADDR + 0x204)
+#define UTIL_GAP_BETWEEN_READS		(UTIL_CSR_BASE_ADDR + 0x208)
+#define UTIL_MAX_BUF_CNT		(UTIL_CSR_BASE_ADDR + 0x20c)
+#define UTIL_TSQ_FIFO_THRES		(UTIL_CSR_BASE_ADDR + 0x210)
+#define UTIL_TSQ_MAX_CNT		(UTIL_CSR_BASE_ADDR + 0x214)
+#define UTIL_IRAM_DATA_0		(UTIL_CSR_BASE_ADDR + 0x218)
+#define UTIL_IRAM_DATA_1		(UTIL_CSR_BASE_ADDR + 0x21c)
+#define UTIL_IRAM_DATA_2		(UTIL_CSR_BASE_ADDR + 0x220)
+#define UTIL_IRAM_DATA_3		(UTIL_CSR_BASE_ADDR + 0x224)
+
+#define UTIL_BUS_ACCESS_ADDR		(UTIL_CSR_BASE_ADDR + 0x228)
+#define UTIL_BUS_ACCESS_WDATA		(UTIL_CSR_BASE_ADDR + 0x22c)
+#define UTIL_BUS_ACCESS_RDATA		(UTIL_CSR_BASE_ADDR + 0x230)
+
+#define UTIL_INQ_AFULL_THRES		(UTIL_CSR_BASE_ADDR + 0x234)
+
+typedef struct {
+} UTIL_CFG;
+
+#endif /* _UTIL_CSR_H_ */

drivers/c2000_eth/pfe/class.h

diff --git a/drivers/c2000_eth/pfe/class.h b/drivers/c2000_eth/pfe/class.h
new file mode 100644
index 0000000..33ad826
--- /dev/null
+++ b/drivers/c2000_eth/pfe/class.h
@@ -0,0 +1,142 @@
+#ifndef _CLASS_H_
+#define _CLASS_H_
+
+#define CLASS_DMEM_BASE_ADDR	0x00000000
+#define CLASS_DMEM_SIZE		0x2000
+#define CLASS_DMEM_END		(CLASS_DMEM_BASE_ADDR + CLASS_DMEM_SIZE)
+#define CLASS_PMEM_BASE_ADDR	0x00010000
+
+#define CBUS_BASE_ADDR		0xc0000000
+#define CLASS_APB_BASE_ADDR	0xc1000000
+#define CLASS_AHB1_BASE_ADDR	0xc2000000
+#define CLASS_AHB2_BASE_ADDR	0xc3000000
+
+#include "cbus.h"
+
+#define GPT_BASE_ADDR		(CLASS_APB_BASE_ADDR + 0x00000)
+#define UART_BASE_ADDR		(CLASS_APB_BASE_ADDR + 0x10000)
+#define PERG_BASE_ADDR		(CLASS_APB_BASE_ADDR + 0x20000)
+#define EFET_BASE_ADDR		(CLASS_APB_BASE_ADDR + 0x40000)
+
+#define MAC_HASH_BASE_ADDR	(CLASS_AHB1_BASE_ADDR + 0x30000)
+#define VLAN_HASH_BASE_ADDR	(CLASS_AHB1_BASE_ADDR + 0x50000)
+
+#define PE_LMEM_BASE_ADDR	(CLASS_AHB2_BASE_ADDR + 0x10000)
+#define PE_LMEM_SIZE		0x8000
+#define PE_LMEM_END		(PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
+#define CCU_BASE_ADDR		(CLASS_AHB2_BASE_ADDR + 0x20000)
+
+#define IS_DMEM(addr, len)	(((unsigned long)(addr) >= CLASS_DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= CLASS_DMEM_END))
+#define IS_PE_LMEM(addr, len)	(((unsigned long)(addr) >= PE_LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PE_LMEM_END))
+
+
+#include "gpt.h"
+#include "uart.h"
+#include "class/perg.h"
+#include "class/efet.h"
+#include "class/mac_hash.h"
+#include "class/vlan_hash.h"
+#include "class/ccu.h"
+
+
+#define CLASS_MAX_PBUFFERS	4
+
+#define PBUF_HWPARSE_OFFSET	0x10	/* Fixed by hardware */
+
+#define PAYLOAD_DMEM_MAX_SIZE	(CLASS_PBUF_SIZE - CLASS_PBUF_HEADER_OFFSET - sizeof(class_rx_hdr_t))
+
+#define PHYPORT_0               0x0
+#define PHYPORT_1               0x1
+#define HOST_PORT_NO		0x3
+
+#define   ACT_SRC_MAC_REPLACE 	(1 << (4+0))
+#define   ACT_VLAN_REPLACE		(1 << (4+3))
+#define   ACT_TCPCHKSUM_REPLACE	(1 << (4+2))
+#define   ACT_VLAN_ADD			(1 << (4+1))
+
+#define MIN_PKT_SIZE		56
+
+#define PARSE_ETH_TYPE		(1 << 0)
+#define PARSE_VLAN_TYPE		(1 << 1)
+#define PARSE_PPPOE_TYPE	(1 << 2)
+#define PARSE_ARP_TYPE		(1 << 3)
+#define PARSE_MCAST_TYPE	(1 << 4)
+#define PARSE_IP_TYPE		(1 << 5)
+#define PARSE_IPV6_TYPE		(1 << 6)
+#define PARSE_IPV4_TYPE		(1 << 7)
+
+#define PARSE_IPX_TYPE		(1 << 9)
+
+#define PARSE_UDP_FLOW		(1 << 11)
+#define PARSE_TCP_FLOW		(1 << 12)
+#define PARSE_ICMP_FLOW		(1 << 13)
+#define PARSE_IGMP_FLOW		(1 << 14)
+#define PARSE_FRAG_FLOW		(1 << 15)
+
+#define PARSE_HIF_PKT		(1 << 23)
+#define PARSE_ARC_HIT		(1 << 24)
+#define PARSE_PKT_OVERFLOW	(1 << 25)
+
+#define PARSE_PROTO_MISMATCH	(1 << 28)
+#define PARSE_L3_MISMATCH	(1 << 29)
+#define PARSE_L2_MISMATCH	(1 << 30)
+#define PARSE_INCOMPLETE	(1 << 31)
+
+
+typedef struct _hwparse_t {
+	u16	sid;
+	u16	connid;
+	u8	toevec;
+	u8	pLayer2Hdr;
+	u8	pLayer3Hdr;
+	u8	pLayer4Hdr;
+	u16	vlanid;
+	u16	ifParseFlags;
+	u32	parseFlags;
+	u16	srcport;
+	u16	dstport;
+	u32	proto:8;
+	u32	port:4;
+	u32	hash:20;
+	u64	rte_res_valid:1;
+	u64	vlan_res_valid:1;
+	u64	dst_res_valid:1;
+	u64	src_res_valid:1;
+	u64	vlan_lookup:20;
+	u64	dst_lookup:20;
+	u64	src_lookup:20;
+} hwparse_t;
+
+
+typedef struct {
+	u32	next_ptr;	/* ptr to the start of the first DDR buffer */
+	u16	length;		/* total packet length */
+	u16	phyno;		/* input physical port number */
+	u32	status;		/* gemac status bits */
+	u32	res;		/* reserved for software usage */
+} class_rx_hdr_t;
+
+
+typedef struct {
+	u8	num_cpy;	/* no of copies to send out from RO block, for each there must be a corresponding tx pre-header */
+	u8	dma_len;	/* len to be DMAed to DDR mem, including all tx pre-headers */
+	u16	src_addr;	/* class dmem source address, pointing to first tx pre-header */
+	u32	dst_addr;	/* DDR memory destination address of first tx pre-header, must be so packet data is continuous in DDR */
+	u32	res1;		/* reserved for software usage - queue number? */
+	u16	res2;		/* reserved for software usage */
+	u16	tsv;		/* time stamp val */
+} class_tx_desc_t;
+
+
+typedef struct {
+	u8	start_data_off;		/* packet data start offset, relative to start of this tx pre-header */
+	u8	start_buf_off;		/* this tx pre-header start offset, relative to start of DDR buffer */
+	u16	pkt_length;		/* total packet lenght */
+	u8	act_phyno;		/* action phy number */
+	u8	queueno;		/* queueno */
+	u16	src_mac_msb;		/* indicates src_mac 47:32 */
+	u32	src_mac_lsb;		/* indicates src_mac 31:0 */
+	u32	vlanid;			/* vlanid */
+} class_tx_hdr_t;
+
+#endif /* _CLASS_H_ */

drivers/c2000_eth/pfe/class/ccu.h

diff --git a/drivers/c2000_eth/pfe/class/ccu.h b/drivers/c2000_eth/pfe/class/ccu.h
new file mode 100644
index 0000000..2c43d97
--- /dev/null
+++ b/drivers/c2000_eth/pfe/class/ccu.h
@@ -0,0 +1,10 @@
+#ifndef _CCU_H_
+#define _CCU_H_
+
+#define CCU_ADDR	(CCU_BASE_ADDR + 0x00)
+#define CCU_CNT		(CCU_BASE_ADDR + 0x04)
+#define CCU_STATUS	(CCU_BASE_ADDR + 0x08)
+#define CCU_VAL		(CCU_BASE_ADDR + 0x0c)
+
+#endif /* _CCU_H_ */
+

drivers/c2000_eth/pfe/class/efet.h

diff --git a/drivers/c2000_eth/pfe/class/efet.h b/drivers/c2000_eth/pfe/class/efet.h
new file mode 100644
index 0000000..4f3cc25
--- /dev/null
+++ b/drivers/c2000_eth/pfe/class/efet.h
@@ -0,0 +1,21 @@
+#ifndef _CLASS_EFET_H_
+#define _CLASS_EFET_H_
+
+#define CLASS_EFET_ENTRY_ADDR		(EFET_BASE_ADDR + 0x00)
+#define CLASS_EFET_ENTRY_SIZE		(EFET_BASE_ADDR + 0x04)
+#define CLASS_EFET_ENTRY_DMEM_ADDR	(EFET_BASE_ADDR + 0x08)
+#define CLASS_EFET_ENTRY_STATUS		(EFET_BASE_ADDR + 0x0c)
+#define CLASS_EFET_ENTRY_ENDIAN		(EFET_BASE_ADDR + 0x10)
+
+#define CBUS2DMEM	0
+#define DMEM2CBUS	1
+
+#define EFET2BUS_LE     (1 << 0)
+#define PE2BUS_LE	(1 << 1)
+
+void class_efet(u32 cbus_addr, u32 dmem_addr, u32 len, u32 dir);
+void class_efet_wait(void);
+void class_efet_sync(u32 cbus_addr, u32 dmem_addr, u32 len, u32 dir);
+
+#endif /* _CLASS_EFET_H_ */
+

drivers/c2000_eth/pfe/class/mac_hash.h

diff --git a/drivers/c2000_eth/pfe/class/mac_hash.h b/drivers/c2000_eth/pfe/class/mac_hash.h
new file mode 100644
index 0000000..68023b4
--- /dev/null
+++ b/drivers/c2000_eth/pfe/class/mac_hash.h
@@ -0,0 +1,28 @@
+#ifndef _MAC_HASH_H_
+#define _MAC_HASH_H_
+
+#define MAC_HASH_REQ1_BASE_ADDR		(MAC_HASH_BASE_ADDR + 0x000)
+#define MAC_HASH_REQ2_BASE_ADDR		(MAC_HASH_BASE_ADDR + 0x020)
+#define MAC_HASH_REQ3_BASE_ADDR		(MAC_HASH_BASE_ADDR + 0x040)
+#define MAC_HASH_REQ4_BASE_ADDR		(MAC_HASH_BASE_ADDR + 0x060)
+#define MAC_HASH_REQ5_BASE_ADDR		(MAC_HASH_BASE_ADDR + 0x080)
+#define MAC_HASH_REQ6_BASE_ADDR		(MAC_HASH_BASE_ADDR + 0x0a0)
+#define MAC_HASH_REQ7_BASE_ADDR		(MAC_HASH_BASE_ADDR + 0x0c0)
+#define MAC_HASH_REQ8_BASE_ADDR		(MAC_HASH_BASE_ADDR + 0x0e0)
+
+#define MAC_HASH_REQ_CMD(i)		(MAC_HASH_REQ##i##_BASE_ADDR + 0x000)
+#define MAC_HASH_REQ_MAC1_ADDR(i)	(MAC_HASH_REQ##i##_BASE_ADDR + 0x004)
+#define MAC_HASH_REQ_MAC2_ADDR(i)	(MAC_HASH_REQ##i##_BASE_ADDR + 0x008)
+#define MAC_HASH_REQ_MASK1_ADDR(i)	(MAC_HASH_REQ##i##_BASE_ADDR + 0x00c)
+#define MAC_HASH_REQ_MASK2_ADDR(i)	(MAC_HASH_REQ##i##_BASE_ADDR + 0x010)
+#define MAC_HASH_REQ_ENTRY(i)		(MAC_HASH_REQ##i##_BASE_ADDR + 0x014)
+#define MAC_HASH_REQ_STATUS(i)		(MAC_HASH_REQ##i##_BASE_ADDR + 0x018)
+#define MAC_HASH_REQ_ENTRY_MAYCH(i)	(MAC_HASH_REQ##i##_BASE_ADDR + 0x01c)
+
+
+#define MAC_HASH_FREELIST_PTR_HEAD	(MAC_HASH_BASE_ADDR + 0x100)
+#define MAC_HASH_FREELIST_PTR_TAIL	(MAC_HASH_BASE_ADDR + 0x104)
+#define MAC_HASH_FREELIST_ENTRIES_ADDR	(MAC_HASH_BASE_ADDR + 0x108)
+
+#endif /* _MAC_HASH_H_ */
+

drivers/c2000_eth/pfe/class/perg.h

diff --git a/drivers/c2000_eth/pfe/class/perg.h b/drivers/c2000_eth/pfe/class/perg.h
new file mode 100644
index 0000000..7297171
--- /dev/null
+++ b/drivers/c2000_eth/pfe/class/perg.h
@@ -0,0 +1,21 @@
+#ifndef _PERG_H_
+#define _PERG_H_
+
+#define PERG_QB_BUF_STATUS		(PERG_BASE_ADDR + 0x00)
+#define PERG_RO_BUF_STATUS		(PERG_BASE_ADDR + 0x04)
+#define PERG_CLR_QB_BUF_STATUS		(PERG_BASE_ADDR + 0x08)
+#define PERG_SET_RO_BUF_STATUS		(PERG_BASE_ADDR + 0x0c)
+#define PERG_CLR_RO_ERR_PKT		(PERG_BASE_ADDR + 0x10)
+#define PERG_CLR_BMU2_ERR_PKT		(PERG_BASE_ADDR + 0x14)
+
+#define PERG_ID				(PERG_BASE_ADDR + 0x18)
+#define PERG_TIMER1			(PERG_BASE_ADDR + 0x1c)
+#define PERG_TIMER2			(PERG_BASE_ADDR + 0x20)
+#define PERG_BUF1			(PERG_BASE_ADDR + 0x24)
+#define PERG_BUF2			(PERG_BASE_ADDR + 0x28)
+#define PERG_HOST_GP			(PERG_BASE_ADDR + 0x2c)
+#define PERG_PE_GP			(PERG_BASE_ADDR + 0x30)
+#define PERG_INT_ENABLE			(PERG_BASE_ADDR + 0x34)
+#define PERG_INT_SRC			(PERG_BASE_ADDR + 0x38)
+
+#endif /* _PERG_H_ */

drivers/c2000_eth/pfe/class/vlan_hash.h

diff --git a/drivers/c2000_eth/pfe/class/vlan_hash.h b/drivers/c2000_eth/pfe/class/vlan_hash.h
new file mode 100644
index 0000000..a54ac19
--- /dev/null
+++ b/drivers/c2000_eth/pfe/class/vlan_hash.h
@@ -0,0 +1,28 @@
+#ifndef _VLAN_HASH_H_
+#define _VLAN_HASH_H_
+
+#define VLAN_HASH_REQ1_BASE_ADDR	(VLAN_HASH_BASE_ADDR + 0x000)
+#define VLAN_HASH_REQ2_BASE_ADDR	(VLAN_HASH_BASE_ADDR + 0x020)
+#define VLAN_HASH_REQ3_BASE_ADDR	(VLAN_HASH_BASE_ADDR + 0x040)
+#define VLAN_HASH_REQ4_BASE_ADDR	(VLAN_HASH_BASE_ADDR + 0x060)
+#define VLAN_HASH_REQ5_BASE_ADDR	(VLAN_HASH_BASE_ADDR + 0x080)
+#define VLAN_HASH_REQ6_BASE_ADDR	(VLAN_HASH_BASE_ADDR + 0x0a0)
+#define VLAN_HASH_REQ7_BASE_ADDR	(VLAN_HASH_BASE_ADDR + 0x0c0)
+#define VLAN_HASH_REQ8_BASE_ADDR	(VLAN_HASH_BASE_ADDR + 0x0e0)
+
+#define VLAN_HASH_REQ_CMD(i)		(VLAN_HASH_REQ##i##_BASE_ADDR + 0x000)
+#define VLAN_HASH_REQ_MAC1_ADDR(i)	(VLAN_HASH_REQ##i##_BASE_ADDR + 0x004)
+#define VLAN_HASH_REQ_MAC2_ADDR(i)	(VLAN_HASH_REQ##i##_BASE_ADDR + 0x008)
+#define VLAN_HASH_REQ_MASK1_ADDR(i)	(VLAN_HASH_REQ##i##_BASE_ADDR + 0x00c)
+#define VLAN_HASH_REQ_MASK2_ADDR(i)	(VLAN_HASH_REQ##i##_BASE_ADDR + 0x010)
+#define VLAN_HASH_REQ_ENTRY(i)		(VLAN_HASH_REQ##i##_BASE_ADDR + 0x014)
+#define VLAN_HASH_REQ_STATUS(i)		(VLAN_HASH_REQ##i##_BASE_ADDR + 0x018)
+#define VLAN_HASH_REQ_ENTRY_MAYCH(i)	(VLAN_HASH_REQ##i##_BASE_ADDR + 0x01c)
+
+
+#define VLAN_HASH_FREELIST_PTR_HEAD	(VLAN_HASH_BASE_ADDR + 0x100)
+#define VLAN_HASH_FREELIST_PTR_TAIL	(VLAN_HASH_BASE_ADDR + 0x104)
+#define VLAN_HASH_FREELIST_ENTRIES_ADDR	(VLAN_HASH_BASE_ADDR + 0x108)
+
+#endif /* _VLAN_HASH_H_ */
+

drivers/c2000_eth/pfe/gpt.h

diff --git a/drivers/c2000_eth/pfe/gpt.h b/drivers/c2000_eth/pfe/gpt.h
new file mode 100644
index 0000000..d820277
--- /dev/null
+++ b/drivers/c2000_eth/pfe/gpt.h
@@ -0,0 +1,11 @@
+#ifndef _GPT_H_
+#define _GPT_H_
+
+#define GPT_VERSION		 (GPT_BASE_ADDR + 0x00)
+#define GPT_STATUS		 (GPT_BASE_ADDR + 0x04)
+#define GPT_CONFIG		 (GPT_BASE_ADDR + 0x08)
+#define GPT_COUNTER		 (GPT_BASE_ADDR + 0x0c)
+#define GPT_PERIOD		 (GPT_BASE_ADDR + 0x10)
+#define GPT_WIDTH		 (GPT_BASE_ADDR + 0x14)
+
+#endif /* _GPT_H_ */

drivers/c2000_eth/pfe/pe.h

diff --git a/drivers/c2000_eth/pfe/pe.h b/drivers/c2000_eth/pfe/pe.h
new file mode 100644
index 0000000..a3838f5
--- /dev/null
+++ b/drivers/c2000_eth/pfe/pe.h
@@ -0,0 +1,147 @@
+#ifndef _PE_H_
+#define _PE_H_
+
+#include "hal.h"
+
+#define DDR_BASE_ADDR		0x00020000
+#define DDR_END			0x86000000 /* This includes ACP and IRAM areas */
+#define IRAM_BASE_ADDR		0x83000000
+
+#define IS_DDR(addr, len)	(((unsigned long)(addr) >= DDR_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DDR_END))
+
+typedef struct {
+
+} ddr_rx_hdr_t;
+
+typedef struct {
+
+} lmem_rx_hdr_t;
+
+
+typedef struct {
+
+} tmu_rx_hdr_t;
+
+typedef struct {
+
+} tmu_tx_hdr_t;
+
+typedef struct {
+
+} util_rx_hdr_t;
+
+
+struct pe_sync_mailbox
+{
+	u32 stop;
+	u32 stopped;
+};
+
+struct pe_msg_mailbox
+{
+	u32 dst;
+	u32 src;
+	u32 len;
+	u32 request;
+};
+
+/** Basic busy loop delay function
+*
+* @param cycles		Number of cycles to delay (actual cpu cycles should be close to 3 x cycles)
+*
+*/
+static inline void delay(u32 cycles)
+{
+	volatile int i;
+
+	for (i = 0; i < cycles; i++);
+}
+
+
+/** Read PE id
+*
+* @return	PE id (0 - 5 for CLASS-PE's, 6 - 9 for TMU-PE's, 10 for UTIL-PE)
+*
+*/
+static inline u32 esi_get_mpid(void)
+{
+	u32 mpid;
+
+	asm ("rcsr %0, Configuration, MPID" : "=d" (mpid));
+
+	return mpid;
+}
+
+/** 64bit aligned memory copy using efet.
+* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR.
+* Source, destination addresses and len must all be 64bit aligned.
+* Uses efet synchronous interface to copy the data.
+*
+* @param dst	Destination address to write to (must be 64bit aligned)
+* @param src	Source address to read from (must be 64bit aligned)
+* @param len	Number of bytes to copy (must be 64bit aligned)
+*
+*/
+void efet_memcpy64(void *dst, void *src, unsigned int len);
+
+
+/** Aligned memory copy using efet.
+* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR.
+* Both the source and destination must have the same 64bit alignment, there is no restriction on length.
+*
+* @param dst	Destination address to write to (must have the same 64bit alignment as src)
+* @param src	Source address to read from (must have the same 64bit alignment as dst)
+* @param len	Number of bytes to copy
+*
+*/
+void efet_memcpy(void *dst, void *src, unsigned int len);
+
+
+/** 32bit aligned memory copy.
+* Source and destination addresses must be 32bit aligned, there is no restriction on the length.
+*
+* @param dst		Destination address (must be 32bit aligned)
+* @param src		Source address (must be 32bit aligned)
+* @param len		Number of bytes to copy
+*
+*/
+void memcpy_aligned32(void *dst, void *src, unsigned int len);
+
+/** Aligned memory copy.
+* Source and destination addresses must have the same alignment
+* relative to 32bit boundaries (but otherwsie may have any alignment),
+* there is no restriction on the length.
+*
+* @param dst		Destination address
+* @param src		Source address (must have same 32bit alignment as dst)
+* @param len		Number of bytes to copy
+*
+*/
+void memcpy_aligned(void *dst, void *src, unsigned int len);
+
+
+/** Generic memory set.
+* Implements a generic memory set. Not very optimal (uses byte writes for the entire range)
+*
+*
+* @param dst		Destination address
+* @param val		Value to set memory to
+* @param len		Number of bytes to set
+*
+*/
+void memset(void *dst, u8 val, unsigned int len);
+
+/** Generic memory copy.
+* Implements generic memory copy. If source and destination have the same
+* alignment memcpy_aligned() is used, otherwise, we first align the destination
+* to a 32bit boundary (using byte copies) then the src, and finally use a loop
+* of read, shift, write
+*
+* @param dst		Destination address
+* @param src		Source address
+* @param len		Number of bytes to copy
+*
+*/
+void memcpy(void *dst, void *src, unsigned int len);
+
+#endif /* _PE_H_ */

drivers/c2000_eth/pfe/pfe.h

diff --git a/drivers/c2000_eth/pfe/pfe.h b/drivers/c2000_eth/pfe/pfe.h
new file mode 100644
index 0000000..343fe8c
--- /dev/null
+++ b/drivers/c2000_eth/pfe/pfe.h
@@ -0,0 +1,258 @@
+#ifndef _PFE_H_
+#define _PFE_H_
+
+#define CLASS_DMEM_BASE_ADDR(i)	(0x00000000 | ((i) << 20))
+#define CLASS_IMEM_BASE_ADDR(i)	(0x00000000 | ((i) << 20)) /* Only valid for mem access register interface */
+#define CLASS_DMEM_SIZE		0x00002000
+#define CLASS_IMEM_SIZE		0x00008000
+
+#define TMU_DMEM_BASE_ADDR(i)	(0x00000000 + ((i) << 20))
+#define TMU_IMEM_BASE_ADDR(i)	(0x00000000 + ((i) << 20)) /* Only valid for mem access register interface */
+#define TMU_DMEM_SIZE		0x00000800
+#define TMU_IMEM_SIZE		0x00002000
+
+#define UTIL_DMEM_BASE_ADDR	0x00000000
+#define UTIL_DMEM_SIZE		0x00002000
+
+#define PE_LMEM_BASE_ADDR	0xc3010000
+#define PE_LMEM_SIZE		0x8000
+#define PE_LMEM_END		(PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
+
+#define DMEM_BASE_ADDR		0x00000000
+#define DMEM_SIZE		0x2000		/**< TMU has less... */
+#define DMEM_END		(DMEM_BASE_ADDR + DMEM_SIZE)
+
+#define PMEM_BASE_ADDR		0x00010000
+#define PMEM_SIZE		0x8000		/**< TMU has less... */
+#define PMEM_END		(PMEM_BASE_ADDR + PMEM_SIZE)
+
+
+/* These check memory ranges from PE point of view/memory map */
+#define IS_DMEM(addr, len)	(((unsigned long)(addr) >= DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DMEM_END))
+#define IS_PMEM(addr, len)	(((unsigned long)(addr) >= PMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PMEM_END))
+#define IS_PE_LMEM(addr, len)	(((unsigned long)(addr) >= PE_LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PE_LMEM_END))
+
+#define IS_PFE_LMEM(addr, len)	(((unsigned long)(addr) >= CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && (((unsigned long)(addr) + (len)) <= CBUS_VIRT_TO_PFE(LMEM_END)))
+#define IS_PHYS_DDR(addr, len)	(((unsigned long)(addr) >= DDR_PHYS_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DDR_PHYS_END))
+
+/* If using a run-time virtual address for the cbus base address use this code */
+extern void *cbus_base_addr;
+extern void *ddr_base_addr;
+extern unsigned long ddr_phys_base_addr;
+
+#if 0
+/* If using a run-time virtual address for the cbus base address use this code */
+extern void *cbus_base_addr;
+#define CBUS_BASE_ADDR		cbus_base_addr
+#else
+#define CBUS_BASE_ADDR		0x9c000000
+#endif
+
+#define DDR_PHYS_BASE_ADDR	ddr_phys_base_addr
+#define DDR_BASE_ADDR		ddr_base_addr
+
+#define DDR_SIZE	0xC00000
+#define DDR_PHYS_END	(DDR_PHYS_BASE_ADDR + DDR_SIZE)
+
+#define PFE_CBUS_PHYS_BASE_ADDR	0xc0000000	/**< CBUS physical base address as seen by PE's. */
+
+
+//#define CBUS_PHYS_TO_VIRT(p)	(((p) - CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
+//#define CBUS_VIRT_TO_PHYS(v)	(((v) - CBUS_BASE_ADDR) + CBUS_PHYS_BASE_ADDR)
+
+#define DDR_PHYS_TO_VIRT(p)	(((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR)
+#define DDR_VIRT_TO_PHYS(v)	(((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR)
+
+#define CBUS_VIRT_TO_PFE(v)	(((v) - CBUS_BASE_ADDR) + PFE_CBUS_PHYS_BASE_ADDR)
+#define CBUS_PFE_TO_VIRT(p)	(((p) - PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
+
+#include "cbus.h"
+
+enum {
+	CLASS0_ID = 0,
+	CLASS1_ID,
+	CLASS2_ID,
+	CLASS3_ID,
+#if !defined(CONFIG_PLATFORM_PCI)
+	CLASS4_ID,
+	CLASS5_ID,
+#endif
+#if !defined(CONFIG_TMU_DUMMY)
+	TMU0_ID,
+	TMU1_ID,
+	TMU2_ID,
+	TMU3_ID,
+#else
+	TMU0_ID,
+#endif
+#if !defined(CONFIG_UTIL_PE_DISABLED)
+	UTIL_ID,
+#endif
+	MAX_PE
+};
+
+#if !defined(CONFIG_PLATFORM_PCI)
+#define CLASS_MASK	((1 << CLASS0_ID) | (1 << CLASS1_ID) | (1 << CLASS2_ID) | (1 << CLASS3_ID) | (1 << CLASS4_ID) | (1 << CLASS5_ID))
+#define CLASS_MAX_ID	CLASS5_ID
+#else
+#define CLASS_MASK      ((1 << CLASS0_ID) | (1 << CLASS1_ID) | (1 << CLASS2_ID) | (1 << CLASS3_ID))
+#define CLASS_MAX_ID	CLASS3_ID
+#endif
+
+#if !defined(CONFIG_TMU_DUMMY)
+#define TMU_MASK	((1 << TMU0_ID) | (1 << TMU1_ID) | (1 << TMU2_ID) | (1 << TMU3_ID))
+#define TMU_MAX_ID	TMU3_ID
+#else
+#define TMU_MASK	(1 << TMU0_ID) 
+#define TMU_MAX_ID	TMU0_ID
+#endif
+
+#if !defined(CONFIG_UTIL_PE_DISABLED)
+#define UTIL_MASK	(1 << UTIL_ID)
+#endif
+
+struct pe_sync_mailbox
+{
+	u32 stop;
+	u32 stopped;
+};
+
+struct pe_msg_mailbox
+{
+	u32 dst;
+	u32 src;
+	u32 len;
+	u32 request;
+};
+
+/** PE information.
+ * Structure containing PE's specific information. It is used to create
+ * generic C functions common to all PE's.
+ * Before using the library functions this structure needs to be initialized with the different registers virtual addresses
+ * (according to the ARM MMU mmaping). The default initialization supports a virtual == physical mapping.
+ *
+ */
+struct pe_info
+{
+	u32 dmem_base_addr;		/**< PE's dmem base address */
+	u32 pmem_base_addr;		/**< PE's pmem base address */
+	u32 pmem_size;			/**< PE's pmem size */
+
+	void *mem_access_wdata;		/**< PE's _MEM_ACCESS_WDATA register address */
+	void *mem_access_addr;		/**< PE's _MEM_ACCESS_ADDR register address */
+	void *mem_access_rdata;		/**< PE's _MEM_ACCESS_RDATA register address */
+};
+
+
+void pe_lmem_read(u32 *dst, u32 len, u32 offset);
+void pe_lmem_write(u32 *src, u32 len, u32 offset);
+
+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
+
+u32 pe_pmem_read(int id, u32 addr, u8 size);
+
+void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
+u32 pe_dmem_read(int id, u32 addr, u8 size);
+void class_bus_write(u32 val, u32 addr, u8 size);
+u32 class_bus_read(u32 addr, u8 size);
+void util_bus_write(u32 val, u32 addr, u8 size);
+u32 util_bus_read(u32 addr, u8 size);
+
+#define class_bus_readl(addr)			class_bus_read(addr, 4)
+#define class_bus_readw(addr)			class_bus_read(addr, 2)
+#define class_bus_readb(addr)			class_bus_read(addr, 1)
+
+#define class_bus_writel(val, addr)		class_bus_write(val, addr, 4)
+#define class_bus_writew(val, addr)		class_bus_write(val, addr, 2)
+#define class_bus_writeb(val, addr)		class_bus_write(val, addr, 1)
+
+#define pe_mem_readl(id, addr)			pe_mem_read(id, addr, 4)
+#define pe_mem_readw(id, addr)			pe_mem_read(id, addr, 2)
+#define pe_mem_readb(id, addr)			pe_mem_read(id, addr, 1)
+
+#define pe_mem_writel(id, val, addr)		pe_mem_write(id, val, addr, 4)
+#define pe_mem_writew(id, val, addr)		pe_mem_write(id, val, addr, 2)
+#define pe_mem_writeb(id, val, addr)		pe_mem_write(id, val, addr, 1)
+
+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
+
+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base);
+void bmu_init(void *base, BMU_CFG *cfg);
+void bmu_reset(void *base);
+void bmu_enable(void *base);
+void bmu_disable(void *base);
+void bmu_set_config(void *base, BMU_CFG *cfg);
+
+void gemac_init(void *base, void *config);
+void gemac_set_speed(void *base, MAC_SPEED gem_speed);
+void gemac_set_duplex(void *base, int duplex);
+void gemac_set_mode(void *base, int mode);
+void gemac_enable_mdio(void *base);
+void gemac_disable_mdio(void *base);
+void gemac_set_mdc_div(void *base, MAC_MDC_DIV gem_mdcdiv);
+void gemac_enable(void *base);
+void gemac_disable(void *base);
+void gemac_enable_mdio(void *base);
+void gemac_disable_mdio(void *base);
+void gemac_reset(void *base);
+void gemac_set_address(void *base, SPEC_ADDR *addr);
+SPEC_ADDR gemac_get_address(void *base);
+void gemac_set_laddr1(void *base, MAC_ADDR *address);
+void gemac_set_laddr2(void *base, MAC_ADDR *address);
+void gemac_set_laddr3(void *base, MAC_ADDR *address);
+void gemac_set_laddr4(void *base, MAC_ADDR *address);
+void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index);
+MAC_ADDR gem_get_laddr1(void *base);
+MAC_ADDR gem_get_laddr2(void *base);
+MAC_ADDR gem_get_laddr3(void *base);
+MAC_ADDR gem_get_laddr4(void *base);
+MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index);
+void gemac_set_config(void *base, GEMAC_CFG *cfg);
+void gemac_enable_copy_all(void *base);
+void gemac_disable_copy_all(void *base);
+void gemac_allow_broadcast(void *base);
+void gemac_no_broadcast(void *base);
+void gemac_enable_unicast(void *base);
+void gemac_disable_unicast(void *base);
+void gemac_enable_multicast(void *base);
+void gemac_disable_multicast(void *base);
+void gemac_enable_fcs_rx(void *base);
+void gemac_disable_fcs_rx(void *base);
+void gemac_enable_1536_rx(void *base);
+void gemac_disable_1536_rx(void *base);
+void gemac_enable_pause_rx(void *base);
+void gemac_disable_pause_rx(void *base);
+void gemac_enable_rx_checksum_offload(void *base);
+void gemac_disable_rx_checksum_offload(void *base);
+unsigned int * gemac_get_stats(void *base);
+void gemac_set_bus_width(void *base, int width);
+
+void gpi_init(void *base, GPI_CFG *cfg);
+void gpi_reset(void *base);
+void gpi_enable(void *base);
+void gpi_disable(void *base);
+void gpi_set_config(void *base, GPI_CFG *cfg);
+
+void class_init(CLASS_CFG *cfg);
+void class_reset(void);
+void class_enable(void);
+void class_disable(void);
+void class_set_config(CLASS_CFG *cfg);
+
+void tmu_init(TMU_CFG *cfg);
+void tmu_enable(u32 pe_mask);
+void tmu_disable(u32 pe_mask);
+
+void util_init(UTIL_CFG *cfg);
+void util_reset(void);
+void util_enable(void);
+void util_disable(void);
+
+void hif_init(void);
+void hif_tx_enable(void);
+void hif_tx_disable(void);
+void hif_rx_enable(void);
+void hif_rx_disable(void);
+
+#endif /* _PFE_H_ */

drivers/c2000_eth/pfe/tmu.h

diff --git a/drivers/c2000_eth/pfe/tmu.h b/drivers/c2000_eth/pfe/tmu.h
new file mode 100644
index 0000000..12eaf12
--- /dev/null
+++ b/drivers/c2000_eth/pfe/tmu.h
@@ -0,0 +1,48 @@
+#ifndef _TMU_H_
+#define _TMU_H_
+
+#define TMU_DMEM_BASE_ADDR	0x00000000
+#define TMU_PMEM_BASE_ADDR	0x00010000
+
+
+#define CBUS_BASE_ADDR		0xc0000000
+#define TMU_APB_BASE_ADDR	0xc1000000
+
+#include "cbus.h"
+
+#define GPT_BASE_ADDR		(TMU_APB_BASE_ADDR + 0x00000)
+#define UART_BASE_ADDR		(TMU_APB_BASE_ADDR + 0x10000)
+
+
+#define SHAPER0_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x020000)
+#define SHAPER1_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x030000)
+#define SHAPER2_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x040000)
+#define SHAPER3_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x050000)
+#define SHAPER4_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x060000)
+#define SHAPER5_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x070000)
+#define SHAPER6_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x080000)
+#define SHAPER7_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x090000)
+#define SHAPER8_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x0a0000)
+#define SHAPER9_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x0b0000)
+
+#define SCHED0_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x1c0000)
+#define SCHED1_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x1d0000)
+#define SCHED2_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x1e0000)
+#define SCHED3_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x1f0000)
+#define SCHED4_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x200000)
+#define SCHED5_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x210000)
+#define SCHED6_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x220000)
+#define SCHED7_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x230000)
+
+
+#define PHY_QUEUE_BASE_ADDR	(TMU_APB_BASE_ADDR + 0x260000)
+#define SHAPER_STATUS		(TMU_APB_BASE_ADDR + 0x270000) /**< [9:0] bitmask of shapers that have positive credit */
+
+
+#include "gpt.h"
+#include "uart.h"
+#include "tmu/shaper.h"
+#include "tmu/sched.h"
+#include "tmu/phy_queue.h"
+
+#endif /* _TMU_H_ */

drivers/c2000_eth/pfe/tmu/phy_queue.h

diff --git a/drivers/c2000_eth/pfe/tmu/phy_queue.h b/drivers/c2000_eth/pfe/tmu/phy_queue.h
new file mode 100644
index 0000000..9eef9a9
--- /dev/null
+++ b/drivers/c2000_eth/pfe/tmu/phy_queue.h
@@ -0,0 +1,31 @@
+#ifndef _PHY_QUEUE_H_
+#define _PHY_QUEUE_H_
+
+#define PHY_QUEUE_SHAPER_STATUS	(PHY_QUEUE_BASE_ADDR + 0x00)	/**< [28:19] same as SHAPER_STATUS, [18:3] same as QUEUE_STATUS, [2:0] must be zero before a new packet may be dequeued */
+#define QUEUE_STATUS		(PHY_QUEUE_BASE_ADDR + 0x04)	/**< [15:0] bit mask of input queues with pending packets */
+
+#define QUEUE0_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x08)
+#define QUEUE1_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x0c)
+#define QUEUE2_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x10)
+#define QUEUE3_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x14)
+#define QUEUE4_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x18)
+#define QUEUE5_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x1c)
+#define QUEUE6_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x20)
+#define QUEUE7_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x24)
+#define QUEUE8_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x28)
+#define QUEUE9_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x2c)
+#define QUEUE10_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x30)
+#define QUEUE11_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x34)
+#define QUEUE12_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x38)
+#define QUEUE13_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x3c)
+#define QUEUE14_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x40)
+#define QUEUE15_PKT_LEN		(PHY_QUEUE_BASE_ADDR + 0x44)
+#define QUEUE_RESULT0		(PHY_QUEUE_BASE_ADDR + 0x48)	/**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY3), [6:0] winner input queue number */
+#define QUEUE_RESULT1		(PHY_QUEUE_BASE_ADDR + 0x4c)	/**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY4), [6:0] winner input queue number */
+#define QUEUE_RESULT2		(PHY_QUEUE_BASE_ADDR + 0x50)	/**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY5), [6:0] winner input queue number */
+#define QUEUE_GBL_PKTLEN	(PHY_QUEUE_BASE_ADDR + 0x5c)
+#define QUEUE_GBL_PKTLEN_MASK	(PHY_QUEUE_BASE_ADDR + 0x60)
+
+
+
+#endif /* _PHY_QUEUE_H_ */

drivers/c2000_eth/pfe/tmu/sched.h

diff --git a/drivers/c2000_eth/pfe/tmu/sched.h b/drivers/c2000_eth/pfe/tmu/sched.h
new file mode 100644
index 0000000..0c741cc
--- /dev/null
+++ b/drivers/c2000_eth/pfe/tmu/sched.h
@@ -0,0 +1,47 @@
+#ifndef _SCHED_H_
+#define _SCHED_H_
+
+/* Offsets from SCHEDx_BASE_ADDR */
+#define SCHED_CTRL			0x00
+#define SCHED_SLOT_TIME			0x04
+#define SCHED_RES			0x08
+#define SCHED_QUEUE_ALLOC0		0x0c
+#define SCHED_QUEUE_ALLOC1		0x10
+#define SCHED_BW			0x14
+#define SCHED_GUR_DEF_CTR		0x18
+#define SCHED_AVL_CTR			0x1c
+#define SCHED_QU0_WGHT			0x20
+#define SCHED_QU1_WGHT			0x24
+#define SCHED_QU2_WGHT			0x28
+#define SCHED_QU3_WGHT			0x2c
+#define SCHED_QU4_WGHT			0x30
+#define SCHED_QU5_WGHT			0x34
+#define SCHED_QU6_WGHT			0x38
+#define SCHED_QU7_WGHT			0x3c
+#define SCHED_QUE0_DEFICIT_CNT		0x40
+#define SCHED_QUE1_DEFICIT_CNT		0x44
+#define SCHED_QUE2_DEFICIT_CNT		0x48
+#define SCHED_QUE3_DEFICIT_CNT		0x4c
+#define SCHED_QUE4_DEFICIT_CNT		0x50
+#define SCHED_QUE5_DEFICIT_CNT		0x54
+#define SCHED_QUE6_DEFICIT_CNT		0x58
+#define SCHED_QUE7_DEFICIT_CNT		0x5c
+#define SCHED_PKT_LEN			0x60
+
+#define SCHED_CTRL_ALGOTYPE(x) 		(((x) & 0xf) << 0)
+#define SCHED_CTRL_CALQUOTA(x) 		(((x) & 0x1) << 4)
+#define SCHED_CTRL_ACTIVE_Q(x) 		(((x) & 0xff) << 8)
+#define SCHED_CTRL_SHARE_BW(x) 		(((x) & 0xff) << 16)
+#define SCHED_CTRL_BARROW_BW(x) 	(((x) & 0xff) << 24)
+
+#define SCHED_QUEUE_ALLOC0_QUEUEA(x)	(((x) & 0x1f) << 0)
+#define SCHED_QUEUE_ALLOC0_QUEUEB(x)	(((x) & 0x1f) << 8)
+#define SCHED_QUEUE_ALLOC0_QUEUEC(x)	(((x) & 0x1f) << 16)
+#define SCHED_QUEUE_ALLOC0_QUEUED(x)	(((x) & 0x1f) << 24)
+
+#define SCHED_QUEUE_ALLOC0_RES0(x)	(((x) & 0x7) << 5)
+#define SCHED_QUEUE_ALLOC0_RES1(x)	(((x) & 0x7) << 13)
+#define SCHED_QUEUE_ALLOC0_RES2(x)	(((x) & 0x7) << 21)
+#define SCHED_QUEUE_ALLOC0_RES3(x)	(((x) & 0x7) << 29)
+
+#endif /* _SCHED_H_ */

drivers/c2000_eth/pfe/tmu/shaper.h

diff --git a/drivers/c2000_eth/pfe/tmu/shaper.h b/drivers/c2000_eth/pfe/tmu/shaper.h
new file mode 100644
index 0000000..76315f3
--- /dev/null
+++ b/drivers/c2000_eth/pfe/tmu/shaper.h
@@ -0,0 +1,19 @@
+#ifndef _SHAPER_H_
+#define _SHAPER_H_
+
+/* Offsets from SHAPPERx_BASE_ADDR */
+#define SHAPER_CTRL		0x00
+#define SHAPER_WEIGHT		0x04
+#define SHAPER_PKT_LEN		0x08
+
+#define SHAPER_CTRL_ENABLE(x) 	(((x) & 0x1) << 0)
+#define SHAPER_CTRL_QNO(x) 	(((x) & 0x3f) << 1)
+#define SHAPER_CTRL_CLKDIV(x) 	(((x) & 0xffff) << 16)
+
+#define SHAPER_WEIGHT_FRACWT(x) 	(((x) & 0xff) << 0)
+#define SHAPER_WEIGHT_INTWT(x) 		(((x) & 0x3) << 8)
+#define SHAPER_WEIGHT_MAXCREDIT(x) 	(((x) & 0x3fffff) << 10)
+
+#define PORT_SHAPER_MASK (1 << 0)
+
+#endif /* _SHAPER_H_ */

drivers/c2000_eth/pfe/uart.h

diff --git a/drivers/c2000_eth/pfe/uart.h b/drivers/c2000_eth/pfe/uart.h
new file mode 100644
index 0000000..483d446
--- /dev/null
+++ b/drivers/c2000_eth/pfe/uart.h
@@ -0,0 +1,13 @@
+#ifndef _UART_H_
+#define _UART_H_
+
+#define UART_THR	(UART_BASE_ADDR + 0x00)
+#define UART_IER	(UART_BASE_ADDR + 0x04)
+#define UART_IIR	(UART_BASE_ADDR + 0x08)
+#define UART_LCR	(UART_BASE_ADDR + 0x0c)
+#define UART_MCR	(UART_BASE_ADDR + 0x10)
+#define UART_LSR	(UART_BASE_ADDR + 0x14)
+#define UART_MDR	(UART_BASE_ADDR + 0x18)
+#define UART_SCRATCH	(UART_BASE_ADDR + 0x1c)
+
+#endif /* _UART_H_ */

drivers/c2000_eth/pfe/util.h

diff --git a/drivers/c2000_eth/pfe/util.h b/drivers/c2000_eth/pfe/util.h
new file mode 100644
index 0000000..fb2417c
--- /dev/null
+++ b/drivers/c2000_eth/pfe/util.h
@@ -0,0 +1,30 @@
+#ifndef _UTIL_H_
+#define _UTIL_H_
+
+#define UTIL_DMEM_BASE_ADDR	0x00000000
+#define UTIL_DMEM_SIZE		0x00002000
+#define UTIL_DMEM_END		(UTIL_DMEM_BASE_ADDR + UTIL_DMEM_SIZE)
+
+#define IS_DMEM(addr, len)	(((unsigned long)(addr) >= UTIL_DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= UTIL_DMEM_END))
+
+#define CBUS_BASE_ADDR		0xc0000000
+#define UTIL_APB_BASE_ADDR	0xc1000000
+
+#include "cbus.h"
+
+#define GPT_BASE_ADDR		(UTIL_APB_BASE_ADDR + 0x00000)
+#define UART_BASE_ADDR		(UTIL_APB_BASE_ADDR + 0x10000)
+#define EAPE_BASE_ADDR		(UTIL_APB_BASE_ADDR + 0x20000)
+#define INQ_BASE_ADDR		(UTIL_APB_BASE_ADDR + 0x30000)
+#define EFET1_BASE_ADDR		(UTIL_APB_BASE_ADDR + 0x40000)
+#define EFET2_BASE_ADDR		(UTIL_APB_BASE_ADDR + 0x50000)
+#define EFET3_BASE_ADDR		(UTIL_APB_BASE_ADDR + 0x60000)
+
+
+#include "gpt.h"
+#include "uart.h"
+#include "util/eape.h"
+#include "util/inq.h"
+#include "util/efet.h"
+
+#endif /* _UTIL_H_ */

drivers/c2000_eth/pfe/util/eape.h

diff --git a/drivers/c2000_eth/pfe/util/eape.h b/drivers/c2000_eth/pfe/util/eape.h
new file mode 100644
index 0000000..07344dc
--- /dev/null
+++ b/drivers/c2000_eth/pfe/util/eape.h
@@ -0,0 +1,10 @@
+#ifndef _EAPE_H_
+#define _EAPE_H_
+
+#define EAPE_STATUS		(EAPE_BASE_ADDR + 0x0)
+#define EAPE_INT_ENABLE		(EAPE_BASE_ADDR + 0x4)
+#define EAPE_INT_SRC		(EAPE_BASE_ADDR + 0x8)
+#define EAPE_HOST_INT_ENABLE	(EAPE_BASE_ADDR + 0xc)
+
+
+#endif /* _EAPE_H_ */

drivers/c2000_eth/pfe/util/efet.h

diff --git a/drivers/c2000_eth/pfe/util/efet.h b/drivers/c2000_eth/pfe/util/efet.h
new file mode 100644
index 0000000..12d0310
--- /dev/null
+++ b/drivers/c2000_eth/pfe/util/efet.h
@@ -0,0 +1,20 @@
+#ifndef _UTIL_EFET_H_
+#define _UTIL_EFET_H_
+
+#define EFET_ENTRY_ADDR		0x00
+#define EFET_ENTRY_SIZE		0x04
+#define EFET_ENTRY_DMEM_ADDR	0x08
+#define EFET_ENTRY_STATUS	0x0c
+#define EFET_ENTRY_ENDIAN	0x10
+
+#define CBUS2DMEM	0
+#define DMEM2CBUS	1
+
+#define EFET2BUS_LE     (1 << 0)
+
+void util_efet(int i, u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir);
+void util_efet_wait(int i);
+void util_efet_sync(int i, u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir);
+
+#endif /* _UTIL_EFET_H_ */
+

drivers/c2000_eth/pfe/util/inq.h

diff --git a/drivers/c2000_eth/pfe/util/inq.h b/drivers/c2000_eth/pfe/util/inq.h
new file mode 100644
index 0000000..73d1acb
--- /dev/null
+++ b/drivers/c2000_eth/pfe/util/inq.h
@@ -0,0 +1,10 @@
+#ifndef _INQ_H_
+#define _INQ_H_
+
+#define INQ_HOST_GP	(INQ_BASE_ADDR + 0x00) /* FIXME what are these for ? */
+#define INQ_UPE_GP	(INQ_BASE_ADDR + 0x04) /* FIXME what are these for ? */
+
+#define INQ_QB_PKTPTR	(INQ_BASE_ADDR + 0x08)
+#define INQ_FIFO_CNT	(INQ_BASE_ADDR + 0x0c)
+
+#endif /* _INQ_H_ */

drivers/c2000_eth/pfe_driver.c

diff --git a/drivers/c2000_eth/pfe_driver.c b/drivers/c2000_eth/pfe_driver.c
new file mode 100644
index 0000000..7c65e94
--- /dev/null
+++ b/drivers/c2000_eth/pfe_driver.c
@@ -0,0 +1,687 @@
+/*
+ *  (C) Copyright 2011
+ *  Author : Mindspeed Technologes
+ *
+ *  See file CREDITS for list of people who contributed to this
+ *  project.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License as
+ *  published by the Free Software Foundation; either version 2 of
+ *  the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ *  MA 02111-1307 USA
+ * */
+
+
+#include "hal.h"
+#include "pfe/pfe.h"
+#include "pfe_driver.h"
+#include "pfe_firmware.h"
+
+
+static struct tx_desc_s *g_tx_desc = NULL;
+static struct rx_desc_s *g_rx_desc = NULL;
+
+
+/** HIF Rx interface function
+ * Reads the rx descriptor from the current location (rxToRead).
+ * - If the descriptor has a valid data/pkt, then get the data pointer
+ * - check for the input rx phy number
+ * - increments the rx data pointer by pkt_head_room_size
+ * - decrements the data length by pkt_head_room_size
+ * - handover the packet to caller.
+ *
+ * @param[out]	pkt_ptr	Pointer to store rx packet pointer
+ * @param[out] phy_port Pointer to store recv phy port
+ *
+ * @return	-1 if no packet, else returns length of packet.
+ */
+int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
+{
+	struct rx_desc_s *rx_desc = g_rx_desc;
+	struct bufDesc *bd;
+	int len = -1;
+	volatile u32 ctrl;
+	struct hif_header_s *hif_header;
+
+	bd = rx_desc->rxBase + rx_desc->rxToRead;
+
+	if (bd->ctrl & BD_CTRL_DESC_EN)
+		return len; //No pending Rx packet
+
+	/* this len include hif_header(8bytes) */
+	len = bd->ctrl & 0xFFFF;
+
+	hif_header = (struct hif_header_s *)DDR_PHYS_TO_VIRT(bd->data);
+
+
+	/* Get the recive port info from the packet */
+	dprint("Pkt recv'd: Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
+				hif_header, len, hif_header->port_no, bd->status);
+
+#if 0
+	{
+		int i;
+		unsigned char *p = (unsigned char *)hif_header;
+		for(i=0; i < len; i++) {
+			if(!(i % 16))
+				printf("\n");
+			printf(" %02x", p[i]);
+		}
+		printf("\n");
+	}
+#endif
+
+	*pkt_ptr = (unsigned int )(hif_header + 1);
+	*phy_port = hif_header->port_no;
+	len -= sizeof(struct hif_header_s);
+
+	/* reset bd control field */
+	ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR);
+	bd->ctrl = ctrl;
+	bd->status = 0;
+
+	rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
+
+	/* Give START_STROBE to BDP to fetch the descriptor __NOW__,
+	 * BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
+	 * In idle state (ie., no rx pkt), BDP will not fetch
+	 * the descriptor even if strobe is given(I think) */
+	writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+
+	return len;
+}
+
+
+/** HIF Tx interface function
+ * This function sends a single packet to PFE from HIF interface.
+ * - No interrupt indication on tx completion.
+ * - After tx descriptor is updated and TX DMA is enabled.
+ * - To support both chipit and read c2k environment, data is copied to
+ *   tx buffers. After verification this copied can be avoided.
+ *
+ * @param[in] phy_port	Phy port number to send out this packet
+ * @param[in] data	Pointer to the data
+ * @param[in] length	Length of the ethernet packet to be transfered.
+ *
+ * @return -1 if tx Q is full, else returns the tx location where the pkt is placed.
+ */
+int pfe_send(int phy_port, void *data, int length)
+{
+	struct tx_desc_s *tx_desc = g_tx_desc;
+	struct bufDesc *bd;
+	struct hif_header_s hif_header;
+	u8 *tx_buf_va;
+	volatile u32 ctrl_word;
+
+	dprint("%s:pkt: %p, len: %d, txBase: %p, txToSend: %d\n", __func__,
+			data, length, tx_desc->txBase, tx_desc->txToSend);
+
+	bd = tx_desc->txBase + tx_desc->txToSend;
+
+	/* check queue-full condition */
+	if (bd->ctrl & BD_CTRL_DESC_EN) {
+		printf("Tx queue full\n");
+		return -1;
+	}
+
+	/* PFE checks for min pkt size */
+	if (length < MIN_PKT_SIZE) {
+		length = MIN_PKT_SIZE;
+	}
+
+	tx_buf_va = (u8 *)DDR_PHYS_TO_VIRT(bd->data);
+	dprint("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va, bd->data);
+
+	/* Fill the gemac/phy port number to send this packet out */
+	memset(&hif_header, 0 ,  sizeof(struct hif_header_s));
+	hif_header.port_no = phy_port;
+
+	memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s));
+	memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length);
+	length += sizeof(struct hif_header_s);
+
+#if 0
+	{
+		int i;
+		unsigned char *p = (unsigned char *)tx_buf_va;
+		for(i=0; i < length; i++) {
+			if (!(i % 16)) printf("\n");
+			printf("%02x ", p[i]);
+		}
+	}
+#endif
+
+	dprint("before0: Tx Done, status: %08x, ctrl: %08x\n", bd->status, bd->ctrl);
+
+	/* fill the tx desc */
+	ctrl_word = (u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF));
+	bd->ctrl = ctrl_word;
+	bd->status = 0;
+
+	/* NOTE: This code can be removed after verification */
+#if 1 //SRAM_RETENTION_BUG
+	ctrl_word = 0;
+	bd->status = 0xF0;
+	ctrl_word = bd->ctrl;
+	//printf("0: contrl word: %08x\n", ctrl_word);
+#endif
+
+	/* Indicate Tx DMA to start fetching the Tx Descriptor,
+    	 * set START_STOBE */
+	//writel((readl(HIF_TX_CTRL) | HIF_TX_BDP_CH_START_WSTB), HIF_TX_CTRL);
+	//writel((readl(HIF_TX_CTRL) | (HIF_TX_DMA_EN | HIF_TX_BDP_CH_START_WSTB)), HIF_TX_CTRL);
+	writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
+
+	udelay(100);
+
+	return tx_desc->txToSend;
+}
+
+/** HIF to check the Tx done
+ *  This function will chceck the tx done indication of the current txToSend locations
+ *  if success, moves the txToSend to next location.
+ *
+ * @return -1 if TX ownership bit is not cleared by hw.
+			  else on success (tx done copletion) returns zero.
+ */
+int pfe_tx_done(void)
+{
+	struct tx_desc_s *tx_desc = g_tx_desc;
+	struct bufDesc *bd;
+	volatile u32 ctrl_word;
+
+	dprint("%s:txBase: %p, txToSend: %d\n", __func__, tx_desc->txBase, tx_desc->txToSend);
+
+	bd = tx_desc->txBase + tx_desc->txToSend;
+
+	/* check queue-full condition */
+	ctrl_word = bd->ctrl;
+	if (ctrl_word & BD_CTRL_DESC_EN)
+		return -1;
+
+	/* reset the control field */
+	bd->ctrl = 0;
+	//bd->data = (u32)NULL;
+	bd->status = 0;
+
+	dprint("Tx Done : status: %08x, ctrl: %08x\n", bd->status, bd->ctrl);
+
+	/* increment the txtosend index to next location */
+	tx_desc->txToSend = (tx_desc->txToSend + 1) & (tx_desc->txRingSize - 1);
+
+	dprint("Tx next pkt location: %d\n", tx_desc->txToSend);
+
+	return 0;
+}
+
+/** GEMAC initialization
+ * Initializes the GEMAC registers.
+ *
+ * @param[in] gemac_base   Pointer to GEMAC reg base
+ * @param[in] mode GEMAC mode to configure (MII config)
+ * @param[in] speed GEMAC speed
+ * @param[in] duplex
+ */
+void pfe_gemac_init(void *gemac_base, u32 mode, u32 speed, u32 duplex)
+{
+	GEMAC_CFG gemac_cfg  = {
+		.mode = mode,
+		.speed = speed,
+		.duplex = duplex,
+	};
+
+	dprint("%s: gemac_base=%p\n", __func__, gemac_base);
+
+	gemac_init(gemac_base, &gemac_cfg);
+
+	//gemac_set_loop(gemac_base, LB_NONE);
+	//gemac_disable_copy_all(gemac_base);
+	//gemac_disable_rx_checksum_offload(gemac_base);
+
+	gemac_allow_broadcast(gemac_base);
+	gemac_disable_unicast(gemac_base); /* unicast hash disabled  */
+	gemac_disable_multicast(gemac_base); /* multicast hash disabled */
+	gemac_disable_fcs_rx(gemac_base);
+	gemac_disable_1536_rx(gemac_base);
+	gemac_enable_pause_rx(gemac_base);
+	gemac_enable_rx_checksum_offload(gemac_base);
+}
+
+/** Helper function to dump Rx descriptors.
+ */
+void hif_rx_desc_dump(void)
+{
+	struct bufDesc *bd_va;
+	int i;
+	struct rx_desc_s *rx_desc;
+
+	if (g_rx_desc == NULL) {
+		printf("%s: HIF Rx desc no init \n", __func__);
+		return;
+	}
+
+	rx_desc = g_rx_desc;
+	bd_va = rx_desc->rxBase;
+
+	printf("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rxBase, rx_desc->rxBase_pa);
+	for (i=0; i < rx_desc->rxRingSize; i++) {
+//		printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
+//			bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
+		bd_va++;
+	}
+}
+
+/** HIF Rx Desc initialization function.
+ */
+static int hif_rx_desc_init(struct pfe *pfe)
+{
+	u32 ctrl;
+	struct bufDesc *bd_va;
+	struct bufDesc *bd_pa;
+	struct rx_desc_s *rx_desc;
+	u32 rx_buf_va;
+	u32 rx_buf_pa;
+	int i;
+
+	/* sanity check */
+	if (g_rx_desc) {
+		printf("%s: HIF Rx desc re-init request\n", __func__);
+		return 0;
+	}
+
+	rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s));
+	if (rx_desc == NULL) {
+		printf("%s:%d:Memory allocation failure\n", __func__, __LINE__);
+		return -1;
+	}
+	memset(rx_desc, 0 , sizeof(struct rx_desc_s));
+
+	/* init: Rx ring buffer */
+	rx_desc->rxRingSize = HIF_RX_DESC_NT;
+
+	/* NOTE: must be 64bit aligned  */
+	bd_va = (struct bufDesc *)(pfe->ddr_baseaddr + RX_BD_BASEADDR);
+	bd_pa = (struct bufDesc *)(pfe->ddr_phys_baseaddr + RX_BD_BASEADDR);
+
+	rx_desc->rxBase = bd_va;
+	rx_desc->rxBase_pa = (unsigned long)bd_pa;
+
+	rx_buf_va = (u32)(pfe->ddr_baseaddr + HIF_RX_PKT_DDR_BASEADDR);
+	rx_buf_pa = pfe->ddr_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR;
+
+
+	dprint("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n",
+		__func__, rx_desc->rxBase, rx_desc->rxBase_pa, rx_desc->rxRingSize);
+
+	memset(bd_va, 0, sizeof(struct bufDesc) * rx_desc->rxRingSize);
+
+	ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
+	for (i=0; i < rx_desc->rxRingSize; i++) {
+		bd_va->next = bd_pa + 1;
+		bd_va->ctrl = ctrl;
+		bd_va->data = rx_buf_pa + (i * MAX_FRAME_SIZE);
+//		printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
+//			bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
+		bd_va++;
+		bd_pa++;
+	}
+	--bd_va;
+	bd_va->next = (struct bufDesc *)rx_desc->rxBase_pa;
+
+	/* !!! This is a redundent information for h/w as we are also
+		maintaining next address in the buffer descriptor
+		Posedge: reference code does not using this bit to go back to base address */
+	//bd->ctrl |= BD_CTRL_LAST_BD;
+
+	writel(rx_desc->rxBase_pa, HIF_RX_BDP_ADDR);
+	writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+
+	g_rx_desc = rx_desc;
+
+	return 0;
+}
+
+/** Helper function to dump Tx Descriptors.
+ */
+void hif_tx_desc_dump(void)
+{
+	struct tx_desc_s *tx_desc;
+	int i;
+	struct bufDesc *bd_va;
+
+	if (g_tx_desc == NULL) {
+		printf("%s: HIF Tx desc no init \n", __func__);
+		return;
+	}
+
+	tx_desc = g_tx_desc;
+	bd_va = tx_desc->txBase;
+
+	printf("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->txBase, tx_desc->txBase_pa);
+	for (i=0; i < tx_desc->txRingSize; i++) {
+//		printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
+//			bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
+		bd_va++;
+	}
+}
+
+/** HIF Tx descriptor initialization function.
+ */
+static int hif_tx_desc_init(struct pfe *pfe)
+{
+	struct bufDesc *bd_va;
+	struct bufDesc *bd_pa;
+	int i;
+	struct tx_desc_s *tx_desc;
+	u32 tx_buf_pa;
+
+	/* sanity check */
+	if (g_tx_desc) {
+		printf("%s: HIF Tx desc re-init request\n", __func__);
+		return 0;
+	}
+
+	tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s));
+	if (tx_desc == NULL) {
+		printf("%s:%d:Memory allocation failure\n", __func__, __LINE__);
+		return -1;
+	}
+	memset(tx_desc, 0 , sizeof(struct tx_desc_s));
+
+	/* init: Tx ring buffer */
+	tx_desc->txRingSize = HIF_TX_DESC_NT;
+	/* NOTE: must be 64bit aligned  */
+	bd_va = (struct bufDesc *)(pfe->ddr_baseaddr + TX_BD_BASEADDR);
+	bd_pa = (struct bufDesc *)(pfe->ddr_phys_baseaddr + TX_BD_BASEADDR);
+
+	tx_desc->txBase_pa = (unsigned long)bd_pa;
+	tx_desc->txBase = bd_va;
+
+	dprint("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n",
+			__func__, tx_desc->txBase, tx_desc->txBase_pa, tx_desc->txRingSize);
+
+	memset(bd_va, 0, sizeof(struct bufDesc) * tx_desc->txRingSize);
+
+	tx_buf_pa = pfe->ddr_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
+
+	for (i=0; i < tx_desc->txRingSize; i++) {
+		bd_va->next = bd_pa + 1;
+		bd_va->data = tx_buf_pa + (i * MAX_FRAME_SIZE);
+//		printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
+//			bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
+		bd_va++;
+		bd_pa++;
+	}
+	--bd_va;
+	bd_va->next = (struct bufDesc *)tx_desc->txBase_pa;
+//	printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
+//		bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
+
+	/* !!! This is a redundent information for h/w as we are also
+		maintaining next address in the buffer descriptor,
+		Posedge: reference code does not using LAST_BD for moving back to base address */
+	//bd->ctrl |= BD_CTRL_LAST_BD;
+
+	writel(tx_desc->txBase_pa, HIF_TX_BDP_ADDR);
+
+	g_tx_desc = tx_desc;
+
+	return 0;
+}
+
+/** PFE/Class initialization.
+ */
+static void pfe_class_init(struct pfe *pfe)
+{
+	CLASS_CFG class_cfg = {
+		.route_table_baseaddr = pfe->ddr_phys_baseaddr + ROUTE_TABLE_BASEADDR,
+		.route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
+	};
+
+	class_init(&class_cfg);
+	printf("class init complete\n");
+}
+
+/** PFE/TMU initialization.
+ */
+static void pfe_tmu_init(struct pfe *pfe)
+{
+	TMU_CFG tmu_cfg = {
+		.llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR,
+		.llm_queue_len = TMU_LLM_QUEUE_LEN,
+	};
+
+	tmu_init(&tmu_cfg);
+	printf("tmu init complete\n");
+}
+
+/** PFE/BMU (both BMU1 & BMU2) initialization.
+ */
+static void pfe_bmu_init(struct pfe *pfe)
+{
+	BMU_CFG bmu1_cfg = {
+		.baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR + BMU1_LMEM_BASEADDR),
+		.count = BMU1_BUF_COUNT,
+		.size = BMU1_BUF_SIZE,
+	};
+
+	BMU_CFG bmu2_cfg = {
+		.baseaddr = pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR,
+		.count = BMU2_BUF_COUNT,
+		.size = BMU2_BUF_SIZE,
+	};
+
+	bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
+	printf("bmu1 init: done\n");
+
+	bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
+	printf("bmu2 init: done\n");
+}
+
+#if !defined(CONFIG_UTIL_PE_DISABLED)
+/** PFE/Util initialization function.
+ */
+static void pfe_util_init(struct pfe *pfe)
+{
+	UTIL_CFG util_cfg = { };
+
+	util_init(&util_cfg);
+	printf("util init complete\n");
+}
+#endif
+
+/** PFE/GPI initialization function.
+ *  - egpi1, egpi2, egpi3, hgpi
+ */
+static void pfe_gpi_init(struct pfe *pfe)
+{
+	GPI_CFG egpi1_cfg = {
+		.lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
+		.tmlf_txthres = EGPI1_TMLF_TXTHRES,
+		.aseq_len = EGPI1_ASEQ_LEN,
+	};
+
+	GPI_CFG egpi2_cfg = {
+		.lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
+		.tmlf_txthres = EGPI2_TMLF_TXTHRES,
+		.aseq_len = EGPI2_ASEQ_LEN,
+	};
+
+#if 0
+	GPI_CFG egpi3_cfg = {
+		.lmem_rtry_cnt = EGPI3_LMEM_RTRY_CNT,
+		.tmlf_txthres = EGPI3_TMLF_TXTHRES,
+		.aseq_len = EGPI3_ASEQ_LEN,
+	};
+#endif
+
+	GPI_CFG hgpi_cfg = {
+		.lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
+		.tmlf_txthres = HGPI_TMLF_TXTHRES,
+		.aseq_len = HGPI_ASEQ_LEN,
+	};
+
+	gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
+	printf("GPI1 init complete\n");
+
+   gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
+	printf("GPI2 init complete\n");
+
+#if 0
+   gpi_init(EGPI3_BASE_ADDR, &egpi3_cfg);
+#endif
+
+   gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
+	printf("HGPI init complete\n");
+}
+
+/** Helper function for PCI init sequence.
+ */
+void pfe_gem_enable_all(void)
+{
+	gpi_enable(EGPI1_BASE_ADDR);
+	gemac_enable(EMAC1_BASE_ADDR);
+
+	gpi_enable(EGPI2_BASE_ADDR);
+	gemac_enable(EMAC2_BASE_ADDR);
+
+#if 0
+	gpi_enable(EGPI3_BASE_ADDR);
+	gemac_enable(EMAC3_BASE_ADDR);
+#endif
+}
+
+/** PFE/HIF initialization function.
+ */
+static void pfe_hif_init(struct pfe *pfe)
+{
+	hif_tx_disable();
+	hif_rx_disable();
+
+	hif_tx_desc_init(pfe);
+	hif_rx_desc_init(pfe);
+
+	hif_init();
+
+	hif_tx_enable();
+	hif_rx_enable();
+
+	hif_rx_desc_dump();
+	hif_tx_desc_dump();
+
+	printf("HIF init complete\n");
+}
+
+/** PFE initialization
+ * - Firmware loading (CLASS-PE and TMU-PE)
+ * - BMU1 and BMU2 init
+ * - GEMAC init
+ * - GPI init
+ * - CLASS-PE init
+ * - TMU-PE init
+ * - HIF tx and rx descriptors init
+ *
+ * @param[in]	edev	Pointer to eth device structure.
+ *
+ * @return 0, on success.
+ */
+static int pfe_hw_init(struct pfe *pfe)
+{
+
+	dprint("%s: start \n", __func__);
+
+	pfe_class_init(pfe);
+
+	pfe_tmu_init(pfe);
+
+	pfe_bmu_init(pfe);
+
+#if !defined(CONFIG_UTIL_PE_DISABLED)
+	pfe_util_init(pfe);
+#endif
+
+	pfe_gpi_init(pfe);
+
+	pfe_hif_init(pfe);
+
+	bmu_enable(BMU1_BASE_ADDR);
+	printf("bmu1 enabled\n");
+
+	bmu_enable(BMU2_BASE_ADDR);
+	printf("bmu2 enabled\n");
+
+	printf("%s: done\n", __func__);
+
+	/* NOTE: Load PE specific data (if any) */
+
+	return 0;
+}
+
+
+/** PFE probe function.
+ * - Initializes pfe_lib
+ * - pfe hw init
+ * - fw loading and enables PEs
+ * - should be executed once.
+ *
+ * @param[in] pfe  Pointer the pfe control block
+ */
+int pfe_probe(struct pfe *pfe)
+{
+	static int init_done = 0;
+
+	if (init_done)
+		return 0;
+
+	printf("cbus_baseaddr: %p, ddr_baseaddr: %p, ddr_phys_baseaddr: %08x\n",
+	             pfe->cbus_baseaddr, pfe->ddr_baseaddr, (u32)pfe->ddr_phys_baseaddr);
+
+	pfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr, pfe->ddr_phys_baseaddr);
+
+
+	pfe_hw_init(pfe);
+
+	/* Load the class,TM, Util fw
+    * by now pfe is,
+    * - out of reset + disabled + configured,
+    * Fw loading should be done after pfe_hw_init() */
+	pfe_firmware_init();
+
+	init_done = 1;
+
+	return 0;
+}
+
+
+/** PFE remove function
+ *  - stopes PEs
+ *  - frees tx/rx descriptor resources
+ *  - should be called once.
+ *
+ * @param[in] pfe Pointer to pfe control block.
+ */
+int pfe_remove(struct pfe *pfe)
+{
+	if (g_tx_desc) {
+		free(g_tx_desc);
+	}
+
+	if (g_rx_desc) {
+		free(g_rx_desc);
+	}
+
+	pfe_firmware_exit();
+
+	return 0;
+}
+

drivers/c2000_eth/pfe_driver.h

diff --git a/drivers/c2000_eth/pfe_driver.h b/drivers/c2000_eth/pfe_driver.h
new file mode 100644
index 0000000..9f7256f
--- /dev/null
+++ b/drivers/c2000_eth/pfe_driver.h
@@ -0,0 +1,139 @@
+/*
+ *  (C) Copyright 2011
+ *  Author : Mindspeed Technologes
+ *  
+ *  See file CREDITS for list of people who contributed to this
+ *  project.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License as
+ *  published by the Free Software Foundation; either version 2 of
+ *  the License, or (at your option) any later version.
+ *  
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *  
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ *  MA 02111-1307 USA
+ * */
+
+#ifndef __PFE_DRIVER_H__
+#define __PFE_DRIVER_H__
+
+#include "hal.h"
+
+#include "pfe/pfe.h"
+#include "pfe/cbus.h"
+#include "pfe/cbus/bmu.h"
+
+
+
+typedef struct bufDesc {
+		  u32 ctrl;
+		  u32 status;
+		  u32 data;
+		  struct bufDesc *next;
+}bufDesc_t;
+
+#if defined(CONFIG_PLATFORM_PCI)
+#define HIF_RX_DESC_NT		4
+#define	HIF_TX_DESC_NT		4
+#else
+#define HIF_RX_DESC_NT		64
+#define	HIF_TX_DESC_NT		64
+#endif
+#define RX_BD_BASEADDR		(HIF_DESC_BASEADDR)
+#define TX_BD_BASEADDR		(HIF_DESC_BASEADDR + HIF_TX_DESC_SIZE)
+
+#define MIN_PKT_SIZE   		56
+#define MAX_FRAME_SIZE     2048
+
+
+typedef struct hif_header_s {
+	u8	port_no; //Carries input port no for host rx packets and output port no for tx pkts
+	u8 reserved0;
+	u32 reserved2;
+} __attribute__((packed)) hif_header_t;
+
+
+typedef struct rx_desc_s {
+	struct bufDesc *rxBase;
+	unsigned int rxBase_pa;
+	int rxToRead;
+	int rxRingSize;
+}rx_desc_t;
+
+typedef struct tx_desc_s {
+	struct bufDesc *txBase;
+	unsigned int txBase_pa;
+	int txToSend;
+	int txRingSize;
+}tx_desc_t;
+
+
+/* The set of statistics registers implemented in the Cadence MAC.
+ * The statistics registers implemented are a subset of all the statistics
+ * available, but contains all the compulsory ones.
+ */
+typedef struct gem_stats{
+    u32 octets_tx_bot;      /* Lower 32-bits for number of octets tx'd */
+    u32 octets_tx_top;      /* Upper 16-bits for number of octets tx'd */
+    u32 frames_tx;          /* Number of frames transmitted OK */
+    u32 broadcast_tx;       /* Number of broadcast frames transmitted */
+    u32 multicast_tx;       /* Number of multicast frames transmitted */
+    u32 pause_tx;           /* Number of pause frames transmitted. */
+    u32 frame64_tx;         /* Number of 64byte frames transmitted */
+    u32 frame65_127_tx;     /* Number of 65-127 byte frames transmitted */
+    u32 frame128_255_tx;    /* Number of 128-255 byte frames transmitted */
+    u32 frame256_511_tx;    /* Number of 256-511 byte frames transmitted */
+    u32 frame512_1023_tx;   /* Number of 512-1023 byte frames transmitted */
+    u32 frame1024_1518_tx;  /* Number of 1024-1518 byte frames transmitted*/
+    u32 frame1519_tx;       /* Number of frames greater than 1518 bytes tx*/
+    u32 tx_urun;            /* Transmit underrun errors due to DMA */
+    u32 single_col;         /* Number of single collision frames */
+    u32 multi_col;          /* Number of multi collision frames */
+    u32 excess_col;         /* Number of excessive collision frames. */
+    u32 late_col;           /* Collisions occuring after slot time */
+    u32 def_tx;             /* Frames deferred due to crs */
+    u32 crs_errors;         /* Errors caused by crs not being asserted. */
+    u32 octets_rx_bot;      /* Lower 32-bits for number of octets rx'd */
+    u32 octets_rx_top;      /* Upper 16-bits for number of octets rx'd */
+    u32 frames_rx;          /* Number of frames received OK */
+    u32 broadcast_rx;       /* Number of broadcast frames received */
+    u32 multicast_rx;       /* Number of multicast frames received */
+    u32 pause_rx;           /* Number of pause frames received. */
+    u32 frame64_rx;         /* Number of 64byte frames received */
+    u32 frame65_127_rx;     /* Number of 65-127 byte frames received */
+    u32 frame128_255_rx;    /* Number of 128-255 byte frames received */
+    u32 frame256_511_rx;    /* Number of 256-511 byte frames received */
+    u32 frame512_1023_rx;   /* Number of 512-1023 byte frames received */
+    u32 frame1024_1518_rx;  /* Number of 1024-1518 byte frames received*/
+    u32 frame1519_rx;       /* Number of frames greater than 1518 bytes rx*/
+    u32 usize_frames;       /* Frames received less than min of 64 bytes */
+    u32 excess_length;      /* Number of excessive length frames rx */
+    u32 jabbers;            /* Excessive length + crc or align errors. */
+    u32 fcs_errors;         /* Number of frames received with crc errors */
+    u32 length_check_errors;/* Number of frames with incorrect length */
+    u32 rx_symbol_errors;   /* Number of times rx_er asserted during rx */
+    u32 align_errors;       /* Frames received without integer no. bytes */
+    u32 rx_res_errors;      /* Number of times buffers ran out during rx */
+    u32 rx_orun;            /* Receive overrun errors due to DMA */
+    u32 ip_cksum;           /* IP header checksum errors */
+    u32 tcp_cksum;           /* TCP checksum errors */
+    u32 udp_cksum;           /* UDP checksum errors */
+} volatile GEM_STATS;
+
+
+int pfe_send(int phy_port, void *data, int length);
+int pfe_recv(unsigned int *pkt_ptr, int *phy_port);
+int pfe_tx_done(void);
+void pfe_gem_enable_all(void);
+void pfe_gemac_init(void *gemac_base, u32 mode, u32 speed, u32 duplex);
+
+
+#endif
+

drivers/c2000_eth/pfe_firmware.c

diff --git a/drivers/c2000_eth/pfe_firmware.c b/drivers/c2000_eth/pfe_firmware.c
new file mode 100644
index 0000000..202647a
--- /dev/null
+++ b/drivers/c2000_eth/pfe_firmware.c
@@ -0,0 +1,173 @@
+
+
+/** @file
+ *  Contains all the functions to handle parsing and loading of PE firmware files.
+ */
+
+#include "hal.h"
+#include "pfe_firmware.h"
+#include "pfe/pfe.h"
+
+
+/* CLASS-PE ELF file content */
+unsigned char class_fw_data[] __attribute__((aligned(sizeof(int)))) = {
+#include CLASS_FIRMWARE_FILENAME
+};
+
+/* TMU-PE ELF file content */
+unsigned char tmu_fw_data[] __attribute__((aligned(sizeof(int)))) = {
+#include TMU_FIRMWARE_FILENAME
+};
+
+#if !defined(CONFIG_UTIL_PE_DISABLED)
+unsigned char util_fw_data[] = {
+#include UTIL_FIRMWARE_FILENAME
+};
+#endif
+
+/** PFE elf firmware loader.
+* Loads an elf firmware image into a list of PE's (specified using a bitmask)
+*
+* @param pe_mask	Mask of PE id's to load firmware to
+* @param fw		Pointer to the firmware image
+*
+* @return		0 on sucess, a negative value on error
+*
+*/
+int pfe_load_elf(int pe_mask, const struct firmware *fw)
+{
+	Elf32_Ehdr *elf_hdr = (Elf32_Ehdr *)fw->data;
+	Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum);
+	Elf32_Shdr *shdr = (Elf32_Shdr *) (fw->data + be32_to_cpu(elf_hdr->e_shoff));
+	int id, section;
+	int rc;
+
+	printf("%s\n", __func__);
+
+	printf("%s no of sections: %d\n", __func__, sections);
+
+	/* Some sanity checks */
+	if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
+	{
+		printf("%s: incorrect elf magic number\n", __func__);
+		return -1;
+	}
+
+	if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32)
+	{
+		printf("%s: incorrect elf class(%x)\n", __func__, elf_hdr->e_ident[EI_CLASS]);
+		return -1;
+	}
+
+	if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB)
+	{
+		printf("%s: incorrect elf data(%x)\n", __func__, elf_hdr->e_ident[EI_DATA]);
+		return -1;
+	}
+
+	if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC)
+	{
+		printf("%s: incorrect elf file type(%x)\n", __func__, be16_to_cpu(elf_hdr->e_type));
+		return -1;
+	}	
+
+	for (section = 0; section < sections; section++, shdr++)
+	{
+		if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR)))
+                        continue;
+		
+		for (id = 0; id < MAX_PE; id++)
+			if (pe_mask & (1 << id))
+			{
+				rc = pe_load_elf_section(id, fw->data, shdr);
+				if (rc < 0)
+					goto err;
+			}
+	}
+
+	return 0;
+
+err:
+	return rc;
+}
+
+/** PFE firmware initialization.
+* Loads different firmware files from filesystem.
+* Initializes PE IMEM/DMEM and UTIL-PE DDR
+* Initializes control path symbol addresses (by looking them up in the elf firmware files
+* Takes PE's out of reset
+*
+* @return	0 on sucess, a negative value on error
+*
+*/
+int pfe_firmware_init(void)
+{
+	struct firmware class_fw, tmu_fw;
+#if !defined(CONFIG_UTIL_PE_DISABLED)
+ 	struct firmware util_fw;
+#endif
+	int rc = 0;
+
+	printf("%s\n", __func__);
+
+	class_fw.data = class_fw_data;
+	tmu_fw.data = tmu_fw_data;
+#if !defined(CONFIG_UTIL_PE_DISABLED)
+	util_fw.data = util_fw_data;
+#endif
+	
+	rc = pfe_load_elf(CLASS_MASK, &class_fw);
+	if (rc < 0) {
+		printf("%s: class firmware load failed\n", __func__);
+		goto err3;
+	}
+
+	printf("%s: class firmware loaded\n", __func__);
+
+	rc = pfe_load_elf(TMU_MASK, &tmu_fw);
+	if (rc < 0) {
+		printf("%s: tmu firmware load failed\n", __func__);
+		goto err3;
+	}
+
+	printf("%s: tmu firmware loaded\n", __func__);
+
+#if !defined(CONFIG_UTIL_PE_DISABLED)
+	rc = pfe_load_elf(UTIL_MASK, &util_fw);
+	if (rc < 0) {
+		printf("%s: util firmware load failed\n", __func__);
+		goto err3;
+	}
+
+	printf("%s: util firmware loaded\n", __func__);
+
+	util_enable();
+#endif
+
+	tmu_enable(0xf);
+	class_enable();
+
+	gpi_enable(HGPI_BASE_ADDR);
+
+
+err3:
+	return rc;
+}
+
+/** PFE firmware cleanup
+* Puts PE's in reset
+*
+*
+*/
+void pfe_firmware_exit(void)
+{
+	printf("%s\n", __func__);
+
+	class_disable();
+	tmu_disable(0xf);
+#if !defined(CONFIG_UTIL_PE_DISABLED)
+	util_disable();
+#endif
+	hif_tx_disable();
+	hif_rx_disable();
+}

drivers/c2000_eth/pfe_firmware.h

diff --git a/drivers/c2000_eth/pfe_firmware.h b/drivers/c2000_eth/pfe_firmware.h
new file mode 100644
index 0000000..abe2e5e
--- /dev/null
+++ b/drivers/c2000_eth/pfe_firmware.h
@@ -0,0 +1,20 @@
+
+
+/** @file
+ *  Contains all the defines to handle parsing and loading of PE firmware files.
+ */
+
+#ifndef __PFE_FIRMWARE_H__
+#define __PFE_FIRMWARE_H__
+
+
+#define CLASS_FIRMWARE_FILENAME		"class_sbl_c2000_elf.fw"
+#define TMU_FIRMWARE_FILENAME		   "tmu_sbl_c2000_elf.fw"
+#define UTIL_FIRMWARE_FILENAME		"util_c2000_elf.fw" 
+
+
+int pfe_firmware_init(void);
+void pfe_firmware_exit(void);
+
+
+#endif

drivers/c2000_eth/pfe_mod.h

diff --git a/drivers/c2000_eth/pfe_mod.h b/drivers/c2000_eth/pfe_mod.h
new file mode 100644
index 0000000..9436b72
--- /dev/null
+++ b/drivers/c2000_eth/pfe_mod.h
@@ -0,0 +1,140 @@
+/*
+ *  (C) Copyright 2011
+ *  Author : Mindspeed Technologes
+ *  
+ *  See file CREDITS for list of people who contributed to this
+ *  project.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License as
+ *  published by the Free Software Foundation; either version 2 of
+ *  the License, or (at your option) any later version.
+ *  
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *  
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ *  MA 02111-1307 USA
+ * */
+
+
+#ifndef _PFE_MOD_H_
+#define _PFE_MOD_H_
+
+#include <linux/device.h>
+
+#include "pfe/pfe.h"
+#include "pfe/cbus.h"
+#include "pfe/cbus/bmu.h"
+
+#include "pfe_driver.h"
+
+struct pfe;
+
+
+struct pfe {
+	unsigned long ddr_phys_baseaddr;
+	void *ddr_baseaddr;
+	void *cbus_baseaddr;
+	void *apb_baseaddr;
+	void *iram_baseaddr;
+	int hif_irq;
+	struct device *dev;
+	struct pci_dev *pdev;
+
+#if 0
+	struct pfe_ctrl ctrl;
+	struct pfe_hif hif;
+	struct pfe_eth eth;
+#endif
+};
+
+extern struct pfe *pfe;
+
+int pfe_probe(struct pfe *pfe);
+int pfe_remove(struct pfe *pfe);
+
+#ifndef SZ_1K
+#define SZ_1K 1024
+#endif
+
+#ifndef SZ_1M
+#define SZ_1M (1024 * 1024)
+#endif
+
+/* DDR Mapping */
+#if !defined(CONFIG_PLATFORM_PCI)
+#define UTIL_CODE_BASEADDR	0
+#define UTIL_CODE_SIZE		(128 * SZ_1K)
+#define UTIL_DDR_DATA_BASEADDR	(UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
+#define UTIL_DDR_DATA_SIZE	(64 * SZ_1K)
+#define CLASS_DDR_DATA_BASEADDR	(UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
+#define CLASS_DDR_DATA_SIZE	(32 * SZ_1K)
+#define TMU_DDR_DATA_BASEADDR	(CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
+#define TMU_DDR_DATA_SIZE	(32 * SZ_1K)
+#define ROUTE_TABLE_BASEADDR	(TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
+#define ROUTE_TABLE_HASH_BITS	15	/**< 32K entries */
+#define ROUTE_TABLE_SIZE	((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
+#define BMU2_DDR_BASEADDR	(ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
+#define BMU2_BUF_COUNT		(4096 - 256)			/**< This is to get a total DDR size of 12MiB */
+#define BMU2_DDR_SIZE		(DDR_BUF_SIZE * BMU2_BUF_COUNT)
+#define TMU_LLM_BASEADDR	(BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
+#define TMU_LLM_QUEUE_LEN	(16 * 256)			/**< Must be power of two and at least 16 * 8 = 128 bytes */
+#define TMU_LLM_SIZE		(4 * 16 * TMU_LLM_QUEUE_LEN)	/**< (4 TMU's x 16 queues x queue_len) */
+
+#if (TMU_LLM_BASEADDR + TMU_LLM_SIZE) > 0xC00000
+#error DDR mapping above 12MiB
+#endif
+
+#else
+
+#define UTIL_CODE_BASEADDR	0
+#if defined(CONFIG_UTIL_PE_DISABLED)
+#define UTIL_CODE_SIZE		(0 * SZ_1K)
+#else
+#define UTIL_CODE_SIZE		(8 * SZ_1K)
+#endif
+#define UTIL_DDR_DATA_BASEADDR	(UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
+#define UTIL_DDR_DATA_SIZE	(0 * SZ_1K)
+#define CLASS_DDR_DATA_BASEADDR	(UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
+#define CLASS_DDR_DATA_SIZE	(0 * SZ_1K)
+#define TMU_DDR_DATA_BASEADDR	(CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
+#define TMU_DDR_DATA_SIZE	(0 * SZ_1K)
+#define ROUTE_TABLE_BASEADDR	(TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
+#define ROUTE_TABLE_HASH_BITS	5	/**< 32 entries */
+#define ROUTE_TABLE_SIZE	((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
+#define BMU2_DDR_BASEADDR	(ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
+#define BMU2_BUF_COUNT		8
+#define BMU2_DDR_SIZE		(DDR_BUF_SIZE * BMU2_BUF_COUNT)
+#define TMU_LLM_BASEADDR	(BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
+#define TMU_LLM_QUEUE_LEN	(16 * 8)			/**< Must be power of two and at least 16 * 8 = 128 bytes */
+#define TMU_LLM_SIZE		(4 * 16 * TMU_LLM_QUEUE_LEN)	/**< (4 TMU's x 16 queues x queue_len) */
+#define HIF_DESC_BASEADDR	(TMU_LLM_BASEADDR + TMU_LLM_SIZE)
+#define HIF_RX_DESC_SIZE	(16*HIF_RX_DESC_NT)
+#define HIF_TX_DESC_SIZE	(16*HIF_TX_DESC_NT)
+#define HIF_DESC_SIZE		(HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
+#define HIF_RX_PKT_DDR_BASEADDR	(HIF_DESC_BASEADDR + HIF_DESC_SIZE)
+#define HIF_RX_PKT_DDR_SIZE	(HIF_RX_DESC_NT * DDR_BUF_SIZE)
+#define HIF_TX_PKT_DDR_BASEADDR	(HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
+#define HIF_TX_PKT_DDR_SIZE	(HIF_TX_DESC_NT * DDR_BUF_SIZE)
+#define ROUTE_BASEADDR		(HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
+#define ROUTE_SIZE		(2 * CLASS_ROUTE_SIZE)
+
+#if (ROUTE_BASEADDR + ROUTE_SIZE) > 0x10000
+#error DDR mapping above 64KiB
+#endif
+
+#define PFE_HOST_TO_PCI(addr)	(((u32)addr)- ((u32)DDR_BASE_ADDR))
+#define PFE_PCI_TO_HOST(addr)	(((u32)addr)+ ((u32)DDR_BASE_ADDR))
+#endif
+
+/* LMEM Mapping */
+#define BMU1_LMEM_BASEADDR	0
+#define BMU1_BUF_COUNT		256
+#define BMU1_LMEM_SIZE		(LMEM_BUF_SIZE * BMU1_BUF_COUNT)
+
+#endif /* _PFE_MOD_H */

drivers/c2000_eth/pfe_proc.c

diff --git a/drivers/c2000_eth/pfe_proc.c b/drivers/c2000_eth/pfe_proc.c
new file mode 100644
index 0000000..8c1ba64
--- /dev/null
+++ b/drivers/c2000_eth/pfe_proc.c
@@ -0,0 +1,203 @@
+/*
+ *  (C) Copyright 2011
+ *  Author : Mindspeed Technologes
+ *  
+ *  See file CREDITS for list of people who contributed to this
+ *  project.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License as
+ *  published by the Free Software Foundation; either version 2 of
+ *  the License, or (at your option) any later version.
+ *  
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *  
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ *  MA 02111-1307 USA
+ * */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/proc_fs.h>
+#include <linux/fcntl.h>
+#include <linux/seq_file.h>
+#include <asm/uaccess.h>
+
+
+
+static struct proc_dir_entry *pdir = NULL;
+static struct proc_dir_entry *unit = NULL;
+static struct proc_dir_entry *pkt = NULL;
+static struct proc_dir_entry *dump = NULL;
+
+
+extern void pfe_class_read(int id);
+
+ssize_t pfe_unit_read(struct file *file, char __user *buf,
+			size_t count, loff_t *ppos)
+{
+	printk(KERN_INFO "%s:\n", __func__);
+	return 0;
+}
+
+static unsigned char lbuf[20];
+ssize_t pfe_unit_write(struct file *file, char __user *buf,
+			size_t count, loff_t *ppos)
+{
+	int id = -1;
+
+	printk(KERN_INFO "%s:\n", __func__);
+
+	if (copy_from_user(lbuf, buf,count))
+		return -ENOMEM;
+	lbuf[count] = 0;
+
+	id = simple_strtoul(lbuf, NULL, 0);
+	printk(KERN_INFO "id: %d\n", id);
+
+	if ((id >= 0) || (id < 4))
+		pfe_class_read(id);
+	
+	return count;
+}
+
+extern void pfe_print_tx_status(void);
+ssize_t pfe_pkt_read(struct file *file, char __user *buf,
+			size_t count, loff_t *ppos)
+{
+	printk(KERN_INFO "%s:\n", __func__);
+	pfe_print_tx_status();
+	return 0;
+}
+
+extern void pfe_send_pkt(int len);
+
+ssize_t pfe_pkt_write(struct file *file, char __user *buf,
+			size_t count, loff_t *ppos)
+{
+	int len = -1;
+
+	printk(KERN_INFO "%s:\n", __func__);
+
+	if (copy_from_user(lbuf, buf,count))
+		return -ENOMEM;
+	lbuf[count] = 0;
+
+	len = simple_strtoul(lbuf, NULL, 0);
+	printk(KERN_INFO "len: %d\n", len);
+
+	pfe_send_pkt(len);
+
+	return count;
+}
+//============================================================
+extern void	hif_tx_desc_dump(void);
+extern void	hif_rx_desc_dump(void);
+extern void class_pe_dump(void);
+
+ssize_t pfe_dump_read(struct file *file, char __user *buf,
+			size_t count, loff_t *ppos)
+{
+	printk(KERN_INFO "%s:\n", __func__);
+	hif_tx_desc_dump();
+	hif_rx_desc_dump();
+   class_pe_dump();
+	return 0;
+}
+
+extern void class_dmem_dump(int id);
+ssize_t pfe_dump_write(struct file *file, char __user *buf,
+			size_t count, loff_t *ppos)
+{
+	int id;
+	printk(KERN_INFO "%s:\n", __func__);
+
+	if (copy_from_user(lbuf, buf,count))
+		return -ENOMEM;
+	lbuf[count] = 0;
+
+	id = simple_strtoul(lbuf, NULL, 0);
+	printk(KERN_INFO "id: %d\n", id);
+
+	class_dmem_dump(id);
+
+	return count;
+}
+//============================================================
+
+static struct file_operations pfe_unit_fops = {
+	.owner = THIS_MODULE,
+	.read = pfe_unit_read,
+	.write = pfe_unit_write,
+};
+
+static struct file_operations pfe_pkt_fops = {
+	.owner = THIS_MODULE,
+	.read = pfe_pkt_read,
+	.write = pfe_pkt_write,
+};
+
+static struct file_operations pfe_dump_fops = {
+	.owner = THIS_MODULE,
+	.read = pfe_dump_read,
+	.write = pfe_dump_write,
+};
+
+void pfe_proc_init(void)
+{
+	pdir = proc_mkdir("pfe", NULL);	
+	if (pdir == NULL) {
+		printk(KERN_ERR "%s: Unable to create proc dir entry\n", __func__);
+		return;
+	}
+
+	unit = create_proc_entry("unit", S_IFREG, pdir);
+	if (unit == NULL) {
+		printk(KERN_ERR "%s: Unable to create proc entry: unit\n", __func__);
+		remove_proc_entry("pfe", NULL);
+		return;
+	}
+	unit->proc_fops = &pfe_unit_fops;
+
+	pkt = create_proc_entry("pkt", S_IFREG, pdir);
+	if (unit == NULL) {
+		printk(KERN_ERR "%s: Unable to create proc entry: pkt\n", __func__);
+		remove_proc_entry("unit", pdir);
+		remove_proc_entry("pfe", NULL);
+		return;
+	}
+	pkt->proc_fops = &pfe_pkt_fops;
+
+	dump = create_proc_entry("dump", S_IFREG, pdir);
+	if (dump == NULL) {
+		printk(KERN_ERR "%s: Unable to create proc entry: pkt\n", __func__);
+		remove_proc_entry("unit", pdir);
+		remove_proc_entry("pkt", pdir);
+		remove_proc_entry("pfe", NULL);
+		return;
+	}
+	dump->proc_fops = &pfe_dump_fops;
+
+
+	
+}
+
+void pfe_proc_exit(void)
+{
+	if (unit)
+		remove_proc_entry("unit", pdir);
+	if (pkt)
+		remove_proc_entry("pkt", pdir);
+	if (dump)
+		remove_proc_entry("dump", pdir);
+	if (pdir) 
+		remove_proc_entry("pfe", NULL);
+
+	return;
+}
+

drivers/c2000_eth/pfe_unit.c

diff --git a/drivers/c2000_eth/pfe_unit.c b/drivers/c2000_eth/pfe_unit.c
new file mode 100644
index 0000000..cad779b
--- /dev/null
+++ b/drivers/c2000_eth/pfe_unit.c
@@ -0,0 +1,334 @@
+/*
+ *  (C) Copyright 2011
+ *  Author : Mindspeed Technologes
+ *  
+ *  See file CREDITS for list of people who contributed to this
+ *  project.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License as
+ *  published by the Free Software Foundation; either version 2 of
+ *  the License, or (at your option) any later version.
+ *  
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *  
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ *  MA 02111-1307 USA
+ * */
+
+
+#include <linux/delay.h>
+#include "pfe_driver.h"
+
+
+void dump_phy_reg();
+#if 0
+#define DMEM_TEST_BASE_ADDR	0x0	/* !!! For class overlaps with packets in dmem, for tmu overwrites exception vectors !!! */
+
+#define BUF_SIZE 6
+
+static u32 w[BUF_SIZE] = {0x01234567, 0x89abcdef, 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff};
+static u32 zero[BUF_SIZE] = {0, };
+static u32 r[BUF_SIZE];
+
+static void dmem_read4_write4(unsigned int id)
+{
+	pe_dmem_write(id, w[0], DMEM_TEST_BASE_ADDR, 4);
+
+	r[0] = pe_dmem_read(id, DMEM_TEST_BASE_ADDR, 4);
+
+	if (r[0] != w[0])
+		printk(KERN_ERR "PE %d: %s failed: %#x %#x\n", id, __func__, w[0], r[0]);
+	else
+		printk(KERN_INFO "PE %d: %s wr-pass: %#x %#x\n", id, __func__, w[0], r[0]);
+}
+#endif
+
+#if 0
+void pfe_unit_test(void)
+{
+	u32 i,val,j;
+
+#if 0
+	dmem_read4_write4(0);
+	dmem_read4_write4(1);
+	dmem_read4_write4(2);
+	dmem_read4_write4(3);
+
+	//dmem_read4_write4(4);
+	for(i=0; i < 4; i++) {
+		val = pe_dmem_read(0, 0x830 + (i * 4), 4);
+		printk(KERN_ERR "PE %d: loc: %d, regMask: %08x\n", 0, i, val);
+	}
+
+	val = pe_dmem_read(0, 0x840, 4);
+	printk(KERN_ERR "PE %d: %08x\n", 0, val);
+
+	val = pe_dmem_read(0, 0x844, 4);
+	printk(KERN_ERR "PE %d: %08x\n", 0, val);
+
+	val = pe_dmem_read(0, 0x840, 4);
+	printk(KERN_ERR "PE %d: %08x\n", 0, val);
+
+	val = pe_dmem_read(0, 0x844, 4);
+	printk(KERN_ERR "PE %d: %08x\n", 0, val);
+
+
+	val = pe_dmem_read(0, 0x844, 4);
+	printk(KERN_ERR "PE %d: %08x\n", 0, val);
+
+#endif
+
+	for(i=0; i < 4; i++)  {
+		//printk(KERN_ERR "%s: %#lx %#lx\n", __func__, readl(CLASS_STATE), readl(CLASS_PE0_DEBUG));	
+		
+		for(j=0; j < 10; j++)  {
+			printk(KERN_ERR "%s: %#lx\n", __func__, readl(CLASS_PE0_DEBUG));	
+		}
+		val = pe_dmem_read(i, 0x840, 4);
+		printk(KERN_ERR "PE %d: %08x\n", i, val);
+		val = pe_dmem_read(i, 0x844, 4);
+		printk(KERN_ERR "PE %d: %08x\n", i, val);
+	}
+
+}
+#endif
+static char stat_strings[][50] = {
+	"tx- octets  (Lower 32-bits)",
+	"tx- octets  (Upper 16-bits)",
+	"tx- packets",
+	"tx- broadcast",
+	"tx- multicast",
+	"tx- pause",
+	"tx- 64 bytes packets",
+	"tx- 64 - 127 bytes packets",
+	"tx- 128 - 255 bytes packets",
+	"tx- 256 - 511 bytes packets",
+	"tx- 512 - 1023 bytes packets",
+	"tx- 1024 - 1518 bytes packets",
+	"tx- > 1518 bytes packets",
+	"tx- underruns  - errors",
+	"tx- single collision",
+	"tx- multi collision",
+	"tx- exces. collision  - errors",
+	"tx- late collision  - errors",
+	"tx- deferred",
+	"tx- carrier sense - errors",
+	"rx- octets (Lower 32-bits)",
+	"rx- octets (Upper 16-bits)",
+	"rx- packets",
+	"rx- broadcast",
+	"rx- multicast",
+	"rx- pause",
+	"rx- 64 bytes packets",
+	"rx- 64 - 127 bytes packets",
+	"rx- 128 - 255 bytes packets",
+	"rx- 256 - 511 bytes packets",
+	"rx- 512 - 1023 bytes packets",
+	"rx- 1024 - 1518 bytes packets",
+	"rx- > 1518 bytes packets",
+	"rx- undersize -errors",
+	"rx- oversize  - errors ",
+	"rx- jabbers - errors",
+	"rx- fcs - errors",
+	"rx- length - errors",
+	"rx- symbol - errors",
+	"rx- align - errors",
+	"rx- ressource - errors",
+	"rx- overrun - errors",
+	"rx- IP cksum - errors",
+	"rx- TCP cksum - errors",
+	"rx- UDP cksum - errors" 
+};
+static void gem_print_stats(void *base)
+{
+	u32 *pstat = (u32*)gemac_get_stats(base);
+	int i;
+
+	for (i=0; i<(sizeof(GEM_STATS)/4); i++)
+		printk("%s : %d\n", stat_strings[i], *pstat++);
+}
+
+
+void pfe_class_read (int id)
+{
+	u32 val,j;
+
+	for(j=0; j < 20; j++)  {
+		printk(KERN_ERR "%s: %#lx\n", __func__, readl(CLASS_PE0_DEBUG));	
+	}
+
+	val = pe_dmem_read(id, 0x840, 4);
+	printk(KERN_ERR "PE %d: %08x\n", id, val);
+	val = pe_dmem_read(id, 0x844, 4);
+	printk(KERN_ERR "PE %d: %08x\n", id, val);
+
+	return;
+
+}
+
+void pfe_send_pkt(int len)
+{
+	unsigned char *pbuf;
+	int i;
+	int rcount = 0;
+	int rc,phyport=0;
+
+	printk(KERN_INFO "%s:\n", __func__);
+
+	pbuf = (unsigned char *)kmalloc(1024*2, GFP_ATOMIC | GFP_DMA);
+
+	if ((len >= 0) || (len < 1000))  {
+
+		for(i=0; i < len; i++)
+			pbuf[i] = i;
+#if 0
+		if(len == 100) phyport=0;
+		if(len == 200) phyport=1;
+		if(len == 300) phyport=2;
+		if(len == 400) phyport=3;
+#endif
+
+		rc = pfe_send(phyport, (void *)(pbuf), len);
+
+		if (rc < 0)
+			goto done;
+			
+		/* wait for tx done/completion indication */
+		rcount = 0;
+		while (1) {
+			rc = pfe_tx_done(); 
+			if (rc == 0)
+				break;
+			mdelay(100);
+			if (rcount == 20) {
+				printk(KERN_ERR "Tx send fail\n");
+				break;
+			}
+			rcount++;
+		}
+	}
+
+done:
+	kfree(pbuf);
+}
+
+void pfe_print_tx_status(void)
+{
+	u32 val;
+
+	gem_print_stats(EMAC1_BASE_ADDR);
+	//gem_print_stats(EMAC2_BASE_ADDR);
+
+	val = readl(HIF_TX_CTRL);
+	printk(KERN_INFO "TX_CTRL: %08x\n", val);
+
+	val = readl(HIF_TX_CURR_BD_ADDR);
+	printk(KERN_INFO "TX_CURR_BD_ADDR: %08x\n", val);
+
+	val = readl(HIF_TX_BDP_ADDR);
+	printk(KERN_INFO "TX_BDP_ADDR: %08x\n", val);
+
+	val = readl(HIF_TX_STATUS);
+	printk(KERN_INFO "TX_STATUS: %08x\n", val);
+
+	val = readl(HIF_TX_DMA_STATUS);
+	printk(KERN_INFO "TX_DMA_STATUS: %08x\n", val);
+
+	val = readl(BMU2_BASE_ADDR+BMU_REM_BUF_CNT);
+	printk(KERN_INFO "BMU2_REM_BUF_CNT: %08x\n", val);
+
+	val = readl(BMU1_BASE_ADDR+BMU_REM_BUF_CNT);
+	printk(KERN_INFO "BMU1_REM_BUF_CNT: %08x\n", val);
+
+}
+
+void class_dmem_readn(int id, u32 addr, u32 len)
+{
+	u32 val, i;
+
+
+	for(i=0; i < len; i += 4)  {
+		val = pe_dmem_read(id, addr+i, 4);
+		printk(KERN_INFO "%08x: %08x\n",addr+i, val);
+	}
+}
+
+void class_pmem_readn(int id, u32 addr, u32 len)
+{
+	u32 val, i;
+
+	printk(KERN_INFO "Class pe: %d PMEM\n", id);
+	for(i=0; i < len; i += 4)  {
+		val = pe_pmem_read(id, addr+i, 4);
+		printk(KERN_INFO "%08x: %08x\n",addr+i, val);
+		mdelay(40);
+	}
+}
+
+void class_pe_dump(void)
+{
+	u32 val,j,id;
+
+#if 0
+	printk(KERN_INFO "Class-PE 0: ===========>\n");
+	for(j=0; j < 20; j++)  {
+		printk(KERN_ERR "%s: PC: %#lx\n", __func__, readl(CLASS_PE0_DEBUG)&0xffff);	
+		mdelay(40);
+	}
+	printk(KERN_INFO "Class-PE 0: DMEM /n");
+	class_dmem_readn(0,0x814,20);
+	//class_pmem_readn(0,0x10000, 256);
+#endif
+	printk(KERN_INFO "Class-PE 1: ===========>\n");
+	for(j=0; j < 10; j++)  {
+		printk(KERN_ERR "%s: PC: %#lx\n", __func__, readl(CLASS_PE1_DEBUG)&0xffff);	
+		mdelay(40);
+	}
+	class_dmem_readn(1,0x858,4);
+	//printk(KERN_INFO "Class-PE 1: DMEM /n");
+	//class_dmem_readn(1,0x814,20);
+	//class_pmem_readn(1,0x10000, 256);
+
+#if 0
+	printk(KERN_INFO "Class-PE 2: ===========>\n");
+	for(j=0; j < 20; j++)  {
+		printk(KERN_ERR "%s: PC: %#lx\n", __func__, readl(CLASS_PE2_DEBUG)&0xffff);	
+		mdelay(40);
+	}
+	printk(KERN_INFO "Class-PE 2: DMEM /n");
+	class_dmem_readn(2,0x814,20);
+	//class_pmem_readn(2,0x10000, 256);
+
+
+	printk(KERN_INFO "Class-PE 3: ===========>\n");
+	for(j=0; j < 20; j++)  {
+		printk(KERN_ERR "%s: PC: %#lx\n", __func__, readl(CLASS_PE3_DEBUG)&0xffff);	
+		mdelay(40);
+	}
+	printk(KERN_INFO "Class-PE 3: DMEM /n");
+	class_dmem_readn(3,0x814,20);
+	//class_pmem_readn(3,0x10000, 256);
+#endif
+	
+}
+
+void class_dmem_dump(int id)
+{
+	u32 val, i;
+
+	if (id > 3)
+		id = 0;
+
+	printk(KERN_ERR "PE %d:\n", id);
+
+	for(i=0; i < 256; i += 4)  {
+		val = pe_dmem_read(id, i, 4);
+		printk("%08x: %08x\n",i, val);
+	}
+}

drivers/c2000_eth/tmu_sbl_c2000_elf.fw

diff --git a/drivers/c2000_eth/tmu_sbl_c2000_elf.fw b/drivers/c2000_eth/tmu_sbl_c2000_elf.fw
new file mode 100644
index 0000000..866d315
--- /dev/null
+++ b/drivers/c2000_eth/tmu_sbl_c2000_elf.fw
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\ No newline at end of file

drivers/c2000_eth/util_c2000_elf.fw

diff --git a/drivers/c2000_eth/util_c2000_elf.fw b/drivers/c2000_eth/util_c2000_elf.fw
new file mode 100644
index 0000000..8107af5
--- /dev/null
+++ b/drivers/c2000_eth/util_c2000_elf.fw
@@ -0,0 +1 @@
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\ No newline at end of file

drivers/cfi_flash.c

diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c
index fd0a186..357418c 100644
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -71,6 +71,8 @@
  * Verify erase and program timeouts.
  */
 
+#define       CFG_FLASH_BASE  0xC0000000
+
 #ifndef CFG_FLASH_BANKS_LIST
 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
 #endif
@@ -173,11 +175,19 @@
 /* use CFG_MAX_FLASH_BANKS_DETECT if defined */
 #ifdef CFG_MAX_FLASH_BANKS_DETECT
 static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
+#ifdef CONFIG_COMCERTO
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT];	/* FLASH chips info */
+#else
 flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT];	/* FLASH chips info */
+#endif
 #else
 static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
+#ifdef CONFIG_COMCERTO
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* FLASH chips info */
+#else
 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];		/* FLASH chips info */
 #endif
+#endif
 
 /*
  * Check if chip width is defined. If not, start detecting with 8bit.
@@ -186,6 +196,37 @@
 #define CFG_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
 #endif
 
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+
+extern void board_map(flash_info_t *info, unsigned long addr);
+
+#define map_readc(info, ptr)			(board_map(info, (unsigned long)ptr), (*(ptr)))
+#define map_readw(info, ptr)			(board_map(info, (unsigned long)ptr), __le16_to_cpu(*(ptr)))
+#define map_readl(info, ptr)			(board_map(info, (unsigned long)ptr), __le32_to_cpu(*(ptr)))
+#define map_readll(info, ptr)			(board_map(info, (unsigned long)ptr), __le64_to_cpu(*(ptr)))
+#define map_writec(info, ptr, val)		(board_map(info, (unsigned long)ptr), *(ptr) = (val))
+#define map_writew(info, ptr, val)		(board_map(info, (unsigned long)ptr), *(ptr) = __cpu_to_le16(val))
+#define map_writel(info, ptr, val)		(board_map(info, (unsigned long)ptr), *(ptr) = __cpu_to_le32(val))
+#define map_writell(info, ptr, val)		(board_map(info, (unsigned long)ptr), *(ptr) = __cpu_to_le64(val))
+#define map_copyfrom(info, dst, src, len)	(board_map(info, (unsigned long)src), memcpy(dst, src, len))
+#define map_copyto(info, dst, src, len)		(board_map(info, (unsigned long)dst), memcpy(dst, src, len))
+
+
+#else
+
+#define map_readc(info, ptr)			(*(ptr))
+#define map_readw(info, ptr)			__le16_to_cpu(*(ptr))
+#define map_readl(info, ptr)			__le32_to_cpu(*(ptr))
+#define map_readll(info, ptr)			__le64_to_cpu(*(ptr))
+#define map_copyfrom(info, dst, src, len)	memcpy(dst, src, len)
+#define map_writec(info, ptr, val)		(*(ptr) = (val))
+#define map_writew(info, ptr, val)		(*(ptr) = __cpu_to_le16(val))
+#define map_writel(info, ptr, val)		(*(ptr) = __cpu_to_le32(val))
+#define map_writell(info, ptr, val)		(*(ptr) = __cpu_to_le64(val))
+#define map_copyto(info, dst, src, len)		memcpy(dst, src, len
+
+#endif
+
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -212,6 +253,15 @@
 static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
 #endif
 
+#ifdef CONFIG_COMCERTO
+void cfi_flash_print_info (flash_info_t *);
+int cfi_flash_erase (flash_info_t *, int, int);
+int cfi_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+int cfi_flash_real_protect (flash_info_t * info, long sector, int prot);
+#endif
+
+
+
 /*-----------------------------------------------------------------------
  * create an address based on the offset and the port width
  */
@@ -244,12 +294,14 @@
 					 x + FLASH_OFFSET_CFI_RESP);
 		debug ("%p : ", cptr.cp);
 		for (y = 0; y < 16; y++) {
-			debug ("%2.2x ", cptr.cp[y]);
+			/* COMPLEX_MAPPINGS */
+			debug ("%2.2x ", map_readc(info, cptr.cp + y));
 		}
 		debug (" ");
 		for (y = 0; y < 16; y++) {
-			if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
-				debug ("%c", cptr.cp[y]);
+			/* COMPLEX_MAPPINGS */
+			if (map_readc(info, cptr.cp + y) >= 0x20 && map_readc(info, cptr.cp + y) <= 0x7e) {
+				debug ("%c", map_readc(info, cptr.cp + y));
 			} else {
 				debug (".");
 			}
@@ -268,10 +320,13 @@
 	uchar *cp;
 
 	cp = flash_make_addr (info, 0, offset);
-#if defined(__LITTLE_ENDIAN)
-	return (cp[0]);
+
+#if defined(__LITTLE_ENDIAN) || (defined(CONFIG_COMCERTO) && defined(BE8_MODE))
+	/* COMPLEX_MAPPINGS */
+	return (map_readc(info, cp));
 #else
-	return (cp[info->portwidth - 1]);
+	/* COMPLEX_MAPPINGS */
+	return (map_readc(info, cp + info->portwidth - 1));
 #endif
 }
 
@@ -292,14 +347,18 @@
 	debug ("ushort addr is at %p info->portwidth = %d\n", addr,
 	       info->portwidth);
 	for (x = 0; x < 2 * info->portwidth; x++) {
-		debug ("addr[%x] = 0x%x\n", x, addr[x]);
+		/* COMPLEX_MAPPINGS */
+		debug ("addr[%x] = 0x%x\n", x, map_readc(info, addr + x));
 	}
 #endif
-#if defined(__LITTLE_ENDIAN)
-	retval = ((addr[(info->portwidth)] << 8) | addr[0]);
+
+#if defined(__LITTLE_ENDIAN) || (defined(CONFIG_COMCERTO) && defined(BE8_MODE))
+	/* COMPLEX_MAPPINGS */
+	retval = ((map_readc(info, addr + info->portwidth) << 8) | map_readc(info, addr));
 #else
-	retval = ((addr[(2 * info->portwidth) - 1] << 8) |
-		  addr[info->portwidth - 1]);
+	/* COMPLEX_MAPPINGS */
+	retval = ((map_readc(info, addr + (2 * info->portwidth) - 1) << 8) |
+		  map_readc(info, addr + info->portwidth - 1));
 #endif
 
 	debug ("retval = 0x%x\n", retval);
@@ -324,17 +383,21 @@
 	debug ("long addr is at %p info->portwidth = %d\n", addr,
 	       info->portwidth);
 	for (x = 0; x < 4 * info->portwidth; x++) {
-		debug ("addr[%x] = 0x%x\n", x, addr[x]);
+		/* COMPLEX_MAPPINGS */
+		debug ("addr[%x] = 0x%x\n", x, map_readc(info, addr + x));
 	}
 #endif
-#if defined(__LITTLE_ENDIAN)
-	retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
-		(addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8);
+
+#if defined(__LITTLE_ENDIAN) || (defined(CONFIG_COMCERTO) && defined(BE8_MODE))
+	/* COMPLEX_MAPPINGS */
+	retval = (map_readc(info, addr) << 16) | (map_readc(info, addr + info->portwidth) << 24) |
+		(map_readc(info, addr + 2 * info->portwidth)) | (map_readc(info, addr + 3 * info->portwidth) << 8);
 #else
-	retval = (addr[(2 * info->portwidth) - 1] << 24) |
-		(addr[(info->portwidth) - 1] << 16) |
-		(addr[(4 * info->portwidth) - 1] << 8) |
-		addr[(3 * info->portwidth) - 1];
+	/* COMPLEX_MAPPINGS */
+	retval = (map_readc(info, addr + (2 * info->portwidth) - 1) << 24) |
+		(map_readc(info, addr + (info->portwidth) - 1) << 16) |
+		(map_readc(info, addr + (4 * info->portwidth) - 1) << 8) |
+		map_readc(info, addr + (3 * info->portwidth) - 1);
 #endif
 	return retval;
 }
@@ -342,7 +405,11 @@
 
 /*-----------------------------------------------------------------------
  */
+#ifdef CONFIG_COMCERTO
+unsigned long cfi_flash_init (void)
+#else
 unsigned long flash_init (void)
+#endif
 {
 	unsigned long size = 0;
 	int i;
@@ -452,7 +519,11 @@
 
 /*-----------------------------------------------------------------------
  */
+#ifdef CONFIG_COMCERTO
+int cfi_flash_erase (flash_info_t * info, int s_first, int s_last)
+#else
 int flash_erase (flash_info_t * info, int s_first, int s_last)
+#endif
 {
 	int rcode = 0;
 	int prot;
@@ -516,7 +587,11 @@
 
 /*-----------------------------------------------------------------------
  */
+#ifdef CONFIG_COMCERTO
+void cfi_flash_print_info (flash_info_t * info)
+#else
 void flash_print_info (flash_info_t * info)
+#endif
 {
 	int i;
 
@@ -554,7 +629,9 @@
 		flash = (volatile unsigned long *) info->start[i];
 		size = size >> 2;	/* divide by 4 for longword access */
 		for (k = 0; k < size; k++) {
-			if (*flash++ != 0xffffffff) {
+			/* COMPLEX_MAPPINGS */
+			if (map_readl(info, flash) != 0xffffffff) {
+				flash++;
 				erased = 0;
 				break;
 			}
@@ -584,7 +661,11 @@
  * 1 - write timeout
  * 2 - Flash not erased
  */
+#ifdef CONFIG_COMCERTO
+int cfi_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+#else
 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+#endif
 {
 	ulong wp;
 	ulong cp;
@@ -604,7 +685,7 @@
 		cword.l = 0;
 		cp = wp;
 		for (i = 0; i < aln; ++i, ++cp)
-			flash_add_byte (info, &cword, (*(uchar *) cp));
+			flash_add_byte (info, &cword, map_readc(info, (uchar *)cp));
 
 		for (; (i < info->portwidth) && (cnt > 0); i++) {
 			flash_add_byte (info, &cword, *src++);
@@ -612,7 +693,7 @@
 			cp++;
 		}
 		for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
-			flash_add_byte (info, &cword, (*(uchar *) cp));
+			flash_add_byte (info, &cword, map_readc(info, (uchar *)cp));
 		if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
 			return rc;
 		wp = cp;
@@ -671,7 +752,7 @@
 		--cnt;
 	}
 	for (; i < info->portwidth; ++i, ++cp) {
-		flash_add_byte (info, &cword, (*(uchar *) cp));
+		flash_add_byte (info, &cword, map_readc(info, (uchar *)cp));
 	}
 
 	return flash_write_cfiword (info, wp, cword);
@@ -681,7 +762,11 @@
  */
 #ifdef CFG_FLASH_PROTECTION
 
+#ifdef CONFIG_COMCERTO
+int cfi_flash_real_protect (flash_info_t * info, long sector, int prot)
+#else
 int flash_real_protect (flash_info_t * info, long sector, int prot)
+#endif
 {
 	int retcode = 0;
 
@@ -726,7 +811,7 @@
 	dst = buffer;
 	src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
 	flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
-	memcpy (dst, src + offset, len);
+	map_copyfrom(info, dst, src + offset, len);
 	flash_write_cmd (info, 0, 0, info->cmd_reset);
 }
 
@@ -740,7 +825,7 @@
 
 	src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
 	flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
-	memcpy (buffer, src + offset, len);
+	map_copyfrom(info, buffer, src + offset, len);
 	flash_write_cmd (info, 0, 0, info->cmd_reset);
 }
 
@@ -915,7 +1000,8 @@
 	case FLASH_CFI_8BIT:
 		debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
 		       cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
-		*addr.cp = cword.c;
+		/* COMPLEX_MAPPINGS */
+		map_writec(info, addr.cp, cword.c);
 #ifdef CONFIG_BLACKFIN
 		asm("ssync;");
 #endif
@@ -924,7 +1010,8 @@
 		debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
 		       cmd, cword.w,
 		       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
-		*addr.wp = cword.w;
+		/* COMPLEX_MAPPINGS */
+		map_writew(info, addr.wp, cword.w);
 #ifdef CONFIG_BLACKFIN
 		asm("ssync;");
 #endif
@@ -933,7 +1020,7 @@
 		debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
 		       cmd, cword.l,
 		       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
-		*addr.lp = cword.l;
+		map_writel(info, addr.lp, cword.l);
 #ifdef CONFIG_BLACKFIN
 		asm("ssync;");
 #endif
@@ -950,7 +1037,7 @@
 			       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
 		}
 #endif
-		*addr.llp = cword.ll;
+		map_writell(info, addr.llp, cword.ll);
 #ifdef CONFIG_BLACKFIN
 		asm("ssync;");
 #endif
@@ -978,16 +1065,19 @@
 	debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
 	switch (info->portwidth) {
 	case FLASH_CFI_8BIT:
-		debug ("is= %x %x\n", cptr.cp[0], cword.c);
-		retval = (cptr.cp[0] == cword.c);
+		/* COMPLEX_MAPPINGS */
+		debug ("is= %x %x\n", map_readc(info, cptr.cp), cword.c);
+		retval = (map_readc(info, cptr.cp) == cword.c);
 		break;
 	case FLASH_CFI_16BIT:
-		debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
-		retval = (cptr.wp[0] == cword.w);
+		/* COMPLEX_MAPPINGS */
+		debug ("is= %4.4x %4.4x\n", map_readw(info, cptr.wp), cword.w);
+		retval = (map_readw(info, cptr.wp) == cword.w);
 		break;
 	case FLASH_CFI_32BIT:
-		debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
-		retval = (cptr.lp[0] == cword.l);
+		/* COMPLEX_MAPPINGS */
+		debug ("is= %8.8lx %8.8lx\n", map_readl(info, cptr.lp), cword.l);
+		retval = (map_readl(info, cptr.lp) == cword.l);
 		break;
 	case FLASH_CFI_64BIT:
 #ifdef DEBUG
@@ -995,12 +1085,14 @@
 			char str1[20];
 			char str2[20];
 
-			print_longlong (str1, cptr.llp[0]);
+			/* COMPLEX_MAPPINGS */
+			print_longlong (str1, map_readll(info, cptr.llp));
 			print_longlong (str2, cword.ll);
 			debug ("is= %s %s\n", str1, str2);
 		}
 #endif
-		retval = (cptr.llp[0] == cword.ll);
+		/* COMPLEX_MAPPINGS */
+		retval = (map_readll(info, cptr.llp) == cword.ll);
 		break;
 	default:
 		retval = 0;
@@ -1021,16 +1113,20 @@
 	flash_make_cmd (info, cmd, &cword);
 	switch (info->portwidth) {
 	case FLASH_CFI_8BIT:
-		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		/* COMPLEX_MAPPINGS */
+		retval = ((map_readc(info, cptr.cp) & cword.c) == cword.c);
 		break;
 	case FLASH_CFI_16BIT:
-		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		/* COMPLEX_MAPPINGS */
+		retval = ((map_readw(info, cptr.wp) & cword.w) == cword.w);
 		break;
 	case FLASH_CFI_32BIT:
-		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		/* COMPLEX_MAPPINGS */
+		retval = ((map_readl(info, cptr.lp) & cword.l) == cword.l);
 		break;
 	case FLASH_CFI_64BIT:
-		retval = ((cptr.llp[0] & cword.ll) == cword.ll);
+		/* COMPLEX_MAPPINGS */
+		retval = ((map_readll(info, cptr.llp) & cword.ll) == cword.ll);
 		break;
 	default:
 		retval = 0;
@@ -1051,17 +1147,21 @@
 	flash_make_cmd (info, cmd, &cword);
 	switch (info->portwidth) {
 	case FLASH_CFI_8BIT:
-		retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
+		/* COMPLEX_MAPPINGS */
+		retval = ((map_readc(info, cptr.cp) & cword.c) != (map_readc(info, cptr.cp) & cword.c));
 		break;
 	case FLASH_CFI_16BIT:
-		retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
+		/* COMPLEX_MAPPINGS */
+		retval = ((map_readw(info, cptr.wp) & cword.w) != (map_readw(info, cptr.wp) & cword.w));
 		break;
 	case FLASH_CFI_32BIT:
-		retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
+		/* COMPLEX_MAPPINGS */
+		retval = ((map_readl(info, cptr.lp) & cword.l) != (map_readl(info, cptr.lp) & cword.l));
 		break;
 	case FLASH_CFI_64BIT:
-		retval = ((cptr.llp[0] & cword.ll) !=
-			  (cptr.llp[0] & cword.ll));
+		/* COMPLEX_MAPPINGS */
+		retval = ((map_readll(info, cptr.llp) & cword.ll) !=
+			  (map_readll(info, cptr.llp) & cword.ll));
 		break;
 	default:
 		retval = 0;
@@ -1125,6 +1225,10 @@
 	info->legacy_unlock = 0;
 #endif
 
+#ifdef CFG_FLASH_CFI_AMD_RESET
+	info->cmd_reset = AMD_CMD_RESET;
+#endif
+
 	info->start[0] = base;
 
 	if (flash_detect_cfi (info)) {
@@ -1252,20 +1356,23 @@
 	ctladdr.cp = flash_make_addr (info, 0, 0);
 	cptr.cp = (uchar *) dest;
 
-
 	/* Check if Flash is (sufficiently) erased */
 	switch (info->portwidth) {
 	case FLASH_CFI_8BIT:
-		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		/* COMPLEX_MAPPINGS */
+		flag = ((map_readc(info, cptr.cp) & cword.c) == cword.c);
 		break;
 	case FLASH_CFI_16BIT:
-		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		/* COMPLEX_MAPPINGS */
+		flag = ((map_readw(info, cptr.wp) & cword.w) == cword.w);
 		break;
 	case FLASH_CFI_32BIT:
-		flag = ((cptr.lp[0] & cword.l) == cword.l);
+		/* COMPLEX_MAPPINGS */
+		flag = ((map_readl(info, cptr.lp) & cword.l) == cword.l);
 		break;
 	case FLASH_CFI_64BIT:
-		flag = ((cptr.llp[0] & cword.ll) == cword.ll);
+		/* COMPLEX_MAPPINGS */
+		flag = ((map_readll(info, cptr.llp) & cword.ll) == cword.ll);
 		break;
 	default:
 		return 2;
@@ -1291,16 +1398,20 @@
 
 	switch (info->portwidth) {
 	case FLASH_CFI_8BIT:
-		cptr.cp[0] = cword.c;
+		/* COMPLEX_MAPPINGS */
+		map_writec(info, cptr.cp, cword.c);
 		break;
 	case FLASH_CFI_16BIT:
-		cptr.wp[0] = cword.w;
+		/* COMPLEX_MAPPINGS */
+		map_writew(info, cptr.wp, cword.w);
 		break;
 	case FLASH_CFI_32BIT:
-		cptr.lp[0] = cword.l;
+		/* COMPLEX_MAPPINGS */
+		map_writel(info, cptr.lp, cword.l);
 		break;
 	case FLASH_CFI_64BIT:
-		cptr.llp[0] = cword.ll;
+		/* COMPLEX_MAPPINGS */
+		map_writell(info, cptr.llp, cword.ll);
 		break;
 	}
 
@@ -1355,16 +1466,24 @@
 			while (cnt-- > 0) {
 				switch (info->portwidth) {
 				case FLASH_CFI_8BIT:
-					*dst.cp++ = *src.cp++;
+					map_writec(info, dst.cp, *src.cp);
+					dst.cp++;
+					src.cp++;
 					break;
 				case FLASH_CFI_16BIT:
-					*dst.wp++ = *src.wp++;
+					map_writew(info, dst.wp, __cpu_to_le16(*src.wp));
+					dst.wp++;
+					src.wp++;
 					break;
 				case FLASH_CFI_32BIT:
-					*dst.lp++ = *src.lp++;
+					map_writel(info, dst.lp, *src.lp);
+					dst.lp++;
+					src.lp++;
 					break;
 				case FLASH_CFI_64BIT:
-					*dst.llp++ = *src.llp++;
+					map_writell(info, dst.llp, *src.llp);
+					dst.llp++;
+					src.llp++;
 					break;
 				default:
 					return ERR_INVAL;
@@ -1392,22 +1511,38 @@
 		case FLASH_CFI_8BIT:
 			cnt = len;
 			flash_write_cmd (info, sector, 0,  (uchar) cnt - 1);
-			while (cnt-- > 0) *dst.cp++ = *src.cp++;
+			while (cnt-- > 0) {
+				map_writec(info, dst.cp, *src.cp);
+				dst.cp++;
+				src.cp++;
+			}
 			break;
 		case FLASH_CFI_16BIT:
 			cnt = len >> 1;
 			flash_write_cmd (info, sector, 0,  (uchar) cnt - 1);
-			while (cnt-- > 0) *dst.wp++ = *src.wp++;
+			while (cnt-- > 0) {
+				map_writew(info, dst.wp, __cpu_to_le16(*src.wp));
+				dst.wp++;
+				src.wp++;
+			}
 			break;
 		case FLASH_CFI_32BIT:
 			cnt = len >> 2;
 			flash_write_cmd (info, sector, 0,  (uchar) cnt - 1);
-			while (cnt-- > 0) *dst.lp++ = *src.lp++;
+			while (cnt-- > 0) {
+				map_writel(info, dst.lp, *src.lp);
+				dst.lp++;
+				src.lp++;
+			}
 			break;
 		case FLASH_CFI_64BIT:
 			cnt = len >> 3;
 			flash_write_cmd (info, sector, 0,  (uchar) cnt - 1);
-			while (cnt-- > 0) *dst.llp++ = *src.llp++;
+			while (cnt-- > 0) {
+				map_writell(info, dst.llp, *src.llp);
+				dst.llp++;
+				src.llp++;
+			}
 			break;
 		default:
 			return ERR_INVAL;

drivers/comcerto1000_gem.h

diff --git a/drivers/comcerto1000_gem.h b/drivers/comcerto1000_gem.h
new file mode 100644
index 0000000..eeb97ce
--- /dev/null
+++ b/drivers/comcerto1000_gem.h
@@ -0,0 +1,345 @@
+#ifndef __COMCERTO_GEM1000_H__
+#define __COMCERTO_GEM1000_H__
+
+
+/* Specify the default PCLK divisor for generating MDC.  This simply defines
+ * which of the divisor control bits are active.  By default, the clock
+ * division is 32.
+ */
+#define GEM_DEF_PCLK_DIV (MDC_DIV_96)
+
+////////////////////////////////////////////////////////////
+//      GEMAC IP wrapper                                                                                    //
+////////////////////////////////////////////////////////////
+
+#define GEM_SCH_CTL			0x8004
+#define	GEM_SCH_PKT_QUEUED		0x8008
+
+#define GEM_IP				0xE000
+#define GEM_CFG				0xF000
+#define GEM_MBIST			0xF004
+#define GEM_SENSE_AMP_DELAY_ADJ		0xF008
+#define GEM_DELAY_ELEMENT_CTRL		0xF00C
+#define ADMITTANCE			0x4000
+
+#define GEM_CONF_MODE_SEL_PIN		(0 << 0)
+#define GEM_CONF_MODE_SEL_GEM		(1 << 0)
+
+#define GEM_CONF_MODE_GEM_MASK		(7 << 1)
+#define GEM_CONF_MODE_GEM_RGMII		(0 << 1)
+#define GEM_CONF_MODE_GEM_RMII		(1 << 1)
+#define GEM_CONF_MODE_GEM_MII		(2 << 1)
+#define GEM_CONF_MODE_GEM_GMII		(3 << 1)
+
+#define GEM_CONF_MODE_PIN_MASK		(7 << 4)
+#define GEM_CONF_MODE_PIN_RGMII		(0 << 4)
+#define GEM_CONF_MODE_PIN_RMII		(1 << 4)
+#define GEM_CONF_MODE_PIN_MII		(2 << 4)
+#define GEM_CONF_MODE_PIN_GMII		(3 << 4)
+
+#define GEM_CONF_DUPLEX_SEL_PHY		(0 << 8)
+#define GEM_CONF_DUPLEX_SEL_GEM		(1 << 8)
+#define GEM_CONF_DUPLEX_GEM_HALF	(0 << 9)
+#define GEM_CONF_DUPLEX_GEM_FULL	(1 << 9)
+#define GEM_CONF_DUPLEX_PHY_HALF	(0 << 10)
+#define GEM_CONF_DUPLEX_PHY_FULL	(1 << 10)
+#define GEM_CONF_SPEED_SEL_PHY		(0 << 11)
+#define GEM_CONF_SPEED_SEL_GEM		(1 << 11)
+
+#define GEM_CONF_SPEED_MASK		(3 << 12)
+#define GEM_CONF_SPEED_GEM_10M		(0 << 12)
+#define GEM_CONF_SPEED_GEM_100M		(1 << 12)
+#define GEM_CONF_SPEED_GEM_1G		(2 << 12)
+#define GEM_CONF_SPEED_PHY_10M		(0 << 14)
+#define GEM_CONF_SPEED_PHY_100M		(1 << 14)
+#define GEM_CONF_SPEED_PHY_1G		(2 << 14)
+
+#define GEM_CONF_PHY_LINK_DOWN		(0 << 16)
+#define GEM_CONF_PHY_LINK_UP		(1 << 16)
+#define GEM_CONF_GEM_LOOPBACK		(1 << 17)
+
+
+/* Define some bit positions for registers. */
+
+/* Bit positions for network control register */
+#define GEM_READ_SNAP       (1<<14)	/* Read snapshot register */
+#define GEM_TAKE_SNAP       (1<<13)	/* Take a snapshot */
+#define GEM_TX_0Q_PAUSE     (1<<12)	/* Transmit zero quantum pause frame */
+#define GEM_TX_PAUSE        (1<<11)	/* Transmit pause frame */
+#define GEM_TX_HALT         (1<<10)	/* Halt transmission after curr frame */
+#define GEM_TX_START        (1<<9)	/* Start tx (tx_go) */
+#define GEM_STATS_WR_EN     (1<<7)	/* Enable writing to stat registers */
+#define GEM_STATS_INC       (1<<6)	/* Increment statistic registers */
+#define GEM_STATS_CLR       (1<<5)	/* Clear statistic registers */
+#define GEM_MDIO_EN         (1<<4)	/* Enable MDIO port */
+#define GEM_TX_EN           (1<<3)	/* Enable transmit circuits */
+#define GEM_RX_EN           (1<<2)	/* Enable receive circuits */
+#define GEM_LB_MAC          (1<<1)	/* Perform local loopback at MAC */
+#define GEM_LB_PHY          (1<<0)	/* Perform ext loopback through PHY */
+
+/* Bit positions for network configuration register */
+#define GEM_RX_NO_PAUSE     (1<<23)	/* Do not copy pause frames to memory */
+#define GEM_MDC_DIV2        (1<<20)	/* PCLK divisor for MDC, bit 2 */
+#define GEM_MDC_DIV1        (1<<19)	/* PCLK divisor for MDC, bit 1 */
+#define GEM_MDC_DIV0        (1<<18)	/* PCLK divisor for MDC, bit 0 */
+#define GEM_RX_NO_FCS       (1<<17)	/* Discard FCS from received frames. */
+#define GEM_RX_LEN_CHK      (1<<16)	/* Receive length check. */
+#define GEM_RX_PAUSE_EN     (1<<13)	/* Enable pause reception */
+#define GEM_RETRY_TEST      (1<<12)	/* Retry test for speeding up debug */
+#define GEM_PCS_SEL         (1<<11)	/* Select PCS */
+#define GEM_EAM_EN          (1<<9)	/* External address match enable */
+#define GEM_FRAME_1536      (1<<8)	/* Enable 1536 byte frames reception */
+#define GEM_UNICAST_EN      (1<<7)	/* Receive unicast hash frames */
+#define GEM_MULTICAST_EN    (1<<6)	/* Receive multicast hash frames */
+#define GEM_NO_BROADCAST    (1<<5)	/* Do not receive broadcast frames */
+#define GEM_COPY_ALL        (1<<4)	/* Copy all frames */
+#define GEM_RX_JUMBO        (1<<3)	/* Allow jumbo frame reception */
+#define GEM_VLAN_ONLY       (1<<2)	/* Receive only VLAN frames */
+
+/* Bit positions for network status register */
+#define GEM_PHY_IDLE        (1<<2)	/* PHY management is idle */
+#define GEM_MDIO_IN         (1<<1)	/* Status of mdio_in pin */
+#define GEM_LINK_STATUS     (1<<0)	/* Status of link pin */
+
+/* Bit positions for transmit status register */
+#define GEM_TX_HRESP        (1<<8)	/* Transmit hresp not OK */
+#define GEM_LATE_COL        (1<<7)	/* Late collision */
+#define GEM_TX_URUN         (1<<6)	/* Transmit underrun occurred */
+#define GEM_TX_COMPLETE     (1<<5)	/* Transmit completed OK */
+#define GEM_TX_BUF_EXH      (1<<4)	/* Transmit buffs exhausted mid frame */
+#define GEM_TX_GO           (1<<3)	/* Status of tx_go internal variable */
+#define GEM_TX_RETRY_EXC    (1<<2)	/* Retry limit exceeded */
+#define GEM_TX_COL          (1<<1)	/* Collision occurred during frame tx */
+#define GEM_TX_USED         (1<<0)	/* Used bit read in tx buffer */
+
+/* Bit positions for receive status register */
+#define GEM_RX_HRESP        (1<<3)	/* Receive hresp not OK */
+#define GEM_RX_ORUN         (1<<2)	/* Receive overrun occurred */
+#define GEM_RX_DONE         (1<<1)	/* Frame successfully received */
+#define GEM_RX_BUF_USED     (1<<0)	/* Receive buffer used bit read */
+
+/* Bit positions for interrupts */
+#define GEM_IRQ_PCS_AN      (1<<16)	/* PCS autonegotiation complete */
+#define GEM_IRQ_EXT_INT     (1<<15)	/* External interrupt pin triggered */
+#define GEM_IRQ_PAUSE_TX    (1<<14)	/* Pause frame transmitted */
+#define GEM_IRQ_PAUSE_0     (1<<13)	/* Pause time has reached zero */
+#define GEM_IRQ_PAUSE_RX    (1<<12)	/* Pause frame received */
+#define GEM_IRQ_HRESP       (1<<11)	/* hresp not ok */
+#define GEM_IRQ_RX_ORUN     (1<<10)	/* Receive overrun occurred */
+#define GEM_IRQ_PCS_LINK    (1<<9)	/* Status of PCS link changed */
+#define GEM_IRQ_TX_DONE     (1<<7)	/* Frame transmitted ok */
+#define GEM_IRQ_TX_ERROR    (1<<6)	/* Transmit err occurred or no buffers */
+#define GEM_IRQ_RETRY_EXC   (1<<5)	/* Retry limit exceeded */
+#define GEM_IRQ_TX_URUN     (1<<4)	/* Transmit underrun occurred */
+#define GEM_IRQ_TX_USED     (1<<3)	/* Tx buffer used bit read */
+#define GEM_IRQ_RX_USED     (1<<2)	/* Rx buffer used bit read */
+#define GEM_IRQ_RX_DONE     (1<<1)	/* Frame received ok */
+#define GEM_IRQ_MAN_DONE    (1<<0)	/* PHY management operation complete */
+#define GEM_IRQ_ALL         (0xFFFFFFFF)	/* Everything! */
+
+/* Revision ID Register */
+#define GEM_REV_ID_MODEL_MASK   (0x000F0000)	/* Model ID */
+#define GEM_REV_ID_MODEL_BASE   (16)	/* For Shifting */
+#define GEM_REV_ID_REG_MODEL    (0x00020000)	/* GEM module ID */
+#define GEM_REV_ID_REV_MASK     (0x0000FFFF)	/* Revision ID */
+
+/* Define some memory offsets for easier direct access to memory map. */
+#define GEM_NET_CONTROL         (0x00)
+#define GEM_NET_CONFIG          (0x04)
+#define GEM_NET_STATUS          (0x08)
+#define GEM_USER_IO             (0x0C)
+#define GEM_DMA_CONFIG		(0x10)
+#define GEM_TX_STATUS           (0x14)
+#define GEM_RX_QPTR             (0x18)
+#define GEM_RX_OFFSET           (0x1C)
+#define GEM_RX_STATUS           (0x20)
+#define GEM_IRQ_STATUS          (0x24)
+#define GEM_IRQ_ENABLE          (0x28)
+#define GEM_IRQ_DISABLE         (0x2C)
+#define GEM_IRQ_MASK            (0x30)
+#define GEM_PHY_MAN             (0x34)
+#define GEM_RX_PAUSE_TIME       (0x38)
+#define GEM_TX_PAUSE_QUANT      (0x3C)
+
+#define GEM_HASH_BOT            (0x80)
+#define GEM_HASH_TOP            (0x84)
+#define GEM_LADDR1_BOT          (0x88)
+#define GEM_LADDR1_TOP          (0x8C)
+#define GEM_LADDR2_BOT          (0x90)
+#define GEM_LADDR2_TOP          (0x94)
+#define GEM_LADDR3_BOT          (0x98)
+#define GEM_LADDR3_TOP          (0x9C)
+#define GEM_LADDR4_BOT          (0xA0)
+#define GEM_LADDR4_TOP          (0xA4)
+#define GEM_ID_CHECK1           (0x320)
+#define GEM_ID_CHECK2           (0x324)
+#define GEM_ID_CHECK3           (0x328)
+#define GEM_ID_CHECK4           (0x32C)
+#define GEM_REV_ID              (0xFC)
+
+#define GEM_OCT_TX_BOT          (0x100)
+#define GEM_OCT_TX_TOP          (0x104)
+#define GEM_STATS_FRAMES_TX     (0x108)
+#define GEM_BROADCAST_TX        (0x10C)
+#define GEM_MULTICAST_TX        (0x110)
+#define GEM_STATS_PAUSE_TX      (0x114)
+#define GEM_FRAME64_TX          (0x118)
+#define GEM_FRAME65_TX          (0x11C)
+#define GEM_FRAME128_TX         (0x120)
+#define GEM_FRAME256_TX         (0x124)
+#define GEM_FRAME512_TX         (0x128)
+#define GEM_FRAME1024_TX        (0x12C)
+#define GEM_FRAME1519_TX        (0x130)
+#define GEM_STATS_TX_URUN       (0x134)
+#define GEM_STATS_SINGLE_COL    (0x138)
+#define GEM_STATS_MULTI_COL     (0x13C)
+#define GEM_STATS_EXCESS_COL    (0x140)
+#define GEM_STATS_LATE_COL      (0x144)
+#define GEM_STATS_DEF_TX        (0x148)
+#define GEM_STATS_CRS_ERRORS    (0x14C)
+#define GEM_OCT_RX_BOT          (0x150)
+#define GEM_OCT_RX_TOP          (0x154)
+#define GEM_STATS_FRAMES_RX     (0x158)
+#define GEM_BROADCAST_RX        (0x15C)
+#define GEM_MULTICAST_RX        (0x160)
+#define GEM_STATS_PAUSE_RX      (0x164)
+#define GEM_FRAME64_RX          (0x168)
+#define GEM_FRAME65_RX          (0x16C)
+#define GEM_FRAME128_RX         (0x170)
+#define GEM_FRAME256_RX         (0x174)
+#define GEM_FRAME512_RX         (0x178)
+#define GEM_FRAME1024_RX        (0x17C)
+#define GEM_FRAME1519_RX        (0x180)
+#define GEM_STATS_USIZE_FRAMES  (0x184)
+#define GEM_STATS_EXCESS_LEN    (0x188)
+#define GEM_STATS_JABBERS       (0x18C)
+#define GEM_STATS_FCS_ERRORS    (0x190)
+#define GEM_STATS_LENGTH_ERRORS (0x194)
+#define GEM_STATS_RX_SYM_ERR    (0x198)
+#define GEM_STATS_ALIGN_ERRORS  (0x19C)
+#define GEM_STATS_RX_RES_ERR    (0x1a0)
+#define GEM_STATS_RX_ORUN       (0x1a4)
+
+#define GEM_REG_TOP             (0x23C)
+
+#define	GEM_QUEUE_BASE0		(0x300)
+#define	GEM_QUEUE_BASE1		(0x304)
+#define	GEM_QUEUE_BASE2		(0x308)
+#define	GEM_QUEUE_BASE3		(0x30C)
+#define	GEM_QUEUE_BASE4		(0x310)
+#define	GEM_QUEUE_BASE5		(0x314)
+#define	GEM_QUEUE_BASE6		(0x318)
+#define	GEM_QUEUE_BASE7		(0x31C)
+
+#define GEM_ID_CHECK5           (0x320)
+#define GEM_ID_CHECK6           (0x324)
+#define GEM_ID_CHECK7           (0x328)
+#define GEM_ID_CHECK8           (0x32C)
+ 
+// memory offsets for admittance registers
+#define ADM_CFG			(0x00C)
+
+struct gemac_info_struct {
+	unsigned int baseaddr;
+	unsigned int phyaddr;
+	unsigned int gemacconfig;
+	u32 mode;
+	u32 phyflags;		// to indicate if gigabit supported or not
+	unsigned int phyregidx;
+};
+
+struct rx_desc {
+	volatile u32 data;
+	volatile u32 status;
+	volatile u32 extstatus;
+	u32 pad;
+};
+//gemac rx controls
+// Wrap flag - marks last descriptor in a queue when set
+// goes to the status word (offset 0x4)
+#define GEMRX_WRAP 	(1<<28)
+// Ownership flag - when 0 gem can use the descriptor
+// goes to the extended status word (offset 0x8)
+#define GEMRX_OWN	(1<<15)
+
+// gemac rx status
+#define RX_STA_BCAST		(1UL<<31)
+#define RX_STA_MCAST		(1<<30)
+#define RX_STA_UM		(1<<29)
+#define RX_MAC_MATCH_FLAG 	(0x4<<25)
+#define RX_MAC_MATCH_NUM_MASK	(0x3<<25)
+#define RX_MAC_MATCH_POS 	25
+#define RX_INT 			(1<<24)
+#define RX_IPSEC_OUT		(1<<23)
+#define RX_IPSEC_IN	 	(1<<22)
+#define RX_STA_VLAN 		(1<<21)
+#define RX_STA_VLAN_802p 	(1<<20)
+#define RX_STA_VLAN_PRI_MASK	(7<<17)
+#define RX_STA_VLAN_PRI_POS	17
+#define RX_STA_VLAN_CFI		(1<<16)
+#define RX_STA_SOF		(1<<15)
+#define RX_STA_EOF		(1<<14)
+#define RX_STA_PACKET		(RX_STA_SOF|RX_STA_EOF)
+#define RX_STA_CRCERR		(1<<13)
+#define RX_STA_LEN_MASK		0x1fff
+#define RX_STA_LEN_POS		0
+#define	RX_CHECK_ERROR		RX_STA_CRCERR
+// gemac rx extended status(word2)
+#define RX_STA_L4OFF_MASK	(0xff<<24)
+#define RX_STA_L4OFF_POS	24
+#define RX_STA_L3OFF_MASK	(0xff<<16)
+#define RX_STA_L3OFF_POS	16
+
+#define RX_STA_L3_CKSUM		(1<<11)
+#define RX_STA_L3_GOOD		(1<<12)
+#define RX_STA_L4_CKSUM		(1<<13)
+#define RX_STA_L4_GOOD		(1<<14)
+
+#define RX_STA_TCP		(1<<9)
+#define RX_STA_UDP		(1<<8)
+#define RX_STA_IPV6		(1<<7)
+#define RX_STA_IPV4		(1<<6)
+#define RX_STA_PPPOE		(1<<5)
+#define RX_STA_WILLHANDLE	(RX_STA_IPV6 | RX_STA_IPV4)
+#define RX_STA_QinQ		(1<<4)
+#define RX_STA_TYPEID_MATCH_FLAG (0x8 << 0)
+#define RX_STA_TYPEID		(0x7 << 0)
+#define RX_STA_TYPEID_POS	0
+
+struct tx_desc {
+	volatile u32 data;
+	volatile u32 ctl;
+};
+
+#define TX_DESC_WORD1_USED	(BIT31)
+#define TX_DESC_WORD1_WRAP	(BIT30)
+#define TX_DESC_WORD1_INT	(BIT29)
+#define TX_DESC_WORD1_ERR1	(BIT28)
+#define TX_DESC_WORD1_ERR2	(BIT27)
+#define TX_DESC_WORD1_TXCSUM_MASK	(BIT26|BIT25)
+#define	TX_DESC_CSUM(a)		((a&(TX_DESC_WORD1_TXCSUM_MASK))<<25)
+#define TX_DESC_WORD1_FCS	(BIT24)
+#define TX_DESC_WORD1_LAST	(BIT15)
+#define TX_DESC_WORD1_POOLB	(BIT14)
+#define TX_DESC_WORD1_BUFRET	(BIT13)
+#define TX_DESC_WORD1_LEGTH_MASK (0x1FFF)
+
+/* This is a structure that will be passed and used for all HAL operations, it
+ * consists of pointers to the various MAC structures such as the MAC register
+ * block and the first descriptor element for the rx and tx buffer queues.
+ * Other internal variables declared for use in function calls and to keep track
+ * of where things are.
+ */
+struct gemac_dev {
+	void *registers;	/* Pointer to the MAC address space. */
+	void *phyregisters;	/* Pointer to the MAC address space controlling the phy */
+
+	void *baseaddr;
+	struct phy_info *phyinfo;
+	u32 phyaddr;
+	u32 mode;
+	u32 phyflags;
+	struct eth_device *dev;
+};
+
+#endif

drivers/comcerto100_gem.h

diff --git a/drivers/comcerto100_gem.h b/drivers/comcerto100_gem.h
new file mode 100644
index 0000000..a6d9b48
--- /dev/null
+++ b/drivers/comcerto100_gem.h
@@ -0,0 +1,352 @@
+#ifndef __COMCERTO_GEM100_H__
+#define __COMCERTO_GEM100_H__
+
+#include <asm/arch/idma.h>
+
+#define GEM_DEF_PCLK_DIV (MDC_DIV_32)
+
+
+////////////////////////////////////////////////////////////
+//      GEMAC IP wrapper                                                                                    //
+////////////////////////////////////////////////////////////
+#define GEM_ARM_FIFO_CTRL		0x0000
+#define GEM_ARM_TX_FIFO_SIZE		0x0014
+#define GEM_ARM_RX_FIFO_SIZE		0x0024
+#define GEM_ARM_RX_FIFO_HIGH		0x0028
+#define GEM_ARM_RX_FIFO_LOW		0x002C
+
+#define GEM_FIFO_CTRL			0xD000
+#define GEM_RX_FIFO_HIGH		0xD024
+#define GEM_RX_FIFO_LOW			0xD028
+#define GEM_IP				0xE000
+#define GEM_CFG				0xF000
+#define GEM_TX_CTRL			0xF004
+#define GEM_TX_COLL			0xF008
+#define GEM_RX_CTRL			0xF010
+#define GEM_RX_STAT_PKTSIZE		0xF014
+#define GEM_RX_STAT_FIFODEPTH		0xF018
+#define GEM_RX_STAT_FIFODATA		0xF01C
+
+#define	GEM_FIFO_CTRL_TXFF_EN		(1 << 0)
+#define	GEM_FIFO_CTRL_HBTXRQ_EN		(1 << 1)
+#define	GEM_FIFO_CTRL_RXFF_EN		(1 << 3)
+#define	GEM_FIFO_CTRL_HBRXRQ_EN		(1 << 4)
+#define	GEM_FIFO_CTRL_TXCP_INH		(1 << 5)
+#define	GEM_FIFO_CTRL_RXCMPLTIE		(1 << 11)
+
+#define GEM_CONF_MODE_SEL_PIN		(0 << 0)
+#define GEM_CONF_MODE_SEL_GEM		(1 << 0)
+#define GEM_CONF_MODE_GEM_MASK		(7 << 1)
+#define GEM_CONF_MODE_GEM_MII		(0 << 1)
+#define GEM_CONF_MODE_GEM_GMII		(1 << 1)
+#define GEM_CONF_MODE_GEM_RMII		(2 << 1)
+#define GEM_CONF_MODE_GEM_RGMII		(3 << 1)
+#define GEM_CONF_MODE_GEM_SMII		(6 << 1)
+
+#define GEM_CONF_MODE_PIN_MASK		(7 << 4)
+#define GEM_CONF_MODE_PIN_MII		(0 << 4)
+#define GEM_CONF_MODE_PIN_GMII		(1 << 4)
+#define GEM_CONF_MODE_PIN_RMII		(2 << 4)
+#define GEM_CONF_MODE_PIN_RGMII		(3 << 4)
+#define GEM_CONF_MODE_PIN_SMII		(6 << 4)
+
+#define GEM_CONF_DUPLEX_SEL_PHY		(0 << 8)
+#define GEM_CONF_DUPLEX_SEL_GEM		(1 << 8)
+#define GEM_CONF_DUPLEX_GEM_HALF	(0 << 9)
+#define GEM_CONF_DUPLEX_GEM_FULL	(1 << 9)
+#define GEM_CONF_DUPLEX_PHY_HALF	(0 << 10)
+#define GEM_CONF_DUPLEX_PHY_FULL	(1 << 10)
+#define GEM_CONF_SPEED_SEL_PHY		(0 << 11)
+#define GEM_CONF_SPEED_SEL_GEM		(1 << 11)
+#define GEM_CONF_SPEED_MASK		(3 << 12)
+#define GEM_CONF_SPEED_GEM_10M		(0 << 12)
+#define GEM_CONF_SPEED_GEM_100M		(1 << 12)
+#define GEM_CONF_SPEED_GEM_1G		(2 << 12)
+#define GEM_CONF_SPEED_PHY_10M		(0 << 14)
+#define GEM_CONF_SPEED_PHY_100M		(1 << 14)
+#define GEM_CONF_SPEED_PHY_1G		(2 << 14)
+#define GEM_CONF_PHY_LINK_DOWN		(0 << 16)
+#define GEM_CONF_PHY_LINK_UP		(1 << 16)
+#define GEM_CONF_GEM_LOOPBACK		(1 << 17)
+
+#define GEM_TXCTRL_DMAIF_EN		(1 << 0)
+#define GEM_TXCTRL_CRC_EN		(1 << 1)
+#define GEM_TXCTRL_RETR_EN		(1 << 2)
+#define GEM_TXCTRL_TX_STATE		0xf0000
+
+#define GEM_RXCTRL_DMAIF_EN		(1 << 0)
+#define GEM_RXCTRL_RX_STATE		0xf0000
+
+// Host fifo control bits
+#define ARM_FIFO_RXDREQWE		(1 << 2)
+#define ARM_FIFO_TXDREQRE		(1 << 3)
+#define ARM_FIFO_TXFF_RES		(1 << 12)
+#define ARM_FIFO_RXFF_RES		(1 << 13)
+#define ARM_FIFO_RXCP_INH		(1 << 15)
+
+/* Define some bit positions for registers. */
+
+/* Bit positions for network control register */
+#define GEM_READ_SNAP       (1<<14)	/* Read snapshot register */
+#define GEM_TAKE_SNAP       (1<<13)	/* Take a snapshot */
+#define GEM_TX_0Q_PAUSE     (1<<12)	/* Transmit zero quantum pause frame */
+#define GEM_TX_PAUSE        (1<<11)	/* Transmit pause frame */
+#define GEM_TX_HALT         (1<<10)	/* Halt transmission after curr frame */
+#define GEM_TX_START        (1<<9)	/* Start tx (tx_go) */
+#define GEM_STATS_WR_EN     (1<<7)	/* Enable writing to stat registers */
+#define GEM_STATS_INC       (1<<6)	/* Increment statistic registers */
+#define GEM_STATS_CLR       (1<<5)	/* Clear statistic registers */
+#define GEM_MDIO_EN         (1<<4)	/* Enable MDIO port */
+#define GEM_TX_EN           (1<<3)	/* Enable transmit circuits */
+#define GEM_RX_EN           (1<<2)	/* Enable receive circuits */
+#define GEM_LB_MAC          (1<<1)	/* Perform local loopback at MAC */
+#define GEM_LB_PHY          (1<<0)	/* Perform ext loopback through PHY */
+
+/* Bit positions for network configuration register */
+#define GEM_RX_NO_PAUSE     (1<<23)	/* Do not copy pause frames to memory */
+#define GEM_AHB_WIDTH1      (1<<22)	/* Bit 1 for defining AHB width */
+#define GEM_AHB_WIDTH0      (1<<21)	/* Bit 0 for defining AHB width */
+#define GEM_MDC_DIV2        (1<<20)	/* PCLK divisor for MDC, bit 2 */
+#define GEM_MDC_DIV1        (1<<19)	/* PCLK divisor for MDC, bit 1 */
+#define GEM_MDC_DIV0        (1<<18)	/* PCLK divisor for MDC, bit 0 */
+#define GEM_RX_NO_FCS       (1<<17)	/* Discard FCS from received frames. */
+#define GEM_RX_LEN_CHK      (1<<16)	/* Receive length check. */
+#define GEM_RX_OFFSET_BASE  14	/* Pos of LSB for rx buffer offsets. */
+#define GEM_RX_OFFSET1      (1<<(GEM_RX_OFFSET_BASE + 1))	/* RX offset bit 1 */
+#define GEM_RX_OFFSET0      (1<<GEM_RX_OFFSET_BASE)	/* RX offset bit 0 */
+#define GEM_RX_PAUSE_EN     (1<<13)	/* Enable pause reception */
+#define GEM_RETRY_TEST      (1<<12)	/* Retry test for speeding up debug */
+#define GEM_PCS_SEL         (1<<11)	/* Select PCS */
+#define GEM_GIG_MODE        (1<<10)	/* Gigabit mode enable */
+#define GEM_EAM_EN          (1<<9)	/* External address match enable */
+#define GEM_FRAME_1536      (1<<8)	/* Enable 1536 byte frames reception */
+#define GEM_UNICAST_EN      (1<<7)	/* Receive unicast hash frames */
+#define GEM_MULTICAST_EN    (1<<6)	/* Receive multicast hash frames */
+#define GEM_NO_BROADCAST    (1<<5)	/* Do not receive broadcast frames */
+#define GEM_COPY_ALL        (1<<4)	/* Copy all frames */
+#define GEM_RX_JUMBO        (1<<3)	/* Allow jumbo frame reception */
+#define GEM_VLAN_ONLY       (1<<2)	/* Receive only VLAN frames */
+#define GEM_FULL_DUPLEX     (1<<1)	/* Enable full duplex */
+#define GEM_SPEED_100       (1<<0)	/* Set to 100Mb mode */
+
+/* Bit positions for network status register */
+#define GEM_PHY_IDLE        (1<<2)	/* PHY management is idle */
+#define GEM_MDIO_IN         (1<<1)	/* Status of mdio_in pin */
+#define GEM_LINK_STATUS     (1<<0)	/* Status of link pin */
+
+/* Bit positions for transmit status register */
+#define GEM_TX_HRESP        (1<<8)	/* Transmit hresp not OK */
+#define GEM_LATE_COL        (1<<7)	/* Late collision */
+#define GEM_TX_URUN         (1<<6)	/* Transmit underrun occurred */
+#define GEM_TX_COMPLETE     (1<<5)	/* Transmit completed OK */
+#define GEM_TX_BUF_EXH      (1<<4)	/* Transmit buffs exhausted mid frame */
+#define GEM_TX_GO           (1<<3)	/* Status of tx_go internal variable */
+#define GEM_TX_RETRY_EXC    (1<<2)	/* Retry limit exceeded */
+#define GEM_TX_COL          (1<<1)	/* Collision occurred during frame tx */
+#define GEM_TX_USED         (1<<0)	/* Used bit read in tx buffer */
+
+/* Bit positions for receive status register */
+#define GEM_RX_HRESP        (1<<3)	/* Receive hresp not OK */
+#define GEM_RX_ORUN         (1<<2)	/* Receive overrun occurred */
+#define GEM_RX_DONE         (1<<1)	/* Frame successfully received */
+#define GEM_RX_BUF_USED     (1<<0)	/* Receive buffer used bit read */
+
+/* Bit positions for interrupts */
+#define GEM_IRQ_PCS_AN      (1<<16)	/* PCS autonegotiation complete */
+#define GEM_IRQ_EXT_INT     (1<<15)	/* External interrupt pin triggered */
+#define GEM_IRQ_PAUSE_TX    (1<<14)	/* Pause frame transmitted */
+#define GEM_IRQ_PAUSE_0     (1<<13)	/* Pause time has reached zero */
+#define GEM_IRQ_PAUSE_RX    (1<<12)	/* Pause frame received */
+#define GEM_IRQ_HRESP       (1<<11)	/* hresp not ok */
+#define GEM_IRQ_RX_ORUN     (1<<10)	/* Receive overrun occurred */
+#define GEM_IRQ_PCS_LINK    (1<<9)	/* Status of PCS link changed */
+#define GEM_IRQ_TX_DONE     (1<<7)	/* Frame transmitted ok */
+#define GEM_IRQ_TX_ERROR    (1<<6)	/* Transmit err occurred or no buffers */
+#define GEM_IRQ_RETRY_EXC   (1<<5)	/* Retry limit exceeded */
+#define GEM_IRQ_TX_URUN     (1<<4)	/* Transmit underrun occurred */
+#define GEM_IRQ_TX_USED     (1<<3)	/* Tx buffer used bit read */
+#define GEM_IRQ_RX_USED     (1<<2)	/* Rx buffer used bit read */
+#define GEM_IRQ_RX_DONE     (1<<1)	/* Frame received ok */
+#define GEM_IRQ_MAN_DONE    (1<<0)	/* PHY management operation complete */
+#define GEM_IRQ_ALL         (0xFFFFFFFF)	/* Everything! */
+
+/* Transmit buffer descriptor status words bit positions. */
+#define GEM_TBQE_USED       (1<<31)	/* Used bit. */
+#define GEM_TBQE_WRAP       (1<<30)	/* Wrap bit */
+#define GEM_TBQE_RETRY_EXC  (1<<29)	/* Retry limit exceeded. */
+#define GEM_TBQE_URUN       (1<<28)	/* Transmit underrun occurred. */
+#define GEM_TBQE_BUF_EXH    (1<<27)	/* Buffers exhausted mid frame. */
+#define GEM_TBQE_LATE_COL   (1<<26)	/* Late collision. */
+#define GEM_TBQE_NO_CRC     (1<<16)	/* No CRC */
+#define GEM_TBQE_LAST_BUF   (1<<15)	/* Last buffer */
+#define GEM_TBQE_LEN_MASK   (0x3FFF)	/* Mask for length field */
+#define GEM_TX_MAX_LEN      (0x3FFF)	/* Maximum transmit length value */
+#define GEM_TBQE_DUMMY      (0x8000BFFF)	/* Dummy value to check for free buffer */
+/* Receive buffer descriptor status words bit positions. */
+#define GEM_RBQE_BROADCAST  (1<<31)	/* Broadcast frame */
+#define GEM_RBQE_MULTICAST  (1<<30)	/* Multicast hashed frame */
+#define GEM_RBQE_UNICAST    (1<<29)	/* Unicast hashed frame */
+#define GEM_RBQE_EXT_ADDR   (1<<28)	/* External address match */
+#define GEM_RBQE_SPEC_MATCH (1<<27)	/* Specific address matched */
+#define GEM_RBQE_SPEC_BASE  (25)	/* Pos for base of specific match */
+#define GEM_RBQE_SPEC_MAT1  (1<<(RBQE_SPEC_BASE + 1))
+#define GEM_RBQE_SPEC_MAT0  (1<<RBQE_SPEC_BASE)
+#define GEM_RBQE_TYPE_MATCH (1<<24)	/* Type ID matched */
+#define GEM_RBQE_TYPE_BASE  (22)	/* Position for base of type id match */
+#define GEM_RBQE_TYPE_MAT1  (1<<(RBQE_TYPE_BASE + 1))
+#define GEM_RBQE_TYPE_MAT0  (1<<RBQE_TYPE_BASE)
+#define GEM_RBQE_VLAN       (1<<21)	/* VLAN tagged */
+#define GEM_RBQE_PRIORITY   (1<<20)	/* Priority tagged */
+#define GEM_RBQE_VLAN_BASE  (17)	/* Position for base of VLAN priority */
+#define GEM_RBQE_VLAN_P2    (1<<(RBQE_VLAN_BASE+2))
+#define GEM_RBQE_VLAN_P1    (1<<(RBQE_VLAN_BASE+1))
+#define GEM_RBQE_VLAN_P0    (1<<RBQE_VLAN_BASE)
+#define GEM_RBQE_CFI        (1<<16)	/* CFI frame */
+#define GEM_RBQE_EOF        (1<<15)	/* End of frame. */
+#define GEM_RBQE_SOF        (1<<14)	/* Start of frame. */
+#define GEM_RBQE_LEN_MASK   (0x3FFF)	/* Mask for the length field. */
+#define GEM_RBQE_WRAP       (1<<1)	/* Wrap bit.. */
+#define GEM_RBQE_USED       (1<<0)	/* Used bit.. */
+#define GEM_RBQE_ADD_MASK   (0xFFFFFFFC)	/* Mask for address */
+
+/* Revision ID Register */
+#define GEM_REV_ID_MODEL_MASK   (0x000F0000)	/* Model ID */
+#define GEM_REV_ID_MODEL_BASE   (16)	/* For Shifting */
+#define GEM_REV_ID_REG_MODEL    (0x00020000)	/* GEM module ID */
+#define GEM_REV_ID_REV_MASK     (0x0000FFFF)	/* Revision ID */
+
+/* Define some memory offsets for easier direct access to memory map. */
+#define GEM_NET_CONTROL         (0x00)
+#define GEM_NET_CONFIG          (0x04)
+#define GEM_NET_STATUS          (0x08)
+#define GEM_USER_IO             (0x0C)
+#define GEM_TX_STATUS           (0x14)
+#define GEM_RX_QPTR             (0x18)
+#define GEM_TX_QPTR             (0x1C)
+#define GEM_RX_STATUS           (0x20)
+#define GEM_IRQ_STATUS          (0x24)
+#define GEM_IRQ_ENABLE          (0x28)
+#define GEM_IRQ_DISABLE         (0x2C)
+#define GEM_IRQ_MASK            (0x30)
+#define GEM_PHY_MAN             (0x34)
+#define GEM_RX_PAUSE_TIME       (0x38)
+#define GEM_TX_PAUSE_QUANT      (0x3C)
+
+#define GEM_HASH_BOT            (0x80)
+#define GEM_HASH_TOP            (0x84)
+#define GEM_LADDR1_BOT          (0x88)
+#define GEM_LADDR1_TOP          (0x8C)
+#define GEM_LADDR2_BOT          (0x90)
+#define GEM_LADDR2_TOP          (0x94)
+#define GEM_LADDR3_BOT          (0x98)
+#define GEM_LADDR3_TOP          (0x9C)
+#define GEM_LADDR4_BOT          (0xA0)
+#define GEM_LADDR4_TOP          (0xA4)
+#define GEM_ID_CHECK1           (0xA8)
+#define GEM_ID_CHECK2           (0xAC)
+#define GEM_ID_CHECK3           (0xB0)
+#define GEM_ID_CHECK4           (0xB4)
+#define GEM_REV_ID              (0xFC)
+
+#define GEM_OCT_TX_BOT          (0x100)
+#define GEM_OCT_TX_TOP          (0x104)
+#define GEM_STATS_FRAMES_TX     (0x108)
+#define GEM_BROADCAST_TX        (0x10C)
+#define GEM_MULTICAST_TX        (0x110)
+#define GEM_STATS_PAUSE_TX      (0x114)
+#define GEM_FRAME64_TX          (0x118)
+#define GEM_FRAME65_TX          (0x11C)
+#define GEM_FRAME128_TX         (0x120)
+#define GEM_FRAME256_TX         (0x124)
+#define GEM_FRAME512_TX         (0x128)
+#define GEM_FRAME1024_TX        (0x12C)
+#define GEM_FRAME1519_TX        (0x130)
+#define GEM_STATS_TX_URUN       (0x134)
+#define GEM_STATS_SINGLE_COL    (0x138)
+#define GEM_STATS_MULTI_COL     (0x13C)
+#define GEM_STATS_EXCESS_COL    (0x140)
+#define GEM_STATS_LATE_COL      (0x144)
+#define GEM_STATS_DEF_TX        (0x148)
+#define GEM_STATS_CRS_ERRORS    (0x14C)
+#define GEM_OCT_RX_BOT          (0x150)
+#define GEM_OCT_RX_TOP          (0x154)
+#define GEM_STATS_FRAMES_RX     (0x158)
+#define GEM_BROADCAST_RX        (0x15C)
+#define GEM_MULTICAST_RX        (0x160)
+#define GEM_STATS_PAUSE_RX      (0x164)
+#define GEM_FRAME64_RX          (0x168)
+#define GEM_FRAME65_RX          (0x16C)
+#define GEM_FRAME128_RX         (0x170)
+#define GEM_FRAME256_RX         (0x174)
+#define GEM_FRAME512_RX         (0x178)
+#define GEM_FRAME1024_RX        (0x17C)
+#define GEM_FRAME1519_RX        (0x180)
+#define GEM_STATS_USIZE_FRAMES  (0x184)
+#define GEM_STATS_EXCESS_LEN    (0x188)
+#define GEM_STATS_JABBERS       (0x18C)
+#define GEM_STATS_FCS_ERRORS    (0x190)
+#define GEM_STATS_LENGTH_ERRORS (0x194)
+#define GEM_STATS_RX_SYM_ERR    (0x198)
+#define GEM_STATS_ALIGN_ERRORS  (0x19C)
+#define GEM_STATS_RX_RES_ERR    (0x1a0)
+#define GEM_STATS_RX_ORUN       (0x1a4)
+
+#define GEM_REG_TOP             (0x23C)
+
+
+/* Define some types for using with the HAL.  These types correspond to the
+ * memory map and programming structure of the MAC device.
+ * All structures are 'volatile' to indicate they can be changed by some non-
+ * programming means - i.e. by the hardware itself.  This prevents the compiler
+ * from making false assumptions on how to optimise the code.  Some elements
+ * are also defined as 'const' to enforce some checks on the programmer.  These
+ * are only for register fields that can only be changed by the hardware and are
+ * not writable.
+ */
+
+
+struct bdesc {
+	volatile u8 *bptr;
+	volatile u32 bcontrol;
+	u32 dummy1;
+	u32 dummy2;
+};
+
+struct fdesc {
+	// Hardware mapped fields
+	void *next;
+	volatile u32 system;
+	volatile u32 fstatus;
+	volatile u32 fcontrol;
+	struct bdesc bdesc;
+};
+
+struct gemac_info_struct {
+	unsigned int baseaddr;
+	unsigned int idma_baseaddr;
+	unsigned int phyaddr;
+	unsigned int gemacconfig;
+	u32 mode;
+	u32 phyflags;		// to indicate if gigabit supported or not
+	unsigned int phyregidx;
+};
+
+/* This is a structure that will be passed and used for all HAL operations, it
+ * consists of pointers to the various MAC structures such as the MAC register
+ * block and the first descriptor element for the rx and tx buffer queues.
+ * Other internal variables declared for use in function calls and to keep track
+ * of where things are.
+ */
+struct gemac_dev {
+	void *registers;	/* Pointer to the MAC address space. */
+	void *phyregisters;	/* Pointer to the MAC address space controlling the phy */
+	void *idma_baseaddr;
+	void *baseaddr;
+	struct phy_info *phyinfo;
+	u32 phyaddr;
+	u32 mode;
+	u32 phyflags;
+	struct eth_device *dev;
+};
+
+#endif

drivers/comcerto_gem.c

diff --git a/drivers/comcerto_gem.c b/drivers/comcerto_gem.c
new file mode 100644
index 0000000..6ca0986
--- /dev/null
+++ b/drivers/comcerto_gem.c
@@ -0,0 +1,799 @@
+/*
+ * comcerto_gem.c
+ * Mindspeed Comcerto GEMAC driver
+ *
+ * From TSEC.c 
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003, Motorola, Inc.
+ * author Andy Fleming
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+#include <asm/byteorder.h>
+#include <malloc.h>
+#include <net.h>
+#include <command.h>
+#include <miiphy.h>
+
+#if defined(CONFIG_COMCERTO_GEMAC)
+#include "comcerto_gem.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct gemac_info_struct gemac_info[] = {
+#if defined(CONFIG_COMCERTO_900) || defined(CONFIG_COMCERTO_100)
+	{GEMAC_BASEADDR, MMGEM0_START, GEMAC0_PHY_ADDR, GEMAC0_CONFIG, GEMAC0_MODE, GEMAC0_PHY_FLAGS, GEMAC0_PHYIDX},
+#elif defined(CONFIG_COMCERTO_1000)
+	{GEMAC_BASEADDR, GEMAC0_PHY_ADDR, GEMAC0_CONFIG, GEMAC0_MODE, GEMAC0_PHY_FLAGS, GEMAC0_PHYIDX},
+#else
+	{0, 0, 0},
+#endif
+#if defined(CONFIG_COMCERTO_100)
+	{GEMAC1_BASEADDR, MMGEM1_START, GEMAC1_PHY_ADDR, GEMAC1_CONFIG, GEMAC1_MODE, GEMAC1_PHY_FLAGS, GEMAC1_PHYIDX},
+#elif defined(CONFIG_COMCERTO_1000)
+	{GEMAC1_BASEADDR, GEMAC1_PHY_ADDR, GEMAC1_CONFIG, GEMAC1_MODE, GEMAC1_PHY_FLAGS, GEMAC1_PHYIDX},
+#else
+	{0, 0, 0},
+#endif
+};
+
+#define MAX_GEMACS	2
+
+static struct gemac_dev *gemac_list[MAX_GEMACS];
+
+#define NUM_RX_DESC		16
+#define MAX_RX_BUFF_SIZE	2048
+
+static u32 rx_next;
+
+#if defined(CONFIG_COMCERTO_100)
+static u8 rx_ring_data_buff[NUM_RX_DESC * MAX_RX_BUFF_SIZE] __attribute((aligned(4)));
+static struct fdesc rx_ring[NUM_RX_DESC] __attribute((aligned(16)));
+static struct fdesc tx_fdesc __attribute((aligned(16)));
+#else
+static u8 rx_ring_data_buff[NUM_RX_DESC * MAX_RX_BUFF_SIZE] __attribute((aligned(16)));
+static struct rx_desc rx_ring[NUM_RX_DESC] __attribute((aligned(16)));
+static struct tx_desc tx_fdesc[2] __attribute((aligned(8)));
+#endif
+
+/* Initialize device structure. Returns success if PHY
+ * initialization succeeded (i.e. if it recognizes the PHY)
+ */
+
+static void default_speed_duplex(struct gemac_dev *gemac, int *speed, int *duplex)
+{
+	switch (gemac->mode & GEM_CONF_SPEED_MASK) {
+	case GEM_CONF_SPEED_GEM_10M:
+		*speed = _10BASET;
+		break;
+
+	case GEM_CONF_SPEED_GEM_100M:
+		*speed = _100BASET;
+		break;
+
+	case GEM_CONF_SPEED_GEM_1G:
+	default:
+		*speed = _1000BASET;
+		break;
+	}
+
+	if (gemac->mode & GEM_CONF_DUPLEX_GEM_FULL)
+		*duplex = FULL;
+	else
+		*duplex = HALF;
+}
+
+static void gemt_reinit(struct gemac_dev *gemac, int speed, int duplex)
+{
+	switch (speed) {
+	case _1000BASET:
+		printf("PHY 1000Mbit ");
+		gem_set_speed(gemac, SPEED_1000M);
+		break;
+
+	case _100BASET:
+		printf("PHY 100Mbit ");
+		gem_set_speed(gemac, SPEED_100M);
+		break;
+
+	default:
+	case _10BASET:
+		printf("PHY 10Mbit ");
+		gem_set_speed(gemac, SPEED_10M);
+		break;
+	}
+
+	switch (duplex) {
+	case FULL:
+		printf("FD\n");
+		gem_full_duplex(gemac);
+		break;
+
+	default:
+	case HALF:
+		printf("HD\n");
+		gem_half_duplex(gemac);
+		break;
+	}
+}
+
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+
+static int gemt_PHY_timeout(struct gemac_dev *gemac, int timeout)
+{
+	while (!gem_phy_man_idle(gemac)) {
+
+		if (timeout-- <= 0) {
+			printf("PHY MDIO read/write timeout\n");
+			return -1;
+		}
+
+		udelay(1);
+	}
+
+	return 0;
+}
+
+static struct gemac_dev *get_gemac(char *devname)
+{
+	int i;
+
+	for (i = 0; i < MAX_GEMACS; i++) {
+		if (!strcmp(gemac_list[i]->dev->name, devname))
+			return gemac_list[i];
+	}
+
+	return NULL;
+}
+
+static int comcerto_miiphy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value)
+{
+	struct gemac_dev *gemac = get_gemac(devname);
+
+	if (!gemac) {
+		printf("Unknown device %s\n", devname);
+		return -1;
+	}
+
+	if ((addr > 31) || (reg > 31))
+		return -1;
+
+	gem_phy_man_wr(gemac, addr, reg, value);
+	if (gemt_PHY_timeout(gemac, MDIO_TIMEOUT))
+		return -1;
+
+	return 0;
+}
+
+static int comcerto_miiphy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
+{
+	struct gemac_dev *gemac = get_gemac(devname);
+
+	if (!gemac) {
+		printf("Unknown device %s\n", devname);
+		return -1;
+	}
+
+	if ((addr > 31) || (reg > 31))
+		return -1;
+
+	gem_phy_man_rd(gemac, addr, reg);
+	if (gemt_PHY_timeout(gemac, MDIO_TIMEOUT))
+		return -1;
+
+	*value = gem_phy_man_data(gemac);
+
+	return 0;
+}
+
+/*=============================================================================
+ *
+ * NAME: gemt_config_PHY
+ * 
+ * PARAMETERS:   
+ *   net_device *dev    -INOUT
+ *
+ * DESCRIPTION   
+ *   Reconfigure PHY
+ *   This function will set up the PHY device.  This is a required external
+ *   support routine.
+ *   The parameters set up the maximum desired advertised ability for the 
+ *   device.
+ *   TODO - read back negotiated ability and set MAC appropriately.
+ *          duplex configuration to be done.
+ *
+ * ASSUMPTIONS
+ *   None
+ *
+ * SIDE EFFECTS / STATIC DATA USE
+ *   None
+ *
+ * RETURNS:      
+ *   int        0       -successful
+ *              <0      -failed
+ *
+ *===========================================================================*/
+static int gemt_config_PHY(struct gemac_dev *gemac, int phy_addr, MAC_SPEED speed, u8 duplex)
+{
+	unsigned short anar, bmcr, btcr;
+
+	if (gemac->phyflags & GEMAC_M88E1111_PHY_RGMII_ADD_DELAY) {
+		unsigned short tmp;
+
+		if (!miiphy_read(gemac->dev->name, phy_addr, 20, &tmp)) {
+			tmp |= 0x82;
+			miiphy_write(gemac->dev->name, phy_addr, 20, tmp);
+		}
+	}
+
+	if (miiphy_reset(gemac->dev->name, gemac->phyaddr))
+		return -1;
+
+	switch (speed) {
+	case _10BASET:
+		if (duplex == FULL) {
+			anar = PHY_ANAR_10FD | PHY_ANAR_10;
+			btcr = 0x0;
+			bmcr = PHY_BMCR_DPLX | PHY_BMCR_10_MBPS;
+		} else {
+			anar = PHY_ANAR_10;
+			btcr = 0x0;
+			bmcr = PHY_BMCR_10_MBPS;
+		}
+
+		break;
+
+	case _100BASET:
+	default:
+		if (duplex == FULL) {
+			anar = PHY_ANAR_TXFD | PHY_ANAR_TX | PHY_ANAR_10FD | PHY_ANAR_10;
+			btcr = 0x0;
+			bmcr = PHY_BMCR_DPLX | PHY_BMCR_100_MBPS;
+		} else {
+			anar = PHY_ANAR_TX | PHY_ANAR_10;
+			btcr = 0x0;
+			bmcr = PHY_BMCR_100_MBPS;
+		}
+
+		break;
+
+	case _1000BASET:
+		if (duplex == FULL) {
+			anar = PHY_ANAR_TXFD | PHY_ANAR_TX | PHY_ANAR_10FD | PHY_ANAR_10;
+			btcr = PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD;
+			bmcr = PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS;
+		} else {
+			anar = PHY_ANAR_TX | PHY_ANAR_10;
+			btcr = PHY_1000BTCR_1000HD;
+			bmcr = PHY_BMCR_1000_MBPS;
+		}
+
+		break;
+	}
+
+	if (gemac->phyflags & GEMAC_PHY_AUTONEG) {
+		if (miiphy_write(gemac->dev->name, phy_addr, PHY_ANAR, anar | PHY_ANAR_PSB_802_3))
+			return -1;
+
+		if (miiphy_supports_1000base_t(gemac->dev->name, phy_addr)) {
+			if (miiphy_write(gemac->dev->name, phy_addr, PHY_1000BTCR, btcr))
+				return -1;
+		}
+
+		if (miiphy_write(gemac->dev->name, phy_addr, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | bmcr))
+			return -1;
+	} else {
+		if (miiphy_write(gemac->dev->name, phy_addr, PHY_BMCR, bmcr))
+			return -1;
+	}
+
+	return 0;
+}
+
+#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
+
+/*=============================================================================
+ *
+ * NAME: gemt_reset_gem
+ * 
+ * PARAMETERS:   
+ *   net_device *dev    -INOUT
+ *
+ * DESCRIPTION   
+ *   Reset MAC hardware
+ *   This function will reset MAC hardware after stop the MAC for both 
+ *   transmission and reception.
+ *
+ * ASSUMPTIONS
+ *   None
+ *
+ * SIDE EFFECTS / STATIC DATA USE
+ *   None
+ *
+ * RETURNS:      
+ *   None
+ *
+ *===========================================================================*/
+static void gemt_reset_gem(struct gemac_dev *gemac)
+{
+	gem_abort_tx(gemac);
+	gem_disable_rx(gemac);
+
+	gem_mask_irq(gemac, GEM_IRQ_ALL);
+	gem_get_irq_stat(gemac);
+
+	if (gem_reset(gemac) != 0)
+		printf("Failed to reset device!\n");
+}
+
+#if defined(CONFIG_COMCERTO_100)
+static void gemac_rx_ring_init(struct gemac_dev *gemac)
+{
+	u32 i;
+	u8 *pU8 = rx_ring_data_buff;
+
+	for (i = 0; i < NUM_RX_DESC - 1; i++) {
+		rx_ring[i].next = (void *)(__cpu_to_le32((u32)&(rx_ring[i + 1])));
+		rx_ring[i].system = __cpu_to_le32(i);
+		rx_ring[i].fstatus = __cpu_to_le32(0);
+		rx_ring[i].fcontrol = __cpu_to_le32(IDMA_FCONTROL_FREADY);
+		rx_ring[i].bdesc.bptr = (volatile u8 *)(__cpu_to_le32((u32)pU8));
+		rx_ring[i].bdesc.bcontrol = __cpu_to_le32(0);
+		pU8 += MAX_RX_BUFF_SIZE;
+	}
+
+	rx_ring[i].next = (void *)(__cpu_to_le32((u32)&(rx_ring[0])));
+	rx_ring[i].system = __cpu_to_le32(i);
+	rx_ring[i].fstatus = __cpu_to_le32(0);
+	rx_ring[i].fcontrol = __cpu_to_le32(0);
+	rx_ring[i].bdesc.bptr = (volatile u8 *)(__cpu_to_le32((u32)pU8));
+	rx_ring[i].bdesc.bcontrol = __cpu_to_le32(0);
+
+	rx_next = 0;
+}
+
+static int gemac_send(struct eth_device *dev, volatile void *packet, int length)
+{
+	struct gemac_dev *gemac = (struct gemac_dev *)dev->priv;
+	int i;
+
+	if (length <= 0) {
+		printf("Comcerto_Emac: bad packet size: %d\n", length);
+		return (-1);
+	}
+
+	memset(&tx_fdesc, 0, sizeof(struct fdesc));
+
+	// build the tx frame descriptor here
+	tx_fdesc.fcontrol = __cpu_to_le32(IDMA_FCONTROL_FREADY | IDMA_FCONTROL_FLAST);
+	tx_fdesc.fstatus = __cpu_to_le32(0);
+	tx_fdesc.bdesc.bptr = (volatile u8 *)(__cpu_to_le32((u32)((u8 *)packet)));
+	tx_fdesc.bdesc.bcontrol = __cpu_to_le32(length | IDMA_BCONTROL_BLAST);
+
+	// Check if DMA Stopped
+	if (!(*(volatile u32 *)(gemac->idma_baseaddr + MMEM_START) & __cpu_to_le32(IDMA_START))) {
+		*(volatile u32 *)(gemac->idma_baseaddr + MMEM_HEAD) = __cpu_to_le32((u32) &tx_fdesc);
+		*(volatile u32 *)(gemac->idma_baseaddr + MMEM_START) |= __cpu_to_le32(IDMA_START);
+	} else {
+		printf("Emac: tx EDMA busy!\n");
+		return (-1);
+	}
+
+	i = 0;
+	while ((tx_fdesc.fstatus & __cpu_to_le32(IDMA_FSTATUS_FRAME_DONE_MASK)) == 0) {
+		udelay(100);
+		i++;
+		if (i == 50000) {
+			printf("Emac: tx timed out!\n");
+			return (-1);
+		}
+	}
+
+	if (*(volatile u32 *)(gemac->idma_baseaddr + MMEM_START) & __cpu_to_le32(IDMA_START)) {
+		printf("Error! Emac: tx did not stop after sending a packet!\n");
+	}
+
+	return (length);
+}
+
+static int gemac_recv(struct eth_device *dev)
+{
+	struct gemac_dev *gemac = (struct gemac_dev *)dev->priv;
+	int rx_prev;
+	int length;
+	int total_length = 0;
+
+	// loop thru rx FDescs
+	while (1) {
+		if ((rx_ring[rx_next].fstatus & __cpu_to_le32(IDMA_FSTATUS_FRAME_DONE_MASK)) == 0)
+			break;
+
+		// mark rx_next not usable
+		rx_ring[rx_next].fcontrol = __cpu_to_le32(0);
+
+		length = __le32_to_cpu(rx_ring[rx_next].bdesc.bcontrol) & 0x0000ffff;
+		if (length > MAX_RX_BUFF_SIZE) {
+			printf("Comcerto_Emac: frame too big (%d bytes)!\n", length);
+			length = MAX_RX_BUFF_SIZE;
+		}
+
+		// Pass the packet up to the protocol layers.
+                NetReceive((volatile uchar *)(__le32_to_cpu((u32)(rx_ring[rx_next].bdesc.bptr))), length);
+		total_length += length;
+
+		// rx_prev can be used now
+		if (rx_next == 0)
+			rx_prev = NUM_RX_DESC - 1;
+		else
+			rx_prev = rx_next - 1;
+
+		rx_ring[rx_prev].fstatus = __cpu_to_le32(0);
+		rx_ring[rx_prev].fcontrol = __cpu_to_le32(IDMA_FCONTROL_FREADY);
+
+		rx_next++;
+		if (rx_next == NUM_RX_DESC)
+			rx_next = 0;
+	}
+
+	// Check if DMA Stopped
+	// if RX is stopped, restart
+	if (!(*(volatile u32 *)(gemac->idma_baseaddr + EMMM_START) & __cpu_to_le32(IDMA_START))) {
+		*(volatile u32 *)(gemac->idma_baseaddr + EMMM_HEAD) = __cpu_to_le32((u32) (&(rx_ring[rx_next])));
+		*(volatile u32 *)(gemac->idma_baseaddr + EMMM_START) |= __cpu_to_le32(IDMA_START);
+	}
+
+	return (total_length);
+}
+
+/* Stop the interface */
+static void gemac_halt(struct eth_device *dev)
+{
+	struct gemac_dev *gemac = (struct gemac_dev *)dev->priv;
+
+	*(volatile u32 *)(gemac->idma_baseaddr + MMEM_SOFT_RESET) = __cpu_to_le32(1);
+	*(volatile u32 *)(gemac->idma_baseaddr + EMMM_SOFT_RESET) = __cpu_to_le32(1);
+
+	gem_stop_tx(gemac);
+	gem_disable_rx(gemac);
+}
+
+#else
+static void gemac_rx_ring_init(struct gemac_dev *gemac)
+{
+	u8 *pU8;
+	int i;
+
+//	printf("%s()\n", __func__);
+
+	memset(rx_ring, 0, NUM_RX_DESC * sizeof(struct rx_desc));
+	pU8 = rx_ring_data_buff;
+
+	for (i = 0; i < NUM_RX_DESC - 1; i++) {
+		rx_ring[i].data = (volatile u8 *)(__cpu_to_le32((u32)pU8));
+		pU8 += MAX_RX_BUFF_SIZE;
+	}
+
+	rx_ring[i].data = (volatile u8 *)(__cpu_to_le32((u32)pU8));
+	rx_ring[i].status |= __cpu_to_le32(GEMRX_WRAP);	// last descriptor in the list
+	rx_next = 0;
+	*(volatile u32 *)(gemac->baseaddr + GEM_IP + GEM_RX_QPTR) = __cpu_to_le32((u32)rx_ring);
+}
+
+static int gemac_send(struct eth_device *dev, volatile void *packet, int length)
+{
+	struct gemac_dev *gemac = (struct gemac_dev *)dev->priv;
+	int i, rc = -1;
+
+	if (length <= 0) {
+		printf("Comcerto_Emac: bad packet size: %d\n", length);
+		return (-1);
+	}
+
+	// build the tx frame descriptor here
+	memset(&tx_fdesc, 0, 2 * sizeof(struct tx_desc));
+
+	tx_fdesc[0].ctl |= __cpu_to_le32(TX_DESC_WORD1_LAST | TX_DESC_WORD1_FCS);
+	tx_fdesc[0].data = (volatile u8 *)(__cpu_to_le32((u32)packet));
+	tx_fdesc[0].ctl |= __cpu_to_le32(length & TX_DESC_WORD1_LEGTH_MASK);
+	tx_fdesc[1].ctl |= __cpu_to_le32(TX_DESC_WORD1_WRAP | TX_DESC_WORD1_USED);
+
+	// just enable queue0, let the other queues uninitialized
+	*(volatile u32 *)(gemac->baseaddr + GEM_IP + GEM_QUEUE_BASE0) = __cpu_to_le32((u32)&tx_fdesc[0]);
+
+	gem_start_tx(gemac);
+	// Notify scheduler
+	*(volatile u32 *)(gemac->baseaddr + GEM_SCH_PKT_QUEUED) = __cpu_to_le32((u32) length);
+
+	i = 0;
+	while ((tx_fdesc[0].ctl & __cpu_to_le32(TX_DESC_WORD1_USED)) == 0) {
+		udelay(100);
+		i++;
+		if (i == 50000) {
+			printf("Emac: tx timed out!\n");
+			goto out;
+		}
+	}
+
+	rc = length;
+//      printf("gemac_send done \n");
+out:
+
+	return rc;
+}
+
+static int gemac_recv(struct eth_device *dev)
+{
+	int length = 0;
+	int total_length = 0;
+	u32 rx_status;
+	u32 rx_data;
+	u32 rx_extstatus;
+
+	// loop thru rx FDescs
+	while (1) {
+
+		rx_extstatus = rx_ring[rx_next].extstatus;
+		if (((rx_extstatus & __cpu_to_le32(GEMRX_OWN)) == 0)) {
+//			printf("done %d index %d\n",total_length, rx_next); 
+			break;
+		}
+
+		rx_data = __le32_to_cpu(rx_ring[rx_next].data);
+		rx_status = __le32_to_cpu(rx_ring[rx_next].status);
+		length = (rx_status & RX_STA_LEN_MASK) /*>>RX_STA_LEN_POS */ ;
+
+		// Pass the packet up to the protocol layers.
+		if (!(rx_status & RX_CHECK_ERROR)) {
+			NetReceive((u8 *)rx_data, length);
+			total_length += length;
+		}
+
+		//clear bits... the buffer can be reused
+		rx_ring[rx_next].status &= __cpu_to_le32(GEMRX_WRAP);
+		rx_ring[rx_next].extstatus = __cpu_to_le32(0);
+		length = 0;
+
+		rx_next++;
+		if (rx_next == NUM_RX_DESC)
+			rx_next = 0;
+	}
+
+	return (total_length);
+}
+
+/* Stop the interface */
+static void gemac_halt(struct eth_device *dev)
+{
+	struct gemac_dev *gemac = (struct gemac_dev *)dev->priv;
+
+//	printf("%s()\n", __func__);
+
+	gem_stop_tx(gemac);
+	gem_abort_tx(gemac);
+	gem_disable_rx(gemac);
+}
+#endif
+
+/* Initializes data structures and registers for the controller,
+ * and brings the interface up.	 Returns the link status, meaning
+ * that it returns success if the link is up, failure otherwise.
+ * This allows u-boot to find the first active controller. */
+static int gemac_init(struct eth_device *dev, bd_t * bd)
+{
+	struct gemac_dev *gemac = (struct gemac_dev *)dev->priv;
+	MAC_ADDR enet_addr;
+	int speed = _1000BASET, duplex = FULL;
+
+//	printf("%s()\n", __func__);
+
+	/* Make sure the controller is stopped */
+	gemac_halt(dev);
+
+	default_speed_duplex(gemac, &speed, &duplex);
+
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+	if (!(gemac->phyflags & GEMAC_NO_PHY))
+		if (miiphy_speed_duplex(gemac->dev->name, gemac->phyaddr, &speed, &duplex))
+			return -1;
+#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
+
+	gemt_reinit(gemac, speed, duplex);
+
+	gem_disable_copy_all(gemac);
+	gem_allow_broadcast(gemac);
+	gem_enable_unicast(gemac);
+	gem_disable_multicast(gemac);
+	gem_disable_fcs_rx(gemac);
+
+	gem_enet_addr_byte_mac(dev->enetaddr, &enet_addr);
+	gem_set_laddr1(gemac, &enet_addr);
+
+	gemac_rx_ring_init(gemac);
+
+	/* Ready the device for tx/rx */
+	gem_start_tx(gemac);
+	gem_enable_rx(gemac);
+
+	return (1);
+}
+
+int comcerto_gemac_initialize(bd_t * bis, int index, char *devname)
+{
+	struct eth_device *dev;
+	struct gemac_dev *gemac;
+	int i;
+
+	dev = (struct eth_device *)malloc(sizeof(struct eth_device));
+	if (!dev)
+		return -1;
+
+	memset(dev, 0, sizeof(struct eth_device));
+
+	gemac = (struct gemac_dev *)malloc(sizeof(struct gemac_dev));
+	if (!gemac)
+		return -1;
+
+	gemac_list[index] = gemac;
+	gemac->baseaddr = (void *)gemac_info[index].baseaddr;
+	gemac->registers = (void *)(gemac_info[index].baseaddr + GEM_IP);
+	gemac->phyregisters = (void *)(gemac_info[gemac_info[index].phyregidx].baseaddr + GEM_IP);
+	gemac->phyaddr = gemac_info[index].phyaddr;
+	gemac->mode = gemac_info[index].mode;
+
+#if defined(CONFIG_COMCERTO_100)
+	gemac->idma_baseaddr = (void *)(gemac_info[index].idma_baseaddr);
+#endif
+	gemac->phyflags = gemac_info[index].phyflags;
+	sprintf(dev->name, devname);
+	dev->iobase = 0;
+	dev->priv = gemac;
+	gemac->dev = dev;
+	dev->init = gemac_init;
+	dev->halt = gemac_halt;
+	dev->send = gemac_send;
+	dev->recv = gemac_recv;
+
+	/* Tell u-boot to get the addr from the env */
+	for (i = 0; i < 6; i++)
+		dev->enetaddr[i] = 0;
+
+	eth_register(dev);
+
+	/* put gemac out of reset */
+#if defined(CONFIG_COMCERTO_100)
+	{
+// TODO: please cleanup need centralize the reset bock
+		volatile int delay_count;
+
+		// get GEMAC out of reset
+		*(volatile u32 *)(BLOCK_RESET_REG) |= __cpu_to_le32(GEMAC0_RST << index);
+		// 20 ops delay
+		delay_count = 20;
+		while (delay_count--) ;
+	}
+#else
+	{
+		// TODO: please cleanup need centralize the reset bock
+		volatile int delay_count;
+
+		// get GEMAC out of reset
+		*(volatile u32 *)(CLKCORE_BLK_RESET) |=
+		    __cpu_to_le32((BLK_RESET_GEMAC0_AHB_RESET_N << index) | (BLK_RESET_GEMAC0_REF_RESET_N << index));
+		// 20 ops delay
+		delay_count = 20;
+		while (delay_count--) ;
+	}
+#endif
+
+#if !defined(CONFIG_COMCERTO_MII_CFG_BOOTSTRAP)
+	// software config
+	switch (gemac_info[index].gemacconfig) {
+	case CONFIG_COMCERTO_USE_GMII:
+		*(volatile u32 *)(gemac->baseaddr + GEM_CFG) = __cpu_to_le32(gemac->mode | GEM_CONF_MODE_SEL_GEM | GEM_CONF_MODE_GEM_GMII);
+		break;
+	case CONFIG_COMCERTO_USE_RGMII:
+		*(volatile u32 *)(gemac->baseaddr + GEM_CFG) = __cpu_to_le32(gemac->mode | GEM_CONF_MODE_SEL_GEM | GEM_CONF_MODE_GEM_RGMII);
+		break;
+	case CONFIG_COMCERTO_USE_RMII:
+		*(volatile u32 *)(gemac->baseaddr + GEM_CFG) = __cpu_to_le32(gemac->mode | GEM_CONF_MODE_SEL_GEM | GEM_CONF_MODE_GEM_RMII);
+		break;
+	case CONFIG_COMCERTO_USE_MII:
+		*(volatile u32 *)(gemac->baseaddr + GEM_CFG) = __cpu_to_le32(gemac->mode | GEM_CONF_MODE_SEL_GEM | GEM_CONF_MODE_GEM_MII);
+		break;
+	default:
+		printf("comcerto gemac software config requires one MII mode defined %d\n");
+		return (-1);
+	}
+#else
+	*(volatile u32 *)(gemac->baseaddr + GEM_CFG) = __cpu_to_le32(gemac->mode);
+#endif
+
+#if defined(CONFIG_COMCERTO_1000)
+	if ((gemac->phyflags & GEMAC_GEM_DELAY_DISABLE))
+		*(volatile u32 *)(gemac->baseaddr + GEM_DELAY_ELEMENT_CTRL) = __cpu_to_le32(0);
+#endif
+
+#if defined(CONFIG_COMCERTO_100)
+	*(volatile u32 *)(gemac->baseaddr + GEM_TX_CTRL) = __cpu_to_le32(GEM_TXCTRL_DMAIF_EN | GEM_TXCTRL_CRC_EN | GEM_TXCTRL_RETR_EN);
+	*(volatile u32 *)(gemac->baseaddr + GEM_RX_CTRL) = __cpu_to_le32(GEM_RXCTRL_DMAIF_EN);
+	*(volatile u32 *)(gemac->baseaddr + GEM_RX_STAT_PKTSIZE) = __cpu_to_le32(0x100);
+	*(volatile u32 *)(gemac->baseaddr + GEM_ARM_FIFO_CTRL) = __cpu_to_le32(ARM_FIFO_RXDREQWE | ARM_FIFO_TXDREQRE);
+	*(volatile u32 *)(gemac->baseaddr + GEM_ARM_RX_FIFO_HIGH) = __cpu_to_le32(0x1D0);
+	*(volatile u32 *)(gemac->baseaddr + GEM_ARM_RX_FIFO_LOW) = __cpu_to_le32(0x180);
+	*(volatile u32 *)(gemac->baseaddr + GEM_RX_FIFO_HIGH) = __cpu_to_le32(0x1CD);
+	*(volatile u32 *)(gemac->baseaddr + GEM_FIFO_CTRL) = __cpu_to_le32(GEM_FIFO_CTRL_TXFF_EN | GEM_FIFO_CTRL_HBTXRQ_EN | GEM_FIFO_CTRL_RXFF_EN | GEM_FIFO_CTRL_HBRXRQ_EN);
+#else
+	/* configure DMA register */
+	/* enable scheduler */
+	*(volatile u32 *)(gemac->baseaddr + GEM_IP + GEM_DMA_CONFIG) |= __cpu_to_le32((1UL << 31));
+
+	/* Master enable scheduler block*/
+	*(volatile u32 *)(gemac->baseaddr + GEM_SCH_CTL) |= __cpu_to_le32(1UL);
+
+	/* enable 16 bytes aligned bursts */
+	*(volatile u32 *)(gemac->baseaddr + GEM_IP + GEM_DMA_CONFIG) |= __cpu_to_le32((1UL << 27));
+
+	/* enable software buffer allocation (legacy mode) */
+	*(volatile u32 *)(gemac->baseaddr + GEM_IP + GEM_DMA_CONFIG) |= __cpu_to_le32((1UL << 26));
+	*(volatile u32 *)(gemac->baseaddr + GEM_IP + GEM_DMA_CONFIG) |= __cpu_to_le32((1UL << 25));
+
+	*(volatile u32 *)(gemac->baseaddr + GEM_IP + GEM_DMA_CONFIG) &= __cpu_to_le32(~(0x00FF001F));
+
+	/* set buffer size to 2048 bytes */
+	*(volatile u32 *)(gemac->baseaddr + GEM_IP + GEM_DMA_CONFIG) |= __cpu_to_le32(0x00200000);
+
+	/* attempt to use INCR16 AHB bursts */
+	*(volatile u32 *)(gemac->baseaddr + GEM_IP + GEM_DMA_CONFIG) |= __cpu_to_le32(0x00000010);
+
+	/* disable admittance manager */
+	*(volatile u32 *)(gemac->baseaddr + GEM_IP + GEM_DMA_CONFIG) &= __cpu_to_le32(~(1UL << 12));
+
+ 	/* disable admittance master config bit */
+ 	*(volatile u32 *)(gemac->baseaddr + ADMITTANCE + ADM_CFG) &= ~(1UL);
+
+#endif
+	/* Reset the MAC */
+	gemt_reset_gem(gemac);
+
+	if (index == 0) {
+#if defined(CONFIG_COMCERTO_100)
+/* todo remove this from this file */
+		// set ephy divider and switch to ref clk (25Mhz)
+		*(volatile u32 *)(CLKCORE_CLKDIV_CNTRL) &= __cpu_to_le32(~(0x1F << EPHY_CLKDIV_RATIO_SHIFT));
+		*(volatile u32 *)(CLKCORE_CLKDIV_CNTRL) |= __cpu_to_le32(((CFG_ARM_CLOCK / 25000000) << EPHY_CLKDIV_RATIO_SHIFT));
+		*(volatile u32 *)(CLKCORE_CLKDIV_CNTRL) &= __cpu_to_le32(~EPHY_CLKDIV_BYPASS);
+#endif
+		reset_emac0_phy(1);
+	}
+
+	if (index == 1) {
+		reset_emac1_phy(1);
+	}
+
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+	gem_enable_MDIO(gemac);
+
+	if (!(gemac->phyflags & GEMAC_NO_PHY)) {
+		int speed, duplex;
+
+		miiphy_register(dev->name, comcerto_miiphy_read, comcerto_miiphy_write);
+
+		default_speed_duplex(gemac, &speed, &duplex);
+
+		if (gemt_config_PHY(gemac, gemac->phyaddr, speed, duplex))
+			return -1;
+	}
+#endif
+
+	return 0;
+}
+
+#endif /* CONFIG_COMCERTO_GEMAC */

drivers/comcerto_gem.h

diff --git a/drivers/comcerto_gem.h b/drivers/comcerto_gem.h
new file mode 100644
index 0000000..d6087ed
--- /dev/null
+++ b/drivers/comcerto_gem.h
@@ -0,0 +1,398 @@
+#ifndef __COMCERTO_GEM_H__
+#define __COMCERTO_GEM_H__
+
+/* An enumerated type for loopback values.  This can be one of three values, no
+ * loopback -normal operation, local loopback with internal loopback module of
+ * MAC or PHY loopback which is through the external PHY.
+ */
+#ifndef __MAC_LOOP_ENUM__
+#define __MAC_LOOP_ENUM__
+typedef enum { LB_NONE, LB_EXT, LB_LOCAL } MAC_LOOP;
+#endif
+
+/* The possible operating speeds of the MAC, currently supporting 10, 100 and
+ * 1000Mb modes.
+ */
+#ifndef __MAC_SPEED_ENUM__
+#define __MAC_SPEED_ENUM__
+typedef enum { SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS } MAC_SPEED;
+#endif
+
+/* The possible AMBA AHB bus width of the MAC, currently supporting 32, 64 and
+ * 128 bits.
+ */
+#ifndef __MAC_AHB_ENUM__
+#define __MAC_AHB_ENUM__
+typedef enum { AMBA_AHB_32, AMBA_AHB_64, AMBA_AHB_128 } MAC_AHB_WIDTH;
+#endif
+
+/* The possible MDC clock division of the MAC, currently supporting 8, 16 , 32,
+ * 48, 64, 96, 128, 224.
+ */
+#ifndef __MAC_DMCDIV_ENUM__
+#define __MAC_DMCDIV_ENUM__
+typedef enum { MDC_DIV_8, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, MDC_DIV_64,
+	MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} MAC_MDC_DIV;
+#endif
+
+#define MDIO_TIMEOUT            5000	/* instruction cycles? */
+
+/* Specify whether the MDIO should be available, this is set so that for reset
+ * function, appropriate options are setup.  To disable, use 0.
+ */
+#define GEM_MDIO_ENABLED (GEM_MDIO_EN)
+
+/* Specify the default AMBA AHB bus width.  This simply defines
+ * which of the bus width control bits are active.  By default, the bus
+ * width is 32.
+ */
+#define GEM_DEF_AHB_WIDTH (AMBA_AHB_32)
+
+/* Specify default duplex mode, for half duplex - specify 0. */
+#ifndef GEM_DEF_DUPLEX
+/* Allow the value to be specified as compiler option 
+   0 - half-duplex, 
+   GEM_FULL_DUPLEX - full-duplex
+*/
+#define GEM_DEF_DUPLEX (GEM_FULL_DUPLEX)
+#endif
+
+/* Specify default operating speed, 1 for 100Mb.  Note that this is left
+ * shifted.  Also note that this simply asserts a signal to the PHY and has no
+ * effect on the operation of the MAC.
+ * For 10Mb/s mode, specify         SPEED_10M
+ * For 100Mb/s mode, specify        SPEED_100M
+ * For 1Gb/s mode, specify          SPEED_1000M
+ * For 1Gb/s with PCS mode, specify SPEED_1000M_PCS
+ */
+#ifndef GEM_DEF_SPEED
+/* Allow the value to be specified as compiler option */
+#define GEM_DEF_SPEED (SPEED_1000M)
+#endif
+
+/* Specify default loopback mode.  LB_NONE for no loopback, other values are LB_MAC
+ * and LB_PHY
+ */
+#define GEM_DEF_LOOP (LB_NONE)
+
+/* Define some types for using with the HAL.  These types correspond to the
+ * memory map and programming structure of the MAC device.
+ * All structures are 'volatile' to indicate they can be changed by some non-
+ * programming means - i.e. by the hardware itself.  This prevents the compiler
+ * from making false assumptions on how to optimise the code.  Some elements
+ * are also defined as 'const' to enforce some checks on the programmer.  These
+ * are only for register fields that can only be changed by the hardware and are
+ * not writable.
+ */
+
+/* The Address organisation for the MAC device.  All addresses are split into
+ * two 32-bit register fields.  The first one (bottom) is the lower 32-bits of
+ * the address and the other field are the high order bits - this may be 16-bits
+ * in the case of MAC addresses, or 32-bits for the hash address.
+ * In terms of memory storage, the first item (bottom) is assumed to be at a
+ * lower address location than 'top'. i.e. top should be at address location of
+ * 'bottom' + 4 bytes.
+ */
+#ifndef __MAC_ADDR_DEF__
+#define __MAC_ADDR_DEF__
+typedef struct {
+	u32 bottom;		/* Lower 32-bits of address. */
+	u32 top;		/* Upper 32-bits of address. */
+} volatile MAC_ADDR;
+#endif
+
+/* The following is the organisation of the address filters section of the MAC
+ * registers.  The Cadence MAC contains four possible specific address match
+ * addresses, if an incoming frame corresponds to any one of these four
+ * addresses then the frame will be copied to memory.
+ * It is not necessary for all four of the address match registers to be
+ * programmed, this is application dependant.
+ */
+#ifndef __SPEC_ADDR_DEF__
+#define __SPEC_ADDR_DEF__
+typedef struct {
+	MAC_ADDR one;		/* Specific address register 1. */
+	MAC_ADDR two;		/* Specific address register 2. */
+	MAC_ADDR three;		/* Specific address register 3. */
+	MAC_ADDR four;		/* Specific address register 4. */
+} volatile SPEC_ADDR;
+#endif
+
+/* The set of statistics registers implemented in the Cadence MAC.
+ * The statistics registers implemented are a subset of all the statistics
+ * available, but contains all the compulsory ones.
+ * For full descriptions on the registers, refer to the Cadence MAC programmers
+ * guide or the IEEE 802.3 specifications.
+ */
+typedef struct {
+	u32 octets_tx_bot;	/* Lower 32-bits for number of octets tx'd */
+	u32 octets_tx_top;	/* Upper 16-bits for number of octets tx'd */
+	u32 frames_tx;		/* Number of frames transmitted OK */
+	u32 broadcast_tx;	/* Number of broadcast frames transmitted */
+	u32 multicast_tx;	/* Number of multicast frames transmitted */
+	u32 pause_tx;		/* Number of pause frames transmitted. */
+	u32 frame64_tx;		/* Number of 64byte frames transmitted */
+	u32 frame65_127_tx;	/* Number of 65-127 byte frames transmitted */
+	u32 frame128_255_tx;	/* Number of 128-255 byte frames transmitted */
+	u32 frame256_511_tx;	/* Number of 256-511 byte frames transmitted */
+	u32 frame512_1023_tx;	/* Number of 512-1023 byte frames transmitted */
+	u32 frame1024_1518_tx;	/* Number of 1024-1518 byte frames transmitted */
+	u32 frame1519_tx;	/* Number of frames greater than 1518 bytes tx */
+	u32 tx_urun;		/* Transmit underrun errors due to DMA */
+	u32 single_col;		/* Number of single collision frames */
+	u32 multi_col;		/* Number of multi collision frames */
+	u32 excess_col;		/* Number of excessive collision frames. */
+	u32 late_col;		/* Collisions occuring after slot time */
+	u32 def_tx;		/* Frames deferred due to crs */
+	u32 crs_errors;		/* Errors caused by crs not being asserted. */
+
+	u32 octets_rx_bot;	/* Lower 32-bits for number of octets rx'd */
+	u32 octets_rx_top;	/* Upper 16-bits for number of octets rx'd */
+	u32 frames_rx;		/* Number of frames received OK */
+	u32 broadcast_rx;	/* Number of broadcast frames received */
+	u32 multicast_rx;	/* Number of multicast frames received */
+	u32 pause_rx;		/* Number of pause frames received. */
+	u32 frame64_rx;		/* Number of 64byte frames received */
+	u32 frame65_127_rx;	/* Number of 65-127 byte frames received */
+	u32 frame128_255_rx;	/* Number of 128-255 byte frames received */
+	u32 frame256_511_rx;	/* Number of 256-511 byte frames received */
+	u32 frame512_1023_rx;	/* Number of 512-1023 byte frames received */
+	u32 frame1024_1518_rx;	/* Number of 1024-1518 byte frames received */
+	u32 frame1519_rx;	/* Number of frames greater than 1518 bytes rx */
+	u32 usize_frames;	/* Frames received less than min of 64 bytes */
+	u32 excess_length;	/* Number of excessive length frames rx */
+	u32 jabbers;		/* Excessive length + crc or align errors. */
+	u32 fcs_errors;		/* Number of frames received with crc errors */
+	u32 length_check_errors;	/* Number of frames with incorrect length */
+	u32 rx_symbol_errors;	/* Number of times rx_er asserted during rx */
+	u32 align_errors;	/* Frames received without integer no. bytes */
+	u32 rx_res_errors;	/* Number of times buffers ran out during rx */
+	u32 rx_orun;		/* Receive overrun errors due to DMA */
+
+} volatile GEM_STATS;
+#if 0
+/* This is the memory map for the Cadence Enhanced MAC device.
+ * For full descriptions on the registers, refer to the Cadence MAC programmers
+ * guide or the IEEE 802.3 specifications.
+ */
+typedef struct {
+	u32 net_control;	/* Network control 0x00 */
+	u32 net_config;		/* Network config 0x04 */
+	const volatile u32 net_status;	/* Network status, RO, 0x08 */
+	volatile u32 user_io;	/* User IO 0x0C */
+	volatile u32 dma;	/* DMA interface 0x10 */
+	u32 tx_status;		/* Transmit status 0x14 */
+	u32 rx_qptr;		/* Receive queue pointer 0x18 */
+	u32 tx_qptr;		/* Transmit queue pointer 0x1C */
+	u32 rx_status;		/* Receive status 0x20 */
+	u32 irq_status;		/* Interrupt status 0x24 */
+	u32 irq_enable;		/* Interrupt enable 0x28 */
+	u32 irq_disable;	/* Interrupt disable 0x2C */
+	const volatile u32 irq_mask;	/* Interrupt mask, RO, 0x30 */
+	u32 phy_man;		/* PHY management 0x34 */
+	const volatile u32 pause_time;	/* Pause time register 0x38 */
+	u32 tx_pause_quant;	/* Transmit pause quantum 0x3C */
+	u32 reserved[16];	/* Reserved */
+	MAC_ADDR hash_addr;	/* Hash address 0x80 - 0x84 */
+	SPEC_ADDR address;	/* Specific addresses 0x88 - 0xA4 */
+	u32 id_check1;		/* Type ID check1 0xA8 */
+	u32 id_check2;		/* Type ID check2 0xAC */
+	u32 id_check3;		/* Type ID check3 0xB0 */
+	u32 id_check4;		/* Type ID check4 0xB4 */
+	u32 rsvd2[17];		/* Reserved */
+	u32 rev_id;		/* Device Revision ID 0xFC */
+	GEM_STATS stats;	/* MAC statistics 0x100 - 0x1A4 */
+} volatile GEM_REG;
+#endif
+
+#define GEMAC_SW_CONF		(1 << 8) | (1 << 11)    // GEMAC configured by SW
+#define GEMAC_PHY_CONF		0                       // GEMAC configured by phy lines (not for MII/GMII)
+#define GEMAC_SW_FULL_DUPLEX	(1 << 9)
+#define GEMAC_SW_SPEED_10M	(0 << 12)
+#define GEMAC_SW_SPEED_100M	(1 << 12)
+#define GEMAC_SW_SPEED_1G	(2 << 12)
+
+#define CONFIG_COMCERTO_USE_MII		(1 << 0)
+#define CONFIG_COMCERTO_USE_RMII	(1 << 1)
+#define CONFIG_COMCERTO_USE_GMII	(1 << 2)
+#define CONFIG_COMCERTO_USE_RGMII	(1 << 3)
+
+// flags to be used for phy config
+#define GEMAC_NO_PHY				(1 << 0)	/* GEMAC is not connected to PHY */
+#define GEMAC_PHY_AUTONEG			(1 << 1)	/* Enable PHY autonegotiation */
+#define GEMAC_GEM_DELAY_DISABLE			(1 << 2)	/* Disable delay on GEM Tx/Rx clocks */
+#define GEMAC_M88E1111_PHY_RGMII_ADD_DELAY	(1 << 3)	/* Enable delay on Marvel 88E1111 PHY Tx/Rx clocks */
+
+#if defined(CONFIG_COMCERTO_100)
+#include "comcerto100_gem.h"
+#else
+#include "comcerto1000_gem.h"
+#endif
+
+/******************************************************************************/
+/*
+ * Prototypes for functions of HAL
+*/
+/******************************************************************************/
+
+/* Re-initialise device and check reset values. */
+int gem_reset(struct gemac_dev *gemac);
+
+/* Device setup. */
+
+void gem_set_loop(struct gemac_dev *gemac, MAC_LOOP gem_loop);
+MAC_LOOP gem_get_loop(struct gemac_dev *gemac);
+
+void gem_enable_eam(struct gemac_dev *gemac);
+void gem_disable_eam(struct gemac_dev *gemac);
+
+void gem_enable_fcs_rx(struct gemac_dev *gemac);
+void gem_disable_fcs_rx(struct gemac_dev *gemac);
+
+void gem_enable_1536_rx(struct gemac_dev *gemac);
+void gem_disable_1536_rx(struct gemac_dev *gemac);
+
+void gem_full_duplex(struct gemac_dev *gemac);
+void gem_half_duplex(struct gemac_dev *gemac);
+
+void gem_set_speed(struct gemac_dev *gemac, MAC_SPEED gem_speed);
+MAC_SPEED gem_get_speed(struct gemac_dev *gemac);
+
+void gem_set_ahb_width(struct gemac_dev *gemac, MAC_AHB_WIDTH gem_buswidth);
+MAC_AHB_WIDTH gem_get_ahb_width(struct gemac_dev *gemac);
+
+void gem_set_mdc_div(struct gemac_dev *gemac, MAC_MDC_DIV gem_mdcdiv);
+MAC_MDC_DIV gem_get_mdc_div(struct gemac_dev *gemac);
+
+/* Pause control. */
+void gem_enable_pause_rx(struct gemac_dev *gemac);
+void gem_disable_pause_rx(struct gemac_dev *gemac);
+
+u32 gem_pause_time(struct gemac_dev *gemac);
+
+void gem_enable_pause_cpy(struct gemac_dev *gemac);
+void gem_disable_pause_cpy(struct gemac_dev *gemac);
+
+void gem_send_0q_pause(struct gemac_dev *gemac);
+void gem_send_pause(struct gemac_dev *gemac);
+
+void gem_set_tx_pause_q(struct gemac_dev *gemac, u32 gem_pause);
+u32 gem_get_tx_pause_q(struct gemac_dev *gemac);
+
+/* PHY management control. */
+void gem_enable_MDIO(struct gemac_dev *gemac);
+void gem_disable_MDIO(struct gemac_dev *gemac);
+
+int gem_phy_man_wr(struct gemac_dev *gemac, u8 phy_addr, u8 reg_addr, u32 data);
+int gem_phy_man_rd(struct gemac_dev *gemac, u8 phy_addr, u8 reg_addr);
+u32 gem_phy_man_data(struct gemac_dev *gemac);
+
+int gem_phy_man_idle(struct gemac_dev *gemac);
+
+int gem_link_status(struct gemac_dev *gemac);
+
+/* Address setup and control. */
+void gem_enable_unicast(struct gemac_dev *gemac);
+void gem_disable_unicast(struct gemac_dev *gemac);
+
+void gem_enable_multicast(struct gemac_dev *gemac);
+void gem_disable_multicast(struct gemac_dev *gemac);
+
+void gem_allow_broadcast(struct gemac_dev *gemac);
+void gem_no_broadcast(struct gemac_dev *gemac);
+
+void gem_enable_copy_all(struct gemac_dev *gemac);
+void gem_disable_copy_all(struct gemac_dev *gemac);
+
+void gem_set_hash(struct gemac_dev *gemac, MAC_ADDR *hash_addr);
+MAC_ADDR gem_get_hash(struct gemac_dev *gemac);
+
+void gem_set_address(struct gemac_dev *gemac, SPEC_ADDR *spec_addr);
+SPEC_ADDR gem_get_address(struct gemac_dev *gemac);
+
+/* Functions to convert between address formats. */
+int gem_enet_addr_byte_mac(u8 *enet_byte_addr, MAC_ADDR *enet_addr);
+int gem_enet_addr_mac_byte(u8 *enet_byte_addr, MAC_ADDR *enet_addr);
+
+void gem_set_laddr1(struct gemac_dev *gemac, MAC_ADDR *address);
+void gem_set_laddr2(struct gemac_dev *gemac, MAC_ADDR *address);
+void gem_set_laddr3(struct gemac_dev *gemac, MAC_ADDR *address);
+void gem_set_laddr4(struct gemac_dev *gemac, MAC_ADDR *address);
+MAC_ADDR gem_get_laddr1(struct gemac_dev *gemac);
+MAC_ADDR gem_get_laddr2(struct gemac_dev *gemac);
+MAC_ADDR gem_get_laddr3(struct gemac_dev *gemac);
+MAC_ADDR gem_get_laddr4(struct gemac_dev *gemac);
+
+void gem_set_id_check1(struct gemac_dev *gemac, u32 id_check);
+void gem_set_id_check2(struct gemac_dev *gemac, u32 id_check);
+void gem_set_id_check3(struct gemac_dev *gemac, u32 id_check);
+void gem_set_id_check4(struct gemac_dev *gemac, u32 id_check);
+u32 gem_get_id_check1(struct gemac_dev *gemac);
+u32 gem_get_id_check2(struct gemac_dev *gemac);
+u32 gem_get_id_check3(struct gemac_dev *gemac);
+u32 gem_get_id_check4(struct gemac_dev *gemac);
+
+void gem_enable_len_check(struct gemac_dev *gemac);
+void gem_disable_len_check(struct gemac_dev *gemac);
+
+/* Interrupt handling and masking. */
+void gem_set_irq_stat(struct gemac_dev *gemac, u32 irq_status);
+u32 gem_get_irq_stat(struct gemac_dev *gemac);
+
+void gem_enable_irq(struct gemac_dev *gemac, u32 irq_en);
+void gem_mask_irq(struct gemac_dev *gemac, u32 irq_mask);
+u32 gem_get_irq_mask(struct gemac_dev *gemac);
+
+/* Transmit control. */
+int gem_start_tx(struct gemac_dev *gemac);
+void gem_stop_tx(struct gemac_dev *gemac);
+void gem_abort_tx(struct gemac_dev *gemac);
+int gem_restart_tx(struct gemac_dev *gemac);
+int gem_transmitting(struct gemac_dev *gemac);
+u32 gem_get_tx_stat(struct gemac_dev *gemac);
+void gem_reset_tx_stat(struct gemac_dev *gemac, u32 rst_status);
+void gem_reset_tx_q(struct gemac_dev *gemac);
+
+/* Receive control. */
+int gem_enable_rx(struct gemac_dev *gemac);
+void gem_disable_rx(struct gemac_dev *gemac);
+void gem_reset_rx_q(struct gemac_dev *gemac);
+
+int gem_receive_on(struct gemac_dev *gemac);
+u32 gem_get_rx_stat(struct gemac_dev *gemac);
+void gem_reset_rx_stat(struct gemac_dev *gemac, u32 rst_status);
+
+void gem_enable_rx_jmb(struct gemac_dev *gemac);
+void gem_disable_rx_jmb(struct gemac_dev *gemac);
+
+void gem_enable_vlan_only(struct gemac_dev *gemac);
+void gem_disable_vlan_only(struct gemac_dev *gemac);
+
+/* Snapshot of statistic registers */
+void gem_enable_rd_snap(struct gemac_dev *gemac);
+void gem_disable_rd_snap(struct gemac_dev *gemac);
+void gem_take_snap(struct gemac_dev *gemac);
+
+/* Debug options. */
+void gem_stats_wr_en(struct gemac_dev *gemac);
+void gem_stats_wr_off(struct gemac_dev *gemac);
+void gem_stats_inc(struct gemac_dev *gemac);
+void gem_stats_clr(struct gemac_dev *gemac);
+
+void gem_enable_bp(struct gemac_dev *gemac);
+void gem_disable_bp(struct gemac_dev *gemac);
+
+void gem_en_retry_test(struct gemac_dev *gemac);
+void gem_dis_retry_test(struct gemac_dev *gemac);
+
+GEM_STATS gem_get_stats(struct gemac_dev *gemac);
+void gem_set_stats(struct gemac_dev *gemac, GEM_STATS *stats);
+
+/* Generic register access interface. */
+u32 gem_register_rd(struct gemac_dev *gemac, u32 reg_addr);
+int gem_register_wr(struct gemac_dev *gemac, u32 reg_addr, u32 data);
+
+/******************************************************************************/
+
+#endif

drivers/comcerto_gem_AL.c

diff --git a/drivers/comcerto_gem_AL.c b/drivers/comcerto_gem_AL.c
new file mode 100644
index 0000000..6e6231c
--- /dev/null
+++ b/drivers/comcerto_gem_AL.c
@@ -0,0 +1,1825 @@
+/*------------------------------------------------------------------------------
+ *
+ *                                       Copyright (c) 2003
+ *            CADENCE                    CADENCE DESIGN FOUNDRY
+ *                                       All rights reserved.
+ *
+ *------------------------------------------------------------------------------
+ *
+ *   Filename       :   gem_AL.c
+ *
+ *   Author         :   Steven Ho, DICS, LDC
+ *
+ *   Date           :   9th Oct 2001
+ *
+ *   Limitations    :   Due to the use of bit-fields, only little endian
+ *                      architectures is currently supported.  The header file
+ *                      will need to be updated for other architectures.
+ *
+ *------------------------------------------------------------------------------
+ *   Description    :   A Hardware Abstraction Layer for the Cadence Gigabit
+ *                      Ethernet MAC (gem).
+ *                      This comprises of a set of functions and macros to
+ *                      provide a simple abstracted view to operating the MAC
+ *                      enabling the MAC software development in the minimal
+ *                      amount of time.
+ *
+ *------------------------------------------------------------------------------
+ *   Revision Control
+ *
+ *------------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+#include <asm/byteorder.h>
+#include <malloc.h>
+#include <net.h>
+#include <command.h>
+
+#if defined(CONFIG_COMCERTO_GEMAC)
+#include "comcerto_gem.h"
+/******************************************************************************/
+
+/* Some functions to set/reset and get specific bits in the MAC registers
+ * Note that all functions operate on a read-modify-write basis
+ */
+
+/******************************************************************************/
+/*
+ * Function to start transmission on the specified device.  The parameter to
+ * this function is simply a pointer to the struct gemac_dev structure.
+ * This function should be called after the relevant queues and data has been
+ * set up, however it will check if the number of queue elements is zero first.
+ * Note that this function will also enable tx even if it was previously not set
+ *
+ * Return value:
+ *  0   :   OK
+ *  -1  :   Transmit queue not valid.
+ */
+/******************************************************************************/
+int gem_start_tx(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_TX_START | GEM_TX_EN);
+	return 0;
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Halt transmission after current frame has completed.  This is accomplished
+ * simply by writing to the GEM_TX_HALT bit in the network control register,
+ * which should cause the MAC to complete its current frame then stop.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_stop_tx(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_TX_HALT);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Abort transmission immediately WITHOUT waiting for completion of any current
+ * frame.
+ * Note that after this operation, the transmit buffer descriptor will be reset
+ * to point to the first buffer in the descriptor list!
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_abort_tx(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) &= __cpu_to_le32(~(GEM_TX_START | GEM_TX_EN));
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Obtains status of transmission circuitry, whether it is transmitting or idle.
+ *
+ * Return value:
+ *  0   :   Transmitter is idle.
+ *  1   :   Transmitter active.
+ */
+/******************************************************************************/
+int gem_transmitting(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_TX_STATUS) & __cpu_to_le32(GEM_TX_GO)) == GEM_TX_GO);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable the receive circuitry.  This should be performed only after the
+ * buffers and the descriptor queues have been set up, otherwise unpredictable
+ * results may occur.
+ *
+ * Return value:
+ *  0   :   OK
+ *  -1  :   Receive queue not valid.
+ */
+/******************************************************************************/
+int gem_enable_rx(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_RX_EN);
+	return 0;
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable the receive circuitry.  This will stop reception of any frame
+ * immediately, note that the descriptor pointer is not changed.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_disable_rx(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) &= __cpu_to_le32(~GEM_RX_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Obtain the status of the receive circuitry, whether it is enabled.
+ *
+ * Return value:
+ *  0   :   Receive circuitry disabled.
+ *  -1  :   Receive circuits enabled.
+ */
+/******************************************************************************/
+int gem_receive_on(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) & __cpu_to_le32(GEM_RX_EN)) == GEM_RX_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Set the loopback mode of the MAC.  This can be either no loopback for normal
+ * operation, local loopback through MAC internal loopback module or PHY
+ * loopback for external loopback through a PHY.  This asserts the external loop
+ * pin.
+ * The function parameters are a pointer to the device and an enumerated type
+ * specifying the type of loopback required.
+ *
+ * Note: if an invalid loopback mode is specified, loop back will be disabled.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_set_loop(struct gemac_dev *gemac,	/* Pointer to the device structure. */
+		  MAC_LOOP gem_loop	/* Loopback mode. */
+    ) {
+	switch (gem_loop) {
+	case LB_LOCAL:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) &= __cpu_to_le32(~GEM_LB_PHY);
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_LB_MAC);
+		break;
+	case LB_EXT:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) &= __cpu_to_le32(~GEM_LB_MAC);
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_LB_PHY);
+		break;
+	default:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) &= __cpu_to_le32(~(GEM_LB_MAC | GEM_LB_PHY));
+	}
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Get the loopback mode of the MAC.  This can be either no loopback for normal
+ * operation, local loopback through MAC internal loopback module or PHY
+ * loopback for external loopback through a PHY.  This asserts the external loop
+ * pin.
+ * The function parameters are a pointer to the device.
+ *
+ * Return value:
+ *  LB_LOCAL    :   Local loop back active.
+ *  LB_EXT      :   External loop back active.
+ *  LB_NONE     :   Loop back disabled.
+ *  -1          :   Unknown mode.
+ */
+/******************************************************************************/
+MAC_LOOP gem_get_loop(struct gemac_dev *gemac)
+{
+	u32 lb_mode;
+
+	lb_mode = *(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) & (GEM_LB_PHY | GEM_LB_MAC);
+
+	switch (lb_mode) {
+	case GEM_LB_MAC:
+		return LB_LOCAL;
+		break;
+	case GEM_LB_PHY:
+		return LB_EXT;
+		break;
+	case 0:
+		return LB_NONE;
+		break;
+	default:
+		return -1;
+	}
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Activate the Management interface.  This is required to program the PHY
+ * registers through the MDIO port.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_enable_MDIO(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_MDIO_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable the Management interface.  In this state, the MDIO is placed in a
+ * high impedance state and the MDC clock is driven low.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_disable_MDIO(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) &= __cpu_to_le32(~GEM_MDIO_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable writing to the statistic registers.  This is for debug purposes only
+ * and should not be active during normal operation.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_stats_wr_en(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_STATS_WR_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable writing to the statistic registers.  Under normal operation this is
+ * not necessary as the writing to statistics registers should be off by default
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_stats_wr_off(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) &= __cpu_to_le32(~GEM_STATS_WR_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Increment all the statistic registers by 1.  This is for debug purposes only.
+ * Note that the statistic registers are automatically cleared on read!
+ *
+ * No return value.
+ */
+/******************************************************************************/
+void gem_stats_inc(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_STATS_INC);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Clear all the statistic registers.
+ *
+ * No return value.
+ */
+/******************************************************************************/
+void gem_stats_clr(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_STATS_CLR);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable pause frame reception.  With this enabled, if a valid pause frame is
+ * received, transmission will halt for the specified time after the current
+ * frame has completed transmission.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_enable_pause_rx(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_RX_PAUSE_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable pause frame reception.  Incoming pause frames are ignored.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_disable_pause_rx(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_RX_PAUSE_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable copy of received pause frame.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_enable_pause_cpy(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_RX_NO_PAUSE);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable copy of received pause frame.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_disable_pause_cpy(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_RX_NO_PAUSE);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Send a pause frame with zero quantum.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_send_0q_pause(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_TX_0Q_PAUSE);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Send a normal pause frame.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_send_pause(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_TX_PAUSE);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Set transmit pause quantum.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_set_tx_pause_q(struct gemac_dev *gemac, u32 gem_pause)
+{
+	*(volatile u32 *)(gemac->registers + GEM_TX_PAUSE_QUANT) = __cpu_to_le32(gem_pause);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Read transmit pause quantum.
+ *
+ * Return values:
+ * 0-65535: transmit pause quantum.
+ */
+/******************************************************************************/
+u32 gem_get_tx_pause_q(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_TX_PAUSE_QUANT)));
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Set retry test bit, this is used for debug purposes only to speed up testing.
+ * This should not be enabled for normal operation.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_en_retry_test(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_RETRY_TEST);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable retry test bit.  For normal operation this bit should not be set.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_dis_retry_test(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_RETRY_TEST);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable external address match via the eam pin, which when active will copy
+ * the current frame to memory.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_enable_eam(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_EAM_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable external address match capability.  The MAC will ignore the status of
+ * the eam pin.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_disable_eam(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_EAM_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable storing of the receive frame check sequence into memory.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_enable_fcs_rx(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_RX_NO_FCS);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable storing of the receive frame check sequence into memory.  The last 4
+ * bytes from the incoming frame will be checked for valid CRC, however this
+ * will not be stored into memory.  The frame length will be updated
+ * accordingly.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_disable_fcs_rx(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_RX_NO_FCS);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable reception of long frames up to 1536 bytes in length.
+ * These are not standard IEEE 802.3 frames.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_enable_1536_rx(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_FRAME_1536);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable reception of frames greater than 1518 bytes in length.
+ * This is normal operation mode for the MAC for compatibility with IEEE 802.3
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_disable_1536_rx(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_FRAME_1536);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable reception of unicast hashed frames.  The frame will be received when
+ * the 6 bit hash function of the frame's destination address points a bit that
+ * is set in the 64-bit hash register and is signalled as a unicast frame.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_enable_unicast(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_UNICAST_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable reception of unicast hashed frames.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_disable_unicast(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_UNICAST_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable reception of multicast hashed frames.  The frame will be received when
+ * the 6 bit hash function of the frame's destination address points a bit that
+ * is set in the 64-bit hash register and is signalled as a multicast frame.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_enable_multicast(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_MULTICAST_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable reception of multicast hashed frames.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_disable_multicast(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_MULTICAST_EN);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Allow reception of broadcast frames (frames with address set to all 1's)
+ * This is normal operating mode for the MAC.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_allow_broadcast(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_NO_BROADCAST);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Do not allow reception of broadcast frames, such frames will be ignored.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_no_broadcast(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_NO_BROADCAST);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable copy all frames.  In this mode, the MAC will copy all valid received
+ * frames to memory regardless of the destination address.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_enable_copy_all(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_COPY_ALL);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Do not copy all frames.  Normal operating mode for the MAC, frames will only
+ * be copied to memory if it matches one of the specific or hash addresses.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_disable_copy_all(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_COPY_ALL);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Set MAC into full duplex mode.  The crs and col signals will be ignored in
+ * this mode.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_full_duplex(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->baseaddr + GEM_CFG) |= __cpu_to_le32(GEM_CONF_DUPLEX_GEM_FULL);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Set MAC into half duplex mode.  The crs and col signals are used to detect
+ * collisions and perform deference where necessary.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_half_duplex(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->baseaddr + GEM_CFG) &= __cpu_to_le32(~GEM_CONF_DUPLEX_GEM_FULL);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Set the operating speed of the MAC, for 10 and 100Mb modes, this has no
+ * effect on the MAC functionality, but simply asserts an external speed pin
+ * accordingly.
+ * For 1G modes, this will set the MAC into the appropriate operating mode by
+ * switching to either the GMII or TBI interface depending on required mode.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_set_speed(struct gemac_dev *gemac, MAC_SPEED gem_speed)
+{
+	switch (gem_speed) {
+	case SPEED_10M:
+		*(volatile u32 *)(gemac->baseaddr + GEM_CFG) = (*(volatile u32 *)(gemac->baseaddr + GEM_CFG) & __cpu_to_le32(~GEM_CONF_SPEED_MASK)) | __cpu_to_le32(GEM_CONF_SPEED_SEL_GEM | GEM_CONF_SPEED_GEM_10M);
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_PCS_SEL);
+		break;
+	case SPEED_100M:
+		*(volatile u32 *)(gemac->baseaddr + GEM_CFG) = (*(volatile u32 *)(gemac->baseaddr + GEM_CFG) & __cpu_to_le32(~GEM_CONF_SPEED_MASK)) | __cpu_to_le32(GEM_CONF_SPEED_SEL_GEM | GEM_CONF_SPEED_GEM_100M);
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_PCS_SEL);
+		break;
+	case SPEED_1000M:
+		*(volatile u32 *)(gemac->baseaddr + GEM_CFG) = (*(volatile u32 *)(gemac->baseaddr + GEM_CFG) & __cpu_to_le32(~GEM_CONF_SPEED_MASK)) | __cpu_to_le32(GEM_CONF_SPEED_SEL_GEM | GEM_CONF_SPEED_GEM_1G);
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_PCS_SEL);
+		break;
+	case SPEED_1000M_PCS:
+		*(volatile u32 *)(gemac->baseaddr + GEM_CFG) = (*(volatile u32 *)(gemac->baseaddr + GEM_CFG) & __cpu_to_le32(~GEM_CONF_SPEED_MASK)) | __cpu_to_le32(GEM_CONF_SPEED_SEL_GEM | GEM_CONF_SPEED_GEM_1G);
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_PCS_SEL);
+		break;
+	default:
+		*(volatile u32 *)(gemac->baseaddr + GEM_CFG) = (*(volatile u32 *)(gemac->baseaddr + GEM_CFG) & __cpu_to_le32(~GEM_CONF_SPEED_MASK)) | __cpu_to_le32(GEM_CONF_SPEED_SEL_GEM | GEM_CONF_SPEED_GEM_100M);
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_PCS_SEL);
+	}
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Get the operating speed of the MAC, currently this has no functional effect
+ * on the MAC.
+ *
+ * This function returns an enumerated value cast into an int.  This is for
+ * backward compatibility with the macb driver.
+ *
+ * Return value:
+ *  SPEED_10M   :   MAC in 10Mb/s mode.
+ *  SPEED_100M  :   MAC in 100Mb/s mode.
+ *  SPEED_1000M :   MAC in 1G mode with GMII interface.
+ *  SPEED_1000M_PCS :   MAC in 1G mode with PCS interface.
+ */
+/******************************************************************************/
+MAC_SPEED gem_get_speed(struct gemac_dev *gemac)
+{
+
+	if (*(volatile u32 *)(gemac->baseaddr + GEM_CFG) & __cpu_to_le32(GEM_CONF_SPEED_SEL_GEM)) {
+		if (*(volatile u32 *)(gemac->baseaddr + GEM_CFG) & __cpu_to_le32(GEM_CONF_SPEED_GEM_1G)) {
+			if (*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) & __cpu_to_le32(GEM_PCS_SEL))
+				return (SPEED_1000M_PCS);
+			else
+				return (SPEED_1000M);
+		} else {
+			if (*(volatile u32 *)(gemac->baseaddr + GEM_CFG) & __cpu_to_le32(GEM_CONF_SPEED_GEM_100M))
+				return (SPEED_100M);
+			else
+				return (SPEED_10M);
+		}
+	} else {
+		if (*(volatile u32 *)(gemac->baseaddr + GEM_CFG) & __cpu_to_le32(GEM_CONF_SPEED_PHY_1G)) {
+			if (*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) & __cpu_to_le32(GEM_PCS_SEL))
+				return (SPEED_1000M_PCS);
+			else
+				return (SPEED_1000M);
+		} else {
+			if (*(volatile u32 *)(gemac->baseaddr + GEM_CFG) & __cpu_to_le32(GEM_CONF_SPEED_PHY_100M))
+				return (SPEED_100M);
+			else
+				return (SPEED_10M);
+		}
+	}
+}
+
+/******************************************************************************/
+#if defined(CONFIG_COMCERTO_100)
+/******************************************************************************/
+/*
+ * Set AMBA AHB bus width.
+ * AMBA_AHB_32:
+ * AMBA_AHB_64:
+ * AMBA_AHB_128:
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_set_ahb_width(struct gemac_dev *gemac, MAC_AHB_WIDTH gem_buswidth)
+{
+	switch (gem_buswidth) {
+	case AMBA_AHB_128:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_AHB_WIDTH1);
+		break;
+	case AMBA_AHB_64:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_AHB_WIDTH1);
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_AHB_WIDTH0);
+		break;
+	case AMBA_AHB_32:
+	default:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32((~GEM_AHB_WIDTH1) & (~GEM_AHB_WIDTH0));
+	}
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Get AMBA AHB bus width. 
+ * It returns one of the following values:
+ * AMBA_AHB_32, AMBA_AHB_64, AMBA_AHB_128,
+ */
+/******************************************************************************/
+MAC_AHB_WIDTH gem_get_ahb_width(struct gemac_dev *gemac)
+{
+	if (*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) & __cpu_to_le32(GEM_AHB_WIDTH1)) {
+		return AMBA_AHB_128;
+	} else {
+		if (*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) & __cpu_to_le32(GEM_AHB_WIDTH0)) {
+			return AMBA_AHB_64;
+		} else {
+			return AMBA_AHB_32;
+		}
+	}
+}
+
+/******************************************************************************/
+#endif
+/******************************************************************************/
+/*
+ * Set MDC clock division.
+ * MDC_DIV_8:
+ * MDC_DIV_16:
+ * MDC_DIV_32:
+ * MDC_DIV_48:
+ * MDC_DIV_64:
+ * MDC_DIV_96:
+ * MDC_DIV_128:
+ * MDC_DIV_224:
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_set_mdc_div(struct gemac_dev *gemac, MAC_MDC_DIV gem_mdcdiv)
+{
+	switch (gem_mdcdiv) {
+	case MDC_DIV_8:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32((~GEM_MDC_DIV2) & (~GEM_MDC_DIV1) & (~GEM_MDC_DIV0));
+		break;
+	case MDC_DIV_16:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32((~GEM_MDC_DIV2) & (~GEM_MDC_DIV1));
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_MDC_DIV0);
+		break;
+	case MDC_DIV_32:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32((~GEM_MDC_DIV2) & (~GEM_MDC_DIV0));
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_MDC_DIV1);
+		break;
+	case MDC_DIV_48:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_MDC_DIV1 | GEM_MDC_DIV0);
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_MDC_DIV2);
+		break;
+	case MDC_DIV_64:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32((~GEM_MDC_DIV1) & (~GEM_MDC_DIV0));
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_MDC_DIV2);
+		break;
+	case MDC_DIV_96:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_MDC_DIV2 | GEM_MDC_DIV0);
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_MDC_DIV1);
+		break;
+	case MDC_DIV_128:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_MDC_DIV2 | GEM_MDC_DIV1);
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_MDC_DIV0);
+		break;
+	case MDC_DIV_224:
+		*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_MDC_DIV2 | GEM_MDC_DIV1 | GEM_MDC_DIV0);
+		break;
+	}
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Get MDC clock division.
+ * It returns one of this values:
+ * MDC_DIV_8, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, MDC_DIV_64, MDC_DIV_96,
+ * MDC_DIV_128, MDC_DIV_224.
+ */
+/******************************************************************************/
+MAC_MDC_DIV gem_get_mdc_div(struct gemac_dev *gemac)
+{
+	if (*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) & __cpu_to_le32(GEM_MDC_DIV2)) {
+		if (*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) & __cpu_to_le32(GEM_MDC_DIV1)) {
+			if (*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) & __cpu_to_le32(GEM_MDC_DIV0)) {
+				return MDC_DIV_224;
+			} else {
+				return MDC_DIV_128;
+			}
+		} else {
+			if (*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) & __cpu_to_le32(GEM_MDC_DIV0)) {
+				return MDC_DIV_96;
+			} else {
+				return MDC_DIV_64;
+			}
+		}
+	} else {
+		if (*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) & __cpu_to_le32(GEM_MDC_DIV1)) {
+			if (*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) & __cpu_to_le32(GEM_MDC_DIV0)) {
+				return MDC_DIV_48;
+			} else {
+				return MDC_DIV_32;
+			}
+		} else {
+			if (*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) & __cpu_to_le32(GEM_MDC_DIV0)) {
+				return MDC_DIV_16;
+			} else {
+				return MDC_DIV_8;
+			}
+		}
+	}
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable to read snapshot values of statistic registers.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_enable_rd_snap(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_READ_SNAP);
+}
+
+/******************************************************************************/
+/*
+ * Disable to read snapshot values of statistic registers.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_disable_rd_snap(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) &= __cpu_to_le32(~GEM_READ_SNAP);
+}
+
+/******************************************************************************/
+/*
+ * Take snapshot of statistic registers. Writing a one will record the current 
+ * value of all statistics registers in the snapshot registers and clear the 
+ * statistics registers.
+ *
+ * There is no return value for this function.
+ */
+/******************************************************************************/
+void gem_take_snap(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) |= __cpu_to_le32(GEM_TAKE_SNAP);
+}
+
+/******************************************************************************/
+/*
+ * Get the current link status as returned by the PHY
+ *
+ * Return value:
+ *  0   :   Link is down.
+ *  1   :   Link active.
+ */
+/******************************************************************************/
+int gem_link_status(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_NET_STATUS) & __cpu_to_le32(GEM_LINK_STATUS)) == GEM_LINK_STATUS);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Check if the PHY management logic is idle, i.e. completed management
+ * operation.
+ *
+ * Return value:
+ *  0   :   PHY management not-idle.
+ *  1   :   PHY management completed.
+ */
+/******************************************************************************/
+int gem_phy_man_idle(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->phyregisters + GEM_NET_STATUS) & __cpu_to_le32(GEM_PHY_IDLE)) == GEM_PHY_IDLE);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Get the value of the transmit status register.
+ * The return value is an unsigned 32-bit integer containing the contents of the
+ * register.  This should be masked appropriately to obtain the relevant status.
+ *
+ * Return value:
+ * Returns current value of transmit status register.
+ */
+/******************************************************************************/
+u32 gem_get_tx_stat(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_TX_STATUS)));
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Reset the specified bits of the transmit status register.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_reset_tx_stat(struct gemac_dev *gemac,	/* Pointer to device structure. */
+		       u32 rst_status	/* Status to reset. */
+    ) {
+	*(volatile u32 *)(gemac->registers + GEM_TX_STATUS) |= __cpu_to_le32(rst_status);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Get the value of the receive status register.
+ * The return value is an unsigned 32-bit integer containing the contents of the
+ * register.  This should be masked appropriately to obtain the relevant status.
+ *
+ * Returns current receive status.
+ */
+/******************************************************************************/
+u32 gem_get_rx_stat(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_RX_STATUS)));
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Reset the specified bits of the receive status register.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_reset_rx_stat(struct gemac_dev *gemac,	/* Pointer to device structure. */
+		       u32 rst_status	/* Status to reset. */
+    ) {
+	*(volatile u32 *)(gemac->registers + GEM_RX_STATUS) |= __cpu_to_le32(rst_status);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable jumbo frames to be accepted.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_enable_rx_jmb(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_RX_JUMBO);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable jumbo frames to be accepted.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_disable_rx_jmb(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_RX_JUMBO);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable only VLAN frames to be accepted, all other frames will be discarded.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_enable_vlan_only(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_VLAN_ONLY);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable VLAN frame only mode. All frames will be accepted.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_disable_vlan_only(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_VLAN_ONLY);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Read the interrupt status register.
+ * This returns an unsigned 32-bit integer with the current interrupt status,
+ * this should be masked appropriately to get the required status.
+ * Note that the interrupt status register is automatically reset on read, so
+ * the returned value should be stored if further processing required.
+ *
+ * Returns the current interrupt status.
+ */
+/******************************************************************************/
+u32 gem_get_irq_stat(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_IRQ_STATUS)));
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Set specified bits in the interrupt status register.
+ * This can be used for debug purposes to manually activate an interrupt.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_set_irq_stat(struct gemac_dev *gemac, u32 irq_status)
+{
+	*(volatile u32 *)(gemac->registers + GEM_IRQ_STATUS) |= __cpu_to_le32(irq_status);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable specified interrupts.
+ * The specified interrupt bits are enabled by unmasking them.
+ * Note that this appends to the existing interrupt enable list.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_enable_irq(struct gemac_dev *gemac, u32 irq_en)
+{
+	*(volatile u32 *)(gemac->registers + GEM_IRQ_ENABLE) |= __cpu_to_le32(irq_en);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable specified interrupts.
+ * The specified interrupts are masked out so that they do not generate an
+ * interrupt.
+ * Note that this appends to the existing interrupt mask list.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_mask_irq(struct gemac_dev *gemac, u32 irq_mask)
+{
+	*(volatile u32 *)(gemac->registers + GEM_IRQ_DISABLE) |= __cpu_to_le32(irq_mask);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Obtain the current interrupt mask value.
+ * The return value indicates which interrupts are currently masked out i.e. do
+ * not generate an interrupt.
+ *
+ * Returns the interrupt mask status.
+ */
+/******************************************************************************/
+u32 gem_get_irq_mask(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_IRQ_MASK)));
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Write to the PHY management registers.
+ * This function simply sets off the PHY management operation, completion will
+ * be indicated by an interrupt.
+ * The input parameters are the PHY address, register address, and the 16-bit
+ * data to be written.
+ * Note that the MDIO enable register must be on.
+ *
+ * Return value:
+ *  0   :   OK
+ *  -1  :   Invalid input range.
+ */
+/******************************************************************************/
+int gem_phy_man_wr(struct gemac_dev *gemac, u8 phy_addr, u8 reg_addr, u32 data) {
+	u32 write_data;
+
+	if ((phy_addr > 0x1F) || (reg_addr > 0x1F) || (data > 0xFFFF)) {
+		return -1;
+	} else {
+		write_data = 0x50020000;
+		write_data |= ((phy_addr << 23) | (reg_addr << 18) | data);
+		*(volatile u32 *)(gemac->phyregisters + GEM_PHY_MAN) = __cpu_to_le32(write_data);
+		return 0;
+	}
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Perform PHY management register read operation.
+ * This function simply sets off the PHY management operation, completion will
+ * be indicated by an interrupt.
+ * The input parameters are the PHY address and the register address to be read
+ *
+ * Return value:
+ *  0   :   OK
+ *  -1  :   Invalid input range.
+ */
+/******************************************************************************/
+int gem_phy_man_rd(struct gemac_dev *gemac, u8 phy_addr, u8 reg_addr) {
+	u32 write_data;
+
+	if ((phy_addr > 0x1F) || (reg_addr > 0x1F)) {
+		return -1;
+	} else {
+		write_data = 0x60020000;
+		write_data |= ((phy_addr << 23) | (reg_addr << 18));
+		*(volatile u32 *)(gemac->phyregisters + GEM_PHY_MAN) = __cpu_to_le32(write_data);
+		return 0;
+	}
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Read the data section of the PHY management register.  After a read operation
+ * the data from the PHY will be stored here.
+ *
+ * Return value is the lower 16-bits of the PHY management register.
+ */
+/******************************************************************************/
+u32 gem_phy_man_data(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->phyregisters + GEM_PHY_MAN) & __cpu_to_le32(0xFFFF)));
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Read the pause time register.
+ *
+ * Returns the current value in the pause time register which will
+ * decrement when the MAC has gone into pause mode.
+ */
+/******************************************************************************/
+u32 gem_pause_time(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_RX_PAUSE_TIME)));
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Set the id-check registers of the MAC.
+ * These registers are used to check the type-id field of the incoming frames, 
+ * if matched, the appropriate status bit will be set in word 1 of the receive
+ * descriptor for that frame.
+ * The input parameter is truncated to 16-bits.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_set_id_check1(struct gemac_dev *gemac, u32 id_check) {
+	*(volatile u32 *)(gemac->registers + GEM_ID_CHECK1) = __cpu_to_le32(id_check & 0xFFFF);
+}
+
+void gem_set_id_check2(struct gemac_dev *gemac, u32 id_check) {
+	*(volatile u32 *)(gemac->registers + GEM_ID_CHECK2) = __cpu_to_le32(id_check & 0xFFFF);
+}
+
+void gem_set_id_check3(struct gemac_dev *gemac, u32 id_check) {
+	*(volatile u32 *)(gemac->registers + GEM_ID_CHECK3) = __cpu_to_le32(id_check & 0xFFFF);
+}
+
+void gem_set_id_check4(struct gemac_dev *gemac, u32 id_check) {
+	*(volatile u32 *)(gemac->registers + GEM_ID_CHECK4) = __cpu_to_le32(id_check & 0xFFFF);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Get the value of the id-check registers in the MAC.
+ *
+ * Return value:
+ *  Value of ID check register.
+ */
+/******************************************************************************/
+u32 gem_get_id_check1(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_ID_CHECK1)));
+}
+
+u32 gem_get_id_check2(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_ID_CHECK2)));
+}
+
+u32 gem_get_id_check3(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_ID_CHECK3)));
+}
+
+u32 gem_get_id_check4(struct gemac_dev *gemac)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_ID_CHECK4)));
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Set the hash register of the MAC.
+ * This register is used for matching unicast and multicast frames.
+ * The parameter of this function should be a pointer to type MAC_ADDR as
+ * defined in the header file.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_set_hash(struct gemac_dev *gemac, MAC_ADDR *hash_addr) {
+	*(volatile u32 *)(gemac->registers + GEM_HASH_BOT) = hash_addr->bottom;
+	*(volatile u32 *)(gemac->registers + GEM_HASH_TOP) = hash_addr->top;
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Get the current value of the hash registers of the MAC.
+ *
+ * This function returns a value of type MAC_ADDR
+ */
+/******************************************************************************/
+MAC_ADDR gem_get_hash(struct gemac_dev *gemac)
+{
+	MAC_ADDR addr;
+
+	addr.bottom = *(volatile u32 *)(gemac->registers + GEM_HASH_BOT);
+	addr.top = *(volatile u32 *)(gemac->registers + GEM_HASH_TOP);
+
+	return addr;
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Setup all the specific address registers for the MAC.
+ * These registers are matched against incoming frames to determine whether the
+ * frame should be copied to memory.
+ * The input parameter to this function should be a pointer to type SPEC_ADDR
+ * as defined in the header file.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_set_address(struct gemac_dev *gemac, SPEC_ADDR *spec_addr)
+{
+	*(volatile u32 *)(gemac->registers + GEM_LADDR1_BOT) = spec_addr->one.bottom;
+	*(volatile u32 *)(gemac->registers + GEM_LADDR1_TOP) = spec_addr->one.top;
+	*(volatile u32 *)(gemac->registers + GEM_LADDR2_BOT) = spec_addr->two.bottom;
+	*(volatile u32 *)(gemac->registers + GEM_LADDR2_TOP) = spec_addr->two.top;
+	*(volatile u32 *)(gemac->registers + GEM_LADDR3_BOT) = spec_addr->three.bottom;
+	*(volatile u32 *)(gemac->registers + GEM_LADDR3_TOP) = spec_addr->three.top;
+	*(volatile u32 *)(gemac->registers + GEM_LADDR4_BOT) = spec_addr->four.bottom;
+	*(volatile u32 *)(gemac->registers + GEM_LADDR4_TOP) = spec_addr->four.top;
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Get the current set of specific match addresses for the MAC.
+ * Note that a pointer is not returned as this would give direct access to the
+ * MAC address space which may cause unpredictable behaviour if wrongly used.
+ *
+ * Return type is of type SPEC_ADDR as defined in the header file.
+ */
+/******************************************************************************/
+SPEC_ADDR gem_get_address(struct gemac_dev *gemac)
+{
+        SPEC_ADDR spec_addr;
+
+	spec_addr.one.bottom = *(volatile u32 *)(gemac->registers + GEM_LADDR1_BOT);
+	spec_addr.one.top = *(volatile u32 *)(gemac->registers + GEM_LADDR1_TOP);
+	spec_addr.two.bottom = *(volatile u32 *)(gemac->registers + GEM_LADDR2_BOT);
+	spec_addr.two.top = *(volatile u32 *)(gemac->registers + GEM_LADDR2_TOP);
+	spec_addr.three.bottom = *(volatile u32 *)(gemac->registers + GEM_LADDR3_BOT);
+	spec_addr.three.top = *(volatile u32 *)(gemac->registers + GEM_LADDR3_TOP);
+	spec_addr.four.bottom = *(volatile u32 *)(gemac->registers + GEM_LADDR4_BOT);
+	spec_addr.four.top = *(volatile u32 *)(gemac->registers + GEM_LADDR4_TOP);
+
+        return spec_addr;
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Set specific local addresses of the MAC.
+ * Rather than setting up all four specific addresses, this function sets them
+ * up individually.  The input parameter should be a pointer to type MAC_ADDR.
+ *
+ * There are no return values.
+ */
+/******************************************************************************/
+void gem_set_laddr1(struct gemac_dev *gemac, MAC_ADDR *address)
+{
+	*(volatile u32 *)(gemac->registers + GEM_LADDR1_BOT) = address->bottom;
+	*(volatile u32 *)(gemac->registers + GEM_LADDR1_TOP) = address->top;
+}
+
+void gem_set_laddr2(struct gemac_dev *gemac, MAC_ADDR *address)
+{
+	*(volatile u32 *)(gemac->registers + GEM_LADDR2_BOT) = address->bottom;
+	*(volatile u32 *)(gemac->registers + GEM_LADDR2_TOP) = address->top;
+}
+
+void gem_set_laddr3(struct gemac_dev *gemac, MAC_ADDR *address)
+{
+	*(volatile u32 *)(gemac->registers + GEM_LADDR3_BOT) = address->bottom;
+	*(volatile u32 *)(gemac->registers + GEM_LADDR3_TOP) = address->top;
+}
+
+void gem_set_laddr4(struct gemac_dev *gemac, MAC_ADDR *address)
+{
+	*(volatile u32 *)(gemac->registers + GEM_LADDR4_BOT) = address->bottom;
+	*(volatile u32 *)(gemac->registers + GEM_LADDR4_TOP) = address->top;
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Get specific local addresses of the MAC.
+ * This allows returning of a single specific address stored in the MAC.
+ *
+ * Return value if of type MAC_ADDR as defined in the header file.
+ */
+/******************************************************************************/
+MAC_ADDR gem_get_laddr1(struct gemac_dev *gemac)
+{
+	MAC_ADDR addr;
+
+	addr.bottom = *(volatile u32 *)(gemac->registers + GEM_LADDR1_BOT);
+	addr.top = *(volatile u32 *)(gemac->registers + GEM_LADDR1_TOP);
+
+	return addr;
+}
+
+MAC_ADDR gem_get_laddr2(struct gemac_dev *gemac)
+{
+	MAC_ADDR addr;
+
+	addr.bottom = *(volatile u32 *)(gemac->registers + GEM_LADDR2_BOT);
+	addr.top = *(volatile u32 *)(gemac->registers + GEM_LADDR2_TOP);
+
+	return addr;
+}
+
+MAC_ADDR gem_get_laddr3(struct gemac_dev *gemac)
+{
+	MAC_ADDR addr;
+
+	addr.bottom = *(volatile u32 *)(gemac->registers + GEM_LADDR3_BOT);
+	addr.top = *(volatile u32 *)(gemac->registers + GEM_LADDR3_TOP);
+
+	return addr;
+}
+
+MAC_ADDR gem_get_laddr4(struct gemac_dev *gemac)
+{
+	MAC_ADDR addr;
+
+	addr.bottom = *(volatile u32 *)(gemac->registers + GEM_LADDR4_BOT);
+	addr.top = *(volatile u32 *)(gemac->registers + GEM_LADDR4_TOP);
+
+	return addr;
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Obtain the statistics registers structure.
+ * type GEM_STATS as defined in the header file.
+ * Note that this operation is relatively slow as it is copying all the
+ * statistics register values rather than providing a pointer reference to them.
+ * Note also that the statistics registers will all be automatically cleared
+ * after this operation.
+ *
+ * Returns the entire statistics register block for the MAC in a structure of
+ * type GEM_STATS
+ */
+/******************************************************************************/
+GEM_STATS gem_get_stats(struct gemac_dev *gemac)
+{
+	return (*(GEM_STATS *)(gemac->registers + GEM_OCT_TX_BOT));
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Set the values of the statistics registers.
+ * This is for debug only and allows reading and writing to the statistic
+ * registers to verify functionality.
+ *
+ * There is no return value.
+ */
+/******************************************************************************/
+void gem_set_stats(struct gemac_dev *gemac, GEM_STATS *stats)
+{
+//	gemac->registers->stats = *stats;
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Write to a specific MAC memory address.  The defines in the header file
+ * should be used for this.
+ * Note: care should be taken when using this function so as not to pass null
+ * pointers or write to read only registers etc.
+ *
+ * Return value:
+ *  0   :   OK
+ *  -1  :   Invalid input range.
+ */
+/******************************************************************************/
+int gem_register_wr(struct gemac_dev *gemac, u32 reg_addr, u32 data)
+{
+	if (reg_addr > GEM_REG_TOP) {
+		return -1;
+	} else {
+		*(volatile u32 *)(gemac->registers + reg_addr) = __cpu_to_le32(data);
+		return 0;
+	}
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Read from a specific MAC memory address. The defines in the header file
+ * should be used for this.
+ * Note that the range of the address requested is not checked.
+ *
+ * Returns register contents.
+ */
+/******************************************************************************/
+u32 gem_register_rd(struct gemac_dev *gemac, u32 reg_addr)
+{
+	return (__le32_to_cpu(*(volatile u32 *)(gemac->registers + reg_addr)));
+}
+
+/******************************************************************************/
+/*
+ * Reset the MAC device to its default value and load up the MAC address stored
+ * in the header file into specific address 1.  The MAC will be held in
+ * quiescent state.
+ * This function should be called to initialise and check the device prior to
+ * setting up the buffer queues and enabling the MAC.  If it is called mid way
+ * through operation, the MAC is reset to default value and any pending frames
+ * will be lost.
+ * Note that the values in the struct gemac_dev software structure are not reset, only
+ * the MAC registers are reset.  This is to allow, if necessary to recover the
+ * buffers and reload them into the MAC, however prior to doing this, they
+ * should be cleared first.
+ *
+ * Return value:
+ *  0   :   OK
+ *  -1  :   Error in write/read check on initialisation.
+ */
+/******************************************************************************/
+int gem_reset(struct gemac_dev *gemac)
+{
+	MAC_ADDR zero_address = { 0x00000000, 0x00000000 };
+	MAC_ADDR enet_address = zero_address;
+	int stats_length;
+	int loop_i;
+
+	stats_length = sizeof(GEM_STATS) / 4;
+
+	/* Write to registers and set default values. */
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) = __cpu_to_le32(GEM_STATS_CLR | GEM_MDIO_ENABLED);
+#if defined(CONFIG_COMCERTO_100)
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) = __cpu_to_le32(GEM_DEF_DUPLEX);
+#else
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) = __cpu_to_le32(0);
+#endif
+	gem_set_loop(gemac, GEM_DEF_LOOP);
+	gem_set_mdc_div(gemac, GEM_DEF_PCLK_DIV);
+	gem_set_speed(gemac, GEM_DEF_SPEED);
+#if defined(CONFIG_COMCERTO_100)
+	gem_set_ahb_width(gemac, GEM_DEF_AHB_WIDTH);
+#endif
+
+	*(volatile u32 *)(gemac->registers + GEM_TX_STATUS) = __cpu_to_le32(0xFFFFFFFF);
+	*(volatile u32 *)(gemac->registers + GEM_RX_QPTR) = __cpu_to_le32(0x00000000);
+#if defined(CONFIG_COMCERTO_100)
+	*(volatile u32 *)(gemac->registers + GEM_TX_QPTR) = __cpu_to_le32(0x00000000);
+#endif
+	*(volatile u32 *)(gemac->registers + GEM_RX_STATUS) = __cpu_to_le32(0xFFFFFFFF);
+	*(volatile u32 *)(gemac->registers + GEM_IRQ_DISABLE) = __cpu_to_le32(0xFFFFFFFF);
+	*(volatile u32 *)(gemac->registers + GEM_IRQ_STATUS) = __cpu_to_le32(0x00000000);
+
+	gem_set_hash(gemac, &zero_address);
+	gem_set_laddr1(gemac, &enet_address);
+	gem_set_laddr2(gemac, &zero_address);
+	gem_set_laddr3(gemac, &zero_address);
+	gem_set_laddr4(gemac, &zero_address);
+
+	*(volatile u32 *)(gemac->registers + GEM_ID_CHECK1) = __cpu_to_le32(0x00000000);
+	*(volatile u32 *)(gemac->registers + GEM_ID_CHECK2) = __cpu_to_le32(0x00000000);
+	*(volatile u32 *)(gemac->registers + GEM_ID_CHECK3) = __cpu_to_le32(0x00000000);
+	*(volatile u32 *)(gemac->registers + GEM_ID_CHECK4) = __cpu_to_le32(0x00000000);
+
+	/* Now read back values and return if not correct. */
+	if ((*(volatile u32 *)(gemac->registers + GEM_ID_CHECK1) != __cpu_to_le32(0x00000000)) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_ID_CHECK2) != __cpu_to_le32(0x00000000)) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_ID_CHECK3) != __cpu_to_le32(0x00000000)) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_ID_CHECK4) != __cpu_to_le32(0x00000000)) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_LADDR4_BOT) != zero_address.bottom) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_LADDR4_TOP) != zero_address.top) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_LADDR3_BOT) != zero_address.bottom) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_LADDR3_TOP) != zero_address.top) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_LADDR2_BOT) != zero_address.bottom) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_LADDR2_TOP) != zero_address.top) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_LADDR1_BOT) != enet_address.bottom) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_LADDR1_TOP) != enet_address.top) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_HASH_BOT) != zero_address.bottom) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_HASH_TOP) != zero_address.top) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_IRQ_STATUS) != __cpu_to_le32(0x00000000)) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_IRQ_MASK) != __cpu_to_le32(0x0003FFFF)) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_RX_STATUS) != __cpu_to_le32(0x00000000)) ||
+#if defined(CONFIG_COMCERTO_100)
+	    (*(volatile u32 *)(gemac->registers + GEM_TX_QPTR) != __cpu_to_le32(0x00000000)) ||
+#endif
+	    (*(volatile u32 *)(gemac->registers + GEM_RX_QPTR) != __cpu_to_le32(0x00000000)) ||
+	    (*(volatile u32 *)(gemac->registers + GEM_TX_STATUS) != __cpu_to_le32(0x00000000))
+	    ) {
+		return -1;
+	} else if ((__le32_to_cpu((*(volatile u32 *)(gemac->registers + GEM_NET_CONTROL) & __cpu_to_le32(GEM_MDIO_EN))) != (0x00000000 | GEM_MDIO_ENABLED)) ||
+		   (gem_get_loop(gemac) != GEM_DEF_LOOP) ||
+		   //           (gem_get_speed(gemac) != GEM_DEF_SPEED)  ||
+		   (gem_get_mdc_div(gemac) != GEM_DEF_PCLK_DIV)
+	    ) {
+		return -1;
+	} else {
+		for (loop_i = 0; loop_i < stats_length; loop_i++) {
+			if (__le32_to_cpu(*(volatile u32 *)(gemac->registers + GEM_OCT_TX_BOT + 4 * loop_i)) != 0x00000000) {
+				return -1;
+			}
+		}
+
+		return 0;
+	}
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Enable length field checking feature.
+ * The length field check feature automatically discards frames that has a frame
+ * length smaller than that reported in the length field of the header.
+ *
+ * Note that in accordance with the IEEE spec, frames that are longer than that
+ * reported in length field is still accepted as a valid frame.
+ *
+ * This function has no return value.
+ */
+/******************************************************************************/
+void gem_enable_len_check(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) |= __cpu_to_le32(GEM_RX_LEN_CHK);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Disable length field checking feature.
+ *
+ * This function has no return value.
+ */
+/******************************************************************************/
+void gem_disable_len_check(struct gemac_dev *gemac)
+{
+	*(volatile u32 *)(gemac->registers + GEM_NET_CONFIG) &= __cpu_to_le32(~GEM_RX_LEN_CHK);
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Convert standard byte style ethernet address to format compatible with MAC.
+ *
+ * Input    :   Pointer to beginning of 6 byte address.
+ *              Pointer to MAC_ADDR structure.
+ * Return values:
+ *  0   :   OK
+ *  -1  :   Invalid inputs.
+ */
+/******************************************************************************/
+int gem_enet_addr_byte_mac(u8 *enet_byte_addr, MAC_ADDR *enet_addr)
+{
+	if ((enet_byte_addr == NULL) || (enet_addr == NULL)) {
+		return -1;
+	}
+    else
+    {
+#if defined(BE8_MODE)
+        enet_addr->bottom = ((enet_byte_addr[0] << 24) |
+                             (enet_byte_addr[1] << 16) |
+                             (enet_byte_addr[2] << 8) |
+                             enet_byte_addr[3]);
+        enet_addr->top = ((enet_byte_addr[4] << 24) |
+                          (enet_byte_addr[5] << 16));
+#else
+        enet_addr->bottom = enet_byte_addr[0] |
+                            (enet_byte_addr[1] << 8) |
+                            (enet_byte_addr[2] << 16) |
+                            (enet_byte_addr[3] << 24);
+        enet_addr->top = enet_byte_addr[4] |
+                         (enet_byte_addr[5] << 8);
+#endif
+        return 0;
+    }
+}
+
+/******************************************************************************/
+
+/******************************************************************************/
+/*
+ * Convert MAC type ethernet address to standard byte style ethernet address.
+ *
+ * Input    :   Pointer to beginning of free space for 6 byte address.
+ *              Pointer to MAC_ADDR structure.
+ * Return values:
+ *  0   :   OK
+ *  -1  :   Invalid inputs.
+ */
+/******************************************************************************/
+int gem_enet_addr_mac_byte(u8 *enet_byte_addr, MAC_ADDR *enet_addr)
+{
+	if ((enet_byte_addr == NULL) || (enet_addr == NULL)) {
+		return -1;
+	} 
+    else
+    {
+#if defined(BE8_MODE)
+        enet_byte_addr[0] = (enet_addr->bottom >> 24) & 0xFF;
+        enet_byte_addr[1] = (enet_addr->bottom >> 16) & 0xFF;
+        enet_byte_addr[2] = (enet_addr->bottom >> 8) & 0xFF;
+        enet_byte_addr[3] = (enet_addr->bottom) & 0xFF;
+        enet_byte_addr[4] = (enet_addr->top >> 24) & 0xFF;
+        enet_byte_addr[5] = (enet_addr->top >> 16) & 0xFF;
+#else
+        enet_byte_addr[0] = enet_addr->bottom & 0xFF;
+        enet_byte_addr[1] = (enet_addr->bottom >> 8) & 0xFF;
+        enet_byte_addr[2] = (enet_addr->bottom >> 16) & 0xFF;
+        enet_byte_addr[3] = (enet_addr->bottom >> 24) & 0xFF;
+
+        enet_byte_addr[4] = enet_addr->top & 0xFF;
+        enet_byte_addr[5] = (enet_addr->top >> 8) & 0xFF;
+#endif
+
+        return 0;
+    }
+}
+
+/******************************************************************************/
+
+#endif

drivers/nand/nand.c

diff --git a/drivers/nand/nand.c b/drivers/nand/nand.c
index 3899045..3bc8516 100644
--- a/drivers/nand/nand.c
+++ b/drivers/nand/nand.c
@@ -22,59 +22,98 @@
  */
 
 #include <common.h>
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-
 #include <nand.h>
+#include <errno.h>
+#include <cmd_confdefs.h>
+#include <config.h>
 
-#ifndef CFG_NAND_BASE_LIST
-#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
-#endif
+
+DECLARE_GLOBAL_DATA_PTR;
 
 int nand_curr_device = -1;
-nand_info_t nand_info[CFG_MAX_NAND_DEVICE];
 
-static struct nand_chip nand_chip[CFG_MAX_NAND_DEVICE];
-static ulong base_address[CFG_MAX_NAND_DEVICE] = CFG_NAND_BASE_LIST;
 
-static const char default_nand_name[] = "nand";
+nand_info_t nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
 
-extern void board_nand_init(struct nand_chip *nand);
+#ifndef CONFIG_SYS_NAND_SELF_INIT
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
+#endif
 
-static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
-			   ulong base_addr)
+static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];
+
+static unsigned long total_nand_size; /* in kiB */
+
+/* Register an initialized NAND mtd device with the U-Boot NAND command. */
+int nand_register(int devnum)
 {
-	mtd->priv = nand;
+	struct mtd_info *mtd;
 
-	nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
-	board_nand_init(nand);
+	if (devnum >= CONFIG_SYS_MAX_NAND_DEVICE)
+		return -EINVAL;
 
-	if (nand_scan(mtd, 1) == 0) {
-		if (!mtd->name)
-			mtd->name = (char *)default_nand_name;
-	} else
-		mtd->name = NULL;
+	mtd = &nand_info[devnum];
 
+	sprintf(dev_name[devnum], "nand%d", devnum);
+	mtd->name = dev_name[devnum];
+
+#ifdef CONFIG_MTD_DEVICE
+	/*
+	 * Add MTD device so that we can reference it later
+	 * via the mtdcore infrastructure (e.g. ubi).
+	 */
+	add_mtd_device(mtd);
+#endif
+
+	total_nand_size += mtd->size / 1024;
+
+	if (nand_curr_device == -1)
+		nand_curr_device = devnum;
+
+	return 0;
 }
 
+#ifndef CONFIG_SYS_NAND_SELF_INIT
+static void nand_init_chip(int i)
+{
+	struct mtd_info *mtd = &nand_info[i];
+	struct nand_chip *nand = &nand_chip[i];
+	ulong base_addr = base_address[i];
+	int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
+
+	if (maxchips < 1)
+		maxchips = 1;
+
+	mtd->priv = nand;
+	nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
+
+	if (board_nand_init(nand))
+		return;
+
+	if (nand_scan(mtd, maxchips))
+		return;
+
+	nand_register(i);
+}
+#endif
+
 void nand_init(void)
 {
+#ifdef CONFIG_SYS_NAND_SELF_INIT
+	board_nand_init();
+#else
 	int i;
-	unsigned int size = 0;
-	for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
-		nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]);
-		size += nand_info[i].size;
-		if (nand_curr_device == -1)
-			nand_curr_device = i;
-	}
-	printf("%lu MiB\n", size / (1024 * 1024));
 
-#ifdef CFG_NAND_SELECT_DEVICE
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_init_chip(i);
+#endif
+
+	printf("%lu MiB\n", total_nand_size / 1024);
+
+#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
 	/*
 	 * Select the chip in the board/cpu specific driver
 	 */
 	board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device);
 #endif
 }
-
-#endif

drivers/nand/nand_base.c

diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c
index b7a5d32..8225a39 100644
--- a/drivers/nand/nand_base.c
+++ b/drivers/nand/nand_base.c
@@ -7,41 +7,24 @@
  *   Basic support for AG-AND chips is provided.
  *
  *	Additional technical information is available on
- *	http://www.linux-mtd.infradead.org/tech/nand.html
+ *	http://www.linux-mtd.infradead.org/doc/nand.html
  *
  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
- * 		  2002 Thomas Gleixner (tglx@linutronix.de)
+ *		  2002-2006 Thomas Gleixner (tglx@linutronix.de)
  *
- *  02-08-2004  tglx: support for strange chips, which cannot auto increment
- *		pages on read / read_oob
- *
- *  03-17-2004  tglx: Check ready before auto increment check. Simon Bayes
- *		pointed this out, as he marked an auto increment capable chip
- *		as NOAUTOINCR in the board driver.
- *		Make reads over block boundaries work too
- *
- *  04-14-2004	tglx: first working version for 2k page size chips
- *
- *  05-19-2004  tglx: Basic support for Renesas AG-AND chips
- *
- *  09-24-2004  tglx: add support for hardware controllers (e.g. ECC) shared
- *		among multiple independend devices. Suggestions and initial patch
- *		from Ben Dooks <ben-mtd@fluff.org>
- *
- * Credits:
+ *  Credits:
  *	David Woodhouse for adding multichip support
  *
  *	Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  *	rework for 2K page size chips
  *
- * TODO:
+ *  TODO:
  *	Enable cached programming for 2k page size chips
  *	Check, if mtd->ecctype should be set to MTD_ECC_HW
  *	if we have HW ecc support.
  *	The AG-AND chips have nice features for speed improvement,
  *	which are not supported yet. Read / program 4 pages in one go.
- *
- * $Id: nand_base.c,v 1.126 2004/12/13 11:22:25 lavinen Exp $
+ *	BBT table is not serialized, has to be fixed
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -49,118 +32,120 @@
  *
  */
 
-/* XXX U-BOOT XXX */
-#if 0
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/types.h>
+#include <common.h>
+
+#define ENOTSUPP	524	/* Operation is not supported */
+
+#include <malloc.h>
+#include <watchdog.h>
+#include <linux/compiler.h>
+#include <linux/err.h>
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
-#include <linux/mtd/compatmac.h>
-#include <linux/interrupt.h>
-#include <linux/bitops.h>
-#include <asm/io.h>
+#include <linux/mtd/mtd-abi.h>
+#include <linux/mtd/bbm.h>
+#include <linux/mtd/nand_bch.h>
 
 #ifdef CONFIG_MTD_PARTITIONS
 #include <linux/mtd/partitions.h>
 #endif
 
-#endif
-
-#include <common.h>
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-
-#include <malloc.h>
-#include <watchdog.h>
-#include <linux/mtd/compat.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-
 #include <asm/io.h>
 #include <asm/errno.h>
 
-#ifdef CONFIG_JFFS2_NAND
-#include <jffs2/jffs2.h>
+/*
+ * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
+ * a flash.  NAND flash is initialized prior to interrupts so standard timers
+ * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
+ * which is greater than (max NAND reset time / NAND status read time).
+ * A conservative default of 200000 (500 us / 25 ns) is used as a default.
+ */
+#ifndef CONFIG_SYS_NAND_RESET_CNT
+#define CONFIG_SYS_NAND_RESET_CNT 200000
 #endif
 
 /* Define default oob placement schemes for large and small page devices */
-static struct nand_oobinfo nand_oob_8 = {
-	.useecc = MTD_NANDECC_AUTOPLACE,
+static struct nand_ecclayout nand_oob_8 = {
 	.eccbytes = 3,
 	.eccpos = {0, 1, 2},
-	.oobfree = { {3, 2}, {6, 2} }
+	.oobfree = {
+		{.offset = 3,
+		 .length = 2},
+		{.offset = 6,
+		 .length = 2} }
 };
 
-static struct nand_oobinfo nand_oob_16 = {
-	.useecc = MTD_NANDECC_AUTOPLACE,
+static struct nand_ecclayout nand_oob_16 = {
 	.eccbytes = 6,
 	.eccpos = {0, 1, 2, 3, 6, 7},
-	.oobfree = { {8, 8} }
+	.oobfree = {
+		{.offset = 8,
+		 . length = 8} }
 };
 
-static struct nand_oobinfo nand_oob_64 = {
-	.useecc = MTD_NANDECC_AUTOPLACE,
+static struct nand_ecclayout nand_oob_64 = {
 	.eccbytes = 24,
 	.eccpos = {
-		40, 41, 42, 43, 44, 45, 46, 47,
-		48, 49, 50, 51, 52, 53, 54, 55,
-		56, 57, 58, 59, 60, 61, 62, 63},
-	.oobfree = { {2, 38} }
+		   40, 41, 42, 43, 44, 45, 46, 47,
+		   48, 49, 50, 51, 52, 53, 54, 55,
+		   56, 57, 58, 59, 60, 61, 62, 63},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 38} }
 };
 
-/* This is used for padding purposes in nand_write_oob */
-static u_char ffchars[] = {
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+static struct nand_ecclayout nand_oob_128 = {
+	.eccbytes = 48,
+	.eccpos = {
+		   80, 81, 82, 83, 84, 85, 86, 87,
+		   88, 89, 90, 91, 92, 93, 94, 95,
+		   96, 97, 98, 99, 100, 101, 102, 103,
+		   104, 105, 106, 107, 108, 109, 110, 111,
+		   112, 113, 114, 115, 116, 117, 118, 119,
+		   120, 121, 122, 123, 124, 125, 126, 127},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 78} }
 };
 
-/*
- * NAND low-level MTD interface functions
- */
-static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
-static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
-static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
+static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
+			   int new_state);
 
-static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
-static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
-			  size_t * retlen, u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel);
-static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
-static int nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf);
-static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
-			   size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel);
-static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char *buf);
-/* XXX U-BOOT XXX */
-#if 0
-static int nand_writev (struct mtd_info *mtd, const struct kvec *vecs,
-			unsigned long count, loff_t to, size_t * retlen);
-static int nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs,
-			unsigned long count, loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel);
-#endif
-static int nand_erase (struct mtd_info *mtd, struct erase_info *instr);
-static void nand_sync (struct mtd_info *mtd);
+static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
+			     struct mtd_oob_ops *ops);
 
-/* Some internal functions */
-static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf,
-		struct nand_oobinfo *oobsel, int mode);
-#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
-static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int page, int numpages,
-	u_char *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode);
-#else
-#define nand_verify_pages(...) (0)
-#endif
+static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 
-static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state);
+static int check_offs_len(struct mtd_info *mtd,
+					loff_t ofs, uint64_t len)
+{
+	struct nand_chip *chip = mtd->priv;
+	int ret = 0;
+
+	/* Start address must align on block boundary */
+	if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
+		ret = -EINVAL;
+	}
+
+	/* Length must align on block boundary */
+	if (len & ((1 << chip->phys_erase_shift) - 1)) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
+					__func__);
+		ret = -EINVAL;
+	}
+
+	/* Do not allow past end of device */
+	if (ofs + len > mtd->size) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
+					__func__);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
 
 /**
  * nand_release_device - [GENERIC] release chip
@@ -168,33 +153,13 @@
  *
  * Deselect, release chip lock and wake up anyone waiting on the device
  */
-/* XXX U-BOOT XXX */
-#if 0
-static void nand_release_device (struct mtd_info *mtd)
+static void nand_release_device(struct mtd_info *mtd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 
 	/* De-select the NAND device */
-	this->select_chip(mtd, -1);
-	/* Do we have a hardware controller ? */
-	if (this->controller) {
-		spin_lock(&this->controller->lock);
-		this->controller->active = NULL;
-		spin_unlock(&this->controller->lock);
-	}
-	/* Release the chip */
-	spin_lock (&this->chip_lock);
-	this->state = FL_READY;
-	wake_up (&this->wq);
-	spin_unlock (&this->chip_lock);
+	chip->select_chip(mtd, -1);
 }
-#else
-static void nand_release_device (struct mtd_info *mtd)
-{
-	struct nand_chip *this = mtd->priv;
-	this->select_chip(mtd, -1);	/* De-select the NAND device */
-}
-#endif
 
 /**
  * nand_read_byte - [DEFAULT] read one byte from the chip
@@ -202,23 +167,10 @@
  *
  * Default read function for 8bit buswith
  */
-static u_char nand_read_byte(struct mtd_info *mtd)
+uint8_t nand_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *this = mtd->priv;
-	return readb(this->IO_ADDR_R);
-}
-
-/**
- * nand_write_byte - [DEFAULT] write one byte to the chip
- * @mtd:	MTD device structure
- * @byte:	pointer to data byte to write
- *
- * Default write function for 8it buswith
- */
-static void nand_write_byte(struct mtd_info *mtd, u_char byte)
-{
-	struct nand_chip *this = mtd->priv;
-	writeb(byte, this->IO_ADDR_W);
+	struct nand_chip *chip = mtd->priv;
+	return readb(chip->IO_ADDR_R);
 }
 
 /**
@@ -228,24 +180,10 @@
  * Default read function for 16bit buswith with
  * endianess conversion
  */
-static u_char nand_read_byte16(struct mtd_info *mtd)
+static uint8_t nand_read_byte16(struct mtd_info *mtd)
 {
-	struct nand_chip *this = mtd->priv;
-	return (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
-}
-
-/**
- * nand_write_byte16 - [DEFAULT] write one byte endianess aware to the chip
- * @mtd:	MTD device structure
- * @byte:	pointer to data byte to write
- *
- * Default write function for 16bit buswith with
- * endianess conversion
- */
-static void nand_write_byte16(struct mtd_info *mtd, u_char byte)
-{
-	struct nand_chip *this = mtd->priv;
-	writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
+	struct nand_chip *chip = mtd->priv;
+	return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 }
 
 /**
@@ -257,40 +195,26 @@
  */
 static u16 nand_read_word(struct mtd_info *mtd)
 {
-	struct nand_chip *this = mtd->priv;
-	return readw(this->IO_ADDR_R);
-}
-
-/**
- * nand_write_word - [DEFAULT] write one word to the chip
- * @mtd:	MTD device structure
- * @word:	data word to write
- *
- * Default write function for 16bit buswith without
- * endianess conversion
- */
-static void nand_write_word(struct mtd_info *mtd, u16 word)
-{
-	struct nand_chip *this = mtd->priv;
-	writew(word, this->IO_ADDR_W);
+	struct nand_chip *chip = mtd->priv;
+	return readw(chip->IO_ADDR_R);
 }
 
 /**
  * nand_select_chip - [DEFAULT] control CE line
  * @mtd:	MTD device structure
- * @chip:	chipnumber to select, -1 for deselect
+ * @chipnr:	chipnumber to select, -1 for deselect
  *
  * Default select function for 1 chip devices.
  */
-static void nand_select_chip(struct mtd_info *mtd, int chip)
+static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 {
-	struct nand_chip *this = mtd->priv;
-	switch(chip) {
+	struct nand_chip *chip = mtd->priv;
+
+	switch (chipnr) {
 	case -1:
-		this->hwcontrol(mtd, NAND_CTL_CLRNCE);
+		chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 		break;
 	case 0:
-		this->hwcontrol(mtd, NAND_CTL_SETNCE);
 		break;
 
 	default:
@@ -306,13 +230,13 @@
  *
  * Default write function for 8bit buswith
  */
-static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
 	int i;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 
-	for (i=0; i<len; i++)
-		writeb(buf[i], this->IO_ADDR_W);
+	for (i = 0; i < len; i++)
+		writeb(buf[i], chip->IO_ADDR_W);
 }
 
 /**
@@ -323,13 +247,13 @@
  *
  * Default read function for 8bit buswith
  */
-static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	int i;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 
-	for (i=0; i<len; i++)
-		buf[i] = readb(this->IO_ADDR_R);
+	for (i = 0; i < len; i++)
+		buf[i] = readb(chip->IO_ADDR_R);
 }
 
 /**
@@ -340,15 +264,14 @@
  *
  * Default verify function for 8bit buswith
  */
-static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
 	int i;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 
-	for (i=0; i<len; i++)
-		if (buf[i] != readb(this->IO_ADDR_R))
+	for (i = 0; i < len; i++)
+		if (buf[i] != readb(chip->IO_ADDR_R))
 			return -EFAULT;
-
 	return 0;
 }
 
@@ -360,15 +283,15 @@
  *
  * Default write function for 16bit buswith
  */
-static void nand_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
+void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
 	int i;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 	u16 *p = (u16 *) buf;
 	len >>= 1;
 
-	for (i=0; i<len; i++)
-		writew(p[i], this->IO_ADDR_W);
+	for (i = 0; i < len; i++)
+		writew(p[i], chip->IO_ADDR_W);
 
 }
 
@@ -380,15 +303,15 @@
  *
  * Default read function for 16bit buswith
  */
-static void nand_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
+void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	int i;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 	u16 *p = (u16 *) buf;
 	len >>= 1;
 
-	for (i=0; i<len; i++)
-		p[i] = readw(this->IO_ADDR_R);
+	for (i = 0; i < len; i++)
+		p[i] = readw(chip->IO_ADDR_R);
 }
 
 /**
@@ -399,15 +322,15 @@
  *
  * Default verify function for 16bit buswith
  */
-static int nand_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
+static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
 	int i;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 	u16 *p = (u16 *) buf;
 	len >>= 1;
 
-	for (i=0; i<len; i++)
-		if (p[i] != readw(this->IO_ADDR_R))
+	for (i = 0; i < len; i++)
+		if (p[i] != readw(chip->IO_ADDR_R))
 			return -EFAULT;
 
 	return 0;
@@ -424,38 +347,43 @@
 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 {
 	int page, chipnr, res = 0;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 	u16 bad;
 
-	if (getchip) {
-		page = (int)(ofs >> this->page_shift);
-		chipnr = (int)(ofs >> this->chip_shift);
+	if (chip->options & NAND_BBT_SCANLASTPAGE)
+		ofs += mtd->erasesize - mtd->writesize;
 
-		/* Grab the lock and see if the device is available */
-		nand_get_device (this, mtd, FL_READING);
+	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+
+	if (getchip) {
+		chipnr = (int)(ofs >> chip->chip_shift);
+
+		nand_get_device(chip, mtd, FL_READING);
 
 		/* Select the NAND device */
-		this->select_chip(mtd, chipnr);
-	} else
-		page = (int) ofs;
+		chip->select_chip(mtd, chipnr);
+	}
 
-	if (this->options & NAND_BUSWIDTH_16) {
-		this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos & 0xFE, page & this->pagemask);
-		bad = cpu_to_le16(this->read_word(mtd));
-		if (this->badblockpos & 0x1)
-			bad >>= 1;
-		if ((bad & 0xFF) != 0xff)
-			res = 1;
+	if (chip->options & NAND_BUSWIDTH_16) {
+		chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
+			      page);
+		bad = cpu_to_le16(chip->read_word(mtd));
+		if (chip->badblockpos & 0x1)
+			bad >>= 8;
+		else
+			bad &= 0xFF;
 	} else {
-		this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos, page & this->pagemask);
-		if (this->read_byte(mtd) != 0xff)
-			res = 1;
+		chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
+		bad = chip->read_byte(mtd);
 	}
 
-	if (getchip) {
-		/* Deselect and wake up anyone waiting on the device */
+	if (likely(chip->badblockbits == 8))
+		res = bad != 0xFF;
+	else
+		res = hweight8(bad) < chip->badblockbits;
+
+	if (getchip)
 		nand_release_device(mtd);
-	}
 
 	return res;
 }
@@ -470,22 +398,53 @@
 */
 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 {
-	struct nand_chip *this = mtd->priv;
-	u_char buf[2] = {0, 0};
-	size_t	retlen;
-	int block;
+	struct nand_chip *chip = mtd->priv;
+	uint8_t buf[2] = { 0, 0 };
+	int block, ret, i = 0;
+
+	if (chip->options & NAND_BBT_SCANLASTPAGE)
+		ofs += mtd->erasesize - mtd->writesize;
 
 	/* Get block number */
-	block = ((int) ofs) >> this->bbt_erase_shift;
-	this->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
+	block = (int)(ofs >> chip->bbt_erase_shift);
+	if (chip->bbt)
+		chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 
 	/* Do we have a flash based bad block table ? */
-	if (this->options & NAND_USE_FLASH_BBT)
-		return nand_update_bbt (mtd, ofs);
+	if (chip->options & NAND_USE_FLASH_BBT)
+		ret = nand_update_bbt(mtd, ofs);
+	else {
+		nand_get_device(chip, mtd, FL_WRITING);
 
-	/* We write two bytes, so we dont have to mess with 16 bit access */
-	ofs += mtd->oobsize + (this->badblockpos & ~0x01);
-	return nand_write_oob (mtd, ofs , 2, &retlen, buf);
+		/* Write to first two pages and to byte 1 and 6 if necessary.
+		 * If we write to more than one location, the first error
+		 * encountered quits the procedure. We write two bytes per
+		 * location, so we dont have to mess with 16 bit access.
+		 */
+		do {
+			chip->ops.len = chip->ops.ooblen = 2;
+			chip->ops.datbuf = NULL;
+			chip->ops.oobbuf = buf;
+			chip->ops.ooboffs = chip->badblockpos & ~0x01;
+
+			ret = nand_do_write_oob(mtd, ofs, &chip->ops);
+
+			if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) {
+				chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS
+					& ~0x01;
+				ret = nand_do_write_oob(mtd, ofs, &chip->ops);
+			}
+			i++;
+			ofs += mtd->writesize;
+		} while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
+				i < 2);
+
+		nand_release_device(mtd);
+	}
+	if (!ret)
+		mtd->ecc_stats.badblocks++;
+
+	return ret;
 }
 
 /**
@@ -495,12 +454,17 @@
  *
  * The function expects, that the device is already selected
  */
-static int nand_check_wp (struct mtd_info *mtd)
+static int nand_check_wp(struct mtd_info *mtd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
+
+	/* broken xD cards report WP despite being writable */
+	if (chip->options & NAND_BROKEN_XD)
+		return 0;
+
 	/* Check the WP bit */
-	this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1);
-	return (this->read_byte(mtd) & 0x80) ? 0 : 1;
+	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+	return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 }
 
 /**
@@ -513,15 +477,41 @@
  * Check, if the block is bad. Either by reading the bad block table or
  * calling of the scan function.
  */
-static int nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt)
+static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
+			       int allowbbt)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 
-	if (!this->bbt)
-		return this->block_bad(mtd, ofs, getchip);
+	if (!(chip->options & NAND_BBT_SCANNED)) {
+		chip->options |= NAND_BBT_SCANNED;
+		chip->scan_bbt(mtd);
+	}
+
+	if (!chip->bbt)
+		return chip->block_bad(mtd, ofs, getchip);
 
 	/* Return info from the table */
-	return nand_isbad_bbt (mtd, ofs, allowbbt);
+	return nand_isbad_bbt(mtd, ofs, allowbbt);
+}
+
+/*
+ * Wait for the ready pin, after a command
+ * The timeout is catched later.
+ */
+void nand_wait_ready(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+	u32 time_start;
+
+	time_start = get_timer(0);
+
+	/* wait until command is processed or timeout occures */
+	while (get_timer(time_start) < timeo) {
+		if (chip->dev_ready)
+			if (chip->dev_ready(mtd))
+				break;
+	}
 }
 
 /**
@@ -534,21 +524,22 @@
  * Send command to NAND device. This function is used for small page
  * devices (256/512 Bytes per page)
  */
-static void nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr)
+static void nand_command(struct mtd_info *mtd, unsigned int command,
+			 int column, int page_addr)
 {
-	register struct nand_chip *this = mtd->priv;
+	register struct nand_chip *chip = mtd->priv;
+	int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
+	uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 
-	/* Begin command latch cycle */
-	this->hwcontrol(mtd, NAND_CTL_SETCLE);
 	/*
 	 * Write out the command to the device.
 	 */
 	if (command == NAND_CMD_SEQIN) {
 		int readcmd;
 
-		if (column >= mtd->oobblock) {
+		if (column >= mtd->writesize) {
 			/* OOB area */
-			column -= mtd->oobblock;
+			column -= mtd->writesize;
 			readcmd = NAND_CMD_READOOB;
 		} else if (column < 256) {
 			/* First 256 bytes --> READ0 */
@@ -557,38 +548,37 @@
 			column -= 256;
 			readcmd = NAND_CMD_READ1;
 		}
-		this->write_byte(mtd, readcmd);
+		chip->cmd_ctrl(mtd, readcmd, ctrl);
+		ctrl &= ~NAND_CTRL_CHANGE;
 	}
-	this->write_byte(mtd, command);
+	chip->cmd_ctrl(mtd, command, ctrl);
 
-	/* Set ALE and clear CLE to start address cycle */
-	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
-
-	if (column != -1 || page_addr != -1) {
-		this->hwcontrol(mtd, NAND_CTL_SETALE);
-
-		/* Serially input address */
-		if (column != -1) {
-			/* Adjust columns for 16 bit buswidth */
-			if (this->options & NAND_BUSWIDTH_16)
-				column >>= 1;
-			this->write_byte(mtd, column);
-		}
-		if (page_addr != -1) {
-			this->write_byte(mtd, (unsigned char) (page_addr & 0xff));
-			this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff));
-			/* One more address cycle for devices > 32MiB */
-			if (this->chipsize > (32 << 20))
-				this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0x0f));
-		}
-		/* Latch in address */
-		this->hwcontrol(mtd, NAND_CTL_CLRALE);
+	/*
+	 * Address cycle, when necessary
+	 */
+	ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
+	/* Serially input address */
+	if (column != -1) {
+		/* Adjust columns for 16 bit buswidth */
+		if (chip->options & NAND_BUSWIDTH_16)
+			column >>= 1;
+		chip->cmd_ctrl(mtd, column, ctrl);
+		ctrl &= ~NAND_CTRL_CHANGE;
 	}
+	if (page_addr != -1) {
+		chip->cmd_ctrl(mtd, page_addr, ctrl);
+		ctrl &= ~NAND_CTRL_CHANGE;
+		chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
+		/* One more address cycle for devices > 32MiB */
+		if (chip->chipsize > (32 << 20))
+			chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
+	}
+	chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 	/*
 	 * program and erase have their own busy handlers
 	 * status and sequential in needs no delay
-	*/
+	 */
 	switch (command) {
 
 	case NAND_CMD_PAGEPROG:
@@ -599,32 +589,33 @@
 		return;
 
 	case NAND_CMD_RESET:
-		if (this->dev_ready)
+		if (chip->dev_ready)
 			break;
-		udelay(this->chip_delay);
-		this->hwcontrol(mtd, NAND_CTL_SETCLE);
-		this->write_byte(mtd, NAND_CMD_STATUS);
-		this->hwcontrol(mtd, NAND_CTL_CLRCLE);
-		while ( !(this->read_byte(mtd) & 0x40));
+		udelay(chip->chip_delay);
+		chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
+			       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+		chip->cmd_ctrl(mtd,
+			       NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+		while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
+			(rst_sts_cnt--));
 		return;
 
-	/* This applies to read commands */
+		/* This applies to read commands */
 	default:
 		/*
 		 * If we don't have access to the busy pin, we apply the given
 		 * command delay
-		*/
-		if (!this->dev_ready) {
-			udelay (this->chip_delay);
+		 */
+		if (!chip->dev_ready) {
+			udelay(chip->chip_delay);
 			return;
 		}
 	}
-
 	/* Apply this short delay always to ensure that we do wait tWB in
 	 * any case on any machine. */
-	ndelay (100);
-	/* wait until command is processed */
-	while (!this->dev_ready(mtd));
+	ndelay(100);
+
+	nand_wait_ready(mtd);
 }
 
 /**
@@ -634,55 +625,54 @@
  * @column:	the column address for this command, -1 if none
  * @page_addr:	the page address for this command, -1 if none
  *
- * Send command to NAND device. This is the version for the new large page devices
- * We dont have the seperate regions as we have in the small page devices.
- * We must emulate NAND_CMD_READOOB to keep the code compatible.
- *
+ * Send command to NAND device. This is the version for the new large page
+ * devices We dont have the separate regions as we have in the small page
+ * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
  */
-static void nand_command_lp (struct mtd_info *mtd, unsigned command, int column, int page_addr)
+static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
+			    int column, int page_addr)
 {
-	register struct nand_chip *this = mtd->priv;
+	register struct nand_chip *chip = mtd->priv;
+	uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 
 	/* Emulate NAND_CMD_READOOB */
 	if (command == NAND_CMD_READOOB) {
-		column += mtd->oobblock;
+		column += mtd->writesize;
 		command = NAND_CMD_READ0;
 	}
 
-
-	/* Begin command latch cycle */
-	this->hwcontrol(mtd, NAND_CTL_SETCLE);
-	/* Write out the command to the device. */
-	this->write_byte(mtd, command);
-	/* End command latch cycle */
-	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+	/* Command latch cycle */
+	chip->cmd_ctrl(mtd, command & 0xff,
+		       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 
 	if (column != -1 || page_addr != -1) {
-		this->hwcontrol(mtd, NAND_CTL_SETALE);
+		int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 
 		/* Serially input address */
 		if (column != -1) {
 			/* Adjust columns for 16 bit buswidth */
-			if (this->options & NAND_BUSWIDTH_16)
+			if (chip->options & NAND_BUSWIDTH_16)
 				column >>= 1;
-			this->write_byte(mtd, column & 0xff);
-			this->write_byte(mtd, column >> 8);
+			chip->cmd_ctrl(mtd, column, ctrl);
+			ctrl &= ~NAND_CTRL_CHANGE;
+			chip->cmd_ctrl(mtd, column >> 8, ctrl);
 		}
 		if (page_addr != -1) {
-			this->write_byte(mtd, (unsigned char) (page_addr & 0xff));
-			this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff));
+			chip->cmd_ctrl(mtd, page_addr, ctrl);
+			chip->cmd_ctrl(mtd, page_addr >> 8,
+				       NAND_NCE | NAND_ALE);
 			/* One more address cycle for devices > 128MiB */
-			if (this->chipsize > (128 << 20))
-				this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0xff));
+			if (chip->chipsize > (128 << 20))
+				chip->cmd_ctrl(mtd, page_addr >> 16,
+					       NAND_NCE | NAND_ALE);
 		}
-		/* Latch in address */
-		this->hwcontrol(mtd, NAND_CTL_CLRALE);
 	}
+	chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 	/*
 	 * program and erase have their own busy handlers
-	 * status and sequential in needs no delay
-	*/
+	 * status, sequential in, and deplete1 need no delay
+	 */
 	switch (command) {
 
 	case NAND_CMD_CACHEDPROG:
@@ -690,647 +680,627 @@
 	case NAND_CMD_ERASE1:
 	case NAND_CMD_ERASE2:
 	case NAND_CMD_SEQIN:
+	case NAND_CMD_RNDIN:
 	case NAND_CMD_STATUS:
+	case NAND_CMD_DEPLETE1:
 		return;
 
+		/*
+		 * read error status commands require only a short delay
+		 */
+	case NAND_CMD_STATUS_ERROR:
+	case NAND_CMD_STATUS_ERROR0:
+	case NAND_CMD_STATUS_ERROR1:
+	case NAND_CMD_STATUS_ERROR2:
+	case NAND_CMD_STATUS_ERROR3:
+		udelay(chip->chip_delay);
+		return;
 
 	case NAND_CMD_RESET:
-		if (this->dev_ready)
+		if (chip->dev_ready)
 			break;
-		udelay(this->chip_delay);
-		this->hwcontrol(mtd, NAND_CTL_SETCLE);
-		this->write_byte(mtd, NAND_CMD_STATUS);
-		this->hwcontrol(mtd, NAND_CTL_CLRCLE);
-		while ( !(this->read_byte(mtd) & 0x40));
+		udelay(chip->chip_delay);
+		chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
+			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
+			       NAND_NCE | NAND_CTRL_CHANGE);
+		while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
+			(rst_sts_cnt--));
+		return;
+
+	case NAND_CMD_RNDOUT:
+		/* No ready / busy check necessary */
+		chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
+			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
+			       NAND_NCE | NAND_CTRL_CHANGE);
 		return;
 
 	case NAND_CMD_READ0:
-		/* Begin command latch cycle */
-		this->hwcontrol(mtd, NAND_CTL_SETCLE);
-		/* Write out the start read command */
-		this->write_byte(mtd, NAND_CMD_READSTART);
-		/* End command latch cycle */
-		this->hwcontrol(mtd, NAND_CTL_CLRCLE);
-		/* Fall through into ready check */
+		chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
+			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
+			       NAND_NCE | NAND_CTRL_CHANGE);
 
-	/* This applies to read commands */
+		/* This applies to read commands */
 	default:
 		/*
 		 * If we don't have access to the busy pin, we apply the given
 		 * command delay
-		*/
-		if (!this->dev_ready) {
-			udelay (this->chip_delay);
+		 */
+		if (!chip->dev_ready) {
+			udelay(chip->chip_delay);
 			return;
 		}
 	}
 
 	/* Apply this short delay always to ensure that we do wait tWB in
 	 * any case on any machine. */
-	ndelay (100);
-	/* wait until command is processed */
-	while (!this->dev_ready(mtd));
+	ndelay(100);
+
+	nand_wait_ready(mtd);
 }
 
 /**
  * nand_get_device - [GENERIC] Get chip for selected access
- * @this:	the nand chip descriptor
+ * @chip:	the nand chip descriptor
  * @mtd:	MTD device structure
  * @new_state:	the state which is requested
  *
  * Get the device and lock it for exclusive access
  */
-/* XXX U-BOOT XXX */
-#if 0
-static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
+static int
+nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 {
-	struct nand_chip *active = this;
-
-	DECLARE_WAITQUEUE (wait, current);
-
-	/*
-	 * Grab the lock and see if the device is available
-	*/
-retry:
-	/* Hardware controller shared among independend devices */
-	if (this->controller) {
-		spin_lock (&this->controller->lock);
-		if (this->controller->active)
-			active = this->controller->active;
-		else
-			this->controller->active = this;
-		spin_unlock (&this->controller->lock);
-	}
-
-	if (active == this) {
-		spin_lock (&this->chip_lock);
-		if (this->state == FL_READY) {
-			this->state = new_state;
-			spin_unlock (&this->chip_lock);
-			return;
-		}
-	}
-	set_current_state (TASK_UNINTERRUPTIBLE);
-	add_wait_queue (&active->wq, &wait);
-	spin_unlock (&active->chip_lock);
-	schedule ();
-	remove_wait_queue (&active->wq, &wait);
-	goto retry;
+	chip->state = new_state;
+	return 0;
 }
-#else
-static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state) {}
-#endif
 
 /**
  * nand_wait - [DEFAULT]  wait until the command is done
  * @mtd:	MTD device structure
- * @this:	NAND chip structure
- * @state:	state to select the max. timeout value
+ * @chip:	NAND chip structure
  *
  * Wait for command done. This applies to erase and program only
  * Erase can take up to 400ms and program up to 20ms according to
  * general NAND and SmartMedia specs
- *
-*/
-/* XXX U-BOOT XXX */
-#if 0
-static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
-{
-	unsigned long	timeo = jiffies;
-	int	status;
-
-	if (state == FL_ERASING)
-		 timeo += (HZ * 400) / 1000;
-	else
-		 timeo += (HZ * 20) / 1000;
-
-	/* Apply this short delay always to ensure that we do wait tWB in
-	 * any case on any machine. */
-	ndelay (100);
-
-	if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
-		this->cmdfunc (mtd, NAND_CMD_STATUS_MULTI, -1, -1);
-	else
-		this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1);
-
-	while (time_before(jiffies, timeo)) {
-		/* Check, if we were interrupted */
-		if (this->state != state)
-			return 0;
-
-		if (this->dev_ready) {
-			if (this->dev_ready(mtd))
-				break;
-		} else {
-			if (this->read_byte(mtd) & NAND_STATUS_READY)
-				break;
-		}
-		yield ();
-	}
-	status = (int) this->read_byte(mtd);
-	return status;
-
-	return 0;
-}
-#else
-static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+ */
+static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
 	unsigned long	timeo;
+	int state = chip->state;
+	u32 time_start;
 
 	if (state == FL_ERASING)
-		timeo = CFG_HZ * 400;
+		timeo = (CONFIG_SYS_HZ * 400) / 1000;
 	else
-		timeo = CFG_HZ * 20;
+		timeo = (CONFIG_SYS_HZ * 20) / 1000;
 
-	if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
-		this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
+	if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
+		chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 	else
-		this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+		chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 
-	reset_timer();
+	time_start = get_timer(0);
 
 	while (1) {
-		if (get_timer(0) > timeo) {
+		if (get_timer(time_start) > timeo) {
 			printf("Timeout!");
-			return 0;
-			}
+			return 0x01;
+		}
 
-		if (this->dev_ready) {
-			if (this->dev_ready(mtd))
+		if (chip->dev_ready) {
+			if (chip->dev_ready(mtd))
 				break;
 		} else {
-			if (this->read_byte(mtd) & NAND_STATUS_READY)
+			if (chip->read_byte(mtd) & NAND_STATUS_READY)
 				break;
 		}
 	}
 #ifdef PPCHAMELON_NAND_TIMER_HACK
-	reset_timer();
-	while (get_timer(0) < 10);
+	time_start = get_timer(0);
+	while (get_timer(time_start) < 10)
+		;
 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 
-	return this->read_byte(mtd);
+	return (int)chip->read_byte(mtd);
 }
-#endif
 
 /**
- * nand_write_page - [GENERIC] write one page
- * @mtd:	MTD device structure
- * @this:	NAND chip structure
- * @page: 	startpage inside the chip, must be called with (page & this->pagemask)
- * @oob_buf:	out of band data buffer
- * @oobsel:	out of band selecttion structre
- * @cached:	1 = enable cached programming if supported by chip
+ * nand_read_page_raw - [Intern] read raw page data without ecc
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	buffer to store read data
+ * @page:	page number to read
  *
- * Nand_page_program function is used for write and writev !
- * This function will always program a full page of data
- * If you call it with a non page aligned buffer, you're lost :)
- *
- * Cached programming is not supported yet.
+ * Not for syndrome calculating ecc controllers, which use a special oob layout
  */
-static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page,
-	u_char *oob_buf,  struct nand_oobinfo *oobsel, int cached)
+static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+			      uint8_t *buf, int page)
 {
-	int 	i, status;
-	u_char	ecc_code[32];
-	int	eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
-	uint  	*oob_config = oobsel->eccpos;
-	int	datidx = 0, eccidx = 0, eccsteps = this->eccsteps;
-	int	eccbytes = 0;
+	chip->read_buf(mtd, buf, mtd->writesize);
+	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+	return 0;
+}
 
-	/* FIXME: Enable cached programming */
-	cached = 0;
+/**
+ * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	buffer to store read data
+ * @page:	page number to read
+ *
+ * We need a special oob layout and handling even when OOB isn't used.
+ */
+static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
+					struct nand_chip *chip,
+					uint8_t *buf, int page)
+{
+	int eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	uint8_t *oob = chip->oob_poi;
+	int steps, size;
 
-	/* Send command to begin auto page programming */
-	this->cmdfunc (mtd, NAND_CMD_SEQIN, 0x00, page);
+	for (steps = chip->ecc.steps; steps > 0; steps--) {
+		chip->read_buf(mtd, buf, eccsize);
+		buf += eccsize;
 
-	/* Write out complete page of data, take care of eccmode */
-	switch (eccmode) {
-	/* No ecc, write all */
-	case NAND_ECC_NONE:
-		printk (KERN_WARNING "Writing data without ECC to NAND-FLASH is not recommended\n");
-		this->write_buf(mtd, this->data_poi, mtd->oobblock);
-		break;
-
-	/* Software ecc 3/256, write all */
-	case NAND_ECC_SOFT:
-		for (; eccsteps; eccsteps--) {
-			this->calculate_ecc(mtd, &this->data_poi[datidx], ecc_code);
-			for (i = 0; i < 3; i++, eccidx++)
-				oob_buf[oob_config[eccidx]] = ecc_code[i];
-			datidx += this->eccsize;
+		if (chip->ecc.prepad) {
+			chip->read_buf(mtd, oob, chip->ecc.prepad);
+			oob += chip->ecc.prepad;
 		}
-		this->write_buf(mtd, this->data_poi, mtd->oobblock);
-		break;
-	default:
-		eccbytes = this->eccbytes;
-		for (; eccsteps; eccsteps--) {
-			/* enable hardware ecc logic for write */
-			this->enable_hwecc(mtd, NAND_ECC_WRITE);
-			this->write_buf(mtd, &this->data_poi[datidx], this->eccsize);
-			this->calculate_ecc(mtd, &this->data_poi[datidx], ecc_code);
-			for (i = 0; i < eccbytes; i++, eccidx++)
-				oob_buf[oob_config[eccidx]] = ecc_code[i];
-			/* If the hardware ecc provides syndromes then
-			 * the ecc code must be written immidiately after
-			 * the data bytes (words) */
-			if (this->options & NAND_HWECC_SYNDROME)
-				this->write_buf(mtd, ecc_code, eccbytes);
-			datidx += this->eccsize;
+
+		chip->read_buf(mtd, oob, eccbytes);
+		oob += eccbytes;
+
+		if (chip->ecc.postpad) {
+			chip->read_buf(mtd, oob, chip->ecc.postpad);
+			oob += chip->ecc.postpad;
 		}
-		break;
 	}
 
-	/* Write out OOB data */
-	if (this->options & NAND_HWECC_SYNDROME)
-		this->write_buf(mtd, &oob_buf[oobsel->eccbytes], mtd->oobsize - oobsel->eccbytes);
-	else
-		this->write_buf(mtd, oob_buf, mtd->oobsize);
+	size = mtd->oobsize - (oob - chip->oob_poi);
+	if (size)
+		chip->read_buf(mtd, oob, size);
 
-	/* Send command to actually program the data */
-	this->cmdfunc (mtd, cached ? NAND_CMD_CACHEDPROG : NAND_CMD_PAGEPROG, -1, -1);
+	return 0;
+}
 
-	if (!cached) {
-		/* call wait ready function */
-		status = this->waitfunc (mtd, this, FL_WRITING);
-		/* See if device thinks it succeeded */
-		if (status & 0x01) {
-			DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page);
-			return -EIO;
-		}
-	} else {
-		/* FIXME: Implement cached programming ! */
-		/* wait until cache is ready*/
-		/* status = this->waitfunc (mtd, this, FL_CACHEDRPG); */
+/**
+ * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	buffer to store read data
+ * @page:	page number to read
+ */
+static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
+				uint8_t *buf, int page)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	uint8_t *ecc_code = chip->buffers->ecccode;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+
+	chip->ecc.read_page_raw(mtd, chip, buf, page);
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+	for (i = 0; i < chip->ecc.total; i++)
+		ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+	eccsteps = chip->ecc.steps;
+	p = buf;
+
+	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		int stat;
+
+		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+		if (stat < 0)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
 	}
 	return 0;
 }
 
-#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
 /**
- * nand_verify_pages - [GENERIC] verify the chip contents after a write
- * @mtd:	MTD device structure
- * @this:	NAND chip structure
- * @page: 	startpage inside the chip, must be called with (page & this->pagemask)
- * @numpages:	number of pages to verify
- * @oob_buf:	out of band data buffer
- * @oobsel:	out of band selecttion structre
- * @chipnr:	number of the current chip
- * @oobmode:	1 = full buffer verify, 0 = ecc only
- *
- * The NAND device assumes that it is always writing to a cleanly erased page.
- * Hence, it performs its internal write verification only on bits that
- * transitioned from 1 to 0. The device does NOT verify the whole page on a
- * byte by byte basis. It is possible that the page was not completely erased
- * or the page is becoming unusable due to wear. The read with ECC would catch
- * the error later when the ECC page check fails, but we would rather catch
- * it early in the page write stage. Better to write no data than invalid data.
+ * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @data_offs:	offset of requested data within the page
+ * @readlen:	data length
+ * @bufpoi:	buffer to store read data
  */
-static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int page, int numpages,
-	u_char *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode)
+static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
+			uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 {
-	int 	i, j, datidx = 0, oobofs = 0, res = -EIO;
-	int	eccsteps = this->eccsteps;
-	int	hweccbytes;
-	u_char 	oobdata[64];
+	int start_step, end_step, num_steps;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+	uint8_t *p;
+	int data_col_addr, i, gaps = 0;
+	int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
+	int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
+	int index = 0;
 
-	hweccbytes = (this->options & NAND_HWECC_SYNDROME) ? (oobsel->eccbytes / eccsteps) : 0;
+	/* Column address wihin the page aligned to ECC size (256bytes). */
+	start_step = data_offs / chip->ecc.size;
+	end_step = (data_offs + readlen - 1) / chip->ecc.size;
+	num_steps = end_step - start_step + 1;
 
-	/* Send command to read back the first page */
-	this->cmdfunc (mtd, NAND_CMD_READ0, 0, page);
+	/* Data size aligned to ECC ecc.size*/
+	datafrag_len = num_steps * chip->ecc.size;
+	eccfrag_len = num_steps * chip->ecc.bytes;
 
-	for(;;) {
-		for (j = 0; j < eccsteps; j++) {
-			/* Loop through and verify the data */
-			if (this->verify_buf(mtd, &this->data_poi[datidx], mtd->eccsize)) {
-				DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
-				goto out;
-			}
-			datidx += mtd->eccsize;
-			/* Have we a hw generator layout ? */
-			if (!hweccbytes)
-				continue;
-			if (this->verify_buf(mtd, &this->oob_buf[oobofs], hweccbytes)) {
-				DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
-				goto out;
-			}
-			oobofs += hweccbytes;
+	data_col_addr = start_step * chip->ecc.size;
+	/* If we read not a page aligned data */
+	if (data_col_addr != 0)
+		chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
+
+	p = bufpoi + data_col_addr;
+	chip->read_buf(mtd, p, datafrag_len);
+
+	/* Calculate  ECC */
+	for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
+		chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
+
+	/* The performance is faster if to position offsets
+	   according to ecc.pos. Let make sure here that
+	   there are no gaps in ecc positions */
+	for (i = 0; i < eccfrag_len - 1; i++) {
+		if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
+			eccpos[i + start_step * chip->ecc.bytes + 1]) {
+			gaps = 1;
+			break;
+		}
+	}
+	if (gaps) {
+		chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
+		chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+	} else {
+		/* send the command to read the particular ecc bytes */
+		/* take care about buswidth alignment in read_buf */
+		index = start_step * chip->ecc.bytes;
+
+		aligned_pos = eccpos[index] & ~(busw - 1);
+		aligned_len = eccfrag_len;
+		if (eccpos[index] & (busw - 1))
+			aligned_len++;
+		if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
+			aligned_len++;
+
+		chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
+					mtd->writesize + aligned_pos, -1);
+		chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
+	}
+
+	for (i = 0; i < eccfrag_len; i++)
+		chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
+
+	p = bufpoi + data_col_addr;
+	for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
+		int stat;
+
+		stat = chip->ecc.correct(mtd, p,
+			&chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
+		if (stat < 0)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+	}
+	return 0;
+}
+
+/**
+ * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	buffer to store read data
+ * @page:	page number to read
+ *
+ * Not for syndrome calculating ecc controllers which need a special oob layout
+ */
+static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+				uint8_t *buf, int page)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	uint8_t *ecc_code = chip->buffers->ecccode;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		chip->ecc.hwctl(mtd, NAND_ECC_READ);
+		chip->read_buf(mtd, p, eccsize);
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+	}
+	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+	for (i = 0; i < chip->ecc.total; i++)
+		ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+	eccsteps = chip->ecc.steps;
+	p = buf;
+
+	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		int stat;
+
+		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+		if (stat < 0)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+	}
+	return 0;
+}
+
+/**
+ * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	buffer to store read data
+ * @page:	page number to read
+ *
+ * Hardware ECC for large page chips, require OOB to be read first.
+ * For this ECC mode, the write_page method is re-used from ECC_HW.
+ * These methods read/write ECC from the OOB area, unlike the
+ * ECC_HW_SYNDROME support with multiple ECC steps, follows the
+ * "infix ECC" scheme and reads/writes ECC from the data area, by
+ * overwriting the NAND manufacturer bad block markings.
+ */
+static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
+	struct nand_chip *chip, uint8_t *buf, int page)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *ecc_code = chip->buffers->ecccode;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+
+	/* Read the OOB area first */
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+
+	for (i = 0; i < chip->ecc.total; i++)
+		ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		int stat;
+
+		chip->ecc.hwctl(mtd, NAND_ECC_READ);
+		chip->read_buf(mtd, p, eccsize);
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+		stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
+		if (stat < 0)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+	}
+	return 0;
+}
+
+/**
+ * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	buffer to store read data
+ * @page:	page number to read
+ *
+ * The hw generator calculates the error syndrome automatically. Therefor
+ * we need a special oob layout and handling.
+ */
+static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+				   uint8_t *buf, int page)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		int stat;
+
+		chip->ecc.hwctl(mtd, NAND_ECC_READ);
+		chip->read_buf(mtd, p, eccsize);
+
+		if (chip->ecc.prepad) {
+			chip->read_buf(mtd, oob, chip->ecc.prepad);
+			oob += chip->ecc.prepad;
 		}
 
-		/* check, if we must compare all data or if we just have to
-		 * compare the ecc bytes
-		 */
-		if (oobmode) {
-			if (this->verify_buf(mtd, &oob_buf[oobofs], mtd->oobsize - hweccbytes * eccsteps)) {
-				DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
-				goto out;
+		chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
+		chip->read_buf(mtd, oob, eccbytes);
+		stat = chip->ecc.correct(mtd, p, oob, NULL);
+
+		if (stat < 0)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+
+		oob += eccbytes;
+
+		if (chip->ecc.postpad) {
+			chip->read_buf(mtd, oob, chip->ecc.postpad);
+			oob += chip->ecc.postpad;
+		}
+	}
+
+	/* Calculate remaining oob bytes */
+	i = mtd->oobsize - (oob - chip->oob_poi);
+	if (i)
+		chip->read_buf(mtd, oob, i);
+
+	return 0;
+}
+
+/**
+ * nand_transfer_oob - [Internal] Transfer oob to client buffer
+ * @chip:	nand chip structure
+ * @oob:	oob destination address
+ * @ops:	oob ops structure
+ * @len:	size of oob to transfer
+ */
+static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
+				  struct mtd_oob_ops *ops, size_t len)
+{
+	switch (ops->mode) {
+
+	case MTD_OOB_PLACE:
+	case MTD_OOB_RAW:
+		memcpy(oob, chip->oob_poi + ops->ooboffs, len);
+		return oob + len;
+
+	case MTD_OOB_AUTO: {
+		struct nand_oobfree *free = chip->ecc.layout->oobfree;
+		uint32_t boffs = 0, roffs = ops->ooboffs;
+		size_t bytes = 0;
+
+		for (; free->length && len; free++, len -= bytes) {
+			/* Read request not from offset 0 ? */
+			if (unlikely(roffs)) {
+				if (roffs >= free->length) {
+					roffs -= free->length;
+					continue;
+				}
+				boffs = free->offset + roffs;
+				bytes = min_t(size_t, len,
+					      (free->length - roffs));
+				roffs = 0;
+			} else {
+				bytes = min_t(size_t, len, free->length);
+				boffs = free->offset;
+			}
+			memcpy(oob, chip->oob_poi + boffs, bytes);
+			oob += bytes;
+		}
+		return oob;
+	}
+	default:
+		BUG();
+	}
+	return NULL;
+}
+
+/**
+ * nand_do_read_ops - [Internal] Read data with ECC
+ *
+ * @mtd:	MTD device structure
+ * @from:	offset to read from
+ * @ops:	oob ops structure
+ *
+ * Internal function. Called with chip held.
+ */
+static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
+			    struct mtd_oob_ops *ops)
+{
+	int chipnr, page, realpage, col, bytes, aligned;
+	struct nand_chip *chip = mtd->priv;
+	struct mtd_ecc_stats stats;
+	int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
+	int sndcmd = 1;
+	int ret = 0;
+	uint32_t readlen = ops->len;
+	uint32_t oobreadlen = ops->ooblen;
+	uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
+		mtd->oobavail : mtd->oobsize;
+
+	uint8_t *bufpoi, *oob, *buf;
+
+//	printk(KERN_INFO "size of loff_t = %d \n", sizeof(loff_t));
+
+	stats = mtd->ecc_stats;
+
+	chipnr = (int)(from >> chip->chip_shift);
+	chip->select_chip(mtd, chipnr);
+
+	realpage = (int)(from >> chip->page_shift);
+	page = realpage & chip->pagemask;
+
+	col = (int)(from & (mtd->writesize - 1));
+
+	buf = ops->datbuf;
+	oob = ops->oobbuf;
+
+	while (1) {
+		WATCHDOG_RESET();
+
+		bytes = min(mtd->writesize - col, readlen);
+		aligned = (bytes == mtd->writesize);
+
+		/* Is the current page in the buffer ? */
+		if (realpage != chip->pagebuf || oob) {
+			bufpoi = aligned ? buf : chip->buffers->databuf;
+
+			if (likely(sndcmd)) {
+				chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+				sndcmd = 0;
+			}
+
+			/* Now read the page into the buffer */
+			if (unlikely(ops->mode == MTD_OOB_RAW))
+				ret = chip->ecc.read_page_raw(mtd, chip,
+							      bufpoi, page);
+			else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
+				ret = chip->ecc.read_subpage(mtd, chip,
+							col, bytes, bufpoi);
+			else
+				ret = chip->ecc.read_page(mtd, chip, bufpoi,
+							  page);
+			if (ret < 0)
+				break;
+
+			/* Transfer not aligned data */
+			if (!aligned) {
+				if (!NAND_SUBPAGE_READ(chip) && !oob &&
+				    !(mtd->ecc_stats.failed - stats.failed))
+					chip->pagebuf = realpage;
+				memcpy(buf, chip->buffers->databuf + col, bytes);
+			}
+
+			buf += bytes;
+
+			if (unlikely(oob)) {
+
+				int toread = min(oobreadlen, max_oobsize);
+
+				if (toread) {
+					oob = nand_transfer_oob(chip,
+						oob, ops, toread);
+					oobreadlen -= toread;
+				}
+			}
+
+			if (!(chip->options & NAND_NO_READRDY)) {
+				/*
+				 * Apply delay or wait for ready/busy pin. Do
+				 * this before the AUTOINCR check, so no
+				 * problems arise if a chip which does auto
+				 * increment is marked as NOAUTOINCR by the
+				 * board driver.
+				 */
+				if (!chip->dev_ready)
+					udelay(chip->chip_delay);
+				else
+					nand_wait_ready(mtd);
 			}
 		} else {
-			/* Read always, else autoincrement fails */
-			this->read_buf(mtd, oobdata, mtd->oobsize - hweccbytes * eccsteps);
-
-			if (oobsel->useecc != MTD_NANDECC_OFF && !hweccbytes) {
-				int ecccnt = oobsel->eccbytes;
-
-				for (i = 0; i < ecccnt; i++) {
-					int idx = oobsel->eccpos[i];
-					if (oobdata[idx] != oob_buf[oobofs + idx] ) {
-						DEBUG (MTD_DEBUG_LEVEL0,
-					       	"%s: Failed ECC write "
-						"verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i);
-						goto out;
-					}
-				}
-			}
-		}
-		oobofs += mtd->oobsize - hweccbytes * eccsteps;
-		page++;
-		numpages--;
-
-		/* Apply delay or wait for ready/busy pin
-		 * Do this before the AUTOINCR check, so no problems
-		 * arise if a chip which does auto increment
-		 * is marked as NOAUTOINCR by the board driver.
-		 * Do this also before returning, so the chip is
-		 * ready for the next command.
-		*/
-		if (!this->dev_ready)
-			udelay (this->chip_delay);
-		else
-			while (!this->dev_ready(mtd));
-
-		/* All done, return happy */
-		if (!numpages)
-			return 0;
-
-
-		/* Check, if the chip supports auto page increment */
-		if (!NAND_CANAUTOINCR(this))
-			this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page);
-	}
-	/*
-	 * Terminate the read command. We come here in case of an error
-	 * So we must issue a reset command.
-	 */
-out:
-	this->cmdfunc (mtd, NAND_CMD_RESET, -1, -1);
-	return res;
-}
-#endif
-
-/**
- * nand_read - [MTD Interface] MTD compability function for nand_read_ecc
- * @mtd:	MTD device structure
- * @from:	offset to read from
- * @len:	number of bytes to read
- * @retlen:	pointer to variable to store the number of read bytes
- * @buf:	the databuffer to put data
- *
- * This function simply calls nand_read_ecc with oob buffer and oobsel = NULL
-*/
-static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
-{
-	return nand_read_ecc (mtd, from, len, retlen, buf, NULL, NULL);
-}
-
-
-/**
- * nand_read_ecc - [MTD Interface] Read data with ECC
- * @mtd:	MTD device structure
- * @from:	offset to read from
- * @len:	number of bytes to read
- * @retlen:	pointer to variable to store the number of read bytes
- * @buf:	the databuffer to put data
- * @oob_buf:	filesystem supplied oob data buffer
- * @oobsel:	oob selection structure
- *
- * NAND read with ECC
- */
-static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
-			  size_t * retlen, u_char * buf, u_char * oob_buf, struct nand_oobinfo *oobsel)
-{
-	int i, j, col, realpage, page, end, ecc, chipnr, sndcmd = 1;
-	int read = 0, oob = 0, ecc_status = 0, ecc_failed = 0;
-	struct nand_chip *this = mtd->priv;
-	u_char *data_poi, *oob_data = oob_buf;
-	u_char ecc_calc[32];
-	u_char ecc_code[32];
-	int eccmode, eccsteps;
-	unsigned *oob_config;
-	int	datidx;
-	int	blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1;
-	int	eccbytes;
-	int	compareecc = 1;
-	int	oobreadlen;
-
-
-	DEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
-
-	/* Do not allow reads past end of device */
-	if ((from + len) > mtd->size) {
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n");
-		*retlen = 0;
-		return -EINVAL;
-	}
-
-	/* Grab the lock and see if the device is available */
-	nand_get_device (this, mtd ,FL_READING);
-
-	/* use userspace supplied oobinfo, if zero */
-	if (oobsel == NULL)
-		oobsel = &mtd->oobinfo;
-
-	/* Autoplace of oob data ? Use the default placement scheme */
-	if (oobsel->useecc == MTD_NANDECC_AUTOPLACE)
-		oobsel = this->autooob;
-
-	eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
-	oob_config = oobsel->eccpos;
-
-	/* Select the NAND device */
-	chipnr = (int)(from >> this->chip_shift);
-	this->select_chip(mtd, chipnr);
-
-	/* First we calculate the starting page */
-	realpage = (int) (from >> this->page_shift);
-	page = realpage & this->pagemask;
-
-	/* Get raw starting column */
-	col = from & (mtd->oobblock - 1);
-
-	end = mtd->oobblock;
-	ecc = this->eccsize;
-	eccbytes = this->eccbytes;
-
-	if ((eccmode == NAND_ECC_NONE) || (this->options & NAND_HWECC_SYNDROME))
-		compareecc = 0;
-
-	oobreadlen = mtd->oobsize;
-	if (this->options & NAND_HWECC_SYNDROME)
-		oobreadlen -= oobsel->eccbytes;
-
-	/* Loop until all data read */
-	while (read < len) {
-
-		int aligned = (!col && (len - read) >= end);
-		/*
-		 * If the read is not page aligned, we have to read into data buffer
-		 * due to ecc, else we read into return buffer direct
-		 */
-		if (aligned)
-			data_poi = &buf[read];
-		else
-			data_poi = this->data_buf;
-
-		/* Check, if we have this page in the buffer
-		 *
-		 * FIXME: Make it work when we must provide oob data too,
-		 * check the usage of data_buf oob field
-		 */
-		if (realpage == this->pagebuf && !oob_buf) {
-			/* aligned read ? */
-			if (aligned)
-				memcpy (data_poi, this->data_buf, end);
-			goto readdata;
+			memcpy(buf, chip->buffers->databuf + col, bytes);
+			buf += bytes;
 		}
 
-		/* Check, if we must send the read command */
-		if (sndcmd) {
-			this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page);
-			sndcmd = 0;
-		}
+		readlen -= bytes;
 
-		/* get oob area, if we have no oob buffer from fs-driver */
-		if (!oob_buf || oobsel->useecc == MTD_NANDECC_AUTOPLACE ||
-			oobsel->useecc == MTD_NANDECC_AUTOPL_USR)
-			oob_data = &this->data_buf[end];
-
-		eccsteps = this->eccsteps;
-
-		switch (eccmode) {
-		case NAND_ECC_NONE: {	/* No ECC, Read in a page */
-/* XXX U-BOOT XXX */
-#if 0
-			static unsigned long lastwhinge = 0;
-			if ((lastwhinge / HZ) != (jiffies / HZ)) {
-				printk (KERN_WARNING "Reading data from NAND FLASH without ECC is not recommended\n");
-				lastwhinge = jiffies;
-			}
-#else
-			puts("Reading data from NAND FLASH without ECC is not recommended\n");
-#endif
-			this->read_buf(mtd, data_poi, end);
-			break;
-		}
-
-		case NAND_ECC_SOFT:	/* Software ECC 3/256: Read in a page + oob data */
-			this->read_buf(mtd, data_poi, end);
-			for (i = 0, datidx = 0; eccsteps; eccsteps--, i+=3, datidx += ecc)
-				this->calculate_ecc(mtd, &data_poi[datidx], &ecc_calc[i]);
-			break;
-
-		default:
-			for (i = 0, datidx = 0; eccsteps; eccsteps--, i+=eccbytes, datidx += ecc) {
-				this->enable_hwecc(mtd, NAND_ECC_READ);
-				this->read_buf(mtd, &data_poi[datidx], ecc);
-
-				/* HW ecc with syndrome calculation must read the
-				 * syndrome from flash immidiately after the data */
-				if (!compareecc) {
-					/* Some hw ecc generators need to know when the
-					 * syndrome is read from flash */
-					this->enable_hwecc(mtd, NAND_ECC_READSYN);
-					this->read_buf(mtd, &oob_data[i], eccbytes);
-					/* We calc error correction directly, it checks the hw
-					 * generator for an error, reads back the syndrome and
-					 * does the error correction on the fly */
-					if (this->correct_data(mtd, &data_poi[datidx], &oob_data[i], &ecc_code[i]) == -1) {
-						DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: "
-							"Failed ECC read, page 0x%08x on chip %d\n", page, chipnr);
-						ecc_failed++;
-					}
-				} else {
-					this->calculate_ecc(mtd, &data_poi[datidx], &ecc_calc[i]);
-				}
-			}
-			break;
-		}
-
-		/* read oobdata */
-		this->read_buf(mtd, &oob_data[mtd->oobsize - oobreadlen], oobreadlen);
-
-		/* Skip ECC check, if not requested (ECC_NONE or HW_ECC with syndromes) */
-		if (!compareecc)
-			goto readoob;
-
-		/* Pick the ECC bytes out of the oob data */
-		for (j = 0; j < oobsel->eccbytes; j++)
-			ecc_code[j] = oob_data[oob_config[j]];
-
-		/* correct data, if neccecary */
-		for (i = 0, j = 0, datidx = 0; i < this->eccsteps; i++, datidx += ecc) {
-			ecc_status = this->correct_data(mtd, &data_poi[datidx], &ecc_code[j], &ecc_calc[j]);
-
-			/* Get next chunk of ecc bytes */
-			j += eccbytes;
-
-			/* Check, if we have a fs supplied oob-buffer,
-			 * This is the legacy mode. Used by YAFFS1
-			 * Should go away some day
-			 */
-			if (oob_buf && oobsel->useecc == MTD_NANDECC_PLACE) {
-				int *p = (int *)(&oob_data[mtd->oobsize]);
-				p[i] = ecc_status;
-			}
-
-			if (ecc_status == -1) {
-				DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page);
-				ecc_failed++;
-			}
-		}
-
-	readoob:
-		/* check, if we have a fs supplied oob-buffer */
-		if (oob_buf) {
-			/* without autoplace. Legacy mode used by YAFFS1 */
-			switch(oobsel->useecc) {
-			case MTD_NANDECC_AUTOPLACE:
-			case MTD_NANDECC_AUTOPL_USR:
-				/* Walk through the autoplace chunks */
-				for (i = 0, j = 0; j < mtd->oobavail; i++) {
-					int from = oobsel->oobfree[i][0];
-					int num = oobsel->oobfree[i][1];
-					memcpy(&oob_buf[oob], &oob_data[from], num);
-					j+= num;
-				}
-				oob += mtd->oobavail;
-				break;
-			case MTD_NANDECC_PLACE:
-				/* YAFFS1 legacy mode */
-				oob_data += this->eccsteps * sizeof (int);
-			default:
-				oob_data += mtd->oobsize;
-			}
-		}
-	readdata:
-		/* Partial page read, transfer data into fs buffer */
-		if (!aligned) {
-			for (j = col; j < end && read < len; j++)
-				buf[read++] = data_poi[j];
-			this->pagebuf = realpage;
-		} else
-			read += mtd->oobblock;
-
-		/* Apply delay or wait for ready/busy pin
-		 * Do this before the AUTOINCR check, so no problems
-		 * arise if a chip which does auto increment
-		 * is marked as NOAUTOINCR by the board driver.
-		*/
-		if (!this->dev_ready)
-			udelay (this->chip_delay);
-		else
-			while (!this->dev_ready(mtd));
-
-		if (read == len)
+		if (!readlen)
 			break;
 
 		/* For subsequent reads align to page boundary. */
@@ -1338,705 +1308,879 @@
 		/* Increment page address */
 		realpage++;
 
-		page = realpage & this->pagemask;
+		page = realpage & chip->pagemask;
 		/* Check, if we cross a chip boundary */
 		if (!page) {
 			chipnr++;
-			this->select_chip(mtd, -1);
-			this->select_chip(mtd, chipnr);
+			chip->select_chip(mtd, -1);
+			chip->select_chip(mtd, chipnr);
 		}
+
 		/* Check, if the chip supports auto page increment
 		 * or if we have hit a block boundary.
-		*/
-		if (!NAND_CANAUTOINCR(this) || !(page & blockcheck))
+		 */
+		if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
 			sndcmd = 1;
 	}
 
-	/* Deselect and wake up anyone waiting on the device */
-	nand_release_device(mtd);
+	ops->retlen = ops->len - (size_t) readlen;
+	if (oob)
+		ops->oobretlen = ops->ooblen - oobreadlen;
 
-	/*
-	 * Return success, if no ECC failures, else -EBADMSG
-	 * fs driver will take care of that, because
-	 * retlen == desired len and result == -EBADMSG
-	 */
-	*retlen = read;
-	return ecc_failed ? -EBADMSG : 0;
+	if (ret)
+		return ret;
+
+	if (mtd->ecc_stats.failed - stats.failed)
+		return -EBADMSG;
+
+	return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
 }
 
 /**
- * nand_read_oob - [MTD Interface] NAND read out-of-band
+ * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
  * @mtd:	MTD device structure
  * @from:	offset to read from
  * @len:	number of bytes to read
  * @retlen:	pointer to variable to store the number of read bytes
  * @buf:	the databuffer to put data
  *
- * NAND read out-of-band data from the spare area
+ * Get hold of the chip and call nand_do_read
  */
-static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
+static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
+		     size_t *retlen, uint8_t *buf)
 {
-	int i, col, page, chipnr;
-	struct nand_chip *this = mtd->priv;
-	int	blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1;
-
-	DEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
-
-	/* Shift to get page */
-	page = (int)(from >> this->page_shift);
-	chipnr = (int)(from >> this->chip_shift);
-
-	/* Mask to get column */
-	col = from & (mtd->oobsize - 1);
-
-	/* Initialize return length value */
-	*retlen = 0;
+	struct nand_chip *chip = mtd->priv;
+	int ret;
 
 	/* Do not allow reads past end of device */
-	if ((from + len) > mtd->size) {
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: Attempt read beyond end of device\n");
-		*retlen = 0;
+	if ((from + len) > mtd->size)
 		return -EINVAL;
-	}
+	if (!len)
+		return 0;
 
-	/* Grab the lock and see if the device is available */
-	nand_get_device (this, mtd , FL_READING);
+	nand_get_device(chip, mtd, FL_READING);
 
-	/* Select the NAND device */
-	this->select_chip(mtd, chipnr);
+	chip->ops.len = len;
+	chip->ops.datbuf = buf;
+	chip->ops.oobbuf = NULL;
 
-	/* Send the read command */
-	this->cmdfunc (mtd, NAND_CMD_READOOB, col, page & this->pagemask);
-	/*
-	 * Read the data, if we read more than one page
-	 * oob data, let the device transfer the data !
-	 */
-	i = 0;
-	while (i < len) {
-		int thislen = mtd->oobsize - col;
-		thislen = min_t(int, thislen, len);
-		this->read_buf(mtd, &buf[i], thislen);
-		i += thislen;
+	ret = nand_do_read_ops(mtd, from, &chip->ops);
 
-		/* Apply delay or wait for ready/busy pin
-		 * Do this before the AUTOINCR check, so no problems
-		 * arise if a chip which does auto increment
-		 * is marked as NOAUTOINCR by the board driver.
-		*/
-		if (!this->dev_ready)
-			udelay (this->chip_delay);
-		else
-			while (!this->dev_ready(mtd));
+	*retlen = chip->ops.retlen;
 
-		/* Read more ? */
-		if (i < len) {
-			page++;
-			col = 0;
-
-			/* Check, if we cross a chip boundary */
-			if (!(page & this->pagemask)) {
-				chipnr++;
-				this->select_chip(mtd, -1);
-				this->select_chip(mtd, chipnr);
-			}
-
-			/* Check, if the chip supports auto page increment
-			 * or if we have hit a block boundary.
-			*/
-			if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) {
-				/* For subsequent page reads set offset to 0 */
-				this->cmdfunc (mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
-			}
-		}
-	}
-
-	/* Deselect and wake up anyone waiting on the device */
 	nand_release_device(mtd);
 
-	/* Return happy */
-	*retlen = len;
-	return 0;
+	return ret;
 }
 
 /**
- * nand_read_raw - [GENERIC] Read raw data including oob into buffer
- * @mtd:	MTD device structure
- * @buf:	temporary buffer
- * @from:	offset to read from
- * @len:	number of bytes to read
- * @ooblen:	number of oob data bytes to read
- *
- * Read raw data including oob into buffer
+ * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @page:	page number to read
+ * @sndcmd:	flag whether to issue read command or not
  */
-int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen)
+static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
+			     int page, int sndcmd)
 {
-	struct nand_chip *this = mtd->priv;
-	int page = (int) (from >> this->page_shift);
-	int chip = (int) (from >> this->chip_shift);
-	int sndcmd = 1;
-	int cnt = 0;
-	int pagesize = mtd->oobblock + mtd->oobsize;
-	int	blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1;
+	if (sndcmd) {
+		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+		sndcmd = 0;
+	}
+	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+	return sndcmd;
+}
 
-	/* Do not allow reads past end of device */
-	if ((from + len) > mtd->size) {
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt read beyond end of device\n");
+/**
+ * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
+ *			    with syndromes
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @page:	page number to read
+ * @sndcmd:	flag whether to issue read command or not
+ */
+static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+				  int page, int sndcmd)
+{
+	uint8_t *buf = chip->oob_poi;
+	int length = mtd->oobsize;
+	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+	int eccsize = chip->ecc.size;
+	uint8_t *bufpoi = buf;
+	int i, toread, sndrnd = 0, pos;
+
+	chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
+	for (i = 0; i < chip->ecc.steps; i++) {
+		if (sndrnd) {
+			pos = eccsize + i * (eccsize + chunk);
+			if (mtd->writesize > 512)
+				chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
+			else
+				chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
+		} else
+			sndrnd = 1;
+		toread = min_t(int, length, chunk);
+		chip->read_buf(mtd, bufpoi, toread);
+		bufpoi += toread;
+		length -= toread;
+	}
+	if (length > 0)
+		chip->read_buf(mtd, bufpoi, length);
+
+	return 1;
+}
+
+/**
+ * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @page:	page number to write
+ */
+static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
+			      int page)
+{
+	int status = 0;
+	const uint8_t *buf = chip->oob_poi;
+	int length = mtd->oobsize;
+
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+	chip->write_buf(mtd, buf, length);
+	/* Send command to program the OOB data */
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+	status = chip->waitfunc(mtd, chip);
+
+	return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/**
+ * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
+ *			     with syndrome - only for large page flash !
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @page:	page number to write
+ */
+static int nand_write_oob_syndrome(struct mtd_info *mtd,
+				   struct nand_chip *chip, int page)
+{
+	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+	int eccsize = chip->ecc.size, length = mtd->oobsize;
+	int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
+	const uint8_t *bufpoi = chip->oob_poi;
+
+	/*
+	 * data-ecc-data-ecc ... ecc-oob
+	 * or
+	 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
+	 */
+	if (!chip->ecc.prepad && !chip->ecc.postpad) {
+		pos = steps * (eccsize + chunk);
+		steps = 0;
+	} else
+		pos = eccsize;
+
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
+	for (i = 0; i < steps; i++) {
+		if (sndcmd) {
+			if (mtd->writesize <= 512) {
+				uint32_t fill = 0xFFFFFFFF;
+
+				len = eccsize;
+				while (len > 0) {
+					int num = min_t(int, len, 4);
+					chip->write_buf(mtd, (uint8_t *)&fill,
+							num);
+					len -= num;
+				}
+			} else {
+				pos = eccsize + i * (eccsize + chunk);
+				chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
+			}
+		} else
+			sndcmd = 1;
+		len = min_t(int, length, chunk);
+		chip->write_buf(mtd, bufpoi, len);
+		bufpoi += len;
+		length -= len;
+	}
+	if (length > 0)
+		chip->write_buf(mtd, bufpoi, length);
+
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+	status = chip->waitfunc(mtd, chip);
+
+	return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/**
+ * nand_do_read_oob - [Intern] NAND read out-of-band
+ * @mtd:	MTD device structure
+ * @from:	offset to read from
+ * @ops:	oob operations description structure
+ *
+ * NAND read out-of-band data from the spare area
+ */
+static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
+			    struct mtd_oob_ops *ops)
+{
+	int page, realpage, chipnr, sndcmd = 1;
+	struct nand_chip *chip = mtd->priv;
+	int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
+	int readlen = ops->ooblen;
+	int len;
+	uint8_t *buf = ops->oobbuf;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
+			__func__, (unsigned long long)from, readlen);
+
+	if (ops->mode == MTD_OOB_AUTO)
+		len = chip->ecc.layout->oobavail;
+	else
+		len = mtd->oobsize;
+
+	if (unlikely(ops->ooboffs >= len)) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
+					"outside oob\n", __func__);
 		return -EINVAL;
 	}
 
-	/* Grab the lock and see if the device is available */
-	nand_get_device (this, mtd , FL_READING);
+	/* Do not allow reads past end of device */
+	if (unlikely(from >= mtd->size ||
+		     ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
+					(from >> chip->page_shift)) * len)) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
+					"of device\n", __func__);
+		return -EINVAL;
+	}
 
-	this->select_chip (mtd, chip);
+	chipnr = (int)(from >> chip->chip_shift);
+	chip->select_chip(mtd, chipnr);
 
-	/* Add requested oob length */
-	len += ooblen;
+	/* Shift to get page */
+	realpage = (int)(from >> chip->page_shift);
+	page = realpage & chip->pagemask;
 
-	while (len) {
-		if (sndcmd)
-			this->cmdfunc (mtd, NAND_CMD_READ0, 0, page & this->pagemask);
-		sndcmd = 0;
+	while (1) {
+		WATCHDOG_RESET();
+		sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
 
-		this->read_buf (mtd, &buf[cnt], pagesize);
+		len = min(len, readlen);
+		buf = nand_transfer_oob(chip, buf, ops, len);
 
-		len -= pagesize;
-		cnt += pagesize;
-		page++;
+		if (!(chip->options & NAND_NO_READRDY)) {
+			/*
+			 * Apply delay or wait for ready/busy pin. Do this
+			 * before the AUTOINCR check, so no problems arise if a
+			 * chip which does auto increment is marked as
+			 * NOAUTOINCR by the board driver.
+			 */
+			if (!chip->dev_ready)
+				udelay(chip->chip_delay);
+			else
+				nand_wait_ready(mtd);
+		}
 
-		if (!this->dev_ready)
-			udelay (this->chip_delay);
-		else
-			while (!this->dev_ready(mtd));
+		readlen -= len;
+		if (!readlen)
+			break;
 
-		/* Check, if the chip supports auto page increment */
-		if (!NAND_CANAUTOINCR(this) || !(page & blockcheck))
+		/* Increment page address */
+		realpage++;
+
+		page = realpage & chip->pagemask;
+		/* Check, if we cross a chip boundary */
+		if (!page) {
+			chipnr++;
+			chip->select_chip(mtd, -1);
+			chip->select_chip(mtd, chipnr);
+		}
+
+		/* Check, if the chip supports auto page increment
+		 * or if we have hit a block boundary.
+		 */
+		if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
 			sndcmd = 1;
 	}
 
-	/* Deselect and wake up anyone waiting on the device */
-	nand_release_device(mtd);
+	ops->oobretlen = ops->ooblen;
 	return 0;
 }
 
-
 /**
- * nand_prepare_oobbuf - [GENERIC] Prepare the out of band buffer
+ * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
  * @mtd:	MTD device structure
- * @fsbuf:	buffer given by fs driver
- * @oobsel:	out of band selection structre
- * @autoplace:	1 = place given buffer into the oob bytes
- * @numpages:	number of pages to prepare
+ * @from:	offset to read from
+ * @ops:	oob operation description structure
  *
- * Return:
- * 1. Filesystem buffer available and autoplacement is off,
- *    return filesystem buffer
- * 2. No filesystem buffer or autoplace is off, return internal
- *    buffer
- * 3. Filesystem buffer is given and autoplace selected
- *    put data from fs buffer into internal buffer and
- *    retrun internal buffer
- *
- * Note: The internal buffer is filled with 0xff. This must
- * be done only once, when no autoplacement happens
- * Autoplacement sets the buffer dirty flag, which
- * forces the 0xff fill before using the buffer again.
- *
-*/
-static u_char * nand_prepare_oobbuf (struct mtd_info *mtd, u_char *fsbuf, struct nand_oobinfo *oobsel,
-		int autoplace, int numpages)
-{
-	struct nand_chip *this = mtd->priv;
-	int i, len, ofs;
-
-	/* Zero copy fs supplied buffer */
-	if (fsbuf && !autoplace)
-		return fsbuf;
-
-	/* Check, if the buffer must be filled with ff again */
-	if (this->oobdirty) {
-		memset (this->oob_buf, 0xff,
-			mtd->oobsize << (this->phys_erase_shift - this->page_shift));
-		this->oobdirty = 0;
-	}
-
-	/* If we have no autoplacement or no fs buffer use the internal one */
-	if (!autoplace || !fsbuf)
-		return this->oob_buf;
-
-	/* Walk through the pages and place the data */
-	this->oobdirty = 1;
-	ofs = 0;
-	while (numpages--) {
-		for (i = 0, len = 0; len < mtd->oobavail; i++) {
-			int to = ofs + oobsel->oobfree[i][0];
-			int num = oobsel->oobfree[i][1];
-			memcpy (&this->oob_buf[to], fsbuf, num);
-			len += num;
-			fsbuf += num;
-		}
-		ofs += mtd->oobavail;
-	}
-	return this->oob_buf;
-}
-
-#define NOTALIGNED(x) (x & (mtd->oobblock-1)) != 0
-
-/**
- * nand_write - [MTD Interface] compability function for nand_write_ecc
- * @mtd:	MTD device structure
- * @to:		offset to write to
- * @len:	number of bytes to write
- * @retlen:	pointer to variable to store the number of written bytes
- * @buf:	the data to write
- *
- * This function simply calls nand_write_ecc with oob buffer and oobsel = NULL
- *
-*/
-static int nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
-{
-	return (nand_write_ecc (mtd, to, len, retlen, buf, NULL, NULL));
-}
-
-/**
- * nand_write_ecc - [MTD Interface] NAND write with ECC
- * @mtd:	MTD device structure
- * @to:		offset to write to
- * @len:	number of bytes to write
- * @retlen:	pointer to variable to store the number of written bytes
- * @buf:	the data to write
- * @eccbuf:	filesystem supplied oob data buffer
- * @oobsel:	oob selection structure
- *
- * NAND write with ECC
+ * NAND read data and/or out-of-band data
  */
-static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
-			   size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel)
+static int nand_read_oob(struct mtd_info *mtd, loff_t from,
+			 struct mtd_oob_ops *ops)
 {
-	int startpage, page, ret = -EIO, oob = 0, written = 0, chipnr;
-	int autoplace = 0, numpages, totalpages;
-	struct nand_chip *this = mtd->priv;
-	u_char *oobbuf, *bufstart;
-	int	ppblock = (1 << (this->phys_erase_shift - this->page_shift));
+	struct nand_chip *chip = mtd->priv;
+	int ret = -ENOTSUPP;
 
-	DEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
+	ops->retlen = 0;
 
-	/* Initialize retlen, in case of early exit */
-	*retlen = 0;
-
-	/* Do not allow write past end of device */
-	if ((to + len) > mtd->size) {
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Attempt to write past end of page\n");
+	/* Do not allow reads past end of device */
+	if (ops->datbuf && (from + ops->len) > mtd->size) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
+				"beyond end of device\n", __func__);
 		return -EINVAL;
 	}
 
-	/* reject writes, which are not page aligned */
-	if (NOTALIGNED (to) || NOTALIGNED(len)) {
-		printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n");
-		return -EINVAL;
-	}
+	nand_get_device(chip, mtd, FL_READING);
 
-	/* Grab the lock and see if the device is available */
-	nand_get_device (this, mtd, FL_WRITING);
+	switch (ops->mode) {
+	case MTD_OOB_PLACE:
+	case MTD_OOB_AUTO:
+	case MTD_OOB_RAW:
+		break;
 
-	/* Calculate chipnr */
-	chipnr = (int)(to >> this->chip_shift);
-	/* Select the NAND device */
-	this->select_chip(mtd, chipnr);
-
-	/* Check, if it is write protected */
-	if (nand_check_wp(mtd))
+	default:
 		goto out;
-
-	/* if oobsel is NULL, use chip defaults */
-	if (oobsel == NULL)
-		oobsel = &mtd->oobinfo;
-
-	/* Autoplace of oob data ? Use the default placement scheme */
-	if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) {
-		oobsel = this->autooob;
-		autoplace = 1;
 	}
-	if (oobsel->useecc == MTD_NANDECC_AUTOPL_USR)
-		autoplace = 1;
 
-	/* Setup variables and oob buffer */
-	totalpages = len >> this->page_shift;
-	page = (int) (to >> this->page_shift);
-	/* Invalidate the page cache, if we write to the cached page */
-	if (page <= this->pagebuf && this->pagebuf < (page + totalpages))
-		this->pagebuf = -1;
-
-	/* Set it relative to chip */
-	page &= this->pagemask;
-	startpage = page;
-	/* Calc number of pages we can write in one go */
-	numpages = min (ppblock - (startpage  & (ppblock - 1)), totalpages);
-	oobbuf = nand_prepare_oobbuf (mtd, eccbuf, oobsel, autoplace, numpages);
-	bufstart = (u_char *)buf;
-
-	/* Loop until all data is written */
-	while (written < len) {
-
-		this->data_poi = (u_char*) &buf[written];
-		/* Write one page. If this is the last page to write
-		 * or the last page in this block, then use the
-		 * real pageprogram command, else select cached programming
-		 * if supported by the chip.
-		 */
-		ret = nand_write_page (mtd, this, page, &oobbuf[oob], oobsel, (--numpages > 0));
-		if (ret) {
-			DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: write_page failed %d\n", ret);
-			goto out;
-		}
-		/* Next oob page */
-		oob += mtd->oobsize;
-		/* Update written bytes count */
-		written += mtd->oobblock;
-		if (written == len)
-			goto cmp;
-
-		/* Increment page address */
-		page++;
-
-		/* Have we hit a block boundary ? Then we have to verify and
-		 * if verify is ok, we have to setup the oob buffer for
-		 * the next pages.
-		*/
-		if (!(page & (ppblock - 1))){
-			int ofs;
-			this->data_poi = bufstart;
-			ret = nand_verify_pages (mtd, this, startpage,
-				page - startpage,
-				oobbuf, oobsel, chipnr, (eccbuf != NULL));
-			if (ret) {
-				DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret);
-				goto out;
-			}
-			*retlen = written;
-
-			ofs = autoplace ? mtd->oobavail : mtd->oobsize;
-			if (eccbuf)
-				eccbuf += (page - startpage) * ofs;
-			totalpages -= page - startpage;
-			numpages = min (totalpages, ppblock);
-			page &= this->pagemask;
-			startpage = page;
-			oob = 0;
-			this->oobdirty = 1;
-			oobbuf = nand_prepare_oobbuf (mtd, eccbuf, oobsel,
-					autoplace, numpages);
-			/* Check, if we cross a chip boundary */
-			if (!page) {
-				chipnr++;
-				this->select_chip(mtd, -1);
-				this->select_chip(mtd, chipnr);
-			}
-		}
-	}
-	/* Verify the remaining pages */
-cmp:
-	this->data_poi = bufstart;
- 	ret = nand_verify_pages (mtd, this, startpage, totalpages,
-		oobbuf, oobsel, chipnr, (eccbuf != NULL));
-	if (!ret)
-		*retlen = written;
+	if (!ops->datbuf)
+		ret = nand_do_read_oob(mtd, from, ops);
 	else
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret);
+		ret = nand_do_read_ops(mtd, from, ops);
 
 out:
-	/* Deselect and wake up anyone waiting on the device */
 	nand_release_device(mtd);
-
 	return ret;
 }
 
 
 /**
- * nand_write_oob - [MTD Interface] NAND write out-of-band
- * @mtd:	MTD device structure
- * @to:		offset to write to
- * @len:	number of bytes to write
- * @retlen:	pointer to variable to store the number of written bytes
- * @buf:	the data to write
+ * nand_write_page_raw - [Intern] raw page write function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	data buffer
  *
- * NAND write out-of-band
+ * Not for syndrome calculating ecc controllers, which use a special oob layout
  */
-static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
+static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+				const uint8_t *buf)
 {
-	int column, page, status, ret = -EIO, chipnr;
-	struct nand_chip *this = mtd->priv;
+	chip->write_buf(mtd, buf, mtd->writesize);
+	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+}
 
-	DEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
+/**
+ * nand_write_page_raw_syndrome - [Intern] raw page write function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	data buffer
+ *
+ * We need a special oob layout and handling even when ECC isn't checked.
+ */
+static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
+					struct nand_chip *chip,
+					const uint8_t *buf)
+{
+	int eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	uint8_t *oob = chip->oob_poi;
+	int steps, size;
 
-	/* Shift to get page */
-	page = (int) (to >> this->page_shift);
-	chipnr = (int) (to >> this->chip_shift);
+	for (steps = chip->ecc.steps; steps > 0; steps--) {
+		chip->write_buf(mtd, buf, eccsize);
+		buf += eccsize;
 
-	/* Mask to get column */
-	column = to & (mtd->oobsize - 1);
+		if (chip->ecc.prepad) {
+			chip->write_buf(mtd, oob, chip->ecc.prepad);
+			oob += chip->ecc.prepad;
+		}
 
-	/* Initialize return length value */
-	*retlen = 0;
+		chip->read_buf(mtd, oob, eccbytes);
+		oob += eccbytes;
 
-	/* Do not allow write past end of page */
-	if ((column + len) > mtd->oobsize) {
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n");
-		return -EINVAL;
+		if (chip->ecc.postpad) {
+			chip->write_buf(mtd, oob, chip->ecc.postpad);
+			oob += chip->ecc.postpad;
+		}
 	}
 
-	/* Grab the lock and see if the device is available */
-	nand_get_device (this, mtd, FL_WRITING);
+	size = mtd->oobsize - (oob - chip->oob_poi);
+	if (size)
+		chip->write_buf(mtd, oob, size);
+}
+/**
+ * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	data buffer
+ */
+static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
+				  const uint8_t *buf)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	const uint8_t *p = buf;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
 
-	/* Select the NAND device */
-	this->select_chip(mtd, chipnr);
+	/* Software ecc calculation */
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 
-	/* Reset the chip. Some chips (like the Toshiba TC5832DC found
-	   in one of my DiskOnChip 2000 test units) will clear the whole
-	   data page too if we don't do this. I have no clue why, but
-	   I seem to have 'fixed' it in the doc2000 driver in
-	   August 1999.  dwmw2. */
-	this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+	for (i = 0; i < chip->ecc.total; i++)
+		chip->oob_poi[eccpos[i]] = ecc_calc[i];
 
-	/* Check, if it is write protected */
-	if (nand_check_wp(mtd))
-		goto out;
+	chip->ecc.write_page_raw(mtd, chip, buf);
+}
 
-	/* Invalidate the page cache, if we write to the cached page */
-	if (page == this->pagebuf)
-		this->pagebuf = -1;
+/**
+ * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	data buffer
+ */
+static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+				  const uint8_t *buf)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	const uint8_t *p = buf;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
 
-	if (NAND_MUST_PAD(this)) {
-		/* Write out desired data */
-		this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page & this->pagemask);
-		/* prepad 0xff for partial programming */
-		this->write_buf(mtd, ffchars, column);
-		/* write data */
-		this->write_buf(mtd, buf, len);
-		/* postpad 0xff for partial programming */
-		this->write_buf(mtd, ffchars, mtd->oobsize - (len+column));
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+		chip->write_buf(mtd, p, eccsize);
+		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+	}
+
+	for (i = 0; i < chip->ecc.total; i++)
+		chip->oob_poi[eccpos[i]] = ecc_calc[i];
+
+	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+}
+
+/**
+ * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
+ * @mtd:	mtd info structure
+ * @chip:	nand chip info structure
+ * @buf:	data buffer
+ *
+ * The hw generator calculates the error syndrome automatically. Therefor
+ * we need a special oob layout and handling.
+ */
+static void nand_write_page_syndrome(struct mtd_info *mtd,
+				    struct nand_chip *chip, const uint8_t *buf)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	const uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+
+		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+		chip->write_buf(mtd, p, eccsize);
+
+		if (chip->ecc.prepad) {
+			chip->write_buf(mtd, oob, chip->ecc.prepad);
+			oob += chip->ecc.prepad;
+		}
+
+		chip->ecc.calculate(mtd, p, oob);
+		chip->write_buf(mtd, oob, eccbytes);
+		oob += eccbytes;
+
+		if (chip->ecc.postpad) {
+			chip->write_buf(mtd, oob, chip->ecc.postpad);
+			oob += chip->ecc.postpad;
+		}
+	}
+
+	/* Calculate remaining oob bytes */
+	i = mtd->oobsize - (oob - chip->oob_poi);
+	if (i)
+		chip->write_buf(mtd, oob, i);
+}
+
+/**
+ * nand_write_page - [REPLACEABLE] write one page
+ * @mtd:	MTD device structure
+ * @chip:	NAND chip descriptor
+ * @buf:	the data to write
+ * @page:	page number to write
+ * @cached:	cached programming
+ * @raw:	use _raw version of write_page
+ */
+static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+			   const uint8_t *buf, int page, int cached, int raw)
+{
+	int status;
+
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+
+	if (unlikely(raw))
+		chip->ecc.write_page_raw(mtd, chip, buf);
+	else
+		chip->ecc.write_page(mtd, chip, buf);
+
+	/*
+	 * Cached progamming disabled for now, Not sure if its worth the
+	 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
+	 */
+	cached = 0;
+
+	if (!cached || !(chip->options & NAND_CACHEPRG)) {
+
+		chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+		status = chip->waitfunc(mtd, chip);
+		/*
+		 * See if operation failed and additional status checks are
+		 * available
+		 */
+		if ((status & NAND_STATUS_FAIL) && (chip->errstat))
+			status = chip->errstat(mtd, chip, FL_WRITING, status,
+					       page);
+
+		if (status & NAND_STATUS_FAIL)
+			return -EIO;
 	} else {
-		/* Write out desired data */
-		this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock + column, page & this->pagemask);
-		/* write data */
-		this->write_buf(mtd, buf, len);
+		chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
+		status = chip->waitfunc(mtd, chip);
 	}
-	/* Send command to program the OOB data */
-	this->cmdfunc (mtd, NAND_CMD_PAGEPROG, -1, -1);
-
-	status = this->waitfunc (mtd, this, FL_WRITING);
-
-	/* See if device thinks it succeeded */
-	if (status & 0x01) {
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page);
-		ret = -EIO;
-		goto out;
-	}
-	/* Return happy */
-	*retlen = len;
 
 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
 	/* Send command to read back the data */
-	this->cmdfunc (mtd, NAND_CMD_READOOB, column, page & this->pagemask);
+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
 
-	if (this->verify_buf(mtd, buf, len)) {
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write verify, page 0x%08x\n", page);
-		ret = -EIO;
-		goto out;
-	}
+	if (chip->verify_buf(mtd, buf, mtd->writesize))
+		return -EIO;
 #endif
-	ret = 0;
-out:
-	/* Deselect and wake up anyone waiting on the device */
+	return 0;
+}
+
+/**
+ * nand_fill_oob - [Internal] Transfer client buffer to oob
+ * @chip:	nand chip structure
+ * @oob:	oob data buffer
+ * @len:	oob data write length
+ * @ops:	oob ops structure
+ */
+static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
+						struct mtd_oob_ops *ops)
+{
+	switch (ops->mode) {
+
+	case MTD_OOB_PLACE:
+	case MTD_OOB_RAW:
+		memcpy(chip->oob_poi + ops->ooboffs, oob, len);
+		return oob + len;
+
+	case MTD_OOB_AUTO: {
+		struct nand_oobfree *free = chip->ecc.layout->oobfree;
+		uint32_t boffs = 0, woffs = ops->ooboffs;
+		size_t bytes = 0;
+
+		for (; free->length && len; free++, len -= bytes) {
+			/* Write request not from offset 0 ? */
+			if (unlikely(woffs)) {
+				if (woffs >= free->length) {
+					woffs -= free->length;
+					continue;
+				}
+				boffs = free->offset + woffs;
+				bytes = min_t(size_t, len,
+					      (free->length - woffs));
+				woffs = 0;
+			} else {
+				bytes = min_t(size_t, len, free->length);
+				boffs = free->offset;
+			}
+			memcpy(chip->oob_poi + boffs, oob, bytes);
+			oob += bytes;
+		}
+		return oob;
+	}
+	default:
+		BUG();
+	}
+	return NULL;
+}
+
+#define NOTALIGNED(x)	((x & (chip->subpagesize - 1)) != 0)
+
+/**
+ * nand_do_write_ops - [Internal] NAND write with ECC
+ * @mtd:	MTD device structure
+ * @to:		offset to write to
+ * @ops:	oob operations description structure
+ *
+ * NAND write with ECC
+ */
+static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
+			     struct mtd_oob_ops *ops)
+{
+	int chipnr, realpage, page, blockmask, column;
+	struct nand_chip *chip = mtd->priv;
+	uint32_t writelen = ops->len;
+
+	uint32_t oobwritelen = ops->ooblen;
+	uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
+				mtd->oobavail : mtd->oobsize;
+
+	uint8_t *oob = ops->oobbuf;
+	uint8_t *buf = ops->datbuf;
+	int ret, subpage;
+
+	ops->retlen = 0;
+	if (!writelen)
+		return 0;
+
+	column = to & (mtd->writesize - 1);
+	subpage = column || (writelen & (mtd->writesize - 1));
+
+	if (subpage && oob)
+		return -EINVAL;
+
+	chipnr = (int)(to >> chip->chip_shift);
+	chip->select_chip(mtd, chipnr);
+
+	/* Check, if it is write protected */
+	if (nand_check_wp(mtd)) {
+		printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
+		return -EIO;
+	}
+
+	realpage = (int)(to >> chip->page_shift);
+	page = realpage & chip->pagemask;
+	blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
+
+	/* Invalidate the page cache, when we write to the cached page */
+	if (to <= (chip->pagebuf << chip->page_shift) &&
+	    (chip->pagebuf << chip->page_shift) < (to + ops->len))
+		chip->pagebuf = -1;
+
+	/* If we're not given explicit OOB data, let it be 0xFF */
+	if (likely(!oob))
+		memset(chip->oob_poi, 0xff, mtd->oobsize);
+
+	/* Don't allow multipage oob writes with offset */
+	if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
+		return -EINVAL;
+
+	while (1) {
+		WATCHDOG_RESET();
+
+		int bytes = mtd->writesize;
+		int cached = writelen > bytes && page != blockmask;
+		uint8_t *wbuf = buf;
+
+		/* Partial page write ? */
+		if (unlikely(column || writelen < (mtd->writesize - 1))) {
+			cached = 0;
+			bytes = min_t(int, bytes - column, (int) writelen);
+			chip->pagebuf = -1;
+			memset(chip->buffers->databuf, 0xff, mtd->writesize);
+			memcpy(&chip->buffers->databuf[column], buf, bytes);
+			wbuf = chip->buffers->databuf;
+		}
+
+		if (unlikely(oob)) {
+			size_t len = min(oobwritelen, oobmaxlen);
+			oob = nand_fill_oob(chip, oob, len, ops);
+			oobwritelen -= len;
+		}
+
+		printf(" Page %d writesize %d writelen %d\n",page,bytes, cached);
+
+		ret = chip->write_page(mtd, chip, wbuf, page, cached,
+				       (ops->mode == MTD_OOB_RAW));
+		if (ret)
+			break;
+
+		writelen -= bytes;
+		if (!writelen)
+			break;
+
+		column = 0;
+		buf += bytes;
+		realpage++;
+
+		page = realpage & chip->pagemask;
+		/* Check, if we cross a chip boundary */
+		if (!page) {
+			chipnr++;
+			chip->select_chip(mtd, -1);
+			chip->select_chip(mtd, chipnr);
+		}
+	}
+
+	ops->retlen = ops->len - writelen;
+	if (unlikely(oob))
+		ops->oobretlen = ops->ooblen;
+	return ret;
+}
+
+/**
+ * nand_write - [MTD Interface] NAND write with ECC
+ * @mtd:	MTD device structure
+ * @to:		offset to write to
+ * @len:	number of bytes to write
+ * @retlen:	pointer to variable to store the number of written bytes
+ * @buf:	the data to write
+ *
+ * NAND write with ECC
+ */
+static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
+			  size_t *retlen, const uint8_t *buf)
+{
+	struct nand_chip *chip = mtd->priv;
+	int ret;
+
+	/* Do not allow writes past end of device */
+	if ((to + len) > mtd->size)
+		return -EINVAL;
+	if (!len)
+		return 0;
+
+	nand_get_device(chip, mtd, FL_WRITING);
+
+	chip->ops.len = len;
+	chip->ops.datbuf = (uint8_t *)buf;
+	chip->ops.oobbuf = NULL;
+
+	ret = nand_do_write_ops(mtd, to, &chip->ops);
+
+	*retlen = chip->ops.retlen;
+
 	nand_release_device(mtd);
 
 	return ret;
 }
 
-/* XXX U-BOOT XXX */
-#if 0
 /**
- * nand_writev - [MTD Interface] compabilty function for nand_writev_ecc
+ * nand_do_write_oob - [MTD Interface] NAND write out-of-band
  * @mtd:	MTD device structure
- * @vecs:	the iovectors to write
- * @count:	number of vectors
  * @to:		offset to write to
- * @retlen:	pointer to variable to store the number of written bytes
+ * @ops:	oob operation description structure
  *
- * NAND write with kvec. This just calls the ecc function
+ * NAND write out-of-band
  */
-static int nand_writev (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count,
-		loff_t to, size_t * retlen)
+static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
+			     struct mtd_oob_ops *ops)
 {
-	return (nand_writev_ecc (mtd, vecs, count, to, retlen, NULL, NULL));
-}
+	int chipnr, page, status, len;
+	struct nand_chip *chip = mtd->priv;
 
-/**
- * nand_writev_ecc - [MTD Interface] write with iovec with ecc
- * @mtd:	MTD device structure
- * @vecs:	the iovectors to write
- * @count:	number of vectors
- * @to:		offset to write to
- * @retlen:	pointer to variable to store the number of written bytes
- * @eccbuf:	filesystem supplied oob data buffer
- * @oobsel:	oob selection structure
- *
- * NAND write with iovec with ecc
- */
-static int nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count,
-		loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel)
-{
-	int i, page, len, total_len, ret = -EIO, written = 0, chipnr;
-	int oob, numpages, autoplace = 0, startpage;
-	struct nand_chip *this = mtd->priv;
-	int	ppblock = (1 << (this->phys_erase_shift - this->page_shift));
-	u_char *oobbuf, *bufstart;
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
+			 __func__, (unsigned int)to, (int)ops->ooblen);
 
-	/* Preset written len for early exit */
-	*retlen = 0;
-
-	/* Calculate total length of data */
-	total_len = 0;
-	for (i = 0; i < count; i++)
-		total_len += (int) vecs[i].iov_len;
-
-	DEBUG (MTD_DEBUG_LEVEL3,
-	       "nand_writev: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count);
+	if (ops->mode == MTD_OOB_AUTO)
+		len = chip->ecc.layout->oobavail;
+	else
+		len = mtd->oobsize;
 
 	/* Do not allow write past end of page */
-	if ((to + total_len) > mtd->size) {
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Attempted write past end of device\n");
+	if ((ops->ooboffs + ops->ooblen) > len) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
+				"past end of page\n", __func__);
 		return -EINVAL;
 	}
 
-	/* reject writes, which are not page aligned */
-	if (NOTALIGNED (to) || NOTALIGNED(total_len)) {
-		printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n");
+	if (unlikely(ops->ooboffs >= len)) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
+				"write outside oob\n", __func__);
 		return -EINVAL;
 	}
 
-	/* Grab the lock and see if the device is available */
-	nand_get_device (this, mtd, FL_WRITING);
+	/* Do not allow write past end of device */
+	if (unlikely(to >= mtd->size ||
+		     ops->ooboffs + ops->ooblen >
+			((mtd->size >> chip->page_shift) -
+			 (to >> chip->page_shift)) * len)) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
+				"end of device\n", __func__);
+		return -EINVAL;
+	}
 
-	/* Get the current chip-nr */
-	chipnr = (int) (to >> this->chip_shift);
-	/* Select the NAND device */
-	this->select_chip(mtd, chipnr);
+	chipnr = (int)(to >> chip->chip_shift);
+	chip->select_chip(mtd, chipnr);
+
+	/* Shift to get page */
+	page = (int)(to >> chip->page_shift);
+
+	/*
+	 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
+	 * of my DiskOnChip 2000 test units) will clear the whole data page too
+	 * if we don't do this. I have no clue why, but I seem to have 'fixed'
+	 * it in the doc2000 driver in August 1999.  dwmw2.
+	 */
+	chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 
 	/* Check, if it is write protected */
 	if (nand_check_wp(mtd))
-		goto out;
+		return -EROFS;
 
-	/* if oobsel is NULL, use chip defaults */
-	if (oobsel == NULL)
-		oobsel = &mtd->oobinfo;
-
-	/* Autoplace of oob data ? Use the default placement scheme */
-	if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) {
-		oobsel = this->autooob;
-		autoplace = 1;
-	}
-	if (oobsel->useecc == MTD_NANDECC_AUTOPL_USR)
-		autoplace = 1;
-
-	/* Setup start page */
-	page = (int) (to >> this->page_shift);
 	/* Invalidate the page cache, if we write to the cached page */
-	if (page <= this->pagebuf && this->pagebuf < ((to + total_len) >> this->page_shift))
-		this->pagebuf = -1;
+	if (page == chip->pagebuf)
+		chip->pagebuf = -1;
 
-	startpage = page & this->pagemask;
+	memset(chip->oob_poi, 0xff, mtd->oobsize);
+	nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
+	status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
+	memset(chip->oob_poi, 0xff, mtd->oobsize);
 
-	/* Loop until all kvec' data has been written */
-	len = 0;
-	while (count) {
-		/* If the given tuple is >= pagesize then
-		 * write it out from the iov
-		 */
-		if ((vecs->iov_len - len) >= mtd->oobblock) {
-			/* Calc number of pages we can write
-			 * out of this iov in one go */
-			numpages = (vecs->iov_len - len) >> this->page_shift;
-			/* Do not cross block boundaries */
-			numpages = min (ppblock - (startpage & (ppblock - 1)), numpages);
-			oobbuf = nand_prepare_oobbuf (mtd, NULL, oobsel, autoplace, numpages);
-			bufstart = (u_char *)vecs->iov_base;
-			bufstart += len;
-			this->data_poi = bufstart;
-			oob = 0;
-			for (i = 1; i <= numpages; i++) {
-				/* Write one page. If this is the last page to write
-				 * then use the real pageprogram command, else select
-				 * cached programming if supported by the chip.
-				 */
-				ret = nand_write_page (mtd, this, page & this->pagemask,
-					&oobbuf[oob], oobsel, i != numpages);
-				if (ret)
-					goto out;
-				this->data_poi += mtd->oobblock;
-				len += mtd->oobblock;
-				oob += mtd->oobsize;
-				page++;
-			}
-			/* Check, if we have to switch to the next tuple */
-			if (len >= (int) vecs->iov_len) {
-				vecs++;
-				len = 0;
-				count--;
-			}
-		} else {
-			/* We must use the internal buffer, read data out of each
-			 * tuple until we have a full page to write
-			 */
-			int cnt = 0;
-			while (cnt < mtd->oobblock) {
-				if (vecs->iov_base != NULL && vecs->iov_len)
-					this->data_buf[cnt++] = ((u_char *) vecs->iov_base)[len++];
-				/* Check, if we have to switch to the next tuple */
-				if (len >= (int) vecs->iov_len) {
-					vecs++;
-					len = 0;
-					count--;
-				}
-			}
-			this->pagebuf = page;
-			this->data_poi = this->data_buf;
-			bufstart = this->data_poi;
-			numpages = 1;
-			oobbuf = nand_prepare_oobbuf (mtd, NULL, oobsel, autoplace, numpages);
-			ret = nand_write_page (mtd, this, page & this->pagemask,
-				oobbuf, oobsel, 0);
-			if (ret)
-				goto out;
-			page++;
-		}
+	if (status)
+		return status;
 
-		this->data_poi = bufstart;
-		ret = nand_verify_pages (mtd, this, startpage, numpages, oobbuf, oobsel, chipnr, 0);
-		if (ret)
-			goto out;
+	ops->oobretlen = ops->ooblen;
 
-		written += mtd->oobblock * numpages;
-		/* All done ? */
-		if (!count)
-			break;
+	return 0;
+}
 
-		startpage = page & this->pagemask;
-		/* Check, if we cross a chip boundary */
-		if (!startpage) {
-			chipnr++;
-			this->select_chip(mtd, -1);
-			this->select_chip(mtd, chipnr);
-		}
+/**
+ * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
+ * @mtd:	MTD device structure
+ * @to:		offset to write to
+ * @ops:	oob operation description structure
+ */
+static int nand_write_oob(struct mtd_info *mtd, loff_t to,
+			  struct mtd_oob_ops *ops)
+{
+	struct nand_chip *chip = mtd->priv;
+	int ret = -ENOTSUPP;
+
+	ops->retlen = 0;
+
+	/* Do not allow writes past end of device */
+	if (ops->datbuf && (to + ops->len) > mtd->size) {
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
+				"end of device\n", __func__);
+		return -EINVAL;
 	}
-	ret = 0;
-out:
-	/* Deselect and wake up anyone waiting on the device */
-	nand_release_device(mtd);
 
-	*retlen = written;
+	nand_get_device(chip, mtd, FL_WRITING);
+
+	switch (ops->mode) {
+	case MTD_OOB_PLACE:
+	case MTD_OOB_AUTO:
+	case MTD_OOB_RAW:
+		break;
+
+	default:
+		goto out;
+	}
+
+	if (!ops->datbuf)
+		ret = nand_do_write_oob(mtd, to, ops);
+	else
+		ret = nand_do_write_ops(mtd, to, ops);
+
+out:
+	nand_release_device(mtd);
 	return ret;
 }
-#endif
 
 /**
  * single_erease_cmd - [GENERIC] NAND standard block erase command function
@@ -2045,12 +2189,12 @@
  *
  * Standard erase command for NAND chips
  */
-static void single_erase_cmd (struct mtd_info *mtd, int page)
+static void single_erase_cmd(struct mtd_info *mtd, int page)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 	/* Send commands to erase a block */
-	this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page);
-	this->cmdfunc (mtd, NAND_CMD_ERASE2, -1, -1);
+	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+	chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
 }
 
 /**
@@ -2061,15 +2205,15 @@
  * AND multi block erase command function
  * Erase 4 consecutive blocks
  */
-static void multi_erase_cmd (struct mtd_info *mtd, int page)
+static void multi_erase_cmd(struct mtd_info *mtd, int page)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 	/* Send commands to erase a block */
-	this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++);
-	this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++);
-	this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++);
-	this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page);
-	this->cmdfunc (mtd, NAND_CMD_ERASE2, -1, -1);
+	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
+	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
+	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
+	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+	chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
 }
 
 /**
@@ -2079,108 +2223,143 @@
  *
  * Erase one ore more blocks
  */
-static int nand_erase (struct mtd_info *mtd, struct erase_info *instr)
+static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
 {
-	return nand_erase_nand (mtd, instr, 0);
+	return nand_erase_nand(mtd, instr, 0);
 }
 
+#define BBT_PAGE_MASK	0xffffff3f
 /**
- * nand_erase_intern - [NAND Interface] erase block(s)
+ * nand_erase_nand - [Internal] erase block(s)
  * @mtd:	MTD device structure
  * @instr:	erase instruction
  * @allowbbt:	allow erasing the bbt area
  *
  * Erase one ore more blocks
  */
-int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt)
+int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
+		    int allowbbt)
 {
-	int page, len, status, pages_per_block, ret, chipnr;
-	struct nand_chip *this = mtd->priv;
+	int page, status, pages_per_block, ret, chipnr;
+	struct nand_chip *chip = mtd->priv;
+	loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
+	unsigned int bbt_masked_page = 0xffffffff;
+	loff_t len;
 
-	DEBUG (MTD_DEBUG_LEVEL3,
-	       "nand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len);
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
+				__func__, (unsigned long long)instr->addr,
+				(unsigned long long)instr->len);
 
-	/* Start address must align on block boundary */
-	if (instr->addr & ((1 << this->phys_erase_shift) - 1)) {
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
+	if (check_offs_len(mtd, instr->addr, instr->len))
 		return -EINVAL;
-	}
 
-	/* Length must align on block boundary */
-	if (instr->len & ((1 << this->phys_erase_shift) - 1)) {
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Length not block aligned\n");
-		return -EINVAL;
-	}
-
-	/* Do not allow erase past end of device */
-	if ((instr->len + instr->addr) > mtd->size) {
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Erase past end of device\n");
-		return -EINVAL;
-	}
-
-	instr->fail_addr = 0xffffffff;
+	instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
 
 	/* Grab the lock and see if the device is available */
-	nand_get_device (this, mtd, FL_ERASING);
+	nand_get_device(chip, mtd, FL_ERASING);
 
 	/* Shift to get first page */
-	page = (int) (instr->addr >> this->page_shift);
-	chipnr = (int) (instr->addr >> this->chip_shift);
+	page = (int)(instr->addr >> chip->page_shift);
+	chipnr = (int)(instr->addr >> chip->chip_shift);
 
 	/* Calculate pages in each block */
-	pages_per_block = 1 << (this->phys_erase_shift - this->page_shift);
+	pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
 
 	/* Select the NAND device */
-	this->select_chip(mtd, chipnr);
+	chip->select_chip(mtd, chipnr);
 
-	/* Check the WP bit */
 	/* Check, if it is write protected */
 	if (nand_check_wp(mtd)) {
-		DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Device is write protected!!!\n");
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
+					__func__);
 		instr->state = MTD_ERASE_FAILED;
 		goto erase_exit;
 	}
 
+	/*
+	 * If BBT requires refresh, set the BBT page mask to see if the BBT
+	 * should be rewritten. Otherwise the mask is set to 0xffffffff which
+	 * can not be matched. This is also done when the bbt is actually
+	 * erased to avoid recusrsive updates
+	 */
+	if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
+		bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
+
 	/* Loop through the pages */
 	len = instr->len;
 
 	instr->state = MTD_ERASING;
 
 	while (len) {
-#ifndef NAND_ALLOW_ERASE_ALL
-		/* Check if we have a bad block, we do not erase bad blocks ! */
-		if (nand_block_checkbad(mtd, ((loff_t) page) << this->page_shift, 0, allowbbt)) {
-			printk (KERN_WARNING "nand_erase: attempt to erase a bad block at page 0x%08x\n", page);
+		WATCHDOG_RESET();
+		/*
+		 * heck if we have a bad block, we do not erase bad blocks !
+		 */
+		if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
+					chip->page_shift, 0, allowbbt)) {
+			printk(KERN_WARNING "%s: attempt to erase a bad block "
+					"at page 0x%08x\n", __func__, page);
 			instr->state = MTD_ERASE_FAILED;
 			goto erase_exit;
 		}
-#endif
-		/* Invalidate the page cache, if we erase the block which contains
-		   the current cached page */
-		if (page <= this->pagebuf && this->pagebuf < (page + pages_per_block))
-			this->pagebuf = -1;
 
-		this->erase_cmd (mtd, page & this->pagemask);
+		/*
+		 * Invalidate the page cache, if we erase the block which
+		 * contains the current cached page
+		 */
+		if (page <= chip->pagebuf && chip->pagebuf <
+		    (page + pages_per_block))
+			chip->pagebuf = -1;
 
-		status = this->waitfunc (mtd, this, FL_ERASING);
+		chip->erase_cmd(mtd, page & chip->pagemask);
+
+		status = chip->waitfunc(mtd, chip);
+
+		/*
+		 * See if operation failed and additional status checks are
+		 * available
+		 */
+		if ((status & NAND_STATUS_FAIL) && (chip->errstat))
+			status = chip->errstat(mtd, chip, FL_ERASING,
+					       status, page);
 
 		/* See if block erase succeeded */
-		if (status & 0x01) {
-			DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page);
+		if (status & NAND_STATUS_FAIL) {
+			MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
+					"page 0x%08x\n", __func__, page);
 			instr->state = MTD_ERASE_FAILED;
-			instr->fail_addr = (page << this->page_shift);
+			instr->fail_addr =
+				((loff_t)page << chip->page_shift);
 			goto erase_exit;
 		}
 
+		/*
+		 * If BBT requires refresh, set the BBT rewrite flag to the
+		 * page being erased
+		 */
+		if (bbt_masked_page != 0xffffffff &&
+		    (page & BBT_PAGE_MASK) == bbt_masked_page)
+			rewrite_bbt[chipnr] =
+				((loff_t)page << chip->page_shift);
+
 		/* Increment page address and decrement length */
-		len -= (1 << this->phys_erase_shift);
+		len -= (1 << chip->phys_erase_shift);
 		page += pages_per_block;
 
 		/* Check, if we cross a chip boundary */
-		if (len && !(page & this->pagemask)) {
+		if (len && !(page & chip->pagemask)) {
 			chipnr++;
-			this->select_chip(mtd, -1);
-			this->select_chip(mtd, chipnr);
+			chip->select_chip(mtd, -1);
+			chip->select_chip(mtd, chipnr);
+
+			/*
+			 * If BBT requires refresh and BBT-PERCHIP, set the BBT
+			 * page mask to see if this BBT should be rewritten
+			 */
+			if (bbt_masked_page != 0xffffffff &&
+			    (chip->bbt_td->options & NAND_BBT_PERCHIP))
+				bbt_masked_page = chip->bbt_td->pages[chipnr] &
+					BBT_PAGE_MASK;
 		}
 	}
 	instr->state = MTD_ERASE_DONE;
@@ -2188,12 +2367,30 @@
 erase_exit:
 
 	ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
+
+	/* Deselect and wake up anyone waiting on the device */
+	nand_release_device(mtd);
+
 	/* Do call back function */
 	if (!ret)
 		mtd_erase_callback(instr);
 
-	/* Deselect and wake up anyone waiting on the device */
-	nand_release_device(mtd);
+	/*
+	 * If BBT requires refresh and erase was successful, rewrite any
+	 * selected bad block tables
+	 */
+	if (bbt_masked_page == 0xffffffff || ret)
+		return ret;
+
+	for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
+		if (!rewrite_bbt[chipnr])
+			continue;
+		/* update the BBT for chip */
+		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
+			"(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
+			rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
+		nand_update_bbt(mtd, rewrite_bbt[chipnr]);
+	}
 
 	/* Return more or less happy */
 	return ret;
@@ -2205,51 +2402,790 @@
  *
  * Sync is actually a wait for chip ready function
  */
-static void nand_sync (struct mtd_info *mtd)
+static void nand_sync(struct mtd_info *mtd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 
-	DEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
+	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
 
 	/* Grab the lock and see if the device is available */
-	nand_get_device (this, mtd, FL_SYNCING);
+	nand_get_device(chip, mtd, FL_SYNCING);
 	/* Release it and go back */
-	nand_release_device (mtd);
+	nand_release_device(mtd);
 }
 
-
 /**
- * nand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
+ * nand_block_isbad - [MTD Interface] Check if block at offset is bad
  * @mtd:	MTD device structure
- * @ofs:	offset relative to mtd start
+ * @offs:	offset relative to mtd start
  */
-static int nand_block_isbad (struct mtd_info *mtd, loff_t ofs)
+static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
 {
 	/* Check for invalid offset */
-	if (ofs > mtd->size)
+	if (offs > mtd->size)
 		return -EINVAL;
 
-	return nand_block_checkbad (mtd, ofs, 1, 0);
+	return nand_block_checkbad(mtd, offs, 1, 0);
 }
 
 /**
- * nand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
+ * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
  * @mtd:	MTD device structure
  * @ofs:	offset relative to mtd start
  */
-static int nand_block_markbad (struct mtd_info *mtd, loff_t ofs)
+static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 	int ret;
 
-	if ((ret = nand_block_isbad(mtd, ofs))) {
+	ret = nand_block_isbad(mtd, ofs);
+	if (ret) {
 		/* If it was bad already, return success and do nothing. */
 		if (ret > 0)
 			return 0;
 		return ret;
 	}
 
-	return this->block_markbad(mtd, ofs);
+	return chip->block_markbad(mtd, ofs);
+}
+
+/*
+ * Set default functions
+ */
+static void nand_set_defaults(struct nand_chip *chip, int busw)
+{
+	/* check for proper chip_delay setup, set 20us if not */
+	if (!chip->chip_delay)
+		chip->chip_delay = 20;
+
+	/* check, if a user supplied command function given */
+	if (chip->cmdfunc == NULL)
+		chip->cmdfunc = nand_command;
+
+	/* check, if a user supplied wait function given */
+	if (chip->waitfunc == NULL)
+		chip->waitfunc = nand_wait;
+
+	if (!chip->select_chip)
+		chip->select_chip = nand_select_chip;
+	if (!chip->read_byte)
+		chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
+	if (!chip->read_word)
+		chip->read_word = nand_read_word;
+	if (!chip->block_bad)
+		chip->block_bad = nand_block_bad;
+	if (!chip->block_markbad)
+		chip->block_markbad = nand_default_block_markbad;
+	if (!chip->write_buf)
+		chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
+	if (!chip->read_buf)
+		chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
+	if (!chip->verify_buf)
+		chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
+	if (!chip->scan_bbt)
+		chip->scan_bbt = nand_default_bbt;
+	if (!chip->controller)
+		chip->controller = &chip->hwcontrol;
+}
+
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+/*
+ * sanitize ONFI strings so we can safely print them
+ */
+static void sanitize_string(char *s, size_t len)
+{
+	ssize_t i;
+
+	/* null terminate */
+	s[len - 1] = 0;
+
+	/* remove non printable chars */
+	for (i = 0; i < len - 1; i++) {
+		if (s[i] < ' ' || s[i] > 127)
+			s[i] = '?';
+	}
+
+	/* remove trailing spaces */
+	strim(s);
+}
+
+static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
+{
+	int i;
+	while (len--) {
+		crc ^= *p++ << 8;
+		for (i = 0; i < 8; i++)
+			crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
+	}
+
+	return crc;
+}
+
+/*
+ * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
+ */
+static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
+					int *busw)
+{
+	struct nand_onfi_params *p = &chip->onfi_params;
+	int i;
+	int val;
+
+	/* try ONFI for unknow chip or LP */
+	chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
+	if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
+		chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
+		return 0;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL0, "ONFI flash detected\n");
+	chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
+	for (i = 0; i < 3; i++) {
+		chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
+		if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
+				le16_to_cpu(p->crc)) {
+			MTDDEBUG(MTD_DEBUG_LEVEL0,
+				 "ONFI param page %d valid\n", i);
+			break;
+		}
+	}
+
+	if (i == 3)
+		return 0;
+
+	/* check version */
+	val = le16_to_cpu(p->revision);
+	if (val & (1 << 5))
+		chip->onfi_version = 23;
+	else if (val & (1 << 4))
+		chip->onfi_version = 22;
+	else if (val & (1 << 3))
+		chip->onfi_version = 21;
+	else if (val & (1 << 2))
+		chip->onfi_version = 20;
+	else if (val & (1 << 1))
+		chip->onfi_version = 10;
+	else
+		chip->onfi_version = 0;
+
+	if (!chip->onfi_version) {
+		printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
+								__func__, val);
+		return 0;
+	}
+
+	sanitize_string(p->manufacturer, sizeof(p->manufacturer));
+	sanitize_string(p->model, sizeof(p->model));
+	if (!mtd->name)
+		mtd->name = p->model;
+	mtd->writesize = le32_to_cpu(p->byte_per_page);
+	mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
+	mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
+	chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
+	*busw = 0;
+	if (le16_to_cpu(p->features) & 1)
+		*busw = NAND_BUSWIDTH_16;
+
+	chip->options &= ~NAND_CHIPOPTIONS_MSK;
+	chip->options |= (NAND_NO_READRDY |
+			NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
+
+	return 1;
+}
+#else
+static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
+					struct nand_chip *chip,
+					int *busw)
+{
+	return 0;
+}
+#endif
+
+/*
+ * Get the flash and manufacturer id and lookup if the type is supported
+ */
+static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
+						  struct nand_chip *chip,
+						  int busw,
+						  int *maf_id, int *dev_id,
+						  const struct nand_flash_dev *type)
+{
+	int i, maf_idx;
+	u8 id_data[8];
+	int ret;
+
+	/* Select the device */
+	chip->select_chip(mtd, 0);
+
+	/*
+	 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
+	 * after power-up
+	 */
+	chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+	/* Send the command for reading device ID */
+	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+	/* Read manufacturer and device IDs */
+	*maf_id = chip->read_byte(mtd);
+	*dev_id = chip->read_byte(mtd);
+
+	/* Try again to make sure, as some systems the bus-hold or other
+	 * interface concerns can cause random data which looks like a
+	 * possibly credible NAND flash to appear. If the two results do
+	 * not match, ignore the device completely.
+	 */
+
+	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+	for (i = 0; i < 2; i++)
+		id_data[i] = chip->read_byte(mtd);
+
+	if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
+		printk(KERN_INFO "%s: second ID read did not match "
+		       "%02x,%02x against %02x,%02x\n", __func__,
+		       *maf_id, *dev_id, id_data[0], id_data[1]);
+		return ERR_PTR(-ENODEV);
+	}
+
+	if (!type)
+		type = nand_flash_ids;
+
+	for (; type->name != NULL; type++)
+		if (*dev_id == type->id)
+			break;
+
+	chip->onfi_version = 0;
+	if (!type->name || !type->pagesize) {
+		/* Check is chip is ONFI compliant */
+		ret = nand_flash_detect_onfi(mtd, chip, &busw);
+		if (ret)
+			goto ident_done;
+	}
+
+	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+	/* Read entire ID string */
+
+	for (i = 0; i < 8; i++)
+		id_data[i] = chip->read_byte(mtd);
+
+	if (!type->name)
+		return ERR_PTR(-ENODEV);
+
+	if (!mtd->name)
+		mtd->name = type->name;
+
+	chip->chipsize = (uint64_t)type->chipsize << 20;
+
+	if (!type->pagesize && chip->init_size) {
+		/* set the pagesize, oobsize, erasesize by the driver*/
+		busw = chip->init_size(mtd, chip, id_data);
+	} else if (!type->pagesize) {
+		int extid;
+		/* The 3rd id byte holds MLC / multichip data */
+		chip->cellinfo = id_data[2];
+		/* The 4th id byte is the important one */
+		extid = id_data[3];
+
+		/*
+		 * Field definitions are in the following datasheets:
+		 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
+		 * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
+		 *
+		 * Check for wraparound + Samsung ID + nonzero 6th byte
+		 * to decide what to do.
+		 */
+		if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
+				id_data[0] == NAND_MFR_SAMSUNG &&
+				(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+				id_data[5] != 0x00) {
+			/* Calc pagesize */
+			mtd->writesize = 2048 << (extid & 0x03);
+			extid >>= 2;
+			/* Calc oobsize */
+			switch (extid & 0x03) {
+			case 1:
+				mtd->oobsize = 128;
+				break;
+			case 2:
+				mtd->oobsize = 218;
+				break;
+			case 3:
+				mtd->oobsize = 400;
+				break;
+			default:
+				mtd->oobsize = 436;
+				break;
+			}
+			extid >>= 2;
+			/* Calc blocksize */
+			mtd->erasesize = (128 * 1024) <<
+				(((extid >> 1) & 0x04) | (extid & 0x03));
+			busw = 0;
+		} else {
+			/* Calc pagesize */
+			mtd->writesize = 1024 << (extid & 0x03);
+			extid >>= 2;
+			/* Calc oobsize */
+			mtd->oobsize = (8 << (extid & 0x01)) *
+				(mtd->writesize >> 9);
+			extid >>= 2;
+			/* Calc blocksize. Blocksize is multiples of 64KiB */
+			mtd->erasesize = (64 * 1024) << (extid & 0x03);
+			extid >>= 2;
+			/* Get buswidth information */
+			busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
+		}
+	} else {
+		/*
+		 * Old devices have chip data hardcoded in the device id table
+		 */
+		mtd->erasesize = type->erasesize;
+		mtd->writesize = type->pagesize;
+		mtd->oobsize = mtd->writesize / 32;
+		busw = type->options & NAND_BUSWIDTH_16;
+
+		/*
+		 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
+		 * some Spansion chips have erasesize that conflicts with size
+		 * listed in nand_ids table
+		 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
+		 */
+		if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
+				id_data[5] == 0x00 && id_data[6] == 0x00 &&
+				id_data[7] == 0x00 && mtd->writesize == 512) {
+			mtd->erasesize = 128 * 1024;
+			mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
+		}
+	}
+	/* Get chip options, preserve non chip based options */
+	chip->options &= ~NAND_CHIPOPTIONS_MSK;
+	chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
+
+	/* Check if chip is a not a samsung device. Do not clear the
+	 * options for chips which are not having an extended id.
+	 */
+	if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
+		chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
+ident_done:
+
+	/*
+	 * Set chip as a default. Board drivers can override it, if necessary
+	 */
+	chip->options |= NAND_NO_AUTOINCR;
+
+	/* Try to identify manufacturer */
+	for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
+		if (nand_manuf_ids[maf_idx].id == *maf_id)
+			break;
+	}
+
+	/*
+	 * Check, if buswidth is correct. Hardware drivers should set
+	 * chip correct !
+	 */
+	if (busw != (chip->options & NAND_BUSWIDTH_16)) {
+		printk(KERN_INFO "NAND device: Manufacturer ID:"
+		       " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
+		       *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
+		printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
+		       (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
+		       busw ? 16 : 8);
+		return ERR_PTR(-EINVAL);
+	}
+
+	/* Calculate the address shift from the page size */
+	chip->page_shift = ffs(mtd->writesize) - 1;
+	/* Convert chipsize to number of pages per chip -1. */
+	chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
+
+	chip->bbt_erase_shift = chip->phys_erase_shift =
+		ffs(mtd->erasesize) - 1;
+	if (chip->chipsize & 0xffffffff)
+		chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
+	else {
+		chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
+		chip->chip_shift += 32 - 1;
+	}
+
+	chip->badblockbits = 8;
+
+	/* Set the bad block position */
+	if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
+		chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
+	else
+		chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
+
+	/*
+	 * Bad block marker is stored in the last page of each block
+	 * on Samsung and Hynix MLC devices; stored in first two pages
+	 * of each block on Micron devices with 2KiB pages and on
+	 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
+	 * only the first page.
+	 */
+	if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+			(*maf_id == NAND_MFR_SAMSUNG ||
+			 *maf_id == NAND_MFR_HYNIX))
+		chip->options |= NAND_BBT_SCANLASTPAGE;
+	else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+				(*maf_id == NAND_MFR_SAMSUNG ||
+				 *maf_id == NAND_MFR_HYNIX ||
+				 *maf_id == NAND_MFR_TOSHIBA ||
+				 *maf_id == NAND_MFR_AMD)) ||
+			(mtd->writesize == 2048 &&
+			 *maf_id == NAND_MFR_MICRON))
+		chip->options |= NAND_BBT_SCAN2NDPAGE;
+
+	/*
+	 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
+	 */
+	if (!(busw & NAND_BUSWIDTH_16) &&
+			*maf_id == NAND_MFR_STMICRO &&
+			mtd->writesize == 2048) {
+		chip->options |= NAND_BBT_SCANBYTE1AND6;
+		chip->badblockpos = 0;
+	}
+
+	/* Check for AND chips with 4 page planes */
+	if (chip->options & NAND_4PAGE_ARRAY)
+		chip->erase_cmd = multi_erase_cmd;
+	else
+		chip->erase_cmd = single_erase_cmd;
+
+	/* Do not replace user supplied command function ! */
+	if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
+		chip->cmdfunc = nand_command_lp;
+
+	/* TODO onfi flash name */
+	MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
+		" 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
+		nand_manuf_ids[maf_idx].name,
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+		chip->onfi_version ? chip->onfi_params.model : type->name);
+#else
+		type->name);
+#endif
+
+	return type;
+}
+
+/**
+ * nand_scan_ident - [NAND Interface] Scan for the NAND device
+ * @mtd:	     MTD device structure
+ * @maxchips:	     Number of chips to scan for
+ * @table:	     Alternative NAND ID table
+ *
+ * This is the first phase of the normal nand_scan() function. It
+ * reads the flash ID and sets up MTD fields accordingly.
+ *
+ * The mtd->owner field must be set to the module of the caller.
+ */
+int nand_scan_ident(struct mtd_info *mtd, int maxchips,
+		    const struct nand_flash_dev *table)
+{
+	int i, busw, nand_maf_id, nand_dev_id;
+	struct nand_chip *chip = mtd->priv;
+	const struct nand_flash_dev *type;
+
+	/* Get buswidth to select the correct functions */
+	busw = chip->options & NAND_BUSWIDTH_16;
+	/* Set the default functions */
+	nand_set_defaults(chip, busw);
+
+	/* Read the flash type */
+	type = nand_get_flash_type(mtd, chip, busw,
+				&nand_maf_id, &nand_dev_id, table);
+
+	if (IS_ERR(type)) {
+#ifndef CONFIG_SYS_NAND_QUIET_TEST
+		printk(KERN_WARNING "No NAND device found!!!\n");
+#endif
+		chip->select_chip(mtd, -1);
+		return PTR_ERR(type);
+	}
+
+	/* Check for a chip array */
+	for (i = 1; i < maxchips; i++) {
+		chip->select_chip(mtd, i);
+		/* See comment in nand_get_flash_type for reset */
+		chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+		/* Send the command for reading device ID */
+		chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+		/* Read manufacturer and device IDs */
+		if (nand_maf_id != chip->read_byte(mtd) ||
+		    nand_dev_id != chip->read_byte(mtd))
+			break;
+	}
+#ifdef DEBUG
+	if (i > 1)
+		printk(KERN_INFO "%d NAND chips detected\n", i);
+#endif
+
+	/* Store the number of chips and calc total size for mtd */
+	chip->numchips = i;
+	mtd->size = i * chip->chipsize;
+
+	return 0;
+}
+
+
+/**
+ * nand_scan_tail - [NAND Interface] Scan for the NAND device
+ * @mtd:	    MTD device structure
+ *
+ * This is the second phase of the normal nand_scan() function. It
+ * fills out all the uninitialized function pointers with the defaults
+ * and scans for a bad block table if appropriate.
+ */
+int nand_scan_tail(struct mtd_info *mtd)
+{
+	int i;
+	struct nand_chip *chip = mtd->priv;
+
+	if (!(chip->options & NAND_OWN_BUFFERS))
+		chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
+	if (!chip->buffers)
+		return -ENOMEM;
+
+	/* Set the internal oob buffer location, just after the page data */
+	chip->oob_poi = chip->buffers->databuf + mtd->writesize;
+
+	/*
+	 * If no default placement scheme is given, select an appropriate one
+	 */
+	if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
+		switch (mtd->oobsize) {
+		case 8:
+			chip->ecc.layout = &nand_oob_8;
+			break;
+		case 16:
+			chip->ecc.layout = &nand_oob_16;
+			break;
+		case 64:
+			chip->ecc.layout = &nand_oob_64;
+			break;
+		case 128:
+			chip->ecc.layout = &nand_oob_128;
+			break;
+		case 224:
+			chip->ecc.layout = &nand_oob_128;
+			break;
+		default:
+			printk(KERN_WARNING "No oob scheme defined for "
+			       "oobsize %d\n", mtd->oobsize);
+		}
+	}
+
+	if (!chip->write_page)
+		chip->write_page = nand_write_page;
+
+	/*
+	 * check ECC mode, default to software if 3byte/512byte hardware ECC is
+	 * selected and we have 256 byte pagesize fallback to software ECC
+	 */
+
+	switch (chip->ecc.mode) {
+	case NAND_ECC_HW_OOB_FIRST:
+		/* Similar to NAND_ECC_HW, but a separate read_page handle */
+		if (!chip->ecc.calculate || !chip->ecc.correct ||
+		     !chip->ecc.hwctl) {
+			printk(KERN_WARNING "No ECC functions supplied; "
+			       "Hardware ECC not possible\n");
+			BUG();
+		}
+		if (!chip->ecc.read_page)
+			chip->ecc.read_page = nand_read_page_hwecc_oob_first;
+
+	case NAND_ECC_HW:
+		/* Use standard hwecc read page function ? */
+		if (!chip->ecc.read_page)
+			chip->ecc.read_page = nand_read_page_hwecc;
+		if (!chip->ecc.write_page)
+			chip->ecc.write_page = nand_write_page_hwecc;
+		if (!chip->ecc.read_page_raw)
+			chip->ecc.read_page_raw = nand_read_page_raw;
+		if (!chip->ecc.write_page_raw)
+			chip->ecc.write_page_raw = nand_write_page_raw;
+		if (!chip->ecc.read_oob)
+			chip->ecc.read_oob = nand_read_oob_std;
+		if (!chip->ecc.write_oob)
+			chip->ecc.write_oob = nand_write_oob_std;
+
+	case NAND_ECC_HW_SYNDROME:
+		if ((!chip->ecc.calculate || !chip->ecc.correct ||
+		     !chip->ecc.hwctl) &&
+		    (!chip->ecc.read_page ||
+		     chip->ecc.read_page == nand_read_page_hwecc ||
+		     !chip->ecc.write_page ||
+		     chip->ecc.write_page == nand_write_page_hwecc)) {
+			printk(KERN_WARNING "No ECC functions supplied; "
+			       "Hardware ECC not possible\n");
+			BUG();
+		}
+		/* Use standard syndrome read/write page function ? */
+		if (!chip->ecc.read_page)
+			chip->ecc.read_page = nand_read_page_syndrome;
+		if (!chip->ecc.write_page)
+			chip->ecc.write_page = nand_write_page_syndrome;
+		if (!chip->ecc.read_page_raw)
+			chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
+		if (!chip->ecc.write_page_raw)
+			chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
+		if (!chip->ecc.read_oob)
+			chip->ecc.read_oob = nand_read_oob_syndrome;
+		if (!chip->ecc.write_oob)
+			chip->ecc.write_oob = nand_write_oob_syndrome;
+
+		if (mtd->writesize >= chip->ecc.size)
+			break;
+		printk(KERN_WARNING "%d byte HW ECC not possible on "
+		       "%d byte page size, fallback to SW ECC\n",
+		       chip->ecc.size, mtd->writesize);
+		chip->ecc.mode = NAND_ECC_SOFT;
+
+	case NAND_ECC_SOFT:
+		chip->ecc.calculate = nand_calculate_ecc;
+		chip->ecc.correct = nand_correct_data;
+		chip->ecc.read_page = nand_read_page_swecc;
+		chip->ecc.read_subpage = nand_read_subpage;
+		chip->ecc.write_page = nand_write_page_swecc;
+		chip->ecc.read_page_raw = nand_read_page_raw;
+		chip->ecc.write_page_raw = nand_write_page_raw;
+		chip->ecc.read_oob = nand_read_oob_std;
+		chip->ecc.write_oob = nand_write_oob_std;
+		if (!chip->ecc.size)
+			chip->ecc.size = 256;
+		chip->ecc.bytes = 3;
+		break;
+#if defined CONFIG_BCH
+	case NAND_ECC_SOFT_BCH:
+		if (!mtd_nand_has_bch()) {
+			printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
+			return -EINVAL;
+		}
+		chip->ecc.calculate = nand_bch_calculate_ecc;
+		chip->ecc.correct = nand_bch_correct_data;
+		chip->ecc.read_page = nand_read_page_swecc;
+		chip->ecc.read_subpage = nand_read_subpage;
+		chip->ecc.write_page = nand_write_page_swecc;
+		chip->ecc.read_page_raw = nand_read_page_raw;
+		chip->ecc.write_page_raw = nand_write_page_raw;
+		chip->ecc.read_oob = nand_read_oob_std;
+		chip->ecc.write_oob = nand_write_oob_std;
+		/*
+		 * Board driver should supply ecc.size and ecc.bytes values to
+		 * select how many bits are correctable; see nand_bch_init()
+		 * for details.
+		 * Otherwise, default to 4 bits for large page devices
+		 */
+		if (!chip->ecc.size && (mtd->oobsize >= 64)) {
+			chip->ecc.size = 512;
+			chip->ecc.bytes = 7;
+		}
+		chip->ecc.priv = nand_bch_init(mtd,
+					       chip->ecc.size,
+					       chip->ecc.bytes,
+					       &chip->ecc.layout);
+		if (!chip->ecc.priv)
+			printk(KERN_WARNING "BCH ECC initialization failed!\n");
+
+		break;
+#endif
+
+	case NAND_ECC_NONE:
+		printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
+		       "This is not recommended !!\n");
+		chip->ecc.read_page = nand_read_page_raw;
+		chip->ecc.write_page = nand_write_page_raw;
+		chip->ecc.read_oob = nand_read_oob_std;
+		chip->ecc.read_page_raw = nand_read_page_raw;
+		chip->ecc.write_page_raw = nand_write_page_raw;
+		chip->ecc.write_oob = nand_write_oob_std;
+		chip->ecc.size = mtd->writesize;
+		chip->ecc.bytes = 0;
+		break;
+
+	default:
+		printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
+		       chip->ecc.mode);
+		BUG();
+	}
+
+	/*
+	 * The number of bytes available for a client to place data into
+	 * the out of band area
+	 */
+	chip->ecc.layout->oobavail = 0;
+	for (i = 0; chip->ecc.layout->oobfree[i].length
+			&& i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
+		chip->ecc.layout->oobavail +=
+			chip->ecc.layout->oobfree[i].length;
+	mtd->oobavail = chip->ecc.layout->oobavail;
+
+	/*
+	 * Set the number of read / write steps for one page depending on ECC
+	 * mode
+	 */
+	chip->ecc.steps = mtd->writesize / chip->ecc.size;
+	if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
+		printk(KERN_WARNING "Invalid ecc parameters\n");
+		BUG();
+	}
+	chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
+
+	/*
+	 * Allow subpage writes up to ecc.steps. Not possible for MLC
+	 * FLASH.
+	 */
+	if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
+	    !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
+		switch (chip->ecc.steps) {
+		case 2:
+			mtd->subpage_sft = 1;
+			break;
+		case 4:
+		case 8:
+		case 16:
+			mtd->subpage_sft = 2;
+			break;
+		}
+	}
+	chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
+
+	/* Initialize state */
+	chip->state = FL_READY;
+
+	/* De-select the device */
+	chip->select_chip(mtd, -1);
+
+	/* Invalidate the pagebuffer reference */
+	chip->pagebuf = -1;
+
+	/* Fill in remaining MTD driver data */
+	mtd->type = MTD_NANDFLASH;
+	mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
+						MTD_CAP_NANDFLASH;
+	mtd->erase = nand_erase;
+	mtd->point = NULL;
+	mtd->unpoint = NULL;
+	mtd->read = nand_read;
+	mtd->write = nand_write;
+	mtd->read_oob = nand_read_oob;
+	mtd->write_oob = nand_write_oob;
+	mtd->sync = nand_sync;
+	mtd->lock = NULL;
+	mtd->unlock = NULL;
+	mtd->block_isbad = nand_block_isbad;
+	mtd->block_markbad = nand_block_markbad;
+
+	/* propagate ecc.layout to mtd_info */
+	mtd->ecclayout = chip->ecc.layout;
+
+	/* Check, if we should skip the bad block table scan */
+	if (chip->options & NAND_SKIP_BBTSCAN)
+		chip->options |= NAND_BBT_SCANNED;
+
+	return 0;
 }
 
 /**
@@ -2257,409 +3193,48 @@
  * @mtd:	MTD device structure
  * @maxchips:	Number of chips to scan for
  *
- * This fills out all the not initialized function pointers
+ * This fills out all the uninitialized function pointers
  * with the defaults.
  * The flash ID is read and the mtd/chip structures are
- * filled with the appropriate values. Buffers are allocated if
- * they are not provided by the board driver
+ * filled with the appropriate values.
+ * The mtd->owner field must be set to the module of the caller
  *
  */
-int nand_scan (struct mtd_info *mtd, int maxchips)
+int nand_scan(struct mtd_info *mtd, int maxchips)
 {
-	int i, j, nand_maf_id, nand_dev_id, busw;
-	struct nand_chip *this = mtd->priv;
+	int ret;
 
-	/* Get buswidth to select the correct functions*/
-	busw = this->options & NAND_BUSWIDTH_16;
-
-	/* check for proper chip_delay setup, set 20us if not */
-	if (!this->chip_delay)
-		this->chip_delay = 20;
-
-	/* check, if a user supplied command function given */
-	if (this->cmdfunc == NULL)
-		this->cmdfunc = nand_command;
-
-	/* check, if a user supplied wait function given */
-	if (this->waitfunc == NULL)
-		this->waitfunc = nand_wait;
-
-	if (!this->select_chip)
-		this->select_chip = nand_select_chip;
-	if (!this->write_byte)
-		this->write_byte = busw ? nand_write_byte16 : nand_write_byte;
-	if (!this->read_byte)
-		this->read_byte = busw ? nand_read_byte16 : nand_read_byte;
-	if (!this->write_word)
-		this->write_word = nand_write_word;
-	if (!this->read_word)
-		this->read_word = nand_read_word;
-	if (!this->block_bad)
-		this->block_bad = nand_block_bad;
-	if (!this->block_markbad)
-		this->block_markbad = nand_default_block_markbad;
-	if (!this->write_buf)
-		this->write_buf = busw ? nand_write_buf16 : nand_write_buf;
-	if (!this->read_buf)
-		this->read_buf = busw ? nand_read_buf16 : nand_read_buf;
-	if (!this->verify_buf)
-		this->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
-	if (!this->scan_bbt)
-		this->scan_bbt = nand_default_bbt;
-
-	/* Select the device */
-	this->select_chip(mtd, 0);
-
-	/* Send the command for reading device ID */
-	this->cmdfunc (mtd, NAND_CMD_READID, 0x00, -1);
-
-	/* Read manufacturer and device IDs */
-	nand_maf_id = this->read_byte(mtd);
-	nand_dev_id = this->read_byte(mtd);
-
-	/* Print and store flash device information */
-	for (i = 0; nand_flash_ids[i].name != NULL; i++) {
-
-		if (nand_dev_id != nand_flash_ids[i].id)
-			continue;
-
-		if (!mtd->name) mtd->name = nand_flash_ids[i].name;
-		this->chipsize = nand_flash_ids[i].chipsize << 20;
-
-		/* New devices have all the information in additional id bytes */
-		if (!nand_flash_ids[i].pagesize) {
-			int extid;
-			/* The 3rd id byte contains non relevant data ATM */
-			extid = this->read_byte(mtd);
-			/* The 4th id byte is the important one */
-			extid = this->read_byte(mtd);
-			/* Calc pagesize */
-			mtd->oobblock = 1024 << (extid & 0x3);
-			extid >>= 2;
-			/* Calc oobsize */
-			mtd->oobsize = (8 << (extid & 0x03)) * (mtd->oobblock / 512);
-			extid >>= 2;
-			/* Calc blocksize. Blocksize is multiples of 64KiB */
-			mtd->erasesize = (64 * 1024)  << (extid & 0x03);
-			extid >>= 2;
-			/* Get buswidth information */
-			busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
-
-		} else {
-			/* Old devices have this data hardcoded in the
-			 * device id table */
-			mtd->erasesize = nand_flash_ids[i].erasesize;
-			mtd->oobblock = nand_flash_ids[i].pagesize;
-			mtd->oobsize = mtd->oobblock / 32;
-			busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16;
-		}
-
-		/* Check, if buswidth is correct. Hardware drivers should set
-		 * this correct ! */
-		if (busw != (this->options & NAND_BUSWIDTH_16)) {
-			printk (KERN_INFO "NAND device: Manufacturer ID:"
-				" 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id,
-				nand_manuf_ids[i].name , mtd->name);
-			printk (KERN_WARNING
-				"NAND bus width %d instead %d bit\n",
-					(this->options & NAND_BUSWIDTH_16) ? 16 : 8,
-					busw ? 16 : 8);
-			this->select_chip(mtd, -1);
-			return 1;
-		}
-
-		/* Calculate the address shift from the page size */
-		this->page_shift = ffs(mtd->oobblock) - 1;
-		this->bbt_erase_shift = this->phys_erase_shift = ffs(mtd->erasesize) - 1;
-		this->chip_shift = ffs(this->chipsize) - 1;
-
-		/* Set the bad block position */
-		this->badblockpos = mtd->oobblock > 512 ?
-			NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
-
-		/* Get chip options, preserve non chip based options */
-		this->options &= ~NAND_CHIPOPTIONS_MSK;
-		this->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK;
-		/* Set this as a default. Board drivers can override it, if neccecary */
-		this->options |= NAND_NO_AUTOINCR;
-		/* Check if this is a not a samsung device. Do not clear the options
-		 * for chips which are not having an extended id.
-		 */
-		if (nand_maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize)
-			this->options &= ~NAND_SAMSUNG_LP_OPTIONS;
-
-		/* Check for AND chips with 4 page planes */
-		if (this->options & NAND_4PAGE_ARRAY)
-			this->erase_cmd = multi_erase_cmd;
-		else
-			this->erase_cmd = single_erase_cmd;
-
-		/* Do not replace user supplied command function ! */
-		if (mtd->oobblock > 512 && this->cmdfunc == nand_command)
-			this->cmdfunc = nand_command_lp;
-
-		/* Try to identify manufacturer */
-		for (j = 0; nand_manuf_ids[j].id != 0x0; j++) {
-			if (nand_manuf_ids[j].id == nand_maf_id)
-				break;
-		}
-		break;
-	}
-
-	if (!nand_flash_ids[i].name) {
-		printk (KERN_WARNING "No NAND device found!!!\n");
-		this->select_chip(mtd, -1);
-		return 1;
-	}
-
-	for (i=1; i < maxchips; i++) {
-		this->select_chip(mtd, i);
-
-		/* Send the command for reading device ID */
-		this->cmdfunc (mtd, NAND_CMD_READID, 0x00, -1);
-
-		/* Read manufacturer and device IDs */
-		if (nand_maf_id != this->read_byte(mtd) ||
-		    nand_dev_id != this->read_byte(mtd))
-			break;
-	}
-	if (i > 1)
-		printk(KERN_INFO "%d NAND chips detected\n", i);
-
-	/* Allocate buffers, if neccecary */
-	if (!this->oob_buf) {
-		size_t len;
-		len = mtd->oobsize << (this->phys_erase_shift - this->page_shift);
-		this->oob_buf = kmalloc (len, GFP_KERNEL);
-		if (!this->oob_buf) {
-			printk (KERN_ERR "nand_scan(): Cannot allocate oob_buf\n");
-			return -ENOMEM;
-		}
-		this->options |= NAND_OOBBUF_ALLOC;
-	}
-
-	if (!this->data_buf) {
-		size_t len;
-		len = mtd->oobblock + mtd->oobsize;
-		this->data_buf = kmalloc (len, GFP_KERNEL);
-		if (!this->data_buf) {
-			if (this->options & NAND_OOBBUF_ALLOC)
-				kfree (this->oob_buf);
-			printk (KERN_ERR "nand_scan(): Cannot allocate data_buf\n");
-			return -ENOMEM;
-		}
-		this->options |= NAND_DATABUF_ALLOC;
-	}
-
-	/* Store the number of chips and calc total size for mtd */
-	this->numchips = i;
-	mtd->size = i * this->chipsize;
-	/* Convert chipsize to number of pages per chip -1. */
-	this->pagemask = (this->chipsize >> this->page_shift) - 1;
-	/* Preset the internal oob buffer */
-	memset(this->oob_buf, 0xff, mtd->oobsize << (this->phys_erase_shift - this->page_shift));
-
-	/* If no default placement scheme is given, select an
-	 * appropriate one */
-	if (!this->autooob) {
-		/* Select the appropriate default oob placement scheme for
-		 * placement agnostic filesystems */
-		switch (mtd->oobsize) {
-		case 8:
-			this->autooob = &nand_oob_8;
-			break;
-		case 16:
-			this->autooob = &nand_oob_16;
-			break;
-		case 64:
-			this->autooob = &nand_oob_64;
-			break;
-		default:
-			printk (KERN_WARNING "No oob scheme defined for oobsize %d\n",
-				mtd->oobsize);
-/*			BUG(); */
-		}
-	}
-
-	/* The number of bytes available for the filesystem to place fs dependend
-	 * oob data */
-	if (this->options & NAND_BUSWIDTH_16) {
-		mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 2);
-		if (this->autooob->eccbytes & 0x01)
-			mtd->oobavail--;
-	} else
-		mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 1);
-
-	/*
-	 * check ECC mode, default to software
-	 * if 3byte/512byte hardware ECC is selected and we have 256 byte pagesize
-	 * fallback to software ECC
-	*/
-	this->eccsize = 256;	/* set default eccsize */
-	this->eccbytes = 3;
-
-	switch (this->eccmode) {
-	case NAND_ECC_HW12_2048:
-		if (mtd->oobblock < 2048) {
-			printk(KERN_WARNING "2048 byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
-			       mtd->oobblock);
-			this->eccmode = NAND_ECC_SOFT;
-			this->calculate_ecc = nand_calculate_ecc;
-			this->correct_data = nand_correct_data;
-		} else
-			this->eccsize = 2048;
-		break;
-
-	case NAND_ECC_HW3_512:
-	case NAND_ECC_HW6_512:
-	case NAND_ECC_HW8_512:
-		if (mtd->oobblock == 256) {
-			printk (KERN_WARNING "512 byte HW ECC not possible on 256 Byte pagesize, fallback to SW ECC \n");
-			this->eccmode = NAND_ECC_SOFT;
-			this->calculate_ecc = nand_calculate_ecc;
-			this->correct_data = nand_correct_data;
-		} else
-			this->eccsize = 512; /* set eccsize to 512 */
-		break;
-
-	case NAND_ECC_HW3_256:
-		break;
-
-	case NAND_ECC_NONE:
-		printk (KERN_WARNING "NAND_ECC_NONE selected by board driver. This is not recommended !!\n");
-		this->eccmode = NAND_ECC_NONE;
-		break;
-
-	case NAND_ECC_SOFT:
-		this->calculate_ecc = nand_calculate_ecc;
-		this->correct_data = nand_correct_data;
-		break;
-
-	default:
-		printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
-/*		BUG(); */
-	}
-
-	/* Check hardware ecc function availability and adjust number of ecc bytes per
-	 * calculation step
-	*/
-	switch (this->eccmode) {
-	case NAND_ECC_HW12_2048:
-		this->eccbytes += 4;
-	case NAND_ECC_HW8_512:
-		this->eccbytes += 2;
-	case NAND_ECC_HW6_512:
-		this->eccbytes += 3;
-	case NAND_ECC_HW3_512:
-	case NAND_ECC_HW3_256:
-		if (this->calculate_ecc && this->correct_data && this->enable_hwecc)
-			break;
-		printk (KERN_WARNING "No ECC functions supplied, Hardware ECC not possible\n");
-/*		BUG();	*/
-	}
-
-	mtd->eccsize = this->eccsize;
-
-	/* Set the number of read / write steps for one page to ensure ECC generation */
-	switch (this->eccmode) {
-	case NAND_ECC_HW12_2048:
-		this->eccsteps = mtd->oobblock / 2048;
-		break;
-	case NAND_ECC_HW3_512:
-	case NAND_ECC_HW6_512:
-	case NAND_ECC_HW8_512:
-		this->eccsteps = mtd->oobblock / 512;
-		break;
-	case NAND_ECC_HW3_256:
-	case NAND_ECC_SOFT:
-		this->eccsteps = mtd->oobblock / 256;
-		break;
-
-	case NAND_ECC_NONE:
-		this->eccsteps = 1;
-		break;
-	}
-
-/* XXX U-BOOT XXX */
-#if 0
-	/* Initialize state, waitqueue and spinlock */
-	this->state = FL_READY;
-	init_waitqueue_head (&this->wq);
-	spin_lock_init (&this->chip_lock);
-#endif
-
-	/* De-select the device */
-	this->select_chip(mtd, -1);
-
-	/* Invalidate the pagebuffer reference */
-	this->pagebuf = -1;
-
-	/* Fill in remaining MTD driver data */
-	mtd->type = MTD_NANDFLASH;
-	mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC;
-	mtd->ecctype = MTD_ECC_SW;
-	mtd->erase = nand_erase;
-	mtd->point = NULL;
-	mtd->unpoint = NULL;
-	mtd->read = nand_read;
-	mtd->write = nand_write;
-	mtd->read_ecc = nand_read_ecc;
-	mtd->write_ecc = nand_write_ecc;
-	mtd->read_oob = nand_read_oob;
-	mtd->write_oob = nand_write_oob;
-/* XXX U-BOOT XXX */
-#if 0
-	mtd->readv = NULL;
-	mtd->writev = nand_writev;
-	mtd->writev_ecc = nand_writev_ecc;
-#endif
-	mtd->sync = nand_sync;
-/* XXX U-BOOT XXX */
-#if 0
-	mtd->lock = NULL;
-	mtd->unlock = NULL;
-	mtd->suspend = NULL;
-	mtd->resume = NULL;
-#endif
-	mtd->block_isbad = nand_block_isbad;
-	mtd->block_markbad = nand_block_markbad;
-
-	/* and make the autooob the default one */
-	memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo));
-/* XXX U-BOOT XXX */
-#if 0
-	mtd->owner = THIS_MODULE;
-#endif
-	/* Build bad block table */
-	return this->scan_bbt (mtd);
+	ret = nand_scan_ident(mtd, maxchips, NULL);
+	if (!ret)
+		ret = nand_scan_tail(mtd);
+	return ret;
 }
 
 /**
  * nand_release - [NAND Interface] Free resources held by the NAND device
  * @mtd:	MTD device structure
- */
-void nand_release (struct mtd_info *mtd)
+*/
+void nand_release(struct mtd_info *mtd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
+
+#if defined CONFIG_BCH
+	if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
+		nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
+#endif
 
 #ifdef CONFIG_MTD_PARTITIONS
 	/* Deregister partitions */
-	del_mtd_partitions (mtd);
+	del_mtd_partitions(mtd);
 #endif
-	/* Deregister the device */
-/* XXX U-BOOT XXX */
-#if 0
-	del_mtd_device (mtd);
-#endif
-	/* Free bad block table memory, if allocated */
-	if (this->bbt)
-		kfree (this->bbt);
-	/* Buffer allocated by nand_scan ? */
-	if (this->options & NAND_OOBBUF_ALLOC)
-		kfree (this->oob_buf);
-	/* Buffer allocated by nand_scan ? */
-	if (this->options & NAND_DATABUF_ALLOC)
-		kfree (this->data_buf);
-}
 
-#endif
+	/* Free bad block table memory */
+	kfree(chip->bbt);
+	if (!(chip->options & NAND_OWN_BUFFERS))
+		kfree(chip->buffers);
+
+	/* Free bad block descriptor memory */
+	if (chip->badblock_pattern && chip->badblock_pattern->options
+			& NAND_BBT_DYNAMICSTRUCT)
+		kfree(chip->badblock_pattern);
+}

drivers/nand/nand_bbt.c

diff --git a/drivers/nand/nand_bbt.c b/drivers/nand/nand_bbt.c
index aaa9400..1db8f27 100644
--- a/drivers/nand/nand_bbt.c
+++ b/drivers/nand/nand_bbt.c
@@ -6,8 +6,6 @@
  *
  *  Copyright (C) 2004 Thomas Gleixner (tglx@linutronix.de)
  *
- * $Id: nand_bbt.c,v 1.28 2004/11/13 10:19:09 gleixner Exp $
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
@@ -15,28 +13,37 @@
  * Description:
  *
  * When nand_scan_bbt is called, then it tries to find the bad block table
- * depending on the options in the bbt descriptor(s). If a bbt is found
- * then the contents are read and the memory based bbt is created. If a
- * mirrored bbt is selected then the mirror is searched too and the
- * versions are compared. If the mirror has a greater version number
- * than the mirror bbt is used to build the memory based bbt.
+ * depending on the options in the BBT descriptor(s). If no flash based BBT
+ * (NAND_USE_FLASH_BBT) is specified then the device is scanned for factory
+ * marked good / bad blocks. This information is used to create a memory BBT.
+ * Once a new bad block is discovered then the "factory" information is updated
+ * on the device.
+ * If a flash based BBT is specified then the function first tries to find the
+ * BBT on flash. If a BBT is found then the contents are read and the memory
+ * based BBT is created. If a mirrored BBT is selected then the mirror is
+ * searched too and the versions are compared. If the mirror has a greater
+ * version number than the mirror BBT is used to build the memory based BBT.
  * If the tables are not versioned, then we "or" the bad block information.
- * If one of the bbt's is out of date or does not exist it is (re)created.
- * If no bbt exists at all then the device is scanned for factory marked
+ * If one of the BBTs is out of date or does not exist it is (re)created.
+ * If no BBT exists at all then the device is scanned for factory marked
  * good / bad blocks and the bad block tables are created.
  *
- * For manufacturer created bbts like the one found on M-SYS DOC devices
- * the bbt is searched and read but never created
+ * For manufacturer created BBTs like the one found on M-SYS DOC devices
+ * the BBT is searched and read but never created
  *
- * The autogenerated bad block table is located in the last good blocks
+ * The auto generated bad block table is located in the last good blocks
  * of the device. The table is mirrored, so it can be updated eventually.
- * The table is marked in the oob area with an ident pattern and a version
- * number which indicates which of both tables is more up to date.
+ * The table is marked in the OOB area with an ident pattern and a version
+ * number which indicates which of both tables is more up to date. If the NAND
+ * controller needs the complete OOB area for the ECC information then the
+ * option NAND_USE_FLASH_BBT_NO_OOB should be used: it moves the ident pattern
+ * and the version byte into the data area and the OOB area will remain
+ * untouched.
  *
  * The table uses 2 bits per block
- * 11b: 	block is good
- * 00b: 	block is factory marked bad
- * 01b, 10b: 	block is marked bad due to wear
+ * 11b:		block is good
+ * 00b:		block is factory marked bad
+ * 01b, 10b:	block is marked bad due to wear
  *
  * The memory bad block table uses the following scheme:
  * 00b:		block is good
@@ -48,21 +55,31 @@
  *
  * Following assumptions are made:
  * - bbts start at a page boundary, if autolocated on a block boundary
- * - the space neccecary for a bbt in FLASH does not exceed a block boundary
+ * - the space necessary for a bbt in FLASH does not exceed a block boundary
  *
  */
 
 #include <common.h>
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-
 #include <malloc.h>
-#include <linux/mtd/compat.h>
+#include <linux/compiler.h>
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/bitops.h>
 
 #include <asm/errno.h>
 
+static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td)
+{
+	int ret;
+
+	ret = memcmp(buf, td->pattern, td->len);
+	if (!ret)
+		return ret;
+	return -1;
+}
+
 /**
  * check_pattern - [GENERIC] check if a pattern is in the buffer
  * @buf:	the buffer to search
@@ -76,11 +93,14 @@
  * pattern area contain 0xff
  *
 */
-static int check_pattern (uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td)
+static int check_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td)
 {
-	int i, end;
+	int i, end = 0;
 	uint8_t *p = buf;
 
+	if (td->options & NAND_BBT_NO_OOB)
+		return check_pattern_no_oob(buf, td);
+
 	end = paglen + td->offs;
 	if (td->options & NAND_BBT_SCANEMPTY) {
 		for (i = 0; i < end; i++) {
@@ -96,9 +116,31 @@
 			return -1;
 	}
 
-	p += td->len;
-	end += td->len;
+	/* Check both positions 1 and 6 for pattern? */
+	if (td->options & NAND_BBT_SCANBYTE1AND6) {
+		if (td->options & NAND_BBT_SCANEMPTY) {
+			p += td->len;
+			end += NAND_SMALL_BADBLOCK_POS - td->offs;
+			/* Check region between positions 1 and 6 */
+			for (i = 0; i < NAND_SMALL_BADBLOCK_POS - td->offs - td->len;
+					i++) {
+				if (*p++ != 0xff)
+					return -1;
+			}
+		}
+		else {
+			p += NAND_SMALL_BADBLOCK_POS - td->offs;
+		}
+		/* Compare the pattern */
+		for (i = 0; i < td->len; i++) {
+			if (p[i] != td->pattern[i])
+				return -1;
+		}
+	}
+
 	if (td->options & NAND_BBT_SCANEMPTY) {
+		p += td->len;
+		end += td->len;
 		for (i = end; i < len; i++) {
 			if (*p++ != 0xff)
 				return -1;
@@ -108,39 +150,100 @@
 }
 
 /**
+ * check_short_pattern - [GENERIC] check if a pattern is in the buffer
+ * @buf:	the buffer to search
+ * @td:		search pattern descriptor
+ *
+ * Check for a pattern at the given place. Used to search bad block
+ * tables and good / bad block identifiers. Same as check_pattern, but
+ * no optional empty check
+ *
+*/
+static int check_short_pattern(uint8_t *buf, struct nand_bbt_descr *td)
+{
+	int i;
+	uint8_t *p = buf;
+
+	/* Compare the pattern */
+	for (i = 0; i < td->len; i++) {
+		if (p[td->offs + i] != td->pattern[i])
+			return -1;
+	}
+	/* Need to check location 1 AND 6? */
+	if (td->options & NAND_BBT_SCANBYTE1AND6) {
+		for (i = 0; i < td->len; i++) {
+			if (p[NAND_SMALL_BADBLOCK_POS + i] != td->pattern[i])
+				return -1;
+		}
+	}
+	return 0;
+}
+
+/**
+ * add_marker_len - compute the length of the marker in data area
+ * @td:		BBT descriptor used for computation
+ *
+ * The length will be 0 if the markeris located in OOB area.
+ */
+static u32 add_marker_len(struct nand_bbt_descr *td)
+{
+	u32 len;
+
+	if (!(td->options & NAND_BBT_NO_OOB))
+		return 0;
+
+	len = td->len;
+	if (td->options & NAND_BBT_VERSION)
+		len++;
+	return len;
+}
+
+/**
  * read_bbt - [GENERIC] Read the bad block table starting from page
  * @mtd:	MTD device structure
  * @buf:	temporary buffer
  * @page:	the starting page
  * @num:	the number of bbt descriptors to read
- * @bits:	number of bits per block
+ * @td:		the bbt describtion table
  * @offs:	offset in the memory table
- * @reserved_block_code:	Pattern to identify reserved blocks
  *
  * Read the bad block table starting from page.
  *
  */
-static int read_bbt (struct mtd_info *mtd, uint8_t *buf, int page, int num,
-	int bits, int offs, int reserved_block_code)
+static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num,
+		struct nand_bbt_descr *td, int offs)
 {
 	int res, i, j, act = 0;
 	struct nand_chip *this = mtd->priv;
 	size_t retlen, len, totlen;
 	loff_t from;
+	int bits = td->options & NAND_BBT_NRBITS_MSK;
 	uint8_t msk = (uint8_t) ((1 << bits) - 1);
+	u32 marker_len;
+	int reserved_block_code = td->reserved_block_code;
 
 	totlen = (num * bits) >> 3;
-	from = ((loff_t)page) << this->page_shift;
+	marker_len = add_marker_len(td);
+	from = ((loff_t) page) << this->page_shift;
 
 	while (totlen) {
-		len = min (totlen, (size_t) (1 << this->bbt_erase_shift));
-		res = mtd->read_ecc (mtd, from, len, &retlen, buf, NULL, this->autooob);
+		len = min(totlen, (size_t) (1 << this->bbt_erase_shift));
+		if (marker_len) {
+			/*
+			 * In case the BBT marker is not in the OOB area it
+			 * will be just in the first page.
+			 */
+			len -= marker_len;
+			from += marker_len;
+			marker_len = 0;
+		}
+		res = mtd->read(mtd, from, len, &retlen, buf);
 		if (res < 0) {
 			if (retlen != len) {
-				printk (KERN_INFO "nand_bbt: Error reading bad block table\n");
+				printk(KERN_INFO "nand_bbt: Error reading bad block table\n");
 				return res;
 			}
-			printk (KERN_WARNING "nand_bbt: ECC error while reading bad block table\n");
+			printk(KERN_WARNING "nand_bbt: ECC error while reading bad block table\n");
 		}
 
 		/* Analyse data */
@@ -150,22 +253,23 @@
 				uint8_t tmp = (dat >> j) & msk;
 				if (tmp == msk)
 					continue;
-				if (reserved_block_code &&
-				    (tmp == reserved_block_code)) {
-					printk (KERN_DEBUG "nand_read_bbt: Reserved block at 0x%08x\n",
-						((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
+				if (reserved_block_code && (tmp == reserved_block_code)) {
+					printk(KERN_DEBUG "nand_read_bbt: Reserved block at 0x%012llx\n",
+					       (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
 					this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06);
+					mtd->ecc_stats.bbtblocks++;
 					continue;
 				}
-				/* Leave it for now, if its matured we can move this
-				 * message to MTD_DEBUG_LEVEL0 */
-				printk (KERN_DEBUG "nand_read_bbt: Bad block at 0x%08x\n",
-					((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
+				MTDDEBUG(MTD_DEBUG_LEVEL0, "nand_read_bbt: " \
+					"Bad block at 0x%012llx\n",
+					(loff_t)((offs << 2) + (act >> 1))
+					<< this->bbt_erase_shift);
 				/* Factory marked bad or worn out ? */
 				if (tmp == 0)
 					this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06);
 				else
 					this->bbt[offs + (act >> 3)] |= 0x1 << (act & 0x06);
+				mtd->ecc_stats.badblocks++;
 			}
 		}
 		totlen -= len;
@@ -185,30 +289,119 @@
  * Read the bad block table for all chips starting at a given page
  * We assume that the bbt bits are in consecutive order.
 */
-static int read_abs_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip)
+static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip)
 {
 	struct nand_chip *this = mtd->priv;
 	int res = 0, i;
-	int bits;
 
-	bits = td->options & NAND_BBT_NRBITS_MSK;
 	if (td->options & NAND_BBT_PERCHIP) {
 		int offs = 0;
 		for (i = 0; i < this->numchips; i++) {
 			if (chip == -1 || chip == i)
-				res = read_bbt (mtd, buf, td->pages[i], this->chipsize >> this->bbt_erase_shift, bits, offs, td->reserved_block_code);
+				res = read_bbt(mtd, buf, td->pages[i],
+					this->chipsize >> this->bbt_erase_shift,
+					td, offs);
 			if (res)
 				return res;
 			offs += this->chipsize >> (this->bbt_erase_shift + 2);
 		}
 	} else {
-		res = read_bbt (mtd, buf, td->pages[0], mtd->size >> this->bbt_erase_shift, bits, 0, td->reserved_block_code);
+		res = read_bbt(mtd, buf, td->pages[0],
+				mtd->size >> this->bbt_erase_shift, td, 0);
 		if (res)
 			return res;
 	}
 	return 0;
 }
 
+/*
+ * BBT marker is in the first page, no OOB.
+ */
+static int scan_read_raw_data(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
+			 struct nand_bbt_descr *td)
+{
+	size_t retlen;
+	size_t len;
+
+	len = td->len;
+	if (td->options & NAND_BBT_VERSION)
+		len++;
+
+	return mtd->read(mtd, offs, len, &retlen, buf);
+}
+
+/*
+ * Scan read raw data from flash
+ */
+static int scan_read_raw_oob(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
+			 size_t len)
+{
+	struct mtd_oob_ops ops;
+	int res;
+
+	ops.mode = MTD_OOB_RAW;
+	ops.ooboffs = 0;
+	ops.ooblen = mtd->oobsize;
+
+
+	while (len > 0) {
+		if (len <= mtd->writesize) {
+			ops.oobbuf = buf + len;
+			ops.datbuf = buf;
+			ops.len = len;
+			return mtd->read_oob(mtd, offs, &ops);
+		} else {
+			ops.oobbuf = buf + mtd->writesize;
+			ops.datbuf = buf;
+			ops.len = mtd->writesize;
+			res = mtd->read_oob(mtd, offs, &ops);
+
+			if (res)
+				return res;
+		}
+
+		buf += mtd->oobsize + mtd->writesize;
+		len -= mtd->writesize;
+	}
+	return 0;
+}
+
+static int scan_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
+			 size_t len, struct nand_bbt_descr *td)
+{
+	if (td->options & NAND_BBT_NO_OOB)
+		return scan_read_raw_data(mtd, buf, offs, td);
+	else
+		return scan_read_raw_oob(mtd, buf, offs, len);
+}
+
+/*
+ * Scan write data with oob to flash
+ */
+static int scan_write_bbt(struct mtd_info *mtd, loff_t offs, size_t len,
+			  uint8_t *buf, uint8_t *oob)
+{
+	struct mtd_oob_ops ops;
+
+	ops.mode = MTD_OOB_PLACE;
+	ops.ooboffs = 0;
+	ops.ooblen = mtd->oobsize;
+	ops.datbuf = buf;
+	ops.oobbuf = oob;
+	ops.len = len;
+
+	return mtd->write_oob(mtd, offs, &ops);
+}
+
+static u32 bbt_get_ver_offs(struct mtd_info *mtd, struct nand_bbt_descr *td)
+{
+	u32 ver_offs = td->veroffs;
+
+	if (!(td->options & NAND_BBT_NO_OOB))
+		ver_offs += mtd->writesize;
+	return ver_offs;
+}
+
 /**
  * read_abs_bbts - [GENERIC] Read the bad block table(s) for all chips starting at a given page
  * @mtd:	MTD device structure
@@ -220,28 +413,84 @@
  * We assume that the bbt bits are in consecutive order.
  *
 */
-static int read_abs_bbts (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td,
-	struct nand_bbt_descr *md)
+static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf,
+			 struct nand_bbt_descr *td, struct nand_bbt_descr *md)
 {
 	struct nand_chip *this = mtd->priv;
 
 	/* Read the primary version, if available */
 	if (td->options & NAND_BBT_VERSION) {
-		nand_read_raw (mtd, buf, td->pages[0] << this->page_shift, mtd->oobblock, mtd->oobsize);
-		td->version[0] = buf[mtd->oobblock + td->veroffs];
-		printk (KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", td->pages[0], td->version[0]);
+		scan_read_raw(mtd, buf, (loff_t)td->pages[0] << this->page_shift,
+			      mtd->writesize, td);
+		td->version[0] = buf[bbt_get_ver_offs(mtd, td)];
+		printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n",
+		       td->pages[0], td->version[0]);
 	}
 
 	/* Read the mirror version, if available */
 	if (md && (md->options & NAND_BBT_VERSION)) {
-		nand_read_raw (mtd, buf, md->pages[0] << this->page_shift, mtd->oobblock, mtd->oobsize);
-		md->version[0] = buf[mtd->oobblock + md->veroffs];
-		printk (KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", md->pages[0], md->version[0]);
+		scan_read_raw(mtd, buf, (loff_t)md->pages[0] << this->page_shift,
+			      mtd->writesize, td);
+		md->version[0] = buf[bbt_get_ver_offs(mtd, md)];
+		printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n",
+		       md->pages[0], md->version[0]);
 	}
-
 	return 1;
 }
 
+/*
+ * Scan a given block full
+ */
+static int scan_block_full(struct mtd_info *mtd, struct nand_bbt_descr *bd,
+			   loff_t offs, uint8_t *buf, size_t readlen,
+			   int scanlen, int len)
+{
+	int ret, j;
+
+	ret = scan_read_raw_oob(mtd, buf, offs, readlen);
+	if (ret)
+		return ret;
+
+	for (j = 0; j < len; j++, buf += scanlen) {
+		if (check_pattern(buf, scanlen, mtd->writesize, bd))
+			return 1;
+	}
+	return 0;
+}
+
+/*
+ * Scan a given block partially
+ */
+static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd,
+			   loff_t offs, uint8_t *buf, int len)
+{
+	struct mtd_oob_ops ops;
+	int j, ret;
+
+	ops.ooblen = mtd->oobsize;
+	ops.oobbuf = buf;
+	ops.ooboffs = 0;
+	ops.datbuf = NULL;
+	ops.mode = MTD_OOB_PLACE;
+
+	for (j = 0; j < len; j++) {
+		/*
+		 * Read the full oob until read_oob is fixed to
+		 * handle single byte reads for 16 bit
+		 * buswidth
+		 */
+		ret = mtd->read_oob(mtd, offs, &ops);
+		if (ret)
+			return ret;
+
+		if (check_short_pattern(buf, bd))
+			return 1;
+
+		offs += mtd->writesize;
+	}
+	return 0;
+}
+
 /**
  * create_bbt - [GENERIC] Create a bad block table by scanning the device
  * @mtd:	MTD device structure
@@ -253,55 +502,84 @@
  * Create a bad block table by scanning the device
  * for the given good/bad block identify pattern
  */
-static void create_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd, int chip)
+static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
+	struct nand_bbt_descr *bd, int chip)
 {
 	struct nand_chip *this = mtd->priv;
-	int i, j, numblocks, len, scanlen;
+	int i, numblocks, len, scanlen;
 	int startblock;
 	loff_t from;
-	size_t readlen, ooblen;
+	size_t readlen;
+
+	MTDDEBUG(MTD_DEBUG_LEVEL0, "Scanning device for bad blocks\n");
+
+//	printf("size of loff_t = %d \n", sizeof(from));
 
 	if (bd->options & NAND_BBT_SCANALLPAGES)
 		len = 1 << (this->bbt_erase_shift - this->page_shift);
-	else {
-		if (bd->options & NAND_BBT_SCAN2NDPAGE)
-			len = 2;
-		else
-			len = 1;
+	else if (bd->options & NAND_BBT_SCAN2NDPAGE)
+		len = 2;
+	else
+		len = 1;
+
+	if (!(bd->options & NAND_BBT_SCANEMPTY)) {
+		/* We need only read few bytes from the OOB area */
+		scanlen = 0;
+		readlen = bd->len;
+	} else {
+		/* Full page content should be read */
+		scanlen = mtd->writesize + mtd->oobsize;
+		readlen = len * mtd->writesize;
 	}
-	scanlen	= mtd->oobblock + mtd->oobsize;
-	readlen = len * mtd->oobblock;
-	ooblen = len * mtd->oobsize;
 
 	if (chip == -1) {
-		/* Note that numblocks is 2 * (real numblocks) here, see i+=2 below as it
-		 * makes shifting and masking less painful */
+		/* Note that numblocks is 2 * (real numblocks) here, see i+=2
+		 * below as it makes shifting and masking less painful */
 		numblocks = mtd->size >> (this->bbt_erase_shift - 1);
 		startblock = 0;
 		from = 0;
 	} else {
 		if (chip >= this->numchips) {
-			printk (KERN_WARNING "create_bbt(): chipnr (%d) > available chips (%d)\n",
-				chip + 1, this->numchips);
-			return;
+			printk(KERN_WARNING "create_bbt(): chipnr (%d) > available chips (%d)\n",
+			       chip + 1, this->numchips);
+			return -EINVAL;
 		}
 		numblocks = this->chipsize >> (this->bbt_erase_shift - 1);
 		startblock = chip * numblocks;
 		numblocks += startblock;
-		from = startblock << (this->bbt_erase_shift - 1);
+		from = (loff_t)startblock << (this->bbt_erase_shift - 1);
 	}
 
+	if (this->options & NAND_BBT_SCANLASTPAGE)
+		from += mtd->erasesize - (mtd->writesize * len);
+
 	for (i = startblock; i < numblocks;) {
-		nand_read_raw (mtd, buf, from, readlen, ooblen);
-		for (j = 0; j < len; j++) {
-			if (check_pattern (&buf[j * scanlen], scanlen, mtd->oobblock, bd)) {
-				this->bbt[i >> 3] |= 0x03 << (i & 0x6);
-				break;
-			}
+		int ret;
+
+		BUG_ON(bd->options & NAND_BBT_NO_OOB);
+
+		if (bd->options & NAND_BBT_SCANALLPAGES)
+			ret = scan_block_full(mtd, bd, from, buf, readlen,
+					      scanlen, len);
+		else
+			ret = scan_block_fast(mtd, bd, from, buf, len);
+
+		if (ret < 0)
+			return ret;
+
+//		printf("Printing BAD erase block by CJ!!!!!!\n");
+		if (ret) {
+			this->bbt[i >> 3] |= 0x03 << (i & 0x6);
+			MTDDEBUG(MTD_DEBUG_LEVEL0,
+				  "Bad eraseblock %d at 0x%012llx\n",
+				  i >> 1, (unsigned long long)from);
+			mtd->ecc_stats.badblocks++;
 		}
+
 		i += 2;
 		from += (1 << this->bbt_erase_shift);
 	}
+	return 0;
 }
 
 /**
@@ -316,22 +594,23 @@
  * block.
  * If the option NAND_BBT_PERCHIP is given, each chip is searched
  * for a bbt, which contains the bad block information of this chip.
- * This is neccecary to provide support for certain DOC devices.
+ * This is necessary to provide support for certain DOC devices.
  *
  * The bbt ident pattern resides in the oob area of the first page
  * in a block.
  */
-static int search_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td)
+static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td)
 {
 	struct nand_chip *this = mtd->priv;
 	int i, chips;
-	int bits, startblock, block, dir;
-	int scanlen = mtd->oobblock + mtd->oobsize;
+	int startblock, block, dir;
+	int scanlen = mtd->writesize + mtd->oobsize;
 	int bbtblocks;
+	int blocktopage = this->bbt_erase_shift - this->page_shift;
 
 	/* Search direction top -> down ? */
 	if (td->options & NAND_BBT_LASTBLOCK) {
-		startblock = (mtd->size >> this->bbt_erase_shift) -1;
+		startblock = (mtd->size >> this->bbt_erase_shift) - 1;
 		dir = -1;
 	} else {
 		startblock = 0;
@@ -348,22 +627,23 @@
 		bbtblocks = mtd->size >> this->bbt_erase_shift;
 	}
 
-	/* Number of bits for each erase block in the bbt */
-	bits = td->options & NAND_BBT_NRBITS_MSK;
-
 	for (i = 0; i < chips; i++) {
 		/* Reset version information */
 		td->version[i] = 0;
 		td->pages[i] = -1;
 		/* Scan the maximum number of blocks */
 		for (block = 0; block < td->maxblocks; block++) {
+
 			int actblock = startblock + dir * block;
+			loff_t offs = (loff_t)actblock << this->bbt_erase_shift;
+
 			/* Read first page */
-			nand_read_raw (mtd, buf, actblock << this->bbt_erase_shift, mtd->oobblock, mtd->oobsize);
-			if (!check_pattern(buf, scanlen, mtd->oobblock, td)) {
-				td->pages[i] = actblock << (this->bbt_erase_shift - this->page_shift);
+			scan_read_raw(mtd, buf, offs, mtd->writesize, td);
+			if (!check_pattern(buf, scanlen, mtd->writesize, td)) {
+				td->pages[i] = actblock << blocktopage;
 				if (td->options & NAND_BBT_VERSION) {
-					td->version[i] = buf[mtd->oobblock + td->veroffs];
+					offs = bbt_get_ver_offs(mtd, td);
+					td->version[i] = buf[offs];
 				}
 				break;
 			}
@@ -373,9 +653,11 @@
 	/* Check, if we found a bbt for each requested chip */
 	for (i = 0; i < chips; i++) {
 		if (td->pages[i] == -1)
-			printk (KERN_WARNING "Bad block table not found for chip %d\n", i);
+			printk(KERN_WARNING "Bad block table not found for chip %d\n", i);
 		else
-			printk (KERN_DEBUG "Bad block table found at page %d, version 0x%02X\n", td->pages[i], td->version[i]);
+			MTDDEBUG(MTD_DEBUG_LEVEL0, "Bad block table found " \
+				"at page %d, version 0x%02X\n", td->pages[i],
+				td->version[i]);
 	}
 	return 0;
 }
@@ -389,21 +671,19 @@
  *
  * Search and read the bad block table(s)
 */
-static int search_read_bbts (struct mtd_info *mtd, uint8_t *buf,
-	struct nand_bbt_descr *td, struct nand_bbt_descr *md)
+static int search_read_bbts(struct mtd_info *mtd, uint8_t * buf, struct nand_bbt_descr *td, struct nand_bbt_descr *md)
 {
 	/* Search the primary table */
-	search_bbt (mtd, buf, td);
+	search_bbt(mtd, buf, td);
 
 	/* Search the mirror table */
 	if (md)
-		search_bbt (mtd, buf, md);
+		search_bbt(mtd, buf, md);
 
 	/* Force result check */
 	return 1;
 }
 
-
 /**
  * write_bbt - [GENERIC] (Re)write the bad block table
  *
@@ -416,25 +696,31 @@
  * (Re)write the bad block table
  *
 */
-static int write_bbt (struct mtd_info *mtd, uint8_t *buf,
-	struct nand_bbt_descr *td, struct nand_bbt_descr *md, int chipsel)
+static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
+		     struct nand_bbt_descr *td, struct nand_bbt_descr *md,
+		     int chipsel)
 {
 	struct nand_chip *this = mtd->priv;
-	struct nand_oobinfo oobinfo;
 	struct erase_info einfo;
 	int i, j, res, chip = 0;
 	int bits, startblock, dir, page, offs, numblocks, sft, sftmsk;
-	int nrchips, bbtoffs, pageoffs;
+	int nrchips, bbtoffs, pageoffs, ooboffs;
 	uint8_t msk[4];
 	uint8_t rcode = td->reserved_block_code;
 	size_t retlen, len = 0;
 	loff_t to;
+	struct mtd_oob_ops ops;
+
+	ops.ooblen = mtd->oobsize;
+	ops.ooboffs = 0;
+	ops.datbuf = NULL;
+	ops.mode = MTD_OOB_PLACE;
 
 	if (!rcode)
 		rcode = 0xff;
 	/* Write bad block table per chip rather than per device ? */
 	if (td->options & NAND_BBT_PERCHIP) {
-		numblocks = (int) (this->chipsize >> this->bbt_erase_shift);
+		numblocks = (int)(this->chipsize >> this->bbt_erase_shift);
 		/* Full device write or specific chip ? */
 		if (chipsel == -1) {
 			nrchips = this->numchips;
@@ -443,7 +729,7 @@
 			chip = chipsel;
 		}
 	} else {
-		numblocks = (int) (mtd->size >> this->bbt_erase_shift);
+		numblocks = (int)(mtd->size >> this->bbt_erase_shift);
 		nrchips = 1;
 	}
 
@@ -472,27 +758,38 @@
 		for (i = 0; i < td->maxblocks; i++) {
 			int block = startblock + dir * i;
 			/* Check, if the block is bad */
-			switch ((this->bbt[block >> 2] >> (2 * (block & 0x03))) & 0x03) {
+			switch ((this->bbt[block >> 2] >>
+				 (2 * (block & 0x03))) & 0x03) {
 			case 0x01:
 			case 0x03:
 				continue;
 			}
-			page = block << (this->bbt_erase_shift - this->page_shift);
+			page = block <<
+				(this->bbt_erase_shift - this->page_shift);
 			/* Check, if the block is used by the mirror table */
 			if (!md || md->pages[chip] != page)
 				goto write;
 		}
-		printk (KERN_ERR "No space left to write bad block table\n");
+		printk(KERN_ERR "No space left to write bad block table\n");
 		return -ENOSPC;
-write:
+	write:
 
 		/* Set up shift count and masks for the flash table */
 		bits = td->options & NAND_BBT_NRBITS_MSK;
+		msk[2] = ~rcode;
 		switch (bits) {
-		case 1: sft = 3; sftmsk = 0x07; msk[0] = 0x00; msk[1] = 0x01; msk[2] = ~rcode; msk[3] = 0x01; break;
-		case 2: sft = 2; sftmsk = 0x06; msk[0] = 0x00; msk[1] = 0x01; msk[2] = ~rcode; msk[3] = 0x03; break;
-		case 4: sft = 1; sftmsk = 0x04; msk[0] = 0x00; msk[1] = 0x0C; msk[2] = ~rcode; msk[3] = 0x0f; break;
-		case 8: sft = 0; sftmsk = 0x00; msk[0] = 0x00; msk[1] = 0x0F; msk[2] = ~rcode; msk[3] = 0xff; break;
+		case 1: sft = 3; sftmsk = 0x07; msk[0] = 0x00; msk[1] = 0x01;
+			msk[3] = 0x01;
+			break;
+		case 2: sft = 2; sftmsk = 0x06; msk[0] = 0x00; msk[1] = 0x01;
+			msk[3] = 0x03;
+			break;
+		case 4: sft = 1; sftmsk = 0x04; msk[0] = 0x00; msk[1] = 0x0C;
+			msk[3] = 0x0f;
+			break;
+		case 8: sft = 0; sftmsk = 0x00; msk[0] = 0x00; msk[1] = 0x0F;
+			msk[3] = 0xff;
+			break;
 		default: return -EINVAL;
 		}
 
@@ -500,82 +797,108 @@
 
 		to = ((loff_t) page) << this->page_shift;
 
-		memcpy (&oobinfo, this->autooob, sizeof(oobinfo));
-		oobinfo.useecc = MTD_NANDECC_PLACEONLY;
-
 		/* Must we save the block contents ? */
 		if (td->options & NAND_BBT_SAVECONTENT) {
 			/* Make it block aligned */
 			to &= ~((loff_t) ((1 << this->bbt_erase_shift) - 1));
 			len = 1 << this->bbt_erase_shift;
-			res = mtd->read_ecc (mtd, to, len, &retlen, buf, &buf[len], &oobinfo);
+			res = mtd->read(mtd, to, len, &retlen, buf);
 			if (res < 0) {
 				if (retlen != len) {
-					printk (KERN_INFO "nand_bbt: Error reading block for writing the bad block table\n");
+					printk(KERN_INFO "nand_bbt: Error "
+					       "reading block for writing "
+					       "the bad block table\n");
 					return res;
 				}
-				printk (KERN_WARNING "nand_bbt: ECC error while reading block for writing bad block table\n");
+				printk(KERN_WARNING "nand_bbt: ECC error "
+				       "while reading block for writing "
+				       "bad block table\n");
 			}
+			/* Read oob data */
+			ops.ooblen = (len >> this->page_shift) * mtd->oobsize;
+			ops.oobbuf = &buf[len];
+			res = mtd->read_oob(mtd, to + mtd->writesize, &ops);
+			if (res < 0 || ops.oobretlen != ops.ooblen)
+				goto outerr;
+
 			/* Calc the byte offset in the buffer */
 			pageoffs = page - (int)(to >> this->page_shift);
 			offs = pageoffs << this->page_shift;
 			/* Preset the bbt area with 0xff */
-			memset (&buf[offs], 0xff, (size_t)(numblocks >> sft));
-			/* Preset the bbt's oob area with 0xff */
-			memset (&buf[len + pageoffs * mtd->oobsize], 0xff,
-				((len >> this->page_shift) - pageoffs) * mtd->oobsize);
-			if (td->options & NAND_BBT_VERSION) {
-				buf[len + (pageoffs * mtd->oobsize) + td->veroffs] = td->version[chip];
-			}
+			memset(&buf[offs], 0xff, (size_t) (numblocks >> sft));
+			ooboffs = len + (pageoffs * mtd->oobsize);
+
+		} else if (td->options & NAND_BBT_NO_OOB) {
+			ooboffs = 0;
+			offs = td->len;
+			/* the version byte */
+			if (td->options & NAND_BBT_VERSION)
+				offs++;
+			/* Calc length */
+			len = (size_t) (numblocks >> sft);
+			len += offs;
+			/* Make it page aligned ! */
+			len = ALIGN(len, mtd->writesize);
+			/* Preset the buffer with 0xff */
+			memset(buf, 0xff, len);
+			/* Pattern is located at the begin of first page */
+			memcpy(buf, td->pattern, td->len);
 		} else {
 			/* Calc length */
 			len = (size_t) (numblocks >> sft);
 			/* Make it page aligned ! */
-			len = (len + (mtd->oobblock-1)) & ~(mtd->oobblock-1);
+			len = ALIGN(len, mtd->writesize);
 			/* Preset the buffer with 0xff */
-			memset (buf, 0xff, len + (len >> this->page_shift) * mtd->oobsize);
+			memset(buf, 0xff, len +
+			       (len >> this->page_shift)* mtd->oobsize);
 			offs = 0;
+			ooboffs = len;
 			/* Pattern is located in oob area of first page */
-			memcpy (&buf[len + td->offs], td->pattern, td->len);
-			if (td->options & NAND_BBT_VERSION) {
-				buf[len + td->veroffs] = td->version[chip];
-			}
+			memcpy(&buf[ooboffs + td->offs], td->pattern, td->len);
 		}
 
+		if (td->options & NAND_BBT_VERSION)
+			buf[ooboffs + td->veroffs] = td->version[chip];
+
 		/* walk through the memory table */
-		for (i = 0; i < numblocks; ) {
+		for (i = 0; i < numblocks;) {
 			uint8_t dat;
 			dat = this->bbt[bbtoffs + (i >> 2)];
-			for (j = 0; j < 4; j++ , i++) {
+			for (j = 0; j < 4; j++, i++) {
 				int sftcnt = (i << (3 - sft)) & sftmsk;
 				/* Do not store the reserved bbt blocks ! */
-				buf[offs + (i >> sft)] &= ~(msk[dat & 0x03] << sftcnt);
+				buf[offs + (i >> sft)] &=
+					~(msk[dat & 0x03] << sftcnt);
 				dat >>= 2;
 			}
 		}
 
-		memset (&einfo, 0, sizeof (einfo));
+		memset(&einfo, 0, sizeof(einfo));
 		einfo.mtd = mtd;
-		einfo.addr = (unsigned long) to;
+		einfo.addr = to;
 		einfo.len = 1 << this->bbt_erase_shift;
-		res = nand_erase_nand (mtd, &einfo, 1);
-		if (res < 0) {
-			printk (KERN_WARNING "nand_bbt: Error during block erase: %d\n", res);
-			return res;
-		}
+		res = nand_erase_nand(mtd, &einfo, 1);
+		if (res < 0)
+			goto outerr;
 
-		res = mtd->write_ecc (mtd, to, len, &retlen, buf, &buf[len], &oobinfo);
-		if (res < 0) {
-			printk (KERN_WARNING "nand_bbt: Error while writing bad block table %d\n", res);
-			return res;
-		}
-		printk (KERN_DEBUG "Bad block table written to 0x%08x, version 0x%02X\n",
-			(unsigned int) to, td->version[chip]);
+		res = scan_write_bbt(mtd, to, len, buf,
+				td->options & NAND_BBT_NO_OOB ? NULL :
+				&buf[len]);
+		if (res < 0)
+			goto outerr;
+
+		printk(KERN_DEBUG "Bad block table written to 0x%012llx, version "
+		       "0x%02X\n", (unsigned long long)to, td->version[chip]);
 
 		/* Mark it as used */
 		td->pages[chip] = page;
 	}
 	return 0;
+
+ outerr:
+	printk(KERN_WARNING
+	       "nand_bbt: Error while writing bad block table %d\n", res);
+	return res;
 }
 
 /**
@@ -586,29 +909,27 @@
  * The function creates a memory based bbt by scanning the device
  * for manufacturer / software marked good / bad blocks
 */
-static int nand_memory_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd)
+static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 {
 	struct nand_chip *this = mtd->priv;
 
-	/* Ensure that we only scan for the pattern and nothing else */
-	bd->options = 0;
-	create_bbt (mtd, this->data_buf, bd, -1);
-	return 0;
+	bd->options &= ~NAND_BBT_SCANEMPTY;
+	return create_bbt(mtd, this->buffers->databuf, bd, -1);
 }
 
 /**
- * check_create - [GENERIC] create and write bbt(s) if neccecary
+ * check_create - [GENERIC] create and write bbt(s) if necessary
  * @mtd:	MTD device structure
  * @buf:	temporary buffer
  * @bd:		descriptor for the good/bad block search pattern
  *
  * The function checks the results of the previous call to read_bbt
- * and creates / updates the bbt(s) if neccecary
- * Creation is neccecary if no bbt was found for the chip/device
- * Update is neccecary if one of the tables is missing or the
+ * and creates / updates the bbt(s) if necessary
+ * Creation is necessary if no bbt was found for the chip/device
+ * Update is necessary if one of the tables is missing or the
  * version nr. of one table is less than the other
 */
-static int check_create (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd)
+static int check_create(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd)
 {
 	int i, chips, writeops, chipsel, res;
 	struct nand_chip *this = mtd->priv;
@@ -628,7 +949,7 @@
 		rd2 = NULL;
 		/* Per chip or per device ? */
 		chipsel = (td->options & NAND_BBT_PERCHIP) ? i : -1;
-		/* Mirrored table avilable ? */
+		/* Mirrored table available ? */
 		if (md) {
 			if (td->pages[i] == -1 && md->pages[i] == -1) {
 				writeops = 0x03;
@@ -676,35 +997,36 @@
 			rd = td;
 			goto writecheck;
 		}
-create:
+	create:
 		/* Create the bad block table by scanning the device ? */
 		if (!(td->options & NAND_BBT_CREATE))
 			continue;
 
 		/* Create the table in memory by scanning the chip(s) */
-		create_bbt (mtd, buf, bd, chipsel);
+		if (!(this->options & NAND_CREATE_EMPTY_BBT))
+			create_bbt(mtd, buf, bd, chipsel);
 
 		td->version[i] = 1;
 		if (md)
 			md->version[i] = 1;
-writecheck:
+	writecheck:
 		/* read back first ? */
 		if (rd)
-			read_abs_bbt (mtd, buf, rd, chipsel);
+			read_abs_bbt(mtd, buf, rd, chipsel);
 		/* If they weren't versioned, read both. */
 		if (rd2)
-			read_abs_bbt (mtd, buf, rd2, chipsel);
+			read_abs_bbt(mtd, buf, rd2, chipsel);
 
 		/* Write the bad block table to the device ? */
 		if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) {
-			res = write_bbt (mtd, buf, td, md, chipsel);
+			res = write_bbt(mtd, buf, td, md, chipsel);
 			if (res < 0)
 				return res;
 		}
 
 		/* Write the mirror bad block table to the device ? */
 		if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) {
-			res = write_bbt (mtd, buf, md, td, chipsel);
+			res = write_bbt(mtd, buf, md, td, chipsel);
 			if (res < 0)
 				return res;
 		}
@@ -721,7 +1043,7 @@
  * accidental erasures / writes. The regions are identified by
  * the mark 0x02.
 */
-static void mark_bbt_region (struct mtd_info *mtd, struct nand_bbt_descr *td)
+static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td)
 {
 	struct nand_chip *this = mtd->priv;
 	int i, j, chips, block, nrblocks, update;
@@ -739,14 +1061,15 @@
 	for (i = 0; i < chips; i++) {
 		if ((td->options & NAND_BBT_ABSPAGE) ||
 		    !(td->options & NAND_BBT_WRITE)) {
-		    	if (td->pages[i] == -1) continue;
+			if (td->pages[i] == -1)
+				continue;
 			block = td->pages[i] >> (this->bbt_erase_shift - this->page_shift);
 			block <<= 1;
 			oldval = this->bbt[(block >> 3)];
 			newval = oldval | (0x2 << (block & 0x06));
 			this->bbt[(block >> 3)] = newval;
 			if ((oldval != newval) && td->reserved_block_code)
-				nand_update_bbt(mtd, block << (this->bbt_erase_shift - 1));
+				nand_update_bbt(mtd, (loff_t)block << (this->bbt_erase_shift - 1));
 			continue;
 		}
 		update = 0;
@@ -759,18 +1082,67 @@
 			oldval = this->bbt[(block >> 3)];
 			newval = oldval | (0x2 << (block & 0x06));
 			this->bbt[(block >> 3)] = newval;
-			if (oldval != newval) update = 1;
+			if (oldval != newval)
+				update = 1;
 			block += 2;
 		}
 		/* If we want reserved blocks to be recorded to flash, and some
 		   new ones have been marked, then we need to update the stored
 		   bbts.  This should only happen once. */
 		if (update && td->reserved_block_code)
-			nand_update_bbt(mtd, (block - 2) << (this->bbt_erase_shift - 1));
+			nand_update_bbt(mtd, (loff_t)(block - 2) << (this->bbt_erase_shift - 1));
 	}
 }
 
 /**
+ * verify_bbt_descr - verify the bad block description
+ * @mtd:	MTD device structure
+ * @bd:		the table to verify
+ *
+ * This functions performs a few sanity checks on the bad block description
+ * table.
+ */
+static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd)
+{
+	struct nand_chip *this = mtd->priv;
+	u32 pattern_len;
+	u32 bits;
+	u32 table_size;
+
+	if (!bd)
+		return;
+
+	pattern_len = bd->len;
+	bits = bd->options & NAND_BBT_NRBITS_MSK;
+
+	BUG_ON((this->options & NAND_USE_FLASH_BBT_NO_OOB) &&
+			!(this->options & NAND_USE_FLASH_BBT));
+	BUG_ON(!bits);
+
+	if (bd->options & NAND_BBT_VERSION)
+		pattern_len++;
+
+	if (bd->options & NAND_BBT_NO_OOB) {
+		BUG_ON(!(this->options & NAND_USE_FLASH_BBT));
+		BUG_ON(!(this->options & NAND_USE_FLASH_BBT_NO_OOB));
+		BUG_ON(bd->offs);
+		if (bd->options & NAND_BBT_VERSION)
+			BUG_ON(bd->veroffs != bd->len);
+		BUG_ON(bd->options & NAND_BBT_SAVECONTENT);
+	}
+
+	if (bd->options & NAND_BBT_PERCHIP)
+		table_size = this->chipsize >> this->bbt_erase_shift;
+	else
+		table_size = mtd->size >> this->bbt_erase_shift;
+	table_size >>= 3;
+	table_size *= bits;
+	if (bd->options & NAND_BBT_NO_OOB)
+		table_size += pattern_len;
+	BUG_ON(table_size > (1 << this->bbt_erase_shift));
+}
+
+/**
  * nand_scan_bbt - [NAND Interface] scan, find, read and maybe create bad block table(s)
  * @mtd:	MTD device structure
  * @bd:		descriptor for the good/bad block search pattern
@@ -784,7 +1156,7 @@
  * by calling the nand_free_bbt function.
  *
 */
-int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd)
+int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 {
 	struct nand_chip *this = mtd->priv;
 	int len, res = 0;
@@ -793,53 +1165,58 @@
 	struct nand_bbt_descr *md = this->bbt_md;
 
 	len = mtd->size >> (this->bbt_erase_shift + 2);
-	/* Allocate memory (2bit per block) */
-	this->bbt = kmalloc (len, GFP_KERNEL);
+	/* Allocate memory (2bit per block) and clear the memory bad block table */
+	this->bbt = kzalloc(len, GFP_KERNEL);
 	if (!this->bbt) {
-		printk (KERN_ERR "nand_scan_bbt: Out of memory\n");
+		printk(KERN_ERR "nand_scan_bbt: Out of memory\n");
 		return -ENOMEM;
 	}
-	/* Clear the memory bad block table */
-	memset (this->bbt, 0x00, len);
 
 	/* If no primary table decriptor is given, scan the device
 	 * to build a memory based bad block table
 	 */
-	if (!td)
-		return nand_memory_bbt(mtd, bd);
+	if (!td) {
+		if ((res = nand_memory_bbt(mtd, bd))) {
+			printk(KERN_ERR "nand_bbt: Can't scan flash and build the RAM-based BBT\n");
+			kfree(this->bbt);
+			this->bbt = NULL;
+		}
+		return res;
+	}
+	verify_bbt_descr(mtd, td);
+	verify_bbt_descr(mtd, md);
 
 	/* Allocate a temporary buffer for one eraseblock incl. oob */
 	len = (1 << this->bbt_erase_shift);
 	len += (len >> this->page_shift) * mtd->oobsize;
-	buf = kmalloc (len, GFP_KERNEL);
+	buf = vmalloc(len);
 	if (!buf) {
-		printk (KERN_ERR "nand_bbt: Out of memory\n");
-		kfree (this->bbt);
+		printk(KERN_ERR "nand_bbt: Out of memory\n");
+		kfree(this->bbt);
 		this->bbt = NULL;
 		return -ENOMEM;
 	}
 
 	/* Is the bbt at a given page ? */
 	if (td->options & NAND_BBT_ABSPAGE) {
-		res = read_abs_bbts (mtd, buf, td, md);
+		res = read_abs_bbts(mtd, buf, td, md);
 	} else {
 		/* Search the bad block table using a pattern in oob */
-		res = search_read_bbts (mtd, buf, td, md);
+		res = search_read_bbts(mtd, buf, td, md);
 	}
 
 	if (res)
-		res = check_create (mtd, buf, bd);
+		res = check_create(mtd, buf, bd);
 
 	/* Prevent the bbt regions from erasing / writing */
-	mark_bbt_region (mtd, td);
+	mark_bbt_region(mtd, td);
 	if (md)
-		mark_bbt_region (mtd, md);
+		mark_bbt_region(mtd, md);
 
-	kfree (buf);
+	vfree(buf);
 	return res;
 }
 
-
 /**
  * nand_update_bbt - [NAND Interface] update bad block table(s)
  * @mtd:	MTD device structure
@@ -847,7 +1224,7 @@
  *
  * The function updates the bad block table(s)
 */
-int nand_update_bbt (struct mtd_info *mtd, loff_t offs)
+int nand_update_bbt(struct mtd_info *mtd, loff_t offs)
 {
 	struct nand_chip *this = mtd->priv;
 	int len, res = 0, writeops = 0;
@@ -859,13 +1236,12 @@
 	if (!this->bbt || !td)
 		return -EINVAL;
 
-	len = mtd->size >> (this->bbt_erase_shift + 2);
 	/* Allocate a temporary buffer for one eraseblock incl. oob */
 	len = (1 << this->bbt_erase_shift);
 	len += (len >> this->page_shift) * mtd->oobsize;
-	buf = kmalloc (len, GFP_KERNEL);
+	buf = kmalloc(len, GFP_KERNEL);
 	if (!buf) {
-		printk (KERN_ERR "nand_update_bbt: Out of memory\n");
+		printk(KERN_ERR "nand_update_bbt: Out of memory\n");
 		return -ENOMEM;
 	}
 
@@ -873,7 +1249,7 @@
 
 	/* Do we have a bbt per chip ? */
 	if (td->options & NAND_BBT_PERCHIP) {
-		chip = (int) (offs >> this->chip_shift);
+		chip = (int)(offs >> this->chip_shift);
 		chipsel = chip;
 	} else {
 		chip = 0;
@@ -886,55 +1262,24 @@
 
 	/* Write the bad block table to the device ? */
 	if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) {
-		res = write_bbt (mtd, buf, td, md, chipsel);
+		res = write_bbt(mtd, buf, td, md, chipsel);
 		if (res < 0)
 			goto out;
 	}
 	/* Write the mirror bad block table to the device ? */
 	if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) {
-		res = write_bbt (mtd, buf, md, td, chipsel);
+		res = write_bbt(mtd, buf, md, td, chipsel);
 	}
 
-out:
-	kfree (buf);
+ out:
+	kfree(buf);
 	return res;
 }
 
 /* Define some generic bad / good block scan pattern which are used
- * while scanning a device for factory marked good / bad blocks
- *
- * The memory based patterns just
- */
+ * while scanning a device for factory marked good / bad blocks. */
 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
 
-static struct nand_bbt_descr smallpage_memorybased = {
-	.options = 0,
-	.offs = 5,
-	.len = 1,
-	.pattern = scan_ff_pattern
-};
-
-static struct nand_bbt_descr largepage_memorybased = {
-	.options = 0,
-	.offs = 0,
-	.len = 2,
-	.pattern = scan_ff_pattern
-};
-
-static struct nand_bbt_descr smallpage_flashbased = {
-	.options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
-	.offs = 5,
-	.len = 1,
-	.pattern = scan_ff_pattern
-};
-
-static struct nand_bbt_descr largepage_flashbased = {
-	.options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
-	.offs = 0,
-	.len = 2,
-	.pattern = scan_ff_pattern
-};
-
 static uint8_t scan_agand_pattern[] = { 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7 };
 
 static struct nand_bbt_descr agand_flashbased = {
@@ -969,6 +1314,59 @@
 	.pattern = mirror_pattern
 };
 
+static struct nand_bbt_descr bbt_main_no_bbt_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP
+		| NAND_BBT_NO_OOB,
+	.len = 4,
+	.veroffs = 4,
+	.maxblocks = 4,
+	.pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_no_bbt_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+		| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP
+		| NAND_BBT_NO_OOB,
+	.len = 4,
+	.veroffs = 4,
+	.maxblocks = 4,
+	.pattern = mirror_pattern
+};
+
+#define BBT_SCAN_OPTIONS (NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE | \
+		NAND_BBT_SCANBYTE1AND6)
+/**
+ * nand_create_default_bbt_descr - [Internal] Creates a BBT descriptor structure
+ * @this:	NAND chip to create descriptor for
+ *
+ * This function allocates and initializes a nand_bbt_descr for BBM detection
+ * based on the properties of "this". The new descriptor is stored in
+ * this->badblock_pattern. Thus, this->badblock_pattern should be NULL when
+ * passed to this function.
+ *
+ */
+static int nand_create_default_bbt_descr(struct nand_chip *this)
+{
+	struct nand_bbt_descr *bd;
+	if (this->badblock_pattern) {
+		printk(KERN_WARNING "BBT descr already allocated; not replacing.\n");
+		return -EINVAL;
+	}
+	bd = kzalloc(sizeof(*bd), GFP_KERNEL);
+	if (!bd) {
+		printk(KERN_ERR "nand_create_default_bbt_descr: Out of memory\n");
+		return -ENOMEM;
+	}
+	bd->options = this->options & BBT_SCAN_OPTIONS;
+	bd->offs = this->badblockpos;
+	bd->len = (this->options & NAND_BUSWIDTH_16) ? 2 : 1;
+	bd->pattern = scan_ff_pattern;
+	bd->options |= NAND_BBT_DYNAMICSTRUCT;
+	this->badblock_pattern = bd;
+	return 0;
+}
+
 /**
  * nand_default_bbt - [NAND Interface] Select a default bad block table for the device
  * @mtd:	MTD device structure
@@ -977,7 +1375,7 @@
  * support for the device and calls the nand_scan_bbt function
  *
 */
-int nand_default_bbt (struct mtd_info *mtd)
+int nand_default_bbt(struct mtd_info *mtd)
 {
 	struct nand_chip *this = mtd->priv;
 
@@ -987,7 +1385,7 @@
 	 * of the good / bad information, so we _must_ store
 	 * this information in a good / bad table during
 	 * startup
-	*/
+	 */
 	if (this->options & NAND_IS_AND) {
 		/* Use the default pattern descriptors */
 		if (!this->bbt_td) {
@@ -995,30 +1393,30 @@
 			this->bbt_md = &bbt_mirror_descr;
 		}
 		this->options |= NAND_USE_FLASH_BBT;
-		return nand_scan_bbt (mtd, &agand_flashbased);
+		return nand_scan_bbt(mtd, &agand_flashbased);
 	}
 
-
 	/* Is a flash based bad block table requested ? */
 	if (this->options & NAND_USE_FLASH_BBT) {
 		/* Use the default pattern descriptors */
 		if (!this->bbt_td) {
-			this->bbt_td = &bbt_main_descr;
-			this->bbt_md = &bbt_mirror_descr;
-		}
-		if (!this->badblock_pattern) {
-			this->badblock_pattern = (mtd->oobblock > 512) ?
-				&largepage_flashbased : &smallpage_flashbased;
+			if (this->options & NAND_USE_FLASH_BBT_NO_OOB) {
+				this->bbt_td = &bbt_main_no_bbt_descr;
+				this->bbt_md = &bbt_mirror_no_bbt_descr;
+			} else {
+				this->bbt_td = &bbt_main_descr;
+				this->bbt_md = &bbt_mirror_descr;
+			}
 		}
 	} else {
 		this->bbt_td = NULL;
 		this->bbt_md = NULL;
-		if (!this->badblock_pattern) {
-			this->badblock_pattern = (mtd->oobblock > 512) ?
-				&largepage_memorybased : &smallpage_memorybased;
-		}
 	}
-	return nand_scan_bbt (mtd, this->badblock_pattern);
+
+	if (!this->badblock_pattern)
+		nand_create_default_bbt_descr(this);
+
+	return nand_scan_bbt(mtd, this->badblock_pattern);
 }
 
 /**
@@ -1027,26 +1425,27 @@
  * @offs:	offset in the device
  * @allowbbt:	allow access to bad block table region
  *
- */
-int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt)
+*/
+int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
 {
 	struct nand_chip *this = mtd->priv;
 	int block;
-	uint8_t	res;
+	uint8_t res;
 
 	/* Get block number * 2 */
-	block = (int) (offs >> (this->bbt_erase_shift - 1));
+	block = (int)(offs >> (this->bbt_erase_shift - 1));
 	res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03;
 
-	DEBUG (MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: (block %d) 0x%02x\n",
-		(unsigned int)offs, res, block >> 1);
+	MTDDEBUG(MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: (block %d) 0x%02x\n",
+	      (unsigned int)offs, block >> 1, res);
 
 	switch ((int)res) {
-	case 0x00:	return 0;
-	case 0x01:	return 1;
-	case 0x02:	return allowbbt ? 0 : 1;
+	case 0x00:
+		return 0;
+	case 0x01:
+		return 1;
+	case 0x02:
+		return allowbbt ? 0 : 1;
 	}
 	return 1;
 }
-
-#endif

drivers/nand/nand_bch.c

diff --git a/drivers/nand/nand_bch.c b/drivers/nand/nand_bch.c
new file mode 100644
index 0000000..7835fce
--- /dev/null
+++ b/drivers/nand/nand_bch.c
@@ -0,0 +1,236 @@
+/*
+ * This file provides ECC correction for more than 1 bit per block of data,
+ * using binary BCH codes. It relies on the generic BCH library lib/bch.c.
+ *
+ * Copyright © 2011 Ivan Djelic <ivan.djelic@parrot.com>
+ *
+ * This file is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 or (at your option) any
+ * later version.
+ *
+ * This file is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this file; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#include <common.h>
+/*#include <asm/io.h>*/
+#include <linux/types.h>
+
+#include <linux/bitops.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_bch.h>
+#include <linux/bch.h>
+#include <malloc.h>
+
+/**
+ * struct nand_bch_control - private NAND BCH control structure
+ * @bch:       BCH control structure
+ * @ecclayout: private ecc layout for this BCH configuration
+ * @errloc:    error location array
+ * @eccmask:   XOR ecc mask, allows erased pages to be decoded as valid
+ */
+struct nand_bch_control {
+	struct bch_control   *bch;
+	struct nand_ecclayout ecclayout;
+	unsigned int         *errloc;
+	unsigned char        *eccmask;
+};
+
+/**
+ * nand_bch_calculate_ecc - [NAND Interface] Calculate ECC for data block
+ * @mtd:	MTD block structure
+ * @buf:	input buffer with raw data
+ * @code:	output buffer with ECC
+ */
+int nand_bch_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf,
+			   unsigned char *code)
+{
+	const struct nand_chip *chip = mtd->priv;
+	struct nand_bch_control *nbc = chip->ecc.priv;
+	unsigned int i;
+
+	memset(code, 0, chip->ecc.bytes);
+	encode_bch(nbc->bch, buf, chip->ecc.size, code);
+
+	/* apply mask so that an erased page is a valid codeword */
+	for (i = 0; i < chip->ecc.bytes; i++)
+		code[i] ^= nbc->eccmask[i];
+
+	return 0;
+}
+
+/**
+ * nand_bch_correct_data - [NAND Interface] Detect and correct bit error(s)
+ * @mtd:	MTD block structure
+ * @buf:	raw data read from the chip
+ * @read_ecc:	ECC from the chip
+ * @calc_ecc:	the ECC calculated from raw data
+ *
+ * Detect and correct bit errors for a data byte block
+ */
+int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
+			  unsigned char *read_ecc, unsigned char *calc_ecc)
+{
+	const struct nand_chip *chip = mtd->priv;
+	struct nand_bch_control *nbc = chip->ecc.priv;
+	unsigned int *errloc = nbc->errloc;
+	int i, count;
+
+	count = decode_bch(nbc->bch, NULL, chip->ecc.size, read_ecc, calc_ecc,
+			   NULL, errloc);
+	if (count > 0) {
+		for (i = 0; i < count; i++) {
+			if (errloc[i] < (chip->ecc.size*8))
+				/* error is located in data, correct it */
+				buf[errloc[i] >> 3] ^= (1 << (errloc[i] & 7));
+			/* else error in ecc, no action needed */
+
+			MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: corrected bitflip %u\n",
+			      __func__, errloc[i]);
+		}
+	} else if (count < 0) {
+		printk(KERN_ERR "ecc unrecoverable error\n");
+		count = -1;
+	}
+	return count;
+}
+
+/**
+ * nand_bch_init - [NAND Interface] Initialize NAND BCH error correction
+ * @mtd:	MTD block structure
+ * @eccsize:	ecc block size in bytes
+ * @eccbytes:	ecc length in bytes
+ * @ecclayout:	output default layout
+ *
+ * Returns:
+ *  a pointer to a new NAND BCH control structure, or NULL upon failure
+ *
+ * Initialize NAND BCH error correction. Parameters @eccsize and @eccbytes
+ * are used to compute BCH parameters m (Galois field order) and t (error
+ * correction capability). @eccbytes should be equal to the number of bytes
+ * required to store m*t bits, where m is such that 2^m-1 > @eccsize*8.
+ *
+ * Example: to configure 4 bit correction per 512 bytes, you should pass
+ * @eccsize = 512  (thus, m=13 is the smallest integer such that 2^m-1 > 512*8)
+ * @eccbytes = 7   (7 bytes are required to store m*t = 13*4 = 52 bits)
+ */
+struct nand_bch_control *
+nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
+	      struct nand_ecclayout **ecclayout)
+{
+	unsigned int m, t, eccsteps, i;
+	struct nand_ecclayout *layout;
+	struct nand_bch_control *nbc = NULL;
+	unsigned char *erased_page;
+
+	if (!eccsize || !eccbytes) {
+		printk(KERN_WARNING "ecc parameters not supplied\n");
+		goto fail;
+	}
+
+	m = fls(1+8*eccsize);
+	t = (eccbytes*8)/m;
+
+	nbc = kzalloc(sizeof(*nbc), GFP_KERNEL);
+	if (!nbc)
+		goto fail;
+
+	nbc->bch = init_bch(m, t, 0);
+	if (!nbc->bch)
+		goto fail;
+
+	/* verify that eccbytes has the expected value */
+	if (nbc->bch->ecc_bytes != eccbytes) {
+		printk(KERN_WARNING "invalid eccbytes %u, should be %u\n",
+		       eccbytes, nbc->bch->ecc_bytes);
+		goto fail;
+	}
+
+	eccsteps = mtd->writesize/eccsize;
+
+	/* if no ecc placement scheme was provided, build one */
+	if (!*ecclayout) {
+
+		/* handle large page devices only */
+		if (mtd->oobsize < 64) {
+			printk(KERN_WARNING "must provide an oob scheme for "
+			       "oobsize %d\n", mtd->oobsize);
+			goto fail;
+		}
+
+		layout = &nbc->ecclayout;
+		layout->eccbytes = eccsteps*eccbytes;
+
+		/* reserve 2 bytes for bad block marker */
+		if (layout->eccbytes+2 > mtd->oobsize) {
+			printk(KERN_WARNING "no suitable oob scheme available "
+			       "for oobsize %d eccbytes %u\n", mtd->oobsize,
+			       eccbytes);
+			goto fail;
+		}
+		/* put ecc bytes at oob tail */
+		for (i = 0; i < layout->eccbytes; i++)
+			layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i;
+
+		layout->oobfree[0].offset = 2;
+		layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes;
+
+		*ecclayout = layout;
+	}
+
+	/* sanity checks */
+	if (8*(eccsize+eccbytes) >= (1 << m)) {
+		printk(KERN_WARNING "eccsize %u is too large\n", eccsize);
+		goto fail;
+	}
+	if ((*ecclayout)->eccbytes != (eccsteps*eccbytes)) {
+		printk(KERN_WARNING "invalid ecc layout\n");
+		goto fail;
+	}
+
+	nbc->eccmask = kmalloc(eccbytes, GFP_KERNEL);
+	nbc->errloc = kmalloc(t*sizeof(*nbc->errloc), GFP_KERNEL);
+	if (!nbc->eccmask || !nbc->errloc)
+		goto fail;
+	/*
+	 * compute and store the inverted ecc of an erased ecc block
+	 */
+	erased_page = kmalloc(eccsize, GFP_KERNEL);
+	if (!erased_page)
+		goto fail;
+
+	memset(erased_page, 0xff, eccsize);
+	memset(nbc->eccmask, 0, eccbytes);
+	encode_bch(nbc->bch, erased_page, eccsize, nbc->eccmask);
+	kfree(erased_page);
+
+	for (i = 0; i < eccbytes; i++)
+		nbc->eccmask[i] ^= 0xff;
+
+	return nbc;
+fail:
+	nand_bch_free(nbc);
+	return NULL;
+}
+
+/**
+ * nand_bch_free - [NAND Interface] Release NAND BCH ECC resources
+ * @nbc:	NAND BCH control structure
+ */
+void nand_bch_free(struct nand_bch_control *nbc)
+{
+	if (nbc) {
+		free_bch(nbc->bch);
+		kfree(nbc->errloc);
+		kfree(nbc->eccmask);
+		kfree(nbc);
+	}
+}

drivers/nand/nand_ecc.c

diff --git a/drivers/nand/nand_ecc.c b/drivers/nand/nand_ecc.c
index f33be96..81f0e08 100644
--- a/drivers/nand/nand_ecc.c
+++ b/drivers/nand/nand_ecc.c
@@ -7,7 +7,7 @@
  * Copyright (C) 2000-2004 Steven J. Hill (sjhill@realitydiluted.com)
  *                         Toshiba America Electronics Components, Inc.
  *
- * $Id: nand_ecc.c,v 1.14 2004/06/16 15:34:37 gleixner Exp $
+ * Copyright (C) 2006 Thomas Gleixner <tglx@linutronix.de>
  *
  * This file is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -37,9 +37,20 @@
 
 #include <common.h>
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+#include <asm/errno.h>
+#include <linux/mtd/mtd.h>
 
-#include<linux/mtd/mtd.h>
+/* The PPC4xx NDFC uses Smart Media (SMC) bytes order */
+#ifdef CONFIG_NAND_NDFC
+#define CONFIG_MTD_NAND_ECC_SMC
+#endif
+
+/*
+ * NAND-SPL has no sofware ECC for now, so don't include nand_calculate_ecc(),
+ * only nand_correct_data() is needed
+ */
+
+#if !defined(CONFIG_NAND_SPL) || defined(CONFIG_SPL_NAND_SOFTECC)
 /*
  * Pre-calculated 256-way 1 byte column parity
  */
@@ -62,90 +73,75 @@
 	0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
 };
 
-
 /**
- * nand_trans_result - [GENERIC] create non-inverted ECC
- * @reg2:	line parity reg 2
- * @reg3:	line parity reg 3
- * @ecc_code:	ecc
- *
- * Creates non-inverted ECC code from line parity
- */
-static void nand_trans_result(u_char reg2, u_char reg3,
-	u_char *ecc_code)
-{
-	u_char a, b, i, tmp1, tmp2;
-
-	/* Initialize variables */
-	a = b = 0x80;
-	tmp1 = tmp2 = 0;
-
-	/* Calculate first ECC byte */
-	for (i = 0; i < 4; i++) {
-		if (reg3 & a)		/* LP15,13,11,9 --> ecc_code[0] */
-			tmp1 |= b;
-		b >>= 1;
-		if (reg2 & a)		/* LP14,12,10,8 --> ecc_code[0] */
-			tmp1 |= b;
-		b >>= 1;
-		a >>= 1;
-	}
-
-	/* Calculate second ECC byte */
-	b = 0x80;
-	for (i = 0; i < 4; i++) {
-		if (reg3 & a)		/* LP7,5,3,1 --> ecc_code[1] */
-			tmp2 |= b;
-		b >>= 1;
-		if (reg2 & a)		/* LP6,4,2,0 --> ecc_code[1] */
-			tmp2 |= b;
-		b >>= 1;
-		a >>= 1;
-	}
-
-	/* Store two of the ECC bytes */
-	ecc_code[0] = tmp1;
-	ecc_code[1] = tmp2;
-}
-
-/**
- * nand_calculate_ecc - [NAND Interface] Calculate 3 byte ECC code for 256 byte block
+ * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256-byte block
  * @mtd:	MTD block structure
  * @dat:	raw data
  * @ecc_code:	buffer for ECC
  */
-int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
+int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+		       u_char *ecc_code)
 {
-	u_char idx, reg1, reg2, reg3;
-	int j;
+	uint8_t idx, reg1, reg2, reg3, tmp1, tmp2;
+	int i;
 
 	/* Initialize variables */
 	reg1 = reg2 = reg3 = 0;
-	ecc_code[0] = ecc_code[1] = ecc_code[2] = 0;
 
 	/* Build up column parity */
-	for(j = 0; j < 256; j++) {
-
+	for(i = 0; i < 256; i++) {
 		/* Get CP0 - CP5 from table */
-		idx = nand_ecc_precalc_table[dat[j]];
+		idx = nand_ecc_precalc_table[*dat++];
 		reg1 ^= (idx & 0x3f);
 
 		/* All bit XOR = 1 ? */
 		if (idx & 0x40) {
-			reg3 ^= (u_char) j;
-			reg2 ^= ~((u_char) j);
+			reg3 ^= (uint8_t) i;
+			reg2 ^= ~((uint8_t) i);
 		}
 	}
 
 	/* Create non-inverted ECC code from line parity */
-	nand_trans_result(reg2, reg3, ecc_code);
+	tmp1  = (reg3 & 0x80) >> 0; /* B7 -> B7 */
+	tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */
+	tmp1 |= (reg3 & 0x40) >> 1; /* B6 -> B5 */
+	tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */
+	tmp1 |= (reg3 & 0x20) >> 2; /* B5 -> B3 */
+	tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */
+	tmp1 |= (reg3 & 0x10) >> 3; /* B4 -> B1 */
+	tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */
+
+	tmp2  = (reg3 & 0x08) << 4; /* B3 -> B7 */
+	tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */
+	tmp2 |= (reg3 & 0x04) << 3; /* B2 -> B5 */
+	tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */
+	tmp2 |= (reg3 & 0x02) << 2; /* B1 -> B3 */
+	tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */
+	tmp2 |= (reg3 & 0x01) << 1; /* B0 -> B1 */
+	tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */
 
 	/* Calculate final ECC code */
-	ecc_code[0] = ~ecc_code[0];
-	ecc_code[1] = ~ecc_code[1];
+#ifdef CONFIG_MTD_NAND_ECC_SMC
+	ecc_code[0] = ~tmp2;
+	ecc_code[1] = ~tmp1;
+#else
+	ecc_code[0] = ~tmp1;
+	ecc_code[1] = ~tmp2;
+#endif
 	ecc_code[2] = ((~reg1) << 2) | 0x03;
+
 	return 0;
 }
+#endif /* CONFIG_NAND_SPL */
+
+static inline int countbits(uint32_t byte)
+{
+	int res = 0;
+
+	for (;byte; byte >>= 1)
+		res += byte & 0x01;
+	return res;
+}
 
 /**
  * nand_correct_data - [NAND Interface] Detect and correct bit error(s)
@@ -156,89 +152,51 @@
  *
  * Detect and correct a 1 bit error for 256 byte block
  */
-int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
+int nand_correct_data(struct mtd_info *mtd, u_char *dat,
+		      u_char *read_ecc, u_char *calc_ecc)
 {
-	u_char a, b, c, d1, d2, d3, add, bit, i;
+	uint8_t s0, s1, s2;
 
-	/* Do error detection */
-	d1 = calc_ecc[0] ^ read_ecc[0];
-	d2 = calc_ecc[1] ^ read_ecc[1];
-	d3 = calc_ecc[2] ^ read_ecc[2];
-
-	if ((d1 | d2 | d3) == 0) {
-		/* No errors */
+#ifdef CONFIG_MTD_NAND_ECC_SMC
+	s0 = calc_ecc[0] ^ read_ecc[0];
+	s1 = calc_ecc[1] ^ read_ecc[1];
+	s2 = calc_ecc[2] ^ read_ecc[2];
+#else
+	s1 = calc_ecc[0] ^ read_ecc[0];
+	s0 = calc_ecc[1] ^ read_ecc[1];
+	s2 = calc_ecc[2] ^ read_ecc[2];
+#endif
+	if ((s0 | s1 | s2) == 0)
 		return 0;
-	}
-	else {
-		a = (d1 ^ (d1 >> 1)) & 0x55;
-		b = (d2 ^ (d2 >> 1)) & 0x55;
-		c = (d3 ^ (d3 >> 1)) & 0x54;
 
-		/* Found and will correct single bit error in the data */
-		if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
-			c = 0x80;
-			add = 0;
-			a = 0x80;
-			for (i=0; i<4; i++) {
-				if (d1 & c)
-					add |= a;
-				c >>= 2;
-				a >>= 1;
-			}
-			c = 0x80;
-			for (i=0; i<4; i++) {
-				if (d2 & c)
-					add |= a;
-				c >>= 2;
-				a >>= 1;
-			}
-			bit = 0;
-			b = 0x04;
-			c = 0x80;
-			for (i=0; i<3; i++) {
-				if (d3 & c)
-					bit |= b;
-				c >>= 2;
-				b >>= 1;
-			}
-			b = 0x01;
-			a = dat[add];
-			a ^= (b << bit);
-			dat[add] = a;
-			return 1;
-		} else {
-			i = 0;
-			while (d1) {
-				if (d1 & 0x01)
-					++i;
-				d1 >>= 1;
-			}
-			while (d2) {
-				if (d2 & 0x01)
-					++i;
-				d2 >>= 1;
-			}
-			while (d3) {
-				if (d3 & 0x01)
-					++i;
-				d3 >>= 1;
-			}
-			if (i == 1) {
-				/* ECC Code Error Correction */
-				read_ecc[0] = calc_ecc[0];
-				read_ecc[1] = calc_ecc[1];
-				read_ecc[2] = calc_ecc[2];
-				return 2;
-			}
-			else {
-				/* Uncorrectable Error */
-				return -1;
-			}
-		}
+	/* Check for a single bit error */
+	if( ((s0 ^ (s0 >> 1)) & 0x55) == 0x55 &&
+	    ((s1 ^ (s1 >> 1)) & 0x55) == 0x55 &&
+	    ((s2 ^ (s2 >> 1)) & 0x54) == 0x54) {
+
+		uint32_t byteoffs, bitnum;
+
+		byteoffs = (s1 << 0) & 0x80;
+		byteoffs |= (s1 << 1) & 0x40;
+		byteoffs |= (s1 << 2) & 0x20;
+		byteoffs |= (s1 << 3) & 0x10;
+
+		byteoffs |= (s0 >> 4) & 0x08;
+		byteoffs |= (s0 >> 3) & 0x04;
+		byteoffs |= (s0 >> 2) & 0x02;
+		byteoffs |= (s0 >> 1) & 0x01;
+
+		bitnum = (s2 >> 5) & 0x04;
+		bitnum |= (s2 >> 4) & 0x02;
+		bitnum |= (s2 >> 3) & 0x01;
+
+		dat[byteoffs] ^= (1 << bitnum);
+
+		return 1;
 	}
 
-	/* Should never happen */
-	return -1;
+	if(countbits(s0 | ((uint32_t)s1 << 8) | ((uint32_t)s2 <<16)) == 1)
+		return 1;
+
+	return -EBADMSG;
 }
-
-#endif	/* CONFIG_COMMANDS & CFG_CMD_NAND */

drivers/nand/nand_ids.c

diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c
index 8b58736..37150c2 100644
--- a/drivers/nand/nand_ids.c
+++ b/drivers/nand/nand_ids.c
@@ -2,8 +2,6 @@
  *  drivers/mtd/nandids.c
  *
  *  Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
-  *
- * $Id: nand_ids.c,v 1.10 2004/05/26 13:40:12 gleixner Exp $
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,103 +10,158 @@
  */
 
 #include <common.h>
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-
 #include <linux/mtd/nand.h>
-
 /*
 *	Chip ID list
 *
 *	Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
 *	options
 *
-* 	Pagesize; 0, 256, 512
-*	0 	get this information from the extended chip ID
+*	Pagesize; 0, 256, 512
+*	0	get this information from the extended chip ID
 +	256	256 Byte page size
 *	512	512 Byte page size
 */
-struct nand_flash_dev nand_flash_ids[] = {
-	{"NAND 1MiB 5V 8-bit", 		0x6e, 256, 1, 0x1000, 0},
-	{"NAND 2MiB 5V 8-bit", 		0x64, 256, 2, 0x1000, 0},
-	{"NAND 4MiB 5V 8-bit", 		0x6b, 512, 4, 0x2000, 0},
-	{"NAND 1MiB 3,3V 8-bit", 	0xe8, 256, 1, 0x1000, 0},
-	{"NAND 1MiB 3,3V 8-bit", 	0xec, 256, 1, 0x1000, 0},
-	{"NAND 2MiB 3,3V 8-bit", 	0xea, 256, 2, 0x1000, 0},
+const struct nand_flash_dev nand_flash_ids[] = {
+
+#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
+	{"NAND 1MiB 5V 8-bit",		0x6e, 256, 1, 0x1000, 0},
+	{"NAND 2MiB 5V 8-bit",		0x64, 256, 2, 0x1000, 0},
+	{"NAND 4MiB 5V 8-bit",		0x6b, 512, 4, 0x2000, 0},
+	{"NAND 1MiB 3,3V 8-bit",	0xe8, 256, 1, 0x1000, 0},
+	{"NAND 1MiB 3,3V 8-bit",	0xec, 256, 1, 0x1000, 0},
+	{"NAND 2MiB 3,3V 8-bit",	0xea, 256, 2, 0x1000, 0},
 	{"NAND 4MiB 3,3V 8-bit", 	0xd5, 512, 4, 0x2000, 0},
-	{"NAND 4MiB 3,3V 8-bit", 	0xe3, 512, 4, 0x2000, 0},
-	{"NAND 4MiB 3,3V 8-bit", 	0xe5, 512, 4, 0x2000, 0},
-	{"NAND 8MiB 3,3V 8-bit", 	0xd6, 512, 8, 0x2000, 0},
+	{"NAND 4MiB 3,3V 8-bit",	0xe3, 512, 4, 0x2000, 0},
+	{"NAND 4MiB 3,3V 8-bit",	0xe5, 512, 4, 0x2000, 0},
+	{"NAND 8MiB 3,3V 8-bit",	0xd6, 512, 8, 0x2000, 0},
 
-	{"NAND 8MiB 1,8V 8-bit", 	0x39, 512, 8, 0x2000, 0},
-	{"NAND 8MiB 3,3V 8-bit", 	0xe6, 512, 8, 0x2000, 0},
-	{"NAND 8MiB 1,8V 16-bit", 	0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
-	{"NAND 8MiB 3,3V 16-bit", 	0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
+	{"NAND 8MiB 1,8V 8-bit",	0x39, 512, 8, 0x2000, 0},
+	{"NAND 8MiB 3,3V 8-bit",	0xe6, 512, 8, 0x2000, 0},
+	{"NAND 8MiB 1,8V 16-bit",	0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
+	{"NAND 8MiB 3,3V 16-bit",	0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
+#endif
 
-	{"NAND 16MiB 1,8V 8-bit", 	0x33, 512, 16, 0x4000, 0},
-	{"NAND 16MiB 3,3V 8-bit", 	0x73, 512, 16, 0x4000, 0},
-	{"NAND 16MiB 1,8V 16-bit", 	0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 16MiB 3,3V 16-bit", 	0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 16MiB 1,8V 8-bit",	0x33, 512, 16, 0x4000, 0},
+	{"NAND 16MiB 3,3V 8-bit",	0x73, 512, 16, 0x4000, 0},
+	{"NAND 16MiB 1,8V 16-bit",	0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 16MiB 3,3V 16-bit",	0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
 
-	{"NAND 32MiB 1,8V 8-bit", 	0x35, 512, 32, 0x4000, 0},
-	{"NAND 32MiB 3,3V 8-bit", 	0x75, 512, 32, 0x4000, 0},
-	{"NAND 32MiB 1,8V 16-bit", 	0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 32MiB 3,3V 16-bit", 	0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 32MiB 1,8V 8-bit",	0x35, 512, 32, 0x4000, 0},
+	{"NAND 32MiB 3,3V 8-bit",	0x75, 512, 32, 0x4000, 0},
+	{"NAND 32MiB 1,8V 16-bit",	0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 32MiB 3,3V 16-bit",	0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
 
-	{"NAND 64MiB 1,8V 8-bit", 	0x36, 512, 64, 0x4000, 0},
-	{"NAND 64MiB 3,3V 8-bit", 	0x76, 512, 64, 0x4000, 0},
-	{"NAND 64MiB 1,8V 16-bit", 	0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 64MiB 3,3V 16-bit", 	0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 64MiB 1,8V 8-bit",	0x36, 512, 64, 0x4000, 0},
+	{"NAND 64MiB 3,3V 8-bit",	0x76, 512, 64, 0x4000, 0},
+	{"NAND 64MiB 1,8V 16-bit",	0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 64MiB 3,3V 16-bit",	0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
 
-	{"NAND 128MiB 1,8V 8-bit", 	0x78, 512, 128, 0x4000, 0},
-	{"NAND 128MiB 3,3V 8-bit", 	0x79, 512, 128, 0x4000, 0},
-	{"NAND 128MiB 1,8V 16-bit", 	0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 128MiB 3,3V 16-bit", 	0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 128MiB 1,8V 8-bit",	0x78, 512, 128, 0x4000, 0},
+	{"NAND 128MiB 1,8V 8-bit",	0x39, 512, 128, 0x4000, 0},
+	{"NAND 128MiB 3,3V 8-bit",	0x79, 512, 128, 0x4000, 0},
+	{"NAND 128MiB 1,8V 16-bit",	0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 128MiB 1,8V 16-bit",	0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 128MiB 3,3V 16-bit",	0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
+	{"NAND 128MiB 3,3V 16-bit",	0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
 
-	{"NAND 256MiB 3,3V 8-bit", 	0x71, 512, 256, 0x4000, 0},
+	{"NAND 256MiB 3,3V 8-bit",	0x71, 512, 256, 0x4000, 0},
 
-	{"NAND 512MiB 3,3V 8-bit", 	0xDC, 512, 512, 0x4000, 0},
+	/*
+	 * These are the new chips with large page size. The pagesize and the
+	 * erasesize is determined from the extended id bytes
+	 */
+#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR)
+#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
 
-	/* These are the new chips with large page size. The pagesize
-	* and the erasesize is determined from the extended id bytes
-	*/
+	/*512 Megabit */
+	{"NAND 64MiB 1,8V 8-bit",	0xA2, 0,  64, 0, LP_OPTIONS},
+	{"NAND 64MiB 1,8V 8-bit",	0xA0, 0,  64, 0, LP_OPTIONS},
+	{"NAND 64MiB 3,3V 8-bit",	0xF2, 0,  64, 0, LP_OPTIONS},
+	{"NAND 64MiB 3,3V 8-bit",	0xD0, 0,  64, 0, LP_OPTIONS},
+	{"NAND 64MiB 1,8V 16-bit",	0xB2, 0,  64, 0, LP_OPTIONS16},
+	{"NAND 64MiB 1,8V 16-bit",	0xB0, 0,  64, 0, LP_OPTIONS16},
+	{"NAND 64MiB 3,3V 16-bit",	0xC2, 0,  64, 0, LP_OPTIONS16},
+	{"NAND 64MiB 3,3V 16-bit",	0xC0, 0,  64, 0, LP_OPTIONS16},
+
 	/* 1 Gigabit */
-	{"NAND 128MiB 1,8V 8-bit", 	0xA1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 128MiB 3,3V 8-bit", 	0xF1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 128MiB 1,8V 16-bit", 	0xB1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-	{"NAND 128MiB 3,3V 16-bit", 	0xC1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 128MiB 1,8V 8-bit",	0xA1, 0, 128, 0, LP_OPTIONS},
+	{"NAND 128MiB 3,3V 8-bit",	0xF1, 0, 128, 0, LP_OPTIONS},
+	{"NAND 128MiB 3,3V 8-bit",	0xD1, 0, 128, 0, LP_OPTIONS},
+	{"NAND 128MiB 1,8V 16-bit",	0xB1, 0, 128, 0, LP_OPTIONS16},
+	{"NAND 128MiB 3,3V 16-bit",	0xC1, 0, 128, 0, LP_OPTIONS16},
+	{"NAND 128MiB 1,8V 16-bit",     0xAD, 0, 128, 0, LP_OPTIONS16},
 
 	/* 2 Gigabit */
-	{"NAND 256MiB 1,8V 8-bit", 	0xAA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 256MiB 3,3V 8-bit", 	0xDA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 256MiB 1,8V 16-bit", 	0xBA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-	{"NAND 256MiB 3,3V 16-bit", 	0xCA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 256MiB 1,8V 8-bit",	0xAA, 0, 256, 0, LP_OPTIONS},
+	{"NAND 256MiB 3,3V 8-bit",	0xDA, 0, 256, 0, LP_OPTIONS},
+	{"NAND 256MiB 1,8V 16-bit",	0xBA, 0, 256, 0, LP_OPTIONS16},
+	{"NAND 256MiB 3,3V 16-bit",	0xCA, 0, 256, 0, LP_OPTIONS16},
 
 	/* 4 Gigabit */
-	{"NAND 512MiB 1,8V 8-bit", 	0xAC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 512MiB 3,3V 8-bit", 	0xDC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 512MiB 1,8V 16-bit", 	0xBC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-	{"NAND 512MiB 3,3V 16-bit", 	0xCC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 512MiB 1,8V 8-bit",	0xAC, 0, 512, 0, LP_OPTIONS},
+	{"NAND 512MiB 3,3V 8-bit",	0xDC, 0, 512, 0, LP_OPTIONS},
+	{"NAND 512MiB 1,8V 16-bit",	0xBC, 0, 512, 0, LP_OPTIONS16},
+	{"NAND 512MiB 3,3V 16-bit",	0xCC, 0, 512, 0, LP_OPTIONS16},
 
 	/* 8 Gigabit */
-	{"NAND 1GiB 1,8V 8-bit", 	0xA3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 1GiB 3,3V 8-bit", 	0xD3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 1GiB 1,8V 16-bit", 	0xB3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-	{"NAND 1GiB 3,3V 16-bit", 	0xC3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 1GiB 1,8V 8-bit",	0xA3, 0, 1024, 0, LP_OPTIONS},
+	{"NAND 1GiB 3,3V 8-bit",	0xD3, 0, 1024, 0, LP_OPTIONS},
+	{"NAND 1GiB 1,8V 16-bit",	0xB3, 0, 1024, 0, LP_OPTIONS16},
+	{"NAND 1GiB 3,3V 16-bit",	0xC3, 0, 1024, 0, LP_OPTIONS16},
 
 	/* 16 Gigabit */
-	{"NAND 2GiB 1,8V 8-bit", 	0xA5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 2GiB 3,3V 8-bit", 	0xD5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR},
-	{"NAND 2GiB 1,8V 16-bit", 	0xB5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
-	{"NAND 2GiB 3,3V 16-bit", 	0xC5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR},
+	{"NAND 2GiB 1,8V 8-bit",	0xA5, 0, 2048, 0, LP_OPTIONS},
+	{"NAND 2GiB 3,3V 8-bit",	0xD5, 0, 2048, 0, LP_OPTIONS},
+	{"NAND 2GiB 1,8V 16-bit",	0xB5, 0, 2048, 0, LP_OPTIONS16},
+	{"NAND 2GiB 3,3V 16-bit",	0xC5, 0, 2048, 0, LP_OPTIONS16},
 
-	/* Renesas AND 1 Gigabit. Those chips do not support extended id and have a strange page/block layout !
-	 * The chosen minimum erasesize is 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page planes
-	 * 1 block = 2 pages, but due to plane arrangement the blocks 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7
-	 * Anyway JFFS2 would increase the eraseblock size so we chose a combined one which can be erased in one go
-	 * There are more speed improvements for reads and writes possible, but not implemented now
+//	{"NAND 2GiB 3,3V 8-bit",	0x48, 4096, 2048, 0x100000, 0},
+
+	/* 32 Gigabit */
+	{"NAND 4GiB 1,8V 8-bit",	0xA7, 0, 4096, 0, LP_OPTIONS},
+	{"NAND 4GiB 3,3V 8-bit",	0xD7, 0, 4096, 0, LP_OPTIONS},
+	{"NAND 4GiB 1,8V 16-bit",	0xB7, 0, 4096, 0, LP_OPTIONS16},
+	{"NAND 4GiB 3,3V 16-bit",	0xC7, 0, 4096, 0, LP_OPTIONS16},
+
+	/* 64 Gigabit */
+	{"NAND 8GiB 1,8V 8-bit",	0xAE, 0, 8192, 0, LP_OPTIONS},
+	{"NAND 8GiB 3,3V 8-bit",	0xDE, 0, 8192, 0, LP_OPTIONS},
+	{"NAND 8GiB 1,8V 16-bit",	0xBE, 0, 8192, 0, LP_OPTIONS16},
+	{"NAND 8GiB 3,3V 16-bit",	0xCE, 0, 8192, 0, LP_OPTIONS16},
+
+	/* 128 Gigabit */
+	{"NAND 16GiB 1,8V 8-bit",	0x1A, 0, 16384, 0, LP_OPTIONS},
+	{"NAND 16GiB 3,3V 8-bit",	0x3A, 0, 16384, 0, LP_OPTIONS},
+	{"NAND 16GiB 1,8V 16-bit",	0x2A, 0, 16384, 0, LP_OPTIONS16},
+	{"NAND 16GiB 3,3V 16-bit",	0x4A, 0, 16384, 0, LP_OPTIONS16},
+
+	/* 256 Gigabit */
+	{"NAND 32GiB 1,8V 8-bit",	0x1C, 0, 32768, 0, LP_OPTIONS},
+	{"NAND 32GiB 3,3V 8-bit",	0x3C, 0, 32768, 0, LP_OPTIONS},
+	{"NAND 32GiB 1,8V 16-bit",	0x2C, 0, 32768, 0, LP_OPTIONS16},
+	{"NAND 32GiB 3,3V 16-bit",	0x4C, 0, 32768, 0, LP_OPTIONS16},
+
+	/* 512 Gigabit */
+	{"NAND 64GiB 1,8V 8-bit",	0x1E, 0, 65536, 0, LP_OPTIONS},
+	{"NAND 64GiB 3,3V 8-bit",	0x3E, 0, 65536, 0, LP_OPTIONS},
+	{"NAND 64GiB 1,8V 16-bit",	0x2E, 0, 65536, 0, LP_OPTIONS16},
+	{"NAND 64GiB 3,3V 16-bit",	0x4E, 0, 65536, 0, LP_OPTIONS16},
+
+	/*
+	 * Renesas AND 1 Gigabit. Those chips do not support extended id and
+	 * have a strange page/block layout !  The chosen minimum erasesize is
+	 * 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page
+	 * planes 1 block = 2 pages, but due to plane arrangement the blocks
+	 * 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 Anyway JFFS2 would
+	 * increase the eraseblock size so we chose a combined one which can be
+	 * erased in one go There are more speed improvements for reads and
+	 * writes possible, but not implemented now
 	 */
-	{"AND 128MiB 3,3V 8-bit",	0x01, 2048, 128, 0x4000, NAND_IS_AND | NAND_NO_AUTOINCR | NAND_4PAGE_ARRAY},
+	{"AND 128MiB 3,3V 8-bit",	0x01, 2048, 128, 0x4000,
+	 NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY |
+	 BBT_AUTO_REFRESH
+	},
 
 	{NULL,}
 };
@@ -116,13 +169,15 @@
 /*
 *	Manufacturer ID list
 */
-struct nand_manufacturers nand_manuf_ids[] = {
+const struct nand_manufacturers nand_manuf_ids[] = {
 	{NAND_MFR_TOSHIBA, "Toshiba"},
 	{NAND_MFR_SAMSUNG, "Samsung"},
 	{NAND_MFR_FUJITSU, "Fujitsu"},
 	{NAND_MFR_NATIONAL, "National"},
 	{NAND_MFR_RENESAS, "Renesas"},
 	{NAND_MFR_STMICRO, "ST Micro"},
+	{NAND_MFR_HYNIX, "Hynix"},
+	{NAND_MFR_MICRON, "Micron"},
+	{NAND_MFR_AMD, "AMD"},
 	{0x0, "Unknown"}
 };
-#endif

drivers/nand/nand_util.c

diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c
index 10bf036..7ed8b18 100644
--- a/drivers/nand/nand_util.c
+++ b/drivers/nand/nand_util.c
@@ -1,5 +1,5 @@
 /*
- * drivers/nand/nand_util.c
+ * drivers/mtd/nand/nand_util.c
  *
  * Copyright (C) 2006 by Weiss-Electronic GmbH.
  * All rights reserved.
@@ -11,6 +11,9 @@
  *		nandwrite.c by Steven J. Hill (sjhill@realitydiluted.com)
  *			       and Thomas Gleixner (tglx@linutronix.de)
  *
+ * Copyright (C) 2008 Nokia Corporation: drop_ffs() function by
+ * Artem Bityutskiy <dedekind1@gmail.com> from mtd-utils
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -28,16 +31,22 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  *
+ * Copyright 2010 Freescale Semiconductor
+ * The portions of this file whose copyright is held by Freescale and which
+ * are not considered a derived work of GPL v2-only code may be distributed
+ * and/or modified under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
  */
 
 #include <common.h>
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-
 #include <command.h>
 #include <watchdog.h>
 #include <malloc.h>
+#include <div64.h>
 
+#include <asm/errno.h>
+#include <linux/mtd/mtd.h>
 #include <nand.h>
 #include <jffs2/jffs2.h>
 
@@ -48,12 +57,6 @@
 #define cpu_to_je16(x) (x)
 #define cpu_to_je32(x) (x)
 
-/*****************************************************************************/
-static int nand_block_bad_scrub(struct mtd_info *mtd, loff_t ofs, int getchip)
-{
-	return 0;
-}
-
 /**
  * nand_erase_opts: - erase NAND flash with support for various options
  *		      (jffs2 formating)
@@ -68,92 +71,51 @@
 int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 {
 	struct jffs2_unknown_node cleanmarker;
-	int clmpos = 0;
-	int clmlen = 8;
 	erase_info_t erase;
-	ulong erase_length;
-	int isNAND;
+	unsigned long erase_length, erased_length; /* in blocks */
 	int bbtest = 1;
 	int result;
 	int percent_complete = -1;
-	int (*nand_block_bad_old)(struct mtd_info *, loff_t, int) = NULL;
 	const char *mtd_device = meminfo->name;
+	struct mtd_oob_ops oob_opts;
+	struct nand_chip *chip = meminfo->priv;
+
+	if ((opts->offset & (meminfo->writesize - 1)) != 0) {
+		printf("Attempt to erase non page aligned data\n");
+		return -1;
+	}
 
 	memset(&erase, 0, sizeof(erase));
+	memset(&oob_opts, 0, sizeof(oob_opts));
 
 	erase.mtd = meminfo;
 	erase.len  = meminfo->erasesize;
 	erase.addr = opts->offset;
-	erase_length = opts->length;
+	erase_length = lldiv(opts->length + meminfo->erasesize - 1,
+			     meminfo->erasesize);
 
-	isNAND = meminfo->type == MTD_NANDFLASH ? 1 : 0;
-
-	if (opts->jffs2) {
-		cleanmarker.magic = cpu_to_je16 (JFFS2_MAGIC_BITMASK);
-		cleanmarker.nodetype = cpu_to_je16 (JFFS2_NODETYPE_CLEANMARKER);
-		if (isNAND) {
-			struct nand_oobinfo *oobinfo = &meminfo->oobinfo;
-
-			/* check for autoplacement */
-			if (oobinfo->useecc == MTD_NANDECC_AUTOPLACE) {
-				/* get the position of the free bytes */
-				if (!oobinfo->oobfree[0][1]) {
-					printf(" Eeep. Autoplacement selected "
-					       "and no empty space in oob\n");
-					return -1;
-				}
-				clmpos = oobinfo->oobfree[0][0];
-				clmlen = oobinfo->oobfree[0][1];
-				if (clmlen > 8)
-					clmlen = 8;
-			} else {
-				/* legacy mode */
-				switch (meminfo->oobsize) {
-				case 8:
-					clmpos = 6;
-					clmlen = 2;
-					break;
-				case 16:
-					clmpos = 8;
-					clmlen = 8;
-					break;
-				case 64:
-					clmpos = 16;
-					clmlen = 8;
-					break;
-				}
-			}
-
-			cleanmarker.totlen = cpu_to_je32(8);
-		} else {
-			cleanmarker.totlen =
-				cpu_to_je32(sizeof(struct jffs2_unknown_node));
-		}
-		cleanmarker.hdr_crc =  cpu_to_je32(
-			crc32_no_comp(0, (unsigned char *) &cleanmarker,
-				      sizeof(struct jffs2_unknown_node) - 4));
-	}
+	cleanmarker.magic = cpu_to_je16 (JFFS2_MAGIC_BITMASK);
+	cleanmarker.nodetype = cpu_to_je16 (JFFS2_NODETYPE_CLEANMARKER);
+	cleanmarker.totlen = cpu_to_je32(8);
 
 	/* scrub option allows to erase badblock. To prevent internal
 	 * check from erase() method, set block check method to dummy
 	 * and disable bad block table while erasing.
 	 */
 	if (opts->scrub) {
-		struct nand_chip *priv_nand = meminfo->priv;
-
-		nand_block_bad_old = priv_nand->block_bad;
-		priv_nand->block_bad = nand_block_bad_scrub;
-		/* we don't need the bad block table anymore...
+		erase.scrub = opts->scrub;
+		/*
+		 * We don't need the bad block table anymore...
 		 * after scrub, there are no bad blocks left!
 		 */
-		if (priv_nand->bbt) {
-			kfree(priv_nand->bbt);
+		if (chip->bbt) {
+			kfree(chip->bbt);
 		}
-		priv_nand->bbt = NULL;
+		chip->bbt = NULL;
 	}
 
-	for (;
-	     erase.addr < opts->offset + erase_length;
+	for (erased_length = 0;
+	     erased_length < erase_length;
 	     erase.addr += meminfo->erasesize) {
 
 		WATCHDOG_RESET ();
@@ -163,9 +125,13 @@
 			if (ret > 0) {
 				if (!opts->quiet)
 					printf("\rSkipping bad block at  "
-					       "0x%08x                   "
+					       "0x%08llx                 "
 					       "                         \n",
 					       erase.addr);
+
+				if (!opts->spread)
+					erased_length++;
+
 				continue;
 
 			} else if (ret < 0) {
@@ -176,6 +142,8 @@
 			}
 		}
 
+		erased_length++;
+
 		result = meminfo->erase(meminfo, &erase);
 		if (result != 0) {
 			printf("\n%s: MTD Erase failure: %d\n",
@@ -184,34 +152,29 @@
 		}
 
 		/* format for JFFS2 ? */
-		if (opts->jffs2) {
+		if (opts->jffs2 && chip->ecc.layout->oobavail >= 8) {
+			chip->ops.ooblen = 8;
+			chip->ops.datbuf = NULL;
+			chip->ops.oobbuf = (uint8_t *)&cleanmarker;
+			chip->ops.ooboffs = 0;
+			chip->ops.mode = MTD_OOB_AUTO;
 
-			/* write cleanmarker */
-			if (isNAND) {
-				size_t written;
-				result = meminfo->write_oob(meminfo,
-							    erase.addr + clmpos,
-							    clmlen,
-							    &written,
-							    (unsigned char *)
-							    &cleanmarker);
-				if (result != 0) {
-					printf("\n%s: MTD writeoob failure: %d\n",
-					       mtd_device, result);
-					continue;
-				}
-			} else {
-				printf("\n%s: this erase routine only supports"
-				       " NAND devices!\n",
-				       mtd_device);
+			result = meminfo->write_oob(meminfo,
+			                            erase.addr,
+			                            &chip->ops);
+			if (result != 0) {
+				printf("\n%s: MTD writeoob failure: %d\n",
+				       mtd_device, result);
+				continue;
 			}
 		}
 
 		if (!opts->quiet) {
-			int percent = (int)
-				((unsigned long long)
-				 (erase.addr+meminfo->erasesize-opts->offset)
-				 * 100 / erase_length);
+			unsigned long long n = erased_length * 100ULL;
+			int percent;
+
+			do_div(n, erase_length);
+			percent = (int)n;
 
 			/* output progress message only at whole percent
 			 * steps to reduce the number of messages printed
@@ -220,11 +183,11 @@
 			if (percent != percent_complete) {
 				percent_complete = percent;
 
-				printf("\rErasing at 0x%x -- %3d%% complete.",
+				printf("\rErasing at 0x%llx -- %3d%% complete.",
 				       erase.addr, percent);
 
 				if (opts->jffs2 && result == 0)
-					printf(" Cleanmarker written at 0x%x.",
+					printf(" Cleanmarker written at 0x%llx.",
 					       erase.addr);
 			}
 		}
@@ -232,456 +195,13 @@
 	if (!opts->quiet)
 		printf("\n");
 
-	if (nand_block_bad_old) {
-		struct nand_chip *priv_nand = meminfo->priv;
-
-		priv_nand->block_bad = nand_block_bad_old;
-		priv_nand->scan_bbt(meminfo);
-	}
+	if (opts->scrub)
+		chip->scan_bbt(meminfo);
 
 	return 0;
 }
 
-#define MAX_PAGE_SIZE	2048
-#define MAX_OOB_SIZE	64
-
-/*
- * buffer array used for writing data
- */
-static unsigned char data_buf[MAX_PAGE_SIZE];
-static unsigned char oob_buf[MAX_OOB_SIZE];
-
-/* OOB layouts to pass into the kernel as default */
-static struct nand_oobinfo none_oobinfo = {
-	.useecc = MTD_NANDECC_OFF,
-};
-
-static struct nand_oobinfo jffs2_oobinfo = {
-	.useecc = MTD_NANDECC_PLACE,
-	.eccbytes = 6,
-	.eccpos = { 0, 1, 2, 3, 6, 7 }
-};
-
-static struct nand_oobinfo yaffs_oobinfo = {
-	.useecc = MTD_NANDECC_PLACE,
-	.eccbytes = 6,
-	.eccpos = { 8, 9, 10, 13, 14, 15}
-};
-
-static struct nand_oobinfo autoplace_oobinfo = {
-	.useecc = MTD_NANDECC_AUTOPLACE
-};
-
-/**
- * nand_write_opts: - write image to NAND flash with support for various options
- *
- * @param meminfo	NAND device to erase
- * @param opts		write options (@see nand_write_options)
- * @return		0 in case of success
- *
- * This code is ported from nandwrite.c from Linux mtd utils by
- * Steven J. Hill and Thomas Gleixner.
- */
-int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts)
-{
-	int imglen = 0;
-	int pagelen;
-	int baderaseblock;
-	int blockstart = -1;
-	loff_t offs;
-	int readlen;
-	int oobinfochanged = 0;
-	int percent_complete = -1;
-	struct nand_oobinfo old_oobinfo;
-	ulong mtdoffset = opts->offset;
-	ulong erasesize_blockalign;
-	u_char *buffer = opts->buffer;
-	size_t written;
-	int result;
-
-	if (opts->pad && opts->writeoob) {
-		printf("Can't pad when oob data is present.\n");
-		return -1;
-	}
-
-	/* set erasesize to specified number of blocks - to match
-	 * jffs2 (virtual) block size */
-	if (opts->blockalign == 0) {
-		erasesize_blockalign = meminfo->erasesize;
-	} else {
-		erasesize_blockalign = meminfo->erasesize * opts->blockalign;
-	}
-
-	/* make sure device page sizes are valid */
-	if (!(meminfo->oobsize == 16 && meminfo->oobblock == 512)
-	    && !(meminfo->oobsize == 8 && meminfo->oobblock == 256)
-	    && !(meminfo->oobsize == 64 && meminfo->oobblock == 2048)) {
-		printf("Unknown flash (not normal NAND)\n");
-		return -1;
-	}
-
-	/* read the current oob info */
-	memcpy(&old_oobinfo, &meminfo->oobinfo, sizeof(old_oobinfo));
-
-	/* write without ecc? */
-	if (opts->noecc) {
-		memcpy(&meminfo->oobinfo, &none_oobinfo,
-		       sizeof(meminfo->oobinfo));
-		oobinfochanged = 1;
-	}
-
-	/* autoplace ECC? */
-	if (opts->autoplace && (old_oobinfo.useecc != MTD_NANDECC_AUTOPLACE)) {
-
-		memcpy(&meminfo->oobinfo, &autoplace_oobinfo,
-		       sizeof(meminfo->oobinfo));
-		oobinfochanged = 1;
-	}
-
-	/* force OOB layout for jffs2 or yaffs? */
-	if (opts->forcejffs2 || opts->forceyaffs) {
-		struct nand_oobinfo *oobsel =
-			opts->forcejffs2 ? &jffs2_oobinfo : &yaffs_oobinfo;
-
-		if (meminfo->oobsize == 8) {
-			if (opts->forceyaffs) {
-				printf("YAFSS cannot operate on "
-				       "256 Byte page size\n");
-				goto restoreoob;
-			}
-			/* Adjust number of ecc bytes */
-			jffs2_oobinfo.eccbytes = 3;
-		}
-
-		memcpy(&meminfo->oobinfo, oobsel, sizeof(meminfo->oobinfo));
-	}
-
-	/* get image length */
-	imglen = opts->length;
-	pagelen = meminfo->oobblock
-		+ ((opts->writeoob != 0) ? meminfo->oobsize : 0);
-
-	/* check, if file is pagealigned */
-	if ((!opts->pad) && ((imglen % pagelen) != 0)) {
-		printf("Input block length is not page aligned\n");
-		goto restoreoob;
-	}
-
-	/* check, if length fits into device */
-	if (((imglen / pagelen) * meminfo->oobblock)
-	     > (meminfo->size - opts->offset)) {
-		printf("Image %d bytes, NAND page %d bytes, "
-		       "OOB area %u bytes, device size %u bytes\n",
-		       imglen, pagelen, meminfo->oobblock, meminfo->size);
-		printf("Input block does not fit into device\n");
-		goto restoreoob;
-	}
-
-	if (!opts->quiet)
-		printf("\n");
-
-	/* get data from input and write to the device */
-	while (imglen && (mtdoffset < meminfo->size)) {
-
-		WATCHDOG_RESET ();
-
-		/*
-		 * new eraseblock, check for bad block(s). Stay in the
-		 * loop to be sure if the offset changes because of
-		 * a bad block, that the next block that will be
-		 * written to is also checked. Thus avoiding errors if
-		 * the block(s) after the skipped block(s) is also bad
-		 * (number of blocks depending on the blockalign
-		 */
-		while (blockstart != (mtdoffset & (~erasesize_blockalign+1))) {
-			blockstart = mtdoffset & (~erasesize_blockalign+1);
-			offs = blockstart;
-			baderaseblock = 0;
-
-			/* check all the blocks in an erase block for
-			 * bad blocks */
-			do {
-				int ret = meminfo->block_isbad(meminfo, offs);
-
-				if (ret < 0) {
-					printf("Bad block check failed\n");
-					goto restoreoob;
-				}
-				if (ret == 1) {
-					baderaseblock = 1;
-					if (!opts->quiet)
-						printf("\rBad block at 0x%lx "
-						       "in erase block from "
-						       "0x%x will be skipped\n",
-						       (long) offs,
-						       blockstart);
-				}
-
-				if (baderaseblock) {
-					mtdoffset = blockstart
-						+ erasesize_blockalign;
-				}
-				offs +=	 erasesize_blockalign
-					/ opts->blockalign;
-			} while (offs < blockstart + erasesize_blockalign);
-		}
-
-		readlen = meminfo->oobblock;
-		if (opts->pad && (imglen < readlen)) {
-			readlen = imglen;
-			memset(data_buf + readlen, 0xff,
-			       meminfo->oobblock - readlen);
-		}
-
-		/* read page data from input memory buffer */
-		memcpy(data_buf, buffer, readlen);
-		buffer += readlen;
-
-		if (opts->writeoob) {
-			/* read OOB data from input memory block, exit
-			 * on failure */
-			memcpy(oob_buf, buffer, meminfo->oobsize);
-			buffer += meminfo->oobsize;
-
-			/* write OOB data first, as ecc will be placed
-			 * in there*/
-			result = meminfo->write_oob(meminfo,
-						    mtdoffset,
-						    meminfo->oobsize,
-						    &written,
-						    (unsigned char *)
-						    &oob_buf);
-
-			if (result != 0) {
-				printf("\nMTD writeoob failure: %d\n",
-				       result);
-				goto restoreoob;
-			}
-			imglen -= meminfo->oobsize;
-		}
-
-		/* write out the page data */
-		result = meminfo->write(meminfo,
-					mtdoffset,
-					meminfo->oobblock,
-					&written,
-					(unsigned char *) &data_buf);
-
-		if (result != 0) {
-			printf("writing NAND page at offset 0x%lx failed\n",
-			       mtdoffset);
-			goto restoreoob;
-		}
-		imglen -= readlen;
-
-		if (!opts->quiet) {
-			int percent = (int)
-				((unsigned long long)
-				 (opts->length-imglen) * 100
-				 / opts->length);
-			/* output progress message only at whole percent
-			 * steps to reduce the number of messages printed
-			 * on (slow) serial consoles
-			 */
-			if (percent != percent_complete) {
-				printf("\rWriting data at 0x%x "
-				       "-- %3d%% complete.",
-				       mtdoffset, percent);
-				percent_complete = percent;
-			}
-		}
-
-		mtdoffset += meminfo->oobblock;
-	}
-
-	if (!opts->quiet)
-		printf("\n");
-
-restoreoob:
-	if (oobinfochanged) {
-		memcpy(&meminfo->oobinfo, &old_oobinfo,
-		       sizeof(meminfo->oobinfo));
-	}
-
-	if (imglen > 0) {
-		printf("Data did not fit into device, due to bad blocks\n");
-		return -1;
-	}
-
-	/* return happy */
-	return 0;
-}
-
-/**
- * nand_read_opts: - read image from NAND flash with support for various options
- *
- * @param meminfo	NAND device to erase
- * @param opts		read options (@see struct nand_read_options)
- * @return		0 in case of success
- *
- */
-int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts)
-{
-	int imglen = opts->length;
-	int pagelen;
-	int baderaseblock;
-	int blockstart = -1;
-	int percent_complete = -1;
-	loff_t offs;
-	size_t readlen;
-	ulong mtdoffset = opts->offset;
-	u_char *buffer = opts->buffer;
-	int result;
-
-	/* make sure device page sizes are valid */
-	if (!(meminfo->oobsize == 16 && meminfo->oobblock == 512)
-	    && !(meminfo->oobsize == 8 && meminfo->oobblock == 256)
-	    && !(meminfo->oobsize == 64 && meminfo->oobblock == 2048)) {
-		printf("Unknown flash (not normal NAND)\n");
-		return -1;
-	}
-
-	pagelen = meminfo->oobblock
-		+ ((opts->readoob != 0) ? meminfo->oobsize : 0);
-
-	/* check, if length is not larger than device */
-	if (((imglen / pagelen) * meminfo->oobblock)
-	     > (meminfo->size - opts->offset)) {
-		printf("Image %d bytes, NAND page %d bytes, "
-		       "OOB area %u bytes, device size %u bytes\n",
-		       imglen, pagelen, meminfo->oobblock, meminfo->size);
-		printf("Input block is larger than device\n");
-		return -1;
-	}
-
-	if (!opts->quiet)
-		printf("\n");
-
-	/* get data from input and write to the device */
-	while (imglen && (mtdoffset < meminfo->size)) {
-
-		WATCHDOG_RESET ();
-
-		/*
-		 * new eraseblock, check for bad block(s). Stay in the
-		 * loop to be sure if the offset changes because of
-		 * a bad block, that the next block that will be
-		 * written to is also checked. Thus avoiding errors if
-		 * the block(s) after the skipped block(s) is also bad
-		 * (number of blocks depending on the blockalign
-		 */
-		while (blockstart != (mtdoffset & (~meminfo->erasesize+1))) {
-			blockstart = mtdoffset & (~meminfo->erasesize+1);
-			offs = blockstart;
-			baderaseblock = 0;
-
-			/* check all the blocks in an erase block for
-			 * bad blocks */
-			do {
-				int ret = meminfo->block_isbad(meminfo, offs);
-
-				if (ret < 0) {
-					printf("Bad block check failed\n");
-					return -1;
-				}
-				if (ret == 1) {
-					baderaseblock = 1;
-					if (!opts->quiet)
-						printf("\rBad block at 0x%lx "
-						       "in erase block from "
-						       "0x%x will be skipped\n",
-						       (long) offs,
-						       blockstart);
-				}
-
-				if (baderaseblock) {
-					mtdoffset = blockstart
-						+ meminfo->erasesize;
-				}
-				offs +=	 meminfo->erasesize;
-
-			} while (offs < blockstart + meminfo->erasesize);
-		}
-
-
-		/* read page data to memory buffer */
-		result = meminfo->read(meminfo,
-				       mtdoffset,
-				       meminfo->oobblock,
-				       &readlen,
-				       (unsigned char *) &data_buf);
-
-		if (result != 0) {
-			printf("reading NAND page at offset 0x%lx failed\n",
-			       mtdoffset);
-			return -1;
-		}
-
-		if (imglen < readlen) {
-			readlen = imglen;
-		}
-
-		memcpy(buffer, data_buf, readlen);
-		buffer += readlen;
-		imglen -= readlen;
-
-		if (opts->readoob) {
-			result = meminfo->read_oob(meminfo,
-						   mtdoffset,
-						   meminfo->oobsize,
-						   &readlen,
-						   (unsigned char *)
-						   &oob_buf);
-
-			if (result != 0) {
-				printf("\nMTD readoob failure: %d\n",
-				       result);
-				return -1;
-			}
-
-
-			if (imglen < readlen) {
-				readlen = imglen;
-			}
-
-			memcpy(buffer, oob_buf, readlen);
-
-			buffer += readlen;
-			imglen -= readlen;
-		}
-
-		if (!opts->quiet) {
-			int percent = (int)
-				((unsigned long long)
-				 (opts->length-imglen) * 100
-				 / opts->length);
-			/* output progress message only at whole percent
-			 * steps to reduce the number of messages printed
-			 * on (slow) serial consoles
-			 */
-			if (percent != percent_complete) {
-			if (!opts->quiet)
-				printf("\rReading data from 0x%x "
-				       "-- %3d%% complete.",
-				       mtdoffset, percent);
-				percent_complete = percent;
-			}
-		}
-
-		mtdoffset += meminfo->oobblock;
-	}
-
-	if (!opts->quiet)
-		printf("\n");
-
-	if (imglen > 0) {
-		printf("Could not read entire image due to bad blocks\n");
-		return -1;
-	}
-
-	/* return happy */
-	return 0;
-}
+#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
 
 /******************************************************************************
  * Support for locking / unlocking operations of some NAND devices
@@ -697,7 +217,7 @@
  * nand_lock: Set all pages of NAND flash chip to the LOCK or LOCK-TIGHT
  *	      state
  *
- * @param meminfo	nand mtd instance
+ * @param mtd		nand mtd instance
  * @param tight		bring device in lock tight mode
  *
  * @return		0 on success, -1 in case of error
@@ -714,21 +234,21 @@
  *   calls will fail. It is only posible to leave lock-tight state by
  *   an hardware signal (low pulse on _WP pin) or by power down.
  */
-int nand_lock(nand_info_t *meminfo, int tight)
+int nand_lock(struct mtd_info *mtd, int tight)
 {
 	int ret = 0;
 	int status;
-	struct nand_chip *this = meminfo->priv;
+	struct nand_chip *chip = mtd->priv;
 
 	/* select the NAND device */
-	this->select_chip(meminfo, 0);
+	chip->select_chip(mtd, 0);
 
-	this->cmdfunc(meminfo,
+	chip->cmdfunc(mtd,
 		      (tight ? NAND_CMD_LOCK_TIGHT : NAND_CMD_LOCK),
 		      -1, -1);
 
 	/* call wait ready function */
-	status = this->waitfunc(meminfo, this, FL_WRITING);
+	status = chip->waitfunc(mtd, chip);
 
 	/* see if device thinks it succeeded */
 	if (status & 0x01) {
@@ -736,7 +256,7 @@
 	}
 
 	/* de-select the NAND device */
-	this->select_chip(meminfo, -1);
+	chip->select_chip(mtd, -1);
 	return ret;
 }
 
@@ -744,7 +264,7 @@
  * nand_get_lock_status: - query current lock state from one page of NAND
  *			   flash
  *
- * @param meminfo	nand mtd instance
+ * @param mtd		nand mtd instance
  * @param offset	page address to query (muss be page aligned!)
  *
  * @return		-1 in case of error
@@ -755,19 +275,19 @@
  *			  NAND_LOCK_STATUS_UNLOCK: page unlocked
  *
  */
-int nand_get_lock_status(nand_info_t *meminfo, ulong offset)
+int nand_get_lock_status(struct mtd_info *mtd, loff_t offset)
 {
 	int ret = 0;
 	int chipnr;
 	int page;
-	struct nand_chip *this = meminfo->priv;
+	struct nand_chip *chip = mtd->priv;
 
 	/* select the NAND device */
-	chipnr = (int)(offset >> this->chip_shift);
-	this->select_chip(meminfo, chipnr);
+	chipnr = (int)(offset >> chip->chip_shift);
+	chip->select_chip(mtd, chipnr);
 
 
-	if ((offset & (meminfo->oobblock - 1)) != 0) {
+	if ((offset & (mtd->writesize - 1)) != 0) {
 		printf ("nand_get_lock_status: "
 			"Start address must be beginning of "
 			"nand page!\n");
@@ -776,16 +296,16 @@
 	}
 
 	/* check the Lock Status */
-	page = (int)(offset >> this->page_shift);
-	this->cmdfunc(meminfo, NAND_CMD_LOCK_STATUS, -1, page & this->pagemask);
+	page = (int)(offset >> chip->page_shift);
+	chip->cmdfunc(mtd, NAND_CMD_LOCK_STATUS, -1, page & chip->pagemask);
 
-	ret = this->read_byte(meminfo) & (NAND_LOCK_STATUS_TIGHT
+	ret = chip->read_byte(mtd) & (NAND_LOCK_STATUS_TIGHT
 					  | NAND_LOCK_STATUS_LOCK
 					  | NAND_LOCK_STATUS_UNLOCK);
 
  out:
 	/* de-select the NAND device */
-	this->select_chip(meminfo, -1);
+	chip->select_chip(mtd, -1);
 	return ret;
 }
 
@@ -793,59 +313,65 @@
  * nand_unlock: - Unlock area of NAND pages
  *		  only one consecutive area can be unlocked at one time!
  *
- * @param meminfo	nand mtd instance
+ * @param mtd		nand mtd instance
  * @param start		start byte address
  * @param length	number of bytes to unlock (must be a multiple of
- *			page size nand->oobblock)
+ *			page size nand->writesize)
  *
  * @return		0 on success, -1 in case of error
  */
-int nand_unlock(nand_info_t *meminfo, ulong start, ulong length)
+int nand_unlock(struct mtd_info *mtd, ulong start, ulong length)
 {
 	int ret = 0;
 	int chipnr;
 	int status;
 	int page;
-	struct nand_chip *this = meminfo->priv;
+	struct nand_chip *chip = mtd->priv;
 	printf ("nand_unlock: start: %08x, length: %d!\n",
 		(int)start, (int)length);
 
 	/* select the NAND device */
-	chipnr = (int)(start >> this->chip_shift);
-	this->select_chip(meminfo, chipnr);
+	chipnr = (int)(start >> chip->chip_shift);
+	chip->select_chip(mtd, chipnr);
 
 	/* check the WP bit */
-	this->cmdfunc(meminfo, NAND_CMD_STATUS, -1, -1);
-	if ((this->read_byte(meminfo) & 0x80) == 0) {
+	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+	if (!(chip->read_byte(mtd) & NAND_STATUS_WP)) {
 		printf ("nand_unlock: Device is write protected!\n");
 		ret = -1;
 		goto out;
 	}
 
-	if ((start & (meminfo->oobblock - 1)) != 0) {
+	if ((start & (mtd->erasesize - 1)) != 0) {
 		printf ("nand_unlock: Start address must be beginning of "
-			"nand page!\n");
+			"nand block!\n");
 		ret = -1;
 		goto out;
 	}
 
-	if (length == 0 || (length & (meminfo->oobblock - 1)) != 0) {
-		printf ("nand_unlock: Length must be a multiple of nand page "
-			"size!\n");
+	if (length == 0 || (length & (mtd->erasesize - 1)) != 0) {
+		printf ("nand_unlock: Length must be a multiple of nand block "
+			"size %08x!\n", mtd->erasesize);
 		ret = -1;
 		goto out;
 	}
 
+	/*
+	 * Set length so that the last address is set to the
+	 * starting address of the last block
+	 */
+	length -= mtd->erasesize;
+
 	/* submit address of first page to unlock */
-	page = (int)(start >> this->page_shift);
-	this->cmdfunc(meminfo, NAND_CMD_UNLOCK1, -1, page & this->pagemask);
+	page = (int)(start >> chip->page_shift);
+	chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 
 	/* submit ADDRESS of LAST page to unlock */
-	page += (int)(length >> this->page_shift) - 1;
-	this->cmdfunc(meminfo, NAND_CMD_UNLOCK2, -1, page & this->pagemask);
+	page += (int)(length >> chip->page_shift);
+	chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, page & chip->pagemask);
 
 	/* call wait ready function */
-	status = this->waitfunc(meminfo, this, FL_WRITING);
+	status = chip->waitfunc(mtd, chip);
 	/* see if device thinks it succeeded */
 	if (status & 0x01) {
 		/* there was an error */
@@ -855,8 +381,301 @@
 
  out:
 	/* de-select the NAND device */
-	this->select_chip(meminfo, -1);
+	chip->select_chip(mtd, -1);
+	return ret;
+}
+#endif
+
+/**
+ * check_skip_len
+ *
+ * Check if there are any bad blocks, and whether length including bad
+ * blocks fits into device
+ *
+ * @param nand NAND device
+ * @param offset offset in flash
+ * @param length image length
+ * @return 0 if the image fits and there are no bad blocks
+ *         1 if the image fits, but there are bad blocks
+ *        -1 if the image does not fit
+ */
+static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length)
+{
+	size_t len_excl_bad = 0;
+	int ret = 0;
+
+	while (len_excl_bad < length) {
+		size_t block_len, block_off;
+		loff_t block_start;
+
+		if (offset >= nand->size)
+			return -1;
+
+		block_start = offset & ~(loff_t)(nand->erasesize - 1);
+		block_off = offset & (nand->erasesize - 1);
+		block_len = nand->erasesize - block_off;
+
+		if (!nand_block_isbad(nand, block_start))
+			len_excl_bad += block_len;
+		else
+			ret = 1;
+
+		offset += block_len;
+	}
+
 	return ret;
 }
 
-#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) */
+#ifdef CONFIG_CMD_NAND_TRIMFFS
+static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
+			const size_t *len)
+{
+	size_t i, l = *len;
+
+	for (i = l - 1; i >= 0; i--)
+		if (buf[i] != 0xFF)
+			break;
+
+	/* The resulting length must be aligned to the minimum flash I/O size */
+	l = i + 1;
+	l = (l + nand->writesize - 1) / nand->writesize;
+	l *=  nand->writesize;
+
+	/*
+	 * since the input length may be unaligned, prevent access past the end
+	 * of the buffer
+	 */
+	return min(l, *len);
+}
+#endif
+
+/**
+ * nand_write_skip_bad:
+ *
+ * Write image to NAND flash.
+ * Blocks that are marked bad are skipped and the is written to the next
+ * block instead as long as the image is short enough to fit even after
+ * skipping the bad blocks.
+ *
+ * @param nand  	NAND device
+ * @param offset	offset in flash
+ * @param length	buffer length
+ * @param buffer        buffer to read from
+ * @param flags		flags modifying the behaviour of the write to NAND
+ * @return		0 in case of success
+ */
+int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
+			u_char *buffer, int flags)
+{
+	int rval = 0, blocksize;
+	size_t left_to_write = *length;
+	u_char *p_buffer = buffer;
+	int need_skip;
+
+#ifdef CONFIG_CMD_NAND_YAFFS
+	if (flags & WITH_YAFFS_OOB) {
+		if (flags & ~WITH_YAFFS_OOB)
+			return -EINVAL;
+
+		int pages;
+		pages = nand->erasesize / nand->writesize;
+		blocksize = (pages * nand->oobsize) + nand->erasesize;
+		if (*length % (nand->writesize + nand->oobsize)) {
+			printf ("Attempt to write incomplete page"
+				" in yaffs mode\n");
+			return -EINVAL;
+		}
+	} else
+#endif
+	{
+		blocksize = nand->erasesize;
+	}
+
+	/*
+	 * nand_write() handles unaligned, partial page writes.
+	 *
+	 * We allow length to be unaligned, for convenience in
+	 * using the $filesize variable.
+	 *
+	 * However, starting at an unaligned offset makes the
+	 * semantics of bad block skipping ambiguous (really,
+	 * you should only start a block skipping access at a
+	 * partition boundary).  So don't try to handle that.
+	 */
+	if ((offset & (nand->writesize - 1)) != 0) {
+		printf ("Attempt to write non page aligned data\n");
+		*length = 0;
+		return -EINVAL;
+	}
+
+	need_skip = check_skip_len(nand, offset, *length);
+	if (need_skip < 0) {
+		printf ("Attempt to write outside the flash area\n");
+		*length = 0;
+		return -EINVAL;
+	}
+
+	if (!need_skip && !(flags & WITH_DROP_FFS)) {
+		rval = nand_write (nand, offset, length, buffer);
+		if (rval == 0)
+			return 0;
+
+		*length = 0;
+		printf ("NAND write to offset %llx failed %d\n",
+			offset, rval);
+		return rval;
+	}
+
+	while (left_to_write > 0) {
+		size_t block_offset = offset & (nand->erasesize - 1);
+		size_t write_size, truncated_write_size;
+
+		WATCHDOG_RESET ();
+
+		if (nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) {
+			printf ("Skip bad block 0x%08llx\n",
+				offset & ~(nand->erasesize - 1));
+			offset += nand->erasesize - block_offset;
+			continue;
+		}
+
+		if (left_to_write < (blocksize - block_offset))
+			write_size = left_to_write;
+		else
+			write_size = blocksize - block_offset;
+
+#ifdef CONFIG_CMD_NAND_YAFFS
+		if (flags & WITH_YAFFS_OOB) {
+			int page, pages;
+			size_t pagesize = nand->writesize;
+			size_t pagesize_oob = pagesize + nand->oobsize;
+			struct mtd_oob_ops ops;
+
+			ops.len = pagesize;
+			ops.ooblen = nand->oobsize;
+			ops.mode = MTD_OOB_AUTO;
+			ops.ooboffs = 0;
+
+			pages = write_size / pagesize_oob;
+			for (page = 0; page < pages; page++) {
+				WATCHDOG_RESET();
+
+				ops.datbuf = p_buffer;
+				ops.oobbuf = ops.datbuf + pagesize;
+
+				rval = nand->write_oob(nand, offset, &ops);
+				if (rval != 0)
+					break;
+
+				offset += pagesize;
+				p_buffer += pagesize_oob;
+			}
+		}
+		else
+#endif
+		{
+			truncated_write_size = write_size;
+#ifdef CONFIG_CMD_NAND_TRIMFFS
+			if (flags & WITH_DROP_FFS)
+				truncated_write_size = drop_ffs(nand, p_buffer,
+						&write_size);
+#endif
+
+			rval = nand_write(nand, offset, &truncated_write_size,
+					p_buffer);
+			offset += write_size;
+			p_buffer += write_size;
+		}
+
+		if (rval != 0) {
+			printf ("NAND write to offset %llx failed %d\n",
+				offset, rval);
+			*length -= left_to_write;
+			return rval;
+		}
+
+		left_to_write -= write_size;
+	}
+
+	return 0;
+}
+
+/**
+ * nand_read_skip_bad:
+ *
+ * Read image from NAND flash.
+ * Blocks that are marked bad are skipped and the next block is readen
+ * instead as long as the image is short enough to fit even after skipping the
+ * bad blocks.
+ *
+ * @param nand NAND device
+ * @param offset offset in flash
+ * @param length buffer length, on return holds remaining bytes to read
+ * @param buffer buffer to write to
+ * @return 0 in case of success
+ */
+int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
+		       u_char *buffer)
+{
+	int rval;
+	size_t left_to_read = *length;
+	u_char *p_buffer = buffer;
+	int need_skip;
+
+	if ((offset & (nand->writesize - 1)) != 0) {
+		printf ("Attempt to read non page aligned data\n");
+		*length = 0;
+		return -EINVAL;
+	}
+
+	need_skip = check_skip_len(nand, offset, *length);
+	if (need_skip < 0) {
+		printf ("Attempt to read outside the flash area\n");
+		*length = 0;
+		return -EINVAL;
+	}
+
+	if (!need_skip) {
+		rval = nand_read (nand, offset, length, buffer);
+		if (!rval || rval == -EUCLEAN)
+			return 0;
+
+		*length = 0;
+		printf ("NAND read from offset %llx failed %d\n",
+			offset, rval);
+		return rval;
+	}
+
+	while (left_to_read > 0) {
+		size_t block_offset = offset & (nand->erasesize - 1);
+		size_t read_length;
+
+		WATCHDOG_RESET ();
+
+		if (nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) {
+			printf ("Skipping bad block 0x%08llx\n",
+				offset & ~(nand->erasesize - 1));
+			offset += nand->erasesize - block_offset;
+			continue;
+		}
+
+		if (left_to_read < (nand->erasesize - block_offset))
+			read_length = left_to_read;
+		else
+			read_length = nand->erasesize - block_offset;
+
+		rval = nand_read (nand, offset, &read_length, p_buffer);
+		if (rval && rval != -EUCLEAN) {
+			printf ("NAND read from offset %llx failed %d\n",
+				offset, rval);
+			*length -= left_to_read;
+			return rval;
+		}
+
+		left_to_read -= read_length;
+		offset       += read_length;
+		p_buffer     += read_length;
+	}
+
+	return 0;
+}

fs/jffs2/jffs2_1pass.c

diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index 41ff4c1..42d56a2 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -143,6 +143,12 @@
 /* keeps pointer to currentlu processed partition */
 static struct part_info *current_part;
 
+u32 uimage_inode = 0;
+u32 uimage_version = 0;
+u32 uimage_size = 0;
+static u32 jffs2_1pass_scan_kernel(struct part_info * part,  u32 pino);
+static u32 jffs2_1pass_load_kernel(struct part_info * part, char *dest);
+
 #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
 #if defined(CFG_NAND_LEGACY)
 #include <linux/mtd/nand_legacy.h>
@@ -284,7 +290,74 @@
  * NOR flash memory is mapped in processor's address space,
  * just return address.
  */
-static inline void *get_fl_mem_nor(u32 off)
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+
+extern void board_map(flash_info_t *info, unsigned long addr);
+
+static void *get_fl_mem_nor(u32 off, u32 size, void *ext_buf)
+{
+	u32 addr = off;
+	struct mtdids *id = current_part->dev->id;
+	extern flash_info_t flash_info[];
+	flash_info_t *flash = &flash_info[id->num];
+        u_char *buf = ext_buf ? (u_char*)ext_buf : (u_char*)malloc(size);
+
+        if (buf == NULL) {
+            printf("get_fl_mem_nor: can't alloc %d bytes\n", size);
+            return NULL;
+        }
+        
+	addr += flash->start[0];
+        
+	board_map(flash, addr);
+
+        if ((off < 0x800000) && ((off + size) > 0x800000)) {
+            unsigned long len = 0x800000 - off;
+            
+            memcpy(buf, (void *)addr, len);
+            
+            board_map(flash, addr+len);
+            memcpy(buf + len, (void *)addr + len, size - len);
+        } else {
+            memcpy(buf, (void *)addr, size);
+        }
+
+        return buf;
+}
+
+static void *get_node_mem_nor(u32 off)
+{
+    struct jffs2_unknown_node node;
+    void *ret = NULL;
+    int len;
+
+    if (NULL == get_fl_mem_nor(off, sizeof(node), &node))
+        return NULL;
+    
+    if (node.magic == JFFS2_MAGIC_BITMASK) {
+        if (hdr_crc(&node))
+            len = node.totlen;
+        else
+            return NULL;
+    } else
+        len = sizeof(node);
+    
+    if (!(ret = get_fl_mem_nor(off, len, NULL))) {
+        printf("off = %#x magic %#x type %#x node.totlen = %d\n",
+               off, node.magic, node.nodetype, node.totlen);
+    }
+
+    return ret;
+}
+
+static inline void put_fl_mem_nor(void *buf)
+{
+        if (buf)
+            free(buf);
+}
+#else
+
+static inline void *get_fl_mem_nor(u32 off, u32 size, void *ext_buf)
 {
 	u32 addr = off;
 	struct mtdids *id = current_part->dev->id;
@@ -298,8 +371,14 @@
 
 static inline void *get_node_mem_nor(u32 off)
 {
-	return (void*)get_fl_mem_nor(off);
+	return (void*)get_fl_mem_nor(off, 0, NULL);
 }
+
+static inline void put_fl_mem_nor(void *buf)
+{
+	return;
+}
+#endif /* CFG_FLASH_COMPLEX_MAPPINGS */
 #endif /* #if (CONFIG_COMMANDS & CFG_CMD_FLASH) */
 
 
@@ -313,7 +392,7 @@
 
 #if (CONFIG_COMMANDS & CFG_CMD_FLASH)
 	if (id->type == MTD_DEV_TYPE_NOR)
-		return get_fl_mem_nor(off);
+		return get_fl_mem_nor(off, size, ext_buf);
 #endif
 
 #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
@@ -345,9 +424,14 @@
 
 static inline void put_fl_mem(void *buf)
 {
-#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
 	struct mtdids *id = current_part->dev->id;
 
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+	if (id->type == MTD_DEV_TYPE_NOR)
+		return put_fl_mem_nor(buf);
+#endif
+
+#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND)
 	if (id->type == MTD_DEV_TYPE_NAND)
 		return put_fl_mem_nand(buf);
 #endif
@@ -1190,7 +1274,7 @@
 		}
 
 		node = (struct jffs2_unknown_node *) get_node_mem((u32)part->offset + offset);
-		if (node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) {
+		if (node && node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) {
 			/* if its a fragment add it */
 			if (node->nodetype == JFFS2_NODETYPE_INODE &&
 				    inode_crc((struct jffs2_raw_inode *) node) &&
@@ -1228,7 +1312,7 @@
 			}
 			offset += ((node->totlen + 3) & ~3);
 			counterF++;
-		} else if (node->magic == JFFS2_EMPTY_BITMASK &&
+		} else if (node && node->magic == JFFS2_EMPTY_BITMASK &&
 			   node->nodetype == JFFS2_EMPTY_BITMASK) {
 			offset = jffs2_scan_empty(offset, part);
 		} else {	/* if we know nothing, we just step and look. */
@@ -1236,7 +1320,7 @@
 			counter4++;
 		}
 /*             printf("unknown node magic %4.4x %4.4x @ %lx\n", node->magic, node->nodetype, (unsigned long)node); */
-		put_fl_mem(node);
+                put_fl_mem(node);
 	}
 
 	putstr("\b\b done.\r\n");		/* close off the dots */
@@ -1334,7 +1418,201 @@
 
 	return ret;
 }
+/* This function search for kernel in /boot/uImage. If the kernel is with different name and location then
+disable this function and use full scanning by setting the env variable "fullscan" to 1. */
+static u32
+jffs2_1pass_scan_kernel(struct part_info * part,  u32 pino)
+{
+    struct b_lists *pL;
+    struct jffs2_unknown_node *node;
+    u32 offset, oldoffset = 0;
+    u32 max = part->size - sizeof(struct jffs2_raw_inode);
+    u32 counter = 0;
+    u32 counter4 = 0;
+    u32 counterF = 0;
+    u32 counterN = 0;
+    u32 boot_inode = 0;
+    u32 boot_version = 0;
+    u32 len = 0;
 
+    int ctotsize = 0;
+    int dtotsize = 0;
+
+    struct jffs2_raw_dirent *jDir;
+    struct jffs2_raw_inode *jNode;
+
+    struct mtdids *id = current_part->dev->id;
+
+    /* copy requested part_info struct pointer to global location */
+    current_part = part;
+
+    /* if we are building a list we need to refresh the cache. */
+    jffs2_1pass_rescan_needed(part);
+    jffs_init_1pass_list(part);
+    pL = (struct b_lists *)part->jffs2_priv;
+    offset = 0;
+    len = strlen("boot");
+    puts ("Scanning JFFS2 FS for uImage:   ");
+
+    /* start at the beginning of the partition */
+    while (offset < max) {
+        node = (struct jffs2_unknown_node *) get_node_mem((u32)part->offset + offset);
+        if (node && node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) {
+            /* if its a fragment add it */
+            if (node->nodetype == JFFS2_NODETYPE_INODE &&
+                    inode_crc((struct jffs2_raw_inode *) node) &&
+                    data_crc((struct jffs2_raw_inode *) node) ) {
+                jNode = (struct jffs2_raw_inode *) node;
+                if(uimage_inode == jNode->ino)
+                {
+                    if (insert_node(&pL->frag, (u32) part->offset + offset) == NULL) {
+                        put_fl_mem(node);
+                        return 0;
+                    }
+                    uimage_size = jNode->isize;
+                    //ctotsize += jNode->csize;
+                    dtotsize += jNode->dsize;
+                }
+            } else if (node->nodetype == JFFS2_NODETYPE_DIRENT &&
+                    dirent_crc((struct jffs2_raw_dirent *) node)  &&
+                    dirent_name_crc((struct jffs2_raw_dirent *) node)) {
+                if (! (counterN%100))
+                    ;//puts ("\b\b.  ");
+                jDir = (struct jffs2_raw_dirent *)node;
+                if ((pino == jDir->pino) && (len == jDir->nsize) &&
+                        (jDir->ino) &&  /* 0 for unlink */
+                        (!strncmp((char *)jDir->name, "boot", len))) {    /* a match for directory 'boot'*/
+                    if (jDir->version < boot_version) {
+                        put_fl_mem(jDir);
+                        continue;
+                    }
+                    boot_inode = jDir->ino;
+                    boot_version = jDir->version;
+                }
+                if (boot_inode && (boot_inode == jDir->pino) &&
+                        (jDir->ino) &&  /* 0 for unlink */
+                        (!strncmp((char *)jDir->name, "uImage", strlen("uImage")))) {    /* a match for directory entry 'uImage'*/
+                    if (jDir->version < uimage_version) {
+                        put_fl_mem(jDir);
+                        continue;
+                    }
+                    uimage_inode = jDir->ino;
+                    uimage_version = jDir->version;
+                    printf("...uImage Found\n");
+                }
+
+            } else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) {
+                if (node->totlen != sizeof(struct jffs2_unknown_node))
+                    printf("OOPS Cleanmarker has bad size "
+                        "%d != %d\n", node->totlen,
+                        sizeof(struct jffs2_unknown_node));
+            } else if (node->nodetype == JFFS2_NODETYPE_PADDING) {
+                if (node->totlen < sizeof(struct jffs2_unknown_node))
+                    printf("OOPS Padding has bad size "
+                        "%d < %d\n", node->totlen,
+                        sizeof(struct jffs2_unknown_node));
+            } else {
+                printf("Unknown node type: %x len %d "
+                    "offset 0x%x\n", node->nodetype,
+                    node->totlen, offset);
+            }
+            offset += ((node->totlen + 3) & ~3);
+            counterF++;
+        } else if (node && node->magic == JFFS2_EMPTY_BITMASK &&
+               node->nodetype == JFFS2_EMPTY_BITMASK) {
+            offset = jffs2_scan_empty(offset, part);
+        } else {    /* if we know nothing, we just step and look. */
+            offset += 4;
+            counter4++;
+        }
+/*             printf("unknown node magic %4.4x %4.4x @ %lx\n", node->magic, node->nodetype, (unsigned long)node); */
+                put_fl_mem(node);
+                if(dtotsize && uimage_size && (dtotsize == uimage_size))
+                {
+                    //printf("ctotsize = %d dtotsize = %d uimage_size = %d\n uImage Read Done\n",ctotsize,dtotsize,uimage_size);
+                    printf("...uImage Read Done\n");
+                    return 1;
+                }
+    }
+
+    printf("...uImage Not Found\n");
+
+    return 0;
+}
+
+static u32
+jffs2_1pass_load_kernel(struct part_info * part, char *dest)
+{
+    struct jffs2_raw_inode *jNode;
+    u32 latestVersion = 0;
+    uchar *lDest;
+    uchar *src;
+    long ret;
+    int i=0;
+    struct b_node *b;
+    struct b_lists *pL = (struct b_lists *)part->jffs2_priv;
+    printf("Loading kernel to address 0x%lx\n",(unsigned long) dest);
+    for (b = pL->frag.listHead; b != NULL; b = b->next) {
+        jNode = (struct jffs2_raw_inode *) get_node_mem(b->offset);
+        src = ((uchar *) jNode) + sizeof(struct jffs2_raw_inode);
+        /* ignore data behind latest known EOF */
+        if (jNode->offset > uimage_size) {
+            put_fl_mem(jNode);
+            continue;
+        }
+        i++;
+        lDest = (uchar *) (dest + jNode->offset);
+        switch (jNode->compr) {
+            case JFFS2_COMPR_NONE:
+                ret = (unsigned long) ldr_memcpy(lDest, src, jNode->dsize);
+                break;
+            case JFFS2_COMPR_ZERO:
+                ret = 0;
+                for (i = 0; i < jNode->dsize; i++)
+                    *(lDest++) = 0;
+                break;
+            case JFFS2_COMPR_RTIME:
+                ret = 0;
+                rtime_decompress(src, lDest, jNode->csize, jNode->dsize);
+                break;
+            case JFFS2_COMPR_DYNRUBIN:
+                /* this is slow but it works */
+                ret = 0;
+                dynrubin_decompress(src, lDest, jNode->csize, jNode->dsize);
+                break;
+            case JFFS2_COMPR_ZLIB:
+                ret = zlib_decompress(src, lDest, jNode->csize, jNode->dsize);
+                break;
+#if defined(CONFIG_JFFS2_LZO_LZARI)
+            case JFFS2_COMPR_LZO:
+                ret = lzo_decompress(src, lDest, jNode->csize, jNode->dsize);
+                break;
+            case JFFS2_COMPR_LZARI:
+                ret = lzari_decompress(src, lDest, jNode->csize, jNode->dsize);
+                break;
+#endif
+            default:
+                /* unknown */
+                putLabeledWord("UNKOWN COMPRESSION METHOD = ", jNode->compr);
+                put_fl_mem(jNode);
+                return -1;
+                break;
+        }
+        put_fl_mem(jNode);
+    }
+}
+
+/* Load the kernel file from flash into memory*/
+u32
+jffs2_1pass_uload(char *dest, struct part_info * part, const char *fname)
+{
+        if (! (jffs2_1pass_scan_kernel(part, 1))) {
+            putstr("scan failed: trying loading using fsload\r\n");
+            return 0;
+        }
+        jffs2_1pass_load_kernel(part, dest);
+        return 1;
+}
 
 /* Load a file from flash into memory. fname can be a full path */
 u32

include/asm-arm/arch-comcerto/bits.h

diff --git a/include/asm-arm/arch-comcerto/bits.h b/include/asm-arm/arch-comcerto/bits.h
new file mode 100644
index 0000000..8522335
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/bits.h
@@ -0,0 +1,48 @@
+/* bits.h
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * This package is free software;  you can redistribute it and/or
+ * modify it under the terms of the license found in the file
+ * named COPYING that should have accompanied this file.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef __bits_h
+#define __bits_h 1
+
+#define BIT0  (1<<0)
+#define BIT1  (1<<1)
+#define BIT2  (1<<2)
+#define BIT3  (1<<3)
+#define BIT4  (1<<4)
+#define BIT5  (1<<5)
+#define BIT6  (1<<6)
+#define BIT7  (1<<7)
+#define BIT8  (1<<8)
+#define BIT9  (1<<9)
+#define BIT10 (1<<10)
+#define BIT11 (1<<11)
+#define BIT12 (1<<12)
+#define BIT13 (1<<13)
+#define BIT14 (1<<14)
+#define BIT15 (1<<15)
+#define BIT16 (1<<16)
+#define BIT17 (1<<17)
+#define BIT18 (1<<18)
+#define BIT19 (1<<19)
+#define BIT20 (1<<20)
+#define BIT21 (1<<21)
+#define BIT22 (1<<22)
+#define BIT23 (1<<23)
+#define BIT24 (1<<24)
+#define BIT25 (1<<25)
+#define BIT26 (1<<26)
+#define BIT27 (1<<27)
+#define BIT28 (1<<28)
+#define BIT29 (1<<29)
+#define BIT30 (1<<30)
+#define BIT31 (1<<31)
+
+#endif

include/asm-arm/arch-comcerto/bsp.h

diff --git a/include/asm-arm/arch-comcerto/bsp.h b/include/asm-arm/arch-comcerto/bsp.h
new file mode 100644
index 0000000..ea3173f
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/bsp.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _BSP_H
+#define _BSP_H
+
+#include <config.h>
+
+#if defined(CONFIG_COMCERTO_530)
+#include "bsp_530.h"
+#elif defined(CONFIG_COMCERTO_515) || defined(CONFIG_COMCERTO_800)
+#include "bsp_515.h"
+#elif defined(CONFIG_COMCERTO_100)
+#include "bsp_100.h"
+#elif defined(CONFIG_COMCERTO_1000)
+#include "bsp_1000.h"
+#elif defined(CONFIG_COMCERTO_2000)
+#include "bsp_2000.h"
+#else
+#error "No architecture selected!!!"
+#endif
+
+
+#endif /* _BSP_H */

include/asm-arm/arch-comcerto/bsp_100.h

diff --git a/include/asm-arm/arch-comcerto/bsp_100.h b/include/asm-arm/arch-comcerto/bsp_100.h
new file mode 100644
index 0000000..95bce01
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/bsp_100.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _BSP_100_H
+#define _BSP_100_H
+
+#include <asm/arch/hardware.h>
+#ifndef __ASSEMBLY__
+#include <asm/byteorder.h>
+#endif
+
+#define GPIO_TYPE_INPUT		0
+#define GPIO_TYPE_OUTPUT	1
+
+#define COMCERTO_PART_MAGIC 0x4D535044
+
+void SoC_Check_Device(void);
+void SoC_APB_setup(void);
+void SoC_AHB_setup(void);
+void SoC_ARAM_setup(void);
+
+void SoC_PLL_init(void);
+void SoC_mem_init(u32 board_config);
+void SoC_nand_init(void);
+u32 get_ddr_size(void);
+void start_training(void);
+
+int SoC_gpio_cfg(int gpio, int mode);
+
+#define SoC_gpio_mask(gpio)		(1 << ((gpio) & 0x1f))
+
+#define SoC_gpio_read(gpiomask)		(__le32_to_cpu(*(volatile u32 *)GPIO_INPUT_REG & (gpiomask)))
+#define SoC_gpio_set_0(gpiomask)	(*(volatile u32 *)GPIO_OUTPUT_REG &= __cpu_to_le32(~(gpiomask)))
+
+#define SoC_gpio_set_1(gpiomask)	(*(volatile u32 *)GPIO_OUTPUT_REG |= __cpu_to_le32((gpiomask)))
+
+
+static inline void HAL_set_arm_clk(u32 fclk)
+{
+	volatile u32 delay_count;
+#ifdef M82134G
+	u32 w = 2; 
+#else
+	u32 w = 1; 
+#endif 
+	u32 x = 0;
+	u32 y = (fclk * ((w + 1) * (x + 1) * 2)) / CFG_REFCLKFREQ;
+
+	// set PLL into BYPASS mode using MUX
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL |= __cpu_to_le32(PLL_CLK_BYPASS);
+	// do an internal PLL bypass
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL |= __cpu_to_le32(ARM_PLL_BY_CTRL);
+	// wait 500us 
+	delay_count = 12000;
+	while (delay_count--);
+	// disable the PLL
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL |= __cpu_to_le32(PLL_DISABLE);
+	// wait 500us 
+	delay_count = 12000;
+	while (delay_count--);
+	// enable the PLL
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL &= __cpu_to_le32(~PLL_DISABLE);
+	// wait 500us 
+	delay_count = 12000;
+	while (delay_count--);
+	// set X, W and X
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL &= __cpu_to_le32(0xFF000000) ;
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL |= __cpu_to_le32((x << 16) + (w << 8) + y);
+	// wait for PLL to lock
+	while( (*(volatile u32 *)CLKCORE_PLL_STATUS & __cpu_to_le32(FCLK_PLL_LOCK)) == 0);
+
+	// remove the internal PLL bypass
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL &= __cpu_to_le32(~ARM_PLL_BY_CTRL);
+	// remove PLL from BYPASS mode using MUX
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL &= __cpu_to_le32(~PLL_CLK_BYPASS);
+
+}
+
+static inline int HAL_get_arm_clk(void)
+{
+	u32 w;
+	u32 x;
+	u32 y ;
+	u32 reg;
+
+	reg = __le32_to_cpu(*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL);
+	x = (reg & 0x0001F0000) >> 16;
+	y = (reg & 0x00000007F);
+	w = (reg & 0x000000300) >> 8;
+
+	return (CFG_REFCLKFREQ * y /((w + 1) * (x + 1) * 2));
+}
+
+static inline void HAL_set_amba_clk(u32 fclk)
+{
+	volatile u32 delay_count;
+	u32 w = 1;
+	u32 x = 1;
+	u32 y = (fclk *((w + 1) * (x + 1) * 2)) / CFG_REFCLKFREQ;
+
+	// set PLL into BYPASS mode using MUX
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL |= __cpu_to_le32(PLL_CLK_BYPASS);
+	// do an internal PLL bypass
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL |= __cpu_to_le32(AHB_PLL_BY_CTRL);
+	// wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
+	delay_count = 12000;
+	while (delay_count--);
+	// disable the PLL
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL |= __cpu_to_le32(PLL_DISABLE);
+	// wait 500us 
+	delay_count = 12000;
+	while (delay_count--);
+	// enable the PLL
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL &= __cpu_to_le32(~PLL_DISABLE);
+	// wait 500us 
+	delay_count = 12000;
+	while (delay_count--);
+	// set X, W and X
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL &= __cpu_to_le32(0xFF000000) ;
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL |= __cpu_to_le32((x << 16) + (w << 8) + y);
+	// wait for PLL to lock
+	while( (*(volatile u32 *)CLKCORE_PLL_STATUS & __cpu_to_le32(AHBCLK_PLL_LOCK)) == 0);
+
+	// remove the internal PLL bypass
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL &= __cpu_to_le32(~AHB_PLL_BY_CTRL);
+	// remove PLL from BYPASS mode using MUX
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL &= __cpu_to_le32(~PLL_CLK_BYPASS);
+}
+
+
+
+static inline int HAL_get_amba_clk(void)
+{
+	u32 w;
+	u32 x;
+	u32 y ;
+	u32 reg;
+
+	reg = __le32_to_cpu(*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL);
+	x = (reg & 0x0001F0000) >> 16;
+	y = (reg & 0x00000007F) ;
+	w = (reg & 0x000000300) >> 8;
+	return (CFG_REFCLKFREQ * y / ((w + 1) * (x + 1) * 2));
+}
+
+
+#endif /* _BSP_100_H */

include/asm-arm/arch-comcerto/bsp_1000.h

diff --git a/include/asm-arm/arch-comcerto/bsp_1000.h b/include/asm-arm/arch-comcerto/bsp_1000.h
new file mode 100644
index 0000000..e59fd81
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/bsp_1000.h
@@ -0,0 +1,618 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _BSP_1000_H
+#define _BSP_1000_H
+
+#include <asm/arch/hardware.h>
+#ifndef __ASSEMBLY__
+#include <asm/byteorder.h>
+#endif
+
+#define GPIO_TYPE_INPUT		0
+#define GPIO_TYPE_OUTPUT	1
+
+#define COMCERTO_PART_MAGIC 0x4D535044
+
+void SoC_Check_Device(void);
+void SoC_APB_setup(void);
+void SoC_AHB_setup(void);
+void SoC_ARAM_setup(void);
+
+void SoC_PLL_init(int n);
+void SoC_nand_init(void);
+u32 get_ddr_size(void);
+void start_training(void);
+
+int SoC_gpio_cfg(int gpio, int mode);
+
+#define SoC_gpio_mask(gpio)		(1 << ((gpio) & 0x1f))
+
+#define SoC_gpio_read(gpiomask)		(__le32_to_cpu(*(volatile u32 *)GPIO_INPUT_REG & (gpiomask)))
+#define SoC_gpio_set_0(gpiomask)	(*(volatile u32 *)GPIO_OUTPUT_REG &= __cpu_to_le32(~(gpiomask)))
+
+#define SoC_gpio_set_1(gpiomask)	(*(volatile u32 *)GPIO_OUTPUT_REG |= __cpu_to_le32((gpiomask)))
+
+static inline u32 HAL_get_ahb_clk(void);
+
+extern u32 CFG_HZ_CLOCK;
+
+struct c1000_cfg_clk {
+	u32 arm_pll;
+	u32 arm_pll_nr;
+	u32 arm_pll_od;
+
+	u32 ahb_pll;
+	u32 ahb_pll_nr;
+	u32 ahb_pll_od;
+
+	u32 phy_pll;
+	u32 phy_pll_nr;
+	u32 phy_pll_od;
+
+	int arm_from_sclk2;
+
+	u32 arm_clk;
+
+	int ddr_from_fclk;
+
+	u32 ahb_clk;
+	u32 ddr_clk;
+	u32 ipsec_clk;
+};
+
+#define CFG_CLK_650_187_375 0
+#define CFG_CLK_600_165_330 1
+#define CFG_CLK_534_178_330 2
+#define CFG_CLK_450_165_330 3
+#define CFG_CLK_400_165_330 4
+#define CFG_CLK_650_200_200 5
+#define CFG_CLK_650_187_325 6
+#define CFG_CLK_610_186_372 7
+
+static inline void HAL_set_arm_pll(u32 fclk, u32 NR, u32 OD)
+{
+	volatile u32 delay_count;
+	u32 NF;
+	u32 NB;
+	u32 ref_clk = CFG_REFCLKFREQ / 1000000;
+
+	fclk = fclk / 1000000; 
+	NF = (fclk * NR * OD) / ref_clk;
+
+	NB = (NF * 2) / 5;
+
+	NR--;OD--;NF--;NB--;
+
+#if 0
+	//power up PLL
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL &= ~ARM_CLK_CNTRL_PLL_PWDN;
+
+	//set PLL into reset mode
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 |= ARM_CLK_CNTRL2_PLL_RESET;
+#endif
+
+	// set NR / NF
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL &= __cpu_to_le32(0xFFC0E000);
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL |= __cpu_to_le32((NR << 16) + NF);
+	// set OD and NB (NB=NF/2.5)
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 &= __cpu_to_le32(0x8000FFFF);
+        *(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 |= __cpu_to_le32((OD << 28) + (NB << 16));
+
+	//wait 5 uS.... looks like it is one cycle...
+	delay_count = 12000;
+//	while (delay_count--);
+
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 &= __cpu_to_le32(~ARM_CLK_CNTRL2_PLL_RESET);
+
+	//wait 21 uS.... looks like it is one cycle...
+	delay_count = 10;
+	while (delay_count--);
+
+	//clear status bit 
+	do {
+		*(volatile u32 *)CLKCORE_PLL_STATUS &= __cpu_to_le32(~PLL_STATUS_ARM_PLL_STATUS_CLEAR);	
+		delay_count = 20;
+		while (delay_count--);
+	} while ((*(volatile u32 *)CLKCORE_PLL_STATUS & __cpu_to_le32(PLL_STATUS_ARM_PLL_STATUS)));
+}
+
+static inline u32 HAL_get_arm_pll(void)
+{
+	u32 NR;
+	u32 OD;
+	u32 NF;
+	u32 ref_clk = CFG_REFCLKFREQ / 1000000;
+	u32 reg = __le32_to_cpu(*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL);
+	NR = (reg & 0x003F0000) >> 16;
+	NF = (reg & 0x00001FFF);
+	reg = __le32_to_cpu(*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2);
+	OD = (reg & 0x70000000) >> 28;
+
+	return ( ref_clk * (NF + 1) / (NR  + 1) / (OD  + 1) ) * 1000000;
+}
+
+static inline u32 HAL_get_ahb_pll(void)
+{
+	u32 NR;
+	u32 OD;
+	u32 NF;
+	u32 ref_clk = CFG_REFCLKFREQ / 1000000;
+	u32 reg = __le32_to_cpu(*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL);
+
+	NR = (reg & 0x003F0000) >> 16;
+	NF = (reg & 0x00001FFF);
+	reg = __le32_to_cpu(*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2);
+	OD = (reg & 0x70000000) >> 28;
+
+	return ( ref_clk * (NF + 1) / (NR  + 1) / (OD  + 1) ) * 1000000;
+}
+
+static inline void HAL_set_arm_clk(u32 arm0_clk, u32 arm1_clk, int arm_from_sclk2)
+{
+/*	
+ *	This is new in C1000; you can set different clock for ARM0 and ARM1	
+ *	In u-boot ARM1 is under reset. We will not configure the ARM1_FCLK. It will be set in by-pass mode.
+ */
+	u32 pll;
+
+	if (arm_from_sclk2)
+		pll = HAL_get_ahb_pll();
+	else
+		pll = HAL_get_arm_pll();
+
+//setup arm0 clock
+	if(arm0_clk == pll)
+	{
+		*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 |= __cpu_to_le32(ARM_CLK_CNTRL2_ARM0_DIV_BYPASS);	
+	}
+	else
+	{
+		u32 div0 = pll / arm0_clk;
+
+		*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 &= __cpu_to_le32(0xFFFFFFF0);
+		// ARM0_FCLK = FCLK / div
+		*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 |= __cpu_to_le32(div0 & 0xF);
+		*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 &= __cpu_to_le32(~ARM_CLK_CNTRL2_ARM0_DIV_BYPASS);
+	}
+//setup arm1 clock
+	if(arm1_clk == pll)
+	{
+		*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 |= __cpu_to_le32(ARM_CLK_CNTRL2_ARM1_DIV_BYPASS);	
+	}
+	else
+	{
+		u32 div1 = pll / arm1_clk;
+
+		*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 &= __cpu_to_le32(0xFFFFF0FF);
+		// ARM0_FCLK = FCLK / div
+		*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 |= __cpu_to_le32((div1 & 0xF) << 8);
+		*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 &= __cpu_to_le32(~ARM_CLK_CNTRL2_ARM1_DIV_BYPASS);
+	}
+
+	if (arm_from_sclk2)
+        	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 |= __cpu_to_le32((ARM_CLK_CNTRL2_ARM0_AHB_BYPASS | ARM_CLK_CNTRL2_ARM1_AHB_BYPASS));
+	else
+		*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 &= __cpu_to_le32(~(ARM_CLK_CNTRL2_ARM0_AHB_BYPASS | ARM_CLK_CNTRL2_ARM1_AHB_BYPASS));
+}
+
+static inline u32 HAL_get_arm0_clk(void)
+{
+	u32 mode = __le32_to_cpu(*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2);
+	u32 pll;
+
+	if (mode & ARM_CLK_CNTRL2_ARM0_AHB_BYPASS)
+		pll = HAL_get_ahb_pll();
+	else
+		pll =  HAL_get_arm_pll();
+
+	if (mode & ARM_CLK_CNTRL2_ARM0_DIV_BYPASS)
+	{
+		return pll;
+	}
+	else
+	{
+		u32 div = mode & 0xf;
+
+		return pll / div;
+	}
+}
+
+static inline u32 HAL_get_arm1_clk(void)
+{
+	u32 mode = __le32_to_cpu(*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2);
+	u32 pll;
+
+	if (mode & ARM_CLK_CNTRL2_ARM1_AHB_BYPASS)
+		pll = HAL_get_ahb_pll();
+	else
+		pll = HAL_get_arm_pll();
+
+	if (mode & ARM_CLK_CNTRL2_ARM1_DIV_BYPASS)
+	{
+		return pll;
+	}
+	else
+	{
+		u32 div = (mode >> 8) & 0xf;
+
+		return pll / div;
+	}
+}
+
+
+static inline void HAL_set_ahb_pll(u32 sclk, u32 NR, u32 OD)
+{
+	volatile u32 delay_count;
+	u32 NF;
+        u32 NB;
+	u32 ref_clk = CFG_REFCLKFREQ / 1000000;
+
+	sclk = sclk / 1000000; 
+	NF = (sclk * NR * OD) / ref_clk;
+
+	NB = (NF * 2) / 5;
+	
+	NR--;OD--;NF--;NB--;
+#if 0	
+	//power up PLL
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL &= ~AHB_CLK_CNTRL_PLL_PWDN;
+
+	//set PLL into reset mode
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 |= AHB_CLK_CNTRL2_PLL_RESET;
+#endif
+
+	// set NR / NF
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL &= __cpu_to_le32(0xFFC0E000);
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL |= __cpu_to_le32((NR << 16) + NF);
+	// set OD and NB (NB=NF/2.5)
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 &= __cpu_to_le32(0x8000FFFF);
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 |= __cpu_to_le32((OD << 28) + (NB << 16));
+
+	//wait 5 uS.... looks like it is one cycle...
+	delay_count = 12000;
+//	while (delay_count--);	
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 &= __cpu_to_le32(~AHB_CLK_CNTRL2_PLL_RESET);
+	
+	//wait 21 uS.... looks like it is one cycle...
+	delay_count = 600;
+//	while (delay_count--);	
+//clear status bit 
+	do {
+		*(volatile u32 *)CLKCORE_PLL_STATUS &= __cpu_to_le32(~PLL_STATUS_AHB_PLL_STATUS_CLEAR);	
+		delay_count = 600;
+		while (delay_count--);
+	} while ((*(volatile u32 *)CLKCORE_PLL_STATUS & __cpu_to_le32(PLL_STATUS_AHB_PLL_STATUS)));
+	
+}
+
+static inline u32 HAL_get_ahb_clk(void)
+{
+	u32 sync_mode = __le32_to_cpu(*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL);
+	
+	if (sync_mode & AHB_CLK_CNTRL_SYNC_MODE)
+	{//sync mode ahb is sync with fclk
+		u32 arm_pll = HAL_get_arm_pll();
+
+		if (sync_mode & AHB_CLK_CNTRL_SYNC_DIV_BYPASS)
+		{
+			return arm_pll;
+		}
+		else
+		{// ahb = fclk/sync_div
+			u32 div = (sync_mode >> 26) & 0x7;
+
+			return arm_pll / div;
+		}
+	}
+	else
+	{// not in sync mode
+		u32 ahb_pll = HAL_get_ahb_pll();
+		u32 mode = __le32_to_cpu(*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2);
+		u32 div = 1;
+
+		if (!(mode & AHB_CLK_CNTRL2_AHB_DIV0_BYPASS))
+		{// AHB_DIV0 is used
+			div = div * (mode & 0xF);
+		}
+		
+		if (!(mode & AHB_CLK_CNTRL2_AHB_DIV1_BYPASS))
+		{// AHB_DIV1 is used
+			div = div * ((mode >> 4) & 0xF);
+		}
+
+		return ahb_pll / div;
+	}
+}
+
+static inline u32 HAL_get_ddr_clk(void)
+{
+	u32 ddr_mux_sel = __le32_to_cpu(*(volatile u32 *)CLKCORE_DDR_PCIE_CLK_CNTRL);
+	
+	if (ddr_mux_sel & DDR_PCIE_CLK_CNTRL_DDR_MUX_SEL)
+	{//ddr is derived from arm pll (fclk)
+		u32 arm_pll = HAL_get_arm_pll();
+
+		if (ddr_mux_sel & DDR_PCIE_CLK_CNTRL_DDR_DIV_BYPASS)
+		{//bypass ddr clk = fclk
+			return arm_pll;
+		}
+		else
+		{// ddr = fclk/ddr_div_val
+			u32 div = (ddr_mux_sel >> 4) & 0xf;
+
+			return arm_pll / div;
+		}
+	}
+	else
+	{// ddr is derived from ahb pll (sclk1)
+		u32 ahb_pll = HAL_get_ahb_pll();
+		u32 mode = __le32_to_cpu(*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2);
+		if (mode & AHB_CLK_CNTRL2_AHB_DIV0_BYPASS)
+		{// clock switch is syn_mux output (bypass mode enable)
+			//should not come here!!!
+			return 0;
+		}
+		else
+		{// clock switch output is AHB_DIV0 
+			u32 div0 = mode & 0xF;
+			return ahb_pll / div0;
+		}
+	}
+}
+
+static inline void HAL_set_phy_pll(u32 fclk, u32 NR, u32 OD)
+{
+	volatile u32 delay_count;
+	u32 NF;
+        u32 NB;
+	u32 ref_clk = CFG_REFCLKFREQ / 1000000;
+
+	fclk = fclk / 1000000; 
+	NF = (fclk * NR * OD) / ref_clk;
+
+	NB = (NF * 2) / 5;
+
+	NR--;OD--;NF--;NB--;
+	
+	// set NR / NF
+	*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL &= __cpu_to_le32(0xFFC0E000);
+	*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL |= __cpu_to_le32((NR << 16) + NF);
+	// set OD and NB (NB=NF/2.5)
+	*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 &= __cpu_to_le32(0x8000FFFF);
+        *(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 |= __cpu_to_le32((OD << 28) + (NB << 16));
+
+	//wait 5 uS.... looks like it is one cycle...
+	delay_count = 12000;
+//	while (delay_count--);
+
+	//set PLL into reset mode
+	*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 &= __cpu_to_le32(~PHY_CLK_CNTRL2_PLL_RESET);
+
+	//wait 5 uS.... looks like it is one cycle...
+	delay_count = 600;
+	while (delay_count--);	
+	//clear status bit 
+	do {
+		*(volatile u32 *)CLKCORE_PLL_STATUS &= __cpu_to_le32(~PLL_STATUS_PHY_PLL_STATUS_CLEAR);	
+		delay_count = 600;
+		while (delay_count--);
+	} while ((*(volatile u32 *)CLKCORE_PLL_STATUS & __cpu_to_le32(PLL_STATUS_PHY_PLL_STATUS)));
+}
+
+static inline u32 HAL_get_phy_pll(void)
+{
+	u32 NR;
+	u32 OD;
+	u32 NF;
+	u32 ref_clk = CFG_REFCLKFREQ / 1000000;
+	u32 reg = __le32_to_cpu(*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL);
+	NR = (reg & 0x003F0000) >> 16;
+	NF = (reg & 0x00001FFF);
+	reg = __le32_to_cpu(*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2);
+	OD = (reg & 0x70000000) >> 28;
+
+	return ( ref_clk * (NF + 1) / (NR  + 1) / (OD  + 1) ) * 1000000;
+}
+
+static inline void HAL_set_phy_gem_clk(u32 gem0_refclk, u32 gem1_refclk, u32 phy_refclk)
+{
+	u32 phy_pll = HAL_get_phy_pll();
+	u32 div0 = (phy_pll / gem0_refclk) & 0xF;
+	u32 div1 = (phy_pll / gem1_refclk) & 0xF;
+	u32 div2 = (phy_pll / phy_refclk) & 0xF;
+
+	if (div0 != 1) {
+		*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 &= __cpu_to_le32(0xFFFFFFF0);
+		*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 |= __cpu_to_le32(div0);
+		*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 &= __cpu_to_le32(~PHY_CLK_CNTRL2_PHY_DIV0_BYPASS);
+	}
+	else
+	{
+		*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 |= __cpu_to_le32(PHY_CLK_CNTRL2_PHY_DIV0_BYPASS);
+	}
+
+	if (div1 != 1) {
+		*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 &= __cpu_to_le32(0xFFFFFF0F);
+		*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 |= __cpu_to_le32(div1 << 4);
+		*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 &= __cpu_to_le32(~PHY_CLK_CNTRL2_PHY_DIV1_BYPASS);
+	}
+	else
+	{
+		*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 |= __cpu_to_le32(PHY_CLK_CNTRL2_PHY_DIV1_BYPASS);	
+	}
+
+	if (div2 != 1) {
+		*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 &= __cpu_to_le32(0xFFFFF0FF);
+		*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 |= __cpu_to_le32(div2 << 8);
+		*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 &= __cpu_to_le32(~PHY_CLK_CNTRL2_PHY_DIV2_BYPASS);
+	}
+	else
+	{	
+		*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL2 |= __cpu_to_le32(PHY_CLK_CNTRL2_PHY_DIV2_BYPASS);
+	}
+}
+
+
+static inline void HAL_set_ahb_ddr_clk(u32 ahbclk, u32 ddr_clk, int flags)
+{
+	u32 ahb_pll = HAL_get_ahb_pll();
+	u32 arm_pll = HAL_get_arm_pll();
+	u32 ahb_div0, ahb_div1, ddr_div;
+
+	if (flags)
+	{
+		// DDR uses FLCK
+		// AHB uses SCLK1
+		ddr_div = arm_pll / ddr_clk;
+
+		ahb_div0 = ahb_pll / ahbclk;
+		ahb_div1 = 1;		
+
+		// DDR MUX from ARM PLL
+		*(volatile u32 *)CLKCORE_DDR_PCIE_CLK_CNTRL |= __cpu_to_le32(DDR_PCIE_CLK_CNTRL_DDR_MUX_SEL);
+	}
+	else
+	{
+		// DDR uses SCLK2
+		// AHB uses SCLK1
+		ddr_div = 1;
+		ahb_div0 = ahb_pll / ddr_clk;
+		ahb_div1 = ddr_clk / ahbclk;
+
+		// DDR MUX from AHB PLL
+		*(volatile u32 *)CLKCORE_DDR_PCIE_CLK_CNTRL &= __cpu_to_le32(~DDR_PCIE_CLK_CNTRL_DDR_MUX_SEL);
+	}
+
+	if (ddr_div != 1)
+	{
+		
+		*(volatile u32 *)CLKCORE_DDR_PCIE_CLK_CNTRL &= __cpu_to_le32(0xFFFFFF0F);
+		*(volatile u32 *)CLKCORE_DDR_PCIE_CLK_CNTRL |= __cpu_to_le32((ddr_div & 0xF) << 4);
+		// DDR DIV Bypass disable
+		*(volatile u32 *)CLKCORE_DDR_PCIE_CLK_CNTRL &=  __cpu_to_le32(~DDR_PCIE_CLK_CNTRL_DDR_DIV_BYPASS);
+	}
+	else
+	{	// DDR DIV Bypass enable
+		*(volatile u32 *)CLKCORE_DDR_PCIE_CLK_CNTRL |= __cpu_to_le32(DDR_PCIE_CLK_CNTRL_DDR_DIV_BYPASS);
+	} 
+
+
+	if (ahb_div0 != 1)
+	{
+		
+		*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 &= __cpu_to_le32(0xFFFFFFF0);
+		*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 |= __cpu_to_le32(ahb_div0 & 0xF);
+		// AHB DIV0 Bypass disable
+		*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 &=  __cpu_to_le32(~(AHB_CLK_CNTRL2_AHB_DIV0_BYPASS));
+	}
+	else
+	{	// AHB DIV0 Bypass enable
+		*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 |= __cpu_to_le32(AHB_CLK_CNTRL2_AHB_DIV0_BYPASS);
+	} 
+
+	if (ahb_div1 != 1)
+	{
+		
+		*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 &= __cpu_to_le32(0xFFFFFF0F);
+		*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 |= __cpu_to_le32((ahb_div1 & 0xF) << 4);
+		// AHB DIV1 Bypass disable
+		*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 &=  __cpu_to_le32(~(AHB_CLK_CNTRL2_AHB_DIV1_BYPASS));
+	}
+	else
+	{	// AHB DIV1 Bypass enable
+		*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 |= __cpu_to_le32(AHB_CLK_CNTRL2_AHB_DIV1_BYPASS);
+	}
+}
+
+static inline void HAL_all_pll_bypass(void)
+{
+	*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL |= __cpu_to_le32(PHY_CLK_CNTRL_PHY_REF_BYPASS);
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL |= __cpu_to_le32(AHB_CLK_CNTRL_AHB_REF_BYPASS);
+
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL |= __cpu_to_le32(ARM_CLK_CNTRL_ARM_REF_BYPASS);
+
+	//AHB sync mode disable we will take the clock from AHB pll
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL &= __cpu_to_le32(~AHB_CLK_CNTRL_SYNC_MODE);
+
+	// ARM DIV Bypass
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL2 |= __cpu_to_le32(ARM_CLK_CNTRL2_ARM0_DIV_BYPASS \
+						| ARM_CLK_CNTRL2_ARM1_DIV_BYPASS);
+	// AHB DIV Bypass
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL2 |=  __cpu_to_le32(AHB_CLK_CNTRL2_AHB_DIV0_BYPASS \
+						| AHB_CLK_CNTRL2_AHB_DIV1_BYPASS) ;
+}
+
+static inline void HAL_set_ipsec_clk(u32 ipsec_clk)
+{
+	u32 ahb_pll = HAL_get_ahb_pll();
+	u32 div;
+
+	div = ahb_pll / ipsec_clk;
+
+	div = div << 12;
+	*(volatile u32 *)CLKCORE_DDR_PCIE_CLK_CNTRL = (*(volatile u32 *)CLKCORE_DDR_PCIE_CLK_CNTRL & __cpu_to_le32(~0xf000UL)) | __cpu_to_le32(div);
+
+	*(volatile u32 *)CLKCORE_DDR_PCIE_CLK_CNTRL &= __cpu_to_le32(~DDR_PCIE_CLK_CNTRL_IPsec_DIV0_BYPASS);
+
+	*(volatile u32 *)CLKCORE_DDR_PCIE_CLK_CNTRL &= __cpu_to_le32(~DDR_PCIE_CLK_CNTRL_IPsecMUX_SEL);
+}
+
+static inline u32 HAL_get_ipsec_clk(void)
+{
+        u32 ipsec_mux_sel = __le32_to_cpu(*(volatile u32 *)CLKCORE_DDR_PCIE_CLK_CNTRL);
+
+        if (ipsec_mux_sel & DDR_PCIE_CLK_CNTRL_IPsecMUX_SEL)
+        {
+                u32 arm_pll = HAL_get_arm_pll();
+
+                if (ipsec_mux_sel & DDR_PCIE_CLK_CNTRL_IPsec_DIV1_BYPASS)
+                        return arm_pll;
+                else
+                {
+                        u32 div = (ipsec_mux_sel >> 16) & 0xf;
+
+                        return arm_pll / div;
+                }
+        }
+        else
+        {
+                u32 ahb_pll = HAL_get_ahb_pll();
+
+                if (ipsec_mux_sel & DDR_PCIE_CLK_CNTRL_IPsec_DIV0_BYPASS)
+                        return ahb_pll;
+                else
+                {
+                        u32 div = (ipsec_mux_sel >> 12) & 0xf;
+
+                        return ahb_pll / div;
+                }
+        }
+}
+
+
+static inline void HAL_all_pll_remove_bypass(void)
+{
+	*(volatile u32 *)CLKCORE_ARM_CLK_CNTRL &= __cpu_to_le32(~ARM_CLK_CNTRL_ARM_REF_BYPASS);
+	*(volatile u32 *)CLKCORE_AHB_CLK_CNTRL &= __cpu_to_le32(~AHB_CLK_CNTRL_AHB_REF_BYPASS);
+	*(volatile u32 *)CLKCORE_PHY_CLK_CNTRL &= __cpu_to_le32(~PHY_CLK_CNTRL_PHY_REF_BYPASS);
+}
+#define HAL_get_amba_clk HAL_get_ahb_clk
+#define HAL_get_arm_clk HAL_get_arm0_clk
+#endif /* _BSP_1000_H */

include/asm-arm/arch-comcerto/bsp_2000.h

diff --git a/include/asm-arm/arch-comcerto/bsp_2000.h b/include/asm-arm/arch-comcerto/bsp_2000.h
new file mode 100644
index 0000000..0f893ed
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/bsp_2000.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _BSP_2000_H
+#define _BSP_2000_H
+
+#include <asm/arch/hardware.h>
+#ifndef __ASSEMBLY__
+#include <asm/byteorder.h>
+#endif
+
+#define GPIO_TYPE_INPUT		0
+#define GPIO_TYPE_OUTPUT	1
+
+#define COMCERTO_PART_MAGIC 0x4D535044
+
+int SoC_gpio_cfg(int gpio, int mode);
+
+#define SoC_gpio_mask(gpio)		(1 << ((gpio) & 0x1f))
+#define SoC_gpio_read(gpiomask)		(__le32_to_cpu(*(volatile u32 *)COMCERTO_GPIO_INPUT_REG & (gpiomask)))
+#define SoC_gpio_set_0(gpiomask)	(*(volatile u32 *)COMCERTO_GPIO_OUTPUT_REG &= __cpu_to_le32(~(gpiomask)))
+#define SoC_gpio_set_1(gpiomask)	(*(volatile u32 *)COMCERTO_GPIO_OUTPUT_REG |= __cpu_to_le32((gpiomask)))
+
+#endif /* _BSP_2000_H */

include/asm-arm/arch-comcerto/bsp_515.h

diff --git a/include/asm-arm/arch-comcerto/bsp_515.h b/include/asm-arm/arch-comcerto/bsp_515.h
new file mode 100644
index 0000000..fe8440d
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/bsp_515.h
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _BSP_515_H
+#define _BSP_515_H
+
+/* Chip Select Enable Register */
+#define EXP_CSSD0	0		/* Y17 */
+#define EXP_CSSD1	1		/* AB03 */
+#define EXP_CSBOOT	2
+#define EXP_CSP0	3
+#define EXP_CSP1	5
+#define EXP_CSP2	6
+#define SDR_CSSD0	13
+#define SDR_CSSD1	14
+
+#define CS_DISABLE		0
+#define CS_ENABLE		1
+
+#define CS_MEMTYPE_SRAM		0
+#define CS_MEMTYPE_SDRAM	1
+
+#define CS_ACTIVE_LOW		0
+#define CS_ACTIVE_HIGH		1
+
+#define CS_BUSWIDTH_8BIT	0x0
+#define CS_BUSWIDTH_16BIT	0x1
+#define CS_BUSWIDTH_32BIT	0x2
+
+#define CS_DQMMODE_NORMAL	0x0
+#define CS_DQMMODE_FOLLOW_WE	0x1
+
+#define CLK_MODE_SYNC	0
+#define CLK_MODE_ASYNC	1
+
+#define GPIO_TYPE_INPUT		0
+#define GPIO_TYPE_OUTPUT	1
+
+#define IOCTRL_SPI_BUS		0
+#define IOCTRL_UART0		1
+#define IOCTRL_UART1		2
+#define IOCTRL_EXPA21_A22	3
+
+
+#define BELLOW_MEM_SDC0		0
+#define BELLOW_MEM_SDC1		1
+
+struct cs_cfg {
+
+	u8 memtype; 		/* 1 = SDRAM or 0 = SRAM CS select */
+				/* only xxx_CSSD0 can be SDRAM */
+
+	u32 baseaddr;		/* only valid for xxx_CSSD0 or  xxx_CSSD1 */
+	u32 size;		/* only valid for xxx_CSSD0 or xxx_CSSD1 */ /* segment size? */
+
+	u8 buswidth;	/* Data Bus Width */
+
+	/* SRAM config, only valid if memtype = SDRAM; Chip Select Register Setting for SRAMs  */
+	u8 level;	/* CS Level */
+	u8 cmdwidth;	/* Command Width Index */
+	u8 addrsetup;	/* Address Setup */
+	u8 dqm_mode;	/* DQM Mode */
+
+	/* SDRAM_CFG1 SDRAM Timing Configuration Register 1, only valid if memtype = SDRAM */
+	u8 tras;	/* RAS to Precharge cycle time. (Number of CLK cycles.) */
+	u8 trc;		/* REF to REF/RAS cycle time. (Number of CLK cycles.) */
+	u8 trcd;	/* Row active to Column Active. (Number of CLK cycles.) */
+	u8 trp;		/* Precharge to Row active. (Number of CLK cycles.) */
+	u8 cl;		/* CAS Latency. (Number of CLK cycles.) */
+
+	/* SDRAM_CFG2 SDRAM Timing Configuration Register 2, only valid if memtype = SDRAM */
+	u8 memchip_dtype;	/* Memory Chip Data Size Type */
+	u8 twr;			/* Write Recovery Time (Number of CLK cycles.) */
+	u8 tmrd;		/* Mode register set to active or refresh command. (Number of CLK cycles.) */
+	u8 trrd;		/* RAS to RAS of opposite banks. (Number of CLK cycles.) */
+
+	/* SDRAM_REFRESH SDRAM Refresh Register, only valid if memtype = SDRAM */
+	u16 refcnt;		/* Refresh period count (Number of CLK Cycles). */
+
+	u16 pwroncnt;		/* Power on cycle count */
+};
+
+int SoC_cs_cfg(int cs, int enable, struct cs_cfg *cfg);
+int SoC_pll_cfg (int mode, unsigned int arm_clk, unsigned int bus_clk);
+
+int SoC_high_mem_cfg (int cs);
+int SoC_mem_divider_cfg (u32 address, int sdc);
+
+int SoC_gpio_cfg(int gpio, int mode);
+int SoC_ioctrl_cfg(int resource, int enable);
+
+#define SoC_gpio_mask(gpio)		(1 << ((gpio) & 0x1f))
+
+#define SoC_gpio_read(gpiomask)		(*(volatile u32 *)GPIO_INPUT & (gpiomask))
+#define SoC_gpio_set_0(gpiomask)	(*(volatile u32 *)GPIO_OUTPUT &= ~(gpiomask))
+
+#define SoC_gpio_set_1(gpiomask)	(*(volatile u32 *)GPIO_OUTPUT |= (gpiomask))
+
+#define SoC_timer0_set(val)		(*(volatile u32 *)TIMER0_COUNT = (val))
+#define SoC_timer0_get()		(*(volatile u32 *)TIMER0_CURR_COUNT)
+
+#define SoC_timer1_set(val)		(*(volatile u32 *)TIMER1_COUNT = (val))
+#define SoC_timer1_get()		(*(volatile u32 *)TIMER1_CURR_COUNT)
+
+#define SoC_clk_arm_get()		((CFG_REFCLKFREQ * (*(volatile u32 *)CLKCORE_ARM_PLL & 0x7F)) >> 1)
+
+#define SoC_clk_amba_get()		((*(volatile u32 *)CLKCORE_AMBA_PLL & (PLL_POWER | PLL_BYPASS)) ? \
+					(SoC_clk_arm_get() >> 1) : \
+					((CFG_REFCLKFREQ * (*(volatile u32 *)CLKCORE_AMBA_PLL & 0x7F)) >> 2))
+
+#endif /* _BSP_515_H */

include/asm-arm/arch-comcerto/bsp_530.h

diff --git a/include/asm-arm/arch-comcerto/bsp_530.h b/include/asm-arm/arch-comcerto/bsp_530.h
new file mode 100644
index 0000000..571716e
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/bsp_530.h
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _BSP_530_H
+#define _BSP_530_H
+
+/* Chip Select Enable Register */
+#define EXP_CSSD0	0		/* Y17 */
+#define EXP_CSSD1	1		/* AB03 */
+#define EXP_CSBOOT	2
+#define EXP_CSP0	3
+
+#define CS_DISABLE		0
+#define CS_ENABLE		1
+
+#define CS_MEMTYPE_SRAM		0
+#define CS_MEMTYPE_SDRAM	1
+
+#define CS_ACTIVE_LOW		0
+#define CS_ACTIVE_HIGH		1
+
+#define CS_BUSWIDTH_8BIT	0x0
+#define CS_BUSWIDTH_16BIT	0x1
+#define CS_BUSWIDTH_32BIT	0x2
+
+#define CS_DQMMODE_NORMAL	0x0
+#define CS_DQMMODE_FOLLOW_WE	0x1
+
+#define CLK_MODE_SYNC	0
+#define CLK_MODE_ASYNC	1
+
+#define GPIO_TYPE_INPUT		0
+#define GPIO_TYPE_OUTPUT	1
+
+struct cs_cfg {
+
+	u8 memtype; 		/* 1 = SDRAM or 0 = SRAM CS select */
+				/* only xxx_CSSD0 can be SDRAM */
+
+	u32 baseaddr;		/* only valid for xxx_CSSD0 or  xxx_CSSD1 */
+	u32 size;		/* only valid for xxx_CSSD0 or xxx_CSSD1 */ /* segment size? */
+
+	u8 buswidth;	/* Data Bus Width */
+
+	/* SRAM config, only valid if memtype = SDRAM; Chip Select Register Setting for SRAMs  */
+	u8 level;	/* CS Level */
+	u8 cmdwidth;	/* Command Width Index */
+	u8 addrsetup;	/* Address Setup */
+	u8 dqm_mode;	/* DQM Mode */
+
+	/* SDRAM_CFG1 SDRAM Timing Configuration Register 1, only valid if memtype = SDRAM */
+	u8 tras;	/* RAS to Precharge cycle time. (Number of CLK cycles.) */
+	u8 trc;		/* REF to REF/RAS cycle time. (Number of CLK cycles.) */
+	u8 trcd;	/* Row active to Column Active. (Number of CLK cycles.) */
+	u8 trp;		/* Precharge to Row active. (Number of CLK cycles.) */
+	u8 cl;		/* CAS Latency. (Number of CLK cycles.) */
+
+	/* SDRAM_CFG2 SDRAM Timing Configuration Register 2, only valid if memtype = SDRAM */
+	u8 memchip_dtype;	/* Memory Chip Data Size Type */
+	u8 twr;			/* Write Recovery Time (Number of CLK cycles.) */
+	u8 tmrd;		/* Mode register set to active or refresh command. (Number of CLK cycles.) */
+	u8 trrd;		/* RAS to RAS of opposite banks. (Number of CLK cycles.) */
+
+	/* SDRAM_REFRESH SDRAM Refresh Register, only valid if memtype = SDRAM */
+	u16 refcnt;		/* Refresh period count (Number of CLK Cycles). */
+
+	u16 pwroncnt;		/* Power on cycle count */
+};
+
+int SoC_cs_cfg(int cs, int enable, struct cs_cfg *cfg);
+int SoC_pll_cfg (int mode, unsigned int arm_clk, unsigned int bus_clk);
+
+int SoC_high_mem_cfg (int cs);
+
+int SoC_gpio_cfg(int gpio, int mode);
+
+#define SoC_gpio_mask(gpio)		(1 << ((gpio) & 0x7))
+
+#define SoC_gpio_read(gpiomask)		(*(volatile u32 *)GPIO_INPUT & (gpiomask & 0xff))
+#define SoC_gpio_set_0(gpiomask)	(*(volatile u32 *)GPIO_OUTPUT &= ~(gpiomask & 0xff))
+
+#define SoC_gpio_set_1(gpiomask)	(*(volatile u32 *)GPIO_OUTPUT |= (gpiomask & 0xff))
+
+#define SoC_timer0_set(val)		(*(volatile u32 *)TIMER0_COUNT = ((val) & 0x00ffffff))
+#define SoC_timer0_get()		(*(volatile u32 *)TIMER0_CURR_COUNT & 0x00ffffff)
+
+#define SoC_timer1_set(val)		(*(volatile u32 *)TIMER1_COUNT = (TIMER1_COUNT & 0xff000000) | ((val) & 0x00ffffff))
+#define SoC_timer1_get()		(*(volatile u32 *)TIMER1_CURR_COUNT & 0x00ffffff)
+
+#define SoC_clk_arm_get()		((CFG_REFCLKFREQ * (*(volatile u32 *)CLKCORE_ARM_PLL & 0x3F)) >> 1)
+
+#define SoC_clk_amba_get()		((*(volatile u32 *)CLKCORE_AMBA_PLL & (PLL_POWER | PLL_BYPASS)) ? \
+					(SoC_clk_arm_get() >> 1) : \
+					((CFG_REFCLKFREQ * (*(volatile u32 *)CLKCORE_AMBA_PLL & 0x3F)) >> 2))
+
+#endif /* _BSP_530_H */

include/asm-arm/arch-comcerto/cache_c2000.h

diff --git a/include/asm-arm/arch-comcerto/cache_c2000.h b/include/asm-arm/arch-comcerto/cache_c2000.h
new file mode 100644
index 0000000..dfaf6ff
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/cache_c2000.h
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+#include <asm/arch/system_c2000.h>
+
+/*
+ * Invalidate L2 Cache using co-proc instruction
+ */
+static inline void invalidate_l2_cache(void)
+{
+	unsigned int val=0;
+
+	asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
+		: : "r" (val) : "cc");
+	isb();
+}
+
+void l2_cache_enable(void);
+void l2_cache_disable(void);
+
+#endif /* _ASM_CACHE_H */

include/asm-arm/arch-comcerto/clkcore_c2000.h

diff --git a/include/asm-arm/arch-comcerto/clkcore_c2000.h b/include/asm-arm/arch-comcerto/clkcore_c2000.h
new file mode 100644
index 0000000..627d26e
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/clkcore_c2000.h
@@ -0,0 +1,327 @@
+#include "comcerto_2000.h"
+
+#define USB0_PHY_CTRL_REG0           0x90410000
+#define USB1_PHY_CTRL_REG0           0x90410010
+#define USB_PHY_SCALEDOWN_ADDR       0x9046003C
+
+#define DEVICE_RST_CNTRL	     (COMCERTO_APB_CLK_BASE + 0x00)
+#define SERDES_RST_CNTRL             (COMCERTO_APB_CLK_BASE + 0x04)
+#define PCIe_SATA_RST_CNTRL          (COMCERTO_APB_CLK_BASE + 0x08)
+#define USB_RST_CNTRL                (COMCERTO_APB_CLK_BASE + 0x0C)
+#define A9DP_PWR_STAT                (COMCERTO_APB_CLK_BASE + 0x28)
+#define A9DP_PWR_CNTRL               (COMCERTO_APB_CLK_BASE + 0x2C)
+#define GNRL_CLK_CNTRL_0	     (COMCERTO_APB_CLK_BASE + 0x30)
+#define GNRL_CLK_CNTRL_1	     (COMCERTO_APB_CLK_BASE + 0x34)
+#define PLLS_GLOBAL_CNTRL            (COMCERTO_APB_CLK_BASE + 0x38)
+#define AXI_CLK_CNTRL_0              (COMCERTO_APB_CLK_BASE + 0x40)
+#define AXI_CLK_CNTRL_1              (COMCERTO_APB_CLK_BASE + 0x44)
+#define AXI_CLK_CNTRL_2              (COMCERTO_APB_CLK_BASE + 0x48)
+#define AXI_CLK_DIV_CNTRL            (COMCERTO_APB_CLK_BASE + 0x4C)
+#define AXI_RESET_0                  (COMCERTO_APB_CLK_BASE + 0x50)
+#define AXI_RESET_1                  (COMCERTO_APB_CLK_BASE + 0x54)
+#define AXI_RESET_2                  (COMCERTO_APB_CLK_BASE + 0x58)
+#define A9DP_MPU_CLK_CNTRL           (COMCERTO_APB_CLK_BASE + 0x68)
+#define A9DP_MPU_CLK_DIV_CNTRL       (COMCERTO_APB_CLK_BASE + 0x6C)
+#define A9DP_MPU_RESET               (COMCERTO_APB_CLK_BASE + 0x70)
+#define A9DP_CPU_CLK_CNTRL           (COMCERTO_APB_CLK_BASE + 0x74)
+#define A9DP_CPU_RESET               (COMCERTO_APB_CLK_BASE + 0x78)
+#define A9DP_CLK_CNTRL               (COMCERTO_APB_CLK_BASE + 0x80)
+#define A9DP_CLK_DIV_CNTRL           (COMCERTO_APB_CLK_BASE + 0x84)
+#define A9DP_RESET                   (COMCERTO_APB_CLK_BASE + 0x88)
+#define L2CC_CLK_CNTRL               (COMCERTO_APB_CLK_BASE + 0x90)
+#define L2CC_CLK_DIV_CNTRL           (COMCERTO_APB_CLK_BASE + 0x94)
+#define L2CC_RESET                   (COMCERTO_APB_CLK_BASE + 0x98)
+#define TPI_CLK_CNTRL                (COMCERTO_APB_CLK_BASE + 0xA0)
+#define TPI_CLK_DIV_CNTRL            (COMCERTO_APB_CLK_BASE + 0xA4)
+#define TPI_RESET                    (COMCERTO_APB_CLK_BASE + 0xA8)
+#define CSYS_CLK_CNTRL               (COMCERTO_APB_CLK_BASE + 0xB0)
+#define CSYS_CLK_DIV_CNTRL           (COMCERTO_APB_CLK_BASE + 0xB4)
+#define CSYS_RESET                   (COMCERTO_APB_CLK_BASE + 0xB8)
+#define EXTPHY0_CLK_CNTRL            (COMCERTO_APB_CLK_BASE + 0xC0)
+#define EXTPHY0_CLK_DIV_CNTRL        (COMCERTO_APB_CLK_BASE + 0xC4)
+#define EXTPHY0_RESET                (COMCERTO_APB_CLK_BASE + 0xC8)
+#define EXTPHY1_CLK_CNTRL            (COMCERTO_APB_CLK_BASE + 0xD0)
+#define EXTPHY1_CLK_DIV_CNTRL        (COMCERTO_APB_CLK_BASE + 0xD4)
+#define EXTPHY1_RESET                (COMCERTO_APB_CLK_BASE + 0xD8)
+#define EXTPHY2_CLK_CNTRL            (COMCERTO_APB_CLK_BASE + 0xE0)
+#define EXTPHY2_CLK_DIV_CNTRL        (COMCERTO_APB_CLK_BASE + 0xE4)
+#define EXTPHY2_RESET                (COMCERTO_APB_CLK_BASE + 0xE8)
+#define DDR_CLK_CNTRL                (COMCERTO_APB_CLK_BASE + 0xF0)
+#define DDR_CLK_DIV_CNTRL            (COMCERTO_APB_CLK_BASE + 0xF4)
+#define DDR_RESET                    (COMCERTO_APB_CLK_BASE + 0xF8)
+#define HFE_CLK_CNTRL                (COMCERTO_APB_CLK_BASE + 0x100)
+#define HFE_CLK_DIV_CNTRL            (COMCERTO_APB_CLK_BASE + 0x104)
+#define HFE_RESET                    (COMCERTO_APB_CLK_BASE + 0x108)
+#define IPSEC_CLK_CNTRL              (COMCERTO_APB_CLK_BASE + 0x110)
+#define IPSEC_CLK_DIV_CNTRL          (COMCERTO_APB_CLK_BASE + 0x114)
+#define IPSEC_RESET                  (COMCERTO_APB_CLK_BASE + 0x118)
+#define DECT_CLK_CNTRL               (COMCERTO_APB_CLK_BASE + 0x120)
+#define DECT_CLK_DIV_CNTRL           (COMCERTO_APB_CLK_BASE + 0x124)
+#define DECT_RESET                   (COMCERTO_APB_CLK_BASE + 0x128)
+#define GEMTX_CLK_CNTRL              (COMCERTO_APB_CLK_BASE + 0x130)
+#define GEMTX_CLK_DIV_CNTRL          (COMCERTO_APB_CLK_BASE + 0x134)
+#define GEMTX_RESET                  (COMCERTO_APB_CLK_BASE + 0x138)
+#define TDMNTG_REF_CLK_CNTRL         (COMCERTO_APB_CLK_BASE + 0x140)
+#define TDMNTG_REF_CLK_DIV_CNTRL     (COMCERTO_APB_CLK_BASE + 0x144)
+#define TDMNTG_RESET                 (COMCERTO_APB_CLK_BASE + 0x148)
+#define TDM_CLK_CNTRL                (COMCERTO_APB_CLK_BASE + 0x14C)
+#define TSUNTG_REF_CLK_CNTRL         (COMCERTO_APB_CLK_BASE + 0x150)
+#define TSUNTG_REF_CLK_DIV_CNTRL     (COMCERTO_APB_CLK_BASE + 0x154)
+#define TSUNTG_RESET                 (COMCERTO_APB_CLK_BASE + 0x158)
+#define SATA_PMU_CLK_CNTRL           (COMCERTO_APB_CLK_BASE + 0x160)
+#define SATA_PMU_CLK_DIV_CNTRL       (COMCERTO_APB_CLK_BASE + 0x164)
+#define SATA_PMU_RESET               (COMCERTO_APB_CLK_BASE + 0x168)
+#define SATA_OOB_CLK_CNTRL           (COMCERTO_APB_CLK_BASE + 0x170)
+#define SATA_OOB_CLK_DIV_CNTRL       (COMCERTO_APB_CLK_BASE + 0x174)
+#define SATA_OOB_RESET               (COMCERTO_APB_CLK_BASE + 0x178)
+#define PLL0_M_LSB                   (COMCERTO_APB_CLK_BASE + 0x1C0)
+#define PLL0_M_MSB                   (COMCERTO_APB_CLK_BASE + 0x1C4)
+#define PLL0_P                       (COMCERTO_APB_CLK_BASE + 0x1C8)
+#define PLL0_S                       (COMCERTO_APB_CLK_BASE + 0x1CC)
+#define PLL0_CNTRL                   (COMCERTO_APB_CLK_BASE + 0x1D0)
+#define PLL0_TEST                    (COMCERTO_APB_CLK_BASE + 0x1D4)
+#define PLL0_STATUS                  (COMCERTO_APB_CLK_BASE + 0x1D8)
+#define PLL1_M_LSB                   (COMCERTO_APB_CLK_BASE + 0x1E0)
+#define PLL1_M_MSB                   (COMCERTO_APB_CLK_BASE + 0x1E4)
+#define PLL1_P                       (COMCERTO_APB_CLK_BASE + 0x1E8)
+#define PLL1_S                       (COMCERTO_APB_CLK_BASE + 0x1EC)
+#define PLL1_CNTRL                   (COMCERTO_APB_CLK_BASE + 0x1F0)
+#define PLL1_TEST                    (COMCERTO_APB_CLK_BASE + 0x1F4)
+#define PLL1_STATUS                  (COMCERTO_APB_CLK_BASE + 0x1F8)
+#define PLL2_M_LSB                   (COMCERTO_APB_CLK_BASE + 0x200)
+#define PLL2_M_MSB                   (COMCERTO_APB_CLK_BASE + 0x204)
+#define PLL2_P                       (COMCERTO_APB_CLK_BASE + 0x208)
+#define PLL2_S                       (COMCERTO_APB_CLK_BASE + 0x20C)
+#define PLL2_CNTRL                   (COMCERTO_APB_CLK_BASE + 0x210)
+#define PLL2_TEST                    (COMCERTO_APB_CLK_BASE + 0x214)
+#define PLL2_STATUS                  (COMCERTO_APB_CLK_BASE + 0x218)
+#define PLL3_M_LSB                   (COMCERTO_APB_CLK_BASE + 0x220)
+#define PLL3_M_MSB                   (COMCERTO_APB_CLK_BASE + 0x224)
+#define PLL3_P                       (COMCERTO_APB_CLK_BASE + 0x228)
+#define PLL3_S                       (COMCERTO_APB_CLK_BASE + 0x22C)
+#define PLL3_CNTRL                   (COMCERTO_APB_CLK_BASE + 0x230)
+#define PLL3_TEST                    (COMCERTO_APB_CLK_BASE + 0x234)
+#define PLL3_STATUS                  (COMCERTO_APB_CLK_BASE + 0x238)
+#define PLL3_DITHER_CNTRL 	     (COMCERTO_APB_CLK_BASE + 0x23C)
+#define PLL3_K_LSB 		     (COMCERTO_APB_CLK_BASE + 0x240)
+#define PLL3_K_MSB 		     (COMCERTO_APB_CLK_BASE + 0x244)
+#define PLL3_MFR 		     (COMCERTO_APB_CLK_BASE + 0x248)
+#define PLL3_MRR 		     (COMCERTO_APB_CLK_BASE + 0x24C)
+
+/* PCIe, SATA,  and SERDES Reset bits*/
+#define PCIE0_PWR_RST           (1 << 0)
+#define PCIE0_REG_RST  	        (1 << 1)
+#define PCIE1_PWR_RST           (1 << 2)
+#define PCIE1_REG_RST  	        (1 << 3)
+
+#define SATA0_RX_RST           	(1 << 4)
+#define SATA0_TX_RST 	       	(1 << 5)
+#define SATA1_RX_RST           	(1 << 6)
+#define SATA1_TX_RST  	        (1 << 7)
+
+#define PCIE0_AXI_RST  	        (1 << 0)
+#define PCIE1_AXI_RST  	        (1 << 1)
+#define SATA_AXI_RST	        (1 << 2)
+#define AXI_PCIE0_CLK_EN	(1 << 0)
+#define AXI_PCIE1_CLK_EN	(1 << 1)
+#define AXI_SATA_CLK_EN		(1 << 2)
+
+#define SERDES0_RST           	(1 << 0)
+#define SERDES1_RST           	(1 << 1)
+#define SERDES2_RST           	(1 << 2)
+
+/* AXI_RESET_1 bits */
+#define HFE_AXI_RESET		(1 << 3)
+
+//Clock Divider mirror mechanism in IRAM. It is going to take more than 256 bytes of IRAM
+#define IRAM_CLK_REG_MIRROR	0x8300FC00 //maybe to need to think of the another fixed location
+#define CLK_REG_DIV_BUG_BASE	AXI_CLK_DIV_CNTRL
+
+#define PLL_RESET (1 << 0)
+#define PLL_BYPASS (1 << 4)
+#define PLL_LOCK_EN (1 << 5)
+#define PLL_VSEL (1 << 6)
+
+#define CLK_DIV_BYPASS	(1 << 7)
+#define CLK_A9DP_PERI_DIV_BYPASS	(1 << 3)
+#define CLK_A9DP_ACP_DIV_BYPASS	(1 << 7)
+
+#define CLK_PLL_SRC_MASK	0x7
+#define CLK_PLL_SRC_SHIFT	1
+
+#define CLK_DIV_VAL_DEFAULT		0x2
+#define A9DP_ACP_CLK_DIV_VAL_DEFAULT	0x2
+#define A9DP_PERI_CLK_DIV_VAL_DEFAULT	0x2
+
+struct pll_info {
+	u32 m;
+	u32 p;
+	u32 s;
+	u32 vsel;
+};
+
+struct pll3_info {
+	u32 m;
+	u32 p;
+	u32 s;
+	u32 k;
+	u32 vsel;
+};
+
+struct pll_setting {
+        u32 pll0_freq_idx;
+        u32 pll1_freq_idx;
+        u32 pll2_freq_idx;
+        u32 pll3_freq_idx;
+};
+
+struct clock_cfg_settings
+{
+	u32 pll_cfg_idx;
+
+	u32 arm_clk;
+	u32 arm_clk_src;
+
+	u32 axi_clk;
+	u32 axi_clk_src;
+
+	u32 ddr_clk;
+	u32 ddr_clk_src;
+
+	u32 ipsec_clk;
+	u32 ipsec_clk_src;
+
+	u32 sata_oob_clk;
+	u32 sata_oob_clk_src;
+
+	u32 sata_pmu_clk;
+	u32 sata_pmu_clk_src;
+
+	u32 dect_clk;
+	u32 dect_clk_src;
+
+	u32 l2cc_clk;
+	u32 l2cc_clk_src;
+
+	u32 hfe_clk;
+	u32 hfe_clk_src;
+
+	u32 gemtx_clk;
+	u32 gemtx_clk_src;
+
+	u32 extphy0_clk;
+	u32 extphy0_clk_src;
+
+	u32 extphy1_clk;
+	u32 extphy1_clk_src;
+
+	u32 extphy2_clk;
+	u32 extphy2_clk_src;
+
+	u32 tpi_clk;
+	u32 tpi_clk_src;
+
+	u32 csys_clk;
+	u32 csys_clk_src;
+};
+
+enum {
+	PLL0 = 0,
+	PLL1,
+	PLL2,
+	PLL3
+};
+
+#define CFG_REFCLKFREQ_24          24000000        /* 24 MHz */
+#define CFG_REFCLKFREQ_48          48000000        /* 48 MHz */
+#define CFG_REFCLKFREQ          CFG_REFCLKFREQ_48
+
+#define PLL_FREQ_1800	1800
+#define PLL_FREQ_1600	1600
+#define PLL_FREQ_1500	1500
+#define PLL_FREQ_1400	1400
+#define PLL_FREQ_1300	1300
+#define PLL_FREQ_1066	1066
+#define PLL_FREQ_1000	1000
+#define PLL_FREQ_800	800
+#define PLL_FREQ_750	750
+#define PLL_FREQ_500	500
+
+enum {
+	PLL_CFG_1800 = 0,
+	PLL_CFG_1600,
+	PLL_CFG_1500,
+	PLL_CFG_1400,
+	PLL_CFG_1300,
+	PLL_CFG_1000,
+	PLL_CFG_800,
+	PLL_CFG_750,
+	PLL_CFG_500
+};
+
+enum {
+	PLL3_CFG_1066 = 0,
+	PLL3_CFG_800
+};
+
+#define PLL0_CFG_1300   PLL_CFG_1300
+#define PLL0_CFG_1800   PLL_CFG_1800
+#define PLL0_CFG_750    PLL_CFG_750
+
+#define PLL1_CFG_1000   PLL_CFG_1000
+#define PLL1_CFG_800    PLL_CFG_800
+
+#define PLL2_CFG_1500   PLL_CFG_1500
+#define PLL2_CFG_500    PLL_CFG_500
+
+
+enum {
+	CLK_CFG1 = 0,
+	CLK_CFG2,
+	CLK_CFG3,
+	CLK_CFG4,
+	CLK_CFG5
+};
+
+enum {
+	PLL_CFG_1800_1000_1500_1066 = 0,
+	PLL_CFG_750_1000_1500_800,
+	PLL_CFG_1300_800_500_800,
+	PLL_CFG_1300_800_500_1066,
+	PLL_CFG_1800_800_500_1066,
+};
+
+#define CLK_CFG		CLK_CFG1
+//For Alpha Bringup
+//#define CLK_CFG CLK_CFG4
+//#define CLK_CFG 	CLK_CFG5
+
+#define ARM_CLK_900	900
+#define ARM_CLK_750	750
+#define ARM_CLK_650	650
+#define AXI_CLK_250	250
+#define AXI_CLK_200	200
+#define DDR_CLK_533	533
+#define DDR_CLK_400	400
+#define SATA_OOB_CLK_125	125
+#define SATA_PMU_CLK_30		30
+#define SATA_PMU_CLK_25		25
+#define	IPSEC_CLK_300	300
+#define	IPSEC_CLK_250	250
+#define DECT_CLK_250	250
+#define L2CC_CLK_450	450
+#define L2CC_CLK_375	375
+#define L2CC_CLK_325	325
+#define HFE_CLK_500	500
+#define HFE_CLK_400	400
+#define GEMTX_CLK_125	125
+#define EXTPHY0_CLK_125	125
+#define EXTPHY1_CLK_125	125
+#define EXTPHY2_CLK_125	125
+#define TPI_CLK_250	250
+#define CSYS_CLK_166	166
+
+
+#define read_clk_div_bypass_backup(reg) readl(reg - CLK_REG_DIV_BUG_BASE + IRAM_CLK_REG_MIRROR)
+#define write_clk_div_bypass_backup(val, reg) writel(val, reg - CLK_REG_DIV_BUG_BASE + IRAM_CLK_REG_MIRROR)
+

include/asm-arm/arch-comcerto/comcerto_100.h

diff --git a/include/asm-arm/arch-comcerto/comcerto_100.h b/include/asm-arm/arch-comcerto/comcerto_100.h
new file mode 100644
index 0000000..1247ebd
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/comcerto_100.h
@@ -0,0 +1,669 @@
+#ifndef __COMCERTO_1XX_H__
+#define __COMCERTO_1XX_H__
+
+/* to be moved somewhere else */
+#ifndef __ASSEMBLY__
+#include <asm/byteorder.h>
+#endif
+
+#define FAILURE           0
+#define SUCCESS           1
+#define UNSET             0 	// pay attention that it is out of the LOW..HIGH values, so it will not be a possible value
+
+#define BYTE_SZ		8
+#define HALF_WORD	16
+#define WORD		32
+#define DOUBLE_WORD	64
+
+#define BOARD_CFG_1	1	/* ASIC board 256MB Micron */
+#define BOARD_CFG_2	2	/* ASIC board 1GB Micron */
+#define BOARD_CFG_3	3	/* ASIC board 1GB Samsum */
+#define BOARD_CFG_4	4	/* Packet IAD 128MB */
+#define BOARD_CFG_5	5	/* Router Board 64MB */
+#define BOARD_CFG_6	6	/* ASIC board 256MB Micron */
+#define BOARD_CFG_7	7	/* FE Router Board 64MB */
+#define BOARD_CFG_MOCA  8       /* MoCA EVM 128MB */
+#define BOARD_CFG_8     8       /* MoCA EVM 128MB */
+#define BOARD_CFG_9     9       /* Packet IAD C50 64MB */
+#define BOARD_CFG_10   10       /* Router C50 */
+
+/* memcore */
+/* device memory base addresses */
+// device memory sizes
+#define ARAM_SIZE		0x00010000 /* 64K */
+#define ARAM_BASEADDR		0x0A000000
+
+/* Hardware Interface Units */
+#define APB_BASEADDR		0x10000000
+#define APB_SIZE		0x01000000 /* 16M address range */
+
+#define EXP_CS0_BASEADDR	0x20000000
+#define EXP_CS1_BASEADDR	0x24000000
+#define EXP_CS2_BASEADDR	0x28000000
+#define EXP_CS3_BASEADDR	0x2C000000
+#define EXP_CS4_BASEADDR	0x30000000
+
+#define DDR_BASEADDR		0x80000000
+
+#define TDM_BASEADDR		(APB_BASEADDR + 0x000000)
+#define PHI_BASEADDR		(APB_BASEADDR + 0x010000)
+#define TDMA_BASEADDR		(APB_BASEADDR + 0x020000)
+#define ASA_DDR_BASEADDR	(APB_BASEADDR + 0x040000)
+#define ASA_ARAM_BASEADDR	(APB_BASEADDR + 0x048000)
+#define TIMER_BASEADDR		(APB_BASEADDR + 0x050000)
+#define ASD_BASEADDR		(APB_BASEADDR + 0x060000)
+#define GPIO_BASEADDR		(APB_BASEADDR + 0x070000)
+#define UART0_BASEADDR		(APB_BASEADDR + 0x090000)
+#define UART1_BASEADDR		(APB_BASEADDR + 0x094000)
+#define SPI_BASEADDR		(APB_BASEADDR + 0x098000)
+#define I2C_BASEADDR		(APB_BASEADDR + 0x09C000)
+#define INTC_BASEADDR		(APB_BASEADDR + 0x0A0000)
+#define CLKCORE_BASEADDR	(APB_BASEADDR + 0x0B0000)
+#define PUI_BASEADDR		(APB_BASEADDR + 0x0B0000)
+#define GEMAC_BASEADDR		(APB_BASEADDR + 0x0D0000)
+#define IDMA_BASEADDR		(APB_BASEADDR + 0x0E0000)
+#define MEMCORE_BASEADDR	(APB_BASEADDR + 0x0F0000)
+#define ASA_EBUS_BASEADDR	(APB_BASEADDR + 0x100000)
+#define ASA_AAB_BASEADDR	(APB_BASEADDR + 0x108000)
+#define GEMAC1_BASEADDR		(APB_BASEADDR + 0x190000)
+#define EBUS_BASEADDR		(APB_BASEADDR + 0x1A0000)
+#define MDMA_BASEADDR		(APB_BASEADDR + 0x1E0000)
+
+
+////////////////////////////////////////////////////////////
+//	IDMA block											    //
+////////////////////////////////////////////////////////////
+
+#define MMGEM0_START		(IDMA_BASEADDR + 0x100)
+#define MMGEM0_HEAD		(IDMA_BASEADDR + 0x104)
+#define MMGEM0_LOCK		(IDMA_BASEADDR + 0x108)
+#define MMGEM0_SRST		(IDMA_BASEADDR + 0x120)
+#define GEM0MM_START		(IDMA_BASEADDR + 0x180)
+#define GEM0MM_HEAD		(IDMA_BASEADDR + 0x184)
+#define GEM0MM_LOCK		(IDMA_BASEADDR + 0x188)
+#define GEM0MM_SRST		(IDMA_BASEADDR + 0x1A0)
+#define MMGEM1_START		(IDMA_BASEADDR + 0x300)
+#define MMGEM1_HEAD		(IDMA_BASEADDR + 0x304)
+#define MMGEM1_LOCK		(IDMA_BASEADDR + 0x308)
+#define MMGEM1_SRST		(IDMA_BASEADDR + 0x320)
+#define GEM1MM_START		(IDMA_BASEADDR + 0x380)
+#define GEM1MM_HEAD		(IDMA_BASEADDR + 0x384)
+#define GEM1MM_LOCK		(IDMA_BASEADDR + 0x388)
+#define GEM1MM_SRST		(IDMA_BASEADDR + 0x3A0)
+
+
+////////////////////////////////////////////////////////////
+// 	SPI block												    //
+////////////////////////////////////////////////////////////
+
+#define SPI_CTRLR0_REG		(SPI_BASEADDR+0x00)
+#define SPI_CTRLR1_REG		(SPI_BASEADDR+0x04)
+#define SPI_SSIENR_REG		(SPI_BASEADDR+0x08)
+#define SPI_MWCR_REG		(SPI_BASEADDR+0x0c)
+#define SPI_SER_REG		(SPI_BASEADDR+0x10)
+#define SPI_BAUDR_REG		(SPI_BASEADDR+0x14)
+#define SPI_TXFTLR_REG		(SPI_BASEADDR+0x18)
+#define SPI_RXFTLR_REG		(SPI_BASEADDR+0x1c)
+#define SPI_TXFLR_REG		(SPI_BASEADDR+0x20)
+#define SPI_RXFLR_REG		(SPI_BASEADDR+0x24)
+#define SPI_SR_REG		(SPI_BASEADDR+0x28)
+#define SPI_IMR_REG		(SPI_BASEADDR+0x2c)
+#define SPI_ISR_REG		(SPI_BASEADDR+0x30)
+#define SPI_RISR_REG		(SPI_BASEADDR+0x34)
+#define SPI_TXOICR_REG		(SPI_BASEADDR+0x38)
+#define SPI_RXOICR_REG		(SPI_BASEADDR+0x3c)
+#define SPI_RXUICR_REG		(SPI_BASEADDR+0x40)
+#define SPI_MSTICR_REG		(SPI_BASEADDR+0x44)
+#define SPI_ICR_REG		(SPI_BASEADDR+0x48)
+#define SPI_IDR_REG		(SPI_BASEADDR+0x58)
+#define SPI_DR_REG		(SPI_BASEADDR+0x60)
+
+////////////////////////////////////////////////////////////
+//	AHB block											    //
+////////////////////////////////////////////////////////////
+#define ASA_ARAM_PRI_REG	(ASA_ARAM_BASEADDR + 0x00)
+#define ASA_ARAM_TC_REG		(ASA_ARAM_BASEADDR + 0x04)
+#define ASA_ARAM_TC_CR_REG	(ASA_ARAM_BASEADDR + 0x08)
+#define ASA_ARAM_STAT_REG	(ASA_ARAM_BASEADDR + 0x0C)
+
+#define ASA_EBUS_PRI_REG	(ASA_EBUS_BASEADDR + 0x00)
+#define ASA_EBUS_TC_REG		(ASA_EBUS_BASEADDR + 0x04)
+#define ASA_EBUS_TC_CR_REG	(ASA_EBUS_BASEADDR + 0x08)
+#define ASA_EBUS_STAT_REG	(ASA_EBUS_BASEADDR + 0x0C)
+
+#define IDMA_MASTER		0
+#define TDMA_MASTER		1
+#define USBIPSEC_MASTER		2
+#define ARM0_MASTER		3
+#define ARM1_MASTER		4
+#define MDMA_MASTER		5
+
+#define IDMA_PRIORITY(level) (level)
+#define TDM_PRIORITY(level) (level << 4)
+#define USBIPSEC_PRIORITY(level) (level << 8)
+#define ARM0_PRIORITY(level) (level << 12)
+#define ARM1_PRIORITY(level) (level << 16)
+#define MDMA_PRIORITY(level) (level << 20)
+
+#define ASA_TC_REQIDMAEN	(1<<18)
+#define ASA_TC_REQTDMEN		(1<<19)
+#define ASA_TC_REQIPSECUSBEN	(1<<20)
+#define ASA_TC_REQARM0EN	(1<<21)
+#define ASA_TC_REQARM1EN	(1<<22)
+#define ASA_TC_REQMDMAEN	(1<<23)
+
+#define MEMORY_BASE_ADDR	0x80000000
+#define MEMORY_MAX_ADDR		(ASD_BASEADDR + 0x10)
+#define MEMORY_CR 		(ASD_BASEADDR + 0x14)
+#define ROM_REMAP_EN		0x1
+
+#define HAL_asb_priority(level) \
+*(volatile unsigned *)ASA_PRI_REG = __cpu_to_le32(level)
+
+#define HAL_aram_priority(level) \
+*(volatile unsigned *)ASA_ARAM_PRI_REG = __cpu_to_le32(level)
+
+#define HAL_aram_arbitration(arbitration_mask) \
+*(volatile unsigned *)ASA_ARAM_TC_CR_REG |= __cpu_to_le32(arbitration_mask)
+
+#define HAL_aram_defmaster(mask) \
+*(volatile unsigned *)ASA_ARAM_TC_CR_REG = (*(volatile unsigned *)ASA_TC_CR_REG & __cpu_to_le32(0xFFFF)) | __cpu_to_le32(mask << 24)
+////////////////////////////////////////////////////////////
+// INTC block						  //
+////////////////////////////////////////////////////////////
+
+#define INTC_ARM1_CONTROL_REG	(INTC_BASEADDR + 0x18)
+
+
+
+////////////////////////////////////////////////////////////
+// TIMER block						  //
+////////////////////////////////////////////////////////////
+
+#define TIMER0_CNTR_REG		(TIMER_BASEADDR + 0x00)
+#define TIMER0_CURR_COUNT	(TIMER_BASEADDR + 0x04)
+#define TIMER1_CNTR_REG		(TIMER_BASEADDR + 0x08)
+#define TIMER1_CURR_COUNT	(TIMER_BASEADDR + 0x0C)
+
+#define TIMER2_CNTR_REG		(TIMER_BASEADDR + 0x18)
+#define TIMER2_LBOUND_REG	(TIMER_BASEADDR + 0x10)
+#define TIMER2_HBOUND_REG	(TIMER_BASEADDR + 0x14)
+#define TIMER2_CURR_COUNT	(TIMER_BASEADDR + 0x1C)
+
+#define TIMER3_LOBND		(TIMER_BASEADDR + 0x20)
+#define TIMER3_HIBND		(TIMER_BASEADDR + 0x24)
+#define TIMER3_CTRL		(TIMER_BASEADDR + 0x28)
+#define TIMER3_CURR_COUNT	(TIMER_BASEADDR + 0x2C)
+
+#define TIMER_MASK		(TIMER_BASEADDR + 0x40)
+#define TIMER_STATUS		(TIMER_BASEADDR + 0x50)
+#define TIMER_ACK		(TIMER_BASEADDR + 0x50)
+#define TIMER_WDT_HIGH_BOUND	(TIMER_BASEADDR + 0xD0)
+#define TIMER_WDT_CONTROL	(TIMER_BASEADDR + 0xD4)
+
+
+////////////////////////////////////////////////////////////
+//  EBUS block											    //
+////////////////////////////////////////////////////////////
+
+#define EX_SWRST_REG		(EBUS_BASEADDR + 0x00)
+#define EX_CSEN_REG		(EBUS_BASEADDR + 0x04)
+#define EX_CS0_SEG_REG		(EBUS_BASEADDR + 0x08)
+#define EX_CS1_SEG_REG		(EBUS_BASEADDR + 0x0C)
+#define EX_CS2_SEG_REG		(EBUS_BASEADDR + 0x10)
+#define EX_CS3_SEG_REG		(EBUS_BASEADDR + 0x14)
+#define EX_CS4_SEG_REG		(EBUS_BASEADDR + 0x18)
+#define EX_CS0_CFG_REG		(EBUS_BASEADDR + 0x1C)
+#define EX_CS1_CFG_REG		(EBUS_BASEADDR + 0x20)
+#define EX_CS2_CFG_REG		(EBUS_BASEADDR + 0x24)
+#define EX_CS3_CFG_REG		(EBUS_BASEADDR + 0x28)
+#define EX_CS4_CFG_REG		(EBUS_BASEADDR + 0x2C)
+#define EX_CS0_TMG1_REG		(EBUS_BASEADDR + 0x30)
+#define EX_CS1_TMG1_REG		(EBUS_BASEADDR + 0x34)
+#define EX_CS2_TMG1_REG		(EBUS_BASEADDR + 0x38)
+#define EX_CS3_TMG1_REG		(EBUS_BASEADDR + 0x3C)
+#define EX_CS4_TMG1_REG		(EBUS_BASEADDR + 0x40)
+#define EX_CS0_TMG2_REG		(EBUS_BASEADDR + 0x44)
+#define EX_CS1_TMG2_REG		(EBUS_BASEADDR + 0x48)
+#define EX_CS2_TMG2_REG		(EBUS_BASEADDR + 0x4C)
+#define EX_CS3_TMG2_REG		(EBUS_BASEADDR + 0x50)
+#define EX_CS4_TMG2_REG		(EBUS_BASEADDR + 0x54)
+#define EX_CS0_TMG3_REG		(EBUS_BASEADDR + 0x58)
+#define EX_CS1_TMG3_REG		(EBUS_BASEADDR + 0x5C)
+#define EX_CS2_TMG3_REG		(EBUS_BASEADDR + 0x60)
+#define EX_CS3_TMG3_REG		(EBUS_BASEADDR + 0x64)
+#define EX_CS4_TMG3_REG		(EBUS_BASEADDR + 0x68)
+#define EX_CLOCK_DIV_REG	(EBUS_BASEADDR + 0x6C)
+#define EX_MFSM_REG		(EBUS_BASEADDR + 0x100)
+#define EX_CSFSM_REG		(EBUS_BASEADDR + 0x104)
+#define EX_WRFSM_REG		(EBUS_BASEADDR + 0x108)
+#define EX_RDFSM_REG		(EBUS_BASEADDR + 0x10C)
+
+#define EX_CLK_EN		0x00000001
+#define EX_CSBOOT_EN		0x00000002
+#define EX_CS0_EN		0x00000002
+#define EX_CS1_EN		0x00000004
+#define EX_CS2_EN		0x00000008
+#define EX_CS3_EN		0x00000010
+#define EX_CS4_EN		0x00000020
+
+#define EX_MEM_BUS_8		0x00000000
+#define EX_MEM_BUS_16		0x00000002
+#define EX_MEM_BUS_32		0x00000004
+#define EX_CS_HIGH		0x00000008
+#define EX_WE_HIGH		0x00000010
+#define EX_RE_HIGH		0x00000020
+#define EX_ALE_MODE		0x00000040
+#define EX_STRB_MODE		0x00000080
+#define EX_DM_MODE		0x00000100
+#define EX_NAND_MODE		0x00000200
+#define EX_RDY_EN		0x00000400
+#define EX_RDY_EDGE		0x00000800
+
+
+////////////////////////////////////////////////////////////
+//  GPIO block												     //
+////////////////////////////////////////////////////////////
+
+#define GPIO_OUTPUT_REG		(GPIO_BASEADDR + 0x00)	// GPIO outputs register
+#define GPIO_OE_REG		(GPIO_BASEADDR + 0x04)	// GPIO Output Enable register
+#define GPIO_HI_INT_ENABLE_REG	(GPIO_BASEADDR + 0x08)
+#define GPIO_LO_INT_ENABLE_REG	(GPIO_BASEADDR + 0x0C)
+#define GPIO_INPUT_REG		(GPIO_BASEADDR + 0x10)	// GPIO input register
+#define APB_ACCESS_WS_REG	(GPIO_BASEADDR + 0x14)
+#define MUX_CONF_REG		(GPIO_BASEADDR + 0x18)
+#define SYSCONF_REG		(GPIO_BASEADDR + 0x1C)
+#define GPIO_ARM_ID_REG		(GPIO_BASEADDR + 0x30)
+#define GPIO_BOOTSTRAP_REG	(GPIO_BASEADDR + 0x40)
+#define GPIO_LOCK_REG		(GPIO_BASEADDR + 0x38)
+#define GPIO_IOCTRL_REG		(GPIO_BASEADDR + 0x44)
+#define GPIO_DEVID_REG		(GPIO_BASEADDR + 0x50)
+
+#define GPIO_IOCTRL_A15A16	0x00000001
+#define GPIO_IOCTRL_A17A18	0x00000002
+#define GPIO_IOCTRL_A19A21	0x00000004
+#define GPIO_IOCTRL_TMREVT0	0x00000008
+#define GPIO_IOCTRL_TMREVT1	0x00000010
+#define GPIO_IOCTRL_GPBT3	0x00000020
+#define GPIO_IOCTRL_I2C		0x00000040
+#define GPIO_IOCTRL_UART0	0x00000080
+#define GPIO_IOCTRL_UART1	0x00000100
+#define GPIO_IOCTRL_SPI		0x00000200
+#define GPIO_IOCTRL_HBMODE	0x00000400
+
+#define GPIO_IOCTRL_VAL		0x55555555
+
+#define GPIO_0			0x01
+#define GPIO_1			0x02
+#define GPIO_2			0x04
+#define GPIO_3			0x08
+#define GPIO_4			0x10
+#define GPIO_5			0x20
+#define GPIO_6			0x40
+#define GPIO_7			0x80
+
+#define GPIO_RISING_EDGE	1
+#define GPIO_FALLING_EDGE	2
+#define GPIO_BOTH_EDGES		3
+
+
+////////////////////////////////////////////////////////////
+// UART													    //
+////////////////////////////////////////////////////////////
+
+#define UART_RBR		(UART_BASEADDR + 0x00)
+#define UART_THR		(UART_BASEADDR + 0x00)
+#define UART_DLL		(UART_BASEADDR + 0x00)
+#define UART_IER		(UART_BASEADDR + 0x04)
+#define UART_DLH		(UART_BASEADDR + 0x04)
+#define UART_IIR		(UART_BASEADDR + 0x08)
+#define UART_FCR		(UART_BASEADDR + 0x08)
+#define UART_LCR		(UART_BASEADDR + 0x0C)
+#define UART_MCR		(UART_BASEADDR + 0x10)
+#define UART_LSR		(UART_BASEADDR + 0x14)
+#define UART_MSR		(UART_BASEADDR + 0x18)
+#define UART_SCR		(UART_BASEADDR + 0x1C)
+
+////////////////////////////////////////////////////////////
+// CLK  + RESET block 
+////////////////////////////////////////////////////////////
+
+#define CLKCORE_ARM_CLK_CNTRL	(CLKCORE_BASEADDR + 0x00)
+#define CLKCORE_AHB_CLK_CNTRL	(CLKCORE_BASEADDR + 0x04)
+#define CLKCORE_PLL_STATUS	(CLKCORE_BASEADDR + 0x08)
+#define CLKCORE_CLKDIV_CNTRL	(CLKCORE_BASEADDR + 0x0C)
+#define CLKCORE_TDM_CLK_CNTRL	(CLKCORE_BASEADDR + 0x10)
+#define CLKCORE_FSYNC_CNTRL	(CLKCORE_BASEADDR + 0x14)
+#define CLKCORE_CLK_PWR_DWN	(CLKCORE_BASEADDR + 0x18)
+#define CLKCORE_RNG_CNTRL	(CLKCORE_BASEADDR + 0x1C)
+#define CLKCORE_RNG_STATUS	(CLKCORE_BASEADDR + 0x20)
+#define CLKCORE_ARM_CLK_CNTRL2	(CLKCORE_BASEADDR + 0x24)
+#define CLKCORE_TDM_REF_DIV_RST	(CLKCORE_BASEADDR + 0x40)
+
+#define ARM_PLL_BY_CTRL		0x80000000
+#define ARM_AHB_BYP		0x04000000
+#define PLL_DISABLE		0x02000000
+#define PLL_CLK_BYPASS		0x01000000
+
+#define AHB_PLL_BY_CTRL		0x80000000
+#define DIV_BYPASS		0x40000000
+#define SYNC_MODE		0x20000000
+
+#define EPHY_CLKDIV_BYPASS	0x00200000
+#define EPHY_CLKDIV_RATIO_SHIFT	16
+#define PUI_CLKDIV_BYPASS	0x00004000
+#define PUI_CLKDIV_SRCCLK	0x00002000
+#define PUI_CLKDIV_RATIO_SHIFT	8
+#define PCI_CLKDIV_BYPASS	0x00000020
+#define PCI_CLKDIV_RATIO_SHIFT	0
+
+#define ARM0_CLK_PD		0x00200000
+#define ARM1_CLK_PD		0x00100000
+#define EPHY_CLK_PD		0x00080000
+#define TDM_CLK_PD		0x00040000
+#define PUI_CLK_PD		0x00020000
+#define PCI_CLK_PD		0x00010000
+#define MDMA_AHBCLK_PD		0x00000400
+#define I2CSPI_AHBCLK_PD	0x00000200
+#define UART_AHBCLK_PD		0x00000100
+#define IPSEC_AHBCLK_PD		0x00000080
+#define TDM_AHBCLK_PD		0x00000040
+#define USB1_AHBCLK_PD		0x00000020
+#define USB0_AHBCLK_PD		0x00000010
+#define GEMAC1_AHBCLK_PD	0x00000008
+#define GEMAC0_AHBCLK_PD	0x00000004
+#define PUI_AHBCLK_PD		0x00000002
+#define HIF_AHBCLK_PD		0x00000001
+
+#define ARM1_DIV_BP		0x00001000
+#define ARM1_DIV_VAL_SHIFT	8
+#define ARM0_DIV_BP		0x00000010
+#define ARM0_DIV_VAL_SHIFT	0
+
+#define AHBCLK_PLL_LOCK		0x00000002
+#define FCLK_PLL_LOCK		0x00000001
+
+
+// reset block
+#define BLOCK_RESET_REG		(CLKCORE_BASEADDR + 0x100)
+#define CSP_RESET_REG		(CLKCORE_BASEADDR + 0x104)
+
+#define RNG_RST			0x1000
+#define IPSEC_RST		0x0800
+#define DDR_RST			0x0400
+#define USB1_PHY_RST		0x0200
+#define USB0_PHY_RST		0x0100
+#define USB1_RST		0x0080
+#define USB0_RST		0x0040
+#define GEMAC1_RST		0x0020
+#define GEMAC0_RST		0x0010
+#define TDM_RST			0x0008
+#define PUI_RST			0x0004
+#define HIF_RST			0x0002
+#define PCI_RST			0x0001
+
+////////////////////////////////////////////////////////////////
+//	DDR  CONTROLLER block
+////////////////////////////////////////////////////////////////
+
+#define DDR_CONFIG_BASEADDR	0x0D000000
+#define DENALI_CTL_00_DATA	(DDR_CONFIG_BASEADDR + 0x00)
+#define DENALI_CTL_01_DATA	(DDR_CONFIG_BASEADDR + 0x08)
+#define DENALI_CTL_02_DATA	(DDR_CONFIG_BASEADDR + 0x10)
+#define DENALI_CTL_03_DATA	(DDR_CONFIG_BASEADDR + 0x18)
+#define DENALI_CTL_04_DATA	(DDR_CONFIG_BASEADDR + 0x20)
+#define DENALI_CTL_05_DATA	(DDR_CONFIG_BASEADDR + 0x28)
+#define DENALI_CTL_06_DATA	(DDR_CONFIG_BASEADDR + 0x30)
+#define DENALI_CTL_07_DATA	(DDR_CONFIG_BASEADDR + 0x38)
+#define DENALI_CTL_08_DATA	(DDR_CONFIG_BASEADDR + 0x40)
+#define DENALI_CTL_09_DATA	(DDR_CONFIG_BASEADDR + 0x48)
+#define DENALI_CTL_10_DATA	(DDR_CONFIG_BASEADDR + 0x50)
+#define DENALI_CTL_11_DATA	(DDR_CONFIG_BASEADDR + 0x58)
+#define DENALI_CTL_12_DATA	(DDR_CONFIG_BASEADDR + 0x60)
+#define DENALI_CTL_13_DATA	(DDR_CONFIG_BASEADDR + 0x68)
+#define DENALI_CTL_14_DATA	(DDR_CONFIG_BASEADDR + 0x70)
+#define DENALI_CTL_15_DATA	(DDR_CONFIG_BASEADDR + 0x78)
+#define DENALI_CTL_16_DATA	(DDR_CONFIG_BASEADDR + 0x80)
+#define DENALI_CTL_17_DATA	(DDR_CONFIG_BASEADDR + 0x88)
+#define DENALI_CTL_18_DATA	(DDR_CONFIG_BASEADDR + 0x90)
+#define DENALI_CTL_19_DATA	(DDR_CONFIG_BASEADDR + 0x98)
+#define DENALI_CTL_20_DATA	(DDR_CONFIG_BASEADDR + 0xA0)
+
+#define DENALI_READY_CHECK         *((volatile u32 *) (DDR_CONFIG_BASEADDR + 0x44))
+#define DENALI_WR_DQS               *((volatile u8 *)  (DDR_CONFIG_BASEADDR + 0x5D))
+#define DENALI_DQS_OUT             *((volatile u8 *) (DDR_CONFIG_BASEADDR + 0x5A))
+#define DENALI_DQS_DELAY0      *((volatile u8 *) (DDR_CONFIG_BASEADDR + 0x4F))
+#define DENALI_DQS_DELAY1      *((volatile u8 *)  (DDR_CONFIG_BASEADDR +0x50))
+#define DENALI_DQS_DELAY2      *((volatile u8 *)  (DDR_CONFIG_BASEADDR +0x51))
+#define DENALI_DQS_DELAY3       *((volatile u8 *)  (DDR_CONFIG_BASEADDR +0x52))
+
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #1
+#define DENALI_CTL_00_VAL_CFG1	0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG1	0x0100000100000001LL
+#define DENALI_CTL_02_VAL_CFG1	0x0100010000010100LL
+#define DENALI_CTL_03_VAL_CFG1	0x0102020202020201LL
+#define DENALI_CTL_04_VAL_CFG1	0x0000010100000001LL
+#define DENALI_CTL_05_VAL_CFG1	0x0203010300000101LL
+#define DENALI_CTL_06_VAL_CFG1	0x060a020200020202LL
+#define DENALI_CTL_07_VAL_CFG1	0x0000000300000206LL
+#define DENALI_CTL_08_VAL_CFG1	0x6400003f3f0a0200LL
+#define DENALI_CTL_09_VAL_CFG1	0x1700000000000000LL
+#define DENALI_CTL_10_VAL_CFG1	0x0120202020191a18LL
+#define DENALI_CTL_11_VAL_CFG1	0x433a34124a650a00LL
+#define DENALI_CTL_12_VAL_CFG1	0x0000000000000700LL
+#define DENALI_CTL_13_VAL_CFG1	0x0010002000100080LL	
+#define DENALI_CTL_14_VAL_CFG1	0x0010004000100040LL
+#define DENALI_CTL_15_VAL_CFG1	0x050e000000000000LL
+#define DENALI_CTL_16_VAL_CFG1	0x000000002d890000LL
+#define DENALI_CTL_17_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_18_VAL_CFG1	0x0302000000000000LL
+#define DENALI_CTL_19_VAL_CFG1	0x00001400c8030600LL
+#define DENALI_CTL_20_VAL_CFG1	0x00000000823600c8LL
+
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #2
+#define DENALI_CTL_00_VAL_CFG2	0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG2	0x0100010100000001LL
+#define DENALI_CTL_02_VAL_CFG2	0x0100010000010100LL
+#define DENALI_CTL_03_VAL_CFG2	0x0102020202020201LL
+#define DENALI_CTL_04_VAL_CFG2	0x0000010200000003LL 
+#define DENALI_CTL_05_VAL_CFG2	0x0203010300000101LL
+#define DENALI_CTL_06_VAL_CFG2	0x060a020200020202LL
+#define DENALI_CTL_07_VAL_CFG2	0x0000000300000206LL
+#define DENALI_CTL_08_VAL_CFG2	0x6400003f3f0a0207LL
+#define DENALI_CTL_09_VAL_CFG2	0x1700000000000000LL
+#define DENALI_CTL_10_VAL_CFG2	0x0120202020191a18LL
+#define DENALI_CTL_11_VAL_CFG2	0x433a34164a650a00LL
+#define DENALI_CTL_12_VAL_CFG2	0x0000000000000700LL
+#define DENALI_CTL_13_VAL_CFG2	0x0010002000100080LL
+#define DENALI_CTL_14_VAL_CFG2	0x0010004000100040LL
+#define DENALI_CTL_15_VAL_CFG2	0x050e000000000000LL
+#define DENALI_CTL_16_VAL_CFG2	0x000000002d890000LL
+#define DENALI_CTL_17_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_18_VAL_CFG2	0x0302000000000000LL
+#define DENALI_CTL_19_VAL_CFG2	0x00001700c8030600LL
+#define DENALI_CTL_20_VAL_CFG2	0x00000000423600c8LL
+
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #3
+#define DENALI_CTL_00_VAL_CFG3	0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG3	0x0100010100000001LL
+#define DENALI_CTL_02_VAL_CFG3	0x0100010000010100LL
+#define DENALI_CTL_03_VAL_CFG3	0x0102020202020201LL
+#define DENALI_CTL_04_VAL_CFG3	0x0000010200000003LL 
+#define DENALI_CTL_05_VAL_CFG3	0x0203010300000101LL
+#define DENALI_CTL_06_VAL_CFG3	0x060a020200020202LL
+#define DENALI_CTL_07_VAL_CFG3	0x0000000300000206LL
+#define DENALI_CTL_08_VAL_CFG3	0x6400003f3f0a0207LL
+#define DENALI_CTL_09_VAL_CFG3	0x1700000000000000LL
+#define DENALI_CTL_10_VAL_CFG3	0x0120202020191a18LL
+#define DENALI_CTL_11_VAL_CFG3	0x433a34164a650a00LL
+#define DENALI_CTL_12_VAL_CFG3	0x0000000000000700LL
+#define DENALI_CTL_13_VAL_CFG3	0x0010002000100080LL
+#define DENALI_CTL_14_VAL_CFG3	0x0010004000100040LL
+#define DENALI_CTL_15_VAL_CFG3	0x050e000000000000LL
+#define DENALI_CTL_16_VAL_CFG3	0x000000002d890000LL
+#define DENALI_CTL_17_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_18_VAL_CFG3	0x0302000000000000LL
+#define DENALI_CTL_19_VAL_CFG3	0x00001700c8030600LL
+#define DENALI_CTL_20_VAL_CFG3	0x00000000423600c8LL
+
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #4
+#define DENALI_CTL_00_VAL_CFG4	0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG4	0x0100000100000001LL
+#define DENALI_CTL_02_VAL_CFG4	0x0100010000010100LL
+#define DENALI_CTL_03_VAL_CFG4	0x0102020202020201LL
+#define DENALI_CTL_04_VAL_CFG4	0x0000010100000001LL
+#define DENALI_CTL_05_VAL_CFG4	0x0203010300010101LL
+#define DENALI_CTL_06_VAL_CFG4	0x060a020200020202LL
+#define DENALI_CTL_07_VAL_CFG4	0x0000000300000206LL
+#define DENALI_CTL_08_VAL_CFG4	0x6400003f3f0a0200LL
+#define DENALI_CTL_09_VAL_CFG4	0x1700000000000000LL
+#define DENALI_CTL_10_VAL_CFG4	0x0120202020191a18LL
+#define DENALI_CTL_11_VAL_CFG4	0x433a34124a650a00LL
+#define DENALI_CTL_12_VAL_CFG4	0x0000000000000700LL
+#define DENALI_CTL_13_VAL_CFG4	0x0010002000100080LL
+#define DENALI_CTL_14_VAL_CFG4	0x0010004000100040LL
+#define DENALI_CTL_15_VAL_CFG4	0x050e000000000000LL
+#define DENALI_CTL_16_VAL_CFG4	0x000000002d890000LL
+#define DENALI_CTL_17_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_18_VAL_CFG4	0x0302000000000000LL
+#define DENALI_CTL_19_VAL_CFG4	0x00001400c8030600LL
+#define DENALI_CTL_20_VAL_CFG4	0x00000000423600c8LL
+
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #5
+#define DENALI_CTL_00_VAL_CFG5	0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG5	0x0100000100000001LL
+#define DENALI_CTL_02_VAL_CFG5	0x0100010000010100LL
+#define DENALI_CTL_03_VAL_CFG5	0x0102020202020201LL
+#define DENALI_CTL_04_VAL_CFG5	0x0000010100000001LL
+#define DENALI_CTL_05_VAL_CFG5	0x0203020300010101LL
+#define DENALI_CTL_06_VAL_CFG5	0x060a020200020202LL
+#define DENALI_CTL_07_VAL_CFG5	0x0000000300000206LL
+#define DENALI_CTL_08_VAL_CFG5	0x6400003f3f0a0200LL
+#define DENALI_CTL_09_VAL_CFG5	0x1700000000000000LL
+#define DENALI_CTL_10_VAL_CFG5	0x0120202020191a18LL
+#define DENALI_CTL_11_VAL_CFG5	0x433a340d4a650a00LL
+#define DENALI_CTL_12_VAL_CFG5	0x0000000000000700LL
+#define DENALI_CTL_13_VAL_CFG5	0x0010002000100080LL
+#define DENALI_CTL_14_VAL_CFG5	0x0010004000100040LL
+#define DENALI_CTL_15_VAL_CFG5	0x050e000000000000LL
+#define DENALI_CTL_16_VAL_CFG5	0x000000002d890000LL
+#define DENALI_CTL_17_VAL_CFG5	0x0000000000000000LL
+#define DENALI_CTL_18_VAL_CFG5	0x0302000000000000LL
+#define DENALI_CTL_19_VAL_CFG5	0x00000f00c8030600LL
+#define DENALI_CTL_20_VAL_CFG5	0x00000000423600c8LL
+
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #6
+#define DENALI_CTL_00_VAL_CFG6	0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG6	0x0100000100000001LL
+#define DENALI_CTL_02_VAL_CFG6	0x0100010000010100LL
+#define DENALI_CTL_03_VAL_CFG6	0x0102020202020201LL
+#define DENALI_CTL_04_VAL_CFG6	0x0000010200000001LL
+#define DENALI_CTL_05_VAL_CFG6	0x0203010300000101LL
+#define DENALI_CTL_06_VAL_CFG6	0x060a020200020202LL
+#define DENALI_CTL_07_VAL_CFG6	0x0000000300000206LL
+#define DENALI_CTL_08_VAL_CFG6	0x6400003f3f0a0200LL
+#define DENALI_CTL_09_VAL_CFG6	0x1700000000000000LL
+#define DENALI_CTL_10_VAL_CFG6	0x0120202020191a18LL
+#define DENALI_CTL_11_VAL_CFG6	0x433a34124a650a00LL
+#define DENALI_CTL_12_VAL_CFG6	0x0000000000000700LL
+#define DENALI_CTL_13_VAL_CFG6	0x0010002000100080LL	
+#define DENALI_CTL_14_VAL_CFG6	0x0010004000100040LL
+#define DENALI_CTL_15_VAL_CFG6	0x050e000000000000LL
+#define DENALI_CTL_16_VAL_CFG6	0x000000002d890000LL
+#define DENALI_CTL_17_VAL_CFG6	0x0000000000000000LL
+#define DENALI_CTL_18_VAL_CFG6	0x0302000000000000LL
+#define DENALI_CTL_19_VAL_CFG6	0x00001400c8030600LL
+#define DENALI_CTL_20_VAL_CFG6	0x00000000423600c8LL
+
+
+/* For 125 MHz AHB clock speed for CONFIG #9 (Similar to Config #4) */
+#define DENALI_CTL_07_VAL_CFG4_C50      0x0000000200000206LL
+#define DENALI_CTL_08_VAL_CFG4_C50      0x6400003f3f070200LL
+#define DENALI_CTL_11_VAL_CFG4_C50      0x323a340e4a650a00LL
+#define DENALI_CTL_12_VAL_CFG4_C50      0x0000000000000500LL
+#define DENALI_CTL_15_VAL_CFG4_C50      0x03c8000000000000LL
+#define DENALI_CTL_16_VAL_CFG4_C50      0x0000000022240000LL
+#define DENALI_CTL_18_VAL_CFG4_C50      0x0202000001000000LL
+#define DENALI_CTL_19_VAL_CFG4_C50      0x00000f00c8020400LL
+#define DENALI_CTL_20_VAL_CFG4_C50      0x0000000061a800c8LL
+
+/* DENALI CONFIGRATION FOR BOARD CONFIG #10
+ * C50 Router Board */
+#define DENALI_CTL_00_VAL_CFG10		0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG10		0x0100010100000001LL /* EIGHT_BANK_MODE[40]=0x1 */
+#define DENALI_CTL_02_VAL_CFG10		0x0100010000010100LL
+#define DENALI_CTL_03_VAL_CFG10 	0x0102020202020201LL
+#define DENALI_CTL_04_VAL_CFG10 	0x0000010100000001LL
+#define DENALI_CTL_05_VAL_CFG10 	0x0203010300010101LL
+#define DENALI_CTL_06_VAL_CFG10 	0x060a020200020202LL
+#define DENALI_CTL_07_VAL_CFG10 	0x0000000300000206LL
+#define DENALI_CTL_08_VAL_CFG10 	0x6400003f3f0a0207LL /* TFAW [0:4]=0x7 */
+#define DENALI_CTL_09_VAL_CFG10 	0x1700000000000000LL
+#define DENALI_CTL_10_VAL_CFG10 	0x0120202020191a18LL
+#define DENALI_CTL_11_VAL_CFG10 	0x433a34104a650a00LL /* TRFC [39:32]=0x10 */
+#define DENALI_CTL_12_VAL_CFG10 	0x0000000000000700LL
+#define DENALI_CTL_13_VAL_CFG10 	0x0010002000100080LL
+#define DENALI_CTL_14_VAL_CFG10 	0x0010004000100040LL
+#define DENALI_CTL_15_VAL_CFG10 	0x050e000000000000LL
+#define DENALI_CTL_16_VAL_CFG10 	0x000000002d890000LL
+#define DENALI_CTL_17_VAL_CFG10 	0x0000000000000000LL
+#define DENALI_CTL_18_VAL_CFG10 	0x0302000001000000LL /* REDUC [24]= 0x1 */
+#define DENALI_CTL_19_VAL_CFG10 	0x00001200c8030600LL /* TXSNR [55:40]=0x12 */
+#define DENALI_CTL_20_VAL_CFG10 	0x00000000423600c8LL
+
+
+#define WRITE_VAL_U8                   *((volatile u8 *)   0x80000000)
+#define WRITE_VAL_U16                 *((volatile u16 *)  0x80000000)
+#define WRITE_VAL_U32                 *((volatile u32 *)  0x80000000)
+#define WRITE_VAL_U64                 *((volatile u64 *)  0x80000000)
+
+#define AHB_MAX_MEM_REG                *((volatile u64 *)  0x10060010)
+
+#define REDUC                          *((volatile u64 *)(DDR_CONFIG_BASEADDR +  0x90))
+#define CS_MAP                         *((volatile u64 *)(DDR_CONFIG_BASEADDR +0x20))
+
+#define BOARD_MASK 0x1C00
+#define BOARD1     1024
+#define BOARD2     2048
+#define BOARD3     3072
+#define BOARD4     4096
+#define BOARD5     5120
+#define BOARD6     6144
+    
+#define LOW_WR_DQS        0x3A //0x20
+#define HIGH_WR_DQS       0x50 //0x80
+
+#define LOW_DQS_OUT       0x60 //0x55
+#define HIGH_DQS_OUT      0x70 //0x75
+
+#define LOW_RD0           0x10
+#define HIGH_RD0          0x25
+#define LOW_RD1           0x10
+#define HIGH_RD1          0x25
+#define LOW_RD2           0x10
+#define HIGH_RD2          0x25
+#define LOW_RD3           0x10
+#define HIGH_RD3          0x25
+
+
+#define LOW_DQS_DELAY0    0x10
+#define HIGH_DQS_DELAY0   0x25
+
+#define LOW_DQS_DELAY1    0x10
+#define HIGH_DQS_DELAY1   0x25
+
+#define LOW_DQS_DELAY2    0x10
+#define HIGH_DQS_DELAY2   0x25
+
+#define LOW_DQS_DELAY3    0x10
+#define HIGH_DQS_DELAY3   0x25
+
+#endif
+
+/* end of file comcerto_1xx.h */

include/asm-arm/arch-comcerto/comcerto_1000.h

diff --git a/include/asm-arm/arch-comcerto/comcerto_1000.h b/include/asm-arm/arch-comcerto/comcerto_1000.h
new file mode 100644
index 0000000..afad346
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/comcerto_1000.h
@@ -0,0 +1,476 @@
+#ifndef __COMCERTO_1000_H__
+#define __COMCERTO_1000_H__
+
+/* to be moved somewhere else */
+#include <asm/arch/bits.h>
+
+
+/* memcore */
+/* device memory base addresses */
+// device memory sizes
+#define ARAM_SIZE		0x00020000 /* 128K */
+#define ARAM_BASEADDR		0x0A000000
+
+/* Hardware Interface Units */
+#define APB_BASEADDR		0x10000000
+#define APB_SIZE		0x01000000 /* 16M address range */
+
+#define EXP_CS0_BASEADDR	0x20000000
+#define EXP_CS1_BASEADDR	0x24000000
+#define EXP_CS2_BASEADDR	0x28000000
+#define EXP_CS3_BASEADDR	0x2C000000
+#define EXP_CS4_BASEADDR	0x30000000
+
+#define DDR_BASEADDR		0x80000000
+
+#define TDM_BASEADDR		(APB_BASEADDR + 0x000000)
+#define TDMA_BASEADDR		(APB_BASEADDR + 0x020000)
+#define AHB_BASEADDR		(APB_BASEADDR + 0x040000)
+#define TIMER_BASEADDR		(APB_BASEADDR + 0x050000)
+#define PCIE_PHY_BASEADDR	(APB_BASEADDR + 0x060000)
+#define GPIO_BASEADDR		(APB_BASEADDR + 0x070000)
+#define UART0_BASEADDR		(APB_BASEADDR + 0x090000)
+#define UART1_BASEADDR		(APB_BASEADDR + 0x094000)
+#define SPI_BASEADDR		(APB_BASEADDR + 0x098000)
+#define I2C_BASEADDR		(APB_BASEADDR + 0x09C000)
+#define INTC_BASEADDR		(APB_BASEADDR + 0x0A0000)
+#define CLKCORE_BASEADDR	(APB_BASEADDR + 0x0B0000)
+#define GEMAC_BASEADDR		(APB_BASEADDR + 0x0D0000)
+#define MEMCORE_BASEADDR	(APB_BASEADDR + 0x0F0000)
+#define GEMAC1_BASEADDR		(APB_BASEADDR + 0x190000)
+#define EBUS_BASEADDR		(APB_BASEADDR + 0x1A0000)
+#define MDMA_BASEADDR		(APB_BASEADDR + 0x1E0000)
+
+
+////////////////////////////////////////////////////////////
+// 	SPI block												    //
+////////////////////////////////////////////////////////////
+
+#define SPI_CTRLR0_REG		(SPI_BASEADDR+0x00)
+#define SPI_CTRLR1_REG		(SPI_BASEADDR+0x04)
+#define SPI_SSIENR_REG		(SPI_BASEADDR+0x08)
+#define SPI_MWCR_REG		(SPI_BASEADDR+0x0c)
+#define SPI_SER_REG		(SPI_BASEADDR+0x10)
+#define SPI_BAUDR_REG		(SPI_BASEADDR+0x14)
+#define SPI_TXFTLR_REG		(SPI_BASEADDR+0x18)
+#define SPI_RXFTLR_REG		(SPI_BASEADDR+0x1c)
+#define SPI_TXFLR_REG		(SPI_BASEADDR+0x20)
+#define SPI_RXFLR_REG		(SPI_BASEADDR+0x24)
+#define SPI_SR_REG		(SPI_BASEADDR+0x28)
+#define SPI_IMR_REG		(SPI_BASEADDR+0x2c)
+#define SPI_ISR_REG		(SPI_BASEADDR+0x30)
+#define SPI_RISR_REG		(SPI_BASEADDR+0x34)
+#define SPI_TXOICR_REG		(SPI_BASEADDR+0x38)
+#define SPI_RXOICR_REG		(SPI_BASEADDR+0x3c)
+#define SPI_RXUICR_REG		(SPI_BASEADDR+0x40)
+#define SPI_MSTICR_REG		(SPI_BASEADDR+0x44)
+#define SPI_ICR_REG		(SPI_BASEADDR+0x48)
+#define SPI_IDR_REG		(SPI_BASEADDR+0x58)
+#define SPI_DR_REG		(SPI_BASEADDR+0x60)
+
+////////////////////////////////////////////////////////////
+//	AHB block											    //
+////////////////////////////////////////////////////////////
+#define AHB_LOWMEM_REMAP_CTRL		(AHB_BASEADDR + 0x00)
+#define AHB_HIGHMEM_ADDR_TRANSLATION	(AHB_BASEADDR + 0x04)
+#define AHB_STAGE2_ARBITER_CFG		(AHB_BASEADDR + 0x08)
+
+////////////////////////////////////////////////////////////
+// INTC block											    //
+////////////////////////////////////////////////////////////
+
+#define INTC_ARM1_CONTROL_REG	(INTC_BASEADDR + 0x18)
+
+
+
+////////////////////////////////////////////////////////////
+// TIMER block											    //
+////////////////////////////////////////////////////////////
+
+#define TIMER0_CNTR_REG		(TIMER_BASEADDR + 0x00)
+#define TIMER0_CURR_COUNT	(TIMER_BASEADDR + 0x04)
+#define TIMER1_CNTR_REG		(TIMER_BASEADDR + 0x08)
+#define TIMER1_CURR_COUNT	(TIMER_BASEADDR + 0x0C)
+
+#define TIMER2_CNTR_REG		(TIMER_BASEADDR + 0x18)
+#define TIMER2_LBOUND_REG	(TIMER_BASEADDR + 0x10)
+#define TIMER2_HBOUND_REG	(TIMER_BASEADDR + 0x14)
+#define TIMER2_CURR_COUNT	(TIMER_BASEADDR + 0x1C)
+
+#define TIMER3_LOBND            (TIMER_BASEADDR + 0x20)
+#define TIMER3_HIBND            (TIMER_BASEADDR + 0x24)
+#define TIMER3_CTRL             (TIMER_BASEADDR + 0x28)
+#define TIMER3_CURR_COUNT       (TIMER_BASEADDR + 0x2C)
+
+#define TIMER_MASK              (TIMER_BASEADDR + 0x40)
+#define TIMER_STATUS            (TIMER_BASEADDR + 0x50)
+#define TIMER_ACK               (TIMER_BASEADDR + 0x50)
+#define TIMER_WDT_HIGH_BOUND	(TIMER_BASEADDR + 0xD0)
+#define TIMER_WDT_CONTROL	(TIMER_BASEADDR + 0xD4)
+
+
+////////////////////////////////////////////////////////////
+//  EBUS block											    //
+////////////////////////////////////////////////////////////
+
+#define EX_SWRST_REG		(EBUS_BASEADDR + 0x00)
+#define EX_CSEN_REG		(EBUS_BASEADDR + 0x04)
+#define EX_CS0_SEG_REG		(EBUS_BASEADDR + 0x08)
+#define EX_CS1_SEG_REG		(EBUS_BASEADDR + 0x0C)
+#define EX_CS2_SEG_REG		(EBUS_BASEADDR + 0x10)
+#define EX_CS3_SEG_REG		(EBUS_BASEADDR + 0x14)
+#define EX_CS4_SEG_REG		(EBUS_BASEADDR + 0x18)
+#define EX_CS0_CFG_REG		(EBUS_BASEADDR + 0x1C)
+#define EX_CS1_CFG_REG		(EBUS_BASEADDR + 0x20)
+#define EX_CS2_CFG_REG		(EBUS_BASEADDR + 0x24)
+#define EX_CS3_CFG_REG		(EBUS_BASEADDR + 0x28)
+#define EX_CS4_CFG_REG		(EBUS_BASEADDR + 0x2C)
+#define EX_CS0_TMG1_REG		(EBUS_BASEADDR + 0x30)
+#define EX_CS1_TMG1_REG		(EBUS_BASEADDR + 0x34)
+#define EX_CS2_TMG1_REG		(EBUS_BASEADDR + 0x38)
+#define EX_CS3_TMG1_REG		(EBUS_BASEADDR + 0x3C)
+#define EX_CS4_TMG1_REG		(EBUS_BASEADDR + 0x40)
+#define EX_CS0_TMG2_REG		(EBUS_BASEADDR + 0x44)
+#define EX_CS1_TMG2_REG		(EBUS_BASEADDR + 0x48)
+#define EX_CS2_TMG2_REG		(EBUS_BASEADDR + 0x4C)
+#define EX_CS3_TMG2_REG		(EBUS_BASEADDR + 0x50)
+#define EX_CS4_TMG2_REG		(EBUS_BASEADDR + 0x54)
+#define EX_CS0_TMG3_REG		(EBUS_BASEADDR + 0x58)
+#define EX_CS1_TMG3_REG		(EBUS_BASEADDR + 0x5C)
+#define EX_CS2_TMG3_REG		(EBUS_BASEADDR + 0x60)
+#define EX_CS3_TMG3_REG		(EBUS_BASEADDR + 0x64)
+#define EX_CS4_TMG3_REG		(EBUS_BASEADDR + 0x68)
+#define EX_CLOCK_DIV_REG	(EBUS_BASEADDR + 0x6C)
+#define EX_MFSM_REG		(EBUS_BASEADDR + 0x100)
+#define EX_CSFSM_REG		(EBUS_BASEADDR + 0x104)
+#define EX_WRFSM_REG		(EBUS_BASEADDR + 0x108)
+#define EX_RDFSM_REG		(EBUS_BASEADDR + 0x10C)
+
+#define EX_CLK_EN		0x00000001
+#define EX_CSBOOT_EN		0x00000002
+#define EX_CS0_EN		0x00000002
+#define EX_CS1_EN		0x00000004
+#define EX_CS2_EN		0x00000008
+#define EX_CS3_EN		0x00000010
+#define EX_CS4_EN		0x00000020
+
+#define EX_MEM_BUS_8		0x00000000
+#define EX_MEM_BUS_16		0x00000002
+#define EX_MEM_BUS_32		0x00000004
+#define EX_CS_HIGH		0x00000008
+#define EX_WE_HIGH		0x00000010
+#define EX_RE_HIGH		0x00000020
+#define EX_ALE_MODE		0x00000040
+#define EX_STRB_MODE		0x00000080
+#define EX_DM_MODE		0x00000100
+#define EX_NAND_MODE		0x00000200
+#define EX_RDY_EN		0x00000400
+#define EX_RDY_EDGE		0x00000800
+
+#define CSx_CFG_BUS_SZ_16      0x2
+
+
+////////////////////////////////////////////////////////////
+//  GPIO block												     //
+////////////////////////////////////////////////////////////
+
+#define GPIO_OUTPUT_REG			(GPIO_BASEADDR + 0x00)	// GPIO outputs register
+#define GPIO_OE_REG			(GPIO_BASEADDR + 0x04)	// GPIO Output Enable register
+#define GPIO_CONFIG_IRQ_REG		(GPIO_BASEADDR + 0x08)
+#define GPIO_UP_ALIGN_ACCESS_LOGIC	(GPIO_BASEADDR + 0x0C)
+#define GPIO_INPUT_REG			(GPIO_BASEADDR + 0x10)	// GPIO input register
+#define APB_ACCESS_WS_REG		(GPIO_BASEADDR + 0x14)
+#define USB_PHY_CONF_REG		(GPIO_BASEADDR + 0x18)
+#define SYSCONF_REG			(GPIO_BASEADDR + 0x1C)
+#define GPIO_ARM_ID_REG			(GPIO_BASEADDR + 0x30)
+#define GPIO_GENERIC_PAD_CONTROL	(GPIO_BASEADDR + 0x34)
+#define GPIO_BOOTSTRAP_STATUS_REG	(GPIO_BASEADDR + 0x40)
+#define GPIO_BOOTSTRAP_OVERRIDE_REG	(GPIO_BASEADDR + 0x44)
+#define GPIO_DEVID_REG			(GPIO_BASEADDR + 0x50)
+#define GPIO_ARM_MEMORY_SENSE_REGS	(GPIO_BASEADDR + 0x54)
+#define GPIO_PIN_SELECT_REG		(GPIO_BASEADDR + 0x58)
+
+
+#define GPIO_PIN_SELECT_UART1	((1 << 22) | (1 << 23))
+
+#define GPIO_0			0x01
+#define GPIO_1			0x02
+#define GPIO_2			0x04
+#define GPIO_3			0x08
+#define GPIO_4			0x10
+#define GPIO_5			0x20
+#define GPIO_6			0x40
+#define GPIO_7			0x80
+
+#define GPIO_RISING_EDGE	1
+#define GPIO_FALLING_EDGE	2
+#define GPIO_BOTH_EDGES		3
+
+
+////////////////////////////////////////////////////////////
+// UART													    //
+////////////////////////////////////////////////////////////
+
+#define UART_RBR		(UART_BASEADDR + 0x00)
+#define UART_THR		(UART_BASEADDR + 0x00)
+#define UART_DLL		(UART_BASEADDR + 0x00)
+#define UART_IER		(UART_BASEADDR + 0x04)
+#define UART_DLH		(UART_BASEADDR + 0x04)
+#define UART_IIR		(UART_BASEADDR + 0x08)
+#define UART_FCR		(UART_BASEADDR + 0x08)
+#define UART_LCR		(UART_BASEADDR + 0x0C)
+#define UART_MCR		(UART_BASEADDR + 0x10)
+#define UART_LSR		(UART_BASEADDR + 0x14)
+#define UART_MSR		(UART_BASEADDR + 0x18)
+#define UART_SCR		(UART_BASEADDR + 0x1C)
+
+////////////////////////////////////////////////////////////
+// CLK  + RESET block 
+////////////////////////////////////////////////////////////
+
+#define CLKCORE_ARM_CLK_CNTRL		(CLKCORE_BASEADDR + 0x00)
+#define CLKCORE_ARM_CLK_CNTRL2		(CLKCORE_BASEADDR + 0x04)
+#define CLKCORE_AHB_CLK_CNTRL		(CLKCORE_BASEADDR + 0x08)
+#define CLKCORE_AHB_CLK_CNTRL2		(CLKCORE_BASEADDR + 0x0C)
+#define CLKCORE_PHY_CLK_CNTRL		(CLKCORE_BASEADDR + 0x10)
+#define CLKCORE_PHY_CLK_CNTRL2		(CLKCORE_BASEADDR + 0x14)
+#define CLKCORE_DDR_PCIE_CLK_CNTRL	(CLKCORE_BASEADDR + 0x18)
+#define CLKCORE_TDM_CLK_CNTRL		(CLKCORE_BASEADDR + 0x1C)
+#define CLKCORE_TDM_CLK_CNTRL2		(CLKCORE_BASEADDR + 0x20)
+#define CLKCORE_FSYNC_CNTRL		(CLKCORE_BASEADDR + 0x24)
+/*	reserved 0x28-0x3C	*/
+#define CLKCORE_CLK_PWR_DWN		(CLKCORE_BASEADDR + 0x40)
+#define CLKCORE_PLL_STATUS		(CLKCORE_BASEADDR + 0x44)
+#define CLKCORE_RNG_CNTRL		(CLKCORE_BASEADDR + 0x48)
+#define CLKCORE_RNG_STATUS		(CLKCORE_BASEADDR + 0x4C)
+
+//Bit fields
+// ARM_CLK_CNTRL register
+#define ARM_CLK_CNTRL_ARM_REF_BYPASS	BIT29
+#define ARM_CLK_CNTRL_PLL_ENSAT		BIT28
+#define ARM_CLK_CNTRL_PLL_FASTEN	BIT27
+#define ARM_CLK_CNTRL_PLL_TEST		BIT26
+#define ARM_CLK_CNTRL_PLL_PWDN		BIT25
+#define ARM_CLK_CNTRL_PLL_BYPASS	BIT24
+
+// ARM_CLK_CNTRL2 register
+#define ARM_CLK_CNTRL2_PLL_RESET	BIT31
+#define ARM_CLK_CNTRL2_ARM1_AHB_BYPASS	BIT13
+#define ARM_CLK_CNTRL2_ARM1_DIV_BYPASS	BIT12
+#define ARM_CLK_CNTRL2_ARM0_AHB_BYPASS	BIT5
+#define ARM_CLK_CNTRL2_ARM0_DIV_BYPASS	BIT4
+
+// AHB_CLK_CNTRL register
+#define AHB_CLK_CNTRL_AHB_REF_BYPASS	BIT31
+#define AHB_CLK_CNTRL_SYNC_DIV_BYPASS	BIT30
+#define AHB_CLK_CNTRL_SYNC_MODE		BIT29
+#define AHB_CLK_CNTRL_PLL_PWDN		BIT25
+#define AHB_CLK_CNTRL_PLL_BYPASS	BIT24
+#define AHB_CLK_CNTRL_PLL_ENSAT		BIT23
+#define AHB_CLK_CNTRL_PLL_FASTEN	BIT22
+
+// AHB_CLK_CNTRL2 register
+#define AHB_CLK_CNTRL2_PLL_RESET	BIT31
+#define AHB_CLK_CNTRL2_PLL_TEST		BIT14
+#define AHB_CLK_CNTRL2_AHB_DIV1_BYPASS	BIT13
+#define AHB_CLK_CNTRL2_AHB_DIV0_BYPASS	BIT12
+
+// PHY_CLK_CNTRL register
+#define PHY_CLK_CNTRL_PHY_REF_BYPASS	BIT29
+#define PHY_CLK_CNTRL_PLL_ENSAT		BIT28
+#define PHY_CLK_CNTRL_PLL_FASTEN	BIT27
+#define PHY_CLK_CNTRL_PLL_TEST		BIT26
+#define PHY_CLK_CNTRL_PLL_PWDN		BIT25
+#define PHY_CLK_CNTRL_PLL_BYPASS	BIT24
+
+// PHY_CLK_CNTRL2 register
+#define PHY_CLK_CNTRL2_PLL_RESET	BIT31
+#define PHY_CLK_CNTRL2_PHY_DIV2_BYPASS	BIT14
+#define PHY_CLK_CNTRL2_PHY_DIV1_BYPASS	BIT13
+#define PHY_CLK_CNTRL2_PHY_DIV0_BYPASS	BIT12
+
+// DDR_PCIE_CLK_CNTRL
+#define DDR_PCIE_CLK_CNTRL_USB_DIV_BYPASS	BIT30
+#define DDR_PCIE_CLK_CNTRL_IPsec_DIV1_BYPASS	BIT29
+#define DDR_PCIE_CLK_CNTRL_IPsec_DIV0_BYPASS	BIT28
+#define DDR_PCIE_CLK_CNTRL_PCIe_DIV_BYPASS	BIT27
+#define DDR_PCIE_CLK_CNTRL_DDR_DIV_BYPASS	BIT26
+#define DDR_PCIE_CLK_CNTRL_USB_MUX_SEL		BIT3
+#define DDR_PCIE_CLK_CNTRL_IPsecMUX_SEL		BIT2
+#define DDR_PCIE_CLK_CNTRL_PCIe_MUX_SEL		BIT1
+#define DDR_PCIE_CLK_CNTRL_DDR_MUX_SEL		BIT0
+
+// TDMCLK_CNTRL
+#define TDMCLK_CNTRL_TDM_CLK_EN		BIT31
+#define TDMCLK_CNTRL_TDM_GEN_BYPASS	BIT30
+
+// TDMCLK_CNTRL2
+#define TDMCLK_CNTRL2_TDM_DIV_BYPASS	BIT24
+#define TDMCLK_CNTRL2_TDM_REF_DIV_RST	BIT0
+
+// FSYNC_CNTRL
+#define FSYNC_CNTRL_FSYNC_EN		BIT29
+#define FSYNC_CNTRL_FSYN_FALL_EDGE	BIT28
+
+// CLK_PWR_DWN
+#define CLK_PWR_DWN_USBREFCLK_PD	BIT24
+#define CLK_PWR_DWN_IPSEC2AHBCLK_PD	BIT23
+#define CLK_PWR_DWN_TDMCLK_PD		BIT22
+#define CLK_PWR_DWN_IPSECAHBCLK_PD	BIT21
+#define CLK_PWR_DWN_I2CAHBCLK_PD	BIT20
+#define CLK_PWR_DWN_USBAHBCLK_PD	BIT19
+#define CLK_PWR_DWN_UARTAHBCLK_PD	BIT18
+#define CLK_PWR_DWN_MDMAAHBCLK_PD	BIT17
+#define CLK_PWR_DWN_TDMAAHBCLK_PD	BIT16
+#define CLK_PWR_DWN_PCIE1AHBCLK_PD	BIT15
+#define CLK_PWR_DWN_PCIE0AHBCLK_PD	BIT14
+#define CLK_PWR_DWN_DDRCTRLAHBCLK_PD	BIT13
+#define CLK_PWR_DWN_GEM1AHBCLK_PD	BIT12
+#define CLK_PWR_DWN_GEM0AHBCLK_PD	BIT11
+#define CLK_PWR_DWN_ARM1AHBCLK_PD	BIT10
+#define CLK_PWR_DWN_ARM0AHBCLK_PD	BIT9
+#define CLK_PWR_DWN_IPSECCORECLK_PD	BIT8
+#define CLK_PWR_DWN_RSVD		BIT7
+#define CLK_PWR_DWN_PCIeREFCLK_NP_PD	BIT6
+#define CLK_PWR_DWN_DDRCLK_PD		BIT5
+#define CLK_PWR_DWN_PHYREFCLK_PD	BIT4
+#define CLK_PWR_DWN_GEM1REFCLK_PD	BIT3
+#define CLK_PWR_DWN_GEM0REFCLK_PD	BIT2
+#define CLK_PWR_DWN_ARM1FCLK_PD		BIT1
+#define CLK_PWR_DWN_ARM0FCLK_PD		BIT0
+
+// PLL_STATUS register
+#define PLL_STATUS_PHY_PLL_STATUS_CLEAR	BIT5
+#define PLL_STATUS_AHB_PLL_STATUS_CLEAR	BIT4
+#define PLL_STATUS_ARM_PLL_STATUS_CLEAR	BIT3
+#define PLL_STATUS_PHY_PLL_STATUS	BIT2
+#define PLL_STATUS_AHB_PLL_STATUS	BIT1
+#define PLL_STATUS_ARM_PLL_STATUS	BIT0
+
+// reset block
+#define CLKCORE_BLK_RESET		(CLKCORE_BASEADDR + 0x100)
+#define CLKCORE_GLBL_SW_RESET		(CLKCORE_BASEADDR + 0x104)
+#define CLKCORE_GLBL_SW_RESET_STATUS	(CLKCORE_BASEADDR + 0x108)
+
+// BLK_RESET register
+#define BLK_RESET_USB_REF_RESET_N		BIT20
+#define BLK_RESET_NO_BAL_DDR_REF_RESET_N	BIT19
+#define BLK_RESET_IPSEC2_AHB_RESET_N		BIT18
+#define BLK_RESET_RNG_RESET_N			BIT17
+#define BLK_RESET_IPSEC_CORE_N			BIT16
+#define BLK_RESET_IPSEC_AHB_RESET_N		BIT15
+#define BLK_RESET_USB_AHB_RESET_N		BIT14
+#define BLK_RESET_TDM_REF_RESET_N		BIT13
+#define BLK_RESET_TDM_AHB_RESET_N		BIT12
+#define BLK_RESET_DDR_REF_RESET_N		BIT11
+#define BLK_RESET_DDR_AHB_RESET_N		BIT10
+#define BLK_RESET_PCIe1_REF_RESET_N		BIT9
+#define BLK_RESET_PCIe0_REF_RESET_N		BIT8
+#define BLK_RESET_PCIe1_AHB_RESET_N		BIT7
+#define BLK_RESET_PCIe0_AHB_RESET_N		BIT6
+#define BLK_RESET_GEMAC1_REF_RESET_N		BIT5
+#define BLK_RESET_GEMAC0_REF_RESET_N		BIT4
+#define BLK_RESET_GEMAC1_AHB_RESET_N		BIT3
+#define BLK_RESET_GEMAC0_AHB_RESET_N		BIT2
+#define BLK_RESET_ARM1_AHB_RESET_N		BIT1
+#define BLK_RESET_ARM0_AHB_RESET_N		BIT0
+
+// GLBL_SW_RESET
+#define GLBL_SW_RESET_N		BIT0
+
+// GLBL_SW_RESET_STATUS
+#define GLBL_SW_RESET_STATUS 	BIT0
+
+////////////////////////////////////////////////////////////////
+//	DDR  CONTROLLER block
+////////////////////////////////////////////////////////////////
+
+#define DDR_CONFIG_BASEADDR	0x0D000000
+#define DENALI_CTL_00_DATA	(DDR_CONFIG_BASEADDR + 0x00)
+#define DENALI_CTL_01_DATA	(DDR_CONFIG_BASEADDR + 0x08)
+#define DENALI_CTL_02_DATA	(DDR_CONFIG_BASEADDR + 0x10)
+#define DENALI_CTL_03_DATA	(DDR_CONFIG_BASEADDR + 0x18)
+#define DENALI_CTL_04_DATA	(DDR_CONFIG_BASEADDR + 0x20)
+#define DENALI_CTL_05_DATA	(DDR_CONFIG_BASEADDR + 0x28)
+#define DENALI_CTL_06_DATA	(DDR_CONFIG_BASEADDR + 0x30)
+#define DENALI_CTL_07_DATA	(DDR_CONFIG_BASEADDR + 0x38)
+#define DENALI_CTL_08_DATA	(DDR_CONFIG_BASEADDR + 0x40)
+#define DENALI_CTL_09_DATA	(DDR_CONFIG_BASEADDR + 0x48)
+#define DENALI_CTL_10_DATA	(DDR_CONFIG_BASEADDR + 0x50)
+#define DENALI_CTL_11_DATA	(DDR_CONFIG_BASEADDR + 0x58)
+#define DENALI_CTL_12_DATA	(DDR_CONFIG_BASEADDR + 0x60)
+#define DENALI_CTL_13_DATA	(DDR_CONFIG_BASEADDR + 0x68)
+#define DENALI_CTL_14_DATA	(DDR_CONFIG_BASEADDR + 0x70)
+#define DENALI_CTL_15_DATA	(DDR_CONFIG_BASEADDR + 0x78)
+#define DENALI_CTL_16_DATA	(DDR_CONFIG_BASEADDR + 0x80)
+#define DENALI_CTL_17_DATA	(DDR_CONFIG_BASEADDR + 0x88)
+#define DENALI_CTL_18_DATA	(DDR_CONFIG_BASEADDR + 0x90)
+#define DENALI_CTL_19_DATA	(DDR_CONFIG_BASEADDR + 0x98)
+#define DENALI_CTL_20_DATA	(DDR_CONFIG_BASEADDR + 0xA0)
+#define DENALI_CTL_21_DATA	(DDR_CONFIG_BASEADDR + 0xA8)
+#define DENALI_CTL_22_DATA	(DDR_CONFIG_BASEADDR + 0xB0)
+#define DENALI_CTL_23_DATA	(DDR_CONFIG_BASEADDR + 0xB8)
+#define DENALI_CTL_24_DATA	(DDR_CONFIG_BASEADDR + 0xC0)
+#define DENALI_CTL_25_DATA	(DDR_CONFIG_BASEADDR + 0xC8)
+#define DENALI_CTL_26_DATA	(DDR_CONFIG_BASEADDR + 0xD0)
+#define DENALI_CTL_27_DATA	(DDR_CONFIG_BASEADDR + 0xD8)
+#define DENALI_CTL_28_DATA	(DDR_CONFIG_BASEADDR + 0xE0)
+#define DENALI_CTL_29_DATA	(DDR_CONFIG_BASEADDR + 0xE8)
+#define DENALI_CTL_30_DATA	(DDR_CONFIG_BASEADDR + 0xF0)
+#define DENALI_CTL_31_DATA	(DDR_CONFIG_BASEADDR + 0xF8)
+#define DENALI_CTL_32_DATA	(DDR_CONFIG_BASEADDR + 0x100)
+#define DENALI_CTL_33_DATA	(DDR_CONFIG_BASEADDR + 0x108)
+#define DENALI_CTL_34_DATA	(DDR_CONFIG_BASEADDR + 0x110)
+#define DENALI_CTL_35_DATA	(DDR_CONFIG_BASEADDR + 0x118)
+#define DENALI_CTL_36_DATA	(DDR_CONFIG_BASEADDR + 0x120)
+#define DENALI_CTL_37_DATA	(DDR_CONFIG_BASEADDR + 0x128)
+#define DENALI_CTL_38_DATA	(DDR_CONFIG_BASEADDR + 0x130)
+#define DENALI_CTL_39_DATA	(DDR_CONFIG_BASEADDR + 0x138)
+#define DENALI_CTL_40_DATA	(DDR_CONFIG_BASEADDR + 0x140)
+#define DENALI_CTL_41_DATA	(DDR_CONFIG_BASEADDR + 0x148)
+#define DENALI_CTL_42_DATA	(DDR_CONFIG_BASEADDR + 0x150)
+#define DENALI_CTL_43_DATA	(DDR_CONFIG_BASEADDR + 0x158)
+#define DENALI_CTL_44_DATA	(DDR_CONFIG_BASEADDR + 0x160)
+#define DENALI_CTL_45_DATA	(DDR_CONFIG_BASEADDR + 0x168)
+#define DENALI_CTL_46_DATA	(DDR_CONFIG_BASEADDR + 0x170)
+#define DENALI_CTL_47_DATA	(DDR_CONFIG_BASEADDR + 0x178)
+#define DENALI_CTL_48_DATA	(DDR_CONFIG_BASEADDR + 0x180)
+#define DENALI_CTL_49_DATA	(DDR_CONFIG_BASEADDR + 0x188)
+#define DENALI_CTL_50_DATA	(DDR_CONFIG_BASEADDR + 0x190)
+#define DENALI_CTL_51_DATA	(DDR_CONFIG_BASEADDR + 0x198)
+#define DENALI_CTL_52_DATA	(DDR_CONFIG_BASEADDR + 0x1a0)
+#define DENALI_CTL_53_DATA	(DDR_CONFIG_BASEADDR + 0x1a8)
+#define DENALI_CTL_54_DATA	(DDR_CONFIG_BASEADDR + 0x1b0)
+#define DENALI_CTL_55_DATA	(DDR_CONFIG_BASEADDR + 0x1b8)
+#define DENALI_CTL_56_DATA	(DDR_CONFIG_BASEADDR + 0x1c0)
+#define DENALI_CTL_57_DATA	(DDR_CONFIG_BASEADDR + 0x1c8)
+#define DENALI_CTL_58_DATA	(DDR_CONFIG_BASEADDR + 0x1d0)
+#define DENALI_CTL_59_DATA	(DDR_CONFIG_BASEADDR + 0x1d8)
+#define DENALI_CTL_60_DATA	(DDR_CONFIG_BASEADDR + 0x1e0)
+#define DENALI_CTL_61_DATA	(DDR_CONFIG_BASEADDR + 0x1e8)
+#define DENALI_CTL_62_DATA	(DDR_CONFIG_BASEADDR + 0x1f0)
+#define DENALI_CTL_63_DATA	(DDR_CONFIG_BASEADDR + 0x1f8)
+#define DENALI_CTL_64_DATA	(DDR_CONFIG_BASEADDR + 0x200)
+#define DENALI_CTL_65_DATA	(DDR_CONFIG_BASEADDR + 0x208)
+#define DENALI_CTL_66_DATA	(DDR_CONFIG_BASEADDR + 0x210)
+#define DENALI_CTL_67_DATA	(DDR_CONFIG_BASEADDR + 0x218)
+#define DENALI_CTL_68_DATA	(DDR_CONFIG_BASEADDR + 0x220)
+#define DENALI_CTL_69_DATA	(DDR_CONFIG_BASEADDR + 0x228)
+
+#define DENALI_WR_DQS_DELAY0		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x11B))
+#define DENALI_WR_DQS_DELAY1		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x11C))
+#define DENALI_WR_DQS_DELAY2		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x11D))
+#define DENALI_WR_DQS_DELAY3		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x11E))
+
+#define DENALI_SW_LEVELING_START	*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x278))
+#define DENALI_SW_LEVELING_MODE		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x279))
+#define DENALI_SW_LEVELING_LOAD		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x276))
+#define DENALI_DLL_MADJ0		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x148))
+#define DENALI_DLL_ADJ1_DS0_L		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x14A))
+#define DENALI_DLL_ADJ1_DS1_H		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x14E))
+#define DENALI_DLL_ADJ1_DS2_L		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x152))
+#define DENALI_DLL_ADJ1_DS3_H		*((volatile u8 *)(DDR_CONFIG_BASEADDR + 0x156))
+
+#endif
+
+/* end of file comcerto_1000.h */

include/asm-arm/arch-comcerto/comcerto_2000.h

diff --git a/include/asm-arm/arch-comcerto/comcerto_2000.h b/include/asm-arm/arch-comcerto/comcerto_2000.h
new file mode 100644
index 0000000..8bbe9a1
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/comcerto_2000.h
@@ -0,0 +1,192 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/comcerto-2000.h
+ *
+ *  Copyright (C) 2011 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __COMCERTO_2000_H__
+#define __COMCERTO_2000_H__
+
+/*
+ * AXI Bus
+ */
+#define COMCERTO_AXI_DDR_BASE		0x00000000 /* 2G */
+#define COMCERTO_AXI_ACP_BASE		0x80000000 /* 48MB */
+#define COMCERTO_AXI_IRAM_BASE		0x83000000 /* 48MB */
+#define COMCERTO_AXI_IBR_BASE		0x90000000 /* 4MB */
+#define COMCERTO_AXI_APB_CFG_BASE	0x90400000 /* 12MB */
+#define COMCERTO_AXI_SEM_CFG_BASE	0x91000000 /* 16MB */
+#define COMCERTO_AXI_USB2p0_CFG_BASE	0x92000000 /* 16MB */
+#define COMCERTO_AXI_TZ_CFG_BASE	0x93000000 /* 16MB */
+#define COMCERTO_AXI_DPI0_CFG_BASE	0x94000000 /* 16MB */
+#define COMCERTO_AXI_DPI1_CFG_BASE	0x95000000 /* 16MB */
+#define COMCERTO_AXI_UART_SPI_CFG_BASE	0x96000000 /* 16MB */
+#define COMCERTO_AXI_DDR_CFG_BASE	0x97000000 /* 16MB */
+#define COMCERTO_AXI_PCIe0_CFG_BASE	0x98000000 /* 16MB */
+#define COMCERTO_AXI_PCIe1_CFG_BASE	0x99000000 /* 16MB */
+#define COMCERTO_AXI_ESPAH_CFG_BASE	0x9A000000 /* 16MB */
+#define COMCERTO_AXI_SPACC_CFG_BASE	0x9B000000 /* 16MB */
+#define COMCERTO_AXI_HFE_CFG_BASE	0x9C000000 /* 16MB */
+#define COMCERTO_AXI_SATA_CFG_BASE	0x9D000000 /* 16MB */
+#define COMCERTO_AXI_DECT_CFG_BASE	0x9E000000 /* 16MB */
+#define COMCERTO_AXI_USB3p0_CFG_BASE	0x9F000000 /* 16MB */
+#define COMCERTO_AXI_PCIe0_SLV_BASE	0xA0000000 /* 256MB */
+#define COMCERTO_AXI_PCIe1_SLV_BASE	0xB0000000 /* 256MB */
+#define COMCERTO_AXI_EXP_BASE		0xC0000000 /* 256MB */
+#define COMCERTO_AXI_EXP_ECC_BASE	0xCFFF0000 /* 64KB */
+
+/*
+ * APB Bus
+ */
+#define COMCERTO_TDM_BASE			(COMCERTO_AXI_APB_CFG_BASE + 0x000000)
+#define COMCERTO_USB_PHY_SERDES_BASE		(COMCERTO_AXI_APB_CFG_BASE + 0x010000)
+#define COMCERTO_TDMA_BASE			(COMCERTO_AXI_APB_CFG_BASE + 0x020000)
+#define COMCERTO_APB_RESERVED2			(COMCERTO_AXI_APB_CFG_BASE + 0x030000)
+#define COMCERTO_APB_RESERVED3			(COMCERTO_AXI_APB_CFG_BASE + 0x040000)
+#define COMCERTO_TIMER_BASE   			(COMCERTO_AXI_APB_CFG_BASE + 0x050000)
+#define COMCERTO_PCIE_SATA_USB_CTRL_BASE	(COMCERTO_AXI_APB_CFG_BASE + 0x060000)
+#define COMCERTO_GPIO_BASE			(COMCERTO_AXI_APB_CFG_BASE + 0x070000)
+#define COMCERTO_APB_RESERVED5			(COMCERTO_AXI_APB_CFG_BASE + 0x080000)
+#define COMCERTO_UART0_BASE   			(COMCERTO_AXI_APB_CFG_BASE + 0x090000)
+#define COMCERTO_APB_RESERVED6			(COMCERTO_AXI_APB_CFG_BASE + 0x094000)
+#define COMCERTO_SPI_BASE     			(COMCERTO_AXI_APB_CFG_BASE + 0x098000)
+#define COMCERTO_I2C_BASE     			(COMCERTO_AXI_APB_CFG_BASE + 0x09C000)
+#define COMCERTO_USB3_0_BASE  			(COMCERTO_AXI_APB_CFG_BASE + 0x0A0000)
+#define COMCERTO_CLKCORE_BASE 			(COMCERTO_AXI_APB_CFG_BASE + 0x0B0000)
+#define COMCERTO_APB_RESERVED7			(COMCERTO_AXI_APB_CFG_BASE + 0x0C0000)
+#define COMCERTO_APB_RESERVED8			(COMCERTO_AXI_APB_CFG_BASE + 0x0D0000)
+#define COMCERTO_RTC_BASE     			(COMCERTO_AXI_APB_CFG_BASE + 0x0E0000)
+#define COMCERTO_OTP_BASE     			(COMCERTO_AXI_APB_CFG_BASE + 0x0F0000)
+#define COMCERTO_HFEWRAPPER_BASE		(COMCERTO_AXI_APB_CFG_BASE + 0x100000)
+#define COMCERTO_APB_RESERVED10			(COMCERTO_AXI_APB_CFG_BASE + 0x110000)
+#define COMCERTO_APB_RESERVED11			(COMCERTO_AXI_APB_CFG_BASE + 0x120000)
+#define COMCERTO_APB_RESERVED12			(COMCERTO_AXI_APB_CFG_BASE + 0x130000)
+#define COMCERTO_APB_RESERVED13			(COMCERTO_AXI_APB_CFG_BASE + 0x140000)
+#define COMCERTO_APB_RESERVED14			(COMCERTO_AXI_APB_CFG_BASE + 0x150000)
+#define COMCERTO_APB_RESERVED15			(COMCERTO_AXI_APB_CFG_BASE + 0x160000)
+#define COMCERTO_APB_RESERVED16			(COMCERTO_AXI_APB_CFG_BASE + 0x170000)
+#define COMCERTO_APB_RESERVED17			(COMCERTO_AXI_APB_CFG_BASE + 0x180000)
+#define COMCERTO_SERDES_CFG_BASE		(COMCERTO_AXI_APB_CFG_BASE + 0x190000)
+#define COMCERTO_EXP_CONF_BASE			(COMCERTO_AXI_APB_CFG_BASE + 0x1A0000)
+#define COMCERTO_DDR_PHY			(COMCERTO_AXI_APB_CFG_BASE + 0x1B0000)
+#define COMCERTO_APB_RESERVED20			(COMCERTO_AXI_APB_CFG_BASE + 0x1C0000)
+#define COMCERTO_TDMA2_BASE			(COMCERTO_AXI_APB_CFG_BASE + 0x1D0000)
+#define COMCERTO_MDMA_BASE			(COMCERTO_AXI_APB_CFG_BASE + 0x1E0000)
+#define COMCERTO_A9_CORESIGHT_BASE		(COMCERTO_AXI_APB_CFG_BASE + 0x200000)
+
+#define COMCERTO_APB_USBPHY_SERDES_STAT_BASE	0x90410000
+#define COMCERTO_APB_GPIO_BASE		0x90470000
+#define COMCERTO_APB_CLK_BASE		0x904B0000
+#define COMCERTO_APB_SERDES_BASE	0x90590000
+#define COMCERTO_APB_EXP_BASE		0x905A0000
+#define COMCERTO_APB_DDR_BASE		0x97000000
+#define COMCERTO_APB_DDR_PHY_BASE	0x905B0000
+#define COMCERTO_SATA_AHCI_BASE		0x9D000000
+
+#define COMCERTO_L2CC_BASE       0xFFF10000
+#define COMCERTO_A9_PERIPH_BASE     0xFFF00000
+#define COMCERTO_A9_SCU_BASE		(COMCERTO_A9_PERIPH_BASE + 0x0000)
+#define COMCERTO_A9_IC_INT_BASE		(COMCERTO_A9_PERIPH_BASE + 0x100)
+#define COMCERTO_A9_TIMER_BASE		(COMCERTO_A9_PERIPH_BASE + 0x600)
+#define COMCERTO_A9_IC_DIST_BASE	(COMCERTO_A9_PERIPH_BASE + 0x1000)
+
+#define COMCERTO_APB_SERDES0_BASE	(COMCERTO_APB_SERDES_BASE)
+#define COMCERTO_APB_SERDES1_BASE	(COMCERTO_APB_SERDES_BASE + 0x4000)
+#define COMCERTO_APB_SERDES2_BASE	(COMCERTO_APB_SERDES_BASE + 0x8000)
+#define COMCERTO_SER_DES0_PHY_CFG_BASE 	0x9041002C
+
+#define EXP_SWRST	(COMCERTO_APB_EXP_BASE + 0x0)
+#define EXP_CSEN	(COMCERTO_APB_EXP_BASE + 0x4)
+#define EXP_CS0_BASE 	(COMCERTO_APB_EXP_BASE + 0x8)
+#define EXP_CS0_SEG 	(COMCERTO_APB_EXP_BASE + 0x1c)
+#define EXP_CSO_CFG	(COMCERTO_APB_EXP_BASE + 0x30)
+
+#define DECT_SYS_CFG0	(COMCERTO_APB_GPIO_BASE + 0xb0)
+#define DECT_SYS_CFG1	(COMCERTO_APB_GPIO_BASE + 0xb4)
+#define DECT_CTRL	(COMCERTO_APB_GPIO_BASE + 0xb8)
+
+#define COMCERTO_SERDES_REG( _num, _ofst) ((COMCERTO_APB_SERDES_BASE + (0x4000 * _num)) + _ofst)
+
+//#define TEMP_STACK     0x8300C000
+
+#define UART_BASEADDR	0x96400000
+
+////////////////////////////////////////////////////////////
+//  GPIO block												     //
+////////////////////////////////////////////////////////////
+
+#define COMCERTO_GPIO_OUTPUT_REG			(COMCERTO_APB_GPIO_BASE + 0x00)
+#define COMCERTO_GPIO_OE_REG				(COMCERTO_APB_GPIO_BASE + 0x04)
+#define COMCERTO_GPIO_INT_CFG_REG			(COMCERTO_APB_GPIO_BASE + 0x08)
+#define COMCERTO_GPIO_ARM_UNALIGNED_LOGIC_ENABLE	(COMCERTO_APB_GPIO_BASE + 0x0C)
+#define COMCERTO_GPIO_INPUT_REG				(COMCERTO_APB_GPIO_BASE + 0x10)
+#define COMCERTO_GPIO_APB_WS				(COMCERTO_APB_GPIO_BASE + 0x14)
+#define COMCERTO_GPIO_SYSTEM_CONFIG			(COMCERTO_APB_GPIO_BASE + 0x1C)
+#define COMCERTO_GPIO_MBIST				(COMCERTO_APB_GPIO_BASE + 0x20)
+#define COMCERTO_GPIO_TDM_MUX				(COMCERTO_APB_GPIO_BASE + 0x28)
+#define COMCERTO_GPIO_ARM_ID				(COMCERTO_APB_GPIO_BASE + 0x30)
+#define COMCERTO_GPIO_PAD_CTRL				(COMCERTO_APB_GPIO_BASE + 0x34)
+#define COMCERTO_GPIO_BOOTSTRAP_STATUS			(COMCERTO_APB_GPIO_BASE + 0x40)
+#define COMCERTO_GPIO_BOOTSTRAP_OVERRIDE		(COMCERTO_APB_GPIO_BASE + 0x44)
+#define COMCERTO_GPIO_USB_PHY_BIST_STATUS_REG		(COMCERTO_APB_GPIO_BASE + 0x48)
+#define COMCERTO_GPIO_GENERAL_CONTROL_REG		(COMCERTO_APB_GPIO_BASE + 0x4C)
+#define COMCERTO_GPIO_DEVICE_ID_REG			(COMCERTO_APB_GPIO_BASE + 0x50)
+#define COMCERTO_GPIO_ARM_MEMORY_SENSE_AMP		(COMCERTO_APB_GPIO_BASE + 0x54)
+#define COMCERTO_GPIO_PIN_SELECT_REG_L			(COMCERTO_APB_GPIO_BASE + 0x58)
+#define COMCERTO_GPIO_PIN_SELECT_REG_H			(COMCERTO_APB_GPIO_BASE + 0x5C)
+#define COMCERTO_GPIO_MISC_PIN_SELECT_REG		(COMCERTO_APB_GPIO_BASE + 0x60)
+#define COMCERTO_GPIO_PAD_CONFIG0                       (COMCERTO_APB_GPIO_BASE + 0x100)
+#define COMCERTO_GPIO_PAD_CONFIG3                       (COMCERTO_APB_GPIO_BASE + 0x10C)
+#define COMCERTO_GPIO_PAD_CONFIG4                       (COMCERTO_APB_GPIO_BASE + 0x110)
+#define COMCERTO_GPIO_PAD_CONFIG5                       (COMCERTO_APB_GPIO_BASE + 0x114)
+#define COMCERTO_GPIO_MEM_EMA_CONFIG0                   (COMCERTO_APB_GPIO_BASE + 0x1A0)
+#define COMCERTO_GPIO_MEM_EMA_CONFIG1                   (COMCERTO_APB_GPIO_BASE + 0x1A4)
+
+#define GPIO_0		0x00000001
+#define GPIO_1		0x00000002
+#define GPIO_2		0x00000004
+#define GPIO_3		0x00000008
+#define GPIO_4		0x00000010
+#define GPIO_5		0x00000020
+#define GPIO_6	        0x00000040
+#define GPIO_7		0x00000080
+#define GPIO_8		0x00000100
+#define GPIO_9		0x00000200
+#define GPIO_10		0x00000400
+#define GPIO_11		0x00000800
+#define GPIO_12		0x00001000
+#define GPIO_13		0x00002000
+#define GPIO_14		0x00004000
+#define GPIO_15		0x00008000
+#define GPIO_16		0x00010000
+#define GPIO_17		0x00020000
+#define GPIO_18		0x00040000
+#define GPIO_19		0x00080000
+#define GPIO_20		0x00100000
+#define GPIO_21		0x00200000
+#define GPIO_22		0x00400000
+#define GPIO_23		0x00800000
+#define GPIO_24		0x01000000
+#define GPIO_25		0x02000000
+#define GPIO_26		0x04000000
+#define GPIO_27		0x08000000
+#define GPIO_28		0x10000000
+#define GPIO_29		0x20000000
+#define GPIO_30		0x40000000
+#define GPIO_31		0x80000000
+
+#endif /* __COMCERTO_2000_H__ */

include/asm-arm/arch-comcerto/comcerto_515.h

diff --git a/include/asm-arm/arch-comcerto/comcerto_515.h b/include/asm-arm/arch-comcerto/comcerto_515.h
new file mode 100644
index 0000000..6e925ad
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/comcerto_515.h
@@ -0,0 +1,247 @@
+#ifndef __COMCERTO_515_H
+#define __COMCERTO_515_H
+
+
+/* Memory map */
+/* Internal Memory */
+#define ERAM_BASEADDR			0x08000000
+#define IRAM_BASEADDR			0x09000000
+#define ARAM_BASEADDR			0x0A000000
+
+/* Expansion bus */
+#define APB_BASEADDR			0x10000000
+
+/* Chip select */
+#define EXP_CSBOOT_BASEADDR		0x11000000
+#define EXP_CSP0_BASEADDR		0x11400000
+#define EXP_CSP1_BASEADDR		0x11800000
+#define EXP_CSP2_BASEADDR		0x11C00000
+
+#define ERAM_SIZE			0x00060000
+#define IRAM_SIZE			0x00022000
+#define ARAM_SIZE			0x00020000
+
+#define APB_SIZE			0x01000000			/* 16M address range */
+
+#define EXP_CSBOOT_SIZE			0x00400000
+#define EXP_CSP0_SIZE			0x00400000
+#define EXP_CSP1_SIZE			0x00400000
+#define EXP_CSP2_SIZE			0x00400000
+
+/* Expansion bus peripherals */
+#define TDM_BASEADDR			(APB_BASEADDR + 0x000000)
+#define PHI_BASEADDR			(APB_BASEADDR + 0x010000)
+#define TDMA_BASEADDR			(APB_BASEADDR + 0x020000)
+#define SMC_BASEADDR			(APB_BASEADDR + 0x030000)
+#define ASA_CM_BASEADDR			(APB_BASEADDR + 0x040000)
+#define ASA_ARAM_BASEADDR		(APB_BASEADDR + 0x048000)
+#define TIMER_BASEADDR			(APB_BASEADDR + 0x050000)
+#define ASD_BASEADDR			(APB_BASEADDR + 0x060000)
+#define GPIO_BASEADDR			(APB_BASEADDR + 0x070000)
+#define SDC0_BASEADDR			(APB_BASEADDR + 0x080000)
+#define UART0_BASEADDR			(APB_BASEADDR + 0x090000)
+#define UART1_BASEADDR			(APB_BASEADDR + 0x094000)
+#define SPI_BASEADDR			(APB_BASEADDR + 0x098000)
+#define I2C_BASEADDR			(APB_BASEADDR + 0x09C000)
+#define INTC_BASEADDR			(APB_BASEADDR + 0x0A0000)
+#define CLKCORE_BASEADDR		(APB_BASEADDR + 0x0B0000)
+#define PUI_BASEADDR			(APB_BASEADDR + 0x0C0000)
+#define EMAC0_BASEADDR			(APB_BASEADDR + 0x0D0000)
+#define IDMA_BASEADDR			(APB_BASEADDR + 0x0E0000)
+#define ERAM_CFG_BASEADDR		(APB_BASEADDR + 0x0F0000)
+#define ASA_ERAM_BASEADDR		(APB_BASEADDR + 0x100000)
+#define SPU0_BASEADDR			(APB_BASEADDR + 0x110000)
+#define SDC1_BASEADDR			(APB_BASEADDR + 0x1B0000)
+
+
+/* PCI HI (PHI) Control Registers */
+#define PHI_FIFO_CTRL			(PHI_BASEADDR + 0x0000)
+#define PHI_FIFO_INT_STATUS		(PHI_BASEADDR + 0x0004)
+#define PHI_FIFO_INT_ACK		(PHI_BASEADDR + 0x0004)
+#define	PHI_TX_FIFO_SIZE		(PHI_BASEADDR + 0x0014)
+#define	PHI_TX_FIFO_HIGH_THRESHOLD	(PHI_BASEADDR + 0x0018)
+#define	PHI_TX_FIFO_LOW_THRESHOLD	(PHI_BASEADDR + 0x001C)
+#define	PHI_RX_FIFO_SIZE		(PHI_BASEADDR + 0x0024)
+#define	PHI_RX_FIFO_HIGH_THRESHOLD	(PHI_BASEADDR + 0x0028)
+#define	PHI_RX_FIFO_LOW_THRESHOLD	(PHI_BASEADDR + 0x002C)
+
+#define RXEIE				0x0100
+#define TXM3IE				0x0400
+#define RXM3IE				0x0800
+
+#define TXM3IAK				0x04
+#define RXEIAK				0x10
+#define RXM3IAK				0x40
+#define FLUSH_RX			0x80
+
+/* TX Mailbox */
+#define PHI_TX_MAIL0			(PHI_BASEADDR + 0x0030)
+#define PHI_TX_MAIL1			(PHI_BASEADDR + 0x0034)
+#define PHI_TX_MAIL2			(PHI_BASEADDR + 0x0038)
+#define PHI_TX_MAIL3			(PHI_BASEADDR + 0x003C)
+
+/* RX Mailbox */
+#define PHI_RX_MAIL0			(PHI_BASEADDR + 0x0040)
+#define PHI_RX_MAIL1			(PHI_BASEADDR + 0x0044)
+#define PHI_RX_MAIL2			(PHI_BASEADDR + 0x0048)
+#define PHI_RX_MAIL3			(PHI_BASEADDR + 0x004C)
+
+#define HI_PCI_CNTL			(PHI_BASEADDR + 0x0050)
+#define HI_PCI_STATUS			(PHI_BASEADDR + 0x0054)
+#define HI_PCI_IAK_REG			(PHI_BASEADDR + 0x0054)
+#define HI_PCI_START_ADDR		(PHI_BASEADDR + 0x0060)
+#define	HI_PCI_BURST_SIZE		(PHI_BASEADDR + 0x0064)
+#define HI_PCI_XFER_LEN			(PHI_BASEADDR + 0x0068)
+
+/* FIFO */
+#define PHI_TX_FIFO_DATA_BYTE		(PHI_BASEADDR + 0x4000)
+#define PHI_RX_FIFO_DATA_BYTE		(PHI_BASEADDR + 0x4000)
+#define PHI_TX_FIFO_DATA_HWORD		(PHI_BASEADDR + 0x8000)
+#define PHI_RX_FIFO_DATA_HWORD		(PHI_BASEADDR + 0x8000)
+#define PHI_TX_FIFO_DATA_WORD		(PHI_BASEADDR + 0xC000)
+#define PHI_RX_FIFO_DATA_WORD		(PHI_BASEADDR + 0xC000)
+
+
+/* AHB arbiter */
+#define ASA_PRIORITY_LEVEL		(ASA_CM_BASEADDR + 0x00)
+#define ASA_TERMINAL_COUNT		(ASA_CM_BASEADDR + 0x04)
+#define ASA_TERMINAL_COUNT_CFG		(ASA_CM_BASEADDR + 0x08)
+#define ASA_TC_REQTDMEN			(1<<10)
+#define ASA_TC_REQARM0EN		(1<<11)
+#define ASA_TC_REQARM1EN		(1<<12)
+#define ASA_TC_REQIDMAEN		(1<<13)
+#define ASA_TC_REQSMCEN			(1<<14)
+#define ASA_TC_REQTICEN			(1<<15)
+
+
+/* Timer Block */
+#define TIMER0_COUNT			(TIMER_BASEADDR + 0x00)
+#define TIMER0_CURR_COUNT		(TIMER_BASEADDR + 0x04)
+#define TIMER1_COUNT			(TIMER_BASEADDR + 0x08)
+#define TIMER1_CURR_COUNT		(TIMER_BASEADDR + 0x0C)
+
+#define TIMER_MASK			(TIMER_BASEADDR + 0x40)
+#define TIMER_STATUS			(TIMER_BASEADDR + 0x50)
+#define TIMER_ACK			(TIMER_BASEADDR + 0x50)
+
+
+/* AHB decoder block */
+#define ASD_MBA_EXP_CSSD0		(ASD_BASEADDR + 0x00)
+#define ASD_MBA_EXP_CSSD1		(ASD_BASEADDR + 0x04)
+#define ASD_CSE				(ASD_BASEADDR + 0x0C)
+#define ASD_EXA_EXP_CSSD0		(ASD_BASEADDR + 0x10)
+#define ASD_EXA_EXP_CSSD1		(ASD_BASEADDR + 0x14)
+#define ASD_MBA_SDR_CSSD0		(ASD_BASEADDR + 0x18)
+#define ASD_MBA_SDR_CSSD1		(ASD_BASEADDR + 0x1C)
+#define ASD_EXA_SDR_CSSD0		(ASD_BASEADDR + 0x20)
+#define ASD_EXA_SDR_CSSD1		(ASD_BASEADDR + 0x24)
+#define ASD_MEM_DIVIDER			(ASD_BASEADDR + 0x28)
+
+
+/* GPIO block */
+#define GPIO_OUTPUT			(GPIO_BASEADDR + 0x00)		/* GPIO output register */
+#define GPIO_OUTPUT_ENABLE		(GPIO_BASEADDR + 0x04)		/* GPIO output enable register */
+#define GPIO_HI_INT_ENABLE		(GPIO_BASEADDR + 0x08)
+#define GPIO_LO_INT_ENABLE		(GPIO_BASEADDR + 0x0C)
+#define GPIO_INPUT			(GPIO_BASEADDR + 0x10)		/* GPIO input register */
+#define GPIO_APB_ACCESS_WS		(GPIO_BASEADDR + 0x14)
+#define GPIO_MUX_CONF			(GPIO_BASEADDR + 0x18)
+#define GPIO_SYSCONF			(GPIO_BASEADDR + 0x1C)
+#define GPIO_LOCK			(GPIO_BASEADDR + 0x38)
+#define GPIO_IOCTRL			(GPIO_BASEADDR + 0x44)
+
+#define GPIO_0				0x01
+#define GPIO_1				0x02
+#define GPIO_2				0x04
+#define GPIO_3				0x08
+#define GPIO_4				0x10
+#define GPIO_5				0x20
+#define GPIO_6				0x40
+#define GPIO_7				0x80
+
+#define GPIO_RISING_EDGE		1
+#define GPIO_FALLING_EDGE		2
+#define GPIO_BOTH_EDGES			3
+
+
+/* SDRAM & SRAM controller block */
+#define SDC0_CSSD0_CFG			(SDC0_BASEADDR + 0x00)
+#define SDC0_CSSD1_CFG			(SDC0_BASEADDR + 0x04)
+#define SDC0_CSBOOT_CFG			(SDC0_BASEADDR + 0x08)
+#define SDC0_CSP0_CFG			(SDC0_BASEADDR + 0x0C)
+#define SDC0_SDRAM_CFG1			(SDC0_BASEADDR + 0x10)
+#define SDC0_SDRAM_CFG2			(SDC0_BASEADDR + 0x14)
+#define SDC0_SDRAM_REFRESH		(SDC0_BASEADDR + 0x18)
+#define SDC0_SDRAM_POWERON		(SDC0_BASEADDR + 0x1C)
+#define SDC0_CSP1_CFG			(SDC0_BASEADDR + 0x20)
+#define SDC0_CSP1_CFG			(SDC0_BASEADDR + 0x20)
+#define SDC0_CSP2_CFG			(SDC0_BASEADDR + 0x24)
+#define SDC0_VERSION			(SDC0_BASEADDR + 0x28)
+#define SDC0_DEV_ID			(SDC0_BASEADDR + 0x2C)
+
+/* UART */
+#define UART_RBR			(UART0_BASEADDR + 0x00)		/* Receive Buffer Register (R/O) */
+#define UART_THR			(UART0_BASEADDR + 0x00)		/* Transmit Holding Register (W/O) */
+#define UART_IER			(UART0_BASEADDR + 0x04)		/* Interrupt Enable Register */
+#define UART_MCR			(UART0_BASEADDR + 0x08)		/* Mode Control Register */
+#define UART_LCR			(UART0_BASEADDR + 0x0C)		/* Line Control Register */
+#define UART_SSR			(UART0_BASEADDR + 0x10)		/* Serial Status Register */
+#define UART_FCR			(UART0_BASEADDR + 0x14)		/* Form Control Register */
+#define UART_RXD			(UART0_BASEADDR + 0x18)		/* Transmiter Divider Latch (R/O) */
+#define UART_TXD			(UART0_BASEADDR + 0x1C)		/* Receiver Divider Latch (W/O) */
+#define UART_HR				(UART0_BASEADDR + 0x20)		/* Hunt Character */
+
+
+/* Clock block */
+#define CLKCORE_ARM_PLL 		(CLKCORE_BASEADDR + 0x00)
+#define CLKCORE_SPU_PLL			(CLKCORE_BASEADDR + 0x04)
+#define CLKCORE_AMBA_PLL		(CLKCORE_BASEADDR + 0x08)
+#define PLL_MUXSEL			0x04000000			/* PLL clock source selection */
+#define PLL_POWER			0x02000000			/* PLL power control */
+#define PLL_BYPASS			0x01000000			/* PLL bypass */
+
+
+/* EMAC */
+#include "emac.h"
+
+
+/* IDMA */
+#include "idma.h"
+
+
+/* SPI */
+#include "spi.h"
+
+
+/* Eram */
+#define ERAM_BIST_CTRL			(ERAM_CFG_BASEADDR + 0x00)
+#define ERAM_SPARE_FAIL			(ERAM_CFG_BASEADDR + 0x04)
+#define ERAM_BIST_ADDR			(ERAM_CFG_BASEADDR + 0x08)
+#define ERAM_BIST_BCK			(ERAM_CFG_BASEADDR + 0x0C)
+#define ERAM_MROW_FAIL			(ERAM_CFG_BASEADDR + 0x10)
+#define ERAM_MCOL_FAIL			(ERAM_CFG_BASEADDR + 0x14)
+#define ERAM_SHIFT_COL_FAIL		(ERAM_CFG_BASEADDR + 0x18)
+#define ERAM_RETN_TIME			(ERAM_CFG_BASEADDR + 0x1C)
+#define ERAM_SPCOL_ALLOC		(ERAM_CFG_BASEADDR + 0x20)
+#define ERAM_SPROW_ALLOC		(ERAM_CFG_BASEADDR + 0x30)
+#define ERAM_FUSE_SPCOL			(ERAM_CFG_BASEADDR + 0x40)
+#define ERAM_FUSE_SPROW			(ERAM_CFG_BASEADDR + 0x50)
+#define ERAM_IRAM_FAIL			(ERAM_CFG_BASEADDR + 0x60)
+
+
+/* Eram bus arbiter */
+#define ASA_ERAM_PRIORITY		(ASA_ERAM_BASEADDR + 0x00)
+#define ASA_ERAM_TERMINAL_COUNT		(ASA_ERAM_BASEADDR + 0x04)
+#define ASA_ERAM_TERMINAL_COUNT_CFG	(ASA_ERAM_BASEADDR + 0x08)
+
+
+/* Secondary SDRAM controller block */
+#define SDC1_CSSD0_CFG			(SDC1_BASEADDR + 0x00)
+#define SDC1_CSSD1_CFG			(SDC1_BASEADDR + 0x04)
+#define SDC1_SDRAM_CFG1		(SDC1_BASEADDR + 0x10)
+#define SDC1_SDRAM_CFG2		(SDC1_BASEADDR + 0x14)
+#define SDC1_SDRAM_REFRESH		(SDC1_BASEADDR + 0x18)
+#define SDC1_SDRAM_POWERON		(SDC1_BASEADDR + 0x1C)
+
+
+#endif /* __COMCERTO_515_H */

include/asm-arm/arch-comcerto/comcerto_530.h

diff --git a/include/asm-arm/arch-comcerto/comcerto_530.h b/include/asm-arm/arch-comcerto/comcerto_530.h
new file mode 100644
index 0000000..4835d49
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/comcerto_530.h
@@ -0,0 +1,211 @@
+#ifndef __COMCERTO_530_H
+#define __COMCERTO_530_H
+
+/* Memory map */
+/* Internal Memory */
+#define ERAM_BASEADDR			0x08000000
+#define IRAM_BASEADDR			0x09000000
+
+/* Expansion bus */
+#define APB_BASEADDR			0x10000000
+
+/* Chip select */
+#define EXP_CSBOOT_BASEADDR		0x11000000
+#define EXP_CSP0_BASEADDR		0x11400000
+
+#define ERAM_SIZE			0x00100000
+#define IRAM_SIZE			0x00002000
+#define APB_SIZE			0x01000000 /* 16M address range */
+#define EXP_CSBOOT_SIZE			0x00400000
+#define EXP_CSP0_SIZE			0x00400000
+
+/* Expansion bus peripherals */
+#define TDM_BASEADDR			(APB_BASEADDR + 0x000000)
+#define PHI_BASEADDR			(APB_BASEADDR + 0x010000)
+#define TDMA_BASEADDR			(APB_BASEADDR + 0x020000)
+#define SMC_BASEADDR			(APB_BASEADDR + 0x030000)
+#define ASA_BASEADDR			(APB_BASEADDR + 0x040000)
+#define TIMER_BASEADDR			(APB_BASEADDR + 0x050000)
+#define ASD_BASEADDR			(APB_BASEADDR + 0x060000)
+#define GPIO_BASEADDR			(APB_BASEADDR + 0x070000)
+#define SDC0_BASEADDR			(APB_BASEADDR + 0x080000)
+#define UART0_BASEADDR			(APB_BASEADDR + 0x090000)
+#define INTC_BASEADDR			(APB_BASEADDR + 0x0A0000)
+#define CLKCORE_BASEADDR		(APB_BASEADDR + 0x0B0000)
+#define PUI_BASEADDR			(APB_BASEADDR + 0x0C0000)
+#define EMAC0_BASEADDR			(APB_BASEADDR + 0x0D0000)
+#define IDMA_BASEADDR			(APB_BASEADDR + 0x0E0000)
+#define ERAM_CFG_BASEADDR		(APB_BASEADDR + 0x0F0000)
+#define ASA_ERAM_BASEADDR		(APB_BASEADDR + 0x100000)
+#define SPU0_BASEADDR			(APB_BASEADDR + 0x110000)
+#define SPU1_BASEADDR			(APB_BASEADDR + 0x120000)
+#define SPU2_BASEADDR			(APB_BASEADDR + 0x130000)
+#define SPU3_BASEADDR			(APB_BASEADDR + 0x140000)
+
+
+/* PCI HI (PHI) Control Registers */
+#define PHI_FIFO_CTRL			(PHI_BASEADDR + 0x0000)
+#define PHI_FIFO_INT_STATUS		(PHI_BASEADDR + 0x0004)
+#define PHI_FIFO_INT_ACK		(PHI_BASEADDR + 0x0004)
+#define	PHI_TX_FIFO_SIZE		(PHI_BASEADDR + 0x0014)
+#define	PHI_TX_FIFO_HIGH_THRESHOLD	(PHI_BASEADDR + 0x0018)
+#define	PHI_TX_FIFO_LOW_THRESHOLD	(PHI_BASEADDR + 0x001C)
+#define	PHI_RX_FIFO_SIZE		(PHI_BASEADDR + 0x0024)
+#define	PHI_RX_FIFO_HIGH_THRESHOLD	(PHI_BASEADDR + 0x0028)
+#define	PHI_RX_FIFO_LOW_THRESHOLD	(PHI_BASEADDR + 0x002C)
+
+#define RXEIE		0x0100
+#define TXM3IE		0x0400
+#define RXM3IE		0x0800
+
+#define TXM3IAK		0x04
+#define RXEIAK		0x10
+#define RXM3IAK		0x40
+#define FLUSH_RX	0x80
+
+/* TX Mailbox */
+#define PHI_TX_MAIL0			(PHI_BASEADDR + 0x0030)
+#define PHI_TX_MAIL1			(PHI_BASEADDR + 0x0034)
+#define PHI_TX_MAIL2			(PHI_BASEADDR + 0x0038)
+#define PHI_TX_MAIL3			(PHI_BASEADDR + 0x003C)
+
+/* RX Mailbox */
+#define PHI_RX_MAIL0			(PHI_BASEADDR + 0x0040)
+#define PHI_RX_MAIL1			(PHI_BASEADDR + 0x0044)
+#define PHI_RX_MAIL2			(PHI_BASEADDR + 0x0048)
+#define PHI_RX_MAIL3			(PHI_BASEADDR + 0x004C)
+
+#define HI_PCI_CNTL			(PHI_BASEADDR + 0x0050)
+#define HI_PCI_STATUS			(PHI_BASEADDR + 0x0054)
+#define HI_PCI_IAK_REG			(PHI_BASEADDR + 0x0054)
+#define HI_PCI_START_ADDR		(PHI_BASEADDR + 0x0060)
+#define	HI_PCI_BURST_SIZE		(PHI_BASEADDR + 0x0064)
+#define HI_PCI_XFER_LEN			(PHI_BASEADDR + 0x0068)
+
+/* FIFO */
+#define PHI_TX_FIFO_DATA_BYTE		(PHI_BASEADDR + 0x4000)
+#define PHI_RX_FIFO_DATA_BYTE		(PHI_BASEADDR + 0x4000)
+#define PHI_TX_FIFO_DATA_HWORD		(PHI_BASEADDR + 0x8000)
+#define PHI_RX_FIFO_DATA_HWORD		(PHI_BASEADDR + 0x8000)
+#define PHI_TX_FIFO_DATA_WORD		(PHI_BASEADDR + 0xC000)
+#define PHI_RX_FIFO_DATA_WORD		(PHI_BASEADDR + 0xC000)
+
+
+/* AHB arbiter */
+#define ASA_PRIORITY_LEVEL		(ASA_BASEADDR + 0x00)
+#define ASA_TERMINAL_COUNT		(ASA_BASEADDR + 0x04)
+#define ASA_TERMINAL_COUNT_CFG		(ASA_BASEADDR + 0x08)
+#define ASA_TC_REQTDMEN			(1<<10)
+#define ASA_TC_REQARM0EN		(1<<11)
+#define ASA_TC_REQARM1EN		(1<<12)
+#define ASA_TC_REQIDMAEN		(1<<13)
+#define ASA_TC_REQSMCEN			(1<<14)
+#define ASA_TC_REQTICEN			(1<<15)
+
+
+/* Timer Block */
+#define TIMER0_COUNT			(TIMER_BASEADDR + 0x00)
+#define TIMER0_CURR_COUNT		(TIMER_BASEADDR + 0x04)
+#define TIMER1_COUNT			(TIMER_BASEADDR + 0x08)
+#define TIMER1_CURR_COUNT		(TIMER_BASEADDR + 0x0C)
+
+#define TIMER_MASK			(TIMER_BASEADDR + 0x40)
+#define TIMER_STATUS			(TIMER_BASEADDR + 0x50)
+#define TIMER_ACK			(TIMER_BASEADDR + 0x50)
+
+
+/* AHB decoder block */
+#define ASD_MBA_EXP_CSSD0		(ASD_BASEADDR + 0x00)
+#define ASD_MBA_EXP_CSSD1		(ASD_BASEADDR + 0x04)
+#define ASD_CSE				(ASD_BASEADDR + 0x0C)
+
+
+/* GPIO block */
+#define GPIO_OUTPUT			(GPIO_BASEADDR + 0x00)	/* GPIO output register */
+#define GPIO_OUTPUT_ENABLE		(GPIO_BASEADDR + 0x04)	/* GPIO output enable register */
+#define GPIO_HI_INT_ENABLE		(GPIO_BASEADDR + 0x08)
+#define GPIO_LO_INT_ENABLE		(GPIO_BASEADDR + 0x0C)
+#define GPIO_INPUT			(GPIO_BASEADDR + 0x10)	/* GPIO input register */
+#define GPIO_APB_ACCESS_WS		(GPIO_BASEADDR + 0x14)
+#define GPIO_MUX_CONF			(GPIO_BASEADDR + 0x18)
+#define GPIO_SYSCONF			(GPIO_BASEADDR + 0x1C)
+
+#define GPIO_0		0x01
+#define GPIO_1		0x02
+#define GPIO_2		0x04
+#define GPIO_3		0x08
+#define GPIO_4		0x10
+#define GPIO_5		0x20
+#define GPIO_6		0x40
+#define GPIO_7		0x80
+
+#define GPIO_RISING_EDGE		1
+#define GPIO_FALLING_EDGE		2
+#define GPIO_BOTH_EDGES			3
+
+
+/* SDRAM & SRAM controller block */
+#define SDC0_CSSD0_CFG			(SDC0_BASEADDR + 0x00)
+#define SDC0_CSSD1_CFG			(SDC0_BASEADDR + 0x04)
+#define SDC0_CSBOOT_CFG			(SDC0_BASEADDR + 0x08)
+#define SDC0_CSP0_CFG			(SDC0_BASEADDR + 0x0C)
+#define SDC0_SDRAM_CFG1			(SDC0_BASEADDR + 0x10)
+#define SDC0_SDRAM_CFG2			(SDC0_BASEADDR + 0x14)
+#define SDC0_SDRAM_REFRESH		(SDC0_BASEADDR + 0x18)
+#define SDC0_SDRAM_POWERON		(SDC0_BASEADDR + 0x1C)
+#define SDC0_VERSION			(SDC0_BASEADDR + 0x28)
+
+
+/* UART */
+#define UART_RBR			(UART0_BASEADDR + 0x00)		/* Receive Buffer Register (R/O) */
+#define UART_THR			(UART0_BASEADDR + 0x00)		/* Transmit Holding Register (W/O) */
+#define UART_IER			(UART0_BASEADDR + 0x04)		/* Interrupt Enable Register */
+#define UART_MCR			(UART0_BASEADDR + 0x08)		/* Mode Control Register */
+#define UART_LCR			(UART0_BASEADDR + 0x0C)		/* Line Control Register */
+#define UART_SSR			(UART0_BASEADDR + 0x10)		/* Serial Status Register */
+#define UART_FCR			(UART0_BASEADDR + 0x14)		/* Form Control Register */
+#define UART_RXD			(UART0_BASEADDR + 0x18)		/* Transmiter Divider Latch (R/O) */
+#define UART_TXD			(UART0_BASEADDR + 0x1C)		/* Receiver Divider Latch (W/O) */
+#define UART_HR				(UART0_BASEADDR + 0x20)		/* Hunt Character */
+
+
+/* Clock block */
+#define CLKCORE_ARM_PLL 		(CLKCORE_BASEADDR + 0x00)
+#define CLKCORE_SPU_PLL			(CLKCORE_BASEADDR + 0x04)
+#define CLKCORE_AMBA_PLL		(CLKCORE_BASEADDR + 0x08)
+#define PLL_MUXSEL			0x04000000	/* PLL clock source selection */
+#define PLL_POWER			0x02000000	/* PLL power control */
+#define PLL_BYPASS			0x01000000	/* PLL bypass */
+
+
+/* EMAC */
+#include "emac.h"
+
+
+/* IDMA */
+#include "idma.h"
+
+
+/* Eram */
+#define ERAM_BIST_CTRL			(ERAM_CFG_BASEADDR + 0x00)
+#define ERAM_SPARE_FAIL			(ERAM_CFG_BASEADDR + 0x04)
+#define ERAM_BIST_ADDR			(ERAM_CFG_BASEADDR + 0x08)
+#define ERAM_BIST_BCK			(ERAM_CFG_BASEADDR + 0x0C)
+#define ERAM_MROW_FAIL			(ERAM_CFG_BASEADDR + 0x10)
+#define ERAM_MCOL_FAIL			(ERAM_CFG_BASEADDR + 0x14)
+#define ERAM_SHIFT_COL_FAIL		(ERAM_CFG_BASEADDR + 0x18)
+#define ERAM_RETN_TIME			(ERAM_CFG_BASEADDR + 0x1C)
+#define ERAM_SPCOL_ALLOC		(ERAM_CFG_BASEADDR + 0x20)
+#define ERAM_SPROW_ALLOC		(ERAM_CFG_BASEADDR + 0x30)
+#define ERAM_FUSE_SPCOL			(ERAM_CFG_BASEADDR + 0x40)
+#define ERAM_FUSE_SPROW			(ERAM_CFG_BASEADDR + 0x50)
+#define ERAM_IRAM_FAIL			(ERAM_CFG_BASEADDR + 0x60)
+
+
+/* Eram bus arbiter */
+#define ASA_ERAM_PRIORITY		(ASA_ERAM_BASEADDR + 0x00)
+#define ASA_ERAM_TERMINAL_COUNT		(ASA_ERAM_BASEADDR + 0x04)
+#define ASA_ERAM_TERMINAL_COUNT_CFG	(ASA_ERAM_BASEADDR + 0x08)
+
+
+#endif /* __COMCERTO_530_H */

include/asm-arm/arch-comcerto/comcerto_800.h

diff --git a/include/asm-arm/arch-comcerto/comcerto_800.h b/include/asm-arm/arch-comcerto/comcerto_800.h
new file mode 100644
index 0000000..cb1011d
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/comcerto_800.h
@@ -0,0 +1,252 @@
+#ifndef __COMCERTO_800_H
+#define __COMCERTO_800_H
+
+
+/* Memory map */
+/* Internal Memory */
+#define ERAM_BASEADDR			0x08000000
+#define IRAM_BASEADDR			0x09000000
+#define ARAM_BASEADDR			0x0A000000
+
+/* Expansion bus */
+#define APB_BASEADDR			0x10000000
+
+/* Chip select */
+#define EXP_CSBOOT_BASEADDR		0x11000000
+#define EXP_CSP0_BASEADDR		0x11400000
+#define EXP_CSP1_BASEADDR		0x11800000
+#define EXP_CSP2_BASEADDR		0x11C00000
+
+#define ERAM_SIZE			0x00060000
+#define IRAM_SIZE			0x00022000
+#define ARAM_SIZE			0x00020000
+
+#define APB_SIZE			0x01000000 /* 16M address range */
+
+#define EXP_CSBOOT_SIZE			0x00400000
+#define EXP_CSP0_SIZE			0x00400000
+#define EXP_CSP1_SIZE			0x00400000
+#define EXP_CSP2_SIZE			0x00400000
+
+/* Expansion bus peripherals */
+#define TDM_BASEADDR			(APB_BASEADDR + 0x000000)
+#define PHI_BASEADDR			(APB_BASEADDR + 0x010000)
+#define TDMA_BASEADDR			(APB_BASEADDR + 0x020000)
+#define SMC_BASEADDR			(APB_BASEADDR + 0x030000)
+#define ASA_CM_BASEADDR			(APB_BASEADDR + 0x040000)
+#define ASA_ARAM_BASEADDR		(APB_BASEADDR + 0x048000)
+#define TIMER_BASEADDR			(APB_BASEADDR + 0x050000)
+#define ASD_BASEADDR			(APB_BASEADDR + 0x060000)
+#define GPIO_BASEADDR			(APB_BASEADDR + 0x070000)
+#define SDC0_BASEADDR			(APB_BASEADDR + 0x080000)
+#define UART0_BASEADDR			(APB_BASEADDR + 0x090000)
+#define UART1_BASEADDR			(APB_BASEADDR + 0x094000)
+#define SPI_BASEADDR			(APB_BASEADDR + 0x098000)
+#define I2C_BASEADDR			(APB_BASEADDR + 0x09C000)
+#define INTC_BASEADDR			(APB_BASEADDR + 0x0A0000)
+#define CLKCORE_BASEADDR		(APB_BASEADDR + 0x0B0000)
+#define PUI_BASEADDR			(APB_BASEADDR + 0x0C0000)
+#define EMAC0_BASEADDR			(APB_BASEADDR + 0x0D0000)
+#define IDMA_BASEADDR			(APB_BASEADDR + 0x0E0000)
+#define USB_BASEADDR			(APB_BASEADDR + 0x0E0400)
+#define ERAM_CFG_BASEADDR		(APB_BASEADDR + 0x0F0000)
+#define ASA_ERAM_BASEADDR		(APB_BASEADDR + 0x100000)
+#define SPU0_BASEADDR			(APB_BASEADDR + 0x110000)
+#define EMAC1_BASEADDR			(APB_BASEADDR + 0x170000)
+#define WIF_BASEADDR			(APB_BASEADDR + 0x190000)
+#define SDC1_BASEADDR			(APB_BASEADDR + 0x1B0000)
+#define IPSEC_BASEADDR			(APB_BASEADDR + 0x1C0000)
+
+
+/* PCI HI (PHI) Control Registers */
+#define PHI_FIFO_CTRL			(PHI_BASEADDR + 0x0000)
+#define PHI_FIFO_INT_STATUS		(PHI_BASEADDR + 0x0004)
+#define PHI_FIFO_INT_ACK		(PHI_BASEADDR + 0x0004)
+#define	PHI_TX_FIFO_SIZE		(PHI_BASEADDR + 0x0014)
+#define	PHI_TX_FIFO_HIGH_THRESHOLD	(PHI_BASEADDR + 0x0018)
+#define	PHI_TX_FIFO_LOW_THRESHOLD	(PHI_BASEADDR + 0x001C)
+#define	PHI_RX_FIFO_SIZE		(PHI_BASEADDR + 0x0024)
+#define	PHI_RX_FIFO_HIGH_THRESHOLD	(PHI_BASEADDR + 0x0028)
+#define	PHI_RX_FIFO_LOW_THRESHOLD	(PHI_BASEADDR + 0x002C)
+
+#define RXEIE		0x0100
+#define TXM3IE		0x0400
+#define RXM3IE		0x0800
+
+#define TXM3IAK		0x04
+#define RXEIAK		0x10
+#define RXM3IAK		0x40
+#define FLUSH_RX	0x80
+
+/* TX Mailbox */
+#define PHI_TX_MAIL0			(PHI_BASEADDR + 0x0030)
+#define PHI_TX_MAIL1			(PHI_BASEADDR + 0x0034)
+#define PHI_TX_MAIL2			(PHI_BASEADDR + 0x0038)
+#define PHI_TX_MAIL3			(PHI_BASEADDR + 0x003C)
+
+/* RX Mailbox */
+#define PHI_RX_MAIL0			(PHI_BASEADDR + 0x0040)
+#define PHI_RX_MAIL1			(PHI_BASEADDR + 0x0044)
+#define PHI_RX_MAIL2			(PHI_BASEADDR + 0x0048)
+#define PHI_RX_MAIL3			(PHI_BASEADDR + 0x004C)
+
+#define HI_PCI_CNTL			(PHI_BASEADDR + 0x0050)
+#define HI_PCI_STATUS			(PHI_BASEADDR + 0x0054)
+#define HI_PCI_IAK_REG			(PHI_BASEADDR + 0x0054)
+#define HI_PCI_START_ADDR		(PHI_BASEADDR + 0x0060)
+#define	HI_PCI_BURST_SIZE		(PHI_BASEADDR + 0x0064)
+#define HI_PCI_XFER_LEN			(PHI_BASEADDR + 0x0068)
+
+/* FIFO */
+#define PHI_TX_FIFO_DATA_BYTE		(PHI_BASEADDR + 0x4000)
+#define PHI_RX_FIFO_DATA_BYTE		(PHI_BASEADDR + 0x4000)
+#define PHI_TX_FIFO_DATA_HWORD		(PHI_BASEADDR + 0x8000)
+#define PHI_RX_FIFO_DATA_HWORD		(PHI_BASEADDR + 0x8000)
+#define PHI_TX_FIFO_DATA_WORD		(PHI_BASEADDR + 0xC000)
+#define PHI_RX_FIFO_DATA_WORD		(PHI_BASEADDR + 0xC000)
+
+
+/* AHB arbiter */
+#define ASA_PRIORITY_LEVEL		(ASA_CM_BASEADDR + 0x00)
+#define ASA_TERMINAL_COUNT		(ASA_CM_BASEADDR + 0x04)
+#define ASA_TERMINAL_COUNT_CFG		(ASA_CM_BASEADDR + 0x08)
+#define ASA_TC_REQTDMEN			(1<<10)
+#define ASA_TC_REQARM0EN		(1<<11)
+#define ASA_TC_REQARM1EN		(1<<12)
+#define ASA_TC_REQIDMAEN		(1<<13)
+#define ASA_TC_REQSMCEN			(1<<14)
+#define ASA_TC_REQTICEN			(1<<15)
+
+
+/* Timer Block */
+#define TIMER0_COUNT			(TIMER_BASEADDR + 0x00)
+#define TIMER0_CURR_COUNT		(TIMER_BASEADDR + 0x04)
+#define TIMER1_COUNT			(TIMER_BASEADDR + 0x08)
+#define TIMER1_CURR_COUNT		(TIMER_BASEADDR + 0x0C)
+
+#define TIMER_MASK			(TIMER_BASEADDR + 0x40)
+#define TIMER_STATUS			(TIMER_BASEADDR + 0x50)
+#define TIMER_ACK			(TIMER_BASEADDR + 0x50)
+
+
+/* AHB decoder block */
+#define ASD_MBA_EXP_CSSD0		(ASD_BASEADDR + 0x00)
+#define ASD_MBA_EXP_CSSD1		(ASD_BASEADDR + 0x04)
+#define ASD_CSE				(ASD_BASEADDR + 0x0C)
+#define ASD_EXA_EXP_CSSD0		(ASD_BASEADDR + 0x10)
+#define ASD_EXA_EXP_CSSD1		(ASD_BASEADDR + 0x14)
+#define ASD_MBA_SDR_CSSD0		(ASD_BASEADDR + 0x18)
+#define ASD_MBA_SDR_CSSD1		(ASD_BASEADDR + 0x1C)
+#define ASD_EXA_SDR_CSSD0		(ASD_BASEADDR + 0x20)
+#define ASD_EXA_SDR_CSSD1		(ASD_BASEADDR + 0x24)
+#define ASD_MEM_DIVIDER			(ASD_BASEADDR + 0x28)
+
+
+/* GPIO block */
+#define GPIO_OUTPUT			(GPIO_BASEADDR + 0x00)	/* GPIO output register */
+#define GPIO_OUTPUT_ENABLE		(GPIO_BASEADDR + 0x04)	/* GPIO output enable register */
+#define GPIO_HI_INT_ENABLE		(GPIO_BASEADDR + 0x08)
+#define GPIO_LO_INT_ENABLE		(GPIO_BASEADDR + 0x0C)
+#define GPIO_INPUT			(GPIO_BASEADDR + 0x10)	/* GPIO input register */
+#define GPIO_APB_ACCESS_WS		(GPIO_BASEADDR + 0x14)
+#define GPIO_MUX_CONF			(GPIO_BASEADDR + 0x18)
+#define GPIO_SYSCONF			(GPIO_BASEADDR + 0x1C)
+#define GPIO_LOCK			(GPIO_BASEADDR + 0x38)
+#define GPIO_IOCTRL			(GPIO_BASEADDR + 0x44)
+
+#define GPIO_0		0x01
+#define GPIO_1		0x02
+#define GPIO_2		0x04
+#define GPIO_3		0x08
+#define GPIO_4		0x10
+#define GPIO_5		0x20
+#define GPIO_6		0x40
+#define GPIO_7		0x80
+
+#define GPIO_RISING_EDGE		1
+#define GPIO_FALLING_EDGE		2
+#define GPIO_BOTH_EDGES			3
+
+
+/* SDRAM & SRAM controller block */
+#define SDC0_CSSD0_CFG			(SDC0_BASEADDR + 0x00)
+#define SDC0_CSSD1_CFG			(SDC0_BASEADDR + 0x04)
+#define SDC0_CSBOOT_CFG			(SDC0_BASEADDR + 0x08)
+#define SDC0_CSP0_CFG			(SDC0_BASEADDR + 0x0C)
+#define SDC0_SDRAM_CFG1			(SDC0_BASEADDR + 0x10)
+#define SDC0_SDRAM_CFG2			(SDC0_BASEADDR + 0x14)
+#define SDC0_SDRAM_REFRESH		(SDC0_BASEADDR + 0x18)
+#define SDC0_SDRAM_POWERON		(SDC0_BASEADDR + 0x1C)
+#define SDC0_CSP1_CFG			(SDC0_BASEADDR + 0x20)
+#define SDC0_CSP1_CFG			(SDC0_BASEADDR + 0x20)
+#define SDC0_CSP2_CFG			(SDC0_BASEADDR + 0x24)
+#define SDC0_VERSION			(SDC0_BASEADDR + 0x28)
+#define SDC0_DEV_ID			(SDC0_BASEADDR + 0x2C)
+
+
+/* UART */
+#define UART_RBR			(UART0_BASEADDR + 0x00)		/* Receive Buffer Register (R/O) */
+#define UART_THR			(UART0_BASEADDR + 0x00)		/* Transmit Holding Register (W/O) */
+#define UART_IER			(UART0_BASEADDR + 0x04)		/* Interrupt Enable Register */
+#define UART_MCR			(UART0_BASEADDR + 0x08)		/* Mode Control Register */
+#define UART_LCR			(UART0_BASEADDR + 0x0C)		/* Line Control Register */
+#define UART_SSR			(UART0_BASEADDR + 0x10)		/* Serial Status Register */
+#define UART_FCR			(UART0_BASEADDR + 0x14)		/* Form Control Register */
+#define UART_RXD			(UART0_BASEADDR + 0x18)		/* Transmiter Divider Latch (R/O) */
+#define UART_TXD			(UART0_BASEADDR + 0x1C)		/* Receiver Divider Latch (W/O) */
+#define UART_HR				(UART0_BASEADDR + 0x20)		/* Hunt Character */
+
+
+/* Clock block */
+#define CLKCORE_ARM_PLL 		(CLKCORE_BASEADDR + 0x00)
+#define CLKCORE_SPU_PLL			(CLKCORE_BASEADDR + 0x04)
+#define CLKCORE_AMBA_PLL		(CLKCORE_BASEADDR + 0x08)
+#define PLL_MUXSEL			0x04000000	/* PLL clock source selection */
+#define PLL_POWER			0x02000000	/* PLL power control */
+#define PLL_BYPASS			0x01000000	/* PLL bypass */
+
+
+/* EMAC */
+#include "emac.h"
+
+
+/* IDMA */
+#include "idma.h"
+
+
+/* SPI */
+#include "spi.h"
+
+
+/* Eram */
+#define ERAM_BIST_CTRL			(ERAM_CFG_BASEADDR + 0x00)
+#define ERAM_SPARE_FAIL			(ERAM_CFG_BASEADDR + 0x04)
+#define ERAM_BIST_ADDR			(ERAM_CFG_BASEADDR + 0x08)
+#define ERAM_BIST_BCK			(ERAM_CFG_BASEADDR + 0x0C)
+#define ERAM_MROW_FAIL			(ERAM_CFG_BASEADDR + 0x10)
+#define ERAM_MCOL_FAIL			(ERAM_CFG_BASEADDR + 0x14)
+#define ERAM_SHIFT_COL_FAIL		(ERAM_CFG_BASEADDR + 0x18)
+#define ERAM_RETN_TIME			(ERAM_CFG_BASEADDR + 0x1C)
+#define ERAM_SPCOL_ALLOC		(ERAM_CFG_BASEADDR + 0x20)
+#define ERAM_SPROW_ALLOC		(ERAM_CFG_BASEADDR + 0x30)
+#define ERAM_FUSE_SPCOL			(ERAM_CFG_BASEADDR + 0x40)
+#define ERAM_FUSE_SPROW			(ERAM_CFG_BASEADDR + 0x50)
+#define ERAM_IRAM_FAIL			(ERAM_CFG_BASEADDR + 0x60)
+
+
+/* Eram bus arbiter */
+#define ASA_ERAM_PRIORITY		(ASA_ERAM_BASEADDR + 0x00)
+#define ASA_ERAM_TERMINAL_COUNT		(ASA_ERAM_BASEADDR + 0x04)
+#define ASA_ERAM_TERMINAL_COUNT_CFG	(ASA_ERAM_BASEADDR + 0x08)
+
+
+/* Secondary SDRAM controller block */
+#define SDC1_CSSD0_CFG                  (SDC1_BASEADDR + 0x00)
+#define SDC1_CSSD1_CFG                  (SDC1_BASEADDR + 0x04)
+#define SDC1_SDRAM_CFG1                 (SDC1_BASEADDR + 0x10)
+#define SDC1_SDRAM_CFG2                 (SDC1_BASEADDR + 0x14)
+#define SDC1_SDRAM_REFRESH              (SDC1_BASEADDR + 0x18)
+#define SDC1_SDRAM_POWERON              (SDC1_BASEADDR + 0x1C)
+
+
+#endif /* __COMCERTO_515_H */

include/asm-arm/arch-comcerto/comcerto_900.h

diff --git a/include/asm-arm/arch-comcerto/comcerto_900.h b/include/asm-arm/arch-comcerto/comcerto_900.h
new file mode 100644
index 0000000..7192884
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/comcerto_900.h
@@ -0,0 +1,299 @@
+#ifndef __COMCERTO_900_H
+#define __COMCERTO_900_H
+
+
+/* Memory map */
+/* Internal Memory */
+#define ERAM_BASEADDR			0x08000000
+#define ARAM_BASEADDR			0x0A000000
+#define CRAM_BASEADDR			0x0B000000
+
+/* Expansion bus */
+#define APB_BASEADDR			0x10000000
+
+/* Chip select */
+#define EXP_CSBOOT_BASEADDR		0x11000000
+#define EXP_CSP0_BASEADDR		0x11400000
+#define EXP_CSP1_BASEADDR		0x11800000
+
+#define ERAM_SIZE			0x00300000
+#define ARAM_SIZE			0x000A2000
+#define CRAM_SIZE			0x00080000
+#define APB_SIZE			0x01000000 /* 16M address range */
+#define EXP_CSBOOT_SIZE			0x00400000
+#define EXP_CSP0_SIZE			0x00400000
+#define EXP_CSP1_SIZE			0x00800000
+
+/* Expansion bus peripherals */
+#define TDM_BASEADDR			(APB_BASEADDR + 0x000000)
+#define PHI_BASEADDR			(APB_BASEADDR + 0x010000)
+#define TDMA_BASEADDR			(APB_BASEADDR + 0x020000)
+#define SMC_BASEADDR			(APB_BASEADDR + 0x030000)
+#define ASA_CM_BASEADDR			(APB_BASEADDR + 0x040000)
+#define ASA_ARAM_BASEADDR		(APB_BASEADDR + 0x048000)
+#define TIMER_BASEADDR			(APB_BASEADDR + 0x050000)
+#define ASD_BASEADDR			(APB_BASEADDR + 0x060000)
+#define GPIO_BASEADDR			(APB_BASEADDR + 0x070000)
+#define SDC0_BASEADDR			(APB_BASEADDR + 0x080000)
+#define UART0_BASEADDR			(APB_BASEADDR + 0x090000)
+#define INTC_BASEADDR			(APB_BASEADDR + 0x0A0000)
+#define CLKCORE_BASEADDR		(APB_BASEADDR + 0x0B0000)
+#define PUI_BASEADDR			(APB_BASEADDR + 0x0C0000)
+#define GEMAC_BASEADDR			(APB_BASEADDR + 0x0D0000)
+#define IDMA_BASEADDR			(APB_BASEADDR + 0x0E0000)
+#define ERAM_CFG_BASEADDR		(APB_BASEADDR + 0x0F0000)
+#define ASA_ERAM_BASEADDR		(APB_BASEADDR + 0x100000)
+#define ASA_CRAM_BASEADDR		(APB_BASEADDR + 0x108000)
+#define SPU0_BASEADDR			(APB_BASEADDR + 0x110000)
+#define SPU1_BASEADDR			(APB_BASEADDR + 0x120000)
+#define SPU2_BASEADDR			(APB_BASEADDR + 0x130000)
+#define SPU3_BASEADDR			(APB_BASEADDR + 0x140000)
+#define SPU4_BASEADDR			(APB_BASEADDR + 0x150000)
+#define SPU5_BASEADDR			(APB_BASEADDR + 0x160000)
+#define SPU6_BASEADDR			(APB_BASEADDR + 0x170000)
+#define SPU7_BASEADDR			(APB_BASEADDR + 0x180000)
+#define TDMA2_BASEADDR			(APB_BASEADDR + 0x1D0000)
+#define MDMA_BASEADDR			(APB_BASEADDR + 0x1E0000)
+
+
+/* PCI HI (PHI) Control Registers */
+#define PHI_FIFO_CTRL			(PHI_BASEADDR + 0x0000)
+#define PHI_FIFO_INT_STATUS		(PHI_BASEADDR + 0x0004)
+#define PHI_FIFO_INT_ACK		(PHI_BASEADDR + 0x0004)
+#define	PHI_TX_FIFO_SIZE		(PHI_BASEADDR + 0x0014)
+#define	PHI_TX_FIFO_HIGH_THRESHOLD	(PHI_BASEADDR + 0x0018)
+#define	PHI_TX_FIFO_LOW_THRESHOLD	(PHI_BASEADDR + 0x001C)
+#define	PHI_RX_FIFO_SIZE		(PHI_BASEADDR + 0x0024)
+#define	PHI_RX_FIFO_HIGH_THRESHOLD	(PHI_BASEADDR + 0x0028)
+#define	PHI_RX_FIFO_LOW_THRESHOLD	(PHI_BASEADDR + 0x002C)
+
+#define RXEIE		0x0100
+#define TXM3IE		0x0400
+#define RXM3IE		0x0800
+
+#define TXM3IAK		0x04
+#define RXEIAK		0x10
+#define RXM3IAK		0x40
+#define FLUSH_RX	0x80
+
+/* TX Mailbox */
+#define PHI_TX_MAIL0			(PHI_BASEADDR + 0x0030)
+#define PHI_TX_MAIL1			(PHI_BASEADDR + 0x0034)
+#define PHI_TX_MAIL2			(PHI_BASEADDR + 0x0038)
+#define PHI_TX_MAIL3			(PHI_BASEADDR + 0x003C)
+
+/* RX Mailbox */
+#define PHI_RX_MAIL0			(PHI_BASEADDR + 0x0040)
+#define PHI_RX_MAIL1			(PHI_BASEADDR + 0x0044)
+#define PHI_RX_MAIL2			(PHI_BASEADDR + 0x0048)
+#define PHI_RX_MAIL3			(PHI_BASEADDR + 0x004C)
+
+#define HI_PCI_CNTL			(PHI_BASEADDR + 0x0050)
+#define HI_PCI_STATUS			(PHI_BASEADDR + 0x0054)
+#define HI_PCI_IAK_REG			(PHI_BASEADDR + 0x0054)
+#define HI_PCI_START_ADDR		(PHI_BASEADDR + 0x0060)
+#define	HI_PCI_BURST_SIZE		(PHI_BASEADDR + 0x0064)
+#define HI_PCI_XFER_LEN			(PHI_BASEADDR + 0x0068)
+
+/* FIFO */
+#define PHI_TX_FIFO_DATA_BYTE		(PHI_BASEADDR + 0x4000)
+#define PHI_RX_FIFO_DATA_BYTE		(PHI_BASEADDR + 0x4000)
+#define PHI_TX_FIFO_DATA_HWORD		(PHI_BASEADDR + 0x8000)
+#define PHI_RX_FIFO_DATA_HWORD		(PHI_BASEADDR + 0x8000)
+#define PHI_TX_FIFO_DATA_WORD		(PHI_BASEADDR + 0xC000)
+#define PHI_RX_FIFO_DATA_WORD		(PHI_BASEADDR + 0xC000)
+
+
+/* AHB arbiter */
+#define ASA_PRIORITY_LEVEL		(ASA_CM_BASEADDR + 0x00)
+#define ASA_TERMINAL_COUNT		(ASA_CM_BASEADDR + 0x04)
+#define ASA_TERMINAL_COUNT_CFG		(ASA_CM_BASEADDR + 0x08)
+#define ASA_TC_REQTDMEN			(1<<10)
+#define ASA_TC_REQARM0EN		(1<<11)
+#define ASA_TC_REQARM1EN		(1<<12)
+#define ASA_TC_REQIDMAEN		(1<<13)
+#define ASA_TC_REQSMCEN			(1<<14)
+#define ASA_TC_REQTICEN			(1<<15)
+
+
+////////////////////////////////////////////////////////////
+// TIMER block											    //
+////////////////////////////////////////////////////////////
+
+#define TIMER0_CNTR_REG		(TIMER_BASEADDR + 0x00)
+#define TIMER0_CURR_COUNT	(TIMER_BASEADDR + 0x04)
+#define TIMER1_CNTR_REG		(TIMER_BASEADDR + 0x08)
+#define TIMER1_CURR_COUNT	(TIMER_BASEADDR + 0x0C)
+
+#define TIMER_MASK			(TIMER_BASEADDR + 0x40)
+#define TIMER_STATUS			(TIMER_BASEADDR + 0x50)
+#define TIMER_ACK			(TIMER_BASEADDR + 0x50)
+
+
+/* AHB decoder block */
+#define ASD_MBA_EXP_CSSD0		(ASD_BASEADDR + 0x00)
+#define ASD_MBA_EXP_CSSD1		(ASD_BASEADDR + 0x04)
+#define ASD_CSE				(ASD_BASEADDR + 0x0C)
+#define ASD_EXA_EXP_CSSD0		(ASD_BASEADDR + 0x10)
+#define ASD_EXA_EXP_CSSD1		(ASD_BASEADDR + 0x14)
+#define ASD_MEM_DIVIDER			(ASD_BASEADDR + 0x28)
+
+
+/* GPIO block */
+#define GPIO_OUTPUT			(GPIO_BASEADDR + 0x00)	/* GPIO output register */
+#define GPIO_OUTPUT_ENABLE		(GPIO_BASEADDR + 0x04)	/* GPIO output enable register */
+#define GPIO_HI_INT_ENABLE		(GPIO_BASEADDR + 0x08)
+#define GPIO_LO_INT_ENABLE		(GPIO_BASEADDR + 0x0C)
+#define GPIO_INPUT			(GPIO_BASEADDR + 0x10)	/* GPIO input register */
+#define GPIO_APB_ACCESS_WS		(GPIO_BASEADDR + 0x14)
+#define GPIO_MUX_CONF			(GPIO_BASEADDR + 0x18)
+#define GPIO_SYSCONF			(GPIO_BASEADDR + 0x1C)
+#define GPIO_LOCK			(GPIO_BASEADDR + 0x38)
+#define GPIO_IOCTRL			(GPIO_BASEADDR + 0x44)
+
+#define GPIO_0		0x01
+#define GPIO_1		0x02
+#define GPIO_2		0x04
+#define GPIO_3		0x08
+#define GPIO_4		0x10
+#define GPIO_5		0x20
+#define GPIO_6		0x40
+#define GPIO_7		0x80
+
+#define GPIO_RISING_EDGE		1
+#define GPIO_FALLING_EDGE		2
+#define GPIO_BOTH_EDGES			3
+
+
+/* SDRAM & SRAM controller block */
+#define SDC0_CSSD0_CFG			(SDC0_BASEADDR + 0x00)
+#define SDC0_CSSD1_CFG			(SDC0_BASEADDR + 0x04)
+#define SDC0_CSBOOT_CFG			(SDC0_BASEADDR + 0x08)
+#define SDC0_CSP0_CFG			(SDC0_BASEADDR + 0x0C)
+#define SDC0_SDRAM_CFG1			(SDC0_BASEADDR + 0x10)
+#define SDC0_SDRAM_CFG2			(SDC0_BASEADDR + 0x14)
+#define SDC0_SDRAM_REFRESH		(SDC0_BASEADDR + 0x18)
+#define SDC0_SDRAM_POWERON		(SDC0_BASEADDR + 0x1C)
+#define SDC0_CSP1_CFG			(SDC0_BASEADDR + 0x20)
+#define SDC0_VERSION			(SDC0_BASEADDR + 0x28)
+#define SDC0_DEV_ID                     (SDC0_BASEADDR + 0x2C)
+
+
+/* UART */
+#define UART_RBR			(UART0_BASEADDR + 0x00)		/* Receive Buffer Register (R/O) */
+#define UART_THR			(UART0_BASEADDR + 0x00)		/* Transmit Holding Register (W/O) */
+#define UART_IER			(UART0_BASEADDR + 0x04)		/* Interrupt Enable Register */
+#define UART_MCR			(UART0_BASEADDR + 0x08)		/* Mode Control Register */
+#define UART_LCR			(UART0_BASEADDR + 0x0C)		/* Line Control Register */
+#define UART_SSR			(UART0_BASEADDR + 0x10)		/* Serial Status Register */
+#define UART_FCR			(UART0_BASEADDR + 0x14)		/* Form Control Register */
+#define UART_RXD			(UART0_BASEADDR + 0x18)		/* Transmiter Divider Latch (R/O) */
+#define UART_TXD			(UART0_BASEADDR + 0x1C)		/* Receiver Divider Latch (W/O) */
+#define UART_HR				(UART0_BASEADDR + 0x20)		/* Hunt Character */
+
+
+/* Clock block */
+#define CLKCORE_ARM_PLL 		(CLKCORE_BASEADDR + 0x00)
+#define CLKCORE_SPU_PLL			(CLKCORE_BASEADDR + 0x04)
+#define CLKCORE_AMBA_PLL		(CLKCORE_BASEADDR + 0x08)
+
+#define PLL_POWER			0x04000000	/* PLL power control */
+#define PLL_BYPASS			0x02000000	/* PLL bypass */
+#define PLL_MUXSEL			0x01000000	/* PLL clock source selection */
+#define PLL_RESET			0x00800000	/* PLL reset */
+
+
+/* GEMAC */
+
+#include "gemac.h"
+
+
+/* IDMA */
+#include "idma.h"
+
+
+/* Eram */
+#define ERAM_BIST_CTRL			(ERAM_CFG_BASEADDR + 0x00)
+#define ERAM_SPARE_FAIL			(ERAM_CFG_BASEADDR + 0x04)
+#define ERAM_BIST_ADDR			(ERAM_CFG_BASEADDR + 0x08)
+#define ERAM_BIST_BCK			(ERAM_CFG_BASEADDR + 0x0C)
+#define ERAM_MROW_FAIL			(ERAM_CFG_BASEADDR + 0x10)
+#define ERAM_MCOL_FAIL			(ERAM_CFG_BASEADDR + 0x14)
+#define ERAM_SHIFT_COL_FAIL		(ERAM_CFG_BASEADDR + 0x18)
+#define ERAM_RETN_TIME			(ERAM_CFG_BASEADDR + 0x1C)
+#define ERAM_SPCOL_ALLOC		(ERAM_CFG_BASEADDR + 0x20)
+#define ERAM_SPROW_ALLOC		(ERAM_CFG_BASEADDR + 0x30)
+#define ERAM_FUSE_SPCOL			(ERAM_CFG_BASEADDR + 0x40)
+#define ERAM_FUSE_SPROW			(ERAM_CFG_BASEADDR + 0x50)
+#define ERAM_IRAM_FAIL			(ERAM_CFG_BASEADDR + 0x60)
+
+/* Eram bus arbiter */
+#define ASA_ERAM_PRIORITY		(ASA_ERAM_BASEADDR + 0x00)
+#define ASA_ERAM_TERMINAL_COUNT		(ASA_ERAM_BASEADDR + 0x04)
+#define ASA_ERAM_TERMINAL_COUNT_CFG	(ASA_ERAM_BASEADDR + 0x08)
+
+
+#ifndef	__ASSEMBLY__
+static inline void HAL_set_arm_clk(u32 fclk)
+{
+	volatile u32 delay_count;
+	u32 clkf = 2 * fclk / CFG_REFCLKFREQ;
+
+	// set PLL into BYPASS mode
+	*(volatile u32 *)CLKCORE_ARM_PLL |= PLL_BYPASS;
+	*(volatile u32 *)CLKCORE_ARM_PLL &= 0xFFFF0000;
+
+	// reset PLL
+	*(volatile u32 *)CLKCORE_ARM_PLL |= PLL_RESET | clkf;
+
+	//wait 5us for PLL to lock
+	delay_count = 10;
+	while (delay_count--);
+
+	// take PLL out of reset
+	*(volatile u32 *)CLKCORE_ARM_PLL &= ~PLL_RESET;
+
+	//wait 500 cycles
+	delay_count = 500;
+	while (delay_count--);
+
+	// enable PLL
+	*(volatile u32 *)CLKCORE_ARM_PLL &= ~PLL_BYPASS;
+}
+
+
+static inline void HAL_set_amba_clk(u32 fclk)
+{
+	volatile u32 delay_count;
+	u32 clkf = 4 * fclk / CFG_REFCLKFREQ;
+
+	// set PLL into BYPASS mode
+	*(volatile u32 *)CLKCORE_AMBA_PLL |= PLL_BYPASS;
+	*(volatile u32 *)CLKCORE_AMBA_PLL &= 0xFFFF0000;
+
+	// reset PLL
+	*(volatile u32 *)CLKCORE_AMBA_PLL |= PLL_RESET | PLL_MUXSEL | clkf;
+
+	//wait 5us for PLL to lock
+	delay_count = 10;
+	while (delay_count--);
+
+	// take PLL out of reset
+	*(volatile u32 *)CLKCORE_AMBA_PLL &= ~PLL_RESET;
+
+	//wait 500 cycles
+	delay_count = 500;
+	while (delay_count--);
+
+	// enable PLL
+	*(volatile u32 *)CLKCORE_AMBA_PLL &= ~PLL_BYPASS;
+}
+#endif
+
+#define HAL_asb_arbitration(arbitration_mask) (*(volatile u32 *)ASA_TERMINAL_COUNT_CFG |= (arbitration_mask))
+
+
+#define HAL_get_amba_clk() ((CFG_REFCLKFREQ * (*(volatile u32 *)CLKCORE_AMBA_PLL & 0x7F)) >> 2)
+
+
+#endif /* __COMCERTO_900_H */

include/asm-arm/arch-comcerto/ddr_c2000.h

diff --git a/include/asm-arm/arch-comcerto/ddr_c2000.h b/include/asm-arm/arch-comcerto/ddr_c2000.h
new file mode 100644
index 0000000..b21ab00
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/ddr_c2000.h
@@ -0,0 +1,839 @@
+#include "comcerto_2000.h"
+
+/* DDR Controller Registers */
+#define DDRC_CTL_00_REG          (COMCERTO_APB_DDR_BASE + 0x00)
+#define DDRC_CTL_01_REG          (COMCERTO_APB_DDR_BASE + 0x04)
+#define DDRC_CTL_02_REG          (COMCERTO_APB_DDR_BASE + 0x08)
+#define DDRC_CTL_03_REG          (COMCERTO_APB_DDR_BASE + 0x0c)
+#define DDRC_CTL_04_REG          (COMCERTO_APB_DDR_BASE + 0x10)
+#define DDRC_CTL_05_REG          (COMCERTO_APB_DDR_BASE + 0x14)
+#define DDRC_CTL_06_REG          (COMCERTO_APB_DDR_BASE + 0x18)
+#define DDRC_CTL_07_REG          (COMCERTO_APB_DDR_BASE + 0x1c)
+#define DDRC_CTL_08_REG          (COMCERTO_APB_DDR_BASE + 0x20)
+#define DDRC_CTL_09_REG          (COMCERTO_APB_DDR_BASE + 0x24)
+#define DDRC_CTL_10_REG          (COMCERTO_APB_DDR_BASE + 0x28)
+#define DDRC_CTL_11_REG          (COMCERTO_APB_DDR_BASE + 0x2c)
+#define DDRC_CTL_12_REG          (COMCERTO_APB_DDR_BASE + 0x30)
+#define DDRC_CTL_13_REG          (COMCERTO_APB_DDR_BASE + 0x34)
+#define DDRC_CTL_14_REG          (COMCERTO_APB_DDR_BASE + 0x38)
+#define DDRC_CTL_15_REG          (COMCERTO_APB_DDR_BASE + 0x3c)
+#define DDRC_CTL_16_REG          (COMCERTO_APB_DDR_BASE + 0x40)
+#define DDRC_CTL_17_REG          (COMCERTO_APB_DDR_BASE + 0x44)
+#define DDRC_CTL_18_REG          (COMCERTO_APB_DDR_BASE + 0x48)
+#define DDRC_CTL_19_REG          (COMCERTO_APB_DDR_BASE + 0x4c)
+#define DDRC_CTL_20_REG          (COMCERTO_APB_DDR_BASE + 0x50)
+#define DDRC_CTL_21_REG          (COMCERTO_APB_DDR_BASE + 0x54)
+#define DDRC_CTL_22_REG          (COMCERTO_APB_DDR_BASE + 0x58)
+#define DDRC_CTL_23_REG          (COMCERTO_APB_DDR_BASE + 0x5c)
+#define DDRC_CTL_24_REG          (COMCERTO_APB_DDR_BASE + 0x60)
+#define DDRC_CTL_25_REG          (COMCERTO_APB_DDR_BASE + 0x64)
+#define DDRC_CTL_26_REG          (COMCERTO_APB_DDR_BASE + 0x68)
+#define DDRC_CTL_27_REG          (COMCERTO_APB_DDR_BASE + 0x6c)
+#define DDRC_CTL_28_REG          (COMCERTO_APB_DDR_BASE + 0x70)
+#define DDRC_CTL_29_REG          (COMCERTO_APB_DDR_BASE + 0x74)
+#define DDRC_CTL_30_REG          (COMCERTO_APB_DDR_BASE + 0x78)
+#define DDRC_CTL_31_REG          (COMCERTO_APB_DDR_BASE + 0x7c)
+#define DDRC_CTL_32_REG          (COMCERTO_APB_DDR_BASE + 0x80)
+#define DDRC_CTL_33_REG          (COMCERTO_APB_DDR_BASE + 0x84)
+#define DDRC_CTL_34_REG          (COMCERTO_APB_DDR_BASE + 0x88)
+#define DDRC_CTL_35_REG          (COMCERTO_APB_DDR_BASE + 0x8c)
+#define DDRC_CTL_36_REG          (COMCERTO_APB_DDR_BASE + 0x90)
+#define DDRC_CTL_37_REG          (COMCERTO_APB_DDR_BASE + 0x94)
+#define DDRC_CTL_38_REG          (COMCERTO_APB_DDR_BASE + 0x98)
+#define DDRC_CTL_39_REG          (COMCERTO_APB_DDR_BASE + 0x9c)
+#define DDRC_CTL_40_REG          (COMCERTO_APB_DDR_BASE + 0xa0)
+#define DDRC_CTL_41_REG          (COMCERTO_APB_DDR_BASE + 0xa4)
+#define DDRC_CTL_42_REG          (COMCERTO_APB_DDR_BASE + 0xa8)
+#define DDRC_CTL_43_REG          (COMCERTO_APB_DDR_BASE + 0xac)
+#define DDRC_CTL_44_REG          (COMCERTO_APB_DDR_BASE + 0xb0)
+#define DDRC_CTL_45_REG          (COMCERTO_APB_DDR_BASE + 0xb4)
+#define DDRC_CTL_46_REG          (COMCERTO_APB_DDR_BASE + 0xb8)
+#define DDRC_CTL_47_REG          (COMCERTO_APB_DDR_BASE + 0xbc)
+#define DDRC_CTL_48_REG          (COMCERTO_APB_DDR_BASE + 0xc0)
+#define DDRC_CTL_49_REG          (COMCERTO_APB_DDR_BASE + 0xc4)
+#define DDRC_CTL_50_REG          (COMCERTO_APB_DDR_BASE + 0xc8)
+#define DDRC_CTL_51_REG          (COMCERTO_APB_DDR_BASE + 0xcc)
+#define DDRC_CTL_52_REG          (COMCERTO_APB_DDR_BASE + 0xd0)
+#define DDRC_CTL_53_REG          (COMCERTO_APB_DDR_BASE + 0xd4)
+#define DDRC_CTL_54_REG          (COMCERTO_APB_DDR_BASE + 0xd8)
+#define DDRC_CTL_55_REG          (COMCERTO_APB_DDR_BASE + 0xdc)
+#define DDRC_CTL_56_REG          (COMCERTO_APB_DDR_BASE + 0xe0)
+#define DDRC_CTL_57_REG          (COMCERTO_APB_DDR_BASE + 0xe4)
+#define DDRC_CTL_58_REG          (COMCERTO_APB_DDR_BASE + 0xe8)
+#define DDRC_CTL_59_REG          (COMCERTO_APB_DDR_BASE + 0xec)
+#define DDRC_CTL_60_REG          (COMCERTO_APB_DDR_BASE + 0xf0)
+#define DDRC_CTL_61_REG          (COMCERTO_APB_DDR_BASE + 0xf4)
+#define DDRC_CTL_62_REG          (COMCERTO_APB_DDR_BASE + 0xf8)
+#define DDRC_CTL_63_REG          (COMCERTO_APB_DDR_BASE + 0xfc)
+#define DDRC_CTL_64_REG          (COMCERTO_APB_DDR_BASE + 0x100)
+#define DDRC_CTL_65_REG          (COMCERTO_APB_DDR_BASE + 0x104)
+#define DDRC_CTL_66_REG          (COMCERTO_APB_DDR_BASE + 0x108)
+#define DDRC_CTL_67_REG          (COMCERTO_APB_DDR_BASE + 0x10c)
+#define DDRC_CTL_68_REG          (COMCERTO_APB_DDR_BASE + 0x110)
+#define DDRC_CTL_69_REG          (COMCERTO_APB_DDR_BASE + 0x114)
+#define DDRC_CTL_70_REG          (COMCERTO_APB_DDR_BASE + 0x118)
+#define DDRC_CTL_71_REG          (COMCERTO_APB_DDR_BASE + 0x11c)
+#define DDRC_CTL_72_REG          (COMCERTO_APB_DDR_BASE + 0x120)
+#define DDRC_CTL_73_REG          (COMCERTO_APB_DDR_BASE + 0x124)
+#define DDRC_CTL_74_REG          (COMCERTO_APB_DDR_BASE + 0x128)
+#define DDRC_CTL_75_REG          (COMCERTO_APB_DDR_BASE + 0x12c)
+#define DDRC_CTL_76_REG          (COMCERTO_APB_DDR_BASE + 0x130)
+#define DDRC_CTL_77_REG          (COMCERTO_APB_DDR_BASE + 0x134)
+#define DDRC_CTL_78_REG          (COMCERTO_APB_DDR_BASE + 0x138)
+#define DDRC_CTL_79_REG          (COMCERTO_APB_DDR_BASE + 0x13c)
+#define DDRC_CTL_80_REG          (COMCERTO_APB_DDR_BASE + 0x140)
+#define DDRC_CTL_81_REG          (COMCERTO_APB_DDR_BASE + 0x144)
+#define DDRC_CTL_82_REG          (COMCERTO_APB_DDR_BASE + 0x148)
+#define DDRC_CTL_83_REG          (COMCERTO_APB_DDR_BASE + 0x14c)
+#define DDRC_CTL_84_REG          (COMCERTO_APB_DDR_BASE + 0x150)
+#define DDRC_CTL_85_REG          (COMCERTO_APB_DDR_BASE + 0x154)
+#define DDRC_CTL_86_REG          (COMCERTO_APB_DDR_BASE + 0x158)
+#define DDRC_CTL_87_REG          (COMCERTO_APB_DDR_BASE + 0x15c)
+#define DDRC_CTL_88_REG          (COMCERTO_APB_DDR_BASE + 0x160)
+#define DDRC_CTL_89_REG          (COMCERTO_APB_DDR_BASE + 0x164)
+#define DDRC_CTL_90_REG          (COMCERTO_APB_DDR_BASE + 0x168)
+#define DDRC_CTL_91_REG          (COMCERTO_APB_DDR_BASE + 0x16c)
+#define DDRC_CTL_92_REG          (COMCERTO_APB_DDR_BASE + 0x170)
+#define DDRC_CTL_93_REG          (COMCERTO_APB_DDR_BASE + 0x174)
+#define DDRC_CTL_94_REG          (COMCERTO_APB_DDR_BASE + 0x178)
+#define DDRC_CTL_95_REG          (COMCERTO_APB_DDR_BASE + 0x17c)
+#define DDRC_CTL_96_REG          (COMCERTO_APB_DDR_BASE + 0x180)
+#define DDRC_CTL_97_REG          (COMCERTO_APB_DDR_BASE + 0x184)
+#define DDRC_CTL_98_REG          (COMCERTO_APB_DDR_BASE + 0x188)
+#define DDRC_CTL_99_REG          (COMCERTO_APB_DDR_BASE + 0x18c)
+#define DDRC_CTL_100_REG          (COMCERTO_APB_DDR_BASE + 0x190)
+#define DDRC_CTL_101_REG          (COMCERTO_APB_DDR_BASE + 0x194)
+#define DDRC_CTL_102_REG          (COMCERTO_APB_DDR_BASE + 0x198)
+#define DDRC_CTL_103_REG          (COMCERTO_APB_DDR_BASE + 0x19c)
+#define DDRC_CTL_104_REG          (COMCERTO_APB_DDR_BASE + 0x1a0)
+#define DDRC_CTL_105_REG          (COMCERTO_APB_DDR_BASE + 0x1a4)
+#define DDRC_CTL_106_REG          (COMCERTO_APB_DDR_BASE + 0x1a8)
+#define DDRC_CTL_107_REG          (COMCERTO_APB_DDR_BASE + 0x1ac)
+#define DDRC_CTL_108_REG          (COMCERTO_APB_DDR_BASE + 0x1b0)
+#define DDRC_CTL_109_REG          (COMCERTO_APB_DDR_BASE + 0x1b4)
+#define DDRC_CTL_110_REG          (COMCERTO_APB_DDR_BASE + 0x1b8)
+#define DDRC_CTL_111_REG          (COMCERTO_APB_DDR_BASE + 0x1bc)
+#define DDRC_CTL_112_REG          (COMCERTO_APB_DDR_BASE + 0x1c0)
+#define DDRC_CTL_113_REG          (COMCERTO_APB_DDR_BASE + 0x1c4)
+#define DDRC_CTL_114_REG          (COMCERTO_APB_DDR_BASE + 0x1c8)
+#define DDRC_CTL_115_REG          (COMCERTO_APB_DDR_BASE + 0x1cc)
+#define DDRC_CTL_116_REG          (COMCERTO_APB_DDR_BASE + 0x1d0)
+#define DDRC_CTL_117_REG          (COMCERTO_APB_DDR_BASE + 0x1d4)
+#define DDRC_CTL_118_REG          (COMCERTO_APB_DDR_BASE + 0x1d8)
+#define DDRC_CTL_119_REG          (COMCERTO_APB_DDR_BASE + 0x1dc)
+#define DDRC_CTL_120_REG          (COMCERTO_APB_DDR_BASE + 0x1e0)
+#define DDRC_CTL_121_REG          (COMCERTO_APB_DDR_BASE + 0x1e4)
+#define DDRC_CTL_122_REG          (COMCERTO_APB_DDR_BASE + 0x1e8)
+#define DDRC_CTL_123_REG          (COMCERTO_APB_DDR_BASE + 0x1ec)
+#define DDRC_CTL_124_REG          (COMCERTO_APB_DDR_BASE + 0x1f0)
+#define DDRC_CTL_125_REG          (COMCERTO_APB_DDR_BASE + 0x1f4)
+#define DDRC_CTL_126_REG          (COMCERTO_APB_DDR_BASE + 0x1f8)
+
+/* DDR PHY Registers */
+#define DDR_PHY_CTL_00_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x00)
+#define DDR_PHY_CTL_01_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x04)
+#define DDR_PHY_CTL_02_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x08)
+#define DDR_PHY_CTL_03_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x0C)
+#define DDR_PHY_CTL_04_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x10)
+#define DDR_PHY_CTL_05_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x14)
+#define DDR_PHY_CTL_06_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x18)
+#define DDR_PHY_CTL_07_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x1C)
+#define DDR_PHY_DLL_STAT_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x70)
+#define DDR_PHY_ZQ_STAT_REG	(COMCERTO_APB_DDR_PHY_BASE + 0x74)
+
+//DDR2@ 400MHz
+#define DDRC_CTL_DDR2_00_VAL_CFG1  0x00000400
+//#define DDRC_CTL_DDR2_01_VAL_CFG1 0x00000000
+#define DDRC_CTL_DDR2_02_VAL_CFG1  0x00000050
+#define DDRC_CTL_DDR2_03_VAL_CFG1  0x00000050
+#define DDRC_CTL_DDR2_04_VAL_CFG1  0x000000c8
+#define DDRC_CTL_DDR2_05_VAL_CFG1  0x02050c02
+#define DDRC_CTL_DDR2_06_VAL_CFG1  0x10160302
+#define DDRC_CTL_DDR2_07_VAL_CFG1  0x02030603
+#define DDRC_CTL_DDR2_08_VAL_CFG1  0x006d6005
+#define DDRC_CTL_DDR2_09_VAL_CFG1  0x00000303
+#define DDRC_CTL_DDR2_10_VAL_CFG1  0x06060101
+#define DDRC_CTL_DDR2_11_VAL_CFG1  0x0000c80c
+#define DDRC_CTL_DDR2_12_VAL_CFG1  0x00a00e02
+#define DDRC_CTL_DDR2_13_VAL_CFG1  0x00000007
+#define DDRC_CTL_DDR2_14_VAL_CFG1  0x00330100
+#define DDRC_CTL_DDR2_15_VAL_CFG1  0x00000c2d
+#define DDRC_CTL_DDR2_16_VAL_CFG1  0x000a0003
+#define DDRC_CTL_DDR2_17_VAL_CFG1  0x000a0003
+#define DDRC_CTL_DDR2_18_VAL_CFG1  0x003700c8
+#define DDRC_CTL_DDR2_19_VAL_CFG1  0x00010000
+#define DDRC_CTL_DDR2_20_VAL_CFG1  0x00030300
+#define DDRC_CTL_DDR2_21_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_22_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_23_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_24_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_25_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_26_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_27_VAL_CFG1  0x000a6200
+#define DDRC_CTL_DDR2_28_VAL_CFG1  0x00000004
+#define DDRC_CTL_DDR2_29_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_30_VAL_CFG1  0x00040a62
+#define DDRC_CTL_DDR2_31_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_32_VAL_CFG1  0x00020000
+#define DDRC_CTL_DDR2_33_VAL_CFG1  0x00000000
+//#define DDRC_CTL_DDR2_34_VAL_CFG1 0x00000000
+//#define DDRC_CTL_DDR2_35_VAL_CFG1 0x00000000
+//#define DDRC_CTL_DDR2_36_VAL_CFG1 0x00000000
+//#define DDRC_CTL_DDR2_37_VAL_CFG1 0x00000000
+//#define DDRC_CTL_DDR2_38_VAL_CFG1 0x00000000
+//#define DDRC_CTL_DDR2_39_VAL_CFG1 0x00000000
+//#define DDRC_CTL_DDR2_40_VAL_CFG1 0x00000000
+//#define DDRC_CTL_DDR2_41_VAL_CFG1 0x00000000
+//#define DDRC_CTL_DDR2_42_VAL_CFG1 0x00000000
+#define DDRC_CTL_DDR2_43_VAL_CFG1  0x01000200
+#define DDRC_CTL_DDR2_44_VAL_CFG1  0x02000040
+#define DDRC_CTL_DDR2_45_VAL_CFG1  0x00010040
+#define DDRC_CTL_DDR2_46_VAL_CFG1  0xff0a0203
+#define DDRC_CTL_DDR2_47_VAL_CFG1  0x010101ff
+#define DDRC_CTL_DDR2_48_VAL_CFG1  0x01010101
+#define DDRC_CTL_DDR2_49_VAL_CFG1  0x000c0100
+#define DDRC_CTL_DDR2_50_VAL_CFG1  0x00010000
+//#define DDRC_CTL_DDR2_51_VAL_CFG1 0x00000000
+#define DDRC_CTL_DDR2_52_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_53_VAL_CFG1  0x00000000
+//#define DDRC_CTL_DDR2_54_VAL_CFG1 0x00000000
+//#define DDRC_CTL_DDR2_55_VAL_CFG1 0x00000000
+//#define DDRC_CTL_DDR2_56_VAL_CFG1 0x00000000
+//#define DDRC_CTL_DDR2_57_VAL_CFG1 0x00000000
+//#define DDRC_CTL_DDR2_58_VAL_CFG1 0x00000000
+#define DDRC_CTL_DDR2_59_VAL_CFG1  0x01010000
+#define DDRC_CTL_DDR2_60_VAL_CFG1  0x00000202
+#define DDRC_CTL_DDR2_61_VAL_CFG1  0x02020302
+#define DDRC_CTL_DDR2_62_VAL_CFG1  0x01000101
+#define DDRC_CTL_DDR2_63_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_64_VAL_CFG1  0x00000000
+//#define DDRC_CTL_DDR2_65_VAL_CFG1 0x00000000
+#define DDRC_CTL_DDR2_66_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_67_VAL_CFG1  0x00281900
+#define DDRC_CTL_DDR2_68_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_69_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_70_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_71_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_72_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_73_VAL_CFG1  0x00000000
+//#define DDRC_CTL_DDR2_74_VAL_CFG1 0x00000000
+#define DDRC_CTL_DDR2_75_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_76_VAL_CFG1  0x001d1d00
+#define DDRC_CTL_DDR2_77_VAL_CFG1  0x00000000
+//#define DDRC_CTL_DDR2_78_VAL_CFG1 0x00000000
+#define DDRC_CTL_DDR2_79_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_80_VAL_CFG1  0x00001d1d
+//#define DDRC_CTL_DDR2_81_VAL_CFG1 0x00000000
+#define DDRC_CTL_DDR2_82_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_83_VAL_CFG1  0x001d1d00
+#define DDRC_CTL_DDR2_84_VAL_CFG1  0x00000000
+//#define DDRC_CTL_DDR2_85_VAL_CFG1 0x00000000
+#define DDRC_CTL_DDR2_86_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_87_VAL_CFG1  0x00001d1d
+//#define DDRC_CTL_DDR2_88_VAL_CFG1 0x00000000
+#define DDRC_CTL_DDR2_89_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_90_VAL_CFG1  0x001d1d00
+#define DDRC_CTL_DDR2_91_VAL_CFG1  0xffff0000
+#define DDRC_CTL_DDR2_92_VAL_CFG1  0x00000202
+#define DDRC_CTL_DDR2_93_VAL_CFG1  0x0101ffff
+#define DDRC_CTL_DDR2_94_VAL_CFG1  0x02ffff00
+#define DDRC_CTL_DDR2_95_VAL_CFG1  0xffff0002
+#define DDRC_CTL_DDR2_96_VAL_CFG1  0x00000202
+#define DDRC_CTL_DDR2_97_VAL_CFG1  0x01320300
+#define DDRC_CTL_DDR2_98_VAL_CFG1  0x00013200
+#define DDRC_CTL_DDR2_99_VAL_CFG1  0x32000132
+#define DDRC_CTL_DDR2_100_VAL_CFG1  0x00000001
+#define DDRC_CTL_DDR2_101_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_102_VAL_CFG1  0x00000700
+#define DDRC_CTL_DDR2_103_VAL_CFG1  0x000c2d00
+#define DDRC_CTL_DDR2_104_VAL_CFG1  0x02000200
+#define DDRC_CTL_DDR2_105_VAL_CFG1  0x02000200
+#define DDRC_CTL_DDR2_106_VAL_CFG1  0x00000c2d
+#define DDRC_CTL_DDR2_107_VAL_CFG1  0x00003ce1
+#define DDRC_CTL_DDR2_108_VAL_CFG1  0x0002050C
+#define DDRC_CTL_DDR2_109_VAL_CFG1  0x03800001
+#define DDRC_CTL_DDR2_110_VAL_CFG1  0x00040703
+#define DDRC_CTL_DDR2_111_VAL_CFG1  0x0000000a
+#define DDRC_CTL_DDR2_112_VAL_CFG1  0x00000c2d
+#define DDRC_CTL_DDR2_113_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_114_VAL_CFG1  0x0010ffff
+#define DDRC_CTL_DDR2_115_VAL_CFG1  0x11070303
+#define DDRC_CTL_DDR2_116_VAL_CFG1  0x0000000f
+#define DDRC_CTL_DDR2_117_VAL_CFG1  0x00000c2d
+#define DDRC_CTL_DDR2_118_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_119_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_120_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_121_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_122_VAL_CFG1  0x00000c2d
+#define DDRC_CTL_DDR2_123_VAL_CFG1  0x00000204
+//#define DDRC_CTL_DDR2_124_VAL_CFG1 0x00000000
+#define DDRC_CTL_DDR2_125_VAL_CFG1  0x00000000
+#define DDRC_CTL_DDR2_126_VAL_CFG1  0x00000001
+
+
+#define DDRC_DDR2_CFG_400 \
+{DDRC_CTL_00_REG, DDRC_CTL_DDR2_00_VAL_CFG1},\
+{DDRC_CTL_03_REG, DDRC_CTL_DDR2_03_VAL_CFG1},\
+{DDRC_CTL_04_REG, DDRC_CTL_DDR2_04_VAL_CFG1},\
+{DDRC_CTL_05_REG, DDRC_CTL_DDR2_05_VAL_CFG1},\
+{DDRC_CTL_06_REG, DDRC_CTL_DDR2_06_VAL_CFG1},\
+{DDRC_CTL_07_REG, DDRC_CTL_DDR2_07_VAL_CFG1},\
+{DDRC_CTL_08_REG, DDRC_CTL_DDR2_08_VAL_CFG1},\
+{DDRC_CTL_09_REG, DDRC_CTL_DDR2_09_VAL_CFG1},\
+{DDRC_CTL_10_REG, DDRC_CTL_DDR2_10_VAL_CFG1},\
+{DDRC_CTL_11_REG, DDRC_CTL_DDR2_11_VAL_CFG1},\
+{DDRC_CTL_12_REG, DDRC_CTL_DDR2_12_VAL_CFG1},\
+{DDRC_CTL_13_REG, DDRC_CTL_DDR2_13_VAL_CFG1},\
+{DDRC_CTL_14_REG, DDRC_CTL_DDR2_14_VAL_CFG1},\
+{DDRC_CTL_15_REG, DDRC_CTL_DDR2_15_VAL_CFG1},\
+{DDRC_CTL_16_REG, DDRC_CTL_DDR2_16_VAL_CFG1},\
+{DDRC_CTL_17_REG, DDRC_CTL_DDR2_17_VAL_CFG1},\
+{DDRC_CTL_18_REG, DDRC_CTL_DDR2_18_VAL_CFG1},\
+{DDRC_CTL_19_REG, DDRC_CTL_DDR2_19_VAL_CFG1},\
+{DDRC_CTL_20_REG, DDRC_CTL_DDR2_20_VAL_CFG1},\
+{DDRC_CTL_21_REG, DDRC_CTL_DDR2_21_VAL_CFG1},\
+{DDRC_CTL_22_REG, DDRC_CTL_DDR2_22_VAL_CFG1},\
+{DDRC_CTL_23_REG, DDRC_CTL_DDR2_23_VAL_CFG1},\
+{DDRC_CTL_24_REG, DDRC_CTL_DDR2_24_VAL_CFG1},\
+{DDRC_CTL_25_REG, DDRC_CTL_DDR2_25_VAL_CFG1},\
+{DDRC_CTL_26_REG, DDRC_CTL_DDR2_26_VAL_CFG1},\
+{DDRC_CTL_27_REG, DDRC_CTL_DDR2_27_VAL_CFG1},\
+{DDRC_CTL_28_REG, DDRC_CTL_DDR2_28_VAL_CFG1},\
+{DDRC_CTL_29_REG, DDRC_CTL_DDR2_29_VAL_CFG1},\
+{DDRC_CTL_30_REG, DDRC_CTL_DDR2_30_VAL_CFG1},\
+{DDRC_CTL_31_REG, DDRC_CTL_DDR2_31_VAL_CFG1},\
+{DDRC_CTL_32_REG, DDRC_CTL_DDR2_32_VAL_CFG1},\
+{DDRC_CTL_33_REG, DDRC_CTL_DDR2_33_VAL_CFG1},\
+{DDRC_CTL_43_REG, DDRC_CTL_DDR2_43_VAL_CFG1},\
+{DDRC_CTL_44_REG, DDRC_CTL_DDR2_44_VAL_CFG1},\
+{DDRC_CTL_45_REG, DDRC_CTL_DDR2_45_VAL_CFG1},\
+{DDRC_CTL_46_REG, DDRC_CTL_DDR2_46_VAL_CFG1},\
+{DDRC_CTL_47_REG, DDRC_CTL_DDR2_47_VAL_CFG1},\
+{DDRC_CTL_48_REG, DDRC_CTL_DDR2_48_VAL_CFG1},\
+{DDRC_CTL_49_REG, DDRC_CTL_DDR2_49_VAL_CFG1},\
+{DDRC_CTL_50_REG, DDRC_CTL_DDR2_50_VAL_CFG1},\
+{DDRC_CTL_52_REG, DDRC_CTL_DDR2_52_VAL_CFG1},\
+{DDRC_CTL_53_REG, DDRC_CTL_DDR2_53_VAL_CFG1},\
+{DDRC_CTL_59_REG, DDRC_CTL_DDR2_59_VAL_CFG1},\
+{DDRC_CTL_60_REG, DDRC_CTL_DDR2_60_VAL_CFG1},\
+{DDRC_CTL_61_REG, DDRC_CTL_DDR2_61_VAL_CFG1},\
+{DDRC_CTL_62_REG, DDRC_CTL_DDR2_62_VAL_CFG1},\
+{DDRC_CTL_63_REG, DDRC_CTL_DDR2_63_VAL_CFG1},\
+{DDRC_CTL_64_REG, DDRC_CTL_DDR2_64_VAL_CFG1},\
+{DDRC_CTL_66_REG, DDRC_CTL_DDR2_66_VAL_CFG1},\
+{DDRC_CTL_67_REG, DDRC_CTL_DDR2_67_VAL_CFG1},\
+{DDRC_CTL_68_REG, DDRC_CTL_DDR2_68_VAL_CFG1},\
+{DDRC_CTL_69_REG, DDRC_CTL_DDR2_69_VAL_CFG1},\
+{DDRC_CTL_70_REG, DDRC_CTL_DDR2_70_VAL_CFG1},\
+{DDRC_CTL_71_REG, DDRC_CTL_DDR2_71_VAL_CFG1},\
+{DDRC_CTL_72_REG, DDRC_CTL_DDR2_72_VAL_CFG1},\
+{DDRC_CTL_73_REG, DDRC_CTL_DDR2_73_VAL_CFG1},\
+{DDRC_CTL_75_REG, DDRC_CTL_DDR2_75_VAL_CFG1},\
+{DDRC_CTL_76_REG, DDRC_CTL_DDR2_76_VAL_CFG1},\
+{DDRC_CTL_77_REG, DDRC_CTL_DDR2_77_VAL_CFG1},\
+{DDRC_CTL_79_REG, DDRC_CTL_DDR2_79_VAL_CFG1},\
+{DDRC_CTL_80_REG, DDRC_CTL_DDR2_80_VAL_CFG1},\
+{DDRC_CTL_82_REG, DDRC_CTL_DDR2_82_VAL_CFG1},\
+{DDRC_CTL_83_REG, DDRC_CTL_DDR2_83_VAL_CFG1},\
+{DDRC_CTL_84_REG, DDRC_CTL_DDR2_84_VAL_CFG1},\
+{DDRC_CTL_86_REG, DDRC_CTL_DDR2_86_VAL_CFG1},\
+{DDRC_CTL_87_REG, DDRC_CTL_DDR2_87_VAL_CFG1},\
+{DDRC_CTL_89_REG, DDRC_CTL_DDR2_89_VAL_CFG1},\
+{DDRC_CTL_90_REG, DDRC_CTL_DDR2_90_VAL_CFG1},\
+{DDRC_CTL_91_REG, DDRC_CTL_DDR2_91_VAL_CFG1},\
+{DDRC_CTL_92_REG, DDRC_CTL_DDR2_92_VAL_CFG1},\
+{DDRC_CTL_93_REG, DDRC_CTL_DDR2_93_VAL_CFG1},\
+{DDRC_CTL_94_REG, DDRC_CTL_DDR2_94_VAL_CFG1},\
+{DDRC_CTL_95_REG, DDRC_CTL_DDR2_95_VAL_CFG1},\
+{DDRC_CTL_96_REG, DDRC_CTL_DDR2_96_VAL_CFG1},\
+{DDRC_CTL_97_REG, DDRC_CTL_DDR2_97_VAL_CFG1},\
+{DDRC_CTL_98_REG, DDRC_CTL_DDR2_98_VAL_CFG1},\
+{DDRC_CTL_99_REG, DDRC_CTL_DDR2_99_VAL_CFG1},\
+{DDRC_CTL_100_REG, DDRC_CTL_DDR2_100_VAL_CFG1},\
+{DDRC_CTL_101_REG, DDRC_CTL_DDR2_101_VAL_CFG1},\
+{DDRC_CTL_102_REG, DDRC_CTL_DDR2_102_VAL_CFG1},\
+{DDRC_CTL_103_REG, DDRC_CTL_DDR2_103_VAL_CFG1},\
+{DDRC_CTL_104_REG, DDRC_CTL_DDR2_104_VAL_CFG1},\
+{DDRC_CTL_105_REG, DDRC_CTL_DDR2_105_VAL_CFG1},\
+{DDRC_CTL_106_REG, DDRC_CTL_DDR2_106_VAL_CFG1},\
+{DDRC_CTL_107_REG, DDRC_CTL_DDR2_107_VAL_CFG1},\
+{DDRC_CTL_108_REG, DDRC_CTL_DDR2_108_VAL_CFG1},\
+{DDRC_CTL_109_REG, DDRC_CTL_DDR2_109_VAL_CFG1},\
+{DDRC_CTL_110_REG, DDRC_CTL_DDR2_110_VAL_CFG1},\
+{DDRC_CTL_111_REG, DDRC_CTL_DDR2_111_VAL_CFG1},\
+{DDRC_CTL_112_REG, DDRC_CTL_DDR2_112_VAL_CFG1},\
+{DDRC_CTL_113_REG, DDRC_CTL_DDR2_113_VAL_CFG1},\
+{DDRC_CTL_114_REG, DDRC_CTL_DDR2_114_VAL_CFG1},\
+{DDRC_CTL_115_REG, DDRC_CTL_DDR2_115_VAL_CFG1},\
+{DDRC_CTL_116_REG, DDRC_CTL_DDR2_116_VAL_CFG1},\
+{DDRC_CTL_117_REG, DDRC_CTL_DDR2_117_VAL_CFG1},\
+{DDRC_CTL_118_REG, DDRC_CTL_DDR2_118_VAL_CFG1},\
+{DDRC_CTL_119_REG, DDRC_CTL_DDR2_119_VAL_CFG1},\
+{DDRC_CTL_120_REG, DDRC_CTL_DDR2_120_VAL_CFG1},\
+{DDRC_CTL_121_REG, DDRC_CTL_DDR2_121_VAL_CFG1},\
+{DDRC_CTL_122_REG, DDRC_CTL_DDR2_122_VAL_CFG1},\
+{DDRC_CTL_123_REG, DDRC_CTL_DDR2_123_VAL_CFG1},\
+{DDRC_CTL_125_REG, DDRC_CTL_DDR2_125_VAL_CFG1},\
+{DDRC_CTL_126_REG, DDRC_CTL_DDR2_126_VAL_CFG1}
+
+
+/******** DDR3 Controller @400MHz *******/
+#define DDRC_CTL_DDR3_000_VAL_CFG1  0x20410600LL
+//
+#define DDRC_CTL_DDR3_002_VAL_CFG1  0x00000006LL
+#define DDRC_CTL_DDR3_003_VAL_CFG1  0x0001388ALL
+#define DDRC_CTL_DDR3_004_VAL_CFG1  0x00030D4ALL
+#define DDRC_CTL_DDR3_005_VAL_CFG1  0x04060E00LL
+#define DDRC_CTL_DDR3_006_VAL_CFG1  0x0F150404LL
+#define DDRC_CTL_DDR3_007_VAL_CFG1  0x08040604LL
+#define DDRC_CTL_DDR3_008_VAL_CFG1  0x006D9C0CLL
+#define DDRC_CTL_DDR3_009_VAL_CFG1  0x00000103LL
+#define DDRC_CTL_DDR3_010_VAL_CFG1  0x06060101LL
+#define DDRC_CTL_DDR3_011_VAL_CFG1  0x0002000CLL
+#define DDRC_CTL_DDR3_012_VAL_CFG1  0x00011403LL
+#define DDRC_CTL_DDR3_013_VAL_CFG1  0x00000001LL
+#define DDRC_CTL_DDR3_014_VAL_CFG1  0x00400100LL
+#define DDRC_CTL_DDR3_015_VAL_CFG1  0x00000C26LL
+#define DDRC_CTL_DDR3_016_VAL_CFG1  0x000A0003LL
+#define DDRC_CTL_DDR3_017_VAL_CFG1  0x00060002LL
+#define DDRC_CTL_DDR3_018_VAL_CFG1  0x00440200LL
+#define DDRC_CTL_DDR3_019_VAL_CFG1  0x00000000LL
+#define DDRC_CTL_DDR3_020_VAL_CFG1  0x00050500LL
+#define DDRC_CTL_DDR3_021_VAL_CFG1  0x00000000LL
+#define DDRC_CTL_DDR3_022_VAL_CFG1  0x00000000LL
+#define DDRC_CTL_DDR3_023_VAL_CFG1  0x00000000LL
+#define DDRC_CTL_DDR3_024_VAL_CFG1  0x00000000LL
+#define DDRC_CTL_DDR3_025_VAL_CFG1  0x00000000LL
+#define DDRC_CTL_DDR3_026_VAL_CFG1  0x00000000LL
+#define DDRC_CTL_DDR3_027_VAL_CFG1  0x00043000LL
+#define DDRC_CTL_DDR3_028_VAL_CFG1  0x00080006LL
+#define DDRC_CTL_DDR3_029_VAL_CFG1  0x00000000LL
+#define DDRC_CTL_DDR3_030_VAL_CFG1  0x00060430LL
+#define DDRC_CTL_DDR3_031_VAL_CFG1  0x00000008LL
+#define DDRC_CTL_DDR3_032_VAL_CFG1  0x00020000LL
+#define DDRC_CTL_DDR3_033_VAL_CFG1  0x00000000LL
+//
+//
+//
+//
+//
+//
+//
+//
+//
+#define DDRC_CTL_DDR3_043_VAL_CFG1  0x01400200LL
+#define DDRC_CTL_DDR3_044_VAL_CFG1  0x02000040LL
+#define DDRC_CTL_DDR3_045_VAL_CFG1  0x01010080LL
+#define DDRC_CTL_DDR3_046_VAL_CFG1  0xFF0A0102LL
+#define DDRC_CTL_DDR3_047_VAL_CFG1  0x010101FFLL
+#define DDRC_CTL_DDR3_048_VAL_CFG1  0x00010001LL
+#define DDRC_CTL_DDR3_049_VAL_CFG1  0x000C0100LL
+#define DDRC_CTL_DDR3_050_VAL_CFG1  0x00010002LL
+//
+#define DDRC_CTL_DDR3_052_VAL_CFG1  0x00000000LL
+#define DDRC_CTL_DDR3_053_VAL_CFG1  0x007FFFFFLL
+//
+//
+//
+//
+//
+#define DDRC_CTL_DDR3_059_VAL_CFG1  0x01000000LL
+#define DDRC_CTL_DDR3_060_VAL_CFG1  0x00020100LL
+#define DDRC_CTL_DDR3_061_VAL_CFG1  0x02010202LL
+#define DDRC_CTL_DDR3_062_VAL_CFG1  0x02000101LL
+#define DDRC_CTL_DDR3_063_VAL_CFG1  0x00000000LL
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+#define DDRC_CTL_DDR3_091_VAL_CFG1  0xFFFF0000LL
+#define DDRC_CTL_DDR3_092_VAL_CFG1  0x00000202LL
+#define DDRC_CTL_DDR3_093_VAL_CFG1  0x0101FFFFLL
+#define DDRC_CTL_DDR3_094_VAL_CFG1  0x03FFFF00LL
+#define DDRC_CTL_DDR3_095_VAL_CFG1  0xFFFF0003LL
+#define DDRC_CTL_DDR3_096_VAL_CFG1  0x00000303LL
+#define DDRC_CTL_DDR3_097_VAL_CFG1  0x01000400LL
+#define DDRC_CTL_DDR3_098_VAL_CFG1  0x00016400LL
+#define DDRC_CTL_DDR3_099_VAL_CFG1  0x00000100LL
+#define DDRC_CTL_DDR3_100_VAL_CFG1  0x00000001LL
+//
+#define DDRC_CTL_DDR3_102_VAL_CFG1  0x00000800LL
+#define DDRC_CTL_DDR3_103_VAL_CFG1  0x00103300LL
+#define DDRC_CTL_DDR3_104_VAL_CFG1  0x02000200LL
+#define DDRC_CTL_DDR3_105_VAL_CFG1  0x02000200LL
+#define DDRC_CTL_DDR3_106_VAL_CFG1  0x00001033LL
+#define DDRC_CTL_DDR3_107_VAL_CFG1  0x000050FFLL
+#define DDRC_CTL_DDR3_108_VAL_CFG1  0x0002060CLL
+#define DDRC_CTL_DDR3_109_VAL_CFG1  0x00000003LL
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+#define DDRC_CTL_DDR3_126_VAL_CFG1  0x00000000LL
+
+/* DDR3 PHY @400 */
+#define DDR3_PHY_CTL_00_VAL_CFG1  0x000F1003LL
+#define DDR3_PHY_CTL_01_VAL_CFG1  0x18201010LL
+#define DDR3_PHY_CTL_02_VAL_CFG1  0x00000006LL
+#define DDR3_PHY_CTL_03_VAL_CFG1  0x00000000LL
+#define DDR3_PHY_CTL_04_VAL_CFG1  0x00000000LL
+#define DDR3_PHY_CTL_05_VAL_CFG1  0x00000000LL
+#define DDR3_PHY_CTL_06_VAL_CFG1  0x04300622LL
+#define DDR3_PHY_CTL_07_VAL_CFG1  0x00000000LL
+
+
+
+#define DDRC_DDR3_CFG_400 \
+{DDRC_CTL_00_REG, DDRC_CTL_DDR3_000_VAL_CFG1},\
+{DDRC_CTL_02_REG, DDRC_CTL_DDR3_002_VAL_CFG1},\
+{DDRC_CTL_03_REG, DDRC_CTL_DDR3_003_VAL_CFG1},\
+{DDRC_CTL_04_REG, DDRC_CTL_DDR3_004_VAL_CFG1},\
+{DDRC_CTL_05_REG, DDRC_CTL_DDR3_005_VAL_CFG1},\
+{DDRC_CTL_06_REG, DDRC_CTL_DDR3_006_VAL_CFG1},\
+{DDRC_CTL_07_REG, DDRC_CTL_DDR3_007_VAL_CFG1},\
+{DDRC_CTL_08_REG, DDRC_CTL_DDR3_008_VAL_CFG1},\
+{DDRC_CTL_09_REG, DDRC_CTL_DDR3_009_VAL_CFG1},\
+{DDRC_CTL_10_REG, DDRC_CTL_DDR3_010_VAL_CFG1},\
+{DDRC_CTL_11_REG, DDRC_CTL_DDR3_011_VAL_CFG1},\
+{DDRC_CTL_12_REG, DDRC_CTL_DDR3_012_VAL_CFG1},\
+{DDRC_CTL_13_REG, DDRC_CTL_DDR3_013_VAL_CFG1},\
+{DDRC_CTL_14_REG, DDRC_CTL_DDR3_014_VAL_CFG1},\
+{DDRC_CTL_15_REG, DDRC_CTL_DDR3_015_VAL_CFG1},\
+{DDRC_CTL_16_REG, DDRC_CTL_DDR3_016_VAL_CFG1},\
+{DDRC_CTL_17_REG, DDRC_CTL_DDR3_017_VAL_CFG1},\
+{DDRC_CTL_18_REG, DDRC_CTL_DDR3_018_VAL_CFG1},\
+{DDRC_CTL_19_REG, DDRC_CTL_DDR3_019_VAL_CFG1},\
+{DDRC_CTL_20_REG, DDRC_CTL_DDR3_020_VAL_CFG1},\
+{DDRC_CTL_21_REG, DDRC_CTL_DDR3_021_VAL_CFG1},\
+{DDRC_CTL_22_REG, DDRC_CTL_DDR3_022_VAL_CFG1},\
+{DDRC_CTL_23_REG, DDRC_CTL_DDR3_023_VAL_CFG1},\
+{DDRC_CTL_24_REG, DDRC_CTL_DDR3_024_VAL_CFG1},\
+{DDRC_CTL_25_REG, DDRC_CTL_DDR3_025_VAL_CFG1},\
+{DDRC_CTL_26_REG, DDRC_CTL_DDR3_026_VAL_CFG1},\
+{DDRC_CTL_27_REG, DDRC_CTL_DDR3_027_VAL_CFG1},\
+{DDRC_CTL_28_REG, DDRC_CTL_DDR3_028_VAL_CFG1},\
+{DDRC_CTL_29_REG, DDRC_CTL_DDR3_029_VAL_CFG1},\
+{DDRC_CTL_30_REG, DDRC_CTL_DDR3_030_VAL_CFG1},\
+{DDRC_CTL_31_REG, DDRC_CTL_DDR3_031_VAL_CFG1},\
+{DDRC_CTL_32_REG, DDRC_CTL_DDR3_032_VAL_CFG1},\
+{DDRC_CTL_33_REG, DDRC_CTL_DDR3_033_VAL_CFG1},\
+{DDRC_CTL_43_REG, DDRC_CTL_DDR3_043_VAL_CFG1},\
+{DDRC_CTL_44_REG, DDRC_CTL_DDR3_044_VAL_CFG1},\
+{DDRC_CTL_45_REG, DDRC_CTL_DDR3_045_VAL_CFG1},\
+{DDRC_CTL_46_REG, DDRC_CTL_DDR3_046_VAL_CFG1},\
+{DDRC_CTL_47_REG, DDRC_CTL_DDR3_047_VAL_CFG1},\
+{DDRC_CTL_48_REG, DDRC_CTL_DDR3_048_VAL_CFG1},\
+{DDRC_CTL_49_REG, DDRC_CTL_DDR3_049_VAL_CFG1},\
+{DDRC_CTL_50_REG, DDRC_CTL_DDR3_050_VAL_CFG1},\
+{DDRC_CTL_52_REG, DDRC_CTL_DDR3_052_VAL_CFG1},\
+{DDRC_CTL_53_REG, DDRC_CTL_DDR3_053_VAL_CFG1},\
+{DDRC_CTL_59_REG, DDRC_CTL_DDR3_059_VAL_CFG1},\
+{DDRC_CTL_60_REG, DDRC_CTL_DDR3_060_VAL_CFG1},\
+{DDRC_CTL_61_REG, DDRC_CTL_DDR3_061_VAL_CFG1},\
+{DDRC_CTL_62_REG, DDRC_CTL_DDR3_062_VAL_CFG1},\
+{DDRC_CTL_63_REG, DDRC_CTL_DDR3_063_VAL_CFG1},\
+{DDRC_CTL_91_REG, DDRC_CTL_DDR3_091_VAL_CFG1},\
+{DDRC_CTL_92_REG, DDRC_CTL_DDR3_092_VAL_CFG1},\
+{DDRC_CTL_93_REG, DDRC_CTL_DDR3_093_VAL_CFG1},\
+{DDRC_CTL_94_REG, DDRC_CTL_DDR3_094_VAL_CFG1},\
+{DDRC_CTL_95_REG, DDRC_CTL_DDR3_095_VAL_CFG1},\
+{DDRC_CTL_96_REG, DDRC_CTL_DDR3_096_VAL_CFG1},\
+{DDRC_CTL_97_REG, DDRC_CTL_DDR3_097_VAL_CFG1},\
+{DDRC_CTL_98_REG, DDRC_CTL_DDR3_098_VAL_CFG1},\
+{DDRC_CTL_99_REG, DDRC_CTL_DDR3_099_VAL_CFG1},\
+{DDRC_CTL_100_REG, DDRC_CTL_DDR3_100_VAL_CFG1},\
+{DDRC_CTL_102_REG, DDRC_CTL_DDR3_102_VAL_CFG1},\
+{DDRC_CTL_103_REG, DDRC_CTL_DDR3_103_VAL_CFG1},\
+{DDRC_CTL_104_REG, DDRC_CTL_DDR3_104_VAL_CFG1},\
+{DDRC_CTL_105_REG, DDRC_CTL_DDR3_105_VAL_CFG1},\
+{DDRC_CTL_106_REG, DDRC_CTL_DDR3_106_VAL_CFG1},\
+{DDRC_CTL_107_REG, DDRC_CTL_DDR3_107_VAL_CFG1},\
+{DDRC_CTL_108_REG, DDRC_CTL_DDR3_108_VAL_CFG1},\
+{DDRC_CTL_109_REG, DDRC_CTL_DDR3_109_VAL_CFG1},\
+{DDRC_CTL_126_REG, DDRC_CTL_DDR3_126_VAL_CFG1}
+
+#define DDR_PHY_CFG_400 \
+{DDR_PHY_CTL_00_REG, DDR3_PHY_CTL_00_VAL_CFG1},\
+{DDR_PHY_CTL_01_REG, DDR3_PHY_CTL_01_VAL_CFG1},\
+{DDR_PHY_CTL_01_REG, DDR3_PHY_CTL_02_VAL_CFG1},\
+{DDR_PHY_CTL_03_REG, DDR3_PHY_CTL_03_VAL_CFG1},\
+{DDR_PHY_CTL_04_REG, DDR3_PHY_CTL_04_VAL_CFG1},\
+{DDR_PHY_CTL_05_REG, DDR3_PHY_CTL_05_VAL_CFG1},\
+{DDR_PHY_CTL_06_REG, DDR3_PHY_CTL_06_VAL_CFG1},\
+{DDR_PHY_CTL_07_REG, DDR3_PHY_CTL_07_VAL_CFG1}
+
+/*****************************/
+
+/* DDR3 Controller @533MHz */
+#define DDRC_CTL_DDR3_000_VAL_CFG2  0x20410600LL
+//
+#define DDRC_CTL_DDR3_002_VAL_CFG2  0x00000006LL
+#define DDRC_CTL_DDR3_003_VAL_CFG2  0x0001A07CLL
+#define DDRC_CTL_DDR3_004_VAL_CFG2  0x00041127LL
+#define DDRC_CTL_DDR3_005_VAL_CFG2  0x04060E00LL
+#define DDRC_CTL_DDR3_006_VAL_CFG2  0x141C0604LL
+#define DDRC_CTL_DDR3_007_VAL_CFG2  0x08040804LL
+#define DDRC_CTL_DDR3_008_VAL_CFG2  0x0092190CLL
+#define DDRC_CTL_DDR3_009_VAL_CFG2  0x00000504LL
+#define DDRC_CTL_DDR3_010_VAL_CFG2  0x08080101LL
+#define DDRC_CTL_DDR3_011_VAL_CFG2  0x00020010LL
+#define DDRC_CTL_DDR3_012_VAL_CFG2  0x00011B03LL
+#define DDRC_CTL_DDR3_013_VAL_CFG2  0x00000009LL
+#define DDRC_CTL_DDR3_014_VAL_CFG2  0x00560100LL
+#define DDRC_CTL_DDR3_015_VAL_CFG2  0x00001034LL
+#define DDRC_CTL_DDR3_016_VAL_CFG2  0x000D0004LL
+#define DDRC_CTL_DDR3_017_VAL_CFG2  0x00060002LL
+#define DDRC_CTL_DDR3_018_VAL_CFG2  0x005B0200LL
+#define DDRC_CTL_DDR3_019_VAL_CFG2  0x00000000LL
+#define DDRC_CTL_DDR3_020_VAL_CFG2  0x00060600LL
+#define DDRC_CTL_DDR3_021_VAL_CFG2  0x00000000LL
+#define DDRC_CTL_DDR3_022_VAL_CFG2  0x00000000LL
+#define DDRC_CTL_DDR3_023_VAL_CFG2  0x00000000LL
+#define DDRC_CTL_DDR3_024_VAL_CFG2  0x00000000LL
+#define DDRC_CTL_DDR3_025_VAL_CFG2  0x00000000LL
+#define DDRC_CTL_DDR3_026_VAL_CFG2  0x00000000LL
+#define DDRC_CTL_DDR3_027_VAL_CFG2  0x00083000LL
+#define DDRC_CTL_DDR3_028_VAL_CFG2  0x00080006LL
+#define DDRC_CTL_DDR3_029_VAL_CFG2  0x00000000LL
+#define DDRC_CTL_DDR3_030_VAL_CFG2  0x00060830LL
+#define DDRC_CTL_DDR3_031_VAL_CFG2  0x00000008LL
+#define DDRC_CTL_DDR3_032_VAL_CFG2  0x00020000LL
+#define DDRC_CTL_DDR3_033_VAL_CFG2  0x00000000LL
+//
+//
+//
+//
+//
+//
+//
+//
+//
+#define DDRC_CTL_DDR3_043_VAL_CFG2  0x01400200LL
+#define DDRC_CTL_DDR3_044_VAL_CFG2  0x02000040LL
+#define DDRC_CTL_DDR3_045_VAL_CFG2  0x01010080LL
+#define DDRC_CTL_DDR3_046_VAL_CFG2  0xFF0A0102LL
+#define DDRC_CTL_DDR3_047_VAL_CFG2  0x010101FFLL
+#define DDRC_CTL_DDR3_048_VAL_CFG2  0x00010001LL
+#define DDRC_CTL_DDR3_049_VAL_CFG2  0x000C0100LL
+#define DDRC_CTL_DDR3_050_VAL_CFG2  0x00010002LL
+//
+#define DDRC_CTL_DDR3_052_VAL_CFG2  0x00000000LL
+#define DDRC_CTL_DDR3_053_VAL_CFG2  0x007FFFFFLL
+//
+//
+//
+//
+//
+#define DDRC_CTL_DDR3_059_VAL_CFG2  0x01000000LL
+#define DDRC_CTL_DDR3_060_VAL_CFG2  0x00020100LL
+#define DDRC_CTL_DDR3_061_VAL_CFG2  0x02010202LL
+#define DDRC_CTL_DDR3_062_VAL_CFG2  0x02000101LL
+#define DDRC_CTL_DDR3_063_VAL_CFG2  0x00000000LL
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+#define DDRC_CTL_DDR3_091_VAL_CFG2  0xFFFF0000LL
+#define DDRC_CTL_DDR3_092_VAL_CFG2  0x00000202LL
+#define DDRC_CTL_DDR3_093_VAL_CFG2  0x0101FFFFLL
+#define DDRC_CTL_DDR3_094_VAL_CFG2  0x03FFFF00LL
+#define DDRC_CTL_DDR3_095_VAL_CFG2  0xFFFF0003LL
+#define DDRC_CTL_DDR3_096_VAL_CFG2  0x00000303LL
+#define DDRC_CTL_DDR3_097_VAL_CFG2  0x01000400LL
+#define DDRC_CTL_DDR3_098_VAL_CFG2  0x00016400LL
+#define DDRC_CTL_DDR3_099_VAL_CFG2  0x00000100LL
+#define DDRC_CTL_DDR3_100_VAL_CFG2  0x00000001LL
+//
+#define DDRC_CTL_DDR3_102_VAL_CFG2  0x00000800LL
+#define DDRC_CTL_DDR3_103_VAL_CFG2  0x00103300LL
+#define DDRC_CTL_DDR3_104_VAL_CFG2  0x02000200LL
+#define DDRC_CTL_DDR3_105_VAL_CFG2  0x02000200LL
+#define DDRC_CTL_DDR3_106_VAL_CFG2  0x00001033LL
+#define DDRC_CTL_DDR3_107_VAL_CFG2  0x000050FFLL
+#define DDRC_CTL_DDR3_108_VAL_CFG2  0x0002060CLL
+#define DDRC_CTL_DDR3_109_VAL_CFG2  0x00000003LL
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+#define DDRC_CTL_DDR3_126_VAL_CFG2  0x00000000LL
+
+
+/* DDR3 PHY @533 */
+#define DDR3_PHY_CTL_00_VAL_CFG2  0x000F1023LL
+#define DDR3_PHY_CTL_01_VAL_CFG2  0x18201010LL
+#define DDR3_PHY_CTL_02_VAL_CFG2  0x00000006LL
+#define DDR3_PHY_CTL_03_VAL_CFG2  0x09090909LL
+#define DDR3_PHY_CTL_04_VAL_CFG2  0x00000009LL
+#define DDR3_PHY_CTL_05_VAL_CFG2  0x00000000LL
+#define DDR3_PHY_CTL_06_VAL_CFG2  0x04300623LL
+#define DDR3_PHY_CTL_07_VAL_CFG2  0x00000000LL
+
+
+
+#define DDRC_DDR3_CFG_533 \
+{DDRC_CTL_00_REG, DDRC_CTL_DDR3_000_VAL_CFG2},\
+{DDRC_CTL_02_REG, DDRC_CTL_DDR3_002_VAL_CFG2},\
+{DDRC_CTL_03_REG, DDRC_CTL_DDR3_003_VAL_CFG2},\
+{DDRC_CTL_04_REG, DDRC_CTL_DDR3_004_VAL_CFG2},\
+{DDRC_CTL_05_REG, DDRC_CTL_DDR3_005_VAL_CFG2},\
+{DDRC_CTL_06_REG, DDRC_CTL_DDR3_006_VAL_CFG2},\
+{DDRC_CTL_07_REG, DDRC_CTL_DDR3_007_VAL_CFG2},\
+{DDRC_CTL_08_REG, DDRC_CTL_DDR3_008_VAL_CFG2},\
+{DDRC_CTL_09_REG, DDRC_CTL_DDR3_009_VAL_CFG2},\
+{DDRC_CTL_10_REG, DDRC_CTL_DDR3_010_VAL_CFG2},\
+{DDRC_CTL_11_REG, DDRC_CTL_DDR3_011_VAL_CFG2},\
+{DDRC_CTL_12_REG, DDRC_CTL_DDR3_012_VAL_CFG2},\
+{DDRC_CTL_13_REG, DDRC_CTL_DDR3_013_VAL_CFG2},\
+{DDRC_CTL_14_REG, DDRC_CTL_DDR3_014_VAL_CFG2},\
+{DDRC_CTL_15_REG, DDRC_CTL_DDR3_015_VAL_CFG2},\
+{DDRC_CTL_16_REG, DDRC_CTL_DDR3_016_VAL_CFG2},\
+{DDRC_CTL_17_REG, DDRC_CTL_DDR3_017_VAL_CFG2},\
+{DDRC_CTL_18_REG, DDRC_CTL_DDR3_018_VAL_CFG2},\
+{DDRC_CTL_19_REG, DDRC_CTL_DDR3_019_VAL_CFG2},\
+{DDRC_CTL_20_REG, DDRC_CTL_DDR3_020_VAL_CFG2},\
+{DDRC_CTL_21_REG, DDRC_CTL_DDR3_021_VAL_CFG2},\
+{DDRC_CTL_22_REG, DDRC_CTL_DDR3_022_VAL_CFG2},\
+{DDRC_CTL_23_REG, DDRC_CTL_DDR3_023_VAL_CFG2},\
+{DDRC_CTL_24_REG, DDRC_CTL_DDR3_024_VAL_CFG2},\
+{DDRC_CTL_25_REG, DDRC_CTL_DDR3_025_VAL_CFG2},\
+{DDRC_CTL_26_REG, DDRC_CTL_DDR3_026_VAL_CFG2},\
+{DDRC_CTL_27_REG, DDRC_CTL_DDR3_027_VAL_CFG2},\
+{DDRC_CTL_28_REG, DDRC_CTL_DDR3_028_VAL_CFG2},\
+{DDRC_CTL_29_REG, DDRC_CTL_DDR3_029_VAL_CFG2},\
+{DDRC_CTL_30_REG, DDRC_CTL_DDR3_030_VAL_CFG2},\
+{DDRC_CTL_31_REG, DDRC_CTL_DDR3_031_VAL_CFG2},\
+{DDRC_CTL_32_REG, DDRC_CTL_DDR3_032_VAL_CFG2},\
+{DDRC_CTL_33_REG, DDRC_CTL_DDR3_033_VAL_CFG2},\
+{DDRC_CTL_43_REG, DDRC_CTL_DDR3_043_VAL_CFG2},\
+{DDRC_CTL_44_REG, DDRC_CTL_DDR3_044_VAL_CFG2},\
+{DDRC_CTL_45_REG, DDRC_CTL_DDR3_045_VAL_CFG2},\
+{DDRC_CTL_46_REG, DDRC_CTL_DDR3_046_VAL_CFG2},\
+{DDRC_CTL_47_REG, DDRC_CTL_DDR3_047_VAL_CFG2},\
+{DDRC_CTL_48_REG, DDRC_CTL_DDR3_048_VAL_CFG2},\
+{DDRC_CTL_49_REG, DDRC_CTL_DDR3_049_VAL_CFG2},\
+{DDRC_CTL_50_REG, DDRC_CTL_DDR3_050_VAL_CFG2},\
+{DDRC_CTL_52_REG, DDRC_CTL_DDR3_052_VAL_CFG2},\
+{DDRC_CTL_53_REG, DDRC_CTL_DDR3_053_VAL_CFG2},\
+{DDRC_CTL_59_REG, DDRC_CTL_DDR3_059_VAL_CFG2},\
+{DDRC_CTL_60_REG, DDRC_CTL_DDR3_060_VAL_CFG2},\
+{DDRC_CTL_61_REG, DDRC_CTL_DDR3_061_VAL_CFG2},\
+{DDRC_CTL_62_REG, DDRC_CTL_DDR3_062_VAL_CFG2},\
+{DDRC_CTL_63_REG, DDRC_CTL_DDR3_063_VAL_CFG2},\
+{DDRC_CTL_91_REG, DDRC_CTL_DDR3_091_VAL_CFG2},\
+{DDRC_CTL_92_REG, DDRC_CTL_DDR3_092_VAL_CFG2},\
+{DDRC_CTL_93_REG, DDRC_CTL_DDR3_093_VAL_CFG2},\
+{DDRC_CTL_94_REG, DDRC_CTL_DDR3_094_VAL_CFG2},\
+{DDRC_CTL_95_REG, DDRC_CTL_DDR3_095_VAL_CFG2},\
+{DDRC_CTL_96_REG, DDRC_CTL_DDR3_096_VAL_CFG2},\
+{DDRC_CTL_97_REG, DDRC_CTL_DDR3_097_VAL_CFG2},\
+{DDRC_CTL_98_REG, DDRC_CTL_DDR3_098_VAL_CFG2},\
+{DDRC_CTL_99_REG, DDRC_CTL_DDR3_099_VAL_CFG2},\
+{DDRC_CTL_100_REG, DDRC_CTL_DDR3_100_VAL_CFG2},\
+{DDRC_CTL_102_REG, DDRC_CTL_DDR3_102_VAL_CFG2},\
+{DDRC_CTL_103_REG, DDRC_CTL_DDR3_103_VAL_CFG2},\
+{DDRC_CTL_104_REG, DDRC_CTL_DDR3_104_VAL_CFG2},\
+{DDRC_CTL_105_REG, DDRC_CTL_DDR3_105_VAL_CFG2},\
+{DDRC_CTL_106_REG, DDRC_CTL_DDR3_106_VAL_CFG2},\
+{DDRC_CTL_107_REG, DDRC_CTL_DDR3_107_VAL_CFG2},\
+{DDRC_CTL_108_REG, DDRC_CTL_DDR3_108_VAL_CFG2},\
+{DDRC_CTL_109_REG, DDRC_CTL_DDR3_109_VAL_CFG2},\
+{DDRC_CTL_126_REG, DDRC_CTL_DDR3_126_VAL_CFG2}
+
+#define DDR_PHY_CFG_533 \
+{DDR_PHY_CTL_00_REG, DDR3_PHY_CTL_00_VAL_CFG2},\
+{DDR_PHY_CTL_01_REG, DDR3_PHY_CTL_01_VAL_CFG2},\
+{DDR_PHY_CTL_02_REG, DDR3_PHY_CTL_02_VAL_CFG2},\
+{DDR_PHY_CTL_03_REG, DDR3_PHY_CTL_03_VAL_CFG2},\
+{DDR_PHY_CTL_04_REG, DDR3_PHY_CTL_04_VAL_CFG2},\
+{DDR_PHY_CTL_05_REG, DDR3_PHY_CTL_05_VAL_CFG2},\
+{DDR_PHY_CTL_06_REG, DDR3_PHY_CTL_06_VAL_CFG2},\
+{DDR_PHY_CTL_07_REG, DDR3_PHY_CTL_07_VAL_CFG2}, \
+
+//#define DDRC_CFG	DDRC_DDR3_CFG_533
+//#define DDR_PHY_CFG	DDR_PHY_CFG_533
+//For Bringup
+#define DDRC_CFG	DDRC_DDR3_CFG_533
+#define DDR_PHY_CFG	DDR_PHY_CFG_533
+
+struct ddr_reg_val {
+        u32 reg;
+        u32 val;
+};
+
+#define MC_START	0x1
+#define MC_INIT_STAT_MASK	0x200
+
+#define CTRL_RESYNC_EN  (1 << 20)
+#define CTRL_RESYNC_PLS (1 << 21)
+

include/asm-arm/arch-comcerto/emac.h

diff --git a/include/asm-arm/arch-comcerto/emac.h b/include/asm-arm/arch-comcerto/emac.h
new file mode 100644
index 0000000..16b7f05
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/emac.h
@@ -0,0 +1,306 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#ifndef _EMAC_H
+#define _EMAC_H
+
+/********* EMAC registers and masks ******************/
+
+/* Arm side FIFO control registers */
+#define EMAC_ARM_FIFO_CONTROL		0x0000
+#define EMAC_ARM_FIFO_STATUS		0x0004
+#define EMAC_ARM_FIFO_IACK		0x0004
+#define EMAC_ARM_BIST			0x0008
+#define EMAC_ARM_FIFO_TXSIZE		0x0014
+#define EMAC_ARM_FIFO_TXHIGH		0x0018
+#define EMAC_ARM_FIFO_TXLOW		0x001C
+#define EMAC_ARM_FIFO_RXSIZE		0x0024
+#define EMAC_ARM_FIFO_RXHIGH		0x0028
+#define EMAC_ARM_FIFO_RXLOW		0x002C
+#define EMAC_ARM_TXMAIL0		0x0030
+#define EMAC_ARM_TXMAIL1		0x0034
+#define EMAC_ARM_TXMAIL2		0x0038
+#define EMAC_ARM_TXMAIL3		0x003C
+#define EMAC_ARM_RXMAIL0		0x0040
+#define EMAC_ARM_RXMAIL1		0x0044
+#define EMAC_ARM_RXMAIL2		0x0048
+#define EMAC_ARM_RXMAIL3		0x004C
+
+#define EMAC_ARM_FIFO_TXDATABYTE	0x4000
+#define EMAC_ARM_FIFO_RXDATABYTE	0x4000
+#define EMAC_ARM_FIFO_TXDATAHWORD	0x8000
+#define EMAC_ARM_FIFO_RXDATAHWORD	0x8000
+#define EMAC_ARM_FIFO_TXDATAWORD	0xC000
+#define EMAC_ARM_FIFO_RXDATAWORD	0xC000
+
+/* Host side FIFO control registers */
+#define EMAC_HOST_FIFO_CONTROL		0xD000
+#define EMAC_HOST_FIFO_STATUS		0xD004
+#define EMAC_HOST_FIFO_IACK		0xD004
+#define EMAC_HOST_FIFO_TXSIZE		0xD010
+#define EMAC_HOST_FIFO_TXHIGH		0xD014
+#define EMAC_HOST_FIFO_TXLOW		0xD018
+#define EMAC_HOST_FIFO_RXSIZE		0xD020
+#define EMAC_HOST_FIFO_RXHIGH		0xD024
+#define EMAC_HOST_FIFO_RXLOW		0xD028
+#define EMAC_HOST_TXMAIL0		0xD030
+#define EMAC_HOST_TXMAIL1		0xD034
+#define EMAC_HOST_TXMAIL2		0xD038
+#define EMAC_HOST_TXMAIL3		0xD03C
+#define EMAC_HOST_RXMAIL0		0xD040
+#define EMAC_HOST_RXMAIL1		0xD044
+#define EMAC_HOST_RXMAIL2		0xD048
+#define EMAC_HOST_RXMAIL3		0xD04C
+
+#define EMAC_HOST_FIFO_TXDATA		0xD100
+#define EMAC_HOST_FIFO_RXDATA		0xD100
+
+/* EMAC Interface */
+#define EMAC_OCR			0xE000
+#define EMAC_ICR			0xE004
+#define EMAC_IF_INT			0xE008
+#define EMAC_OUTPUT			0xE00C
+#define EMAC_RX_STAT_FIFO_DEPTH		0xE010
+#define EMAC_RX_STAT_FIFO_DATA		0xE020
+
+/* EMAC ARC Table */
+#define EMAC_ARC_TABLE			0xE200
+
+
+/* EMAC IP Flow Control CSR */
+#define EMAC_FLOWCTRL_BASE		0xE330
+
+#define EMAC_FLOWCTRL_PAUSECNT		(EMAC_FLOWCTRL_BASE + 0x00)
+#define EMAC_FLOWCTRL_REMPAUSECNT	(EMAC_FLOWCTRL_BASE + 0x04)
+
+/* EMAC IP Control CSR */
+#define EMAC_CTRL_BASE			0xE340
+#define EMAC_MACCTRL			(EMAC_CTRL_BASE + 0x00)
+#define EMAC_ARCCTRL			(EMAC_CTRL_BASE + 0x04)
+#define EMAC_TXCTRL			(EMAC_CTRL_BASE + 0x08)
+#define EMAC_TXSTATUS			(EMAC_CTRL_BASE + 0x0C)
+#define EMAC_RXCTRL			(EMAC_CTRL_BASE + 0x10) 
+#define EMAC_RXSTATUS			(EMAC_CTRL_BASE + 0x14)
+
+#define EMAC_MDDATA			(EMAC_CTRL_BASE + 0x18)
+#define EMAC_MDCA			(EMAC_CTRL_BASE + 0x1C)
+
+#define EMAC_ARCENA			(EMAC_CTRL_BASE + 0x28)
+
+#define EMAC_PROMCTL			(EMAC_CTRL_BASE + 0x2C)
+#define EMAC_PROMDATA			(EMAC_CTRL_BASE + 0x30)
+
+#define EMAC_MISSCNT			(EMAC_CTRL_BASE + 0x3C)
+
+#define EMAC_RMON_BASE			0xE400
+#define EMAC_CNTDATA			(EMAC_RMON_BASE + 0x00)
+#define EMAC_CNTACC			(EMAC_RMON_BASE + 0x04)
+#define EMAC_TXRMONIE			(EMAC_RMON_BASE + 0x08)
+#define EMAC_RXRMONIE			(EMAC_RMON_BASE + 0x0C)
+
+
+#define MAX_ARC_ENTRIES 					21
+
+/* ARM fifo control bits */
+#define EMAC_ARM_RXDREQWE				0x0004
+#define EMAC_ARM_TXDREQRE					0x0008
+#define EMAC_ARM_TXCMPLTIE				0x0020
+#define EMAC_ARM_TXFIE						0x0040
+#define EMAC_ARM_TXTHIE					0x0080
+#define EMAC_ARM_RXEIE						0x0100
+#define EMAC_ARM_RXTHIE					0x0200
+#define EMAC_ARM_TXM3IE					0x0400
+#define EMAC_ARM_RXM3IE					0x0800
+#define EMAC_ARM_TXFF_RES					0x1000
+#define EMAC_ARM_RXFF_RES					0x2000
+
+
+/* Host fifo control bits */
+#define EMAC_HOST_TXFF_EN					0x0001
+#define EMAC_HOST_HBTXRQ_EN				0x0002
+#define EMAC_HOST_RXFF_EN					0x0008
+#define EMAC_HOST_HBRXRQ_EN				0x0010
+#define EMAC_HOST_TXCP_INH				0x0020
+#define EMAC_HOST_TXEIE					0x0100
+#define EMAC_HOST_TXTHIE					0x0200
+#define EMAC_HOST_TXM3IE					0x0400
+#define EMAC_HOST_RXCMPLTIE				0x0800
+#define EMAC_HOST_RXFIE					0x1000
+#define EMAC_HOST_RXTHIE					0x2000
+#define EMAC_HOST_RXM3IE					0x4000
+#define EMAC_HOST_TRGABORTIE				0x8000
+
+/* Memory BIST register masks */
+#define EMAC_RXBIST_RESET					0x00000001
+#define EMAC_RXBIST_TEST					0x00000002
+#define EMAC_RXBIST_DBG					0x00000004
+#define EMAC_RXBIST_RESUME_RTN			0x00000008
+#define EMAC_RXBIST_DONE					0x00000010
+#define EMAC_RXBIST_FAIL					0x00000020
+#define EMAC_RXBIST_START_RTN				0x00000040 
+#define EMAC_TXBIST_RESET					0x00000100
+#define EMAC_TXBIST_TEST					0x00000200
+#define EMAC_TXBIST_DBG					0x00000400
+#define EMAC_TXBIST_RESUME_RTN			0x00000800
+#define EMAC_TXBIST_DONE					0x00001000
+#define EMAC_TXBIST_FAIL					0x00002000
+#define EMAC_TXBIST_START_RTN				0x00004000
+
+/* EMAC Operation Controling Register masks*/
+#define EMAC_OCR_ROMCKSE				0x00000003
+#define EMAC_OCR_MDCCKSE				0x0000000C
+#define EMAC_OCR_MIIFDL				0x00000010
+#define EMAC_OCR_MII100L				0x00000020
+#define EMAC_OCR_MIILINKL				0x00000040
+#define EMAC_OCR_MIICONN				0x00000080
+#define EMAC_OCR_TESTMODE				0x00000100
+#define EMAC_OCR_CAMHITL				0x00000200
+#define EMAC_OCR_EMACLPBK				0x00000400
+#define EMAC_OCR_TOSS_INHIBIT			0x00000800
+#define EMAC_OCR_OB_SRESET				0x00001000
+#define EMAC_OCR_IB_SRESET				0x00002000
+#define EMAC_OCR_IP_HRESET				0x00004000
+#define EMAC_OCR_RXPCKSIZE				0x00FF8000
+#define EMAC_OCR_RES24					0x01000000
+#if defined(CONFIG_COMCERTO_515) || defined(CONFIG_COMCERTO_800)
+#define EMAC_OCR_SEL_MII_MODE				0x02000000
+#define EMAC_OCR_SW_SMII_OVRD				0x04000000
+#define EMAC_OCR_SW_SMII_MODE				0x08000000
+#endif
+#define EMAC_OCR_STSFFREQIE				0x10000000
+#define EMAC_OCR_RXSTATIE				0x20000000
+#define EMAC_OCR_TXSTATIE				0x40000000
+#define EMAC_OCR_MIIRQIE				0x80000000
+
+/* EMAC Input Controlled Register masks */
+#define EMAC_ICR_TXFRMOPT				0x00000007
+#if defined(CONFIG_COMCERTO_515) || defined(CONFIG_COMCERTO_800)
+#define EMAC_ICR_MII100L_POL				0x00000100
+#define EMAC_ICR_MIIFDL_POL				0x00000200
+#define EMAC_ICR_MIILINK_POL				0x00000400
+#define EMAC_ICR_PHYCTRLDIS				0x00008000
+#endif
+
+/* EMAC I/F Interrupt Register Status masks */
+#define EMAC_INPUT_STSFFREQIRQ			0x10000000	// Read Only
+#define EMAC_INPUT_RXSTATIRQ				0x20000000
+#define EMAC_INPUT_TXSTATIRQ				0x40000000
+#define EMAC_INPUT_MIIRQIRQ				0x80000000
+// EMAC I/F Interrupt Acknowledge Register (same as previsous)
+#define EMAC_INPUT_STSFFREQIAK			0x10000000   // Write Only
+#define EMAC_INPUT_RXSTATIAK				0x20000000
+#define EMAC_INPUT_TXSTATIAK				0x40000000
+
+/* EMAC Output Status masks */
+#define EMAC_OUT_REV_ID					0x0000000F
+#define REV_SIM								0x0000000E
+
+#define EMAC_OUT_INTLINK					0x00000010
+#define EMAC_OUT_CAMLOAD					0x00000020
+
+
+/* EMAC RX status FIFO data masks */
+
+#define EMAC_RX_STAT_TYPE					0x18000000
+#define EMAC_RX_STAT_PKTCNT				0x000000FF
+#define EMAC_RX_STAT_IPSTA					0x03FFFFFF
+
+
+
+/* EMAC_MACCTRL  bits */
+#define MAC_HALTREQ		0x0001
+#define MAC_HALTIMM		0x0002
+#define MAC_RESET			0x0004
+#define MAC_FULLDUP		0x0008
+#define MAC_LOOPBACK		0x0010
+
+#define MAC_CONN_MSK		0x0060
+#define MAC_AUTORATE		0x0000
+#define MAC_10MBITS			0x0020
+#define MAC_MIIRATE			0x0040
+
+#define MAC_LOOP10			0x0080
+#define MAC_LNKCHG			0x0100
+#define MAC_RES9			0x0200
+#define MAC_MISSROLL		0x0400
+#define MAC_RES11			0x0800
+#define MAC_RES12			0x1000
+#define MAC_ENMISSROLL		0x2000
+#define MAC_RES14			0x4000
+#define MAC_LINK10			0x8000
+
+/* EMAC_ARCCTRL bits */
+
+#define ARC_STATIONACC		0x0001
+#define ARC_GROUPACC		0x0002
+#define ARC_BROADACC		0x0004
+#define ARC_NEGARC			0x0008
+#define ARC_COMPENA		0x0010
+#define ARC_RESERVED		0xFFE0
+
+/* EMAC_TXCTRL bits */
+#define TX_EN				0x0001
+#define TX_HALT				0x0002
+#define TX_NOPAD			0x0004
+#define TX_NOCRC			0x0008
+#define TX_FBACK			0x0010
+#define TX_NOEXDEF			0x0020
+#define TX_SDPAUSE			0x0040
+#define TX_MII10				0x0080
+
+#define TX_EN_UNDER		0x0100
+#define TX_EN_EXDEF			0x0200
+#define TX_EN_LCARR			0x0400
+#define TX_EN_EXCOLL		0x0800
+#define TX_EN_LATECOLL		0x1000
+#define TX_EN_TXPAR			0x2000
+#define TX_EN_COMP			0x4000
+
+/* EMAC_RXCTRL bits */
+#define RX_EN				0x0001
+#define RX_HALT				0x0002
+#define RX_LONGEN			0x0004
+#define RX_SHORTEN			0x0008
+#define RX_STRIPCRC			0x0010
+#define RX_PASSCTL			0x0020
+#define RX_IGNORECRC		0x0040
+#define RX_RES7				0x0080 // reserved
+
+#define RX_EN_ALIGN			0x0100
+#define RX_EN_CRCERR		0x0200
+#define RX_EN_OVERFLOW		0x0400
+#define RX_EN_LONGERR		0x0800
+#define RX_RES12			0x1000 // reserved
+#define RX_EN_RXPAR			0x2000
+#define RX_EN_GOOD			0x4000
+#define RX_RES15			0x8000 // reserved
+
+
+#define EMAC_MDIO_WRITE					0x400
+#define EMAC_MDIO_BUSY					0x800
+#define EMAC_MDIO_PRESUP				0x1000
+#define EMAC_MDIO_OPERATION_TIMEOUT		10
+
+
+#define EMAC_MII_MODE		0
+#define EMAC_FORCE_RMII_MODE	1
+#define EMAC_FORCE_SMII_MODE	2
+#define	EMAC_RMII_SMII_MODE	3
+
+#endif /* _EMAC_H */

include/asm-arm/arch-comcerto/exp-bus_c2000.h

diff --git a/include/asm-arm/arch-comcerto/exp-bus_c2000.h b/include/asm-arm/arch-comcerto/exp-bus_c2000.h
new file mode 100644
index 0000000..1d034ce
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/exp-bus_c2000.h
@@ -0,0 +1,102 @@
+/*
+ *  arch/arm/mach-comcerto/include/mach/exp-bus.h
+ *
+ *  Copyright (C) 2011 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __COMCERTO_EXP_BUS_H__
+#define __COMCERTO_EXP_BUS_H__
+
+/*
+ *  Expansion Bus control registers
+ */
+#define EXP_SWRST_REG            (COMCERTO_EXP_CONF_BASE + 0x00)
+#define EXP_CSEN_REG             (COMCERTO_EXP_CONF_BASE + 0x04)
+#define EXP_CS0_BASE_REG         (COMCERTO_EXP_CONF_BASE + 0x08)
+#define EXP_CS1_BASE_REG         (COMCERTO_EXP_CONF_BASE + 0x0C)
+#define EXP_CS2_BASE_REG         (COMCERTO_EXP_CONF_BASE + 0x10)
+#define EXP_CS3_BASE_REG         (COMCERTO_EXP_CONF_BASE + 0x14)
+#define EXP_CS4_BASE_REG         (COMCERTO_EXP_CONF_BASE + 0x18)
+#define EXP_CS0_SEG_REG          (COMCERTO_EXP_CONF_BASE + 0x1C)
+#define EXP_CS1_SEG_REG          (COMCERTO_EXP_CONF_BASE + 0x20)
+#define EXP_CS2_SEG_REG          (COMCERTO_EXP_CONF_BASE + 0x24)
+#define EXP_CS3_SEG_REG          (COMCERTO_EXP_CONF_BASE + 0x28)
+#define EXP_CS4_SEG_REG          (COMCERTO_EXP_CONF_BASE + 0x2C)
+#define EXP_CS0_CFG_REG		 (COMCERTO_EXP_CONF_BASE + 0x30)
+#define EXP_CS1_CFG_REG		 (COMCERTO_EXP_CONF_BASE + 0x34)
+#define EXP_CS2_CFG_REG		 (COMCERTO_EXP_CONF_BASE + 0x38)
+#define EXP_CS3_CFG_REG		 (COMCERTO_EXP_CONF_BASE + 0x3C)
+#define EXP_CS4_CFG_REG		 (COMCERTO_EXP_CONF_BASE + 0x40)
+#define EXP_CS0_TMG1_REG         (COMCERTO_EXP_CONF_BASE + 0x44)
+#define EXP_CS1_TMG1_REG         (COMCERTO_EXP_CONF_BASE + 0x48)
+#define EXP_CS2_TMG1_REG         (COMCERTO_EXP_CONF_BASE + 0x4C)
+#define EXP_CS3_TMG1_REG         (COMCERTO_EXP_CONF_BASE + 0x50)
+#define EXP_CS4_TMG1_REG         (COMCERTO_EXP_CONF_BASE + 0x54)
+#define EXP_CS0_TMG2_REG         (COMCERTO_EXP_CONF_BASE + 0x58)
+#define EXP_CS1_TMG2_REG         (COMCERTO_EXP_CONF_BASE + 0x5C)
+#define EXP_CS2_TMG2_REG         (COMCERTO_EXP_CONF_BASE + 0x60)
+#define EXP_CS3_TMG2_REG         (COMCERTO_EXP_CONF_BASE + 0x64)
+#define EXP_CS4_TMG2_REG         (COMCERTO_EXP_CONF_BASE + 0x68)
+#define EXP_CS0_TMG3_REG         (COMCERTO_EXP_CONF_BASE + 0x6C)
+#define EXP_CS1_TMG3_REG         (COMCERTO_EXP_CONF_BASE + 0x70)
+#define EXP_CS2_TMG3_REG         (COMCERTO_EXP_CONF_BASE + 0x74)
+#define EXP_CS3_TMG3_REG         (COMCERTO_EXP_CONF_BASE + 0x78)
+#define EXP_CS4_TMG3_REG         (COMCERTO_EXP_CONF_BASE + 0x7C)
+#define EXP_CLOCK_DIV_REG        (COMCERTO_EXP_CONF_BASE + 0x80)
+
+#define EXP_MFSM_REG             (COMCERTO_EXP_CONF_BASE + 0x100)
+#define EXP_CSFSM_REG            (COMCERTO_EXP_CONF_BASE + 0x104)
+#define EXP_WRFSM_REG            (COMCERTO_EXP_CONF_BASE + 0x108)
+#define EXP_RDFSM_REG            (COMCERTO_EXP_CONF_BASE + 0x10C)
+
+#define EXP_SW_RST	 0x00000001
+#define EXP_CLK_EN       0x00000001
+#define EXP_CSBOOT_EN    0x00000002
+#define EXP_CS0_EN       0x00000002
+#define EXP_CS1_EN       0x00000004
+#define EXP_CS2_EN       0x00000008
+#define EXP_CS3_EN       0x00000010
+#define EXP_CS4_EN       0x00000020
+#define EXP_MEM_BUS_8    0x00000000
+#define EXP_MEM_BUS_16   0x00000002
+#define EXP_CS_HIGH      0x00000008
+#define EXP_WE_HIGH      0x00000010
+#define EXP_RE_HIGH      0x00000020
+#define EXP_ALE_MODE     0x00000040
+#define EXP_STRB_MODE    0x00000080
+#define EXP_DM_MODE      0x00000100
+#define EXP_NAND_MODE    0x00000200
+#define EXP_RDY_EN       0x00000400
+#define EXP_RDY_EDGE     0x00000800
+
+#define COMCERTO_NAND_RDY	GPIO_29
+#define COMCERTO_NAND_CE	GPIO_28
+
+#define BIT_9_MSK	0x00000200
+#define BIT_10_MSK	0x00000400
+
+#if defined(CONFIG_MACH_COMCERTO_C2K_ASIC) && defined(CONFIG_NAND_TYPE_SLC)
+//SLC NAND on ASIC is 16-bit, and bit[0] of Exp bus is used for data mask
+//hence the ALE and CLE signal is shifted by 1 bit
+#define COMCERTO_NAND_ALE	(BIT_9_MSK << 1)
+#define COMCERTO_NAND_CLE	(BIT_10_MSK << 1)
+#else
+#define COMCERTO_NAND_ALE	BIT_9_MSK
+#define COMCERTO_NAND_CLE	BIT_10_MSK
+#endif
+
+#endif	/* __COMCERTO_EXP_BUS_H__ */

include/asm-arm/arch-comcerto/gpio_c2000.h

diff --git a/include/asm-arm/arch-comcerto/gpio_c2000.h b/include/asm-arm/arch-comcerto/gpio_c2000.h
new file mode 100644
index 0000000..2911e51
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/gpio_c2000.h
@@ -0,0 +1,95 @@
+/*
+ *  Copyright (C) 2008 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __GPIO_C2000_H__
+#define __GPIO_C2000_H__
+
+/***** GPIO  *****/
+#define COMCERTO_GPIO_OUTPUT_REG			(COMCERTO_APB_GPIO_BASE + 0x00)
+#define COMCERTO_GPIO_OE_REG				(COMCERTO_APB_GPIO_BASE + 0x04)
+#define COMCERTO_GPIO_INT_CFG_REG			(COMCERTO_APB_GPIO_BASE + 0x08)
+#define COMCERTO_GPIO_ARM_UNALIGNED_LOGIC_ENABLE	(COMCERTO_APB_GPIO_BASE + 0x0C)
+#define COMCERTO_GPIO_INPUT_REG				(COMCERTO_APB_GPIO_BASE + 0x10)
+#define COMCERTO_GPIO_APB_WS				(COMCERTO_APB_GPIO_BASE + 0x14)
+#define COMCERTO_GPIO_SYSTEM_CONFIG			(COMCERTO_APB_GPIO_BASE + 0x1C)
+#define COMCERTO_GPIO_MBIST				(COMCERTO_APB_GPIO_BASE + 0x20)
+#define COMCERTO_GPIO_TDM_MUX				(COMCERTO_APB_GPIO_BASE + 0x28)
+#define COMCERTO_GPIO_ARM_ID				(COMCERTO_APB_GPIO_BASE + 0x30)
+#define COMCERTO_GPIO_PAD_CTRL				(COMCERTO_APB_GPIO_BASE + 0x34)
+#define COMCERTO_GPIO_BOOTSTRAP_STATUS			(COMCERTO_APB_GPIO_BASE + 0x40)
+#define COMCERTO_GPIO_BOOTSTRAP_OVERRIDE		(COMCERTO_APB_GPIO_BASE + 0x44)
+#define COMCERTO_GPIO_USB_PHY_BIST_STATUS_REG		(COMCERTO_APB_GPIO_BASE + 0x48)
+#define COMCERTO_GPIO_GENERAL_CONTROL_REG		(COMCERTO_APB_GPIO_BASE + 0x4C)
+#define COMCERTO_GPIO_DEVICE_ID_REG			(COMCERTO_APB_GPIO_BASE + 0x50)
+#define COMCERTO_GPIO_ARM_MEMORY_SENSE_AMP		(COMCERTO_APB_GPIO_BASE + 0x54)
+#define COMCERTO_GPIO_PIN_SELECT_REG			(COMCERTO_APB_GPIO_BASE + 0x58)
+#define COMCERTO_GPIO_MISC_PIN_SELECT_REG		(COMCERTO_APB_GPIO_BASE + 0x60)
+#define COMCERTO_GPIO_PAD_CONFIG0                       (COMCERTO_APB_GPIO_BASE + 0x100)
+#define COMCERTO_GPIO_PAD_CONFIG3                       (COMCERTO_APB_GPIO_BASE + 0x10C)
+#define COMCERTO_GPIO_PAD_CONFIG4                       (COMCERTO_APB_GPIO_BASE + 0x110)
+#define COMCERTO_GPIO_PAD_CONFIG5                       (COMCERTO_APB_GPIO_BASE + 0x114)
+#define COMCERTO_GPIO_MEM_EMA_CONFIG0                       (COMCERTO_APB_GPIO_BASE + 0x1A0)
+#define COMCERTO_GPIO_MEM_EMA_CONFIG1                       (COMCERTO_APB_GPIO_BASE + 0x1A4)
+
+#define GPIO_0		0x00000001
+#define GPIO_1		0x00000002
+#define GPIO_2		0x00000004
+#define GPIO_3		0x00000008
+#define GPIO_4		0x00000010
+#define GPIO_5		0x00000020
+#define GPIO_6	        0x00000040
+#define GPIO_7		0x00000080
+#define GPIO_8		0x00000100
+#define GPIO_9		0x00000200
+#define GPIO_10		0x00000400
+#define GPIO_11		0x00000800
+#define GPIO_12		0x00001000
+#define GPIO_13		0x00002000
+#define GPIO_14		0x00004000
+#define GPIO_15		0x00008000
+#define GPIO_16		0x00010000
+#define GPIO_17		0x00020000
+#define GPIO_18		0x00040000
+#define GPIO_19		0x00080000
+#define GPIO_20		0x00100000
+#define GPIO_21		0x00200000
+#define GPIO_22		0x00400000
+#define GPIO_23		0x00800000
+#define GPIO_24		0x01000000
+#define GPIO_25		0x02000000
+#define GPIO_26		0x04000000
+#define GPIO_27		0x08000000
+#define GPIO_28		0x10000000
+#define GPIO_29		0x20000000
+#define GPIO_30		0x40000000
+#define GPIO_31		0x80000000
+
+
+
+/* Bootstrap configuration bit definitions */
+#define BOOTSTRAP_SERDES2_CNF_SGMII	(1 << 10)
+#define BOOTSTRAP_SERDES1_CNF_SATA0	(1 << 11)
+
+
+/* GPIO Pin Select Pins */
+#define EXP_NAND_RDY	GPIO_29
+#define EXP_NAND_CS	GPIO_28
+
+#define DISABLE_FABRIC_REMAP 0x10
+
+#endif

include/asm-arm/arch-comcerto/hardware.h

diff --git a/include/asm-arm/arch-comcerto/hardware.h b/include/asm-arm/arch-comcerto/hardware.h
new file mode 100644
index 0000000..3404ef4
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/hardware.h
@@ -0,0 +1,26 @@
+#ifndef __HARDWARE_H__
+#define __HARDWARE_H__
+
+#include <config.h>
+
+#if defined(CONFIG_COMCERTO_1000)
+#include "comcerto_1000.h"
+#elif defined(CONFIG_COMCERTO_100)
+#include "comcerto_100.h"
+#elif defined(CONFIG_COMCERTO_530)
+#include "comcerto_530.h"
+#elif defined(CONFIG_COMCERTO_515)
+#include "comcerto_515.h"
+#elif defined(CONFIG_COMCERTO_800)
+#include "comcerto_800.h"
+#elif defined(CONFIG_COMCERTO_900)
+#include "comcerto_900.h"
+#elif defined(CONFIG_COMCERTO_2000)
+#include "comcerto_2000.h"
+#else
+#error no architecture selected!!!
+#endif
+
+
+#define CSE_BOOT	4
+#endif

include/asm-arm/arch-comcerto/idma.h

diff --git a/include/asm-arm/arch-comcerto/idma.h b/include/asm-arm/arch-comcerto/idma.h
new file mode 100644
index 0000000..b90b9a6
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/idma.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _IDMA_H
+#define _IDMA_H
+
+#define HDMA_SOFT_RESET			(IDMA_BASEADDR + 0x0000)
+
+#define IDMA_EMAC0_BASEADDR		(IDMA_BASEADDR + 0x0100)
+
+#define MMPU_START			(IDMA_BASEADDR + 0x0200)
+#define MMPU_HEAD			(IDMA_BASEADDR + 0x0204)
+#define MMPU_BURST			(IDMA_BASEADDR + 0x0208)
+#define MMPU_SOFT_RESET			(IDMA_BASEADDR + 0x0220)
+
+#define PUMM_START			(IDMA_BASEADDR + 0x0280)
+#define PUMM_HEAD			(IDMA_BASEADDR + 0x0284)
+#define PUMM_BURST			(IDMA_BASEADDR + 0x0288)
+#define PUMM_SOFT_RESET			(IDMA_BASEADDR + 0x02A0)
+
+#define MMFIFO_START			(IDMA_BASEADDR + 0x0300)
+#define MMFIFO_HEAD			(IDMA_BASEADDR + 0x0304)
+#define MMFIFO_BURST			(IDMA_BASEADDR + 0x0308)
+#define MMFIFO_SOFT_RESET		(IDMA_BASEADDR + 0x0320)
+
+#define FIFOMM_START			(IDMA_BASEADDR + 0x0380)
+#define FIFOMM_HEAD			(IDMA_BASEADDR + 0x0384)
+#define FIFOMM_BURST			(IDMA_BASEADDR + 0x0388)
+#define FIFOMM_SOFT_RESET		(IDMA_BASEADDR + 0x03A0)
+
+#define IDMA_EMAC1_BASEADDR		(IDMA_BASEADDR + 0x0700)
+
+/* Memory to EMAC register offsets */
+#define MMEM_START			0x00
+#define MMEM_HEAD			0x04
+#define MMEM_BURST			0x08
+#define MMEM_SOFT_RESET			0x20
+
+
+/* EMAC to Memory register offsets */
+#define EMMM_START			0x80
+#define EMMM_HEAD			0x84
+#define EMMM_BURST			0x88
+#define EMMM_SOFT_RESET			0xA0
+
+
+
+#define	FDESC_ALIGN_BYTES		0x10
+
+//************ IDMA registers and masks *****************
+#define IDMA_FSTATUS_FRAME_DONE_MASK	0x80000000
+#define IDMA_FSTATUS_STATUS_MASK			0x03FFFFFF
+
+#define IDMA_FCONTROL_PHY_NB_MASK		0x00000070
+#define IDMA_FCONTROL_PHY_OFFSET			0x00000004
+
+#define IDMA_FCONTROL_IRQEN				0x00000004
+#define IDMA_FCONTROL_FLAST				0x00000002
+#define IDMA_FCONTROL_FREADY				0x00000001
+
+#define IDMA_BCONTROL_BLAST				0x00010000
+#define IDMA_BCONTROL_BLEN_MASK			0x0000FFFF
+
+#define IDMA_FSTATUS_FDONE				0x80000000
+#define IDMA_FSTATUS_BIT27					0x08000000
+#define IDMA_FSTATUS_FKEEP				0x04000000
+
+
+#define IDMA_START							0x00000001
+#define IDMA_BURST_MASK					0x000000FF
+#define IDMA_PRTY_MASK						0x00000700
+#endif

include/asm-arm/arch-comcerto/linkage_c2000.h

diff --git a/include/asm-arm/arch-comcerto/linkage_c2000.h b/include/asm-arm/arch-comcerto/linkage_c2000.h
new file mode 100644
index 0000000..5a25632
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/linkage_c2000.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#define __ALIGN .align 0
+#define __ALIGN_STR ".align 0"
+
+#define ENDPROC(name) \
+  .type name, %function; \
+  END(name)
+
+#endif

include/asm-arm/arch-comcerto/spi.h

diff --git a/include/asm-arm/arch-comcerto/spi.h b/include/asm-arm/arch-comcerto/spi.h
new file mode 100644
index 0000000..8b01364
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/spi.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2007
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Revision 1.2  2007/04/28 	Iurii.Golovach
+ *  	the SR status register bits were added
+ */
+
+#ifndef _SPI_H
+#define _SPI_H
+
+/* SPI registers */
+#define SPI_CTRLR0	(SPI_BASEADDR + 0x00)
+#define SPI_CTRLR1	(SPI_BASEADDR + 0x04)
+#define SPI_SSIENR	(SPI_BASEADDR + 0x08)
+#define SPI_MWCR	(SPI_BASEADDR + 0x0c)
+#define SPI_SER		(SPI_BASEADDR + 0x10)
+#define SPI_BAUDR	(SPI_BASEADDR + 0x14)
+#define SPI_TXFTLR	(SPI_BASEADDR + 0x18)
+#define SPI_RXFTLR	(SPI_BASEADDR + 0x1c)
+#define SPI_TXFLR	(SPI_BASEADDR + 0x20)
+#define SPI_RXFLR	(SPI_BASEADDR + 0x24)
+#define SPI_SR		(SPI_BASEADDR + 0x28)
+#define SPI_IMR		(SPI_BASEADDR + 0x2c)
+#define SPI_ISR		(SPI_BASEADDR + 0x30)
+#define SPI_RISR	(SPI_BASEADDR + 0x34)
+#define SPI_TXOICR	(SPI_BASEADDR + 0x38)
+#define SPI_RXOICR	(SPI_BASEADDR + 0x3c)
+#define SPI_RXUICR	(SPI_BASEADDR + 0x40)
+#define SPI_MSTICR	(SPI_BASEADDR + 0x44)
+#define SPI_ICR		(SPI_BASEADDR + 0x48)
+#define SPI_IDR		(SPI_BASEADDR + 0x58)
+#define SPI_DR		(SPI_BASEADDR + 0x60)
+
+/* SR - status register bits */
+#define BUSY		(1 << 0)	/* SSI busy flag, serial transfer in progress */
+#define TFNF		(1 << 1)	/* Transmit FIFO not full */
+#define TFE		(1 << 2)	/* Transmit FIFO empty */
+#define RFNE		(1 << 3)	/* Receive FIFO not empty */
+#define RFF		(1 << 4)	/* Receive FIFO full */
+#define TXE		(1 << 5)	/* Transmission error */
+#define DCOL		(1 << 6)	/* Data collision error */
+
+#endif /* _SPI_H */

include/asm-arm/arch-comcerto/sys_proto.h

diff --git a/include/asm-arm/arch-comcerto/sys_proto.h b/include/asm-arm/arch-comcerto/sys_proto.h
new file mode 100644
index 0000000..7361d08
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/sys_proto.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+  */
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+typedef struct {
+	u32 mtype;
+	char *board_string;
+	char *nand_string;
+} omap3_sysinfo;
+
+void prcm_init(void);
+void per_clocks_enable(void);
+
+void memif_init(void);
+void sdrc_init(void);
+void do_sdrc_init(u32, u32);
+void gpmc_init(void);
+
+void watchdog_init(void);
+void set_muxconf_regs(void);
+
+u32 get_cpu_rev(void);
+u32 get_mem_type(void);
+u32 get_sysboot_value(void);
+u32 is_gpmc_muxed(void);
+u32 get_gpmc0_type(void);
+u32 get_gpmc0_width(void);
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+u32 is_running_in_sdram(void);
+u32 is_running_in_sram(void);
+u32 is_running_in_flash(void);
+u32 get_device_type(void);
+void l2cache_enable(void);
+void secureworld_exit(void);
+void setup_auxcr(void);
+void try_unlock_memory(void);
+u32 get_boot_type(void);
+void v7_flush_dcache_all(u32);
+void sr32(void *, u32, u32, u32);
+u32 wait_on_value(u32, u32, void *, u32);
+void sdelay(unsigned long);
+void make_cs1_contiguous(void);
+void omap_nand_switch_ecc(int);
+void power_init_r(void);
+void dieid_num_r(void);
+
+#endif

include/asm-arm/arch-comcerto/system_c2000.h

diff --git a/include/asm-arm/arch-comcerto/system_c2000.h b/include/asm-arm/arch-comcerto/system_c2000.h
new file mode 100644
index 0000000..77d6305
--- /dev/null
+++ b/include/asm-arm/arch-comcerto/system_c2000.h
@@ -0,0 +1,72 @@
+#ifndef __ASM_ARM_SYSTEM_H
+#define __ASM_ARM_SYSTEM_H
+
+#if __LINUX_ARM_ARCH__ >= 7
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
+#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+                                    : : "r" (0) : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+                                    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
+                                    : : "r" (0) : "memory")
+#elif defined(CONFIG_CPU_FA526)
+#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+                                    : : "r" (0) : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+                                    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+                                    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#endif
+
+/*
+ * CR1 bits (CP#15 CR1)
+ */
+#define CR_M    (1 << 0)	/* MMU enable				*/
+#define CR_A    (1 << 1)	/* Alignment abort enable		*/
+#define CR_C    (1 << 2)	/* Dcache enable			*/
+#define CR_W    (1 << 3)	/* Write buffer enable			*/
+#define CR_P    (1 << 4)	/* 32-bit exception handler		*/
+#define CR_D    (1 << 5)	/* 32-bit data address range		*/
+#define CR_L    (1 << 6)	/* Implementation defined		*/
+#define CR_B    (1 << 7)	/* Big endian				*/
+#define CR_S    (1 << 8)	/* System MMU protection		*/
+#define CR_R    (1 << 9)	/* ROM MMU protection			*/
+#define CR_F    (1 << 10)	/* Implementation defined		*/
+#define CR_Z    (1 << 11)	/* Implementation defined		*/
+#define CR_I    (1 << 12)	/* Icache enable			*/
+#define CR_V    (1 << 13)	/* Vectors relocated to 0xffff0000	*/
+#define CR_RR   (1 << 14)	/* Round Robin cache replacement	*/
+#define CR_L4   (1 << 15)	/* LDR pc can set T bit			*/
+#define CR_DT   (1 << 16)
+#define CR_IT   (1 << 18)
+#define CR_ST   (1 << 19)
+#define CR_FI   (1 << 21)	/* Fast interrupt (lower latency mode)	*/
+#define CR_U    (1 << 22)	/* Unaligned access operation		*/
+#define CR_XP   (1 << 23)	/* Extended page tables			*/
+#define CR_VE   (1 << 24)	/* Vectored interrupts			*/
+#define CR_EE   (1 << 25)	/* Exception (Big) Endian		*/
+#define CR_TRE  (1 << 28)	/* TEX remap enable			*/
+#define CR_AFE  (1 << 29)	/* Access flag enable			*/
+#define CR_TE   (1 << 30)	/* Thumb exception enable		*/
+
+static inline unsigned int get_cr(void)
+{
+	unsigned int val;
+	asm("mrc p15, 0, %0, c1, c0, 0  @ get CR" : "=r" (val) : : "cc");
+	return val;
+}
+
+static inline void set_cr(unsigned int val)
+{
+	asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
+	  : : "r" (val) : "cc");
+	isb();
+}
+#endif /* __ASM_ARM_SYSTEM_H */

include/asm-arm/assembler.h

diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
new file mode 100644
index 0000000..6116e48
--- /dev/null
+++ b/include/asm-arm/assembler.h
@@ -0,0 +1,116 @@
+/*
+ *  arch/arm/include/asm/assembler.h
+ *
+ *  Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This file contains arm architecture specific defines
+ *  for the different processors.
+ *
+ *  Do not include any C declarations in this file - it is included by
+ *  assembler source.
+ */
+#ifndef __ASSEMBLY__
+#error "Only include this from assembly code"
+#endif
+
+#include <asm/ptrace.h>
+
+/*
+ * Endian independent macros for shifting bytes within registers.
+ */
+#ifndef __ARMEB__
+#define pull            lsr
+#define push            lsl
+#define get_byte_0      lsl #0
+#define get_byte_1	lsr #8
+#define get_byte_2	lsr #16
+#define get_byte_3	lsr #24
+#define put_byte_0      lsl #0
+#define put_byte_1	lsl #8
+#define put_byte_2	lsl #16
+#define put_byte_3	lsl #24
+#else
+#define pull            lsl
+#define push            lsr
+#define get_byte_0	lsr #24
+#define get_byte_1	lsr #16
+#define get_byte_2	lsr #8
+#define get_byte_3      lsl #0
+#define put_byte_0	lsl #24
+#define put_byte_1	lsl #16
+#define put_byte_2	lsl #8
+#define put_byte_3      lsl #0
+#endif
+
+/*
+ * Data preload for architectures that support it
+ */
+#if __LINUX_ARM_ARCH__ >= 5
+#define PLD(code...)	code
+#else
+#define PLD(code...)
+#endif
+
+/*
+ * This can be used to enable code to cacheline align the destination
+ * pointer when bulk writing to memory.  Experiments on StrongARM and
+ * XScale didn't show this a worthwhile thing to do when the cache is not
+ * set to write-allocate (this would need further testing on XScale when WA
+ * is used).
+ *
+ * On Feroceon there is much to gain however, regardless of cache mode.
+ */
+#ifdef CONFIG_CPU_FEROCEON
+#define CALGN(code...) code
+#else
+#define CALGN(code...)
+#endif
+
+/*
+ * Enable and disable interrupts
+ */
+#if __LINUX_ARM_ARCH__ >= 6
+	.macro	disable_irq
+	cpsid	i
+	.endm
+
+	.macro	enable_irq
+	cpsie	i
+	.endm
+#else
+	.macro	disable_irq
+	msr	cpsr_c, #PSR_I_BIT | SVC_MODE
+	.endm
+
+	.macro	enable_irq
+	msr	cpsr_c, #SVC_MODE
+	.endm
+#endif
+
+/*
+ * Save the current IRQ state and disable IRQs.  Note that this macro
+ * assumes FIQs are enabled, and that the processor is in SVC mode.
+ */
+	.macro	save_and_disable_irqs, oldcpsr
+	mrs	\oldcpsr, cpsr
+	disable_irq
+	.endm
+
+/*
+ * Restore interrupt state previously stored in a register.  We don't
+ * guarantee that this will preserve the flags.
+ */
+	.macro	restore_irqs, oldcpsr
+	msr	cpsr_c, \oldcpsr
+	.endm
+
+#define USER(x...)				\
+9999:	x;					\
+	.section __ex_table,"a";		\
+	.align	3;				\
+	.long	9999b,9001f;			\
+	.previous

include/asm-arm/mach-types.h

diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index 7d7888e..d4eae1c 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -737,6 +737,7 @@
 #define MACH_TYPE_CB3RUFC              726
 #define MACH_TYPE_MP2USB               727
 #define MACH_TYPE_PDNB3               1002
+#define MACH_TYPE_COMCERTO             1094
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type

include/asm-arm/types.h

diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h
index 13e9806..ba79923 100644
--- a/include/asm-arm/types.h
+++ b/include/asm-arm/types.h
@@ -45,6 +45,9 @@
 
 typedef u32 dma_addr_t;
 
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
 #endif /* __KERNEL__ */
 
 #endif

include/asm-arm/u-boot.h

diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h
index c120312..ff24b62 100644
--- a/include/asm-arm/u-boot.h
+++ b/include/asm-arm/u-boot.h
@@ -57,4 +57,7 @@
 #define bi_env_data bi_env->data
 #define bi_env_crc  bi_env->crc
 
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_ARM
+
 #endif	/* _U_BOOT_H_ */

include/bootstage.h

diff --git a/include/bootstage.h b/include/bootstage.h
new file mode 100644
index 0000000..a000538
--- /dev/null
+++ b/include/bootstage.h
@@ -0,0 +1,262 @@
+/*
+ * This file implements recording of each stage of the boot process. It is
+ * intended to implement timing of each stage, reporting this information
+ * to the user and passing it to the OS for logging / further analysis.
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BOOTSTAGE_H
+#define _BOOTSTAGE_H
+
+/* The number of boot stage records available for the user */
+#ifndef CONFIG_BOOTSTAGE_USER_COUNT
+#define CONFIG_BOOTSTAGE_USER_COUNT	20
+#endif
+
+/*
+ * A list of boot stages that we know about. Each of these indicates the
+ * state that we are at, and the action that we are about to perform. For
+ * errors, we issue an error for an item when it fails. Therefore the
+ * normal sequence is:
+ *
+ * progress action1
+ * progress action2
+ * progress action3
+ *
+ * and an error condition where action 3 failed would be:
+ *
+ * progress action1
+ * progress action2
+ * progress action3
+ * error on action3
+ */
+enum bootstage_id {
+	BOOTSTAGE_ID_START = 0,
+	BOOTSTAGE_ID_CHECK_MAGIC,	/* Checking image magic */
+	BOOTSTAGE_ID_CHECK_HEADER,	/* Checking image header */
+	BOOTSTAGE_ID_CHECK_CHECKSUM,	/* Checking image checksum */
+	BOOTSTAGE_ID_CHECK_ARCH,	/* Checking architecture */
+
+	BOOTSTAGE_ID_CHECK_IMAGETYPE = 5,/* Checking image type */
+	BOOTSTAGE_ID_DECOMP_IMAGE,	/* Decompressing image */
+	BOOTSTAGE_ID_KERNEL_LOADED,	/* Kernel has been loaded */
+	BOOTSTAGE_ID_DECOMP_UNIMPL = 7,	/* Odd decompression algorithm */
+	BOOTSTAGE_ID_CHECK_BOOT_OS,	/* Calling OS-specific boot function */
+	BOOTSTAGE_ID_BOOT_OS_RETURNED,	/* Tried to boot OS, but it returned */
+	BOOTSTAGE_ID_CHECK_RAMDISK = 9,	/* Checking ram disk */
+
+	BOOTSTAGE_ID_RD_MAGIC,		/* Checking ram disk magic */
+	BOOTSTAGE_ID_RD_HDR_CHECKSUM,	/* Checking ram disk heder checksum */
+	BOOTSTAGE_ID_RD_CHECKSUM,	/* Checking ram disk checksum */
+	BOOTSTAGE_ID_COPY_RAMDISK = 12,	/* Copying ram disk into place */
+	BOOTSTAGE_ID_RAMDISK,		/* Checking for valid ramdisk */
+	BOOTSTAGE_ID_NO_RAMDISK,	/* No ram disk found (not an error) */
+
+	BOOTSTAGE_ID_RUN_OS	= 15,	/* Exiting U-Boot, entering OS */
+
+	BOOTSTAGE_ID_NEED_RESET = 30,
+	BOOTSTAGE_ID_POST_FAIL,		/* Post failure */
+	BOOTSTAGE_ID_POST_FAIL_R,	/* Post failure reported after reloc */
+
+	/*
+	 * This set is reported ony by x86, and the meaning is different. In
+	 * this case we are reporting completion of a particular stage.
+	 * This should probably change in he x86 code (which doesn't report
+	 * errors in any case), but discussion this can perhaps wait until we
+	 * have a generic board implementation.
+	 */
+	BOOTSTAGE_ID_BOARD_INIT_R,	/* We have relocated */
+	BOOTSTAGE_ID_BOARD_GLOBAL_DATA,	/* Global data is set up */
+
+	BOOTSTAGE_ID_BOARD_INIT_SEQ,	/* We completed the init sequence */
+	BOOTSTAGE_ID_BOARD_FLASH,	/* We have configured flash banks */
+	BOOTSTAGE_ID_BOARD_FLASH_37,	/* In case you didn't hear... */
+	BOOTSTAGE_ID_BOARD_ENV,		/* Environment is relocated & ready */
+	BOOTSTAGE_ID_BOARD_PCI,		/* PCI is up */
+
+	BOOTSTAGE_ID_BOARD_INTERRUPTS,	/* Exceptions / interrupts ready */
+	BOOTSTAGE_ID_BOARD_DONE,	/* Board init done, off to main loop */
+	/* ^^^ here ends the x86 sequence */
+
+	/* Boot stages related to loading a kernel from an IDE device */
+	BOOTSTAGE_ID_IDE_START = 41,
+	BOOTSTAGE_ID_IDE_ADDR,
+	BOOTSTAGE_ID_IDE_BOOT_DEVICE,
+	BOOTSTAGE_ID_IDE_TYPE,
+
+	BOOTSTAGE_ID_IDE_PART,
+	BOOTSTAGE_ID_IDE_PART_INFO,
+	BOOTSTAGE_ID_IDE_PART_TYPE,
+	BOOTSTAGE_ID_IDE_PART_READ,
+	BOOTSTAGE_ID_IDE_FORMAT,
+
+	BOOTSTAGE_ID_IDE_CHECKSUM,	/* 50 */
+	BOOTSTAGE_ID_IDE_READ,
+
+	/* Boot stages related to loading a kernel from an NAND device */
+	BOOTSTAGE_ID_NAND_PART,
+	BOOTSTAGE_ID_NAND_SUFFIX,
+	BOOTSTAGE_ID_NAND_BOOT_DEVICE,
+	BOOTSTAGE_ID_NAND_HDR_READ = 55,
+	BOOTSTAGE_ID_NAND_AVAILABLE = 55,
+	BOOTSTAGE_ID_NAND_TYPE = 57,
+	BOOTSTAGE_ID_NAND_READ,
+
+	/* Boot stages related to loading a kernel from an network device */
+	BOOTSTAGE_ID_NET_CHECKSUM = 60,
+	BOOTSTAGE_ID_NET_ETH_START = 64,
+	BOOTSTAGE_ID_NET_ETH_INIT,
+
+	BOOTSTAGE_ID_NET_START = 80,
+	BOOTSTAGE_ID_NET_NETLOOP_OK,
+	BOOTSTAGE_ID_NET_LOADED,
+	BOOTSTAGE_ID_NET_DONE_ERR,
+	BOOTSTAGE_ID_NET_DONE,
+
+	/*
+	 * Boot stages related to loading a FIT image. Some of these are a
+	 * bit wonky.
+	 */
+	BOOTSTAGE_ID_FIT_FORMAT = 100,
+	BOOTSTAGE_ID_FIT_NO_UNIT_NAME,
+	BOOTSTAGE_ID_FIT_UNIT_NAME,
+	BOOTSTAGE_ID_FIT_CONFIG,
+	BOOTSTAGE_ID_FIT_CHECK_SUBIMAGE,
+	BOOTSTAGE_ID_FIT_CHECK_HASH = 104,
+
+	BOOTSTAGE_ID_FIT_CHECK_ARCH,
+	BOOTSTAGE_ID_FIT_CHECK_KERNEL,
+	BOOTSTAGE_ID_FIT_CHECKED,
+
+	BOOTSTAGE_ID_FIT_KERNEL_INFO_ERR = 107,
+	BOOTSTAGE_ID_FIT_KERNEL_INFO,
+	BOOTSTAGE_ID_FIT_TYPE,
+
+	BOOTSTAGE_ID_FIT_COMPRESSION,
+	BOOTSTAGE_ID_FIT_OS,
+	BOOTSTAGE_ID_FIT_LOADADDR,
+	BOOTSTAGE_ID_OVERWRITTEN,
+
+	BOOTSTAGE_ID_FIT_RD_FORMAT = 120,
+	BOOTSTAGE_ID_FIT_RD_FORMAT_OK,
+	BOOTSTAGE_ID_FIT_RD_NO_UNIT_NAME,
+	BOOTSTAGE_ID_FIT_RD_UNIT_NAME,
+	BOOTSTAGE_ID_FIT_RD_SUBNODE,
+
+	BOOTSTAGE_ID_FIT_RD_CHECK,
+	BOOTSTAGE_ID_FIT_RD_HASH = 125,
+	BOOTSTAGE_ID_FIT_RD_CHECK_ALL,
+	BOOTSTAGE_ID_FIT_RD_GET_DATA,
+	BOOTSTAGE_ID_FIT_RD_CHECK_ALL_OK = 127,
+	BOOTSTAGE_ID_FIT_RD_GET_DATA_OK,
+	BOOTSTAGE_ID_FIT_RD_LOAD,
+
+	BOOTSTAGE_ID_IDE_FIT_READ = 140,
+	BOOTSTAGE_ID_IDE_FIT_READ_OK,
+
+	BOOTSTAGE_ID_NAND_FIT_READ = 150,
+	BOOTSTAGE_ID_NAND_FIT_READ_OK,
+
+	/*
+	 * These boot stages are new, higher level, and not directly related
+	 * to the old boot progress numbers. They are useful for recording
+	 * rough boot timing information.
+	 */
+	BOOTSTAGE_ID_AWAKE,
+	BOOTSTAGE_ID_START_UBOOT_F,
+	BOOTSTAGE_ID_START_UBOOT_R,
+	BOOTSTAGE_ID_USB_START,
+	BOOTSTAGE_ID_ETH_START,
+	BOOTSTAGE_ID_BOOTP_START,
+	BOOTSTAGE_ID_BOOTP_STOP,
+	BOOTSTAGE_ID_BOOTM_START,
+	BOOTSTAGE_ID_BOOTM_HANDOFF,
+	BOOTSTAGE_ID_MAIN_LOOP,
+	BOOTSTAGE_KERNELREAD_START,
+	BOOTSTAGE_KERNELREAD_STOP,
+
+	BOOTSTAGE_ID_CPU_AWAKE,
+	BOOTSTAGE_ID_MAIN_CPU_AWAKE,
+	BOOTSTAGE_ID_MAIN_CPU_READY,
+
+	/* a few spare for the user, from here */
+	BOOTSTAGE_ID_USER,
+	BOOTSTAGE_ID_COUNT = BOOTSTAGE_ID_USER + CONFIG_BOOTSTAGE_USER_COUNT,
+	BOOTSTAGE_ID_ALLOC,
+};
+
+/*
+ * Return the time since boot in microseconds, This is needed for bootstage
+ * and should be defined in CPU- or board-specific code. If undefined then
+ * millisecond resolution will be used (the standard get_timer()).
+ */
+ulong timer_get_boot_us(void);
+
+/*
+ * Board code can implement show_boot_progress() if needed.
+ *
+ * @param val	Progress state (enum bootstage_id), or -id if an error
+ *		has occurred.
+ */
+void show_boot_progress(int val);
+
+#ifdef CONFIG_BOOTSTAGE
+/* This is the full bootstage implementation */
+
+/*
+ * Mark a time stamp for the current boot stage.
+ */
+ulong bootstage_mark(enum bootstage_id id);
+
+ulong bootstage_error(enum bootstage_id id);
+
+ulong bootstage_mark_name(enum bootstage_id id, const char *name);
+
+/* Print a report about boot time */
+void bootstage_report(void);
+
+#else
+/*
+ * This is a dummy implementation which just calls show_boot_progress(),
+ * and won't even do that unless CONFIG_SHOW_BOOT_PROGRESS is defined
+ */
+
+static inline ulong bootstage_mark(enum bootstage_id id)
+{
+	show_boot_progress(id);
+	return 0;
+}
+
+static inline ulong bootstage_error(enum bootstage_id id)
+{
+	show_boot_progress(-id);
+	return 0;
+}
+
+static inline ulong bootstage_mark_name(enum bootstage_id id, const char *name)
+{
+	return 0;
+}
+
+
+#endif /* CONFIG_BOOTSTAGE */
+
+#endif

include/command.h

diff --git a/include/command.h b/include/command.h
index a2936ad..6f87203 100644
--- a/include/command.h
+++ b/include/command.h
@@ -76,6 +76,23 @@
 
 typedef	void 	command_t (cmd_tbl_t *, int, int, char *[]);
 
+/*
+ * Error codes that commands return to cmd_process(). We use the standard 0
+ * and 1 for success and failure, but add one more case - failure with a
+ * request to call cmd_usage(). But the cmd_process() function handles
+ * CMD_RET_USAGE itself and after calling cmd_usage() it will return 1.
+ * This is just a convenience for commands to avoid them having to call
+ * cmd_usage() all over the place.
+ */
+enum command_ret_t {
+	CMD_RET_SUCCESS,	/* 0 = Success */
+	CMD_RET_FAILURE,	/* 1 = Failure */
+	CMD_RET_USAGE = -1,	/* Failure, please report 'usage' error */
+};
+
+
+
+
 #endif	/* __ASSEMBLY__ */
 
 /*

include/common.h

diff --git a/include/common.h b/include/common.h
index 349d5cf..42e33ec 100644
--- a/include/common.h
+++ b/include/common.h
@@ -626,4 +626,88 @@
 #error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
 #endif
 
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#define ROUND(a,b)		(((a) + (b) - 1) & ~((b) - 1))
+#define DIV_ROUND(n,d)		(((n) + ((d)/2)) / (d))
+#define DIV_ROUND_UP(n,d)	(((n) + (d) - 1) / (d))
+#define roundup(x, y)		((((x) + ((y) - 1)) / (y)) * (y))
+
+#define ALIGN(x,a)		__ALIGN_MASK((x),(typeof(x))(a)-1)
+#define __ALIGN_MASK(x,mask)	(((x)+(mask))&~(mask))
+
+#if 0
+/*
+ * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture.  It
+ * is used to align DMA buffers.
+ */
+#ifndef __ASSEMBLY__
+#include <asm/cache.h>
+#endif
+
+/*
+ * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the
+ * stack that meets the minimum architecture alignment requirements for DMA.
+ * Such a buffer is useful for DMA operations where flushing and invalidating
+ * the cache before and after a read and/or write operation is required for
+ * correct operations.
+ *
+ * When called the macro creates an array on the stack that is sized such
+ * that:
+ *
+ * 1) The beginning of the array can be advanced enough to be aligned.
+ *
+ * 2) The size of the aligned portion of the array is a multiple of the minimum
+ *    architecture alignment required for DMA.
+ *
+ * 3) The aligned portion contains enough space for the original number of
+ *    elements requested.
+ *
+ * The macro then creates a pointer to the aligned portion of this array and
+ * assigns to the pointer the address of the first element in the aligned
+ * portion of the array.
+ *
+ * Calling the macro as:
+ *
+ *     ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024);
+ *
+ * Will result in something similar to saying:
+ *
+ *     uint32_t    buffer[1024];
+ *
+ * The following differences exist:
+ *
+ * 1) The resulting buffer is guaranteed to be aligned to the value of
+ *    ARCH_DMA_MINALIGN.
+ *
+ * 2) The buffer variable created by the macro is a pointer to the specified
+ *    type, and NOT an array of the specified type.  This can be very important
+ *    if you want the address of the buffer, which you probably do, to pass it
+ *    to the DMA hardware.  The value of &buffer is different in the two cases.
+ *    In the macro case it will be the address of the pointer, not the address
+ *    of the space reserved for the buffer.  However, in the second case it
+ *    would be the address of the buffer.  So if you are replacing hard coded
+ *    stack buffers with this macro you need to make sure you remove the & from
+ *    the locations where you are taking the address of the buffer.
+ *
+ * Note that the size parameter is the number of array elements to allocate,
+ * not the number of bytes.
+ *
+ * This macro can not be used outside of function scope, or for the creation
+ * of a function scoped static buffer.  It can not be used to create a cache
+ * line aligned global buffer.
+ */
+#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size)			\
+	char __##name[ROUND(size * sizeof(type), ARCH_DMA_MINALIGN) +	\
+		      ARCH_DMA_MINALIGN - 1];				\
+									\
+	type *name = (type *) ALIGN((uintptr_t)__##name, ARCH_DMA_MINALIGN)
+
+/* Pull in stuff for the build system */
+#ifdef DO_DEPS_ONLY
+# include <environment.h>
+#endif
+
+
+#endif
 #endif	/* __COMMON_H_ */

include/compiler.h

diff --git a/include/compiler.h b/include/compiler.h
new file mode 100644
index 0000000..0734ed4
--- /dev/null
+++ b/include/compiler.h
@@ -0,0 +1,137 @@
+/*
+ * Keep all the ugly #ifdef for system stuff here
+ */
+
+#ifndef __COMPILER_H__
+#define __COMPILER_H__
+
+#include <stddef.h>
+
+#ifdef USE_HOSTCC
+
+#if defined(__BEOS__)	 || \
+    defined(__NetBSD__)  || \
+    defined(__FreeBSD__) || \
+    defined(__sun__)	 || \
+    defined(__APPLE__)
+# include <inttypes.h>
+#elif defined(__linux__) || defined(__WIN32__) || defined(__MINGW32__)
+# include <stdint.h>
+#endif
+
+#include <errno.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#if !defined(__WIN32__) && !defined(__MINGW32__)
+# include <sys/mman.h>
+#endif
+
+/* Not all systems (like Windows) has this define, and yes
+ * we do replace/emulate mmap() on those systems ...
+ */
+#ifndef MAP_FAILED
+# define MAP_FAILED ((void *)-1)
+#endif
+
+#include <fcntl.h>
+#ifndef O_BINARY		/* should be define'd on __WIN32__ */
+#define O_BINARY	0
+#endif
+
+#ifdef __linux__
+# include <endian.h>
+# include <byteswap.h>
+#elif defined(__MACH__) || defined(__FreeBSD__)
+# include <machine/endian.h>
+typedef unsigned long ulong;
+#endif
+
+typedef uint8_t __u8;
+typedef uint16_t __u16;
+typedef uint32_t __u32;
+typedef unsigned int uint;
+
+#define uswap_16(x) \
+	((((x) & 0xff00) >> 8) | \
+	 (((x) & 0x00ff) << 8))
+#define uswap_32(x) \
+	((((x) & 0xff000000) >> 24) | \
+	 (((x) & 0x00ff0000) >>  8) | \
+	 (((x) & 0x0000ff00) <<  8) | \
+	 (((x) & 0x000000ff) << 24))
+#define _uswap_64(x, sfx) \
+	((((x) & 0xff00000000000000##sfx) >> 56) | \
+	 (((x) & 0x00ff000000000000##sfx) >> 40) | \
+	 (((x) & 0x0000ff0000000000##sfx) >> 24) | \
+	 (((x) & 0x000000ff00000000##sfx) >>  8) | \
+	 (((x) & 0x00000000ff000000##sfx) <<  8) | \
+	 (((x) & 0x0000000000ff0000##sfx) << 24) | \
+	 (((x) & 0x000000000000ff00##sfx) << 40) | \
+	 (((x) & 0x00000000000000ff##sfx) << 56))
+#if defined(__GNUC__)
+# define uswap_64(x) _uswap_64(x, ull)
+#else
+# define uswap_64(x) _uswap_64(x, )
+#endif
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+# define cpu_to_le16(x)		(x)
+# define cpu_to_le32(x)		(x)
+# define cpu_to_le64(x)		(x)
+# define le16_to_cpu(x)		(x)
+# define le32_to_cpu(x)		(x)
+# define le64_to_cpu(x)		(x)
+# define cpu_to_be16(x)		uswap_16(x)
+# define cpu_to_be32(x)		uswap_32(x)
+# define cpu_to_be64(x)		uswap_64(x)
+# define be16_to_cpu(x)		uswap_16(x)
+# define be32_to_cpu(x)		uswap_32(x)
+# define be64_to_cpu(x)		uswap_64(x)
+#else
+# define cpu_to_le16(x)		uswap_16(x)
+# define cpu_to_le32(x)		uswap_32(x)
+# define cpu_to_le64(x)		uswap_64(x)
+# define le16_to_cpu(x)		uswap_16(x)
+# define le32_to_cpu(x)		uswap_32(x)
+# define le64_to_cpu(x)		uswap_64(x)
+# define cpu_to_be16(x)		(x)
+# define cpu_to_be32(x)		(x)
+# define cpu_to_be64(x)		(x)
+# define be16_to_cpu(x)		(x)
+# define be32_to_cpu(x)		(x)
+# define be64_to_cpu(x)		(x)
+#endif
+
+#else /* !USE_HOSTCC */
+
+#include <linux/string.h>
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+#if __SIZEOF_LONG__ == 8
+# define __WORDSIZE	64
+#elif __SIZEOF_LONG__ == 4
+# define __WORDSIZE	32
+#else
+/*
+ * Assume 32-bit for now - only newer toolchains support this feature and
+ * this is only required for sandbox support at present.
+ */
+#define __WORDSIZE	32
+#endif
+
+/* Type for `void *' pointers. */
+typedef unsigned long int uintptr_t;
+
+#endif /* USE_HOSTCC */
+
+/* compiler options */
+#define uninitialized_var(x)		x = x
+
+#define likely(x)	__builtin_expect(!!(x), 1)
+#define unlikely(x)	__builtin_expect(!!(x), 0)
+
+#endif

include/configs/DU405.h

diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index 5489a53..1640b1c 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -32,7 +32,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_IDENT_STRING     " $Name:  $"
+#define CONFIG_IDENT_STRING     " $Name: uboot_c2k_1_00_1 $"
 
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/

include/configs/WUH405.h

diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index faf855d..3c0d2f5 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -32,7 +32,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_IDENT_STRING     " $Name:  $"
+#define CONFIG_IDENT_STRING     " $Name: uboot_c2k_1_00_1 $"
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/

include/configs/asic.h

diff --git a/include/configs/asic.h b/include/configs/asic.h
new file mode 100644
index 0000000..c861868
--- /dev/null
+++ b/include/configs/asic.h
@@ -0,0 +1,291 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_100	1	/* It's an  SoC */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE         0x10000000 /* 256MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_GMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC1_PHYIDX		0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET |  /*CFG_CMD_NAND |*/ CFG_CMD_JFFS2 | CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_MII)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-100 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto100\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-asic\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=rootfs.jffs2-64k\0" \
+	"updatefs=tftp 81000000 ${fsfile};protect off 1:6-127\;erase 1:6-127;cp.b 81000000 20060000 ${filesize}\0" \
+	"updateboot=tftp 81000000 u-boot.bin;protect off 1:0-3\;erase 1:0-3;cp.b 81000000 20000000 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0x20000000	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+  
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (2 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 4 * PHYS_FLASH1_SECT_SIZE)	/* Keep 4 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment 16KiB */
+  
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),7808k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		165000000	/* 165 MHz, must be multiple of 33MHz */
+#define CFG_ARM_CLOCK		450000000	/* 450 MHz, must be multiple of 25MHz */
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00010000 /* 64K */
+#define CFG_ARAM_CODE_SIZE	0x00008000 /* 32K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#define DDR_TRAINING_DBG 
+
+/* New DDR training defines (Bug #44131) */
+#define NEW_DDR_TRAINING  //undef this for old training
+//#undef NEW_DDR_TRAINING  //undef this for old training
+
+#endif /* __CONFIG_H */

include/configs/asic_aram.h

diff --git a/include/configs/asic_aram.h b/include/configs/asic_aram.h
new file mode 100644
index 0000000..b36df50
--- /dev/null
+++ b/include/configs/asic_aram.h
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_100	1	/* It's an  SoC */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_UBOOT_LOADED_IN_ARAM
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE         0x10000000 /* 256MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#undef CONFIG_COMCERTO_GEMAC
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_GMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC1_PHYIDX		0
+
+#undef CONFIG_NET_MULTI
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | /*CFG_CMD_ENV |*/ CFG_CMD_MEMORY | CFG_CMD_RUN /*| CFG_CMD_NET |  CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM */)
+
+#define CONFIG_NO_GZIP		1
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-100 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto100\0"						\
+	"netdev=eth0\0"									\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"boot_flash=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"writeboot=protect off 1:0-3\;erase 1:0-3;cp.b 81000000 20000000 40000\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0x20000000	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+  
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (2 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_NOWHERE	1
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 4 * PHYS_FLASH1_SECT_SIZE)	/* Keep 4 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment 16KiB */
+  
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),7808k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		165000000	/* 165 MHz, must be multiple of 33MHz */
+#define CFG_ARM_CLOCK		450000000	/* 450 MHz, must be multiple of 25MHz */
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00010000 /* 64K */
+#define CFG_ARAM_CODE_SIZE	0x00000400 /* 1K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#define DDR_TRAINING_DBG 
+
+/* New DDR training defines (Bug #44131) */
+#define NEW_DDR_TRAINING  //undef this for old training
+//#undef NEW_DDR_TRAINING  //undef this for old training
+
+#endif /* __CONFIG_H */

include/configs/c1kasic-nand.h

diff --git a/include/configs/c1kasic-nand.h b/include/configs/c1kasic-nand.h
new file mode 100644
index 0000000..9d0dc6a
--- /dev/null
+++ b/include/configs/c1kasic-nand.h
@@ -0,0 +1,702 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_1000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C1KASIC	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		DDR_BASEADDR
+#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+//#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		8
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC1_PHYIDX		0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(/*CFG_CMD_FLASH |*/ CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_NET | CFG_CMD_NAND | CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_ELF/*| CFG_CMD_SPI*/)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-1000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto1000\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root="ROOT_MTDBLOCK" rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; uload /boot/uImage; bootm\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-c1kasic\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+	"bootfile=u-boot-nand.bin\0"\
+	"updatenandfs=tftp 85000000 ${fsfile};nand erase 100000 ${filesize};nand write.jffs2 85000000 100000 ${filesize}\0" \
+	"updatenandboot=tftp 81000000 ${bootfile};nand erase 0 40000;nand write.jffs2 81000000 0 40000\0" \
+	"eepromfile=eeprom.bin\0" \
+	"updateeprom=tftp 81000000 ${eepromfile};eeprom write 81000000 0 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+// #define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+
+#define CFG_NAND_BASE			EXP_CS4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00080000	/* Offset of Environment Sector(512KB) */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x80000	/* Total Size of Environment 512KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:512k(u-boot),512k(env),16384k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+// DDR Configs
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #1
+#define DENALI_CTL_00_VAL_CFG1	0x0100000101010101LL //0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG1	0x0100010001000000LL //0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG1	0x0200000000010100LL //0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG1	0x0202020202020202LL //0x0202020202020202LL
+// #define DENALI_CTL_04_VAL_CFG1	0x0000010100000001LL
+// Original Value
+// #define DENALI_CTL_05_VAL_CFG1	0x0003010500010001LL
+// Dror's modification  rtt_0=1 
+#define DENALI_CTL_05_VAL_CFG1	0x0003010500010001LL
+#define DENALI_CTL_06_VAL_CFG1	0x0a0a040300030300LL
+#define DENALI_CTL_07_VAL_CFG1	0x000000050000020aLL
+#define DENALI_CTL_08_VAL_CFG1	0x6400003f3f16020eLL
+#define DENALI_CTL_09_VAL_CFG1	0x0000640064006400LL
+// #define DENALI_CTL_10_VAL_CFG1	0x0120202020191a18LL
+#define DENALI_CTL_11_VAL_CFG1	0x0000003300000000LL
+#define DENALI_CTL_12_VAL_CFG1	0x0000000000001000LL
+#define DENALI_CTL_13_VAL_CFG1	0x0010001000100010LL	
+#define DENALI_CTL_14_VAL_CFG1	0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG1	0x0c2d000000000000LL
+#define DENALI_CTL_16_VAL_CFG1	0x000000006d560000LL
+#define DENALI_CTL_17_VAL_CFG1	0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG1	0x0600010000000000LL
+#define DENALI_CTL_19_VAL_CFG1	0x00003700c8050b00LL
+#define DENALI_CTL_20_VAL_CFG1	0x00000101388000c8LL
+#define DENALI_CTL_21_VAL_CFG1	0x0202020100000101LL
+#define DENALI_CTL_22_VAL_CFG1	0x0000020007000002LL
+// #define DENALI_CTL_23_VAL_CFG1
+#define DENALI_CTL_24_VAL_CFG1	0x0000000200a00000LL
+#define DENALI_CTL_25_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG1	0x9440492794404927LL
+#define DENALI_CTL_27_VAL_CFG1	0x9440492794404927LL
+#define DENALI_CTL_28_VAL_CFG1	0x07c0040107c00401LL
+#define DENALI_CTL_29_VAL_CFG1	0x07c0040107c00401LL
+#define DENALI_CTL_30_VAL_CFG1	0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG1	0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG1	0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG1	0x0034343434050000LL
+#define DENALI_CTL_36_VAL_CFG1	0x0000000000000004LL
+// original settings
+// #define DENALI_CTL_37_VAL_CFG1	0x0a52000000040000LL
+// Dror's settings rtt=11 bit[1]=1
+#define DENALI_CTL_37_VAL_CFG1	0x0a52000000440200LL
+#define DENALI_CTL_38_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG1	0x00000000000000c8LL
+// #define DENALI_CTL_41_VAL_CFG1	0x00cc005000cc0050LL
+#define DENALI_CTL_41_VAL_CFG1	0x0017005000170050LL
+#define DENALI_CTL_42_VAL_CFG1	DENALI_CTL_41_VAL_CFG1
+#define DENALI_CTL_43_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_44_VAL_CFG1	DENALI_CTL_43_VAL_CFG1
+#define DENALI_CTL_45_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG1	0x0000000000000050LL
+#define DENALI_CTL_50_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG1	0x0000000000000000LL
+// #define DENALI_CTL_63_VAL_CFG1	0x0000000000000000LL
+// #define DENALI_CTL_64_VAL_CFG1	0x0000000000000000LL
+// #define DENALI_CTL_65_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG1	0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG1	0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG1	0x00000003e8050000LL
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #2
+#define DENALI_CTL_00_VAL_CFG2	0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG2	0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG2	0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG2	0x0202020202020202LL
+// #define DENALI_CTL_04_VAL_CFG2	0x0000010100000001LL
+// original settings
+// #define DENALI_CTL_05_VAL_CFG2	0x0003010500010001LL
+// Dror's settings rtt_0=1
+#define DENALI_CTL_05_VAL_CFG2	0x0003010300010001LL
+// original settings
+// #define DENALI_CTL_06_VAL_CFG2	0x0a0a040300030300LL
+// Dror's settings
+#define DENALI_CTL_06_VAL_CFG2	0x060a020200020200LL
+// original settings
+// #define DENALI_CTL_07_VAL_CFG2	0x000000050000020aLL
+// Dror's settings
+#define DENALI_CTL_07_VAL_CFG2	0x0000000300000205LL
+// original settings
+// #define DENALI_CTL_08_VAL_CFG2	0x6400003f3f16020eLL
+// Dror's settings
+#define DENALI_CTL_08_VAL_CFG2	0x6400003f3f0b0207LL
+#define DENALI_CTL_09_VAL_CFG2	0x0000640064006400LL
+// #define DENALI_CTL_10_VAL_CFG2	0x0120202020191a18LL
+// original settings
+// #define DENALI_CTL_11_VAL_CFG2	0x0000003300000000LL
+// Dror's settings
+#define DENALI_CTL_11_VAL_CFG2	0x0000001a00000000LL
+// original settings
+// #define DENALI_CTL_12_VAL_CFG2	0x0000000000001000LL
+// Dror's settings
+#define DENALI_CTL_12_VAL_CFG2	0x0000000000000800LL
+#define DENALI_CTL_13_VAL_CFG2	0x0010001000100010LL	
+#define DENALI_CTL_14_VAL_CFG2	0x0010001000100010LL
+// original settings
+// #define DENALI_CTL_15_VAL_CFG2	0x0c2d000000000000LL
+// Dror's settings
+#define DENALI_CTL_15_VAL_CFG2	0x0612000000000000LL
+// original settings
+// #define DENALI_CTL_16_VAL_CFG2	0x000000006d560000LL
+// Dror's settings
+#define DENALI_CTL_16_VAL_CFG2	0x0000000036a60000LL
+#define DENALI_CTL_17_VAL_CFG2	0x0000010000000000LL
+// original settings
+// #define DENALI_CTL_18_VAL_CFG2	0x0600010000000000LL
+// Dror's settings
+#define DENALI_CTL_18_VAL_CFG2	0x0300010000000000LL
+// original settings
+// #define DENALI_CTL_19_VAL_CFG2	0x00003700c8050b00LL
+// Dror's settings
+#define DENALI_CTL_19_VAL_CFG2	0x00001c00c8030600LL
+// original settings
+// #define DENALI_CTL_20_VAL_CFG2	0x00000101388000c8LL
+// Dror's settings
+#define DENALI_CTL_20_VAL_CFG2	0x000001009c4000c8LL
+/* Original settings, AHB/DDR synchronous */
+#define DENALI_CTL_21_VAL_CFG2	0x0303030100000101LL
+#define DENALI_CTL_22_VAL_CFG2	0x0000020006000003LL
+/* AHB/DDR asynchronous */
+//#define DENALI_CTL_21_VAL_CFG2	0x0000000100000101LL
+//#define DENALI_CTL_22_VAL_CFG2	0x0000020006000000LL
+// #define DENALI_CTL_23_VAL_CFG2
+// original settings
+// #define DENALI_CTL_24_VAL_CFG2	0x0000000200a00000LL
+// Dror's settings
+#define DENALI_CTL_24_VAL_CFG2	0x0000000200500000LL
+#define DENALI_CTL_25_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG2	0x9340492793404927LL
+#define DENALI_CTL_27_VAL_CFG2	0x9340492793404927LL
+#define DENALI_CTL_28_VAL_CFG2	0x07c0040107c00401LL
+#define DENALI_CTL_29_VAL_CFG2	0x07c0040107c00401LL
+#define DENALI_CTL_30_VAL_CFG2	0x0000000000000004LL
+#define DENALI_CTL_31_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG2	0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG2	0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG2	0x0000000000000000LL
+// original settings
+// #define DENALI_CTL_35_VAL_CFG2	0x0034343434050000LL
+// Dror's settings
+#define DENALI_CTL_35_VAL_CFG2	0x0074747474030000LL
+#define DENALI_CTL_36_VAL_CFG2	0x0000000000000004LL
+// original settings
+// #define DENALI_CTL_37_VAL_CFG2	0x0a52000000040000LL
+// Dror's settings rtt=11 bit[1]=1
+#define DENALI_CTL_37_VAL_CFG2	0x0432000000040200LL
+#define DENALI_CTL_38_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG2	0x0000000000000000LL
+// original settings
+// #define DENALI_CTL_40_VAL_CFG2	0x00000000000000c8LL
+// Dror's settings
+#define DENALI_CTL_40_VAL_CFG2	0x0000000000000064LL
+// #define DENALI_CTL_41_VAL_CFG2	0x00cc005000cc0050LL
+// original settings
+// #define DENALI_CTL_41_VAL_CFG2	0x0017005000170050LL
+// Dror's settings adj1 = 0x28 
+#define DENALI_CTL_41_VAL_CFG2	0x0028009000280090LL
+#define DENALI_CTL_42_VAL_CFG2	DENALI_CTL_41_VAL_CFG2
+#define DENALI_CTL_43_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_44_VAL_CFG2	DENALI_CTL_43_VAL_CFG2
+#define DENALI_CTL_45_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG2	0x0000000000000000LL
+// original settings
+// #define DENALI_CTL_49_VAL_CFG2	0x0000000000000050LL
+// Dror's settings
+#define DENALI_CTL_49_VAL_CFG2	0x0000000000000028LL
+#define DENALI_CTL_50_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG2	0x0000000000000000LL
+// #define DENALI_CTL_63_VAL_CFG2	0x0000000000000000LL
+// #define DENALI_CTL_64_VAL_CFG2	0x0000000000000000LL
+// #define DENALI_CTL_65_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG2	0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG2	0x00000003e8050000LL
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #3
+#define DENALI_CTL_00_VAL_CFG3	0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG3	0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG3	0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG3	0x0202020202020202LL
+// #define DENALI_CTL_04_VAL_CFG3	0x0000010100000001LL
+#define DENALI_CTL_05_VAL_CFG3	0x0003010500010001LL
+#define DENALI_CTL_06_VAL_CFG3	0x0a0a040300030300LL
+#define DENALI_CTL_07_VAL_CFG3	0x000000050000020aLL
+#define DENALI_CTL_08_VAL_CFG3	0x6400003f3f15020eLL
+#define DENALI_CTL_09_VAL_CFG3	0x0000640064006400LL
+// #define DENALI_CTL_10_VAL_CFG3	0x0120202020191a18LL
+#define DENALI_CTL_11_VAL_CFG3	0x0000003000000000LL
+#define DENALI_CTL_12_VAL_CFG3	0x0000000000000f00LL
+#define DENALI_CTL_13_VAL_CFG3	0x0010001000100010LL	
+#define DENALI_CTL_14_VAL_CFG3	0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG3	0x0b50000000000000LL
+#define DENALI_CTL_16_VAL_CFG3	0x00000000659d0000LL
+#define DENALI_CTL_17_VAL_CFG3	0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG3	0x0600010000000000LL
+#define DENALI_CTL_19_VAL_CFG3	0x00003400c8050b00LL
+#define DENALI_CTL_20_VAL_CFG3	0x00000101226e00c8LL
+/* Original settings, AHB/DDR synchronous */
+#define DENALI_CTL_21_VAL_CFG3	0x0202020100000101LL
+#define DENALI_CTL_22_VAL_CFG3	0x0000020007000002LL
+/* AHB/DDR asynchronous */
+//#define DENALI_CTL_21_VAL_CFG3	0x0000000100000101LL
+//#define DENALI_CTL_22_VAL_CFG3	0x0000020007000000LL
+// #define DENALI_CTL_23_VAL_CFG3
+#define DENALI_CTL_24_VAL_CFG3	0x0000000200950000LL
+#define DENALI_CTL_25_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG3	0x9440492794404927LL
+#define DENALI_CTL_27_VAL_CFG3	0x9440492794404927LL
+#define DENALI_CTL_28_VAL_CFG3	0x07c0040107c00401LL
+#define DENALI_CTL_29_VAL_CFG3	0x07c0040107c00401LL
+#define DENALI_CTL_30_VAL_CFG3	0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG3	0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG3	0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG3	0x0034343434050000LL
+#define DENALI_CTL_36_VAL_CFG3	0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG3	0x0a52000000040200LL
+#define DENALI_CTL_38_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG3	0x00000000000000baLL
+// #define DENALI_CTL_41_VAL_CFG3	0x00cc005000cc0050LL
+#define DENALI_CTL_41_VAL_CFG3	0x00cc005000cc0050LL
+#define DENALI_CTL_42_VAL_CFG3	DENALI_CTL_41_VAL_CFG3
+#define DENALI_CTL_43_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_44_VAL_CFG3	DENALI_CTL_43_VAL_CFG3
+#define DENALI_CTL_45_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG3	0x000000000000004bLL
+#define DENALI_CTL_50_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG3	0x0000000000000000LL
+// #define DENALI_CTL_63_VAL_CFG3	0x0000000000000000LL
+// #define DENALI_CTL_64_VAL_CFG3	0x0000000000000000LL
+// #define DENALI_CTL_65_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG3	0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG3	0x00000003e8050000LL
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #4
+#define DENALI_CTL_00_VAL_CFG4	0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG4	0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG4	0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG4	0x0202020202020202LL
+// #define DENALI_CTL_04_VAL_CFG4	0x0000010100000001LL
+#define DENALI_CTL_05_VAL_CFG4	0x0003010500010001LL
+#define DENALI_CTL_06_VAL_CFG4	0x0a0a040300030300LL
+#define DENALI_CTL_07_VAL_CFG4	0x000000050000020aLL
+#define DENALI_CTL_08_VAL_CFG4	0x6400003f3f12020cLL
+#define DENALI_CTL_09_VAL_CFG4	0x0000640064006400LL
+// #define DENALI_CTL_10_VAL_CFG4	0x0120202020191a18LL
+#define DENALI_CTL_11_VAL_CFG4	0x0000002a00000000LL
+#define DENALI_CTL_12_VAL_CFG4	0x0000000000001000LL
+#define DENALI_CTL_13_VAL_CFG4	0x0010001000100010LL	
+#define DENALI_CTL_14_VAL_CFG4	0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG4	0x09e0000000000000LL
+#define DENALI_CTL_16_VAL_CFG4	0x0000000058be0000LL
+#define DENALI_CTL_17_VAL_CFG4	0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG4	0x0500010000000000LL
+#define DENALI_CTL_19_VAL_CFG4	0x00002d00c8050a00LL
+#define DENALI_CTL_20_VAL_CFG4	0x00000100fda000c8LL
+/* Original settings, pseudo synchronous */
+//#define DENALI_CTL_21_VAL_CFG4	0x0202020100000101LL
+//#define DENALI_CTL_22_VAL_CFG4	0x0000020007000002LL
+/* AHB/DDR asynchronous */
+#define DENALI_CTL_21_VAL_CFG4	0x0000000100000101LL
+#define DENALI_CTL_22_VAL_CFG4	0x0000020007000000LL
+// #define DENALI_CTL_23_VAL_CFG4
+#define DENALI_CTL_24_VAL_CFG4	0x0000000200820000LL
+#define DENALI_CTL_25_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG4	0x9440492794404927LL
+#define DENALI_CTL_27_VAL_CFG4	0x9440492794404927LL
+#define DENALI_CTL_28_VAL_CFG4	0x07c0040107c00401LL
+#define DENALI_CTL_29_VAL_CFG4	0x07c0040107c00401LL
+#define DENALI_CTL_30_VAL_CFG4	0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG4	0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG4	0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG4	0x004b4b4b4b050000LL
+#define DENALI_CTL_36_VAL_CFG4	0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG4	0x0852000000040200LL
+#define DENALI_CTL_38_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG4	0x00000000000000a3LL
+// #define DENALI_CTL_41_VAL_CFG4	0x00cc005000cc0050LL
+#define DENALI_CTL_41_VAL_CFG4	0x0016005a0016005aLL
+#define DENALI_CTL_42_VAL_CFG4	DENALI_CTL_41_VAL_CFG4
+#define DENALI_CTL_43_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_44_VAL_CFG4	DENALI_CTL_43_VAL_CFG4
+#define DENALI_CTL_45_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG4	0x0000000000000041LL
+#define DENALI_CTL_50_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG4	0x0000000000000000LL
+// #define DENALI_CTL_63_VAL_CFG4	0x0000000000000000LL
+// #define DENALI_CTL_64_VAL_CFG4	0x0000000000000000LL
+// #define DENALI_CTL_65_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG4	0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG4	0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG4	0x00000003e8050000LL
+
+#endif /* __CONFIG_H */

include/configs/c1kasic.h

diff --git a/include/configs/c1kasic.h b/include/configs/c1kasic.h
new file mode 100644
index 0000000..2e3fa4d
--- /dev/null
+++ b/include/configs/c1kasic.h
@@ -0,0 +1,667 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_1000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C1KASIC	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		DDR_BASEADDR
+#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+//#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE | GEMAC_M88E1111_PHY_RGMII_ADD_DELAY)
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		8
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE | GEMAC_M88E1111_PHY_RGMII_ADD_DELAY)
+#define GEMAC1_PHYIDX		0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_NET | /*CFG_CMD_NAND |*/ CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_ELF/*| CFG_CMD_SPI*/)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-1000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto1000\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; uload /boot/uImage; bootm\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-c1kasic\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+	"updatenandfs=tftp 81000000 ${fsfile};nand erase 60000 880000;nand write 81000000 60000 880000\0" \
+ 	"updatefs=tftp 81000000 ${fsfile};protect off 1:3-127\;erase 1:3-127;cp.b 81000000 20060000 ${filesize}\0" \
+	"updateboot=tftp 81000000 u-boot.bin;protect off 1:0-1\;erase 1:0-1;cp.b 81000000 20000000 ${filesize}\0" \
+	"eepromfile=eeprom.bin\0" \
+	"updateeprom=tftp 81000000 ${eepromfile};eeprom write 81000000 0 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+// #define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND_BASE			EXP_CS4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_CLK			CFG_CLK_650_187_375
+#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#define ADJ2_MIN_VAL     90
+#define ADJ2_MAX_VAL    150
+
+#define ADJ2_MIN_ACCEPTED_RANGE     20    /* adj2_val1: error */
+#define ADJ2_ACCEPTED_RANGE         25    /* adj2_val2: warning */
+
+#define ADJ1_MIN_VAL     1
+#define ADJ1_MAX_VAL    80
+
+#define ADJ1_MIN_ACCEPTED_WINDOW    18     /* adj1_val1: ignore */
+#define ADJ1_ACCEPTED_WINDOW        23     /* adj1_val2: warning */
+
+#define DDR_TRAINING_DBG
+
+// DDR Configs
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #1
+#define DENALI_CTL_00_VAL_CFG1   0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG1   0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG1   0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG1   0x0202020202020202LL
+#define DENALI_CTL_05_VAL_CFG1   0x0003010500010001LL
+#define DENALI_CTL_06_VAL_CFG1   0x0A0A040300030300LL
+#define DENALI_CTL_07_VAL_CFG1   0x000000050000020ALL
+#define DENALI_CTL_08_VAL_CFG1   0x6400003F3F16020ELL
+#define DENALI_CTL_09_VAL_CFG1   0x0000640064006400LL
+#define DENALI_CTL_11_VAL_CFG1   0x0000003100000000LL
+#define DENALI_CTL_12_VAL_CFG1   0x0000000000001200LL
+#define DENALI_CTL_13_VAL_CFG1   0x0010001000100010LL
+#define DENALI_CTL_14_VAL_CFG1   0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG1   0x0B60000000000000LL
+#define DENALI_CTL_16_VAL_CFG1   0x0000000066530000LL
+#define DENALI_CTL_17_VAL_CFG1   0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG1   0x0600010000000000LL
+#define DENALI_CTL_19_VAL_CFG1   0x00003400C8050B00LL
+#define DENALI_CTL_20_VAL_CFG1   0x0000010125B400C8LL
+#define DENALI_CTL_21_VAL_CFG1   0x0202020100000101LL
+#define DENALI_CTL_22_VAL_CFG1   0x0000020007000002LL
+#define DENALI_CTL_24_VAL_CFG1   0x0000000200970000LL
+#define DENALI_CTL_25_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG1   0x9400593794005937LL
+#define DENALI_CTL_27_VAL_CFG1   DENALI_CTL_26_VAL_CFG1
+#define DENALI_CTL_28_VAL_CFG1   0x07C0040107C00401LL
+#define DENALI_CTL_29_VAL_CFG1   DENALI_CTL_28_VAL_CFG1
+#define DENALI_CTL_30_VAL_CFG1   0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG1   0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG1   0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG1   0x0078787878050000LL
+#define DENALI_CTL_36_VAL_CFG1   0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG1   0x0A52000000040200LL
+#define DENALI_CTL_38_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG1   0x00000000000000c8LL
+#define DENALI_CTL_41_VAL_CFG1   0x0020138100201381LL
+#define DENALI_CTL_42_VAL_CFG1   DENALI_CTL_41_VAL_CFG1
+#define DENALI_CTL_43_VAL_CFG1   0x0000130000001300LL
+#define DENALI_CTL_44_VAL_CFG1   DENALI_CTL_43_VAL_CFG1
+#define DENALI_CTL_45_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG1   0x0000000000000050LL
+#define DENALI_CTL_50_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG1   0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG1   0x00000003e8050000LL
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #2
+#define DENALI_CTL_00_VAL_CFG2   0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG2   0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG2   0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG2   0x0202020202020202LL
+#define DENALI_CTL_05_VAL_CFG2   0x0003010300010001LL
+#define DENALI_CTL_06_VAL_CFG2   0x060A020200020200LL
+#define DENALI_CTL_07_VAL_CFG2   0x0000000300000205LL
+#define DENALI_CTL_08_VAL_CFG2   0x6400003F3F0C0208LL
+#define DENALI_CTL_09_VAL_CFG2   0x0000640064006400LL
+#define DENALI_CTL_11_VAL_CFG2   0x0000001A00000000LL
+#define DENALI_CTL_12_VAL_CFG2   0x0000000000000A00LL
+#define DENALI_CTL_13_VAL_CFG2   0x0010001000100010LL
+#define DENALI_CTL_14_VAL_CFG2   0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG2   0x0604000000000000LL
+#define DENALI_CTL_16_VAL_CFG2   0x0000000036380000LL
+#define DENALI_CTL_17_VAL_CFG2   0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG2   0x0400010000000000LL
+#define DENALI_CTL_19_VAL_CFG2   0x00001C00C8030600LL
+#define DENALI_CTL_20_VAL_CFG2   0x000001009C4000C8LL
+#define DENALI_CTL_21_VAL_CFG2   0x0303030100000101LL
+#define DENALI_CTL_22_VAL_CFG2   0x0000020007000003LL
+#define DENALI_CTL_24_VAL_CFG2   0x0000000200510000LL
+#define DENALI_CTL_25_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG2   0x9400593794005937LL
+#define DENALI_CTL_27_VAL_CFG2   DENALI_CTL_26_VAL_CFG2
+#define DENALI_CTL_28_VAL_CFG2   0x07C0040107C00401LL
+#define DENALI_CTL_29_VAL_CFG2   DENALI_CTL_28_VAL_CFG2
+#define DENALI_CTL_30_VAL_CFG2   0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG2   0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG2   0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG2   0x00E6E6E6E6030000LL
+#define DENALI_CTL_36_VAL_CFG2   0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG2   0x0632000000040200LL
+#define DENALI_CTL_38_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG2   0x00000000000000c8LL
+#define DENALI_CTL_41_VAL_CFG2   0x004B37EF004B37EFLL
+#define DENALI_CTL_42_VAL_CFG2   DENALI_CTL_41_VAL_CFG2
+#define DENALI_CTL_43_VAL_CFG2   0x0000370000003700LL
+#define DENALI_CTL_44_VAL_CFG2   DENALI_CTL_43_VAL_CFG2
+#define DENALI_CTL_45_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG2   0x0000000000000050LL
+#define DENALI_CTL_50_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG2   0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG2   0x00000003e8050000LL
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #3
+#define DENALI_CTL_00_VAL_CFG3	DENALI_CTL_00_VAL_CFG1
+#define DENALI_CTL_01_VAL_CFG3	DENALI_CTL_01_VAL_CFG1
+#define DENALI_CTL_02_VAL_CFG3	DENALI_CTL_02_VAL_CFG1
+#define DENALI_CTL_03_VAL_CFG3	DENALI_CTL_03_VAL_CFG1
+// #define DENALI_CTL_04_VAL_CFG3	DENALI_CTL_04_VAL_CFG1
+#define DENALI_CTL_05_VAL_CFG3	DENALI_CTL_05_VAL_CFG1
+#define DENALI_CTL_06_VAL_CFG3	DENALI_CTL_06_VAL_CFG1
+#define DENALI_CTL_07_VAL_CFG3	DENALI_CTL_07_VAL_CFG1
+#define DENALI_CTL_08_VAL_CFG3	0x6400003f3f15020eLL
+#define DENALI_CTL_09_VAL_CFG3	DENALI_CTL_09_VAL_CFG1
+// #define DENALI_CTL_10_VAL_CFG3	DENALI_CTL_010_VAL_CFG1
+#define DENALI_CTL_11_VAL_CFG3	0x0000003000000000LL
+#define DENALI_CTL_12_VAL_CFG3	0x0000000000000f00LL
+#define DENALI_CTL_13_VAL_CFG3	DENALI_CTL_13_VAL_CFG1	
+#define DENALI_CTL_14_VAL_CFG3	DENALI_CTL_14_VAL_CFG1
+#define DENALI_CTL_15_VAL_CFG3	0x0b50000000000000LL
+#define DENALI_CTL_16_VAL_CFG3	0x00000000659d0000LL
+#define DENALI_CTL_17_VAL_CFG3	DENALI_CTL_17_VAL_CFG1
+#define DENALI_CTL_18_VAL_CFG3	DENALI_CTL_18_VAL_CFG1
+#define DENALI_CTL_19_VAL_CFG3	0x00003400c8050b00LL
+#define DENALI_CTL_20_VAL_CFG3	0x00000101226e00c8LL
+#define DENALI_CTL_21_VAL_CFG3	DENALI_CTL_21_VAL_CFG1
+#define DENALI_CTL_22_VAL_CFG3	DENALI_CTL_22_VAL_CFG1
+// #define DENALI_CTL_23_VAL_CFG3
+#define DENALI_CTL_24_VAL_CFG3	0x0000000200950000LL
+#define DENALI_CTL_25_VAL_CFG3	DENALI_CTL_25_VAL_CFG1
+#define DENALI_CTL_26_VAL_CFG3	DENALI_CTL_26_VAL_CFG1
+#define DENALI_CTL_27_VAL_CFG3	DENALI_CTL_27_VAL_CFG1
+#define DENALI_CTL_28_VAL_CFG3	DENALI_CTL_28_VAL_CFG1
+#define DENALI_CTL_29_VAL_CFG3	DENALI_CTL_29_VAL_CFG1
+#define DENALI_CTL_30_VAL_CFG3	DENALI_CTL_30_VAL_CFG1
+#define DENALI_CTL_31_VAL_CFG3	DENALI_CTL_31_VAL_CFG1
+#define DENALI_CTL_32_VAL_CFG3	DENALI_CTL_32_VAL_CFG1
+#define DENALI_CTL_33_VAL_CFG3	DENALI_CTL_33_VAL_CFG1
+#define DENALI_CTL_34_VAL_CFG3	DENALI_CTL_34_VAL_CFG1
+#define DENALI_CTL_35_VAL_CFG3	0x003a3a3a3a030000LL
+#define DENALI_CTL_36_VAL_CFG3	DENALI_CTL_36_VAL_CFG1
+#define DENALI_CTL_37_VAL_CFG3	DENALI_CTL_37_VAL_CFG1
+#define DENALI_CTL_38_VAL_CFG3	DENALI_CTL_38_VAL_CFG1
+#define DENALI_CTL_39_VAL_CFG3	DENALI_CTL_39_VAL_CFG1
+#define DENALI_CTL_40_VAL_CFG3	0x00000000000000baLL
+#define DENALI_CTL_41_VAL_CFG3	0x001a0050001a0050LL
+#define DENALI_CTL_42_VAL_CFG3	DENALI_CTL_41_VAL_CFG3
+#define DENALI_CTL_43_VAL_CFG3	DENALI_CTL_43_VAL_CFG1
+#define DENALI_CTL_44_VAL_CFG3	DENALI_CTL_44_VAL_CFG1
+#define DENALI_CTL_45_VAL_CFG3	DENALI_CTL_45_VAL_CFG1
+#define DENALI_CTL_46_VAL_CFG3	DENALI_CTL_46_VAL_CFG1
+#define DENALI_CTL_47_VAL_CFG3	DENALI_CTL_47_VAL_CFG1
+#define DENALI_CTL_48_VAL_CFG3	DENALI_CTL_48_VAL_CFG1
+#define DENALI_CTL_49_VAL_CFG3	0x000000000000004bLL
+#define DENALI_CTL_50_VAL_CFG3	DENALI_CTL_50_VAL_CFG1
+#define DENALI_CTL_51_VAL_CFG3	DENALI_CTL_51_VAL_CFG1
+#define DENALI_CTL_52_VAL_CFG3	DENALI_CTL_52_VAL_CFG1
+#define DENALI_CTL_53_VAL_CFG3	DENALI_CTL_53_VAL_CFG1
+#define DENALI_CTL_54_VAL_CFG3	DENALI_CTL_54_VAL_CFG1
+#define DENALI_CTL_55_VAL_CFG3	DENALI_CTL_55_VAL_CFG1
+#define DENALI_CTL_56_VAL_CFG3	DENALI_CTL_56_VAL_CFG1
+#define DENALI_CTL_57_VAL_CFG3	DENALI_CTL_57_VAL_CFG1
+#define DENALI_CTL_58_VAL_CFG3	DENALI_CTL_58_VAL_CFG1
+#define DENALI_CTL_59_VAL_CFG3	DENALI_CTL_59_VAL_CFG1
+#define DENALI_CTL_60_VAL_CFG3	DENALI_CTL_60_VAL_CFG1
+#define DENALI_CTL_61_VAL_CFG3	DENALI_CTL_61_VAL_CFG1
+#define DENALI_CTL_62_VAL_CFG3	DENALI_CTL_62_VAL_CFG1
+// #define DENALI_CTL_63_VAL_CFG3	DENALI_CTL_63_VAL_CFG1
+// #define DENALI_CTL_64_VAL_CFG3	DENALI_CTL_64_VAL_CFG1
+// #define DENALI_CTL_65_VAL_CFG3	DENALI_CTL_65_VAL_CFG1
+#define DENALI_CTL_66_VAL_CFG3	DENALI_CTL_66_VAL_CFG1
+#define DENALI_CTL_67_VAL_CFG3	DENALI_CTL_67_VAL_CFG1
+#define DENALI_CTL_68_VAL_CFG3	DENALI_CTL_68_VAL_CFG1
+#define DENALI_CTL_69_VAL_CFG3	DENALI_CTL_69_VAL_CFG1
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #4
+#define DENALI_CTL_00_VAL_CFG4   0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG4   0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG4   0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG4   0x0202020202020202LL
+#define DENALI_CTL_05_VAL_CFG4   0x0003010500010001LL
+#define DENALI_CTL_06_VAL_CFG4   0x0A0A040300030300LL
+#define DENALI_CTL_07_VAL_CFG4   0x000000050000020ALL
+#define DENALI_CTL_08_VAL_CFG4   0x6400003F3F13020CLL
+#define DENALI_CTL_09_VAL_CFG4   0x0000640064006400LL
+#define DENALI_CTL_11_VAL_CFG4   0x0000002A00000000LL
+#define DENALI_CTL_12_VAL_CFG4   0x0000000000000F00LL
+#define DENALI_CTL_13_VAL_CFG4   0x0010001000100010LL
+#define DENALI_CTL_14_VAL_CFG4   0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG4   0x09D8000000000000LL
+#define DENALI_CTL_16_VAL_CFG4   0x0000000058990000LL
+#define DENALI_CTL_17_VAL_CFG4   0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG4   0x0500010000000000LL
+#define DENALI_CTL_19_VAL_CFG4   0x00002D00C8050A00LL
+#define DENALI_CTL_20_VAL_CFG4   0x00000100FE7B00C8LL
+#define DENALI_CTL_21_VAL_CFG4   0x0000000100000101LL
+#define DENALI_CTL_22_VAL_CFG4   0x0000020007000000LL
+#define DENALI_CTL_24_VAL_CFG4   0x0000000200830000LL
+#define DENALI_CTL_25_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG4   0x9400593794005937LL
+#define DENALI_CTL_27_VAL_CFG4   DENALI_CTL_26_VAL_CFG4
+#define DENALI_CTL_28_VAL_CFG4   0x07C0040107C00401LL
+#define DENALI_CTL_29_VAL_CFG4   DENALI_CTL_28_VAL_CFG4
+#define DENALI_CTL_30_VAL_CFG4   0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG4   0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG4   0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG4   0x0087878787040000LL
+#define DENALI_CTL_36_VAL_CFG4   0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG4   0x0852000000040200LL
+#define DENALI_CTL_38_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG4   0x00000000000000c8LL
+#define DENALI_CTL_41_VAL_CFG4   0x0024199300241993LL
+#define DENALI_CTL_42_VAL_CFG4   DENALI_CTL_41_VAL_CFG4
+#define DENALI_CTL_43_VAL_CFG4   0x0000190000001900LL
+#define DENALI_CTL_44_VAL_CFG4   DENALI_CTL_43_VAL_CFG4
+#define DENALI_CTL_00_VAL_CFG4   0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG4   0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG4   0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG4   0x0202020202020202LL
+#define DENALI_CTL_05_VAL_CFG4   0x0003010500010001LL
+#define DENALI_CTL_06_VAL_CFG4   0x0A0A040300030300LL
+#define DENALI_CTL_07_VAL_CFG4   0x000000050000020ALL
+#define DENALI_CTL_08_VAL_CFG4   0x6400003F3F13020CLL
+#define DENALI_CTL_09_VAL_CFG4   0x0000640064006400LL
+#define DENALI_CTL_11_VAL_CFG4   0x0000002A00000000LL
+#define DENALI_CTL_12_VAL_CFG4   0x0000000000000F00LL
+#define DENALI_CTL_13_VAL_CFG4   0x0010001000100010LL
+#define DENALI_CTL_14_VAL_CFG4   0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG4   0x09D8000000000000LL
+#define DENALI_CTL_16_VAL_CFG4   0x0000000058990000LL
+#define DENALI_CTL_17_VAL_CFG4   0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG4   0x0500010000000000LL
+#define DENALI_CTL_19_VAL_CFG4   0x00002D00C8050A00LL
+#define DENALI_CTL_20_VAL_CFG4   0x00000100FE7B00C8LL
+#define DENALI_CTL_21_VAL_CFG4   0x0000000100000101LL
+#define DENALI_CTL_22_VAL_CFG4   0x0000020007000000LL
+#define DENALI_CTL_24_VAL_CFG4   0x0000000200830000LL
+#define DENALI_CTL_25_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG4   0x9400593794005937LL
+#define DENALI_CTL_27_VAL_CFG4   DENALI_CTL_26_VAL_CFG4
+#define DENALI_CTL_28_VAL_CFG4   0x07C0040107C00401LL
+#define DENALI_CTL_29_VAL_CFG4   DENALI_CTL_28_VAL_CFG4
+#define DENALI_CTL_30_VAL_CFG4   0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG4   0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG4   0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG4   0x0087878787040000LL
+#define DENALI_CTL_36_VAL_CFG4   0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG4   0x0852000000040200LL
+#define DENALI_CTL_38_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG4   0x00000000000000c8LL
+#define DENALI_CTL_41_VAL_CFG4   0x0024199300241993LL
+#define DENALI_CTL_42_VAL_CFG4   DENALI_CTL_41_VAL_CFG4
+#define DENALI_CTL_43_VAL_CFG4   0x0000190000001900LL
+#define DENALI_CTL_44_VAL_CFG4   DENALI_CTL_43_VAL_CFG4
+#define DENALI_CTL_45_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG4   0x0000000000000050LL
+#define DENALI_CTL_50_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG4   0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG4   0x00000003e8050000LL
+
+#endif /* __CONFIG_H */

include/configs/c1kasic_aram.h

diff --git a/include/configs/c1kasic_aram.h b/include/configs/c1kasic_aram.h
new file mode 100644
index 0000000..5764845
--- /dev/null
+++ b/include/configs/c1kasic_aram.h
@@ -0,0 +1,591 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_1000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C1KASIC	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		DDR_BASEADDR
+#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#undef CONFIG_COMCERTO_GEMAC
+
+// GEMAC mode configured by bootstrap pins or SW
+//#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE | GEMAC_M88E1111_PHY_RGMII_ADD_DELAY)
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		8
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE | GEMAC_M88E1111_PHY_RGMII_ADD_DELAY)
+#define GEMAC1_PHYIDX		0
+
+#undef CONFIG_NET_MULTI
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN)
+
+//#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-1000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+// #define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND_BASE			EXP_CS4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_CLK			CFG_CLK_650_187_375
+#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x0001A000 /* 104K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 4 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(2 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#define ADJ2_MIN_VAL     90
+#define ADJ2_MAX_VAL    150
+
+#define ADJ2_MIN_ACCEPTED_RANGE     20    /* adj2_val1: error */
+#define ADJ2_ACCEPTED_RANGE         25    /* adj2_val2: warning */
+
+#define ADJ1_MIN_VAL     1
+#define ADJ1_MAX_VAL    80
+
+#define ADJ1_MIN_ACCEPTED_WINDOW    18     /* adj1_val1: ignore */
+#define ADJ1_ACCEPTED_WINDOW        23     /* adj1_val2: warning */
+
+// DDR Configs
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #1
+#define DENALI_CTL_00_VAL_CFG1   0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG1   0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG1   0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG1   0x0202020202020202LL
+#define DENALI_CTL_05_VAL_CFG1   0x0003010500010001LL
+#define DENALI_CTL_06_VAL_CFG1   0x0A0A040300030300LL
+#define DENALI_CTL_07_VAL_CFG1   0x000000050000020ALL
+#define DENALI_CTL_08_VAL_CFG1   0x6400003F3F16020ELL
+#define DENALI_CTL_09_VAL_CFG1   0x0000640064006400LL
+#define DENALI_CTL_11_VAL_CFG1   0x0000003100000000LL
+#define DENALI_CTL_12_VAL_CFG1   0x0000000000001200LL
+#define DENALI_CTL_13_VAL_CFG1   0x0010001000100010LL
+#define DENALI_CTL_14_VAL_CFG1   0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG1   0x0B60000000000000LL
+#define DENALI_CTL_16_VAL_CFG1   0x0000000066530000LL
+#define DENALI_CTL_17_VAL_CFG1   0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG1   0x0600010000000000LL
+#define DENALI_CTL_19_VAL_CFG1   0x00003400C8050B00LL
+#define DENALI_CTL_20_VAL_CFG1   0x0000010125B400C8LL
+#define DENALI_CTL_21_VAL_CFG1   0x0202020100000101LL
+#define DENALI_CTL_22_VAL_CFG1   0x0000020007000002LL
+#define DENALI_CTL_24_VAL_CFG1   0x0000000200970000LL
+#define DENALI_CTL_25_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG1   0x9400593794005937LL
+#define DENALI_CTL_27_VAL_CFG1   DENALI_CTL_26_VAL_CFG1
+#define DENALI_CTL_28_VAL_CFG1   0x07C0040107C00401LL
+#define DENALI_CTL_29_VAL_CFG1   DENALI_CTL_28_VAL_CFG1
+#define DENALI_CTL_30_VAL_CFG1   0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG1   0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG1   0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG1   0x0078787878050000LL
+#define DENALI_CTL_36_VAL_CFG1   0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG1   0x0A52000000040200LL
+#define DENALI_CTL_38_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG1   0x00000000000000c8LL
+#define DENALI_CTL_41_VAL_CFG1   0x0020138100201381LL
+#define DENALI_CTL_42_VAL_CFG1   DENALI_CTL_41_VAL_CFG1
+#define DENALI_CTL_43_VAL_CFG1   0x0000130000001300LL
+#define DENALI_CTL_44_VAL_CFG1   DENALI_CTL_43_VAL_CFG1
+#define DENALI_CTL_45_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG1   0x0000000000000050LL
+#define DENALI_CTL_50_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG1   0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG1   0x00000003e8050000LL
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #2
+#define DENALI_CTL_00_VAL_CFG2   0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG2   0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG2   0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG2   0x0202020202020202LL
+#define DENALI_CTL_05_VAL_CFG2   0x0003010300010001LL
+#define DENALI_CTL_06_VAL_CFG2   0x060A020200020200LL
+#define DENALI_CTL_07_VAL_CFG2   0x0000000300000205LL
+#define DENALI_CTL_08_VAL_CFG2   0x6400003F3F0C0208LL
+#define DENALI_CTL_09_VAL_CFG2   0x0000640064006400LL
+#define DENALI_CTL_11_VAL_CFG2   0x0000001A00000000LL
+#define DENALI_CTL_12_VAL_CFG2   0x0000000000000A00LL
+#define DENALI_CTL_13_VAL_CFG2   0x0010001000100010LL
+#define DENALI_CTL_14_VAL_CFG2   0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG2   0x0604000000000000LL
+#define DENALI_CTL_16_VAL_CFG2   0x0000000036380000LL
+#define DENALI_CTL_17_VAL_CFG2   0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG2   0x0400010000000000LL
+#define DENALI_CTL_19_VAL_CFG2   0x00001C00C8030600LL
+#define DENALI_CTL_20_VAL_CFG2   0x000001009C4000C8LL
+#define DENALI_CTL_21_VAL_CFG2   0x0303030100000101LL
+#define DENALI_CTL_22_VAL_CFG2   0x0000020007000003LL
+#define DENALI_CTL_24_VAL_CFG2   0x0000000200510000LL
+#define DENALI_CTL_25_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG2   0x9400593794005937LL
+#define DENALI_CTL_27_VAL_CFG2   DENALI_CTL_26_VAL_CFG2
+#define DENALI_CTL_28_VAL_CFG2   0x07C0040107C00401LL
+#define DENALI_CTL_29_VAL_CFG2   DENALI_CTL_28_VAL_CFG2
+#define DENALI_CTL_30_VAL_CFG2   0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG2   0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG2   0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG2   0x00E6E6E6E6030000LL
+#define DENALI_CTL_36_VAL_CFG2   0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG2   0x0632000000040200LL
+#define DENALI_CTL_38_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG2   0x00000000000000c8LL
+#define DENALI_CTL_41_VAL_CFG2   0x004B37EF004B37EFLL
+#define DENALI_CTL_42_VAL_CFG2   DENALI_CTL_41_VAL_CFG2
+#define DENALI_CTL_43_VAL_CFG2   0x0000370000003700LL
+#define DENALI_CTL_44_VAL_CFG2   DENALI_CTL_43_VAL_CFG2
+#define DENALI_CTL_45_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG2   0x0000000000000050LL
+#define DENALI_CTL_50_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG2   0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG2   0x00000003e8050000LL
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #3
+#define DENALI_CTL_00_VAL_CFG3	0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG3	0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG3	0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG3	0x0202020202020202LL
+// #define DENALI_CTL_04_VAL_CFG3	0x0000010100000001LL
+#define DENALI_CTL_05_VAL_CFG3	0x0003010500010001LL
+#define DENALI_CTL_06_VAL_CFG3	0x0a0a040300030300LL
+#define DENALI_CTL_07_VAL_CFG3	0x000000050000020aLL
+#define DENALI_CTL_08_VAL_CFG3	0x6400003f3f15020eLL
+#define DENALI_CTL_09_VAL_CFG3	0x0000640064006400LL
+// #define DENALI_CTL_10_VAL_CFG3	0x0120202020191a18LL
+#define DENALI_CTL_11_VAL_CFG3	0x0000003000000000LL
+#define DENALI_CTL_12_VAL_CFG3	0x0000000000000f00LL
+#define DENALI_CTL_13_VAL_CFG3	0x0010001000100010LL	
+#define DENALI_CTL_14_VAL_CFG3	0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG3	0x0b50000000000000LL
+#define DENALI_CTL_16_VAL_CFG3	0x00000000659d0000LL
+#define DENALI_CTL_17_VAL_CFG3	0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG3	0x0600010000000000LL
+#define DENALI_CTL_19_VAL_CFG3	0x00003400c8050b00LL
+#define DENALI_CTL_20_VAL_CFG3	0x00000101226e00c8LL
+/* Original settings, AHB/DDR synchronous */
+#define DENALI_CTL_21_VAL_CFG3	0x0202020100000101LL
+#define DENALI_CTL_22_VAL_CFG3	0x0000020007000002LL
+/* AHB/DDR asynchronous */
+//#define DENALI_CTL_21_VAL_CFG3	0x0000000100000101LL
+//#define DENALI_CTL_22_VAL_CFG3	0x0000020007000000LL
+// #define DENALI_CTL_23_VAL_CFG3
+#define DENALI_CTL_24_VAL_CFG3	0x0000000200950000LL
+#define DENALI_CTL_25_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG3	0x9440492794404927LL
+#define DENALI_CTL_27_VAL_CFG3	0x9440492794404927LL
+#define DENALI_CTL_28_VAL_CFG3	0x07c0040107c00401LL
+#define DENALI_CTL_29_VAL_CFG3	0x07c0040107c00401LL
+#define DENALI_CTL_30_VAL_CFG3	0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG3	0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG3	0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG3	0x003a3a3a3a050000LL
+#define DENALI_CTL_36_VAL_CFG3	0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG3	0x0a52000000040200LL
+#define DENALI_CTL_38_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG3	0x00000000000000baLL
+// #define DENALI_CTL_41_VAL_CFG3	0x00cc005000cc0050LL
+#define DENALI_CTL_41_VAL_CFG3	0x001a0050001a0050LL
+#define DENALI_CTL_42_VAL_CFG3	DENALI_CTL_41_VAL_CFG3
+#define DENALI_CTL_43_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_44_VAL_CFG3	DENALI_CTL_43_VAL_CFG3
+#define DENALI_CTL_45_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG3	0x000000000000004bLL
+#define DENALI_CTL_50_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG3	0x0000000000000000LL
+// #define DENALI_CTL_63_VAL_CFG3	0x0000000000000000LL
+// #define DENALI_CTL_64_VAL_CFG3	0x0000000000000000LL
+// #define DENALI_CTL_65_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG3	0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG3	0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG3	0x00000003e8050000LL
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #4
+#define DENALI_CTL_00_VAL_CFG4   0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG4   0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG4   0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG4   0x0202020202020202LL
+#define DENALI_CTL_05_VAL_CFG4   0x0003010500010001LL
+#define DENALI_CTL_06_VAL_CFG4   0x0A0A040300030300LL
+#define DENALI_CTL_07_VAL_CFG4   0x000000050000020ALL
+#define DENALI_CTL_08_VAL_CFG4   0x6400003F3F13020CLL
+#define DENALI_CTL_09_VAL_CFG4   0x0000640064006400LL
+#define DENALI_CTL_11_VAL_CFG4   0x0000002A00000000LL
+#define DENALI_CTL_12_VAL_CFG4   0x0000000000000F00LL
+#define DENALI_CTL_13_VAL_CFG4   0x0010001000100010LL
+#define DENALI_CTL_14_VAL_CFG4   0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG4   0x09D8000000000000LL
+#define DENALI_CTL_16_VAL_CFG4   0x0000000058990000LL
+#define DENALI_CTL_17_VAL_CFG4   0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG4   0x0500010000000000LL
+#define DENALI_CTL_19_VAL_CFG4   0x00002D00C8050A00LL
+#define DENALI_CTL_20_VAL_CFG4   0x00000100FE7B00C8LL
+#define DENALI_CTL_21_VAL_CFG4   0x0000000100000101LL
+#define DENALI_CTL_22_VAL_CFG4   0x0000020007000000LL
+#define DENALI_CTL_24_VAL_CFG4   0x0000000200830000LL
+#define DENALI_CTL_25_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG4   0x9400593794005937LL
+#define DENALI_CTL_27_VAL_CFG4   DENALI_CTL_26_VAL_CFG4
+#define DENALI_CTL_28_VAL_CFG4   0x07C0040107C00401LL
+#define DENALI_CTL_29_VAL_CFG4   DENALI_CTL_28_VAL_CFG4
+#define DENALI_CTL_30_VAL_CFG4   0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG4   0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG4   0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG4   0x0087878787040000LL
+#define DENALI_CTL_36_VAL_CFG4   0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG4   0x0852000000040200LL
+#define DENALI_CTL_38_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG4   0x00000000000000c8LL
+#define DENALI_CTL_41_VAL_CFG4   0x0024199300241993LL
+#define DENALI_CTL_42_VAL_CFG4   DENALI_CTL_41_VAL_CFG4
+#define DENALI_CTL_43_VAL_CFG4   0x0000190000001900LL
+#define DENALI_CTL_44_VAL_CFG4   DENALI_CTL_43_VAL_CFG4
+#define DENALI_CTL_45_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG4   0x0000000000000050LL
+#define DENALI_CTL_50_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG4   0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG4   0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG4   0x00000003e8050000LL
+
+#endif /* __CONFIG_H */

include/configs/c1kevm-nand.h

diff --git a/include/configs/c1kevm-nand.h b/include/configs/c1kevm-nand.h
new file mode 100644
index 0000000..77f4d53
--- /dev/null
+++ b/include/configs/c1kevm-nand.h
@@ -0,0 +1,338 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_1000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C1KEVM	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		DDR_BASEADDR
+#define PHYS_SDRAM_SIZE		0x10000000	/* 256 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0	//not used
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	(GEMAC_NO_PHY | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC1_PHYIDX		0	//not used
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(/*CFG_CMD_FLASH |*/ CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_NET | CFG_CMD_NAND | CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_ELF/*| CFG_CMD_SPI*/)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-1000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto1000\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root="ROOT_MTDBLOCK" rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; uload /boot/uImage; bootm\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-c1kevm\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+        "bootfile=u-boot-nand.bin\0"\
+	"updatenandfs=tftp 85000000 ${fsfile};nand erase 60000 ${filesize};nand write.jffs2 85000000 60000 ${filesize}\0" \
+        "updatenandboot=tftp 81000000 ${bootfile};nand erase 0 40000;nand write.jffs2 81000000 0 40000\0" \
+	"eepromfile=eeprom.bin\0" \
+	"updateeprom=tftp 81000000 ${eepromfile};eeprom write 81000000 0 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+// #define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND_BASE			EXP_CS4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#endif /* __CONFIG_H */

include/configs/c1kevm.h

diff --git a/include/configs/c1kevm.h b/include/configs/c1kevm.h
new file mode 100644
index 0000000..ea038e2
--- /dev/null
+++ b/include/configs/c1kevm.h
@@ -0,0 +1,341 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_1000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C1KEVM	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		DDR_BASEADDR
+#define PHYS_SDRAM_SIZE		0x10000000	/* 256 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0	//not used
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	(GEMAC_NO_PHY | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC1_PHYIDX		0	//not used
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_NET   /* | CFG_CMD_NAND */ | CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_ELF/*| CFG_CMD_SPI*/)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-1000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto1000\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+    "boot_flash=run flashargs addeth addtty addmtd; uload /boot/uImage; bootm\0" \
+    "boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-c1kevm\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+	"updatenandfs=tftp 81000000 ${fsfile};nand erase 60000 880000;nand write 81000000 60000 880000\0" \
+ 	"updatefs=tftp 81000000 ${fsfile};protect off 1:3-127\;erase 1:3-127;cp.b 81000000 20060000 ${filesize}\0" \
+	"updateboot=tftp 81000000 u-boot.bin;protect off 1:0-1\;erase 1:0-1;cp.b 81000000 20000000 ${filesize}\0" \
+	"eepromfile=eeprom.bin\0" \
+	"updateeprom=tftp 81000000 ${eepromfile};eeprom write 81000000 0 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+// #define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND_BASE			EXP_CS4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+#define DDR_TRAINING_DBG
+
+
+
+#endif /* __CONFIG_H */

include/configs/c1kevm_aram.h

diff --git a/include/configs/c1kevm_aram.h b/include/configs/c1kevm_aram.h
new file mode 100644
index 0000000..2fa659a
--- /dev/null
+++ b/include/configs/c1kevm_aram.h
@@ -0,0 +1,303 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_1000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C1KEVM	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		DDR_BASEADDR
+#define PHYS_SDRAM_SIZE		0x10000000	/* 256 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#undef CONFIG_COMCERTO_GEMAC
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0	//not used
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	(GEMAC_NO_PHY | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC1_PHYIDX		0	//not used
+
+#undef CONFIG_NET_MULTI
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN)
+
+//#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-1000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+// #define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND_BASE			EXP_CS4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x0001A000 /* 104K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 4 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(2 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+
+
+#endif /* __CONFIG_H */

include/configs/c1km83240-nand.h

diff --git a/include/configs/c1km83240-nand.h b/include/configs/c1km83240-nand.h
new file mode 100644
index 0000000..3b594df
--- /dev/null
+++ b/include/configs/c1km83240-nand.h
@@ -0,0 +1,343 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_1000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C1KM83240	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		DDR_BASEADDR
+#define PHYS_SDRAM_SIZE		0x8000000	/* 128 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0	//not used
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	(GEMAC_NO_PHY | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC1_PHYIDX		0	//not used
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(/*CFG_CMD_FLASH |*/ CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_NET | CFG_CMD_NAND | CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS |CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_ELF/*| CFG_CMD_SPI*/)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-1000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS               \
+    "hostname=comcerto1000\0"                       \
+    "netdev=eth0\0"                                 \
+    "nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "        \
+        "nfsroot=${serverip}:${rootpath}\0"             \
+    "flashargs=setenv bootargs init=${init_process} root="ROOT_MTDBLOCK" rootfstype=${rootfstype} rw\0"  \
+    "rootfstype=jffs2\0" \
+    "init_process=/etc/preinit\0" \
+    "addip=setenv bootargs ${bootargs} "                \
+        "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"  \
+        ":${hostname}:${netdev}:off\0" \
+    "addeth=setenv bootargs ${bootargs} " \
+    "hwaddress=${netdev},${ethaddr}\0" \
+    "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+    "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+    "flash_self=run flashargs addip addtty;"        \
+        "bootm ${kernel_addr}\0"                \
+    "boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+            "bootm 80600000\0"                      \
+    "boot_flash=run flashargs addeth addtty addmtd; uload /boot/uImage; bootm\0" \
+    "boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+    "rootpath=/devel/fs-c1km83240\0" \
+    "kernelfile=uImage\0" \
+    "mtdids=" MTDIDS_DEFAULT "\0" \
+    "mtdparts=" MTDPARTS_DEFAULT "\0" \
+    "partition=" MTDPARTITION_DEFAULT "\0" \
+    "mtddevnum=2\0" \
+    "mtddevname=fs\0" \
+    "fsfile=root.jffs2-128k\0" \
+        "bootfile=u-boot-nand.bin\0"\
+    "updatenandfs=tftp 81000000 ${fsfile};nand erase 60000 ${filesize};nand write.jffs2 81000000 60000 ${filesize}\0" \
+        "updatenandboot=tftp 81000000 ${bootfile};nand erase 0 40000;nand write.jffs2 81000000 0 40000\0" \
+	"eepromfile=eeprom.bin\0" \
+	"updateeprom=tftp 81000000 ${eepromfile};eeprom write 81000000 0 ${filesize}\0" \
+    ""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+// #define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND_BASE			EXP_CS4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),32384k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),32384k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+
+#define CFG_DDR_16BIT		1
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+#define DDR_TRAINING_DBG
+
+
+
+#endif /* __CONFIG_H */

include/configs/c1km83240.h

diff --git a/include/configs/c1km83240.h b/include/configs/c1km83240.h
new file mode 100644
index 0000000..3f80837
--- /dev/null
+++ b/include/configs/c1km83240.h
@@ -0,0 +1,343 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_1000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C1KM83240	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		DDR_BASEADDR
+#define PHYS_SDRAM_SIZE		0x8000000	/* 128 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0	//not used
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	(GEMAC_NO_PHY | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC1_PHYIDX		0	//not used
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_NET   /* | CFG_CMD_NAND */ | CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_ELF/*| CFG_CMD_SPI*/)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-1000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto1000\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; uload /boot/uImage; bootm\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-c1km83240\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+	"updatenandfs=tftp 81000000 ${fsfile};nand erase 60000 880000;nand write 81000000 60000 880000\0" \
+ 	"updatefs=tftp 81000000 ${fsfile};protect off 1:3-255\;erase 1:3-255;cp.b 81000000 20060000 ${filesize}\0" \
+	"updateboot=tftp 81000000 u-boot.bin;protect off 1:0-1\;erase 1:0-1;cp.b 81000000 20000000 ${filesize}\0" \
+	"eepromfile=eeprom.bin\0" \
+	"updateeprom=tftp 81000000 ${eepromfile};eeprom write 81000000 0 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+// #define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND_BASE			EXP_CS4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),32384k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),32384k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+
+#define CFG_DDR_16BIT		1
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+#define DDR_TRAINING_DBG
+
+
+
+#endif /* __CONFIG_H */

include/configs/c1km83240_aram.h

diff --git a/include/configs/c1km83240_aram.h b/include/configs/c1km83240_aram.h
new file mode 100644
index 0000000..e44edcd
--- /dev/null
+++ b/include/configs/c1km83240_aram.h
@@ -0,0 +1,305 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_1000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C1KM83240	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		DDR_BASEADDR
+#define PHYS_SDRAM_SIZE		0x8000000	/* 128 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#undef CONFIG_COMCERTO_GEMAC
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0	//not used
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	(GEMAC_NO_PHY | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC1_PHYIDX		0	//not used
+
+#undef CONFIG_NET_MULTI
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN)
+
+//#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-1000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+// #define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND_BASE			EXP_CS4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),32384k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),32384k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+
+#define CFG_DDR_16BIT		1
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x0001A000 /* 104K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 4 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(2 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+
+
+#endif /* __CONFIG_H */

include/configs/c1kmfcn-evm-nand.h

diff --git a/include/configs/c1kmfcn-evm-nand.h b/include/configs/c1kmfcn-evm-nand.h
new file mode 100644
index 0000000..6ad38f9
--- /dev/null
+++ b/include/configs/c1kmfcn-evm-nand.h
@@ -0,0 +1,341 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_1000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C1KMFCN_EVM	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		DDR_BASEADDR
+#define PHYS_SDRAM_SIZE		0x10000000	/* 256 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0	//not used
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	(GEMAC_NO_PHY | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC1_PHYIDX		0	//not used
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(/*CFG_CMD_FLASH |*/ CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_NET | CFG_CMD_NAND | CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS |CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_ELF/*| CFG_CMD_SPI*/)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-1000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS               \
+    "hostname=comcerto1000\0"                       \
+    "netdev=eth0\0"                                 \
+    "nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "        \
+        "nfsroot=${serverip}:${rootpath}\0"             \
+    "flashargs=setenv bootargs init=${init_process} root="ROOT_MTDBLOCK" rootfstype=${rootfstype} rw\0"  \
+    "rootfstype=jffs2\0" \
+    "init_process=/etc/preinit\0" \
+    "addip=setenv bootargs ${bootargs} "                \
+        "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"  \
+        ":${hostname}:${netdev}:off\0" \
+    "addeth=setenv bootargs ${bootargs} " \
+    "hwaddress=${netdev},${ethaddr}\0" \
+    "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+    "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+    "flash_self=run flashargs addip addtty;"        \
+        "bootm ${kernel_addr}\0"                \
+    "boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+            "bootm 80600000\0"                      \
+    "boot_flash=run flashargs addeth addtty addmtd; uload /boot/uImage; bootm\0" \
+    "boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+    "rootpath=/devel/fs-c1kmfcn-evm\0" \
+    "kernelfile=uImage\0" \
+    "mtdids=" MTDIDS_DEFAULT "\0" \
+    "mtdparts=" MTDPARTS_DEFAULT "\0" \
+    "partition=" MTDPARTITION_DEFAULT "\0" \
+    "mtddevnum=2\0" \
+    "mtddevname=fs\0" \
+    "fsfile=root.jffs2-128k\0" \
+        "bootfile=u-boot-nand.bin\0"\
+    "updatenandfs=tftp 85000000 ${fsfile};nand erase 60000 ${filesize};nand write.jffs2 85000000 60000 ${filesize}\0" \
+        "updatenandboot=tftp 81000000 ${bootfile};nand erase 0 40000;nand write.jffs2 81000000 0 40000\0" \
+	"eepromfile=eeprom.bin\0" \
+	"updateeprom=tftp 81000000 ${eepromfile};eeprom write 81000000 0 ${filesize}\0" \
+    ""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+// #define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND_BASE			EXP_CS4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+#define DDR_TRAINING_DBG
+
+
+
+#endif /* __CONFIG_H */

include/configs/c1kmfcn-evm.h

diff --git a/include/configs/c1kmfcn-evm.h b/include/configs/c1kmfcn-evm.h
new file mode 100644
index 0000000..b4450c4
--- /dev/null
+++ b/include/configs/c1kmfcn-evm.h
@@ -0,0 +1,341 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_1000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C1KMFCN_EVM	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		DDR_BASEADDR
+#define PHYS_SDRAM_SIZE		0x10000000	/* 256 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0	//not used
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	(GEMAC_NO_PHY | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC1_PHYIDX		0	//not used
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_NET   /* | CFG_CMD_NAND */ | CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_ELF/*| CFG_CMD_SPI*/)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-1000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto1000\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; uload /boot/uImage; bootm\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-c1kmfcn-evm\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+	"updatenandfs=tftp 81000000 ${fsfile};nand erase 60000 880000;nand write 81000000 60000 880000\0" \
+ 	"updatefs=tftp 81000000 ${fsfile};protect off 1:3-127\;erase 1:3-127;cp.b 81000000 20060000 ${filesize}\0" \
+	"updateboot=tftp 81000000 u-boot.bin;protect off 1:0-1\;erase 1:0-1;cp.b 81000000 20000000 ${filesize}\0" \
+	"eepromfile=eeprom.bin\0" \
+	"updateeprom=tftp 81000000 ${eepromfile};eeprom write 81000000 0 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+// #define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND_BASE			EXP_CS4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+#define DDR_TRAINING_DBG
+
+
+
+#endif /* __CONFIG_H */

include/configs/c1kmfcn-evm_aram.h

diff --git a/include/configs/c1kmfcn-evm_aram.h b/include/configs/c1kmfcn-evm_aram.h
new file mode 100644
index 0000000..ff5bad8
--- /dev/null
+++ b/include/configs/c1kmfcn-evm_aram.h
@@ -0,0 +1,303 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_1000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C1KMFCN_EVM	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		DDR_BASEADDR
+#define PHYS_SDRAM_SIZE		0x10000000	/* 256 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#undef CONFIG_COMCERTO_GEMAC
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	(GEMAC_PHY_AUTONEG | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0	//not used
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	(GEMAC_NO_PHY | GEMAC_GEM_DELAY_DISABLE)
+#define GEMAC1_PHYIDX		0	//not used
+
+#undef CONFIG_NET_MULTI
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN)
+
+//#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-1000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+// #define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND_BASE			EXP_CS4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x0001A000 /* 104K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 4 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(2 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+
+
+#endif /* __CONFIG_H */

include/configs/c2kasic-nand.h

diff --git a/include/configs/c2kasic-nand.h b/include/configs/c2kasic-nand.h
new file mode 100644
index 0000000..15fe277
--- /dev/null
+++ b/include/configs/c2kasic-nand.h
@@ -0,0 +1,407 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARMV7 		1
+#define CONFIG_COMCERTO_2000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C2KASIC	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#define	CONFIG_ARM_EXCEPTIONS	1
+#define	CONFIG_ARCH_HAS_LOWLEVEL_INIT	1
+#define	CONFIG_MMU	1
+#define CFG_HZ_CLOCK          250000000
+#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
+
+#define CPU_3XX_ES20            1
+#define	CMD_SAVEENV	1
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		COMCERTO_AXI_DDR_BASE
+#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Gemac Settings
+ */
+#define EMAC0_PHY_ADDR  4
+#define EMAC1_PHY_ADDR  5
+#define EMAC0_FLAGS     0
+#define EMAC1_FLAGS     0 
+#define EMAC2_FLAGS     0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV  | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII  | CFG_CMD_RUN | CFG_CMD_NET | CFG_CMD_NAND | CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS  | CFG_CMD_I2C | CFG_CMD_EEPROM /*| CFG_CMD_ELF| CFG_CMD_SPI*/)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-2000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto2000\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock4 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,115200n8\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; bootm 0xc0080000\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-c2kasic\0" \
+	"kernelfile=uImage\0" \
+	"bootfile=u-boot.bin\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+ 	"updatefs=tftp 3000000 ${fsfile};protect off 1:35-127\;erase 1:35-127;cp.b 3000000 c0480000 ${filesize}\0" \
+ 	"updatekernel=tftp 3000000 ${kernelfile};protect off 1:4-35\;erase 1:4-35;cp.b 3000000 c0080000 ${filesize}\0" \
+	"updateboot=tftp 3000000 ${bootfile};protect off 1:1-3\;erase 1:1-3;cp.b 3000000 c0020000 ${filesize}\0" \
+	"updateuloader=tftp 3000000 uloader.bin;protect off 1:0-1\;erase 1:0-1;cp.b 3000000 c0000000 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+//#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+
+#define CONFIG_SYS_LOAD_ADDR CFG_LOAD_ADDR
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+//#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		1024	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0xC0000000 //EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(1 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+//#define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
+#define CFG_64BIT_STRTOUL
+
+#define EXP_CS0_BASE_VAL	0x0
+#define EXP_CS0_SEG_SIZE_VAL    0x7FFF
+#define EXP_CS0_SEG_END_VAL     (EXP_CS0_BASE_VAL + EXP_CS0_SEG_SIZE_VAL)
+
+#define EXP_CS1_BASE_VAL        (EXP_CS0_SEG_END_VAL + 1)
+#define EXP_CS1_SEG_SIZE_VAL    0xFF
+#define EXP_CS1_SEG_END_VAL     (EXP_CS1_BASE_VAL + EXP_CS1_SEG_SIZE_VAL)
+
+#define EXP_CS2_BASE_VAL        (EXP_CS1_SEG_END_VAL + 1)
+#define EXP_CS2_SEG_SIZE_VAL    0xFF
+#define EXP_CS2_SEG_END_VAL     (EXP_CS2_BASE_VAL + EXP_CS2_SEG_SIZE_VAL)
+
+#define EXP_CS3_BASE_VAL        (EXP_CS2_SEG_END_VAL + 1)
+#define EXP_CS3_SEG_SIZE_VAL    0xFF
+#define EXP_CS3_SEG_END_VAL     (EXP_CS3_BASE_VAL + EXP_CS3_SEG_SIZE_VAL)
+
+#define EXP_CS4_BASE_VAL        (EXP_CS3_SEG_END_VAL + 1)
+#define EXP_CS4_SEG_SIZE_VAL    0xFF
+#define EXP_CS4_SEG_END_VAL     (EXP_CS4_BASE_VAL + EXP_CS4_SEG_SIZE_VAL)
+
+#define SHIFT_4K_MUL    12
+
+#define COMCERTO_EXP_CS4_BASE_ADDR      (COMCERTO_AXI_EXP_BASE + (EXP_CS4_BASE_VAL << SHIFT_4K_MUL))
+
+#define CONFIG_SYS_NAND_BASE_LIST       { COMCERTO_EXP_CS4_BASE_ADDR }
+#define CONFIG_SYS_NAND_BASE       COMCERTO_EXP_CS4_BASE_ADDR
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
+
+#define CONFIG_SYS_NAND_SELF_INIT
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* NAND debugging */
+#define CFG_DFC_DEBUG1 /* usefull */
+#define CFG_DFC_DEBUG2  /* noisy */
+#define CFG_DFC_DEBUG3  /* extremly noisy  */
+
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 1
+
+//In case MLC NAND is used on the Asic Board, comment this out
+//#define CONFIG_NAND_TYPE_SLC
+
+#if defined (CONFIG_NAND_TYPE_SLC)
+#define COMCERTO_NAND_FLASH_SIZE        (512UL * 1024UL * 1024UL)
+#else
+#define COMCERTO_NAND_FLASH_SIZE        (2UL * 1024UL * 1024UL * 1024UL)
+#endif
+
+#define CFG_NAND_BASE			COMCERTO_EXP_CS4_BASE_ADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	29
+#define CFG_NAND_CE_GPIO	28
+#define CFG_NAND_CLE		0x00000400
+#define CFG_NAND_ALE		0x00000200
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+//#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:128k(uloader),256k(u-boot),128k(env),4M(kernel),16M(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,3"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#endif
+
+#define CFG_HZ                  1000
+
+#if 0
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			2000
+//#define CFG_CLK			CFG_CLK_650_187_375
+//#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+//#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+//#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+#endif
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x83000000	//0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define	CONFIG_SYS_GBL_DATA_SIZE	128
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/c2kasic.h

diff --git a/include/configs/c2kasic.h b/include/configs/c2kasic.h
new file mode 100644
index 0000000..145a01d
--- /dev/null
+++ b/include/configs/c2kasic.h
@@ -0,0 +1,408 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARMV7 		1
+#define CONFIG_COMCERTO_2000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C2KASIC	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#define	CONFIG_ARM_EXCEPTIONS	1
+#define	CONFIG_ARCH_HAS_LOWLEVEL_INIT	1
+#define	CONFIG_MMU	1
+#define CFG_HZ_CLOCK          250000000
+#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
+
+#define CPU_3XX_ES20            1
+#define	CMD_SAVEENV	1
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		COMCERTO_AXI_DDR_BASE
+#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Gemac Settings
+ */
+#define EMAC0_PHY_ADDR  4
+#define EMAC1_PHY_ADDR  5
+#define EMAC0_FLAGS     0
+#define EMAC1_FLAGS     0
+#define EMAC2_FLAGS     0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV  | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII  | CFG_CMD_RUN | CFG_CMD_NET /*| CFG_CMD_NAND */ | CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS  | CFG_CMD_I2C | CFG_CMD_EEPROM /*| CFG_CMD_ELF| CFG_CMD_SPI*/)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-2000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto2000\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock4 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,115200n8\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; bootm 0xc0080000\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"loadaddr=0x3000000\0"		\
+	"rootpath=/devel/fs-c2kasic\0" \
+	"kernelfile=uImage\0" \
+	"bootfile=u-boot.bin\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+ 	"updatefs=tftp 3000000 ${fsfile};protect off 1:35-127\;erase 1:35-127;cp.b 3000000 c0480000 ${filesize}\0" \
+ 	"updatekernel=tftp 3000000 ${kernelfile};protect off 1:4-35\;erase 1:4-35;cp.b 3000000 c0080000 ${filesize}\0" \
+	"updateboot=tftp 3000000 ${bootfile};protect off 1:1-3\;erase 1:1-3;cp.b 3000000 c0020000 ${filesize}\0" \
+	"updateuloader=tftp 3000000 uloader.bin;protect off 1:0-1\;erase 1:0-1;cp.b 3000000 c0000000 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+//#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+
+#define CONFIG_SYS_LOAD_ADDR CFG_LOAD_ADDR
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+//#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		1024	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0xC0000000 //EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(1 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+//#define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
+#define CFG_64BIT_STRTOUL
+
+#define EXP_CS0_BASE_VAL	0x0
+#define EXP_CS0_SEG_SIZE_VAL    0x7FFF
+#define EXP_CS0_SEG_END_VAL     (EXP_CS0_BASE_VAL + EXP_CS0_SEG_SIZE_VAL)
+
+#define EXP_CS1_BASE_VAL        (EXP_CS0_SEG_END_VAL + 1)
+#define EXP_CS1_SEG_SIZE_VAL    0xFF
+#define EXP_CS1_SEG_END_VAL     (EXP_CS1_BASE_VAL + EXP_CS1_SEG_SIZE_VAL)
+
+#define EXP_CS2_BASE_VAL        (EXP_CS1_SEG_END_VAL + 1)
+#define EXP_CS2_SEG_SIZE_VAL    0xFF
+#define EXP_CS2_SEG_END_VAL     (EXP_CS2_BASE_VAL + EXP_CS2_SEG_SIZE_VAL)
+
+#define EXP_CS3_BASE_VAL        (EXP_CS2_SEG_END_VAL + 1)
+#define EXP_CS3_SEG_SIZE_VAL    0xFF
+#define EXP_CS3_SEG_END_VAL     (EXP_CS3_BASE_VAL + EXP_CS3_SEG_SIZE_VAL)
+
+#define EXP_CS4_BASE_VAL        (EXP_CS3_SEG_END_VAL + 1)
+#define EXP_CS4_SEG_SIZE_VAL    0xFF
+#define EXP_CS4_SEG_END_VAL     (EXP_CS4_BASE_VAL + EXP_CS4_SEG_SIZE_VAL)
+
+#define SHIFT_4K_MUL    12
+
+#define COMCERTO_EXP_CS4_BASE_ADDR      (COMCERTO_AXI_EXP_BASE + (EXP_CS4_BASE_VAL << SHIFT_4K_MUL))
+
+#define CONFIG_SYS_NAND_BASE_LIST       { COMCERTO_EXP_CS4_BASE_ADDR }
+#define CONFIG_SYS_NAND_BASE       COMCERTO_EXP_CS4_BASE_ADDR
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
+
+#define CONFIG_SYS_NAND_SELF_INIT
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* NAND debugging */
+#define CFG_DFC_DEBUG1 /* usefull */
+#define CFG_DFC_DEBUG2  /* noisy */
+#define CFG_DFC_DEBUG3  /* extremly noisy  */
+
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 1
+
+//In case MLC NAND is used on the Asic Board, comment this out
+//#define CONFIG_NAND_TYPE_SLC
+
+#if defined (CONFIG_NAND_TYPE_SLC)
+#define COMCERTO_NAND_FLASH_SIZE        (512UL * 1024UL * 1024UL)
+#else
+#define COMCERTO_NAND_FLASH_SIZE        (2UL * 1024UL * 1024UL * 1024UL)
+#endif
+
+#define CFG_NAND_BASE			COMCERTO_EXP_CS4_BASE_ADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	29
+#define CFG_NAND_CE_GPIO	28
+#define CFG_NAND_CLE		0x00000400
+#define CFG_NAND_ALE		0x00000200
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+//#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:128k(uloader),256k(u-boot),128k(env),4M(kernel),16M(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,3"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#endif
+
+#define CFG_HZ                  1000
+
+#if 0
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			2000
+//#define CFG_CLK			CFG_CLK_650_187_375
+//#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+//#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+//#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+#endif
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x83000000	//0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define	CONFIG_SYS_GBL_DATA_SIZE	128
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/c2kevm-nand.h

diff --git a/include/configs/c2kevm-nand.h b/include/configs/c2kevm-nand.h
new file mode 100644
index 0000000..20721b1
--- /dev/null
+++ b/include/configs/c2kevm-nand.h
@@ -0,0 +1,410 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARMV7 		1
+#define CONFIG_COMCERTO_2000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C2KEVM	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#define	CONFIG_ARM_EXCEPTIONS	1
+#define	CONFIG_ARCH_HAS_LOWLEVEL_INIT	1
+#define	CONFIG_MMU	1
+#define CFG_HZ_CLOCK          250000000
+#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
+
+#define CPU_3XX_ES20            1
+#define	CMD_SAVEENV	1
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		COMCERTO_AXI_DDR_BASE
+#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Gemac Settings
+ */
+#define EMAC0_PHY_ADDR  4
+#define EMAC1_PHY_ADDR  0
+#define EMAC0_FLAGS     0
+#define EMAC1_FLAGS     1 
+#define EMAC2_FLAGS     0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV  | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII  | CFG_CMD_RUN | CFG_CMD_NET | CFG_CMD_NAND | CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS  | CFG_CMD_I2C | CFG_CMD_EEPROM /*| CFG_CMD_ELF| CFG_CMD_SPI*/)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-2000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto2000\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock4 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,115200n8\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; bootm 0xc0080000\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-c2kasic\0" \
+	"kernelfile=uImage\0" \
+	"bootfile=u-boot.bin\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+ 	"updatefs=tftp 3000000 ${fsfile};protect off 1:35-127\;erase 1:35-127;cp.b 3000000 c0480000 ${filesize}\0" \
+ 	"updatekernel=tftp 3000000 ${kernelfile};protect off 1:4-35\;erase 1:4-35;cp.b 3000000 c0080000 ${filesize}\0" \
+	"updateboot=tftp 3000000 ${bootfile};protect off 1:1-3\;erase 1:1-3;cp.b 3000000 c0020000 ${filesize}\0" \
+	"updateuloader=tftp 3000000 uloader.bin;protect off 1:0-1\;erase 1:0-1;cp.b 3000000 c0000000 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+//#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+
+#define CONFIG_SYS_LOAD_ADDR CFG_LOAD_ADDR
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+//#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		1024	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0xC0000000 //EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(1 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+//#define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CONFIG_SYS_I2C_SPEED	       40000
+#define CFG_I2C_SLAVE                  0
+#define CONFIG_SYS_I2C_SLAVE	       0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
+#define CFG_64BIT_STRTOUL
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
+
+#define CONFIG_SYS_NAND_SELF_INIT
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* NAND debugging */
+#define CFG_DFC_DEBUG1 /* usefull */
+#define CFG_DFC_DEBUG2  /* noisy */
+#define CFG_DFC_DEBUG3  /* extremly noisy  */
+
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 1
+
+
+#define EXP_CS0_BASE_VAL	0x0
+#define EXP_CS0_SEG_SIZE_VAL    0x7FFF
+#define EXP_CS0_SEG_END_VAL     (EXP_CS0_BASE_VAL + EXP_CS0_SEG_SIZE_VAL)
+
+#define EXP_CS1_BASE_VAL        (EXP_CS0_SEG_END_VAL + 1)
+#define EXP_CS1_SEG_SIZE_VAL    0xFF
+#define EXP_CS1_SEG_END_VAL     (EXP_CS1_BASE_VAL + EXP_CS1_SEG_SIZE_VAL)
+
+#define EXP_CS2_BASE_VAL        (EXP_CS1_SEG_END_VAL + 1)
+#define EXP_CS2_SEG_SIZE_VAL    0xFF
+#define EXP_CS2_SEG_END_VAL     (EXP_CS2_BASE_VAL + EXP_CS2_SEG_SIZE_VAL)
+
+#define EXP_CS3_BASE_VAL        (EXP_CS2_SEG_END_VAL + 1)
+#define EXP_CS3_SEG_SIZE_VAL    0xFF
+#define EXP_CS3_SEG_END_VAL     (EXP_CS3_BASE_VAL + EXP_CS3_SEG_SIZE_VAL)
+
+#define EXP_CS4_BASE_VAL        (EXP_CS3_SEG_END_VAL + 1)
+#define EXP_CS4_SEG_SIZE_VAL    0xFF
+#define EXP_CS4_SEG_END_VAL     (EXP_CS4_BASE_VAL + EXP_CS4_SEG_SIZE_VAL)
+
+#define SHIFT_4K_MUL    12
+
+#define COMCERTO_EXP_CS4_BASE_ADDR      (COMCERTO_AXI_EXP_BASE + (EXP_CS4_BASE_VAL << SHIFT_4K_MUL))
+
+#define CONFIG_SYS_NAND_BASE_LIST       { COMCERTO_EXP_CS4_BASE_ADDR }
+#define CONFIG_SYS_NAND_BASE       COMCERTO_EXP_CS4_BASE_ADDR
+
+//In case MLC NAND is used on the Asic Board, comment this out
+//#define CONFIG_NAND_TYPE_SLC
+
+#if defined (CONFIG_NAND_TYPE_SLC)
+#define COMCERTO_NAND_FLASH_SIZE        (512UL * 1024UL * 1024UL)
+#else
+#define COMCERTO_NAND_FLASH_SIZE        (2UL * 1024UL * 1024UL * 1024UL)
+#endif
+
+#define CFG_NAND_BASE			COMCERTO_EXP_CS4_BASE_ADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	29
+#define CFG_NAND_CE_GPIO	28
+#define CFG_NAND_CLE		0x00000400
+#define CFG_NAND_ALE		0x00000200
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+//#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:128k(uloader),256k(u-boot),128k(env),4M(kernel),16M(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,3"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#endif
+
+#define CFG_HZ                  1000
+
+#if 0
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			2000
+//#define CFG_CLK			CFG_CLK_650_187_375
+//#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+//#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+//#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+#endif
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x83000000	//0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define	CONFIG_SYS_GBL_DATA_SIZE	128
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/c2kevm.h

diff --git a/include/configs/c2kevm.h b/include/configs/c2kevm.h
new file mode 100644
index 0000000..1a6e9be
--- /dev/null
+++ b/include/configs/c2kevm.h
@@ -0,0 +1,409 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARMV7 		1
+#define CONFIG_COMCERTO_2000	1	/* It's an  SoC */
+#define CONFIG_BOARD_C2KEVM	1
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#define	CONFIG_ARM_EXCEPTIONS	1
+#define	CONFIG_ARCH_HAS_LOWLEVEL_INIT	1
+#define	CONFIG_MMU	1
+#define CFG_HZ_CLOCK          250000000
+#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
+
+#define CPU_3XX_ES20            1
+#define	CMD_SAVEENV	1
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		COMCERTO_AXI_DDR_BASE
+#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Gemac Settings
+ */
+#define EMAC0_PHY_ADDR  4
+#define EMAC1_PHY_ADDR  0
+#define EMAC0_FLAGS     0
+#define EMAC1_FLAGS     1
+#define EMAC2_FLAGS     0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV  | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII  | CFG_CMD_RUN | CFG_CMD_NET /*| CFG_CMD_NAND */ | CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS  | CFG_CMD_I2C | CFG_CMD_EEPROM /*| CFG_CMD_ELF| CFG_CMD_SPI*/)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-2000 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto2000\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock4 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,115200n8\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; bootm 0xc0080000\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"loadaddr=0x3000000\0"		\
+	"rootpath=/devel/fs-c2kasic\0" \
+	"kernelfile=uImage\0" \
+	"bootfile=u-boot.bin\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+ 	"updatefs=tftp 3000000 ${fsfile};protect off 1:35-127\;erase 1:35-127;cp.b 3000000 c0480000 ${filesize}\0" \
+ 	"updatekernel=tftp 3000000 ${kernelfile};protect off 1:4-35\;erase 1:4-35;cp.b 3000000 c0080000 ${filesize}\0" \
+	"updateboot=tftp 3000000 ${bootfile};protect off 1:1-3\;erase 1:1-3;cp.b 3000000 c0020000 ${filesize}\0" \
+	"updateuloader=tftp 3000000 uloader.bin;protect off 1:0-1\;erase 1:0-1;cp.b 3000000 c0000000 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+//#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+
+#define CONFIG_SYS_LOAD_ADDR CFG_LOAD_ADDR
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+//#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		1024	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0xC0000000 //EXP_CS0_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(1 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#undef CFG_FLASH_COMPLEX_MAPPINGS
+//#define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
+#define CFG_64BIT_STRTOUL
+
+#define EXP_CS0_BASE_VAL	0x0
+#define EXP_CS0_SEG_SIZE_VAL    0x7FFF
+#define EXP_CS0_SEG_END_VAL     (EXP_CS0_BASE_VAL + EXP_CS0_SEG_SIZE_VAL)
+
+#define EXP_CS1_BASE_VAL        (EXP_CS0_SEG_END_VAL + 1)
+#define EXP_CS1_SEG_SIZE_VAL    0xFF
+#define EXP_CS1_SEG_END_VAL     (EXP_CS1_BASE_VAL + EXP_CS1_SEG_SIZE_VAL)
+
+#define EXP_CS2_BASE_VAL        (EXP_CS1_SEG_END_VAL + 1)
+#define EXP_CS2_SEG_SIZE_VAL    0xFF
+#define EXP_CS2_SEG_END_VAL     (EXP_CS2_BASE_VAL + EXP_CS2_SEG_SIZE_VAL)
+
+#define EXP_CS3_BASE_VAL        (EXP_CS2_SEG_END_VAL + 1)
+#define EXP_CS3_SEG_SIZE_VAL    0xFF
+#define EXP_CS3_SEG_END_VAL     (EXP_CS3_BASE_VAL + EXP_CS3_SEG_SIZE_VAL)
+
+#define EXP_CS4_BASE_VAL        (EXP_CS3_SEG_END_VAL + 1)
+#define EXP_CS4_SEG_SIZE_VAL    0xFF
+#define EXP_CS4_SEG_END_VAL     (EXP_CS4_BASE_VAL + EXP_CS4_SEG_SIZE_VAL)
+
+#define SHIFT_4K_MUL    12
+
+#define COMCERTO_EXP_CS4_BASE_ADDR      (COMCERTO_AXI_EXP_BASE + (EXP_CS4_BASE_VAL << SHIFT_4K_MUL))
+
+#define CONFIG_SYS_NAND_BASE_LIST       { COMCERTO_EXP_CS4_BASE_ADDR }
+#define CONFIG_SYS_NAND_BASE       COMCERTO_EXP_CS4_BASE_ADDR
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
+
+#define CONFIG_SYS_NAND_SELF_INIT
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* NAND debugging */
+#define CFG_DFC_DEBUG1 /* usefull */
+#define CFG_DFC_DEBUG2  /* noisy */
+#define CFG_DFC_DEBUG3  /* extremly noisy  */
+
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 1
+
+
+//In case MLC NAND is used on the Asic Board, comment this out
+//#define CONFIG_NAND_TYPE_SLC
+
+#if defined (CONFIG_NAND_TYPE_SLC)
+#define COMCERTO_NAND_FLASH_SIZE        (512UL * 1024UL * 1024UL)
+#else
+#define COMCERTO_NAND_FLASH_SIZE        (2UL * 1024UL * 1024UL * 1024UL)
+#endif
+
+#define CFG_NAND_BASE			COMCERTO_EXP_CS4_BASE_ADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	29
+#define CFG_NAND_CE_GPIO	28
+#define CFG_NAND_CLE		0x00000400
+#define CFG_NAND_ALE		0x00000200
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+//#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:128k(uloader),256k(u-boot),128k(env),4M(kernel),16M(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,3"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#endif
+
+#define CFG_HZ                  1000
+
+#if 0
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			2000
+//#define CFG_CLK			CFG_CLK_650_187_375
+//#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
+//#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
+//#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
+#endif
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x83000000	//0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00020000 /* 128K */
+#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define	CONFIG_SYS_GBL_DATA_SIZE	128
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/ferouter.h

diff --git a/include/configs/ferouter.h b/include/configs/ferouter.h
new file mode 100644
index 0000000..cd3ce98
--- /dev/null
+++ b/include/configs/ferouter.h
@@ -0,0 +1,296 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_100	1	/* It's an  SoC */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE		0x04000000	/* 64 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		4
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_MII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_100M)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		5
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_MII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_100M)
+#define GEMAC1_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC1_PHYIDX		0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET |  /*CFG_CMD_NAND |*/ CFG_CMD_JFFS2 | CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_MII | CFG_CMD_SPI | CFG_CMD_ELF)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-100 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto100\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-ferouter\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-64k\0" \
+	"updatefs=tftp 81000000 ${fsfile};protect off 1:6-255\;erase 1:6-255;cp.b 81000000 20060000 ${filesize}\0" \
+	"updateboot=tftp 81000000 u-boot.bin;protect off 1:0-3\;erase 1:0-3;cp.b 81000000 20000000 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0x20000000	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+
+#define CFG_FLASH_COMPLEX_MAPPINGS
+#define CFG_NOR_FLASH_A22_GPIO 22
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (2 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 4 * PHYS_FLASH1_SECT_SIZE)	/* Keep 4 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment 16KiB */
+  
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		165000000	/* 165 MHz, must be multiple of 33MHz */
+#define CFG_ARM_CLOCK		450000000	/* 450 MHz, must be multiple of 25MHz */
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00010000 /* 64K */
+#define CFG_ARAM_CODE_SIZE	0x00008000 /* 32K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+#define DDR_TRAINING_DBG 
+
+/* New DDR training defines (Bug #44131) */
+//#undef NEW_DDR_TRAINING  //undef this for old training
+#define NEW_DDR_TRAINING  //undef this for old training
+
+#endif /* __CONFIG_H */

include/configs/ferouter_aram.h

diff --git a/include/configs/ferouter_aram.h b/include/configs/ferouter_aram.h
new file mode 100644
index 0000000..5a5171e
--- /dev/null
+++ b/include/configs/ferouter_aram.h
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_100	1	/* It's an  SoC */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_UBOOT_LOADED_IN_ARAM
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE		0x04000000	/* 64 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#undef CONFIG_COMCERTO_GEMAC
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		4
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_MII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_100M)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		5
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_MII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_100M)
+#define GEMAC1_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC1_PHYIDX		0
+
+#undef CONFIG_NET_MULTI
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | /*CFG_CMD_ENV |*/ CFG_CMD_MEMORY | CFG_CMD_RUN /*| CFG_CMD_NET |  CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM */)
+
+#define CONFIG_NO_GZIP		1
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-100 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto100\0"						\
+	"netdev=eth0\0"									\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"boot_flash=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"writeboot=protect off 1:0-3\;erase 1:0-3;cp.b 81000000 20000000 40000\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0x20000000	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+
+#define CFG_FLASH_COMPLEX_MAPPINGS
+#define CFG_NOR_FLASH_A22_GPIO 22
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (2 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_NOWHERE	1
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 4 * PHYS_FLASH1_SECT_SIZE)	/* Keep 4 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment 16KiB */
+  
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		165000000	/* 165 MHz, must be multiple of 33MHz */
+#define CFG_ARM_CLOCK		450000000	/* 450 MHz, must be multiple of 25MHz */
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00010000 /* 64K */
+#define CFG_ARAM_CODE_SIZE	0x00000400 /* 1K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#define DDR_TRAINING_DBG 
+
+/* New DDR training defines (Bug #44131) */
+//#undef NEW_DDR_TRAINING  //undef this for old training
+#define NEW_DDR_TRAINING  //undef this for old training
+
+#endif /* __CONFIG_H */

include/configs/ipots48-515.h

diff --git a/include/configs/ipots48-515.h b/include/configs/ipots48-515.h
new file mode 100644
index 0000000..2fdbc79
--- /dev/null
+++ b/include/configs/ipots48-515.h
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_515			/* It's a SoC */
+#define CONFIG_IPOTS48_515			/* on a Ipots48-515 Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+#define CONFIG_EMAC0_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC0_PHYCTRLDIS		1
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+#define CONFIG_EMAC0_PHY_ADDR		0x0
+
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS			(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET | \
+					 CFG_CMD_MII | CFG_CMD_ELF | CFG_CMD_NAND | CFG_CMD_SPI)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-515 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"tftpdir=.\0"			\
+	"nfsdir=/home/nfs/fsminimal-debian_sarge-0.13\0"			\
+	"mspname=firmware.axf\0"	\
+	"cspname=zImage\0"		\
+	"fsname=fsimage.jffs2\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
+	"updateboot=tftp 1000000 ${tftpdir}/u-boot.bin; erase 1:0-2; cp.b ${fileaddr} 11000000 ${filesize}\0"	\
+	"updatebootNOR=tftp 1000000 ${tftpdir}/u-boot.bin; erase 2:0-2; cp.b ${fileaddr} 80000000 ${filesize}\0"	\
+	"updatecspNOR=tftp 1000000 ${tftpdir}/${cspname}; erase 2:4-31; cp.b ${fileaddr} 80040000 ${filesize}\0"	\
+	"updatemspNOR=tftp 1000000 ${tftpdir}/${mspname}; erase 2:32-63; cp.b ${fileaddr} 80200000 ${filesize}\0"	\
+	"updatecspNAND=tftp 1000000 ${tftpdir}/${cspname}; nand erase 0 200000; nand write.jffs2 ${fileaddr} 0 ${filesize}\0"	\
+	"updatemspNAND=tftp 1000000 ${tftpdir}/${mspname}; nand erase 200000 200000; nand write.jffs2 ${fileaddr} 200000 ${filesize}\0"	\
+	"updatefsNAND=tftp 1000000 ${tftpdir}/${fsname}; nand erase 400000 7c00000; nand write.jffs2 ${fileaddr} 400000 ${filesize}\0"	\
+	"boottt=run setbootargs; tftp 1000000 ${tftpdir}/${mspname}; loadmsp ${fileaddr} ${filesize}; tftp 2000000 ${tftpdir}/${cspname}; bootcomcerto ${fileaddr}\0"	\
+	"bootoo=run setbootargs; loadmsp 80200000 200000; cp.b 80040000 2000000 200000; bootcomcerto 2000000\0"	\
+	"bootaa=run setbootargs; nand read.jffs2 1000000 200000 200000; loadmsp 1000000 200000; nand read.jffs2 2000000 0 200000; bootcomcerto 2000000\0"	\
+	"mtdboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"	\
+	"nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsdir}\0"	\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::eth0\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"setbootargs=run mtdboot addtty addip addmtd\0"
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+
+#include <cmd_confdefs.h>
+
+/* Include basic MMU support if ELF support is included
+ *
+ * NOTE: keep this stuff after "cmd_confdefs.h" include
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+#define USE_920T_MMU
+#endif
+
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0100000	/* 1 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+#define CFG_FLASH_AM040_DRIVER				/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+//#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x800000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH2			0x80000000	/* Flash Bank #2 */
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		2	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1, PHYS_FLASH2}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP0_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+#define CONFIG_SPI			1		/* define to enable SPI using */
+/* 
+* SPI configuration registers values 
+*/
+/* Control Register 0 values*/
+#define CFG_SPI_CLOCK_POLARITY		1		/* Inactive state of serial clock is high */
+#define CFG_SPI_CLOCK_PHASE		1		/* Serial Clock toggles at the start of the first data bit */
+#define CFG_SPI_FRAMESIZE 		8		/* define teh SPI frame sizein bits. 8-bit supported only */
+/* Baud Rate Select Register value*/
+#define CFG_SPI_CLOCK_SPEED		2015151		/* the SPI speed in Hz */
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=comcerto_nand0,nor0=comcerto_nor0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcerto_nand0:2m(csp),2m(msp),124m(fs);comcerto_nor0:192k(bootloader),64k(bootloader env),1792k(csp),2m(msp)"
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		133000000	/* 133 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/ipots48-800.h

diff --git a/include/configs/ipots48-800.h b/include/configs/ipots48-800.h
new file mode 100644
index 0000000..9e7a314
--- /dev/null
+++ b/include/configs/ipots48-800.h
@@ -0,0 +1,278 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_800			/* It's a SoC */
+#define CONFIG_IPOTS48_800			/* on a Ipots48-800 Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+#define CONFIG_EMAC0_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC0_PHYCTRLDIS		1
+
+#undef CONFIG_EMAC1
+#define CONFIG_EMAC1_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC1_PHYCTRLDIS		1
+
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+#define CONFIG_EMAC0_PHY_ADDR		0x0
+
+#define CONFIG_EMAC1_MDCLOCK		2500000
+#define CONFIG_EMAC1_PHY_ADDR		0x0
+
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS			(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET | \
+					 CFG_CMD_MII | CFG_CMD_ELF | CFG_CMD_NAND)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-800 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"tftpdir=.\0"			\
+	"nfsdir=/home/nfs/fsminimal-debian_sarge-0.13\0"			\
+	"mspname=firmware.axf\0"	\
+	"cspname=zImage\0"		\
+	"fsname=fsimage.jffs2\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
+	"updateboot=tftp 1000000 ${tftpdir}/u-boot.bin; erase 1:0-2; cp.b ${fileaddr} 11000000 ${filesize}\0"	\
+	"updatebootNOR=tftp 1000000 ${tftpdir}/u-boot.bin; erase 2:0-2; cp.b ${fileaddr} 80000000 ${filesize}\0"	\
+	"updatecspNOR=tftp 1000000 ${tftpdir}/${cspname}; erase 2:4-31; cp.b ${fileaddr} 80040000 ${filesize}\0"	\
+	"updatemspNOR=tftp 1000000 ${tftpdir}/${mspname}; erase 2:32-63; cp.b ${fileaddr} 80200000 ${filesize}\0"	\
+	"updatecspNAND=tftp 1000000 ${tftpdir}/${cspname}; nand erase 0 200000; nand write.jffs2 ${fileaddr} 0 ${filesize}\0"	\
+	"updatemspNAND=tftp 1000000 ${tftpdir}/${mspname}; nand erase 200000 200000; nand write.jffs2 ${fileaddr} 200000 ${filesize}\0"	\
+	"updatefsNAND=tftp 1000000 ${tftpdir}/${fsname}; nand erase 400000 7c00000; nand write.jffs2 ${fileaddr} 400000 ${filesize}\0"	\
+	"boottt=run setbootargs; tftp 1000000 ${tftpdir}/${mspname}; loadmsp ${fileaddr} ${filesize}; tftp 2000000 ${tftpdir}/${cspname}; bootcomcerto ${fileaddr}\0"	\
+	"bootoo=run setbootargs; loadmsp 80200000 200000; cp.b 80040000 2000000 200000; bootcomcerto 2000000\0"	\
+	"bootaa=run setbootargs; nand read.jffs2 1000000 200000 200000; loadmsp 1000000 200000; nand read.jffs2 2000000 0 200000; bootcomcerto 2000000\0"	\
+	"mtdboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"	\
+	"nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsdir}\0"	\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::eth0\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"setbootargs=run mtdboot addtty addip addmtd\0"
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_ETH1ADDR         00:aa:bb:cc:dd:ff
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+
+#include <cmd_confdefs.h>
+
+/* Include basic MMU support if ELF support is included
+ *
+ * NOTE: keep this stuff after "cmd_confdefs.h" include
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+#define USE_920T_MMU
+#endif
+
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0100000	/* 1 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+#define CFG_FLASH_AM040_DRIVER				/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+//#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x800000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH2			0x80000000	/* Flash Bank #2 */
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		2	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1, PHYS_FLASH2}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP0_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=comcerto_nand0,nor0=comcerto_nor0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcerto_nand0:2m(csp),2m(msp),124m(fs);comcerto_nor0:192k(bootloader),64k(bootloader env),1792k(csp),2m(msp)"
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		133000000	/* 133 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/m8324XG.h

diff --git a/include/configs/m8324XG.h b/include/configs/m8324XG.h
new file mode 100644
index 0000000..c498a6b
--- /dev/null
+++ b/include/configs/m8324XG.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __M8324XG_H
+#define __M8324XG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_M8324XG       1
+
+#define ADJ2_MIN_VAL    105
+#define ADJ2_MAX_VAL    165
+
+#define ADJ2_MIN_ACCEPTED_RANGE     20    /* adj2_val1: error */
+#define ADJ2_ACCEPTED_RANGE         25    /* adj2_val2: warning */
+
+#define ADJ1_MIN_VAL     1
+#define ADJ1_MAX_VAL    80
+
+#define ADJ1_MIN_ACCEPTED_WINDOW    20     /* adj1_val1: ignore */
+#define ADJ1_ACCEPTED_WINDOW        25     /* adj1_val2: warning */
+
+// DDR Configs
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #1
+#define DENALI_CTL_00_VAL_CFG1   0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG1   0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG1   0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG1   0x0202020202020202LL
+// #define DENALI_CTL_04_VAL_CFG1
+#define DENALI_CTL_05_VAL_CFG1   0x0003010500020001LL
+#define DENALI_CTL_06_VAL_CFG1   0x0A0A040300030400LL
+#define DENALI_CTL_07_VAL_CFG1   0x000000050000020ALL
+#define DENALI_CTL_08_VAL_CFG1   0x6400003F3F130210LL
+#define DENALI_CTL_09_VAL_CFG1   0x0000640064006400LL
+// #define DENALI_CTL_10_VAL_CFG1
+#define DENALI_CTL_11_VAL_CFG1   0x0000002B00000000LL
+#define DENALI_CTL_12_VAL_CFG1   0x0000000000001000LL
+#define DENALI_CTL_13_VAL_CFG1   0x0010001000100010LL
+#define DENALI_CTL_14_VAL_CFG1   0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG1   0x09FA000000000000LL
+#define DENALI_CTL_16_VAL_CFG1   0x0000000059C60000LL
+#define DENALI_CTL_17_VAL_CFG1   0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG1   0x0600010000000000LL
+#define DENALI_CTL_19_VAL_CFG1   0x00002E00C8050A00LL
+#define DENALI_CTL_20_VAL_CFG1   0x0000010101D700C8LL
+#define DENALI_CTL_21_VAL_CFG1   0x0202020100000101LL
+#define DENALI_CTL_22_VAL_CFG1   0x0000020007000002LL
+// #define DENALI_CTL_23_VAL_CFG1
+#define DENALI_CTL_24_VAL_CFG1   0x0000000200850000LL
+#define DENALI_CTL_25_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG1   0x9400593794005937LL
+#define DENALI_CTL_27_VAL_CFG1   DENALI_CTL_26_VAL_CFG1
+#define DENALI_CTL_28_VAL_CFG1   0x07C0040107C00401LL
+#define DENALI_CTL_29_VAL_CFG1   DENALI_CTL_28_VAL_CFG1
+#define DENALI_CTL_30_VAL_CFG1   0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG1   0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG1   0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG1   0x0087878787050000LL
+#define DENALI_CTL_36_VAL_CFG1   0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG1   0x0A52000000040200LL
+#define DENALI_CTL_38_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG1   0x00000000000000c8LL
+#define DENALI_CTL_41_VAL_CFG1   0x0024199300241993LL
+#define DENALI_CTL_42_VAL_CFG1   DENALI_CTL_41_VAL_CFG1
+#define DENALI_CTL_43_VAL_CFG1   0x0000190000001900LL
+#define DENALI_CTL_44_VAL_CFG1   DENALI_CTL_43_VAL_CFG1
+#define DENALI_CTL_45_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG1   0x0000000000000050LL
+#define DENALI_CTL_50_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG1   0x0000000000000000LL
+// #define DENALI_CTL_63_VAL_CFG1
+// #define DENALI_CTL_64_VAL_CFG1
+// #define DENALI_CTL_65_VAL_CFG1
+#define DENALI_CTL_66_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG1   0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG1   0x00000003e8050000LL
+
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #2
+#define DENALI_CTL_00_VAL_CFG2	0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG2	0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG2	0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG2	0x0202020202020202LL
+// #define DENALI_CTL_04_VAL_CFG2	0x0000010100000001LL
+// original settings
+// #define DENALI_CTL_05_VAL_CFG2	0x0003010500010001LL
+// Dror's settings rtt_0=1
+#define DENALI_CTL_05_VAL_CFG2	0x0003010400020001LL
+// original settings
+// #define DENALI_CTL_06_VAL_CFG2	0x0a0a040300030300LL
+// Dror's settings
+#define DENALI_CTL_06_VAL_CFG2	0x080a030200020200LL
+// original settings
+// #define DENALI_CTL_07_VAL_CFG2	0x000000050000020aLL
+// Dror's settings
+#define DENALI_CTL_07_VAL_CFG2	0x0000000300000207LL
+// original settings
+// #define DENALI_CTL_08_VAL_CFG2	0x6400003f3f16020eLL
+// Dror's settings
+#define DENALI_CTL_08_VAL_CFG2	0x6400003f3f0b0209LL
+#define DENALI_CTL_09_VAL_CFG2	0x0000640064006400LL
+// #define DENALI_CTL_10_VAL_CFG2	0x0120202020191a18LL
+// original settings
+// #define DENALI_CTL_11_VAL_CFG2	0x0000003300000000LL
+// Dror's settings
+#define DENALI_CTL_11_VAL_CFG2	0x0000001a00000000LL
+// original settings
+// #define DENALI_CTL_12_VAL_CFG2	0x0000000000001000LL
+// Dror's settings
+#define DENALI_CTL_12_VAL_CFG2	0x0000000000000900LL
+#define DENALI_CTL_13_VAL_CFG2	0x0010001000100010LL	
+#define DENALI_CTL_14_VAL_CFG2	0x0010001000100010LL
+// original settings
+// #define DENALI_CTL_15_VAL_CFG2	0x0c2d000000000000LL
+// Dror's settings
+#define DENALI_CTL_15_VAL_CFG2	0x0612000000000000LL
+// original settings
+// #define DENALI_CTL_16_VAL_CFG2	0x000000006d560000LL
+// Dror's settings
+#define DENALI_CTL_16_VAL_CFG2	0x0000000036a60000LL
+#define DENALI_CTL_17_VAL_CFG2	0x0000010000000000LL
+// original settings
+// #define DENALI_CTL_18_VAL_CFG2	0x0600010000000000LL
+// Dror's settings
+#define DENALI_CTL_18_VAL_CFG2	0x0300010000000000LL
+// original settings
+// #define DENALI_CTL_19_VAL_CFG2	0x00003700c8050b00LL
+// Dror's settings
+#define DENALI_CTL_19_VAL_CFG2	0x00001c00c8030600LL
+// original settings
+// #define DENALI_CTL_20_VAL_CFG2	0x00000101388000c8LL
+// Dror's settings
+#define DENALI_CTL_20_VAL_CFG2	0x000001009c4000c8LL
+/* Original settings, AHB/DDR synchronous */
+#define DENALI_CTL_21_VAL_CFG2	0x0303030100000101LL
+#define DENALI_CTL_22_VAL_CFG2	0x0000020006000003LL
+/* AHB/DDR asynchronous */
+//#define DENALI_CTL_21_VAL_CFG2	0x0000000100000101LL
+//#define DENALI_CTL_22_VAL_CFG2	0x0000020006000000LL
+// #define DENALI_CTL_23_VAL_CFG2
+// original settings
+// #define DENALI_CTL_24_VAL_CFG2	0x0000000200a00000LL
+// Dror's settings
+#define DENALI_CTL_24_VAL_CFG2	0x0000000200500000LL
+#define DENALI_CTL_25_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG2	0x9340492793404927LL
+#define DENALI_CTL_27_VAL_CFG2	0x9340492793404927LL
+#define DENALI_CTL_28_VAL_CFG2	0x07c0040107c00401LL
+#define DENALI_CTL_29_VAL_CFG2	0x07c0040107c00401LL
+#define DENALI_CTL_30_VAL_CFG2	0x0000000000000004LL
+#define DENALI_CTL_31_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG2	0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG2	0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG2	0x0000000000000000LL
+// original settings
+// #define DENALI_CTL_35_VAL_CFG2	0x0034343434050000LL
+// Dror's settings
+#define DENALI_CTL_35_VAL_CFG2	0x0074747474030000LL
+#define DENALI_CTL_36_VAL_CFG2	0x0000000000000004LL
+// original settings
+// #define DENALI_CTL_37_VAL_CFG2	0x0a52000000040000LL
+// Dror's settings rtt=11 bit[1]=1
+#define DENALI_CTL_37_VAL_CFG2	0x0442000000040200LL
+#define DENALI_CTL_38_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG2	0x0000000000000000LL
+// original settings
+// #define DENALI_CTL_40_VAL_CFG2	0x00000000000000c8LL
+// Dror's settings
+#define DENALI_CTL_40_VAL_CFG2	0x0000000000000064LL
+// #define DENALI_CTL_41_VAL_CFG2	0x00cc005000cc0050LL
+// original settings
+// #define DENALI_CTL_41_VAL_CFG2	0x0017005000170050LL
+// Dror's settings adj1 = 0x28 
+#define DENALI_CTL_41_VAL_CFG2	0x0028009000280090LL
+#define DENALI_CTL_42_VAL_CFG2	DENALI_CTL_41_VAL_CFG2
+#define DENALI_CTL_43_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_44_VAL_CFG2	DENALI_CTL_43_VAL_CFG2
+#define DENALI_CTL_45_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG2	0x0000000000000000LL
+// original settings
+// #define DENALI_CTL_49_VAL_CFG2	0x0000000000000050LL
+// Dror's settings
+#define DENALI_CTL_49_VAL_CFG2	0x0000000000000028LL
+#define DENALI_CTL_50_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG2	0x0000000000000000LL
+// #define DENALI_CTL_63_VAL_CFG2	0x0000000000000000LL
+// #define DENALI_CTL_64_VAL_CFG2	0x0000000000000000LL
+// #define DENALI_CTL_65_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG2	0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG2	0x00000003e8050000LL
+
+#endif /* __M8324XG_H */

include/configs/m8325XG.h

diff --git a/include/configs/m8325XG.h b/include/configs/m8325XG.h
new file mode 100644
index 0000000..3849588
--- /dev/null
+++ b/include/configs/m8325XG.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __M8325XG_H
+#define __M8325XG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_M8325XG       1
+
+#define CFG_CLK	CFG_CLK_534_178_330
+
+#define ADJ2_MIN_VAL    105
+#define ADJ2_MAX_VAL    165
+
+#define ADJ2_MIN_ACCEPTED_RANGE     20    /* adj2_val1: error */
+#define ADJ2_ACCEPTED_RANGE         25    /* adj2_val2: warning */
+
+#define ADJ1_MIN_VAL     1
+#define ADJ1_MAX_VAL    80
+
+#define ADJ1_MIN_ACCEPTED_WINDOW    20     /* adj1_val1: ignore */
+#define ADJ1_ACCEPTED_WINDOW        25     /* adj1_val2: warning */
+
+// DDR Configs
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #1
+#define DENALI_CTL_00_VAL_CFG1   0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG1   0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG1   0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG1   0x0202020202020202LL
+#define DENALI_CTL_05_VAL_CFG1   0x0003010500020001LL
+#define DENALI_CTL_06_VAL_CFG1   0x0A0A040300030400LL
+#define DENALI_CTL_07_VAL_CFG1   0x000000050000020ALL
+#define DENALI_CTL_08_VAL_CFG1   0x6400003F3F130210LL
+#define DENALI_CTL_09_VAL_CFG1   0x0000640064006400LL
+#define DENALI_CTL_11_VAL_CFG1   0x0000002B00000000LL
+#define DENALI_CTL_12_VAL_CFG1   0x0000000000001000LL
+#define DENALI_CTL_13_VAL_CFG1   0x0010001000100010LL
+#define DENALI_CTL_14_VAL_CFG1   0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG1   0x09FA000000000000LL
+#define DENALI_CTL_16_VAL_CFG1   0x0000000059C60000LL
+#define DENALI_CTL_17_VAL_CFG1   0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG1   0x0600010000000000LL
+#define DENALI_CTL_19_VAL_CFG1   0x00002E00C8050A00LL
+#define DENALI_CTL_20_VAL_CFG1   0x0000010101D700C8LL
+#define DENALI_CTL_21_VAL_CFG1   0x0000000100000101LL
+#define DENALI_CTL_22_VAL_CFG1   0x0000020007000000LL
+#define DENALI_CTL_24_VAL_CFG1   0x0000000200850000LL
+#define DENALI_CTL_25_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG1   0x9400593794005937LL
+#define DENALI_CTL_27_VAL_CFG1   DENALI_CTL_26_VAL_CFG1
+#define DENALI_CTL_28_VAL_CFG1   0x07C0040107C00401LL
+#define DENALI_CTL_29_VAL_CFG1   DENALI_CTL_28_VAL_CFG1
+#define DENALI_CTL_30_VAL_CFG1   0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG1   0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG1   0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG1   0x0087878787050000LL
+#define DENALI_CTL_36_VAL_CFG1   0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG1   0x0A52000000040200LL
+#define DENALI_CTL_38_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG1   0x00000000000000c8LL
+#define DENALI_CTL_41_VAL_CFG1   0x0024199300241993LL
+#define DENALI_CTL_42_VAL_CFG1   DENALI_CTL_41_VAL_CFG1
+#define DENALI_CTL_43_VAL_CFG1   0x0000190000001900LL
+#define DENALI_CTL_44_VAL_CFG1   DENALI_CTL_43_VAL_CFG1
+#define DENALI_CTL_45_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG1   0x0000000000000050LL
+#define DENALI_CTL_50_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG1   0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG1   0x00000003e8050000LL
+
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #2
+#define DENALI_CTL_00_VAL_CFG2	0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG2	0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG2	0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG2	0x0202020202020202LL
+// #define DENALI_CTL_04_VAL_CFG2	0x0000010100000001LL
+// original settings
+// #define DENALI_CTL_05_VAL_CFG2	0x0003010500010001LL
+// Dror's settings rtt_0=1
+#define DENALI_CTL_05_VAL_CFG2	0x0003010400020001LL
+// original settings
+// #define DENALI_CTL_06_VAL_CFG2	0x0a0a040300030300LL
+// Dror's settings
+#define DENALI_CTL_06_VAL_CFG2	0x080a030200020200LL
+// original settings
+// #define DENALI_CTL_07_VAL_CFG2	0x000000050000020aLL
+// Dror's settings
+#define DENALI_CTL_07_VAL_CFG2	0x0000000300000207LL
+// original settings
+// #define DENALI_CTL_08_VAL_CFG2	0x6400003f3f16020eLL
+// Dror's settings
+#define DENALI_CTL_08_VAL_CFG2	0x6400003f3f0b0209LL
+#define DENALI_CTL_09_VAL_CFG2	0x0000640064006400LL
+// #define DENALI_CTL_10_VAL_CFG2	0x0120202020191a18LL
+// original settings
+// #define DENALI_CTL_11_VAL_CFG2	0x0000003300000000LL
+// Dror's settings
+#define DENALI_CTL_11_VAL_CFG2	0x0000001a00000000LL
+// original settings
+// #define DENALI_CTL_12_VAL_CFG2	0x0000000000001000LL
+// Dror's settings
+#define DENALI_CTL_12_VAL_CFG2	0x0000000000000900LL
+#define DENALI_CTL_13_VAL_CFG2	0x0010001000100010LL	
+#define DENALI_CTL_14_VAL_CFG2	0x0010001000100010LL
+// original settings
+// #define DENALI_CTL_15_VAL_CFG2	0x0c2d000000000000LL
+// Dror's settings
+#define DENALI_CTL_15_VAL_CFG2	0x0612000000000000LL
+// original settings
+// #define DENALI_CTL_16_VAL_CFG2	0x000000006d560000LL
+// Dror's settings
+#define DENALI_CTL_16_VAL_CFG2	0x0000000036a60000LL
+#define DENALI_CTL_17_VAL_CFG2	0x0000010000000000LL
+// original settings
+// #define DENALI_CTL_18_VAL_CFG2	0x0600010000000000LL
+// Dror's settings
+#define DENALI_CTL_18_VAL_CFG2	0x0300010000000000LL
+// original settings
+// #define DENALI_CTL_19_VAL_CFG2	0x00003700c8050b00LL
+// Dror's settings
+#define DENALI_CTL_19_VAL_CFG2	0x00001c00c8030600LL
+// original settings
+// #define DENALI_CTL_20_VAL_CFG2	0x00000101388000c8LL
+// Dror's settings
+#define DENALI_CTL_20_VAL_CFG2	0x000001009c4000c8LL
+/* Original settings, AHB/DDR synchronous */
+#define DENALI_CTL_21_VAL_CFG2	0x0303030100000101LL
+#define DENALI_CTL_22_VAL_CFG2	0x0000020006000003LL
+/* AHB/DDR asynchronous */
+//#define DENALI_CTL_21_VAL_CFG2	0x0000000100000101LL
+//#define DENALI_CTL_22_VAL_CFG2	0x0000020006000000LL
+// #define DENALI_CTL_23_VAL_CFG2
+// original settings
+// #define DENALI_CTL_24_VAL_CFG2	0x0000000200a00000LL
+// Dror's settings
+#define DENALI_CTL_24_VAL_CFG2	0x0000000200500000LL
+#define DENALI_CTL_25_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG2	0x9340492793404927LL
+#define DENALI_CTL_27_VAL_CFG2	0x9340492793404927LL
+#define DENALI_CTL_28_VAL_CFG2	0x07c0040107c00401LL
+#define DENALI_CTL_29_VAL_CFG2	0x07c0040107c00401LL
+#define DENALI_CTL_30_VAL_CFG2	0x0000000000000004LL
+#define DENALI_CTL_31_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG2	0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG2	0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG2	0x0000000000000000LL
+// original settings
+// #define DENALI_CTL_35_VAL_CFG2	0x0034343434050000LL
+// Dror's settings
+#define DENALI_CTL_35_VAL_CFG2	0x0074747474030000LL
+#define DENALI_CTL_36_VAL_CFG2	0x0000000000000004LL
+// original settings
+// #define DENALI_CTL_37_VAL_CFG2	0x0a52000000040000LL
+// Dror's settings rtt=11 bit[1]=1
+#define DENALI_CTL_37_VAL_CFG2	0x0442000000040200LL
+#define DENALI_CTL_38_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG2	0x0000000000000000LL
+// original settings
+// #define DENALI_CTL_40_VAL_CFG2	0x00000000000000c8LL
+// Dror's settings
+#define DENALI_CTL_40_VAL_CFG2	0x0000000000000064LL
+// #define DENALI_CTL_41_VAL_CFG2	0x00cc005000cc0050LL
+// original settings
+// #define DENALI_CTL_41_VAL_CFG2	0x0017005000170050LL
+// Dror's settings adj1 = 0x28 
+#define DENALI_CTL_41_VAL_CFG2	0x0028009000280090LL
+#define DENALI_CTL_42_VAL_CFG2	DENALI_CTL_41_VAL_CFG2
+#define DENALI_CTL_43_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_44_VAL_CFG2	DENALI_CTL_43_VAL_CFG2
+#define DENALI_CTL_45_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG2	0x0000000000000000LL
+// original settings
+// #define DENALI_CTL_49_VAL_CFG2	0x0000000000000050LL
+// Dror's settings
+#define DENALI_CTL_49_VAL_CFG2	0x0000000000000028LL
+#define DENALI_CTL_50_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG2	0x0000000000000000LL
+// #define DENALI_CTL_63_VAL_CFG2	0x0000000000000000LL
+// #define DENALI_CTL_64_VAL_CFG2	0x0000000000000000LL
+// #define DENALI_CTL_65_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_66_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG2	0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG2	0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG2	0x00000003e8050000LL
+
+#endif /* __M8325XG_H */

include/configs/m8326XG.h

diff --git a/include/configs/m8326XG.h b/include/configs/m8326XG.h
new file mode 100644
index 0000000..a068301
--- /dev/null
+++ b/include/configs/m8326XG.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __M8326XG_H
+#define __M8326XG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_M8326XG       1
+
+#define CFG_CLK	CFG_CLK_650_187_375
+//#define CFG_CLK CFG_CLK_650_200_200
+
+#define ADJ2_MIN_VAL     90
+#define ADJ2_MAX_VAL    150
+
+#define ADJ2_MIN_ACCEPTED_RANGE     20    /* adj2_val1: error */
+#define ADJ2_ACCEPTED_RANGE         25    /* adj2_val2: warning */
+
+#define ADJ1_MIN_VAL     1
+#define ADJ1_MAX_VAL    80
+
+#define ADJ1_MIN_ACCEPTED_WINDOW    18     /* adj1_val1: ignore */
+#define ADJ1_ACCEPTED_WINDOW        23     /* adj1_val2: warning */
+
+// DDR Configs
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #1
+#define DENALI_CTL_00_VAL_CFG1   0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG1   0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG1   0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG1   0x0202020202020202LL
+
+#define DENALI_CTL_05_VAL_CFG1   0x0003010500020001LL
+#define DENALI_CTL_06_VAL_CFG1   0x0A0A040300030400LL
+#define DENALI_CTL_07_VAL_CFG1   0x000000050000020ALL
+#define DENALI_CTL_08_VAL_CFG1   0x6400003F3F150212LL
+#define DENALI_CTL_09_VAL_CFG1   0x0000640064006400LL
+
+#define DENALI_CTL_11_VAL_CFG1   0x0000003100000000LL
+#define DENALI_CTL_12_VAL_CFG1   0x0000000000001200LL
+#define DENALI_CTL_13_VAL_CFG1   0x0010001000100010LL
+#define DENALI_CTL_14_VAL_CFG1   0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG1   0x0B60000000000000LL
+#define DENALI_CTL_16_VAL_CFG1   0x0000000066530000LL
+#define DENALI_CTL_17_VAL_CFG1   0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG1   0x0600010000000000LL
+#define DENALI_CTL_19_VAL_CFG1   0x00003400C8050B00LL
+#define DENALI_CTL_20_VAL_CFG1   0x0000010125B400C8LL
+#define DENALI_CTL_21_VAL_CFG1   0x0202020100000101LL
+#define DENALI_CTL_22_VAL_CFG1   0x0000020007000002LL
+
+#define DENALI_CTL_24_VAL_CFG1   0x0000000200970000LL
+#define DENALI_CTL_25_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG1   0x9400593794005937LL
+#define DENALI_CTL_27_VAL_CFG1   DENALI_CTL_26_VAL_CFG1
+#define DENALI_CTL_28_VAL_CFG1   0x07C0040107C00401LL
+#define DENALI_CTL_29_VAL_CFG1   DENALI_CTL_28_VAL_CFG1
+#define DENALI_CTL_30_VAL_CFG1   0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG1   0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG1   0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG1   0x0078787878050000LL
+#define DENALI_CTL_36_VAL_CFG1   0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG1   0x0A52000000040200LL
+#define DENALI_CTL_38_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG1   0x00000000000000c8LL
+#define DENALI_CTL_41_VAL_CFG1   0x0020138100201381LL
+#define DENALI_CTL_42_VAL_CFG1   DENALI_CTL_41_VAL_CFG1
+#define DENALI_CTL_43_VAL_CFG1   0x0000130000001300LL
+#define DENALI_CTL_44_VAL_CFG1   DENALI_CTL_43_VAL_CFG1
+#define DENALI_CTL_45_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG1   0x0000000000000050LL
+#define DENALI_CTL_50_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG1   0x0000000000000000LL
+
+#define DENALI_CTL_66_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG1   0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG1   0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG1   0x00000003e8050000LL
+
+
+//DENALI CONFIGRATION FOR BOARD CONFIG #2
+#define DENALI_CTL_00_VAL_CFG2   0x0100000101010101LL
+#define DENALI_CTL_01_VAL_CFG2   0x0100010001000000LL
+#define DENALI_CTL_02_VAL_CFG2   0x0200000000010100LL
+#define DENALI_CTL_03_VAL_CFG2   0x0202020202020202LL
+// #define DENALI_CTL_04_VAL_CFG2
+#define DENALI_CTL_05_VAL_CFG2   0x0003010400020001LL
+#define DENALI_CTL_06_VAL_CFG2   0x080A030200020300LL
+#define DENALI_CTL_07_VAL_CFG2   0x0000000300000207LL
+#define DENALI_CTL_08_VAL_CFG2   0x6400003F3F0C020ALL
+#define DENALI_CTL_09_VAL_CFG2   0x0000640064006400LL
+// #define DENALI_CTL_10_VAL_CFG2
+#define DENALI_CTL_11_VAL_CFG2   0x0000001A00000000LL
+#define DENALI_CTL_12_VAL_CFG2   0x0000000000000A00LL
+#define DENALI_CTL_13_VAL_CFG2   0x0010001000100010LL
+#define DENALI_CTL_14_VAL_CFG2   0x0010001000100010LL
+#define DENALI_CTL_15_VAL_CFG2   0x0604000000000000LL
+#define DENALI_CTL_16_VAL_CFG2   0x0000000036380000LL
+#define DENALI_CTL_17_VAL_CFG2   0x0000010000000000LL
+#define DENALI_CTL_18_VAL_CFG2   0x0400010000000000LL
+#define DENALI_CTL_19_VAL_CFG2   0x00001C00C8030600LL
+#define DENALI_CTL_20_VAL_CFG2   0x000001009C4000C8LL
+#define DENALI_CTL_21_VAL_CFG2   0x0303030100000101LL
+#define DENALI_CTL_22_VAL_CFG2   0x0000020007000003LL
+// #define DENALI_CTL_23_VAL_CFG2
+#define DENALI_CTL_24_VAL_CFG2   0x0000000200510000LL
+#define DENALI_CTL_25_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_26_VAL_CFG2   0x9440492794404927LL
+#define DENALI_CTL_27_VAL_CFG2   DENALI_CTL_26_VAL_CFG2
+#define DENALI_CTL_28_VAL_CFG2   0x07C0040107C00401LL
+#define DENALI_CTL_29_VAL_CFG2   DENALI_CTL_28_VAL_CFG2
+#define DENALI_CTL_30_VAL_CFG2   0x0000000000000005LL
+#define DENALI_CTL_31_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_32_VAL_CFG2   0x0c02000000000000LL
+#define DENALI_CTL_33_VAL_CFG2   0x0000000000000004LL
+#define DENALI_CTL_34_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_35_VAL_CFG2   0x0046464646030000LL
+#define DENALI_CTL_36_VAL_CFG2   0x0000000000000004LL
+#define DENALI_CTL_37_VAL_CFG2   0x0642000000040200LL
+#define DENALI_CTL_38_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_39_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_40_VAL_CFG2   0x00000000000000c8LL
+#define DENALI_CTL_41_VAL_CFG2   0x003B37EF003B37EFLL
+#define DENALI_CTL_42_VAL_CFG2   DENALI_CTL_41_VAL_CFG2
+#define DENALI_CTL_43_VAL_CFG2   0x0000370000003700LL
+#define DENALI_CTL_44_VAL_CFG2   DENALI_CTL_43_VAL_CFG2
+#define DENALI_CTL_45_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_46_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_47_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_48_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_49_VAL_CFG2   0x0000000000000050LL
+#define DENALI_CTL_50_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_51_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_52_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_53_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_54_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_55_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_56_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_57_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_58_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_59_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_60_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_61_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_62_VAL_CFG2   0x0000000000000000LL
+// #define DENALI_CTL_63_VAL_CFG2
+// #define DENALI_CTL_64_VAL_CFG2
+// #define DENALI_CTL_65_VAL_CFG2
+#define DENALI_CTL_66_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_67_VAL_CFG2   0x0000000000000000LL
+#define DENALI_CTL_68_VAL_CFG2   0x0000000002000000LL
+#define DENALI_CTL_69_VAL_CFG2   0x00000003e8050000LL
+
+#endif /* __M8326XG_H */

include/configs/malindi.h

diff --git a/include/configs/malindi.h b/include/configs/malindi.h
new file mode 100644
index 0000000..f13f625
--- /dev/null
+++ b/include/configs/malindi.h
@@ -0,0 +1,289 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_800			/* It's a SoC */
+#define CONFIG_MALINDI				/* on a Malindi Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+#define CONFIG_EMAC0_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC0_PHYCTRLDIS		1
+
+#undef CONFIG_EMAC1
+#define CONFIG_EMAC1_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC1_PHYCTRLDIS		1
+
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+#define CONFIG_EMAC0_PHY_ADDR		0x0
+
+#define CONFIG_EMAC1_MDCLOCK		2500000
+#define CONFIG_EMAC1_PHY_ADDR		0x0
+
+/*
+ * SPI driver
+ */
+#define CONFIG_SPI				/* define to enable SPI using */
+
+#define CFG_SPI_CLOCK_POLARITY		1		/* Inactive state of serial clock is high */
+#define CFG_SPI_CLOCK_PHASE		1		/* Serial Clock toggles at the start of the first data bit */
+#define CFG_SPI_FRAMESIZE 		8		/* define the SPI frame size in bits. 8-bit supported only */
+
+#define CFG_SPI_CLOCK_SPEED		4000000		/* the SPI speed in Hz */
+
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS			(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET | \
+					 CFG_CMD_MII | CFG_CMD_ELF | CFG_CMD_NAND)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-800 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"tftpdir=.\0"			\
+	"nfsdir=/home/nfs/fsminimal-debian_sarge-0.13\0"			\
+	"mspname=firmware.axf\0"	\
+	"cspname=zImage\0"		\
+	"fsname=fsimage.jffs2\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
+	"updateboot=tftp 1000000 ${tftpdir}/u-boot.bin; erase 1:0-2; cp.b ${fileaddr} 11000000 ${filesize}\0"	\
+	"updatebootNOR=tftp 1000000 ${tftpdir}/u-boot.bin; erase 2:0-2; cp.b ${fileaddr} 80000000 ${filesize}\0"	\
+	"updatecspNOR=tftp 1000000 ${tftpdir}/${cspname}; erase 2:4-31; cp.b ${fileaddr} 80040000 ${filesize}\0"	\
+	"updatemspNOR=tftp 1000000 ${tftpdir}/${mspname}; erase 2:32-63; cp.b ${fileaddr} 80200000 ${filesize}\0"	\
+	"updatecspNAND=tftp 1000000 ${tftpdir}/${cspname}; nand erase 0 200000; nand write.jffs2 ${fileaddr} 0 ${filesize}\0"	\
+	"updatemspNAND=tftp 1000000 ${tftpdir}/${mspname}; nand erase 200000 200000; nand write.jffs2 ${fileaddr} 200000 ${filesize}\0"	\
+	"updatefsNAND=tftp 1000000 ${tftpdir}/${fsname}; nand erase 400000 7c00000; nand write.jffs2 ${fileaddr} 400000 ${filesize}\0"	\
+	"boottt=run setbootargs; tftp 1000000 ${tftpdir}/${mspname}; loadmsp ${fileaddr} ${filesize}; tftp 2000000 ${tftpdir}/${cspname}; bootcomcerto ${fileaddr}\0"	\
+	"bootoo=run setbootargs; loadmsp 80200000 200000; cp.b 80040000 2000000 200000; bootcomcerto 2000000\0"	\
+	"bootaa=run setbootargs; nand read.jffs2 1000000 200000 200000; loadmsp 1000000 200000; nand read.jffs2 2000000 0 200000; bootcomcerto 2000000\0"	\
+	"mtdboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"	\
+	"nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsdir}\0"	\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::eth0\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"setbootargs=run mtdboot addtty addip addmtd\0"
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_ETH1ADDR         00:aa:bb:cc:dd:ff
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+
+#include <cmd_confdefs.h>
+
+/* Include basic MMU support if ELF support is included
+ *
+ * NOTE: keep this stuff after "cmd_confdefs.h" include
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+#define USE_920T_MMU
+#endif
+
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0100000	/* 1 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+#define CFG_FLASH_AM040_DRIVER				/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+//#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH2			0x80000000	/* Flash Bank #2 */
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		2	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1, PHYS_FLASH2}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP1_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	22
+#define CFG_NAND_CLE_GPIO	20
+#define CFG_NAND_ALE_GPIO	21
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=comcerto_nand0,nor0=comcerto_nor0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcerto_nand0:2m(csp),2m(msp),124m(fs);comcerto_nor0:192k(bootloader),64k(bootloader env),1792k(csp),2m(msp)"
+
+#define CFG_REFCLKFREQ		12000000	/* 12 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		133000000	/* 133 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/matisse.h

diff --git a/include/configs/matisse.h b/include/configs/matisse.h
new file mode 100644
index 0000000..c3aecbc
--- /dev/null
+++ b/include/configs/matisse.h
@@ -0,0 +1,235 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO			1
+#define CONFIG_ARM1136 			1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_900		1	/* It's an  SoC */
+#define CONFIG_SUPERMOMBASA		1	/* on an Supermombasa Board     */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+//#ifdef CONFIG_DRIVER_ETHER
+#define CONFIG_EMAC0			1
+//#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x02000000	/* 32 MiB */
+
+#define LINUX_BOOTPARAM_ADDR		0x00800100
+
+#define PHYS_FLASH_1			0x80000000	/* Flash Bank #1 */
+#define PHYS_FLASH_SIZE			0x00800000	/* 8 MiB */
+#define PHYS_FLASH_BANK_SIZE    	0x00800000	/* 8 MiB Banks */
+#define PHYS_FLASH_SECT_SIZE    	0x00010000	/* 64 KiB sectors */
+
+#define PHYS_EEPROM_1			0x11000000	/* EEPROM Bank #1 */
+#define PHYS_EEPROM_SIZE		0x0080000	/* 512 KiB */
+#define PHYS_EEPROM_BANK_SIZE		0x0080000	/* 512 KiB Banks */
+#define PHYS_EEPROM_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define PHYS_NAND_1			0x11400000
+#define PHYS_NAND_SIZE			0x80000000
+
+#define CFG_MONITOR_BASE        	PHYS_FLASH_1
+#define CFG_MONITOR_LEN         	(PHYS_FLASH_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#if CFG_MONITOR_BASE < CFG_FLASH_BASE
+#define CFG_RAMSTART
+#endif
+
+/*
+ * Hardware drivers
+ */
+
+/* define one of these to choose the UART0  or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#undef CONFIG_HWFLOW		/* don't include RTS/CTS flow control support   */
+
+#undef CONFIG_MODEM_SUPPORT	/* disable modem initialization stuff */
+
+#define CONFIG_BOOTDELAY		3
+/* #define CONFIG_ENV_OVERWRITE		1 */
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL |CFG_CMD_PING)
+
+#include <cmd_confdefs.h>
+#define CONFIG_BAUDRATE         115200
+#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT		"Comcerto-900 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+#define CFG_MEMTEST_START	PHYS_SDRAM
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + PHYS_SDRAM_SIZE)
+
+#define BOARD_LATE_INIT
+#define MSP_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_COMCERTO_USE_MII		0
+
+//#define CONFIG_NET_MULTI      1
+
+//#define CONFIG_MII		1	/* MII PHY management           */
+//#define CONFIG_PHY_ADDR	0	/* PHY address                  */
+//#define CONFIG_PHY1_ADDR	1	/* PHY address                  */
+
+#define CFG_FLASH_AM040_DRIVER		1
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+#define CFG_MAX_FLASH_SECT      		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION		1
+
+#define CFG_MAX_FLASH_BANKS		1	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST 		{ PHYS_EEPROM_1}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH		1
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+
+
+#if 0
+#define CFG_ENV_IN_OWN_SECTOR	1
+#define CFG_ENV_ADDR		(PHYS_EEPROM_1 + 2 * PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SIZE		PHYS_EEPROM_SECT_SIZE
+#define CFG_ENV_SECT_SIZE	PHYS_EEPROM_SECT_SIZE
+
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	PHYS_EEPROM_SECT_SIZE
+#else
+#define CFG_ENV_IN_OWN_SECTOR	1
+#define CFG_ENV_ADDR		(PHYS_EEPROM_1 + PHYS_EEPROM_SIZE - 2 * PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SIZE		(2 * PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
+#endif
+#else
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment */
+
+#endif
+
+#define CFG_LOAD_ADDR		0x600000	/* default load address */
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			PHYS_NAND_1
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE	1
+//#define CONFIG_MTD_DEBUG
+//#define CONFIG_MTD_DEBUG_VERBOSE	3
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+/* mtdparts command line support */
+#define MTDIDS_DEFAULT		"nor0=comcertoeeprom.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoeeprom.0:128k(u-boot),64k(env),64k(renv)"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto900\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off \0"					\
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"boot_nfs=nfs 600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 600000\0"						\
+	"rootpath=/home/user/devel/CSP_software/distribution/mindspeed-buildroot/build_arm_nofpu/root\0" \
+	"kernelfile=uImage\0" \
+	"updateboot=protect off 1:0-1\;erase 1:0-1;tftp 1000000 u-boot.bin;cp.b 1000000 11000000 ${filesize}\0" \
+	"updateenv=protect off 2:2;saveenv\0" \
+	""
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext {
+	/* helper variable for board environment handling
+	 *
+	 * env_crc_valid == 0    =>   uninitialised
+	 * env_crc_valid  > 0    =>   environment crc in flash is valid
+	 * env_crc_valid  < 0    =>   environment crc in flash is invalid
+	 */
+	int env_crc_valid;
+};
+
+#endif
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		133000000	/* 133 MHz */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/megamombasa515.h

diff --git a/include/configs/megamombasa515.h b/include/configs/megamombasa515.h
new file mode 100644
index 0000000..1b40f81
--- /dev/null
+++ b/include/configs/megamombasa515.h
@@ -0,0 +1,282 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_515			/* It's a SoC */
+#define CONFIG_MEGAMOMBASA515			/* on a Megamombasa-515 Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+#define CONFIG_EMAC0_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC0_PHYCTRLDIS		1
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+#define CONFIG_EMAC0_PHY_ADDR		0x0
+
+/*
+ * SPI driver
+ */
+#define CONFIG_SPI				/* define to enable SPI using */
+
+#define CFG_SPI_CLOCK_POLARITY		1		/* Inactive state of serial clock is high */
+#define CFG_SPI_CLOCK_PHASE		1		/* Serial Clock toggles at the start of the first data bit */
+#define CFG_SPI_FRAMESIZE 		8		/* define the SPI frame size in bits. 8-bit supported only */
+
+#define CFG_SPI_CLOCK_SPEED		4000000		/* the SPI speed in Hz */
+
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS			(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET | \
+					 CFG_CMD_MII | CFG_CMD_ELF | CFG_CMD_NAND | CFG_CMD_SPI)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-515 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"tftpdir=.\0"			\
+	"nfsdir=/home/nfs/fsminimal-debian_sarge-0.13\0"			\
+	"mspname=firmware.axf\0"	\
+	"cspname=zImage\0"		\
+	"fsname=fsimage.jffs2\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
+	"updateboot=tftp 1000000 ${tftpdir}/u-boot.bin; erase 1:0-2; cp.b ${fileaddr} 11000000 ${filesize}\0"	\
+	"updatebootNOR=tftp 1000000 ${tftpdir}/u-boot.bin; erase 2:0-2; cp.b ${fileaddr} 80000000 ${filesize}\0"	\
+	"updatecspNOR=tftp 1000000 ${tftpdir}/${cspname}; erase 2:4-31; cp.b ${fileaddr} 80040000 ${filesize}\0"	\
+	"updatemspNOR=tftp 1000000 ${tftpdir}/${mspname}; erase 2:32-63; cp.b ${fileaddr} 80200000 ${filesize}\0"	\
+	"updatefsNOR=tftp 1000000 ${tftpdir}/${fsname}; erase 2:64-127; cp.b ${fileaddr} 80400000 ${filesize}\0"	\
+	"updatecspNAND=tftp 1000000 ${tftpdir}/${cspname}; nand erase 0 200000; nand write.jffs2 ${fileaddr} 0 ${filesize}\0"	\
+	"updatemspNAND=tftp 1000000 ${tftpdir}/${mspname}; nand erase 200000 200000; nand write.jffs2 ${fileaddr} 200000 ${filesize}\0"	\
+	"updatefsNAND=tftp 1000000 ${tftpdir}/${fsname}; nand erase 400000 fc00000; nand write.jffs2 ${fileaddr} 400000 ${filesize}\0"	\
+	"boottt=run setbootargs; tftp 1000000 ${tftpdir}/${mspname}; loadmsp ${fileaddr} ${filesize}; tftp 2000000 ${tftpdir}/${cspname}; bootcomcerto ${fileaddr}\0"	\
+	"bootoo=run setbootargs; loadmsp 80200000 200000; cp.b 80040000 2000000 200000; bootcomcerto 2000000\0"	\
+	"bootaa=run setbootargs; nand read.jffs2 1000000 200000 200000; loadmsp 1000000 200000; nand read.jffs2 2000000 0 200000; bootcomcerto 2000000\0"	\
+	"mtdboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"	\
+	"nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsdir}\0"	\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::eth0\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"setbootargs=run mtdboot addtty addip addmtd\0"
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+
+#include <cmd_confdefs.h>
+
+/* Include basic MMU support if ELF support is included
+ *
+ * NOTE: keep this stuff after "cmd_confdefs.h" include
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+#define USE_920T_MMU
+#endif
+
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0100000	/* 1 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+#define CFG_FLASH_AM040_DRIVER				/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+//#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x800000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH2			0x80000000	/* Flash Bank #2 */
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		2	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1, PHYS_FLASH2}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP0_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=comcerto_nand0,nor0=comcerto_nor0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcerto_nand0:2m(csp),2m(msp),252m(fs);comcerto_nor0:192k(bootloader),64k(bootloader env),1792k(csp),2m(msp),4m(fs)"
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		133000000	/* 133 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/megamombasa515_256M.h

diff --git a/include/configs/megamombasa515_256M.h b/include/configs/megamombasa515_256M.h
new file mode 100644
index 0000000..63c311a
--- /dev/null
+++ b/include/configs/megamombasa515_256M.h
@@ -0,0 +1,285 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_515			/* It's a SoC */
+#define CONFIG_MEGAMOMBASA515			/* on a Megamombasa-515 Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs 256M"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		2
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 MiB */
+
+#define PHYS_SDRAM1			0x90000000
+#define PHYS_SDRAM1_SIZE		0x08000000	/* 128 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+#define CONFIG_EMAC0_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC0_PHYCTRLDIS		1
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+#define CONFIG_EMAC0_PHY_ADDR		0x0
+
+/*
+ * SPI driver
+ */
+#define CONFIG_SPI				/* define to enable SPI using */
+
+#define CFG_SPI_CLOCK_POLARITY		1		/* Inactive state of serial clock is high */
+#define CFG_SPI_CLOCK_PHASE		1		/* Serial Clock toggles at the start of the first data bit */
+#define CFG_SPI_FRAMESIZE 		8		/* define the SPI frame size in bits. 8-bit supported only */
+
+#define CFG_SPI_CLOCK_SPEED		4000000		/* the SPI speed in Hz */
+
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS			(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET | \
+					 CFG_CMD_MII | CFG_CMD_ELF | CFG_CMD_NAND | CFG_CMD_SPI)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-515 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"tftpdir=.\0"			\
+	"nfsdir=/home/nfs/fsminimal-debian_sarge-0.13\0"			\
+	"mspname=firmware.axf\0"	\
+	"cspname=zImage\0"		\
+	"fsname=fsimage.jffs2\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
+	"updateboot=tftp 1000000 ${tftpdir}/u-boot.bin; erase 1:0-2; cp.b ${fileaddr} 11000000 ${filesize}\0"	\
+	"updatebootNOR=tftp 1000000 ${tftpdir}/u-boot.bin; erase 2:0-2; cp.b ${fileaddr} 80000000 ${filesize}\0"	\
+	"updatecspNOR=tftp 1000000 ${tftpdir}/${cspname}; erase 2:4-31; cp.b ${fileaddr} 80040000 ${filesize}\0"	\
+	"updatemspNOR=tftp 1000000 ${tftpdir}/${mspname}; erase 2:32-63; cp.b ${fileaddr} 80200000 ${filesize}\0"	\
+	"updatefsNOR=tftp 1000000 ${tftpdir}/${fsname}; erase 2:64-127; cp.b ${fileaddr} 80400000 ${filesize}\0"	\
+	"updatecspNAND=tftp 1000000 ${tftpdir}/${cspname}; nand erase 0 200000; nand write.jffs2 ${fileaddr} 0 ${filesize}\0"	\
+	"updatemspNAND=tftp 1000000 ${tftpdir}/${mspname}; nand erase 200000 200000; nand write.jffs2 ${fileaddr} 200000 ${filesize}\0"	\
+	"updatefsNAND=tftp 1000000 ${tftpdir}/${fsname}; nand erase 400000 fc00000; nand write.jffs2 ${fileaddr} 400000 ${filesize}\0"	\
+	"boottt=run setbootargs; tftp 1000000 ${tftpdir}/${mspname}; loadmsp ${fileaddr} ${filesize}; tftp 2000000 ${tftpdir}/${cspname}; bootcomcerto ${fileaddr}\0"	\
+	"bootoo=run setbootargs; loadmsp 80200000 200000; cp.b 80040000 2000000 200000; bootcomcerto 2000000\0"	\
+	"bootaa=run setbootargs; nand read.jffs2 1000000 200000 200000; loadmsp 1000000 200000; nand read.jffs2 2000000 0 200000; bootcomcerto 2000000\0"	\
+	"mtdboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"	\
+	"nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsdir}\0"	\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::eth0\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"setbootargs=run mtdboot addtty addip addmtd\0"
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+
+#include <cmd_confdefs.h>
+
+/* Include basic MMU support if ELF support is included
+ *
+ * NOTE: keep this stuff after "cmd_confdefs.h" include
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+#define USE_920T_MMU
+#endif
+
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0100000	/* 1 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+#define CFG_FLASH_AM040_DRIVER				/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+//#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x800000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH2			0x80000000	/* Flash Bank #2 */
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		2	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1, PHYS_FLASH2}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP0_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=comcerto_nand0,nor0=comcerto_nor0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcerto_nand0:2m(csp),2m(msp),252m(fs);comcerto_nor0:192k(bootloader),64k(bootloader env),1792k(csp),2m(msp),4m(fs)"
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		133000000	/* 133 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/megamombasa515_sdc1.h

diff --git a/include/configs/megamombasa515_sdc1.h b/include/configs/megamombasa515_sdc1.h
new file mode 100644
index 0000000..d66d93c
--- /dev/null
+++ b/include/configs/megamombasa515_sdc1.h
@@ -0,0 +1,282 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_515			/* It's a SoC */
+#define CONFIG_MEGAMOMBASA515			/* on a Megamombasa-515 Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs SDC1"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+#define CONFIG_EMAC0_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC0_PHYCTRLDIS		1
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+#define CONFIG_EMAC0_PHY_ADDR		0x0
+
+/*
+ * SPI driver
+ */
+#define CONFIG_SPI				/* define to enable SPI using */
+
+#define CFG_SPI_CLOCK_POLARITY		1		/* Inactive state of serial clock is high */
+#define CFG_SPI_CLOCK_PHASE		1		/* Serial Clock toggles at the start of the first data bit */
+#define CFG_SPI_FRAMESIZE 		8		/* define the SPI frame size in bits. 8-bit supported only */
+
+#define CFG_SPI_CLOCK_SPEED		4000000		/* the SPI speed in Hz */
+
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS			(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET | \
+					 CFG_CMD_MII | CFG_CMD_ELF | CFG_CMD_NAND | CFG_CMD_SPI)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-515 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"tftpdir=.\0"			\
+	"nfsdir=/home/nfs/fsminimal-debian_sarge-0.13\0"			\
+	"mspname=firmware.axf\0"	\
+	"cspname=zImage\0"		\
+	"fsname=fsimage.jffs2\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
+	"updateboot=tftp 1000000 ${tftpdir}/u-boot.bin; erase 1:0-2; cp.b ${fileaddr} 11000000 ${filesize}\0"	\
+	"updatebootNOR=tftp 1000000 ${tftpdir}/u-boot.bin; erase 2:0-2; cp.b ${fileaddr} 80000000 ${filesize}\0"	\
+	"updatecspNOR=tftp 1000000 ${tftpdir}/${cspname}; erase 2:4-31; cp.b ${fileaddr} 80040000 ${filesize}\0"	\
+	"updatemspNOR=tftp 1000000 ${tftpdir}/${mspname}; erase 2:32-63; cp.b ${fileaddr} 80200000 ${filesize}\0"	\
+	"updatefsNOR=tftp 1000000 ${tftpdir}/${fsname}; erase 2:64-127; cp.b ${fileaddr} 80400000 ${filesize}\0"	\
+	"updatecspNAND=tftp 1000000 ${tftpdir}/${cspname}; nand erase 0 200000; nand write.jffs2 ${fileaddr} 0 ${filesize}\0"	\
+	"updatemspNAND=tftp 1000000 ${tftpdir}/${mspname}; nand erase 200000 200000; nand write.jffs2 ${fileaddr} 200000 ${filesize}\0"	\
+	"updatefsNAND=tftp 1000000 ${tftpdir}/${fsname}; nand erase 400000 fc00000; nand write.jffs2 ${fileaddr} 400000 ${filesize}\0"	\
+	"boottt=run setbootargs; tftp 1000000 ${tftpdir}/${mspname}; loadmsp ${fileaddr} ${filesize}; tftp 2000000 ${tftpdir}/${cspname}; bootcomcerto ${fileaddr}\0"	\
+	"bootoo=run setbootargs; loadmsp 80200000 200000; cp.b 80040000 2000000 200000; bootcomcerto 2000000\0"	\
+	"bootaa=run setbootargs; nand read.jffs2 1000000 200000 200000; loadmsp 1000000 200000; nand read.jffs2 2000000 0 200000; bootcomcerto 2000000\0"	\
+	"mtdboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"	\
+	"nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsdir}\0"	\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::eth0\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"setbootargs=run mtdboot addtty addip addmtd\0"
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+
+#include <cmd_confdefs.h>
+
+/* Include basic MMU support if ELF support is included
+ *
+ * NOTE: keep this stuff after "cmd_confdefs.h" include
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+#define USE_920T_MMU
+#endif
+
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0100000	/* 1 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+#define CFG_FLASH_AM040_DRIVER				/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+//#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x800000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH2			0x80000000	/* Flash Bank #2 */
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		2	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1, PHYS_FLASH2}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP0_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=comcerto_nand0,nor0=comcerto_nor0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcerto_nand0:2m(csp),2m(msp),252m(fs);comcerto_nor0:192k(bootloader),64k(bootloader env),1792k(csp),2m(msp),4m(fs)"
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		133000000	/* 133 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/moca.h

diff --git a/include/configs/moca.h b/include/configs/moca.h
new file mode 100644
index 0000000..7c33d70
--- /dev/null
+++ b/include/configs/moca.h
@@ -0,0 +1,309 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_100	1	/* It's an  SoC */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE		0x08000000	/* 128 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_GMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	GEMAC_NO_PHY
+#define GEMAC1_PHYIDX		0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET /* | CFG_CMD_NAND */ | CFG_CMD_JFFS2 | CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_MII | CFG_CMD_I2C | CFG_CMD_EEPROM)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-100 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto100\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-moca\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+	"updatefs=tftp 81000000 ${fsfile};protect off 1:3-127\;erase 1:3-127;cp.b 81000000 20060000 ${filesize}\0" \
+	"updateboot=tftp 81000000 u-boot.bin;protect off 1:0-1\;erase 1:0-1;cp.b 81000000 20000000 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0x20000000	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+#endif
+
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#if !defined(LITTLE_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x56
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#else
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        1 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+#endif
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment 16KiB */
+  
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+/* NO NAND ON MoCA EVM */
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		165000000	/* 165 MHz, must be multiple of 33MHz */
+#define CFG_ARM_CLOCK		450000000	/* 450 MHz, must be multiple of 25MHz */
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00010000 /* 64K */
+#define CFG_ARAM_CODE_SIZE	0x00008000 /* 32K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#define DDR_TRAINING_DBG 
+
+/* New DDR training defines (Bug #44131) */
+#define NEW_DDR_TRAINING  //undef this for old training
+//#undef NEW_DDR_TRAINING  //undef this for old training
+
+#endif /* __CONFIG_H */

include/configs/moca_aram.h

diff --git a/include/configs/moca_aram.h b/include/configs/moca_aram.h
new file mode 100644
index 0000000..db7d912
--- /dev/null
+++ b/include/configs/moca_aram.h
@@ -0,0 +1,297 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_100	1	/* It's an  SoC */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_UBOOT_LOADED_IN_ARAM
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE		0x08000000	/* 128 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#undef CONFIG_COMCERTO_GEMAC
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_GMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	GEMAC_NO_PHY
+#define GEMAC1_PHYIDX		0
+
+#undef CONFIG_NET_MULTI
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | /*CFG_CMD_ENV |*/ CFG_CMD_MEMORY | CFG_CMD_RUN /*| CFG_CMD_NET |  CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM */)
+
+#define CONFIG_NO_GZIP		1
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-100 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto100\0"						\
+	"netdev=eth0\0"									\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"boot_flash=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"writeboot=protect off 1:0-1\;erase 1:0-1;cp.b 81000000 20000000 40000\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0x20000000	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+#endif
+
+
+/*
+ * I2C support
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#if !defined(LITTLE_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x56
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#else
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        1 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+#endif
+
+/*
+ * Enviroment in flash
+ */
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_NOWHERE	1
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment 16KiB */
+  
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+/* NO NAND ON MoCA EVM */
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		165000000	/* 165 MHz, must be multiple of 33MHz */
+#define CFG_ARM_CLOCK		450000000	/* 450 MHz, must be multiple of 25MHz */
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00010000 /* 64K */
+#define CFG_ARAM_CODE_SIZE	0x00000400 /* 1K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#define DDR_TRAINING_DBG 
+
+/* New DDR training defines (Bug #44131) */
+#define NEW_DDR_TRAINING  //undef this for old training
+//#undef NEW_DDR_TRAINING  //undef this for old training
+
+#endif /* __CONFIG_H */

include/configs/nairobi.h

diff --git a/include/configs/nairobi.h b/include/configs/nairobi.h
new file mode 100644
index 0000000..f26350b
--- /dev/null
+++ b/include/configs/nairobi.h
@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_800			/* It's a SoC */
+#define CONFIG_SUPERMOMBASA			/* on a Supermombasa Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+#define CONFIG_EMAC0_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC0_PHYCTRLDIS		1
+
+#undef CONFIG_EMAC1
+#define CONFIG_EMAC1_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC1_PHYCTRLDIS		1
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+#define CONFIG_EMAC0_PHY_ADDR		0x0
+
+#define CONFIG_EMAC1_MDCLOCK		2500000
+#define CONFIG_EMAC1_PHY_ADDR		0x0
+
+/*
+ * SPI driver
+ */
+#define CONFIG_SPI				/* define to enable SPI using */
+
+#define CFG_SPI_CLOCK_POLARITY		1		/* Inactive state of serial clock is high */
+#define CFG_SPI_CLOCK_PHASE		1		/* Serial Clock toggles at the start of the first data bit */
+#define CFG_SPI_FRAMESIZE 		8		/* define the SPI frame size in bits. 8-bit supported only */
+
+#define CFG_SPI_CLOCK_SPEED		4000000		/* the SPI speed in Hz */
+
+
+/*
+ * Shell configuration
+ */
+#include <cmd_confdefs.h>
+
+#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | CFG_CMD_MII |CFG_CMD_JFFS2 |CFG_CMD_PING)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-800 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_ETH1ADDR         00:aa:bb:cc:dd:ff
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+#define CFG_FLASH_AM040_DRIVER				/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH2			0x80000000	/* Flash Bank #2 */
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		2	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1, PHYS_FLASH2}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP0_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=Amd-eeprom,nor1=Spansion-flash"
+#define MTDPARTS_DEFAULT	"mtdparts=Spansion-flash:512k(u-boot),512k(env),7m(fs)"
+
+#define CFG_REFCLKFREQ		12000000	/* 12 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		132000000	/* 132 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/packet-iad-nand.h

diff --git a/include/configs/packet-iad-nand.h b/include/configs/packet-iad-nand.h
new file mode 100644
index 0000000..c80c31b
--- /dev/null
+++ b/include/configs/packet-iad-nand.h
@@ -0,0 +1,342 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_100	1	/* It's an  SoC */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE		0x08000000	/* 128 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_GMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	GEMAC_NO_PHY
+#define GEMAC1_PHYIDX		0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+//To enable only NOR uncomment CFG_CMD_FLASH and comment CFG_CMD_NAND
+//To enable only NAND uncomment CFG_CMD_NAND  and comment CFG_CMD_FLASH
+//#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_JFFS2 | CFG_CMD_PING)
+#define CONFIG_COMMANDS		(/* CFG_CMD_FLASH | */ CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET |  CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_MII)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-100 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto100\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root="ROOT_MTDBLOCK " rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; uload /boot/uImage; bootm\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-iad\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+	"updatenandfs=tftp 81000000 ${fsfile};nand erase 60000 ${filesize};nand write.jffs2 81000000 60000 ${filesize}\0" \
+	"updatenandboot=tftp 81000000 u-boot.bin;nand erase 0 40000;nand write.jffs2 81000000 0 40000\0" \
+	"eepromfile=eeprom.bin\0" \
+	"updateeprom=tftp 81000000 ${eepromfile};eeprom write 81000000 0 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+#else
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+#endif
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0x20000000	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define EXP_CSP4_BASEADDR		0x30000000
+
+
+#define CFG_NAND_BASE			EXP_CSP4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		165000000	/* 165 MHz, must be multiple of 33MHz */
+#if 0 /* CFG_ARM_CLOCK configuration is pushing from u-boot Makefile into config.h based on the SKU */
+#define CFG_ARM_CLOCK		450000000	/* 450 MHz, must be multiple of 25MHz */
+#endif
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00010000 /* 64K */
+#define CFG_ARAM_CODE_SIZE	0x00008000 /* 32K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#endif /* __CONFIG_H */

include/configs/packet-iad.h

diff --git a/include/configs/packet-iad.h b/include/configs/packet-iad.h
new file mode 100644
index 0000000..b152748
--- /dev/null
+++ b/include/configs/packet-iad.h
@@ -0,0 +1,344 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_100	1	/* It's an  SoC */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE		0x08000000	/* 128 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_GMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	GEMAC_NO_PHY
+#define GEMAC1_PHYIDX		0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET |  /*CFG_CMD_NAND | */CFG_CMD_JFFS2 | CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_ELF  | CFG_CMD_I2C | CFG_CMD_EEPROM  | CFG_CMD_MII)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-100 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto100\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; uload /boot/uImage; bootm\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-iad\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+	"updatenandfs=tftp 81000000 ${fsfile};nand erase 60000 880000;nand write 81000000 60000 880000\0" \
+ 	"updatefs=tftp 81000000 ${fsfile};protect off 1:3-127\;erase 1:3-127;cp.b 81000000 20060000 ${filesize}\0" \
+	"updateboot=tftp 81000000 u-boot.bin;protect off 1:0-1\;erase 1:0-1;cp.b 81000000 20000000 ${filesize}\0" \
+	"eepromfile=eeprom.bin\0" \
+	"updateeprom=tftp 81000000 ${eepromfile};eeprom write 81000000 0 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+#else
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+#endif
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0x20000000	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define EXP_CSP4_BASEADDR		0x30000000
+
+
+#define CFG_NAND_BASE			EXP_CSP4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		165000000	/* 165 MHz, must be multiple of 33MHz */
+#if 0 /* CFG_ARM_CLOCK configuration is pushing from u-boot Makefile into config.h based on the SKU */
+#define CFG_ARM_CLOCK		450000000	/* 450 MHz, must be multiple of 25MHz */
+#endif
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00010000 /* 64K */
+#define CFG_ARAM_CODE_SIZE	0x00008000 /* 32K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+ * DDR Training algorithm
+ */
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#define DDR_TRAINING_DBG 
+
+/* New DDR training defines (Bug #44131) */
+#define NEW_DDR_TRAINING  //undef this for old training
+//#undef  NEW_DDR_TRAINING  //undef this for old training
+
+#endif /* __CONFIG_H */

include/configs/packet-iad_aram.h

diff --git a/include/configs/packet-iad_aram.h b/include/configs/packet-iad_aram.h
new file mode 100644
index 0000000..83f864c
--- /dev/null
+++ b/include/configs/packet-iad_aram.h
@@ -0,0 +1,302 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_100	1	/* It's an  SoC */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_UBOOT_LOADED_IN_ARAM
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE		0x08000000	/* 128 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#undef CONFIG_COMCERTO_GEMAC
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_GMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	GEMAC_NO_PHY
+#define GEMAC1_PHYIDX		0
+
+#undef CONFIG_NET_MULTI
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | /*CFG_CMD_ENV |*/ CFG_CMD_MEMORY | CFG_CMD_RUN /*| CFG_CMD_NET |  CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM */)
+
+#define CONFIG_NO_GZIP		1
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-100 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto100\0"						\
+	"netdev=eth0\0"									\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"boot_flash=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"writeboot=protect off 1:0-1\;erase 1:0-1;cp.b 81000000 20000000 40000\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0x20000000	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+#endif
+
+/*
+ * I2C support
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+/*
+ * Enviroment in flash
+ */
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_NOWHERE	1
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 2 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment 16KiB */
+  
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		165000000	/* 165 MHz, must be multiple of 33MHz */
+#if 0 /* CFG_ARM_CLOCK configuration is pushing from u-boot Makefile into config.h based on the SKU */
+#define CFG_ARM_CLOCK		450000000	/* 450 MHz, must be multiple of 25MHz */
+#endif
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00010000 /* 64K */
+#define CFG_ARAM_CODE_SIZE	0x00000400 /* 1K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#define DDR_TRAINING_DBG 
+
+/* New DDR training defines (Bug #44131) */
+#define NEW_DDR_TRAINING  //undef this for old training
+//#undef  NEW_DDR_TRAINING  //undef this for old training
+
+#endif /* __CONFIG_H */

include/configs/router-nand.h

diff --git a/include/configs/router-nand.h b/include/configs/router-nand.h
new file mode 100644
index 0000000..76a366c
--- /dev/null
+++ b/include/configs/router-nand.h
@@ -0,0 +1,343 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_100	1	/* It's an  SoC */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE		0x04000000	/* 64 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	GEMAC_NO_PHY
+#define GEMAC1_PHYIDX		0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+//To enable only NOR uncomment CFG_CMD_FLASH and comment CFG_CMD_NAND
+//To enable only NAND uncomment CFG_CMD_NAND  and comment CFG_CMD_FLASH
+//#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_JFFS2 | CFG_CMD_PING)
+#define CONFIG_COMMANDS		(/*CFG_CMD_FLASH |*/ CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET |  CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_MII)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-100 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto100\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root="ROOT_MTDBLOCK " rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; uload /boot/uImage; bootm\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-router\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-128k\0" \
+	"updatenandfs=tftp 81000000 ${fsfile};nand erase 60000 ${filesize};nand write.jffs2 81000000 60000 ${filesize}\0" \
+	"updatenandboot=tftp 81000000 u-boot.bin;nand erase 0 40000;nand write.jffs2 81000000 0 40000\0" \
+	"eepromfile=eeprom.bin\0" \
+	"updateeprom=tftp 81000000 ${eepromfile};eeprom write 81000000 0 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+#else
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+#endif
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0x20000000	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (2 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
+#endif
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 4 * PHYS_FLASH1_SECT_SIZE)	/* Keep 4 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+  
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define EXP_CSP4_BASEADDR		0x30000000
+
+
+#define CFG_NAND_BASE			EXP_CSP4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+//TODO
+#else
+/*
+ *EEPORM boot loader does the relocate and lowlevel init work
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Environment is in NAND */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define NAND_MAX_CHIPS          1
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
+#endif
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+//#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=comcertonand"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nand0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock3"
+#else
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+#define ROOT_MTDBLOCK		"/dev/mtdblock2"
+#endif
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		165000000	/* 165 MHz, must be multiple of 33MHz */
+#if 0 /* CFG_ARM_CLOCK configuration is pushing from u-boot Makefile into config.h based on the SKU */
+#define CFG_ARM_CLOCK		450000000	/* 450 MHz, must be multiple of 25MHz */
+#endif
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00010000 /* 64K */
+#define CFG_ARAM_CODE_SIZE	0x00008000 /* 32K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#endif /* __CONFIG_H */

include/configs/router.h

diff --git a/include/configs/router.h b/include/configs/router.h
new file mode 100644
index 0000000..cd1bbd6
--- /dev/null
+++ b/include/configs/router.h
@@ -0,0 +1,316 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_100	1	/* It's an  SoC */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE		0x04000000	/* 64 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#define CONFIG_COMCERTO_GEMAC	1
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	GEMAC_NO_PHY
+#define GEMAC1_PHYIDX		0
+
+#define CONFIG_NET_MULTI	1
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET |  /*CFG_CMD_NAND |*/ CFG_CMD_JFFS2 | CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_SPI | CFG_CMD_ELF | CFG_CMD_MII)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-100 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto100\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 80600000\0"						\
+	"boot_flash=run flashargs addeth addtty addmtd; uload /boot/uImage; bootm\0" \
+	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"rootpath=/devel/fs-router\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"fsfile=root.jffs2-64k\0" \
+	"updatefs=tftp 81000000 ${fsfile};protect off 1:6-255\;erase 1:6-255;cp.b 81000000 20060000 ${filesize}\0" \
+	"updateboot=tftp 81000000 u-boot.bin;protect off 1:0-3\;erase 1:0-3;cp.b 81000000 20000000 ${filesize}\0" \
+	"eepromfile=eeprom.bin\0" \
+	"updateeprom=tftp 81000000 ${eepromfile};eeprom write 81000000 0 ${filesize}\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_BOOTDELAY	3
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0x20000000	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+
+#define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (2 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+
+/*
+ * I2C support
+ */
+#if defined(CFG_CMD_I2C)
+#define CONFIG_HARD_I2C
+#define CFG_TCLK                       CFG_HZ_CLOCK
+#define CFG_I2C_SPEED                  40000
+#define CFG_I2C_SLAVE                  0
+#if defined(CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR            0x50
+#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#endif
+#endif
+
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 4 * PHYS_FLASH1_SECT_SIZE)	/* Keep 4 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment 16KiB */
+  
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		165000000	/* 165 MHz, must be multiple of 33MHz */
+#if 0 /* CFG_ARM_CLOCK configuration is pushing from u-boot Makefile into config.h based on the SKU */
+#define CFG_ARM_CLOCK		450000000	/* 450 MHz, must be multiple of 25MHz */
+#endif
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00010000 /* 64K */
+#define CFG_ARAM_CODE_SIZE	0x00008000 /* 32K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+#define DDR_TRAINING_DBG 
+
+/* New DDR training defines (Bug #44131) */
+#define NEW_DDR_TRAINING  //undef this for old training
+//#undef NEW_DDR_TRAINING  //undef this for old training
+
+#endif /* __CONFIG_H */

include/configs/router_aram.h

diff --git a/include/configs/router_aram.h b/include/configs/router_aram.h
new file mode 100644
index 0000000..14fdd8a
--- /dev/null
+++ b/include/configs/router_aram.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO		1
+#define CONFIG_ARM1136 		1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_100	1	/* It's an  SoC */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00_1 $"
+
+/*
+ * Linux boot configuration
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)
+
+/*
+ *	Relocation options
+ */
+#define CONFIG_UBOOT_LOADED_IN_ARAM
+//#define CONFIG_SKIP_RELOCATE_UBOOT
+//#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * RAM configuration
+ */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE		0x04000000	/* 64 MB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */  
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0		1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+/*
+ * Emac Settings
+ */
+#undef CONFIG_COMCERTO_GEMAC
+
+// GEMAC mode configured by bootstrap pins or SW
+#undef CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+//#define CONFIG_COMCERTO_MII_CFG_BOOTSTRAP
+
+#define GEMAC0_PHY_ADDR		0
+#define GEMAC0_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC0_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC0_PHY_FLAGS	GEMAC_PHY_AUTONEG
+#define GEMAC0_PHYIDX		0
+
+#define GEMAC1_PHY_ADDR		0
+#define GEMAC1_CONFIG		CONFIG_COMCERTO_USE_RGMII
+#define GEMAC1_MODE		(GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G)
+#define GEMAC1_PHY_FLAGS	GEMAC_NO_PHY
+#define GEMAC1_PHYIDX		0
+
+#undef CONFIG_NET_MULTI
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS		(CFG_CMD_FLASH | /*CFG_CMD_ENV |*/ CFG_CMD_MEMORY | CFG_CMD_RUN /*| CFG_CMD_NET |  CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_PING | CFG_CMD_NFS | CFG_CMD_I2C | CFG_CMD_EEPROM */)
+
+#define CONFIG_NO_GZIP		1
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-100 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto100\0"						\
+	"netdev=eth0\0"									\
+	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock2 rootfstype=${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"init_process=/etc/preinit\0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"boot_flash=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
+	"kernelfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=" MTDPARTITION_DEFAULT "\0" \
+	"mtddevnum=2\0" \
+	"mtddevname=fs\0" \
+	"writeboot=protect off 1:0-3\;erase 1:0-3;cp.b 81000000 20000000 40000\0" \
+	""
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+
+#include <cmd_confdefs.h>
+
+#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */
+
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
+#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
+//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		256	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH1			0x20000000	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+
+#define CFG_FLASH_COMPLEX_MAPPINGS
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        PHYS_FLASH1
+#define CFG_MONITOR_LEN         (2 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_NOWHERE	1
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR		(PHYS_FLASH1 + 4 * PHYS_FLASH1_SECT_SIZE)	/* Keep 4 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment 16KiB */
+  
+#define CONFIG_ENV_OVERWRITE	1
+
+
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP4_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	6
+#define CFG_NAND_CE_GPIO	29
+#define CFG_NAND_CLE_GPIO	31
+#define CFG_NAND_ALE_GPIO	30
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:256k(u-boot),128k(env),16000k(fs)"
+#define MTDPARTITION_DEFAULT	"nor0,2"
+
+#define CFG_REFCLKFREQ		24000000	/* 24 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		165000000	/* 165 MHz, must be multiple of 33MHz */
+#if 0 /* CFG_ARM_CLOCK configuration is pushing from u-boot Makefile into config.h based on the SKU */
+#define CFG_ARM_CLOCK		450000000	/* 450 MHz, must be multiple of 25MHz */
+#endif
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR	0x0A000000 /* ARAM_BASEADDR Base address */
+#define CFG_INIT_RAM_END	0x00010000 /* 64K */
+#define CFG_ARAM_CODE_SIZE	0x00000400 /* 1K */
+
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE
+
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+/*
+* DDR Training algorithm
+*/
+#define DDR_TRAINING
+//#undef DDR_TRAINING
+
+#define DDR_TRAINING_DBG 
+
+/* New DDR training defines (Bug #44131) */
+#define NEW_DDR_TRAINING  //undef this for old training
+//#undef NEW_DDR_TRAINING  //undef this for old training
+
+
+#endif /* __CONFIG_H */

include/configs/supermombasa910.h

diff --git a/include/configs/supermombasa910.h b/include/configs/supermombasa910.h
new file mode 100644
index 0000000..b1e95ac
--- /dev/null
+++ b/include/configs/supermombasa910.h
@@ -0,0 +1,247 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO			1
+#define CONFIG_ARM1136 			1	/* This is an arm1136j-s CPU core */
+#define CONFIG_COMCERTO_900		1	/* It's an  SoC */
+#define CONFIG_SUPERMOMBASA		1	/* on an Supermombasa Board     */
+#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+/*
+ * Memory Mapping
+ */
+
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 MiB */
+
+#define LINUX_BOOTPARAM_ADDR		0x0800100
+
+#define PHYS_FLASH_1			0x80000000	/* Flash Bank #1 */
+#define PHYS_FLASH_SIZE			0x00800000	/* 8 MiB */
+#define PHYS_FLASH_BANK_SIZE    	0x00800000	/* 8 MiB Banks */
+#define PHYS_FLASH_SECT_SIZE    	0x00010000	/* 64 KiB sectors */
+
+#define PHYS_EEPROM_1			0x11000000	/* EEPROM Bank #1 */
+#define PHYS_EEPROM_SIZE		0x0080000	/* 512 KiB */
+#define PHYS_EEPROM_BANK_SIZE		0x0080000	/* 512 KiB Banks */
+#define PHYS_EEPROM_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define PHYS_NAND_1			0x11400000
+#define PHYS_NAND_SIZE			0x80000000
+
+#define CFG_MONITOR_BASE        	PHYS_FLASH_1
+#define CFG_MONITOR_LEN         	(PHYS_FLASH_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#if CFG_MONITOR_BASE < CFG_FLASH_BASE
+#define CFG_RAMSTART
+#endif
+
+/*
+ * Hardware drivers
+ */
+
+/* define one of these to choose the UART0  or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#undef	CONFIG_HWFLOW		/* don't include RTS/CTS flow control support   */
+
+#undef	CONFIG_MODEM_SUPPORT	/* disable modem initialization stuff */
+
+#define CONFIG_BOOTDELAY		3
+/* #define CONFIG_ENV_OVERWRITE		1 */
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_JFFS2 | CFG_CMD_PING)
+
+#include <cmd_confdefs.h>
+#define CONFIG_BAUDRATE         115200
+#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT		"Comcerto-900 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+#define CFG_MEMTEST_START	PHYS_SDRAM
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + PHYS_SDRAM_SIZE)
+
+#define BOARD_LATE_INIT
+#define MSP_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_EMAC0
+#define CONFIG_EMAC0_MII		0
+
+
+//#define CONFIG_NET_MULTI      1
+
+//#define CONFIG_MII            1       /* MII PHY management           */
+//#define CONFIG_PHY_ADDR       0       /* PHY address                  */
+//#define CONFIG_PHY1_ADDR      1       /* PHY address                  */
+
+#define CFG_FLASH_AM040_DRIVER		1
+
+/*
+ * Flash Configuration - Using CFI driver 
+ */
+
+#define CFG_FLASH_BASE			PHYS_FLASH_1
+#define CFG_FLASH_SIZE			PHYS_FLASH_SIZE
+#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
+#define CFG_FLASH_CFI_DRIVER		1	/* use common cfi driver        */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+
+#define CFG_MAX_FLASH_BANKS		2	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{ PHYS_EEPROM_1, CFG_FLASH_BASE }
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH		1
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#if 1
+#define CFG_ENV_IN_OWN_SECTOR	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 2 * PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SIZE		PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
+
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	PHYS_FLASH_SECT_SIZE
+#else
+#define CFG_ENV_IN_OWN_SECTOR	1
+#define CFG_ENV_ADDR		(PHYS_EEPROM_1 + PHYS_EEPROM_SIZE - 2 * PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SIZE		(2 * PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
+#endif
+#else
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment */
+#endif
+
+#define CFG_LOAD_ADDR		0x600000	/* default load address */
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			PHYS_NAND_1
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE	1
+//#define CONFIG_MTD_DEBUG
+//#define CONFIG_MTD_DEBUG_VERBOSE	3
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=comcertoeeprom.0,nor1=comcertoflash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:128k(u-boot),64k(env),64k(renv),-(fs)"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hostname=comcerto900\0"						\
+	"netdev=eth0\0"									\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"flashargs=setenv bootargs root=/dev/mtdblock3 rootfstype=\${rootfstype} rw\0"	\
+	"rootfstype=jffs2\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off \0" \
+	"addeth=setenv bootargs ${bootargs} " \
+	"hwaddress=${netdev},${ethaddr}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"flash_self=run flashargs addip addtty;"		\
+		"bootm ${kernel_addr}\0"				\
+	"boot_nfs=nfs 600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
+	        "bootm 600000\0"						\
+	"rootpath=/home/user/devel/CSP_software/distribution/mindspeed-buildroot/build_arm_nofpu/root\0" \
+	"kernelfile=uImage\0" \
+	"fsfile=rootfs.arm_nofpu.jffs2\0" \
+	"updatefs=protect off 2:4-127\;erase 2:4-127;tftp 1000000 ${fsfile};cp.b 1000000 80040000 ${filesize}\0" \
+	"updateboot=protect off 1:0-1\;erase 1:0-1;tftp 1000000 u-boot.bin;cp.b 1000000 11000000 ${filesize}\0" \
+	"updateenv=protect off 2:2;saveenv\0" \
+	""
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext {
+	/* helper variable for board environment handling
+	 *
+	 * env_crc_valid == 0    =>   uninitialised
+	 * env_crc_valid  > 0    =>   environment crc in flash is valid
+	 * env_crc_valid  < 0    =>   environment crc in flash is invalid
+	 */
+	int env_crc_valid;
+};
+
+#endif
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		133000000	/* 133 MHz */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/tsavo515.h

diff --git a/include/configs/tsavo515.h b/include/configs/tsavo515.h
new file mode 100644
index 0000000..1d88f74
--- /dev/null
+++ b/include/configs/tsavo515.h
@@ -0,0 +1,281 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_515			/* It's a SoC */
+#define CONFIG_TSAVO515				/* on a Tsavo-515 Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+#define CONFIG_EMAC0_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC0_PHYCTRLDIS		1
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+#define CONFIG_EMAC0_PHY_ADDR		0x0
+
+/*
+ * SPI driver
+ */
+#define CONFIG_SPI				/* define to enable SPI using */
+
+#define CFG_SPI_CLOCK_POLARITY		1		/* Inactive state of serial clock is high */
+#define CFG_SPI_CLOCK_PHASE		1		/* Serial Clock toggles at the start of the first data bit */
+#define CFG_SPI_FRAMESIZE 		8		/* define the SPI frame size in bits. 8-bit supported only */
+
+#define CFG_SPI_CLOCK_SPEED		4000000		/* the SPI speed in Hz */
+
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS			(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET | \
+					 CFG_CMD_MII | CFG_CMD_ELF | CFG_CMD_NAND | CFG_CMD_SPI)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-515 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"tftpdir=.\0"			\
+	"nfsdir=/home/nfs/fsminimal-debian_sarge-0.13\0"			\
+	"mspname=firmware.axf\0"	\
+	"cspname=zImage\0"		\
+	"fsname=fsimage.jffs2\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
+	"updateboot=tftp 1000000 ${tftpdir}/u-boot.bin; erase 1:0-2; cp.b ${fileaddr} 11000000 ${filesize}\0"	\
+	"updatebootNOR=tftp 1000000 ${tftpdir}/u-boot.bin; erase 2:0-2; cp.b ${fileaddr} 80000000 ${filesize}\0"	\
+	"updatecspNOR=tftp 1000000 ${tftpdir}/${cspname}; erase 2:4-31; cp.b ${fileaddr} 80040000 ${filesize}\0"	\
+	"updatemspNOR=tftp 1000000 ${tftpdir}/${mspname}; erase 2:32-63; cp.b ${fileaddr} 80200000 ${filesize}\0"	\
+	"updatecspNAND=tftp 1000000 ${tftpdir}/${cspname}; nand erase 0 200000; nand write.jffs2 ${fileaddr} 0 ${filesize}\0"	\
+	"updatemspNAND=tftp 1000000 ${tftpdir}/${mspname}; nand erase 200000 200000; nand write.jffs2 ${fileaddr} 200000 ${filesize}\0"	\
+	"updatefsNAND=tftp 1000000 ${tftpdir}/${fsname}; nand erase 400000 7c00000; nand write.jffs2 ${fileaddr} 400000 ${filesize}\0"	\
+	"boottt=run setbootargs; tftp 1000000 ${tftpdir}/${mspname}; loadmsp ${fileaddr} ${filesize}; tftp 2000000 ${tftpdir}/${cspname}; bootcomcerto ${fileaddr}\0"	\
+	"bootoo=run setbootargs; loadmsp 80200000 200000; cp.b 80040000 2000000 200000; bootcomcerto 2000000\0"	\
+	"bootaa=run setbootargs; nand read.jffs2 1000000 200000 200000; loadmsp 1000000 200000; nand read.jffs2 2000000 0 200000; bootcomcerto 2000000\0"	\
+	"mtdboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"	\
+	"nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsdir}\0"	\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::eth0\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"setbootargs=run mtdboot addtty addip addmtd\0"
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+
+#include <cmd_confdefs.h>
+
+/* Include basic MMU support if ELF support is included
+ *
+ * NOTE: keep this stuff after "cmd_confdefs.h" include
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+#define USE_920T_MMU
+#endif
+
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0100000	/* 1 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+#define CFG_FLASH_AM040_DRIVER				/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+//#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x800000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH2			0x80000000	/* Flash Bank #2 */
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		2	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1, PHYS_FLASH2}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP0_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=comcerto_nand0,nor0=comcerto_nor0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcerto_nand0:2m(csp),2m(msp),124m(fs);comcerto_nor0:192k(bootloader),64k(bootloader env),1792k(csp),2m(msp)"
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		133000000	/* 133 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/tsavo515_nor.h

diff --git a/include/configs/tsavo515_nor.h b/include/configs/tsavo515_nor.h
new file mode 100644
index 0000000..78cffcd
--- /dev/null
+++ b/include/configs/tsavo515_nor.h
@@ -0,0 +1,279 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_515			/* It's a SoC */
+#define CONFIG_TSAVO515				/* on a Tsavo-515 Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs NORboot"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+#define CONFIG_EMAC0_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC0_PHYCTRLDIS		1
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+#define CONFIG_EMAC0_PHY_ADDR		0x0
+
+/*
+ * SPI driver
+ */
+#define CONFIG_SPI				/* define to enable SPI using */
+
+#define CFG_SPI_CLOCK_POLARITY		1		/* Inactive state of serial clock is high */
+#define CFG_SPI_CLOCK_PHASE		1		/* Serial Clock toggles at the start of the first data bit */
+#define CFG_SPI_FRAMESIZE 		8		/* define the SPI frame size in bits. 8-bit supported only */
+
+#define CFG_SPI_CLOCK_SPEED		4000000		/* the SPI speed in Hz */
+
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS			(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET | \
+					 CFG_CMD_MII | CFG_CMD_ELF | CFG_CMD_NAND | CFG_CMD_SPI)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-515 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"tftpdir=.\0"			\
+	"nfsdir=/home/nfs/fsminimal-debian_sarge-0.13\0"			\
+	"mspname=firmware.axf\0"	\
+	"cspname=zImage\0"		\
+	"fsname=fsimage.jffs2\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
+	"updateboot=tftp 1000000 ${tftpdir}/u-boot.bin; erase 1:0-2; cp.b ${fileaddr} 11000000 ${filesize}\0"	\
+	"updatecsp=tftp 1000000 ${tftpdir}/${cspname}; erase 1:4-31; cp.b ${fileaddr} 11040000 ${filesize}\0"	\
+	"updatemsp=tftp 1000000 ${tftpdir}/${mspname}; erase 1:32-63; cp.b ${fileaddr} 11200000 ${filesize}\0"	\
+	"updatecspNAND=tftp 1000000 ${tftpdir}/${cspname}; nand erase 0 200000; nand write.jffs2 ${fileaddr} 0 ${filesize}\0"	\
+	"updatemspNAND=tftp 1000000 ${tftpdir}/${mspname}; nand erase 200000 200000; nand write.jffs2 ${fileaddr} 200000 ${filesize}\0"	\
+	"updatefsNAND=tftp 1000000 ${tftpdir}/${fsname}; nand erase 400000 7c00000; nand write.jffs2 ${fileaddr} 400000 ${filesize}\0"	\
+	"boottt=run setbootargs; tftp 1000000 ${tftpdir}/${mspname}; loadmsp ${fileaddr} ${filesize}; tftp 2000000 ${tftpdir}/${cspname}; bootcomcerto ${fileaddr}\0"	\
+	"bootoo=run setbootargs; loadmsp 11200000 200000; cp.b 11040000 2000000 200000; bootcomcerto 2000000\0"	\
+	"bootaa=run setbootargs; nand read.jffs2 1000000 200000 200000; loadmsp 1000000 200000; nand read.jffs2 2000000 0 200000; bootcomcerto 2000000\0"	\
+	"mtdboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"	\
+	"nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsdir}\0"	\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::eth0\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"setbootargs=run mtdboot addtty addip addmtd\0"
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+
+#include <cmd_confdefs.h>
+
+/* Include basic MMU support if ELF support is included
+ *
+ * NOTE: keep this stuff after "cmd_confdefs.h" include
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+#define USE_920T_MMU
+#endif
+
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0100000	/* 1 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+//#define CFG_FLASH_AM040_DRIVER			/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+//#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP0_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=comcerto_nand0,nor0=comcerto_nor0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcerto_nand0:2m(csp),2m(msp),124m(fs);comcerto_nor0:192k(bootloader),64k(bootloader env),1792k(csp),2m(msp)"
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		133000000	/* 133 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/tsavo530.h

diff --git a/include/configs/tsavo530.h b/include/configs/tsavo530.h
new file mode 100644
index 0000000..cb90800
--- /dev/null
+++ b/include/configs/tsavo530.h
@@ -0,0 +1,266 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_530			/* It's a SoC */
+#define CONFIG_TSAVO530				/* on a Tsavo-530 Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x04000000	/* 64 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+#define CONFIG_UART0
+
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+#define CONFIG_EMAC0_PHY_ADDR		0x0
+
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS			(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET | \
+					 CFG_CMD_MII | CFG_CMD_ELF | CFG_CMD_NAND)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-530 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"tftpdir=.\0"			\
+	"nfsdir=/home/nfs/fsminimal-debian_sarge-0.13\0"			\
+	"mspname=firmware.axf\0"	\
+	"cspname=zImage\0"		\
+	"fsname=fsimage.jffs2\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
+	"updateboot=tftp 1000000 ${tftpdir}/u-boot.bin; erase 1:0-2; cp.b ${fileaddr} 11000000 ${filesize}\0"	\
+	"updatebootNOR=tftp 1000000 ${tftpdir}/u-boot.bin; erase 2:0-2; cp.b ${fileaddr} 5000000 ${filesize}\0"	\
+	"updatecspNOR=tftp 1000000 ${tftpdir}/${cspname}; erase 2:4-31; cp.b ${fileaddr} 5040000 ${filesize}\0"	\
+	"updatemspNOR=tftp 1000000 ${tftpdir}/${mspname}; erase 2:32-63; cp.b ${fileaddr} 5200000 ${filesize}\0"	\
+	"updatecspNAND=tftp 1000000 ${tftpdir}/${cspname}; nand erase 0 200000; nand write.jffs2 ${fileaddr} 0 ${filesize}\0"	\
+	"updatemspNAND=tftp 1000000 ${tftpdir}/${mspname}; nand erase 200000 200000; nand write.jffs2 ${fileaddr} 200000 ${filesize}\0"	\
+	"updatefsNAND=tftp 1000000 ${tftpdir}/${fsname}; nand erase 400000 7c00000; nand write.jffs2 ${fileaddr} 400000 ${filesize}\0"	\
+	"boottt=run setbootargs; tftp 1000000 ${tftpdir}/${mspname}; loadmsp ${fileaddr} ${filesize}; tftp 2000000 ${tftpdir}/${cspname}; bootcomcerto ${fileaddr}\0"	\
+	"bootoo=run setbootargs; loadmsp 5200000 200000; cp.b 5040000 2000000 200000; bootcomcerto 2000000\0"	\
+	"bootaa=run setbootargs; nand read.jffs2 1000000 200000 200000; loadmsp 1000000 200000; nand read.jffs2 2000000 0 200000; bootcomcerto 2000000\0"	\
+	"mtdboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"	\
+	"nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsdir}\0"	\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::eth0\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"setbootargs=run mtdboot addtty addip addmtd\0"
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+
+#include <cmd_confdefs.h>
+
+/* Include basic MMU support if ELF support is included
+ *
+ * NOTE: keep this stuff after "cmd_confdefs.h" include
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+#define USE_920T_MMU
+#endif
+
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0100000	/* 1 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+#define CFG_FLASH_AM040_DRIVER				/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+//#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH2			0x05000000	/* Flash Bank #2 */
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		2	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1, PHYS_FLASH2}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP0_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=comcerto_nand0,nor0=comcerto_nor0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcerto_nand0:2m(csp),2m(msp),124m(fs);comcerto_nor0:192k(bootloader),64k(bootloader env),1792k(csp),2m(msp)"
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		125000000	/* 125 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/tsavo530_nor.h

diff --git a/include/configs/tsavo530_nor.h b/include/configs/tsavo530_nor.h
new file mode 100644
index 0000000..3d1b75b
--- /dev/null
+++ b/include/configs/tsavo530_nor.h
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_530			/* It's a SoC */
+#define CONFIG_TSAVO530				/* on a Tsavo-530 Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs NORboot"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x04000000	/* 64 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+#define CONFIG_UART0
+
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+#define CONFIG_EMAC0_PHY_ADDR		0x0
+
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS			(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET | \
+					 CFG_CMD_MII | CFG_CMD_ELF | CFG_CMD_NAND)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-530 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"tftpdir=.\0"			\
+	"nfsdir=/home/nfs/fsminimal-debian_sarge-0.13\0"			\
+	"mspname=firmware.axf\0"	\
+	"cspname=zImage\0"		\
+	"fsname=fsimage.jffs2\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
+	"updateboot=tftp 1000000 ${tftpdir}/u-boot.bin; erase 1:0-2; cp.b ${fileaddr} 11000000 ${filesize}\0"	\
+	"updatecsp=tftp 1000000 ${tftpdir}/${cspname}; erase 1:4-31; cp.b ${fileaddr} 11040000 ${filesize}\0"   \
+	"updatemsp=tftp 1000000 ${tftpdir}/${mspname}; erase 1:32-63; cp.b ${fileaddr} 11200000 ${filesize}\0"  \
+	"updatecspNAND=tftp 1000000 ${tftpdir}/${cspname}; nand erase 0 200000; nand write.jffs2 ${fileaddr} 0 ${filesize}\0"	\
+	"updatemspNAND=tftp 1000000 ${tftpdir}/${mspname}; nand erase 200000 200000; nand write.jffs2 ${fileaddr} 200000 ${filesize}\0"	\
+	"updatefsNAND=tftp 1000000 ${tftpdir}/${fsname}; nand erase 400000 7c00000; nand write.jffs2 ${fileaddr} 400000 ${filesize}\0"	\
+	"boottt=run setbootargs; tftp 1000000 ${tftpdir}/${mspname}; loadmsp ${fileaddr} ${filesize}; tftp 2000000 ${tftpdir}/${cspname}; bootcomcerto ${fileaddr}\0"	\
+	"bootoo=run setbootargs; loadmsp 11200000 200000; cp.b 11040000 2000000 200000; bootcomcerto 2000000\0"  \
+	"bootaa=run setbootargs; nand read.jffs2 1000000 200000 200000; loadmsp 1000000 200000; nand read.jffs2 2000000 0 200000; bootcomcerto 2000000\0" \
+	"mtdboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"	\
+	"nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsdir}\0"	\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::eth0\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"setbootargs=run mtdboot addtty addip addmtd\0"
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+
+#include <cmd_confdefs.h>
+
+/* Include basic MMU support if ELF support is included
+ *
+ * NOTE: keep this stuff after "cmd_confdefs.h" include
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+#define USE_920T_MMU
+#endif
+
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0100000	/* 1 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+//#define CFG_FLASH_AM040_DRIVER			/* enable AM040 flash driver */
+#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+//#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x400000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		1	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			EXP_CSP0_BASEADDR
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=comcerto_nand0,nor0=comcerto_nor0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcerto_nand0:2m(csp),2m(msp),124m(fs);comcerto_nor0:192k(bootloader),64k(bootloader env),1792k(csp),2m(msp)"
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		125000000	/* 125 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/udev515.h

diff --git a/include/configs/udev515.h b/include/configs/udev515.h
new file mode 100644
index 0000000..098402d
--- /dev/null
+++ b/include/configs/udev515.h
@@ -0,0 +1,293 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_515			/* It's a SoC */
+#define CONFIG_UDEV515				/* on a Udev-515 Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+#define CONFIG_EMAC0_MII_MODE		EMAC_MII_MODE
+#define CONFIG_EMAC0_MIIFDL		0
+#define CONFIG_EMAC0_MII100L		0
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+
+/*
+ * SPI driver
+ */
+#define CONFIG_SPI				/* define to enable SPI using */
+
+#define CFG_SPI_CLOCK_POLARITY		1		/* Inactive state of serial clock is high */
+#define CFG_SPI_CLOCK_PHASE		1		/* Serial Clock toggles at the start of the first data bit */
+#define CFG_SPI_FRAMESIZE 		8		/* define the SPI frame size in bits. 8-bit supported only */
+
+#define CFG_SPI_CLOCK_SPEED		4000000		/* the SPI speed in Hz */
+
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS			(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET | \
+					 CFG_CMD_MII | CFG_CMD_ELF | CFG_CMD_NAND | CFG_CMD_SPI)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-515 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"tftpdir=.\0"			\
+	"nfsdir=/home/nfs/fsminimal-debian_sarge-0.13\0"			\
+	"mspname=firmware.axf\0"	\
+	"cspname=zImage\0"		\
+	"fsname=fsimage.jffs2\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
+	"updateboot=tftp 1000000 ${tftpdir}/u-boot.bin; erase 1:0-2; cp.b ${fileaddr} 11000000 ${filesize}\0"	\
+	"updatebootNOR=tftp 1000000 ${tftpdir}/u-boot.bin; erase 2:0-2; cp.b ${fileaddr} 80000000 ${filesize}\0"	\
+	"updatecspNOR=tftp 1000000 ${tftpdir}/${cspname}; erase 2:4-31; cp.b ${fileaddr} 80040000 ${filesize}\0"	\
+	"updatemspNOR=tftp 1000000 ${tftpdir}/${mspname}; erase 2:32-63; cp.b ${fileaddr} 80200000 ${filesize}\0"	\
+	"updatefsNOR=tftp 1000000 ${tftpdir}/${mspname}; erase 2:64-128; cp.b ${fileaddr} 80400000 ${filesize}\0"	\
+	"updatecspNAND=tftp 1000000 ${tftpdir}/${cspname}; nand erase 0 200000; nand write.jffs2 ${fileaddr} 0 ${filesize}\0"	\
+	"updatemspNAND=tftp 1000000 ${tftpdir}/${mspname}; nand erase 200000 200000; nand write.jffs2 ${fileaddr} 200000 ${filesize}\0"	\
+	"updatefsNAND=tftp 1000000 ${tftpdir}/${fsname}; nand erase 400000 fc00000; nand write.jffs2 ${fileaddr} 400000 ${filesize}\0"	\
+	"boottt=run setbootargs; tftp 1000000 ${tftpdir}/${mspname}; loadmsp ${fileaddr} ${filesize}; tftp 2000000 ${tftpdir}/${cspname}; bootcomcerto ${fileaddr}\0"	\
+	"bootoo=run setbootargs; loadmsp 80200000 200000; cp.b 80040000 2000000 200000; bootcomcerto 2000000\0"	\
+	"bootaa=run setbootargs; nand read.jffs2 1000000 200000 200000; loadmsp 1000000 200000; nand read.jffs2 2000000 0 200000; bootcomcerto 2000000\0"	\
+	"mtdboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"	\
+	"nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsdir}\0"	\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::eth0\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"setbootargs=run mtdboot addtty addip addmtd\0"
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+
+#include <cmd_confdefs.h>
+
+/* Include basic MMU support if ELF support is included
+ *
+ * NOTE: keep this stuff after "cmd_confdefs.h" include
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+#define USE_920T_MMU
+#endif
+
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0100000	/* 1 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+#define CFG_FLASH_AM040_DRIVER				/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+//#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x800000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH2			0x80000000	/* Flash Bank #2 */
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		2	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1, PHYS_FLASH2}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			(EXP_CSP0_BASEADDR + 0x9000)
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+
+/* CPLD registers */
+#define CPLD_RESET_CTRL			(EXP_CSP0_BASEADDR + 0x3000)			/* Reset control register */
+#define CPLD_INTMASK			(EXP_CSP0_BASEADDR + 0x5000)			/* Interrupt Mask register */
+
+
+#define ESWITCH_OUT_OF_RESET		0x80		/* Ethernet switch out of reset */
+#define ESWITCH_IRQMASK			0x08		/* Ethernet switch interrupt mask */
+
+#define ESWITCH_SPI_CS                 (1 << 2)
+
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=comcerto_nand0,nor0=comcerto_nor0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcerto_nand0:2m(csp),2m(msp),252m(fs);comcerto_nor0:192k(bootloader),64k(bootloader env),1792k(csp),2m(msp),4m(fs)"
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		133000000	/* 133 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/configs/udev800.h

diff --git a/include/configs/udev800.h b/include/configs/udev800.h
new file mode 100644
index 0000000..e423c8c
--- /dev/null
+++ b/include/configs/udev800.h
@@ -0,0 +1,300 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_COMCERTO
+#define CONFIG_COMCERTO_800			/* It's a SoC */
+#define CONFIG_UDEV800				/* on a Udev-800 Board */
+#undef CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff */
+
+#include <asm/hardware.h>
+
+/* Mindspeed version */
+#define CONFIG_IDENT_STRING		" Mindspeed 0.05.0cvs"
+
+/*
+ * Linux boot configuration
+ */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+//#define CONFIG_INITRD_TAG		1
+
+#define LINUX_BOOTPARAM_ADDR		0x01000100
+
+/*
+ * Initial stack configuration
+ */
+#define CFG_INIT_RAM_ADDR		IRAM_BASEADDR
+#define CFG_INIT_SP_OFFSET		0x1000
+
+
+/*
+ * Malloc/stack configuration
+ */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE		128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x00000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 MiB */
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART configuration
+ */
+/* define one of these to choose the UART0 or UART1 as console */
+#define CONFIG_UART0
+#undef CONFIG_UART1
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}
+
+
+/*
+ * EMAC driver
+ */
+#define CONFIG_COMCERTO_EMAC
+#define CONFIG_EMAC0
+#define CONFIG_EMAC0_MII_MODE		EMAC_MII_MODE
+#define CONFIG_EMAC0_MIIFDL		0
+#define CONFIG_EMAC0_MII100L		0
+
+#undef CONFIG_EMAC1
+#define CONFIG_EMAC1_MII_MODE		EMAC_RMII_SMII_MODE
+#define CONFIG_EMAC1_PHYCTRLDIS		1
+
+/*
+ * MDIO driver
+ */
+#define CONFIG_MII
+#define CFG_FAULT_ECHO_LINK_DOWN
+#define CONFIG_EMAC0_MDCLOCK		2500000
+
+#define CONFIG_EMAC1_MDCLOCK		2500000
+#define CONFIG_EMAC1_PHY_ADDR		0x0
+
+/*
+ * SPI driver
+ */
+#define CONFIG_SPI				/* define to enable SPI using */
+
+#define CFG_SPI_CLOCK_POLARITY		1		/* Inactive state of serial clock is high */
+#define CFG_SPI_CLOCK_PHASE		1		/* Serial Clock toggles at the start of the first data bit */
+#define CFG_SPI_FRAMESIZE 		8		/* define the SPI frame size in bits. 8-bit supported only */
+
+#define CFG_SPI_CLOCK_SPEED		4000000		/* the SPI speed in Hz */
+
+
+/*
+ * Shell configuration
+ */
+#define CONFIG_COMMANDS			(CFG_CMD_FLASH | CFG_CMD_ENV | CFG_CMD_MEMORY | CFG_CMD_RUN | CFG_CMD_NET | \
+					 CFG_CMD_MII | CFG_CMD_ELF | CFG_CMD_NAND | CFG_CMD_SPI)
+
+#define	CFG_LONGHELP					/* undef to save memory		*/
+#define CFG_PROMPT		"Comcerto-800 > "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16			/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */
+
+/*
+ * User Interface
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"tftpdir=.\0"			\
+	"nfsdir=/home/nfs/fsminimal-debian_sarge-0.13\0"			\
+	"mspname=firmware.axf\0"	\
+	"cspname=zImage\0"		\
+	"fsname=fsimage.jffs2\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
+	"updateboot=tftp 1000000 ${tftpdir}/u-boot.bin; erase 1:0-2; cp.b ${fileaddr} 11000000 ${filesize}\0"	\
+	"updatebootNOR=tftp 1000000 ${tftpdir}/u-boot.bin; erase 2:0-2; cp.b ${fileaddr} 80000000 ${filesize}\0"	\
+	"updatecspNOR=tftp 1000000 ${tftpdir}/${cspname}; erase 2:4-31; cp.b ${fileaddr} 80040000 ${filesize}\0"	\
+	"updatemspNOR=tftp 1000000 ${tftpdir}/${mspname}; erase 2:32-63; cp.b ${fileaddr} 80200000 ${filesize}\0"	\
+	"updatefsNOR=tftp 1000000 ${tftpdir}/${mspname}; erase 2:64-128; cp.b ${fileaddr} 80400000 ${filesize}\0"	\
+	"updatecspNAND=tftp 1000000 ${tftpdir}/${cspname}; nand erase 0 200000; nand write.jffs2 ${fileaddr} 0 ${filesize}\0"	\
+	"updatemspNAND=tftp 1000000 ${tftpdir}/${mspname}; nand erase 200000 200000; nand write.jffs2 ${fileaddr} 200000 ${filesize}\0"	\
+	"updatefsNAND=tftp 1000000 ${tftpdir}/${fsname}; nand erase 400000 fc00000; nand write.jffs2 ${fileaddr} 400000 ${filesize}\0"	\
+	"boottt=run setbootargs; tftp 1000000 ${tftpdir}/${mspname}; loadmsp ${fileaddr} ${filesize}; tftp 2000000 ${tftpdir}/${cspname}; bootcomcerto ${fileaddr}\0"	\
+	"bootoo=run setbootargs; loadmsp 80200000 200000; cp.b 80040000 2000000 200000; bootcomcerto 2000000\0"	\
+	"bootaa=run setbootargs; nand read.jffs2 1000000 200000 200000; loadmsp 1000000 200000; nand read.jffs2 2000000 0 200000; bootcomcerto 2000000\0"	\
+	"mtdboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"	\
+	"nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${nfsdir}\0"	\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}::eth0\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"setbootargs=run mtdboot addtty addip addmtd\0"
+
+#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
+#define CONFIG_ETH1ADDR         00:aa:bb:cc:dd:ff
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_SERVERIP		192.168.0.3
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY		3
+
+
+#include <cmd_confdefs.h>
+
+/* Include basic MMU support if ELF support is included
+ *
+ * NOTE: keep this stuff after "cmd_confdefs.h" include
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+#define USE_920T_MMU
+#endif
+
+
+#define CFG_LOAD_ADDR			0x1000000	/* default load address */
+
+
+#define CFG_MEMTEST_START	CFG_LOAD_ADDR		/* memtest works on */
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)
+
+#define BOARD_LATE_INIT
+#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x1000000	/* 16 MiB reserved for MSP */
+#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0100000	/* 1 MiB reserved for MSP */
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_NET_RETRY_COUNT		5
+
+/*
+ * Flash Configuration
+ */
+#define CFG_FLASH_AM040_DRIVER				/* enable AM040 flash driver */
+//#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */
+
+#define CFG_FLASH_AMLV640U_DRIVER			/* enable AMLV640U flash driver */
+//#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
+#define CFG_FLASH_AMLV640U_SIZE		0x800000	/* (Acessible) Size of the AMLV640U flash device */
+
+//#define CFG_FLASH_CFI_DRIVER			/* enable CFI driver */
+#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */
+
+#define CFG_MAX_FLASH_SECT		128	/* max # of sectors on one chip */
+//#define CFG_FLASH_PROTECTION
+
+#define PHYS_FLASH2			0x80000000	/* Flash Bank #2 */
+
+#define PHYS_FLASH1			EXP_CSBOOT_BASEADDR	/* Flash Bank #1 */
+#define PHYS_FLASH1_SECT_SIZE		0x00010000	/* 64 KiB sectors */
+
+#define CFG_MAX_FLASH_BANKS		2	/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST		{PHYS_FLASH1, PHYS_FLASH2}
+
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+/*
+ * CFI driver 
+ */
+#if defined(CFG_FLASH_CFI_DRIVER)
+#define CFG_FLASH_CFI				/* flash is CFI conformant      */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* use buffered writes (20x faster) */
+#define CFG_FLASH_QUIET_TEST
+
+/*
+ * Monitor configuration
+ */
+#define CFG_MONITOR_BASE        	PHYS_FLASH1
+#define CFG_MONITOR_LEN         	(3 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 64 KiB for Monitor */
+
+#endif
+
+
+/*
+ * Enviroment in flash
+ */
+#define CFG_ENV_IS_IN_FLASH
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_ADDR			(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 3 sectors for U-boot image */
+#define CFG_ENV_SECT_SIZE		PHYS_FLASH1_SECT_SIZE
+//#define CFG_ENV_ADDR_REDUND		(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#endif
+
+#define CFG_ENV_SIZE			0x4000	/* Total Size of Environment 16KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND Configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_BASE			(EXP_CSP0_BASEADDR + 0x9000)
+#define CFG_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_JFFS2_NAND
+
+#endif
+
+/* NAND GPIOs config */
+#define CFG_NAND_BR_GPIO	1
+#define CFG_NAND_CE_GPIO	3
+#define CFG_NAND_CLE_GPIO	4
+#define CFG_NAND_ALE_GPIO	5
+
+
+/* CPLD registers */
+#define CPLD_RESET_CTRL			(EXP_CSP0_BASEADDR + 0x3000)			/* Reset control register */
+#define CPLD_INTMASK			(EXP_CSP0_BASEADDR + 0x5000)			/* Interrupt Mask register */
+
+
+#define ESWITCH_OUT_OF_RESET		0x80		/* Ethernet switch out of reset */
+#define ESWITCH_IRQMASK			0x08		/* Ethernet switch interrupt mask */
+
+#define ESWITCH_SPI_CS                 (1 << 2)
+
+/*
+ * JFFS2 Configuration
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=comcerto_nand0,nor0=comcerto_nor0"
+#define MTDPARTS_DEFAULT	"mtdparts=comcerto_nand0:2m(csp),2m(msp),252m(fs);comcerto_nor0:192k(bootloader),64k(bootloader env),1792k(csp),2m(msp),4m(fs)"
+
+#define CFG_REFCLKFREQ		10000000	/* 10 MHz */
+
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		133000000	/* 133 MHz */
+
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */

include/cramfs/cramfs_fs.h

diff --git a/include/cramfs/cramfs_fs.h b/include/cramfs/cramfs_fs.h
index 9f1b1d5..f69ece6 100644
--- a/include/cramfs/cramfs_fs.h
+++ b/include/cramfs/cramfs_fs.h
@@ -84,7 +84,7 @@
 				| CRAMFS_FLAG_WRONG_SIGNATURE \
 				| CRAMFS_FLAG_SHIFTED_ROOT_OFFSET )
 
-#if __BYTE_ORDER == __LITTLE_ENDIAN
+#if (__BYTE_ORDER == __LITTLE_ENDIAN) || (defined(CONFIG_COMCERTO) && (__BYTE_ORDER == __BIG_ENDIAN))
 #define CRAMFS_16(x)	(x)
 #define CRAMFS_24(x)	(x)
 #define CRAMFS_32(x)	(x)

include/div64.h

diff --git a/include/div64.h b/include/div64.h
new file mode 100644
index 0000000..d833144
--- /dev/null
+++ b/include/div64.h
@@ -0,0 +1,49 @@
+#ifndef _ASM_GENERIC_DIV64_H
+#define _ASM_GENERIC_DIV64_H
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
+ *
+ * The semantics of do_div() are:
+ *
+ * uint32_t do_div(uint64_t *n, uint32_t base)
+ * {
+ *	uint32_t remainder = *n % base;
+ *	*n = *n / base;
+ *	return remainder;
+ * }
+ *
+ * NOTE: macro parameter n is evaluated multiple times,
+ *       beware of side effects!
+ */
+
+#include <linux/types.h>
+
+extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
+
+/* The unnecessary pointer compare is there
+ * to check for type safety (n must be 64bit)
+ */
+# define do_div(n,base) ({				\
+	uint32_t __base = (base);			\
+	uint32_t __rem;					\
+	(void)(((typeof((n)) *)0) == ((uint64_t *)0));	\
+	if (((n) >> 32) == 0) {			\
+		__rem = (uint32_t)(n) % __base;		\
+		(n) = (uint32_t)(n) / __base;		\
+	} else						\
+		__rem = __div64_32(&(n), __base);	\
+	__rem;						\
+ })
+
+/* Wrapper for do_div(). Doesn't modify dividend and returns
+ * the result, not reminder.
+ */
+static inline uint64_t lldiv(uint64_t dividend, uint32_t divisor)
+{
+	uint64_t __res = dividend;
+	do_div(__res, divisor);
+	return(__res);
+}
+
+#endif /* _ASM_GENERIC_DIV64_H */

include/errno.h

diff --git a/include/errno.h b/include/errno.h
new file mode 100644
index 0000000..39dc515
--- /dev/null
+++ b/include/errno.h
@@ -0,0 +1,155 @@
+/*
+ * U-boot - errno.h Error number defines
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _GENERIC_ERRNO_H
+#define _GENERIC_ERRNO_H
+
+#define	EPERM		1	/* Operation not permitted */
+#define	ENOENT		2	/* No such file or directory */
+#define	ESRCH		3	/* No such process */
+#define	EINTR		4	/* Interrupted system call */
+#define	EIO		5	/* I/O error */
+#define	ENXIO		6	/* No such device or address */
+#define	E2BIG		7	/* Argument list too long */
+#define	ENOEXEC		8	/* Exec format error */
+#define	EBADF		9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+
+#define	EDEADLOCK	EDEADLK
+
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+#endif

include/image.h

diff --git a/include/image.h b/include/image.h
index 2f575fd..a1d5774 100644
--- a/include/image.h
+++ b/include/image.h
@@ -31,6 +31,18 @@
 #ifndef __IMAGE_H__
 #define __IMAGE_H__
 
+#include <config.h>
+#include <compiler.h>
+#include <asm/u-boot.h>
+
+#if defined(CONFIG_FIT)
+#include <fdt.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#define CONFIG_MD5		/* FIT images need MD5 support */
+#define CONFIG_SHA1		/* and SHA1 */
+#endif
+
 /*
  * Operating System Codes
  */
@@ -55,6 +67,8 @@
 #define IH_OS_RTEMS		18	/* RTEMS	*/
 #define IH_OS_ARTOS		19	/* ARTOS	*/
 #define IH_OS_UNITY		20	/* Unity OS	*/
+#define IH_OS_INTEGRITY		21	/* INTEGRITY	*/
+#define IH_OS_OSE		22	/* OSE		*/
 
 /*
  * CPU Architecture Codes (supported by Linux)
@@ -77,6 +91,28 @@
 #define IH_CPU_NIOS2		15	/* Nios-II	*/
 #define IH_CPU_BLACKFIN		16	/* Blackfin	*/
 #define IH_CPU_AVR32		17	/* AVR32	*/
+#define IH_ARCH_INVALID		0	/* Invalid CPU	*/
+#define IH_ARCH_ALPHA		1	/* Alpha	*/
+#define IH_ARCH_ARM		2	/* ARM		*/
+#define IH_ARCH_I386		3	/* Intel x86	*/
+#define IH_ARCH_IA64		4	/* IA64		*/
+#define IH_ARCH_MIPS		5	/* MIPS		*/
+#define IH_ARCH_MIPS64		6	/* MIPS	 64 Bit */
+#define IH_ARCH_PPC		7	/* PowerPC	*/
+#define IH_ARCH_S390		8	/* IBM S390	*/
+#define IH_ARCH_SH		9	/* SuperH	*/
+#define IH_ARCH_SPARC		10	/* Sparc	*/
+#define IH_ARCH_SPARC64		11	/* Sparc 64 Bit */
+#define IH_ARCH_M68K		12	/* M68K		*/
+#define IH_ARCH_MICROBLAZE	14	/* MicroBlaze   */
+#define IH_ARCH_NIOS2		15	/* Nios-II	*/
+#define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
+#define IH_ARCH_AVR32		17	/* AVR32	*/
+#define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
+#define IH_ARCH_SANDBOX		19	/* Sandbox architecture (test only) */
+#define IH_ARCH_NDS32	        20	/* ANDES Technology - NDS32  */
+#define IH_ARCH_OPENRISC        21	/* OpenRISC 1000  */
+
 
 /*
  * Image Types
@@ -126,6 +162,12 @@
 #define IH_TYPE_SCRIPT		6	/* Script file			*/
 #define IH_TYPE_FILESYSTEM	7	/* Filesystem Image (any type)	*/
 #define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
+#define IH_TYPE_KWBIMAGE	9	/* Kirkwood Boot Image		*/
+#define IH_TYPE_IMXIMAGE	10	/* Freescale IMXBoot Image	*/
+#define IH_TYPE_UBLIMAGE	11	/* Davinci UBL Image		*/
+#define IH_TYPE_OMAPIMAGE	12	/* TI OMAP Config Header Image	*/
+#define IH_TYPE_AISIMAGE	13	/* TI Davinci AIS Image		*/
+#define IH_TYPE_KERNEL_NOLOAD	14	/* OS Kernel Image, can run from any load address */
 
 /*
  * Compression Types
@@ -133,6 +175,8 @@
 #define IH_COMP_NONE		0	/*  No	 Compression Used	*/
 #define IH_COMP_GZIP		1	/* gzip	 Compression Used	*/
 #define IH_COMP_BZIP2		2	/* bzip2 Compression Used	*/
+#define IH_COMP_LZMA		3	/* lzma  Compression Used	*/
+#define IH_COMP_LZO		4	/* lzo   Compression Used	*/
 
 #define IH_MAGIC	0x27051956	/* Image Magic Number		*/
 #define IH_NMLEN		32	/* Image Name Length		*/
@@ -140,7 +184,6 @@
 /*
  * all data in network byte order (aka natural aka bigendian)
  */
-
 typedef struct image_header {
 	uint32_t	ih_magic;	/* Image Header Magic Number	*/
 	uint32_t	ih_hcrc;	/* Image Header CRC Checksum	*/
@@ -156,5 +199,447 @@
 	uint8_t		ih_name[IH_NMLEN];	/* Image Name		*/
 } image_header_t;
 
+typedef struct image_info {
+	ulong		start, end;		/* start/end of blob */
+	ulong		image_start, image_len; /* start of image within blob, len of image */
+	ulong		load;			/* load addr for the image */
+	uint8_t		comp, type, os;		/* compression, type of image, os type */
+} image_info_t;
+
+/*
+ * Legacy and FIT format headers used by do_bootm() and do_bootm_<os>()
+ * routines.
+ */
+typedef struct bootm_headers {
+	/*
+	 * Legacy os image header, if it is a multi component image
+	 * then boot_get_ramdisk() and get_fdt() will attempt to get
+	 * data from second and third component accordingly.
+	 */
+	image_header_t	*legacy_hdr_os;		/* image header pointer */
+	image_header_t	legacy_hdr_os_copy;	/* header copy */
+	ulong		legacy_hdr_valid;
+
+#if defined(CONFIG_FIT)
+	const char	*fit_uname_cfg;	/* configuration node unit name */
+
+	void		*fit_hdr_os;	/* os FIT image header */
+	const char	*fit_uname_os;	/* os subimage node unit name */
+	int		fit_noffset_os;	/* os subimage node offset */
+
+	void		*fit_hdr_rd;	/* init ramdisk FIT image header */
+	const char	*fit_uname_rd;	/* init ramdisk subimage node unit name */
+	int		fit_noffset_rd;	/* init ramdisk subimage node offset */
+
+	void		*fit_hdr_fdt;	/* FDT blob FIT image header */
+	const char	*fit_uname_fdt;	/* FDT blob subimage node unit name */
+	int		fit_noffset_fdt;/* FDT blob subimage node offset */
+#endif
+
+#ifndef USE_HOSTCC
+	image_info_t	os;		/* os image info */
+	ulong		ep;		/* entry point of OS */
+
+	ulong		rd_start, rd_end;/* ramdisk start/end */
+
+#ifdef CONFIG_OF_LIBFDT
+	char		*ft_addr;	/* flat dev tree address */
+#endif
+	ulong		ft_len;		/* length of flat device tree */
+
+	ulong		initrd_start;
+	ulong		initrd_end;
+	ulong		cmdline_start;
+	ulong		cmdline_end;
+	bd_t		*kbd;
+#endif
+
+	int		verify;		/* getenv("verify")[0] != 'n' */
+
+#define	BOOTM_STATE_START	(0x00000001)
+#define	BOOTM_STATE_LOADOS	(0x00000002)
+#define	BOOTM_STATE_RAMDISK	(0x00000004)
+#define	BOOTM_STATE_FDT		(0x00000008)
+#define	BOOTM_STATE_OS_CMDLINE	(0x00000010)
+#define	BOOTM_STATE_OS_BD_T	(0x00000020)
+#define	BOOTM_STATE_OS_PREP	(0x00000040)
+#define	BOOTM_STATE_OS_GO	(0x00000080)
+	int		state;
+
+#ifdef CONFIG_LMB
+	struct lmb	lmb;		/* for memory mgmt */
+#endif
+} bootm_headers_t;
+
+extern bootm_headers_t images;
+
+/*
+ * Some systems (for example LWMON) have very short watchdog periods;
+ * we must make sure to split long operations like memmove() or
+ * checksum calculations into reasonable chunks.
+ */
+#ifndef CHUNKSZ
+#define CHUNKSZ (64 * 1024)
+#endif
+
+#ifndef CHUNKSZ_CRC32
+#define CHUNKSZ_CRC32 (64 * 1024)
+#endif
+
+#ifndef CHUNKSZ_MD5
+#define CHUNKSZ_MD5 (64 * 1024)
+#endif
+
+#ifndef CHUNKSZ_SHA1
+#define CHUNKSZ_SHA1 (64 * 1024)
+#endif
+
+#define uimage_to_cpu(x)		be32_to_cpu(x)
+#define cpu_to_uimage(x)		cpu_to_be32(x)
+
+/*
+ * Translation table for entries of a specific type; used by
+ * get_table_entry_id() and get_table_entry_name().
+ */
+typedef struct table_entry {
+	int	id;
+	char	*sname;		/* short (input) name to find table entry */
+	char	*lname;		/* long (output) name to print for messages */
+	int	val;
+} table_entry_t;
+
+/*
+ * get_table_entry_id() scans the translation table trying to find an
+ * entry that matches the given short name. If a matching entry is
+ * found, it's id is returned to the caller.
+ */
+int get_table_entry_id(const table_entry_t *table,
+		const char *table_name, const char *name);
+/*
+ * get_table_entry_name() scans the translation table trying to find
+ * an entry that matches the given id. If a matching entry is found,
+ * its long name is returned to the caller.
+ */
+char *get_table_entry_name(const table_entry_t *table, char *msg, int id);
+
+const char *genimg_get_os_name(uint8_t os);
+const char *genimg_get_arch_name(uint8_t arch);
+const char *genimg_get_type_name(uint8_t type);
+const char *genimg_get_comp_name(uint8_t comp);
+int genimg_get_os_id(const char *name);
+int genimg_get_arch_id(const char *name);
+int genimg_get_type_id(const char *name);
+int genimg_get_comp_id(const char *name);
+void genimg_print_size(uint32_t size);
+
+#ifndef USE_HOSTCC
+/* Image format types, returned by _get_format() routine */
+#define IMAGE_FORMAT_INVALID	0x00
+#define IMAGE_FORMAT_LEGACY	0x01	/* legacy image_header based format */
+#define IMAGE_FORMAT_FIT	0x02	/* new, libfdt based format */
+
+int genimg_get_format(void *img_addr);
+int genimg_has_config(bootm_headers_t *images);
+ulong genimg_get_image(ulong img_addr);
+
+int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
+		uint8_t arch, ulong *rd_start, ulong *rd_end);
+
+
+#ifdef CONFIG_OF_LIBFDT
+int boot_get_fdt(int flag, int argc, char * const argv[],
+		bootm_headers_t *images, char **of_flat_tree, ulong *of_size);
+void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob);
+int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size);
+#endif
+
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
+int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
+		  ulong *initrd_start, ulong *initrd_end);
+#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
+#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
+int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end);
+#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */
+#ifdef CONFIG_SYS_BOOT_GET_KBD
+int boot_get_kbd(struct lmb *lmb, bd_t **kbd);
+#endif /* CONFIG_SYS_BOOT_GET_KBD */
+#endif /* !USE_HOSTCC */
+
+/*******************************************************************/
+/* Legacy format specific code (prefixed with image_) */
+/*******************************************************************/
+static inline uint32_t image_get_header_size(void)
+{
+	return (sizeof(image_header_t));
+}
+
+#define image_get_hdr_l(f) \
+	static inline uint32_t image_get_##f(const image_header_t *hdr) \
+	{ \
+		return uimage_to_cpu(hdr->ih_##f); \
+	}
+image_get_hdr_l(magic)		/* image_get_magic */
+image_get_hdr_l(hcrc)		/* image_get_hcrc */
+image_get_hdr_l(time)		/* image_get_time */
+image_get_hdr_l(size)		/* image_get_size */
+image_get_hdr_l(load)		/* image_get_load */
+image_get_hdr_l(ep)		/* image_get_ep */
+image_get_hdr_l(dcrc)		/* image_get_dcrc */
+
+#define image_get_hdr_b(f) \
+	static inline uint8_t image_get_##f(const image_header_t *hdr) \
+	{ \
+		return hdr->ih_##f; \
+	}
+image_get_hdr_b(os)		/* image_get_os */
+image_get_hdr_b(arch)		/* image_get_arch */
+image_get_hdr_b(type)		/* image_get_type */
+image_get_hdr_b(comp)		/* image_get_comp */
+
+static inline char *image_get_name(const image_header_t *hdr)
+{
+	return (char *)hdr->ih_name;
+}
+
+static inline uint32_t image_get_data_size(const image_header_t *hdr)
+{
+	return image_get_size(hdr);
+}
+
+/**
+ * image_get_data - get image payload start address
+ * @hdr: image header
+ *
+ * image_get_data() returns address of the image payload. For single
+ * component images it is image data start. For multi component
+ * images it points to the null terminated table of sub-images sizes.
+ *
+ * returns:
+ *     image payload data start address
+ */
+static inline ulong image_get_data(const image_header_t *hdr)
+{
+	return ((ulong)hdr + image_get_header_size());
+}
+
+static inline uint32_t image_get_image_size(const image_header_t *hdr)
+{
+	return (image_get_size(hdr) + image_get_header_size());
+}
+static inline ulong image_get_image_end(const image_header_t *hdr)
+{
+	return ((ulong)hdr + image_get_image_size(hdr));
+}
+
+#define image_set_hdr_l(f) \
+	static inline void image_set_##f(image_header_t *hdr, uint32_t val) \
+	{ \
+		hdr->ih_##f = cpu_to_uimage(val); \
+	}
+image_set_hdr_l(magic)		/* image_set_magic */
+image_set_hdr_l(hcrc)		/* image_set_hcrc */
+image_set_hdr_l(time)		/* image_set_time */
+image_set_hdr_l(size)		/* image_set_size */
+image_set_hdr_l(load)		/* image_set_load */
+image_set_hdr_l(ep)		/* image_set_ep */
+image_set_hdr_l(dcrc)		/* image_set_dcrc */
+
+#define image_set_hdr_b(f) \
+	static inline void image_set_##f(image_header_t *hdr, uint8_t val) \
+	{ \
+		hdr->ih_##f = val; \
+	}
+image_set_hdr_b(os)		/* image_set_os */
+image_set_hdr_b(arch)		/* image_set_arch */
+image_set_hdr_b(type)		/* image_set_type */
+image_set_hdr_b(comp)		/* image_set_comp */
+
+static inline void image_set_name(image_header_t *hdr, const char *name)
+{
+	strncpy(image_get_name(hdr), name, IH_NMLEN);
+}
+
+int image_check_hcrc(const image_header_t *hdr);
+int image_check_dcrc(const image_header_t *hdr);
+#ifndef USE_HOSTCC
+int getenv_yesno(char *var);
+ulong getenv_bootm_low(void);
+phys_size_t getenv_bootm_size(void);
+phys_size_t getenv_bootm_mapsize(void);
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz);
+#endif
+
+static inline int image_check_magic(const image_header_t *hdr)
+{
+	return (image_get_magic(hdr) == IH_MAGIC);
+}
+static inline int image_check_type(const image_header_t *hdr, uint8_t type)
+{
+	return (image_get_type(hdr) == type);
+}
+static inline int image_check_arch(const image_header_t *hdr, uint8_t arch)
+{
+	return (image_get_arch(hdr) == arch);
+}
+static inline int image_check_os(const image_header_t *hdr, uint8_t os)
+{
+	return (image_get_os(hdr) == os);
+}
+
+ulong image_multi_count(const image_header_t *hdr);
+void image_multi_getimg(const image_header_t *hdr, ulong idx,
+			ulong *data, ulong *len);
+
+void image_print_contents(const void *hdr);
+
+#ifndef USE_HOSTCC
+static inline int image_check_target_arch(const image_header_t *hdr)
+{
+#ifndef IH_ARCH_DEFAULT
+# error "please define IH_ARCH_DEFAULT in your arch asm/u-boot.h"
+#endif
+	return image_check_arch(hdr, IH_ARCH_DEFAULT);
+}
+#endif /* USE_HOSTCC */
+
+/*******************************************************************/
+/* New uImage format specific code (prefixed with fit_) */
+/*******************************************************************/
+#if defined(CONFIG_FIT)
+
+#define FIT_IMAGES_PATH		"/images"
+#define FIT_CONFS_PATH		"/configurations"
+
+/* hash node */
+#define FIT_HASH_NODENAME	"hash"
+#define FIT_ALGO_PROP		"algo"
+#define FIT_VALUE_PROP		"value"
+
+/* image node */
+#define FIT_DATA_PROP		"data"
+#define FIT_TIMESTAMP_PROP	"timestamp"
+#define FIT_DESC_PROP		"description"
+#define FIT_ARCH_PROP		"arch"
+#define FIT_TYPE_PROP		"type"
+#define FIT_OS_PROP		"os"
+#define FIT_COMP_PROP		"compression"
+#define FIT_ENTRY_PROP		"entry"
+#define FIT_LOAD_PROP		"load"
+
+/* configuration node */
+#define FIT_KERNEL_PROP		"kernel"
+#define FIT_RAMDISK_PROP	"ramdisk"
+#define FIT_FDT_PROP		"fdt"
+#define FIT_DEFAULT_PROP	"default"
+
+#define FIT_MAX_HASH_LEN	20	/* max(crc32_len(4), sha1_len(20)) */
+
+/* cmdline argument format parsing */
+int fit_parse_conf(const char *spec, ulong addr_curr,
+		ulong *addr, const char **conf_name);
+int fit_parse_subimage(const char *spec, ulong addr_curr,
+		ulong *addr, const char **image_name);
+
+void fit_print_contents(const void *fit);
+void fit_image_print(const void *fit, int noffset, const char *p);
+void fit_image_print_hash(const void *fit, int noffset, const char *p);
+
+/**
+ * fit_get_end - get FIT image size
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ *     size of the FIT image (blob) in memory
+ */
+static inline ulong fit_get_size(const void *fit)
+{
+	return fdt_totalsize(fit);
+}
+
+/**
+ * fit_get_end - get FIT image end
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ *     end address of the FIT image (blob) in memory
+ */
+static inline ulong fit_get_end(const void *fit)
+{
+	return (ulong)fit + fdt_totalsize(fit);
+}
+
+/**
+ * fit_get_name - get FIT node name
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ *     NULL, on error
+ *     pointer to node name, on success
+ */
+static inline const char *fit_get_name(const void *fit_hdr,
+		int noffset, int *len)
+{
+	return fdt_get_name(fit_hdr, noffset, len);
+}
+
+int fit_get_desc(const void *fit, int noffset, char **desc);
+int fit_get_timestamp(const void *fit, int noffset, time_t *timestamp);
+
+int fit_image_get_node(const void *fit, const char *image_uname);
+int fit_image_get_os(const void *fit, int noffset, uint8_t *os);
+int fit_image_get_arch(const void *fit, int noffset, uint8_t *arch);
+int fit_image_get_type(const void *fit, int noffset, uint8_t *type);
+int fit_image_get_comp(const void *fit, int noffset, uint8_t *comp);
+int fit_image_get_load(const void *fit, int noffset, ulong *load);
+int fit_image_get_entry(const void *fit, int noffset, ulong *entry);
+int fit_image_get_data(const void *fit, int noffset,
+				const void **data, size_t *size);
+
+int fit_image_hash_get_algo(const void *fit, int noffset, char **algo);
+int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
+				int *value_len);
+
+int fit_set_timestamp(void *fit, int noffset, time_t timestamp);
+int fit_set_hashes(void *fit);
+int fit_image_set_hashes(void *fit, int image_noffset);
+int fit_image_hash_set_value(void *fit, int noffset, uint8_t *value,
+				int value_len);
+
+int fit_image_check_hashes(const void *fit, int noffset);
+int fit_all_image_check_hashes(const void *fit);
+int fit_image_check_os(const void *fit, int noffset, uint8_t os);
+int fit_image_check_arch(const void *fit, int noffset, uint8_t arch);
+int fit_image_check_type(const void *fit, int noffset, uint8_t type);
+int fit_image_check_comp(const void *fit, int noffset, uint8_t comp);
+int fit_check_format(const void *fit);
+
+int fit_conf_get_node(const void *fit, const char *conf_uname);
+int fit_conf_get_kernel_node(const void *fit, int noffset);
+int fit_conf_get_ramdisk_node(const void *fit, int noffset);
+int fit_conf_get_fdt_node(const void *fit, int noffset);
+
+void fit_conf_print(const void *fit, int noffset, const char *p);
+
+#ifndef USE_HOSTCC
+static inline int fit_image_check_target_arch(const void *fdt, int node)
+{
+	return fit_image_check_arch(fdt, node, IH_ARCH_DEFAULT);
+}
+#endif /* USE_HOSTCC */
+
+#ifdef CONFIG_FIT_VERBOSE
+#define fit_unsupported(msg)	printf("! %s:%d " \
+				"FIT images not supported for '%s'\n", \
+				__FILE__, __LINE__, (msg))
+
+#define fit_unsupported_reset(msg)	printf("! %s:%d " \
+				"FIT images not supported for '%s' " \
+				"- must reset board to recover!\n", \
+				__FILE__, __LINE__, (msg))
+#else
+#define fit_unsupported(msg)
+#define fit_unsupported_reset(msg)
+#endif /* CONFIG_FIT_VERBOSE */
+#endif /* CONFIG_FIT */
 
 #endif	/* __IMAGE_H__ */

include/linux/compat.h

diff --git a/include/linux/compat.h b/include/linux/compat.h
new file mode 100644
index 0000000..593b07f
--- /dev/null
+++ b/include/linux/compat.h
@@ -0,0 +1,55 @@
+#ifndef _LINUX_COMPAT_H_
+#define _LINUX_COMPAT_H_
+
+#define __user
+#define __iomem
+
+#define ndelay(x)	udelay(1)
+
+#define printk	printf
+
+#define KERN_EMERG
+#define KERN_ALERT
+#define KERN_CRIT
+#define KERN_ERR
+#define KERN_WARNING
+#define KERN_NOTICE
+#define KERN_INFO
+#define KERN_DEBUG
+
+#define kmalloc(size, flags)	malloc(size)
+#define kzalloc(size, flags)	calloc(size, 1)
+#define vmalloc(size)		malloc(size)
+#define kfree(ptr)		free(ptr)
+#define vfree(ptr)		free(ptr)
+
+#define DECLARE_WAITQUEUE(...)	do { } while (0)
+#define add_wait_queue(...)	do { } while (0)
+#define remove_wait_queue(...)	do { } while (0)
+
+#define KERNEL_VERSION(a,b,c)	(((a) << 16) + ((b) << 8) + (c))
+
+/*
+ * ..and if you can't take the strict
+ * types, you can specify one yourself.
+ *
+ * Or not use min/max at all, of course.
+ */
+#define min_t(type,x,y) \
+	({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+#define max_t(type,x,y) \
+	({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
+
+#ifndef BUG
+#define BUG() do { \
+	printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \
+} while (0)
+
+#define BUG_ON(condition) do { if (condition) BUG(); } while(0)
+#endif /* BUG */
+
+#define WARN_ON(x) if (x) {printf("WARNING in %s line %d\n" \
+				  , __FILE__, __LINE__); }
+
+#define PAGE_SIZE	4096
+#endif

include/linux/compiler-gcc.h

diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
new file mode 100644
index 0000000..73dcf80
--- /dev/null
+++ b/include/linux/compiler-gcc.h
@@ -0,0 +1,87 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
+#endif
+
+/*
+ * Common definitions for all gcc versions go here.
+ */
+
+
+/* Optimization barrier */
+/* The "volatile" is due to gcc bugs */
+#define barrier() __asm__ __volatile__("": : :"memory")
+
+/*
+ * This macro obfuscates arithmetic on a variable address so that gcc
+ * shouldn't recognize the original var, and make assumptions about it.
+ *
+ * This is needed because the C standard makes it undefined to do
+ * pointer arithmetic on "objects" outside their boundaries and the
+ * gcc optimizers assume this is the case. In particular they
+ * assume such arithmetic does not wrap.
+ *
+ * A miscompilation has been observed because of this on PPC.
+ * To work around it we hide the relationship of the pointer and the object
+ * using this macro.
+ *
+ * Versions of the ppc64 compiler before 4.1 had a bug where use of
+ * RELOC_HIDE could trash r30. The bug can be worked around by changing
+ * the inline assembly constraint from =g to =r, in this particular
+ * case either is valid.
+ */
+#define RELOC_HIDE(ptr, off)					\
+  ({ unsigned long __ptr;					\
+    __asm__ ("" : "=r"(__ptr) : "0"(ptr));		\
+    (typeof(ptr)) (__ptr + (off)); })
+
+/* &a[0] degrades to a pointer: a different type from an array */
+#define __must_be_array(a) \
+  BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(typeof(a), typeof(&a[0])))
+
+/*
+ * Force always-inline if the user requests it so via the .config,
+ * or if gcc is too old:
+ */
+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
+    !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
+# define inline		inline		__attribute__((always_inline))
+# define __inline__	__inline__	__attribute__((always_inline))
+# define __inline	__inline	__attribute__((always_inline))
+#endif
+
+#define __deprecated			__attribute__((deprecated))
+#define __packed			__attribute__((packed))
+#define __weak				__attribute__((weak))
+
+/*
+ * it doesn't make sense on ARM (currently the only user of __naked) to trace
+ * naked functions because then mcount is called without stack and frame pointer
+ * being set up and there is no chance to restore the lr register to the value
+ * before mcount was called.
+ */
+#define __naked				__attribute__((naked)) notrace
+
+#define __noreturn			__attribute__((noreturn))
+
+/*
+ * From the GCC manual:
+ *
+ * Many functions have no effects except the return value and their
+ * return value depends only on the parameters and/or global
+ * variables.  Such a function can be subject to common subexpression
+ * elimination and loop optimization just as an arithmetic operator
+ * would be.
+ * [...]
+ */
+#define __pure				__attribute__((pure))
+#define __aligned(x)			__attribute__((aligned(x)))
+#define __printf(a,b)			__attribute__((format(printf,a,b)))
+#define  noinline			__attribute__((noinline))
+#define __attribute_const__		__attribute__((__const__))
+#define __maybe_unused			__attribute__((unused))
+#define __always_unused			__attribute__((unused))
+
+#define __gcc_header(x) #x
+#define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h)
+#define gcc_header(x) _gcc_header(x)
+#include gcc_header(__GNUC__)

include/linux/compiler-gcc4.h

diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h
new file mode 100644
index 0000000..94dea3f
--- /dev/null
+++ b/include/linux/compiler-gcc4.h
@@ -0,0 +1,61 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-gcc4.h> directly, include <linux/compiler.h> instead."
+#endif
+
+/* GCC 4.1.[01] miscompiles __weak */
+#ifdef __KERNEL__
+# if __GNUC_MINOR__ == 1 && __GNUC_PATCHLEVEL__ <= 1
+#  error Your version of gcc miscompiles the __weak directive
+# endif
+#endif
+
+#define __used			__attribute__((__used__))
+#define __must_check 		__attribute__((warn_unused_result))
+#define __compiler_offsetof(a,b) __builtin_offsetof(a,b)
+#define __always_inline		inline __attribute__((always_inline))
+
+/*
+ * A trick to suppress uninitialized variable warning without generating any
+ * code
+ */
+#define uninitialized_var(x) x = x
+
+#if __GNUC_MINOR__ >= 3
+/* Mark functions as cold. gcc will assume any path leading to a call
+   to them will be unlikely.  This means a lot of manual unlikely()s
+   are unnecessary now for any paths leading to the usual suspects
+   like BUG(), printk(), panic() etc. [but let's keep them for now for
+   older compilers]
+
+   Early snapshots of gcc 4.3 don't support this and we can't detect this
+   in the preprocessor, but we can live with this because they're unreleased.
+   Maketime probing would be overkill here.
+
+   gcc also has a __attribute__((__hot__)) to move hot functions into
+   a special section, but I don't see any sense in this right now in
+   the kernel context */
+#define __cold			__attribute__((__cold__))
+
+
+#if __GNUC_MINOR__ >= 5
+/*
+ * Mark a position in code as unreachable.  This can be used to
+ * suppress control flow warnings after asm blocks that transfer
+ * control elsewhere.
+ *
+ * Early snapshots of gcc 4.5 don't support this and we can't detect
+ * this in the preprocessor, but we can live with this because they're
+ * unreleased.  Really, we need to have autoconf for the kernel.
+ */
+#define unreachable() __builtin_unreachable()
+#endif
+
+#endif
+
+#if __GNUC_MINOR__ > 0
+#define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
+#endif
+#if __GNUC_MINOR__ >= 4
+#define __compiletime_warning(message) __attribute__((warning(message)))
+#define __compiletime_error(message) __attribute__((error(message)))
+#endif

include/linux/compiler.h

diff --git a/include/linux/compiler.h b/include/linux/compiler.h
new file mode 100644
index 0000000..5be3dab
--- /dev/null
+++ b/include/linux/compiler.h
@@ -0,0 +1,303 @@
+#ifndef __LINUX_COMPILER_H
+#define __LINUX_COMPILER_H
+
+#ifndef __ASSEMBLY__
+
+#ifdef __CHECKER__
+# define __user		__attribute__((noderef, address_space(1)))
+# define __kernel	/* default address space */
+# define __safe		__attribute__((safe))
+# define __force	__attribute__((force))
+# define __nocast	__attribute__((nocast))
+# define __iomem	__attribute__((noderef, address_space(2)))
+# define __acquires(x)	__attribute__((context(x,0,1)))
+# define __releases(x)	__attribute__((context(x,1,0)))
+# define __acquire(x)	__context__(x,1)
+# define __release(x)	__context__(x,-1)
+# define __cond_lock(x,c)	((c) ? ({ __acquire(x); 1; }) : 0)
+extern void __chk_user_ptr(const volatile void __user *);
+extern void __chk_io_ptr(const volatile void __iomem *);
+#else
+# define __user
+# define __kernel
+# define __safe
+# define __force
+# define __nocast
+# define __iomem
+# define __chk_user_ptr(x) (void)0
+# define __chk_io_ptr(x) (void)0
+# define __builtin_warning(x, y...) (1)
+# define __acquires(x)
+# define __releases(x)
+# define __acquire(x) (void)0
+# define __release(x) (void)0
+# define __cond_lock(x,c) (c)
+#endif
+
+#ifdef __KERNEL__
+
+#ifdef __GNUC__
+#include <linux/compiler-gcc.h>
+#endif
+
+#define notrace __attribute__((no_instrument_function))
+
+/* Intel compiler defines __GNUC__. So we will overwrite implementations
+ * coming from above header files here
+ */
+#ifdef __INTEL_COMPILER
+# include <linux/compiler-intel.h>
+#endif
+
+/*
+ * Generic compiler-dependent macros required for kernel
+ * build go below this comment. Actual compiler/compiler version
+ * specific implementations come from the above header files
+ */
+
+struct ftrace_branch_data {
+	const char *func;
+	const char *file;
+	unsigned line;
+	union {
+		struct {
+			unsigned long correct;
+			unsigned long incorrect;
+		};
+		struct {
+			unsigned long miss;
+			unsigned long hit;
+		};
+		unsigned long miss_hit[2];
+	};
+};
+
+/*
+ * Note: DISABLE_BRANCH_PROFILING can be used by special lowlevel code
+ * to disable branch tracing on a per file basis.
+ */
+#if defined(CONFIG_TRACE_BRANCH_PROFILING) \
+    && !defined(DISABLE_BRANCH_PROFILING) && !defined(__CHECKER__)
+void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+
+#define likely_notrace(x)	__builtin_expect(!!(x), 1)
+#define unlikely_notrace(x)	__builtin_expect(!!(x), 0)
+
+#define __branch_check__(x, expect) ({					\
+			int ______r;					\
+			static struct ftrace_branch_data		\
+				__attribute__((__aligned__(4)))		\
+				__attribute__((section("_ftrace_annotated_branch"))) \
+				______f = {				\
+				.func = __func__,			\
+				.file = __FILE__,			\
+				.line = __LINE__,			\
+			};						\
+			______r = likely_notrace(x);			\
+			ftrace_likely_update(&______f, ______r, expect); \
+			______r;					\
+		})
+
+/*
+ * Using __builtin_constant_p(x) to ignore cases where the return
+ * value is always the same.  This idea is taken from a similar patch
+ * written by Daniel Walker.
+ */
+# ifndef likely
+#  define likely(x)	(__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 1))
+# endif
+# ifndef unlikely
+#  define unlikely(x)	(__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 0))
+# endif
+
+#ifdef CONFIG_PROFILE_ALL_BRANCHES
+/*
+ * "Define 'is'", Bill Clinton
+ * "Define 'if'", Steven Rostedt
+ */
+#define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) )
+#define __trace_if(cond) \
+	if (__builtin_constant_p((cond)) ? !!(cond) :			\
+	({								\
+		int ______r;						\
+		static struct ftrace_branch_data			\
+			__attribute__((__aligned__(4)))			\
+			__attribute__((section("_ftrace_branch")))	\
+			______f = {					\
+				.func = __func__,			\
+				.file = __FILE__,			\
+				.line = __LINE__,			\
+			};						\
+		______r = !!(cond);					\
+		______f.miss_hit[______r]++;					\
+		______r;						\
+	}))
+#endif /* CONFIG_PROFILE_ALL_BRANCHES */
+
+#else
+# define likely(x)	__builtin_expect(!!(x), 1)
+# define unlikely(x)	__builtin_expect(!!(x), 0)
+#endif
+
+/* Optimization barrier */
+#ifndef barrier
+# define barrier() __memory_barrier()
+#endif
+
+/* Unreachable code */
+#ifndef unreachable
+# define unreachable() do { } while (1)
+#endif
+
+#ifndef RELOC_HIDE
+# define RELOC_HIDE(ptr, off)					\
+  ({ unsigned long __ptr;					\
+     __ptr = (unsigned long) (ptr);				\
+    (typeof(ptr)) (__ptr + (off)); })
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+/*
+ * Allow us to mark functions as 'deprecated' and have gcc emit a nice
+ * warning for each use, in hopes of speeding the functions removal.
+ * Usage is:
+ * 		int __deprecated foo(void)
+ */
+#ifndef __deprecated
+# define __deprecated		/* unimplemented */
+#endif
+
+#ifdef MODULE
+#define __deprecated_for_modules __deprecated
+#else
+#define __deprecated_for_modules
+#endif
+
+#ifndef __must_check
+#define __must_check
+#endif
+
+#ifndef CONFIG_ENABLE_MUST_CHECK
+#undef __must_check
+#define __must_check
+#endif
+#ifndef CONFIG_ENABLE_WARN_DEPRECATED
+#undef __deprecated
+#undef __deprecated_for_modules
+#define __deprecated
+#define __deprecated_for_modules
+#endif
+
+/*
+ * Allow us to avoid 'defined but not used' warnings on functions and data,
+ * as well as force them to be emitted to the assembly file.
+ *
+ * As of gcc 3.4, static functions that are not marked with attribute((used))
+ * may be elided from the assembly file.  As of gcc 3.4, static data not so
+ * marked will not be elided, but this may change in a future gcc version.
+ *
+ * NOTE: Because distributions shipped with a backported unit-at-a-time
+ * compiler in gcc 3.3, we must define __used to be __attribute__((used))
+ * for gcc >=3.3 instead of 3.4.
+ *
+ * In prior versions of gcc, such functions and data would be emitted, but
+ * would be warned about except with attribute((unused)).
+ *
+ * Mark functions that are referenced only in inline assembly as __used so
+ * the code is emitted even though it appears to be unreferenced.
+ */
+#ifndef __used
+# define __used			/* unimplemented */
+#endif
+
+#ifndef __maybe_unused
+# define __maybe_unused		/* unimplemented */
+#endif
+
+#ifndef __always_unused
+# define __always_unused	/* unimplemented */
+#endif
+
+#ifndef noinline
+#define noinline
+#endif
+
+/*
+ * Rather then using noinline to prevent stack consumption, use
+ * noinline_for_stack instead.  For documentaiton reasons.
+ */
+#define noinline_for_stack noinline
+
+#ifndef __always_inline
+#define __always_inline inline
+#endif
+
+#endif /* __KERNEL__ */
+
+/*
+ * From the GCC manual:
+ *
+ * Many functions do not examine any values except their arguments,
+ * and have no effects except the return value.  Basically this is
+ * just slightly more strict class than the `pure' attribute above,
+ * since function is not allowed to read global memory.
+ *
+ * Note that a function that has pointer arguments and examines the
+ * data pointed to must _not_ be declared `const'.  Likewise, a
+ * function that calls a non-`const' function usually must not be
+ * `const'.  It does not make sense for a `const' function to return
+ * `void'.
+ */
+#ifndef __attribute_const__
+# define __attribute_const__	/* unimplemented */
+#endif
+
+/*
+ * Tell gcc if a function is cold. The compiler will assume any path
+ * directly leading to the call is unlikely.
+ */
+
+#ifndef __cold
+#define __cold
+#endif
+
+/* Simple shorthand for a section definition */
+#ifndef __section
+# define __section(S) __attribute__ ((__section__(#S)))
+#endif
+
+/* Are two types/vars the same type (ignoring qualifiers)? */
+#ifndef __same_type
+# define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
+#endif
+
+/* Compile time object size, -1 for unknown */
+#ifndef __compiletime_object_size
+# define __compiletime_object_size(obj) -1
+#endif
+#ifndef __compiletime_warning
+# define __compiletime_warning(message)
+#endif
+#ifndef __compiletime_error
+# define __compiletime_error(message)
+#endif
+
+/*
+ * Prevent the compiler from merging or refetching accesses.  The compiler
+ * is also forbidden from reordering successive instances of ACCESS_ONCE(),
+ * but only when the compiler is aware of some particular ordering.  One way
+ * to make the compiler aware of ordering is to put the two invocations of
+ * ACCESS_ONCE() in different C statements.
+ *
+ * This macro does absolutely -nothing- to prevent the CPU from reordering,
+ * merging, or refetching absolutely anything at any time.  Its main intended
+ * use is to mediate communication between process-level code and irq/NMI
+ * handlers, all running on the same CPU.
+ */
+#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
+
+#endif /* __LINUX_COMPILER_H */

include/linux/err.h

diff --git a/include/linux/err.h b/include/linux/err.h
new file mode 100644
index 0000000..96c0c72
--- /dev/null
+++ b/include/linux/err.h
@@ -0,0 +1,45 @@
+#ifndef _LINUX_ERR_H
+#define _LINUX_ERR_H
+
+/* XXX U-BOOT XXX */
+#if 0
+#include <linux/compiler.h>
+#else
+#include <linux/compat.h>
+#endif
+
+#include <asm/errno.h>
+
+
+/*
+ * Kernel pointers have redundant information, so we can use a
+ * scheme where we can return either an error code or a dentry
+ * pointer with the same return value.
+ *
+ * This should be a per-architecture thing, to allow different
+ * error and pointer decisions.
+ */
+#define MAX_ERRNO	4095
+
+#ifndef __ASSEMBLY__
+
+#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
+
+static inline void *ERR_PTR(long error)
+{
+	return (void *) error;
+}
+
+static inline long PTR_ERR(const void *ptr)
+{
+	return (long) ptr;
+}
+
+static inline long IS_ERR(const void *ptr)
+{
+	return IS_ERR_VALUE((unsigned long)ptr);
+}
+
+#endif
+
+#endif /* _LINUX_ERR_H */

include/linux/linkage.h

diff --git a/include/linux/linkage.h b/include/linux/linkage.h
new file mode 100644
index 0000000..821b2cb
--- /dev/null
+++ b/include/linux/linkage.h
@@ -0,0 +1,95 @@
+#ifndef _LINUX_LINKAGE_H
+#define _LINUX_LINKAGE_H
+
+#include <asm/arch/linkage_c2000.h>
+
+#ifdef __cplusplus
+#define CPP_ASMLINKAGE extern "C"
+#else
+#define CPP_ASMLINKAGE
+#endif
+
+#ifndef asmlinkage
+#define asmlinkage CPP_ASMLINKAGE
+#endif
+
+#ifndef asmregparm
+# define asmregparm
+#endif
+
+#define __page_aligned_data	__section(.data.page_aligned) __aligned(PAGE_SIZE)
+#define __page_aligned_bss	__section(.bss.page_aligned) __aligned(PAGE_SIZE)
+
+/*
+ * This is used by architectures to keep arguments on the stack
+ * untouched by the compiler by keeping them live until the end.
+ * The argument stack may be owned by the assembly-language
+ * caller, not the callee, and gcc doesn't always understand
+ * that.
+ *
+ * We have the return value, and a maximum of six arguments.
+ *
+ * This should always be followed by a "return ret" for the
+ * protection to work (ie no more work that the compiler might
+ * end up needing stack temporaries for).
+ */
+/* Assembly files may be compiled with -traditional .. */
+#ifndef __ASSEMBLY__
+#ifndef asmlinkage_protect
+# define asmlinkage_protect(n, ret, args...)	do { } while (0)
+#endif
+#endif
+
+#ifndef __ALIGN
+#define __ALIGN		.align 4,0x90
+#define __ALIGN_STR	".align 4,0x90"
+#endif
+
+#ifdef __ASSEMBLY__
+
+#define ALIGN __ALIGN
+#define ALIGN_STR __ALIGN_STR
+
+#ifndef ENTRY
+#define ENTRY(name) \
+  .globl name; \
+  ALIGN; \
+  name:
+#endif
+
+#ifndef WEAK
+#define WEAK(name)	   \
+	.weak name;	   \
+	name:
+#endif
+
+#define KPROBE_ENTRY(name) \
+  .pushsection .kprobes.text, "ax"; \
+  ENTRY(name)
+
+#define KPROBE_END(name) \
+  END(name);		 \
+  .popsection
+
+#ifndef END
+#define END(name) \
+  .size name, .-name
+#endif
+
+/* If symbol 'name' is treated as a subroutine (gets called, and returns)
+ * then please use ENDPROC to mark 'name' as STT_FUNC for the benefit of
+ * static analysis tools such as stack depth analyzer.
+ */
+#ifndef ENDPROC
+#define ENDPROC(name) \
+  .type name, @function; \
+  END(name)
+#endif
+
+#endif
+
+#define NORET_TYPE    /**/
+#define ATTRIB_NORET  __attribute__((noreturn))
+#define NORET_AND     noreturn,
+
+#endif

include/linux/mtd/bbm.h

diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
new file mode 100644
index 0000000..8cbcdae
--- /dev/null
+++ b/include/linux/mtd/bbm.h
@@ -0,0 +1,153 @@
+/*
+ *  linux/include/linux/mtd/bbm.h
+ *
+ *  NAND family Bad Block Management (BBM) header file
+ *    - Bad Block Table (BBT) implementation
+ *
+ *  Copyright (c) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ *  Copyright (c) 2000-2005
+ *  Thomas Gleixner <tglx@linuxtronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+#ifndef __LINUX_MTD_BBM_H
+#define __LINUX_MTD_BBM_H
+
+/* The maximum number of NAND chips in an array */
+#ifndef CONFIG_SYS_NAND_MAX_CHIPS
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#endif
+
+/**
+ * struct nand_bbt_descr - bad block table descriptor
+ * @param options	options for this descriptor
+ * @param pages		the page(s) where we find the bbt, used with
+ *			option BBT_ABSPAGE when bbt is searched,
+ *			then we store the found bbts pages here.
+ *			Its an array and supports up to 8 chips now
+ * @param offs		offset of the pattern in the oob area of the page
+ * @param veroffs	offset of the bbt version counter in the oob are of the page
+ * @param version	version read from the bbt page during scan
+ * @param len		length of the pattern, if 0 no pattern check is performed
+ * @param maxblocks	maximum number of blocks to search for a bbt. This number of
+ *			blocks is reserved at the end of the device
+ *			where the tables are written.
+ * @param reserved_block_code	if non-0, this pattern denotes a reserved
+ *			(rather than bad) block in the stored bbt
+ * @param pattern	pattern to identify bad block table or factory marked
+ *			good / bad blocks, can be NULL, if len = 0
+ *
+ * Descriptor for the bad block table marker and the descriptor for the
+ * pattern which identifies good and bad blocks. The assumption is made
+ * that the pattern and the version count are always located in the oob area
+ * of the first block.
+ */
+struct nand_bbt_descr {
+	int options;
+	int pages[CONFIG_SYS_NAND_MAX_CHIPS];
+	int offs;
+	int veroffs;
+	uint8_t version[CONFIG_SYS_NAND_MAX_CHIPS];
+	int len;
+	int maxblocks;
+	int reserved_block_code;
+	uint8_t *pattern;
+};
+
+/* Options for the bad block table descriptors */
+
+/* The number of bits used per block in the bbt on the device */
+#define NAND_BBT_NRBITS_MSK	0x0000000F
+#define NAND_BBT_1BIT		0x00000001
+#define NAND_BBT_2BIT		0x00000002
+#define NAND_BBT_4BIT		0x00000004
+#define NAND_BBT_8BIT		0x00000008
+/* The bad block table is in the last good block of the device */
+#define NAND_BBT_LASTBLOCK	0x00000010
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_ABSPAGE	0x00000020
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_SEARCH		0x00000040
+/* bbt is stored per chip on multichip devices */
+#define NAND_BBT_PERCHIP	0x00000080
+/* bbt has a version counter at offset veroffs */
+#define NAND_BBT_VERSION	0x00000100
+/* Create a bbt if none exists */
+#define NAND_BBT_CREATE		0x00000200
+/* Search good / bad pattern through all pages of a block */
+#define NAND_BBT_SCANALLPAGES	0x00000400
+/* Scan block empty during good / bad block scan */
+#define NAND_BBT_SCANEMPTY	0x00000800
+/* Write bbt if neccecary */
+#define NAND_BBT_WRITE		0x00001000
+/* Read and write back block contents when writing bbt */
+#define NAND_BBT_SAVECONTENT	0x00002000
+/* Search good / bad pattern on the first and the second page */
+#define NAND_BBT_SCAN2NDPAGE	0x00004000
+/* Search good / bad pattern on the last page of the eraseblock */
+#define NAND_BBT_SCANLASTPAGE	0x00008000
+/* Chip stores bad block marker on BOTH 1st and 6th bytes of OOB */
+#define NAND_BBT_SCANBYTE1AND6 0x00100000
+/* The nand_bbt_descr was created dynamicaly and must be freed */
+#define NAND_BBT_DYNAMICSTRUCT 0x00200000
+/* The bad block table does not OOB for marker */
+#define NAND_BBT_NO_OOB		0x00400000
+
+/* The maximum number of blocks to scan for a bbt */
+#define NAND_BBT_SCAN_MAXBLOCKS	4
+
+/*
+ * Constants for oob configuration
+ */
+#define ONENAND_BADBLOCK_POS	0
+
+/*
+ * Bad block scanning errors
+ */
+#define ONENAND_BBT_READ_ERROR          1
+#define ONENAND_BBT_READ_ECC_ERROR      2
+#define ONENAND_BBT_READ_FATAL_ERROR    4
+
+/**
+ * struct bbt_info - [GENERIC] Bad Block Table data structure
+ * @param bbt_erase_shift	[INTERN] number of address bits in a bbt entry
+ * @param badblockpos		[INTERN] position of the bad block marker in the oob area
+ * @param bbt			[INTERN] bad block table pointer
+ * @param badblock_pattern	[REPLACEABLE] bad block scan pattern used for initial bad block scan
+ * @param priv			[OPTIONAL] pointer to private bbm date
+ */
+struct bbm_info {
+	int bbt_erase_shift;
+	int badblockpos;
+	int options;
+
+	uint8_t *bbt;
+
+	int (*isbad_bbt) (struct mtd_info * mtd, loff_t ofs, int allowbbt);
+
+	/* TODO Add more NAND specific fileds */
+	struct nand_bbt_descr *badblock_pattern;
+
+	void *priv;
+};
+
+/* OneNAND BBT interface */
+extern int onenand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int onenand_default_bbt (struct mtd_info *mtd);
+
+#endif				/* __LINUX_MTD_BBM_H */

include/linux/mtd/mtd-abi.h

diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
index 3d1d416..0e09062 100644
--- a/include/linux/mtd/mtd-abi.h
+++ b/include/linux/mtd/mtd-abi.h
@@ -7,6 +7,10 @@
 #ifndef __MTD_ABI_H__
 #define __MTD_ABI_H__
 
+#if 1
+#include <linux/compat.h>
+#endif
+
 struct erase_info_user {
 	uint32_t start;
 	uint32_t length;
@@ -15,7 +19,7 @@
 struct mtd_oob_buf {
 	uint32_t start;
 	uint32_t length;
-	unsigned char *ptr;
+	unsigned char __user *ptr;
 };
 
 #define MTD_ABSENT		0
@@ -23,47 +27,41 @@
 #define MTD_ROM			2
 #define MTD_NORFLASH		3
 #define MTD_NANDFLASH		4
-#define MTD_PEROM		5
-#define MTD_OTHER		14
-#define MTD_UNKNOWN		15
+#define MTD_DATAFLASH		6
+#define MTD_UBIVOLUME		7
 
-#define MTD_CLEAR_BITS		1       /* Bits can be cleared (flash) */
-#define MTD_SET_BITS		2       /* Bits can be set */
-#define MTD_ERASEABLE		4       /* Has an erase function */
-#define MTD_WRITEB_WRITEABLE	8       /* Direct IO is possible */
-#define MTD_VOLATILE		16      /* Set for RAMs */
-#define MTD_XIP			32	/* eXecute-In-Place possible */
-#define MTD_OOB			64	/* Out-of-band data (NAND flash) */
-#define MTD_ECC			128	/* Device capable of automatic ECC */
-#define MTD_NO_VIRTBLOCKS	256	/* Virtual blocks not allowed */
+#define MTD_WRITEABLE		0x400	/* Device is writeable */
+#define MTD_BIT_WRITEABLE	0x800	/* Single bits can be flipped */
+#define MTD_NO_ERASE		0x1000	/* No erase necessary */
+#define MTD_STUPID_LOCK		0x2000	/* Always locked after reset */
 
 /* Some common devices / combinations of capabilities */
 #define MTD_CAP_ROM		0
-#define MTD_CAP_RAM		(MTD_CLEAR_BITS|MTD_SET_BITS|MTD_WRITEB_WRITEABLE)
-#define MTD_CAP_NORFLASH        (MTD_CLEAR_BITS|MTD_ERASEABLE)
-#define MTD_CAP_NANDFLASH       (MTD_CLEAR_BITS|MTD_ERASEABLE|MTD_OOB)
-#define MTD_WRITEABLE		(MTD_CLEAR_BITS|MTD_SET_BITS)
-
-
-/* Types of automatic ECC/Checksum available */
-#define MTD_ECC_NONE		0 	/* No automatic ECC available */
-#define MTD_ECC_RS_DiskOnChip	1	/* Automatic ECC on DiskOnChip */
-#define MTD_ECC_SW		2	/* SW ECC for Toshiba & Samsung devices */
+#define MTD_CAP_RAM		(MTD_WRITEABLE | MTD_BIT_WRITEABLE | MTD_NO_ERASE)
+#define MTD_CAP_NORFLASH	(MTD_WRITEABLE | MTD_BIT_WRITEABLE)
+#define MTD_CAP_NANDFLASH	(MTD_WRITEABLE)
 
 /* ECC byte placement */
 #define MTD_NANDECC_OFF		0	/* Switch off ECC (Not recommended) */
 #define MTD_NANDECC_PLACE	1	/* Use the given placement in the structure (YAFFS1 legacy mode) */
 #define MTD_NANDECC_AUTOPLACE	2	/* Use the default placement scheme */
 #define MTD_NANDECC_PLACEONLY	3	/* Use the given placement in the structure (Do not store ecc result on read) */
-#define MTD_NANDECC_AUTOPL_USR 	4	/* Use the given autoplacement scheme rather than using the default */
+#define MTD_NANDECC_AUTOPL_USR	4	/* Use the given autoplacement scheme rather than using the default */
+
+/* OTP mode selection */
+#define MTD_OTP_OFF		0
+#define MTD_OTP_FACTORY		1
+#define MTD_OTP_USER		2
 
 struct mtd_info_user {
 	uint8_t type;
 	uint32_t flags;
-	uint32_t size;	 /* Total size of the MTD */
+	uint32_t size;			/* Total size of the MTD */
 	uint32_t erasesize;
-	uint32_t oobblock;  /* Size of OOB blocks (e.g. 512) */
-	uint32_t oobsize;   /* Amount of OOB data per block (e.g. 16) */
+	uint32_t writesize;
+	uint32_t oobsize;		/* Amount of OOB data per block (e.g. 16) */
+	/* The below two fields are obsolete and broken, do not use them
+	 * (TODO: remove at some point) */
 	uint32_t ecctype;
 	uint32_t eccsize;
 };
@@ -76,24 +74,83 @@
 	uint32_t regionindex;
 };
 
-#define MEMGETINFO              _IOR('M', 1, struct mtd_info_user)
-#define MEMERASE                _IOW('M', 2, struct erase_info_user)
-#define MEMWRITEOOB             _IOWR('M', 3, struct mtd_oob_buf)
-#define MEMREADOOB              _IOWR('M', 4, struct mtd_oob_buf)
-#define MEMLOCK                 _IOW('M', 5, struct erase_info_user)
-#define MEMUNLOCK               _IOW('M', 6, struct erase_info_user)
+struct otp_info {
+	uint32_t start;
+	uint32_t length;
+	uint32_t locked;
+};
+
+#define MEMGETINFO		_IOR('M', 1, struct mtd_info_user)
+#define MEMERASE		_IOW('M', 2, struct erase_info_user)
+#define MEMWRITEOOB		_IOWR('M', 3, struct mtd_oob_buf)
+#define MEMREADOOB		_IOWR('M', 4, struct mtd_oob_buf)
+#define MEMLOCK			_IOW('M', 5, struct erase_info_user)
+#define MEMUNLOCK		_IOW('M', 6, struct erase_info_user)
 #define MEMGETREGIONCOUNT	_IOR('M', 7, int)
 #define MEMGETREGIONINFO	_IOWR('M', 8, struct region_info_user)
 #define MEMSETOOBSEL		_IOW('M', 9, struct nand_oobinfo)
 #define MEMGETOOBSEL		_IOR('M', 10, struct nand_oobinfo)
 #define MEMGETBADBLOCK		_IOW('M', 11, loff_t)
 #define MEMSETBADBLOCK		_IOW('M', 12, loff_t)
+#define OTPSELECT		_IOR('M', 13, int)
+#define OTPGETREGIONCOUNT	_IOW('M', 14, int)
+#define OTPGETREGIONINFO	_IOW('M', 15, struct otp_info)
+#define OTPLOCK			_IOR('M', 16, struct otp_info)
+#define ECCGETLAYOUT		_IOR('M', 17, struct nand_ecclayout)
+#define ECCGETSTATS		_IOR('M', 18, struct mtd_ecc_stats)
+#define MTDFILEMODE		_IO('M', 19)
 
+/*
+ * Obsolete legacy interface. Keep it in order not to break userspace
+ * interfaces
+ */
 struct nand_oobinfo {
 	uint32_t useecc;
 	uint32_t eccbytes;
 	uint32_t oobfree[8][2];
-	uint32_t eccpos[32];
+	uint32_t eccpos[48];
+};
+
+struct nand_oobfree {
+	uint32_t offset;
+	uint32_t length;
+};
+
+#define MTD_MAX_OOBFREE_ENTRIES	8
+/*
+ * ECC layout control structure. Exported to userspace for
+ * diagnosis and to allow creation of raw images
+ */
+struct nand_ecclayout {
+	uint32_t eccbytes;
+	uint32_t eccpos[128];
+	uint32_t oobavail;
+	struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
+};
+
+/**
+ * struct mtd_ecc_stats - error correction stats
+ *
+ * @corrected:	number of corrected bits
+ * @failed:	number of uncorrectable errors
+ * @badblocks:	number of bad blocks in this partition
+ * @bbtblocks:	number of blocks reserved for bad block tables
+ */
+struct mtd_ecc_stats {
+	uint32_t corrected;
+	uint32_t failed;
+	uint32_t badblocks;
+	uint32_t bbtblocks;
+};
+
+/*
+ * Read/write file modes for access to MTD
+ */
+enum mtd_file_modes {
+	MTD_MODE_NORMAL = MTD_OTP_OFF,
+	MTD_MODE_OTP_FACTORY = MTD_OTP_FACTORY,
+	MTD_MODE_OTP_USER = MTD_OTP_USER,
+	MTD_MODE_RAW,
 };
 
 #endif /* __MTD_ABI_H__ */

include/linux/mtd/mtd.h

diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 13e9080..b06e829 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -1,6 +1,4 @@
 /*
- * $Id: mtd.h,v 1.56 2004/08/09 18:46:04 dmarlin Exp $
- *
  * Copyright (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> et al.
  *
  * Released under GPL
@@ -8,25 +6,49 @@
 
 #ifndef __MTD_MTD_H__
 #define __MTD_MTD_H__
+
 #include <linux/types.h>
+#include "../../types.h"
+#include <div64.h>
 #include <linux/mtd/mtd-abi.h>
 
-#define MAX_MTD_DEVICES 16
 
-#define MTD_ERASE_PENDING      	0x01
+#define MTD_CHAR_MAJOR 90
+#define MTD_BLOCK_MAJOR 31
+#define MAX_MTD_DEVICES 32
+
+#define MTD_ERASE_PENDING	0x01
 #define MTD_ERASING		0x02
 #define MTD_ERASE_SUSPEND	0x04
 #define MTD_ERASE_DONE          0x08
 #define MTD_ERASE_FAILED        0x10
 
+#define MTD_FAIL_ADDR_UNKNOWN	-1LL
+
+/*
+ * Enumeration for NAND/OneNAND flash chip state
+ */
+enum {
+	FL_READY,
+	FL_READING,
+	FL_WRITING,
+	FL_ERASING,
+	FL_SYNCING,
+	FL_CACHEDPRG,
+	FL_RESETING,
+	FL_UNLOCKING,
+	FL_LOCKING,
+	FL_PM_SUSPENDED,
+};
+
 /* If the erase fails, fail_addr might indicate exactly which block failed.  If
-   fail_addr = 0xffffffff, the failure was not at the device level or was not
+   fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not at the device level or was not
    specific to any particular block. */
 struct erase_info {
 	struct mtd_info *mtd;
-	u_int32_t addr;
-	u_int32_t len;
-	u_int32_t fail_addr;
+	uint64_t addr;
+	uint64_t len;
+	uint64_t fail_addr;
 	u_long time;
 	u_long retries;
 	u_int dev;
@@ -35,38 +57,91 @@
 	u_long priv;
 	u_char state;
 	struct erase_info *next;
+	int scrub;
 };
 
 struct mtd_erase_region_info {
-	u_int32_t offset;			/* At which this region starts, from the beginning of the MTD */
+	uint64_t offset;			/* At which this region starts, from the beginning of the MTD */
 	u_int32_t erasesize;		/* For this region */
 	u_int32_t numblocks;		/* Number of blocks of erasesize in this region */
+	unsigned long *lockmap;		/* If keeping bitmap of locks */
+};
+
+/*
+ * oob operation modes
+ *
+ * MTD_OOB_PLACE:	oob data are placed at the given offset
+ * MTD_OOB_AUTO:	oob data are automatically placed at the free areas
+ *			which are defined by the ecclayout
+ * MTD_OOB_RAW:		mode to read raw data+oob in one chunk. The oob data
+ *			is inserted into the data. Thats a raw image of the
+ *			flash contents.
+ */
+typedef enum {
+	MTD_OOB_PLACE,
+	MTD_OOB_AUTO,
+	MTD_OOB_RAW,
+} mtd_oob_mode_t;
+
+/**
+ * struct mtd_oob_ops - oob operation operands
+ * @mode:	operation mode
+ *
+ * @len:	number of data bytes to write/read
+ *
+ * @retlen:	number of data bytes written/read
+ *
+ * @ooblen:	number of oob bytes to write/read
+ * @oobretlen:	number of oob bytes written/read
+ * @ooboffs:	offset of oob data in the oob area (only relevant when
+ *		mode = MTD_OOB_PLACE)
+ * @datbuf:	data buffer - if NULL only oob data are read/written
+ * @oobbuf:	oob data buffer
+ *
+ * Note, it is allowed to read more then one OOB area at one go, but not write.
+ * The interface assumes that the OOB write requests program only one page's
+ * OOB area.
+ */
+struct mtd_oob_ops {
+	mtd_oob_mode_t	mode;
+	size_t		len;
+	size_t		retlen;
+	size_t		ooblen;
+	size_t		oobretlen;
+	uint32_t	ooboffs;
+	uint8_t		*datbuf;
+	uint8_t		*oobbuf;
 };
 
 struct mtd_info {
 	u_char type;
 	u_int32_t flags;
-	u_int32_t size;	 /* Total size of the MTD */
+	uint64_t size;	 /* Total size of the MTD */
 
-	/* "Major" erase size for the device. Naïve users may take this
+	/* "Major" erase size for the device. Naïve users may take this
 	 * to be the only erase size available, or may use the more detailed
 	 * information below if they desire
 	 */
 	u_int32_t erasesize;
+	/* Minimal writable flash unit size. In case of NOR flash it is 1 (even
+	 * though individual bits can be cleared), in case of NAND flash it is
+	 * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR
+	 * it is of ECC block size, etc. It is illegal to have writesize = 0.
+	 * Any driver registering a struct mtd_info must ensure a writesize of
+	 * 1 or larger.
+	 */
+	u_int32_t writesize;
 
 	u_int32_t oobblock;  /* Size of OOB blocks (e.g. 512) */
 	u_int32_t oobsize;   /* Amount of OOB data per block (e.g. 16) */
-	u_int32_t oobavail;  /* Number of bytes in OOB area available for fs  */
-	u_int32_t ecctype;
-	u_int32_t eccsize;
-
+	u_int32_t oobavail;  /* Available OOB bytes per block */
 
 	/* Kernel-only stuff starts here. */
-	char *name;
+	const char *name;
 	int index;
 
-	/* oobinfo is a nand_oobinfo structure, which can be set by iotcl (MEMSETOOBINFO) */
-	struct nand_oobinfo oobinfo;
+	/* ecc layout structure pointer - read only ! */
+	struct nand_ecclayout *ecclayout;
 
 	/* Data for variable erase regions. If numeraseregions is zero,
 	 * it means that the whole device has erasesize as given above.
@@ -74,72 +149,105 @@
 	int numeraseregions;
 	struct mtd_erase_region_info *eraseregions;
 
-	/* This really shouldn't be here. It can go away in 2.5 */
-	u_int32_t bank_size;
-
+	/*
+	 * Erase is an asynchronous operation.  Device drivers are supposed
+	 * to call instr->callback() whenever the operation completes, even
+	 * if it completes with a failure.
+	 * Callers are supposed to pass a callback function and wait for it
+	 * to be called before writing to the block.
+	 */
 	int (*erase) (struct mtd_info *mtd, struct erase_info *instr);
 
 	/* This stuff for eXecute-In-Place */
-	int (*point) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char **mtdbuf);
+	/* phys is optional and may be set to NULL */
+	int (*point) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, void **virt, phys_addr_t *phys);
 
 	/* We probably shouldn't allow XIP if the unpoint isn't a NULL */
-	void (*unpoint) (struct mtd_info *mtd, u_char * addr, loff_t from, size_t len);
+	void (*unpoint) (struct mtd_info *mtd, loff_t from, size_t len);
 
 
 	int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
 	int (*write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
 
-	int (*read_ecc) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel);
-	int (*write_ecc) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel);
+	/* In blackbox flight recorder like scenarios we want to make successful
+	   writes in interrupt context. panic_write() is only intended to be
+	   called when its known the kernel is about to panic and we need the
+	   write to succeed. Since the kernel is not going to be running for much
+	   longer, this function can break locks and delay to ensure the write
+	   succeeds (but not sleep). */
 
-	int (*read_oob) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
-	int (*write_oob) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
+	int (*panic_write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
+
+	int (*read_oob) (struct mtd_info *mtd, loff_t from,
+			 struct mtd_oob_ops *ops);
+	int (*write_oob) (struct mtd_info *mtd, loff_t to,
+			 struct mtd_oob_ops *ops);
 
 	/*
 	 * Methods to access the protection register area, present in some
 	 * flash devices. The user data is one time programmable but the
 	 * factory data is read only.
 	 */
-	int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
-
+	int (*get_fact_prot_info) (struct mtd_info *mtd, struct otp_info *buf, size_t len);
 	int (*read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
-
-	/* This function is not yet implemented */
+	int (*get_user_prot_info) (struct mtd_info *mtd, struct otp_info *buf, size_t len);
+	int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
 	int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
+	int (*lock_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len);
+
+/* XXX U-BOOT XXX */
 #if 0
-	/* kvec-based read/write methods. We need these especially for NAND flash,
-	   with its limited number of write cycles per erase.
+	/* kvec-based read/write methods.
 	   NB: The 'count' parameter is the number of _vectors_, each of
 	   which contains an (ofs, len) tuple.
 	*/
-	int (*readv) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, size_t *retlen);
-	int (*readv_ecc) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from,
-		size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel);
 	int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen);
-	int (*writev_ecc) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to,
-		size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel);
 #endif
+
 	/* Sync */
 	void (*sync) (struct mtd_info *mtd);
-#if 0
-	/* Chip-supported device locking */
-	int (*lock) (struct mtd_info *mtd, loff_t ofs, size_t len);
-	int (*unlock) (struct mtd_info *mtd, loff_t ofs, size_t len);
 
-	/* Power Management functions */
-	int (*suspend) (struct mtd_info *mtd);
-	void (*resume) (struct mtd_info *mtd);
-#endif
+	/* Chip-supported device locking */
+	int (*lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
+	int (*unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
+
 	/* Bad block management functions */
 	int (*block_isbad) (struct mtd_info *mtd, loff_t ofs);
 	int (*block_markbad) (struct mtd_info *mtd, loff_t ofs);
 
+/* XXX U-BOOT XXX */
+#if 0
+	struct notifier_block reboot_notifier;  /* default mode before reboot */
+#endif
+
+	/* ECC status information */
+	struct mtd_ecc_stats ecc_stats;
+	/* Subpage shift (NAND) */
+	int subpage_sft;
+
 	void *priv;
 
 	struct module *owner;
 	int usecount;
+
+	/* If the driver is something smart, like UBI, it may need to maintain
+	 * its own reference counting. The below functions are only for driver.
+	 * The driver may register its callbacks. These callbacks are not
+	 * supposed to be called by MTD users */
+	int (*get_device) (struct mtd_info *mtd);
+	void (*put_device) (struct mtd_info *mtd);
 };
 
+static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd)
+{
+	do_div(sz, mtd->erasesize);
+	return sz;
+}
+
+static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd)
+{
+	return do_div(sz, mtd->erasesize);
+}
 
 	/* Kernel-side ioctl definitions */
 
@@ -147,9 +255,13 @@
 extern int del_mtd_device (struct mtd_info *mtd);
 
 extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num);
+extern struct mtd_info *get_mtd_device_nm(const char *name);
 
 extern void put_mtd_device(struct mtd_info *mtd);
-
+extern void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset,
+				 const uint64_t length, uint64_t *len_incl_bad,
+				 int *truncated);
+/* XXX U-BOOT XXX */
 #if 0
 struct mtd_notifier {
 	void (*add)(struct mtd_info *mtd);
@@ -157,7 +269,6 @@
 	struct list_head list;
 };
 
-
 extern void register_mtd_user (struct mtd_notifier *new);
 extern int unregister_mtd_user (struct mtd_notifier *old);
 
@@ -168,20 +279,6 @@
 		      unsigned long count, loff_t from, size_t *retlen);
 #endif
 
-#define MTD_ERASE(mtd, args...) (*(mtd->erase))(mtd, args)
-#define MTD_POINT(mtd, a,b,c,d) (*(mtd->point))(mtd, a,b,c, (u_char **)(d))
-#define MTD_UNPOINT(mtd, arg) (*(mtd->unpoint))(mtd, (u_char *)arg)
-#define MTD_READ(mtd, args...) (*(mtd->read))(mtd, args)
-#define MTD_WRITE(mtd, args...) (*(mtd->write))(mtd, args)
-#define MTD_READV(mtd, args...) (*(mtd->readv))(mtd, args)
-#define MTD_WRITEV(mtd, args...) (*(mtd->writev))(mtd, args)
-#define MTD_READECC(mtd, args...) (*(mtd->read_ecc))(mtd, args)
-#define MTD_WRITEECC(mtd, args...) (*(mtd->write_ecc))(mtd, args)
-#define MTD_READOOB(mtd, args...) (*(mtd->read_oob))(mtd, args)
-#define MTD_WRITEOOB(mtd, args...) (*(mtd->write_oob))(mtd, args)
-#define MTD_SYNC(mtd) do { if (mtd->sync) (*(mtd->sync))(mtd);  } while (0)
-
-
 #ifdef CONFIG_MTD_PARTITIONS
 void mtd_erase_callback(struct erase_info *instr);
 #else
@@ -201,14 +298,17 @@
 #define MTD_DEBUG_LEVEL3	(3)	/* Noisy   */
 
 #ifdef CONFIG_MTD_DEBUG
-#define DEBUG(n, args...)				\
- 	do {						\
+#define MTDDEBUG(n, args...)				\
+	do {						\
 		if (n <= CONFIG_MTD_DEBUG_VERBOSE)	\
 			printk(KERN_INFO args);		\
 	} while(0)
 #else /* CONFIG_MTD_DEBUG */
-#define DEBUG(n, args...) do { } while(0)
-
+#define MTDDEBUG(n, args...)				\
+	do {						\
+		if (0)					\
+			printk(KERN_INFO args);		\
+	} while(0)
 #endif /* CONFIG_MTD_DEBUG */
 
 #endif /* __MTD_MTD_H__ */

include/linux/mtd/nand.h

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 4b48564..82704de 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -1,115 +1,119 @@
 /*
  *  linux/include/linux/mtd/nand.h
  *
- *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
- *		       Steven J. Hill <sjhill@realitydiluted.com>
- *		       Thomas Gleixner <tglx@linutronix.de>
- *
- * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
+ *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
+ *                        Steven J. Hill <sjhill@realitydiluted.com>
+ *		          Thomas Gleixner <tglx@linutronix.de>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- *  Info:
- *   Contains standard defines and IDs for NAND flash devices
+ * Info:
+ *	Contains standard defines and IDs for NAND flash devices
  *
- *  Changelog:
- *   01-31-2000 DMW	Created
- *   09-18-2000 SJH	Moved structure out of the Disk-On-Chip drivers
- *			so it can be used by other NAND flash device
- *			drivers. I also changed the copyright since none
- *			of the original contents of this file are specific
- *			to DoC devices. David can whack me with a baseball
- *			bat later if I did something naughty.
- *   10-11-2000 SJH	Added private NAND flash structure for driver
- *   10-24-2000 SJH	Added prototype for 'nand_scan' function
- *   10-29-2001 TG	changed nand_chip structure to support
- *			hardwarespecific function for accessing control lines
- *   02-21-2002 TG	added support for different read/write adress and
- *			ready/busy line access function
- *   02-26-2002 TG	added chip_delay to nand_chip structure to optimize
- *			command delay times for different chips
- *   04-28-2002 TG	OOB config defines moved from nand.c to avoid duplicate
- *			defines in jffs2/wbuf.c
- *   08-07-2002 TG	forced bad block location to byte 5 of OOB, even if
- *			CONFIG_MTD_NAND_ECC_JFFS2 is not set
- *   08-10-2002 TG	extensions to nand_chip structure to support HW-ECC
- *
- *   08-29-2002 tglx	nand_chip structure: data_poi for selecting
- *			internal / fs-driver buffer
- *			support for 6byte/512byte hardware ECC
- *			read_ecc, write_ecc extended for different oob-layout
- *			oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
- *			NAND_YAFFS_OOB
- *  11-25-2002 tglx	Added Manufacturer code FUJITSU, NATIONAL
- *			Split manufacturer and device ID structures
- *
- *  02-08-2004 tglx	added option field to nand structure for chip anomalities
- *  05-25-2004 tglx	added bad block table support, ST-MICRO manufacturer id
- *			update of nand_chip structure description
+ * Changelog:
+ *	See git changelog.
  */
 #ifndef __LINUX_MTD_NAND_H
 #define __LINUX_MTD_NAND_H
 
-#include <linux/mtd/compat.h>
-#include <linux/mtd/mtd.h>
+#include "config.h"
+
+#include "linux/compat.h"
+#include "linux/mtd/mtd.h"
+#include "linux/mtd/bbm.h"
+
 
 struct mtd_info;
+struct nand_flash_dev;
 /* Scan and identify a NAND device */
 extern int nand_scan (struct mtd_info *mtd, int max_chips);
+/* Separate phases of nand_scan(), allowing board driver to intervene
+ * and override command or ECC setup according to flash type */
+extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
+			   const struct nand_flash_dev *table);
+extern int nand_scan_tail(struct mtd_info *mtd);
+
 /* Free resources held by the NAND device */
-extern void nand_release (struct mtd_info *mtd);
+extern void nand_release(struct mtd_info *mtd);
 
-/* Read raw data from the device without ECC */
-extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen);
+/* Internal helper for board drivers which need to override command function */
+extern void nand_wait_ready(struct mtd_info *mtd);
 
-
-/* This constant declares the max. oobsize / page, which
+/*
+ * This constant declares the max. oobsize / page, which
  * is supported now. If you add a chip with bigger oobsize/page
  * adjust this accordingly.
  */
-#define NAND_MAX_OOBSIZE	64
+#define NAND_MAX_OOBSIZE	576
+#define NAND_MAX_PAGESIZE	8192
 
 /*
  * Constants for hardware specific CLE/ALE/NCE function
-*/
+ *
+ * These are bits which can be or'ed to set/clear multiple
+ * bits in one go.
+ */
 /* Select the chip by setting nCE to low */
-#define NAND_CTL_SETNCE		1
-/* Deselect the chip by setting nCE to high */
-#define NAND_CTL_CLRNCE		2
+#define NAND_NCE		0x01
 /* Select the command latch by setting CLE to high */
-#define NAND_CTL_SETCLE		3
-/* Deselect the command latch by setting CLE to low */
-#define NAND_CTL_CLRCLE		4
+#define NAND_CLE		0x02
 /* Select the address latch by setting ALE to high */
-#define NAND_CTL_SETALE		5
-/* Deselect the address latch by setting ALE to low */
-#define NAND_CTL_CLRALE		6
-/* Set write protection by setting WP to high. Not used! */
-#define NAND_CTL_SETWP		7
-/* Clear write protection by setting WP to low. Not used! */
-#define NAND_CTL_CLRWP		8
+#define NAND_ALE		0x04
+
+#define NAND_CTRL_CLE		(NAND_NCE | NAND_CLE)
+#define NAND_CTRL_ALE		(NAND_NCE | NAND_ALE)
+#define NAND_CTRL_CHANGE	0x80
 
 /*
  * Standard NAND flash commands
  */
 #define NAND_CMD_READ0		0
 #define NAND_CMD_READ1		1
+#define NAND_CMD_RNDOUT		5
 #define NAND_CMD_PAGEPROG	0x10
 #define NAND_CMD_READOOB	0x50
 #define NAND_CMD_ERASE1		0x60
 #define NAND_CMD_STATUS		0x70
 #define NAND_CMD_STATUS_MULTI	0x71
 #define NAND_CMD_SEQIN		0x80
+#define NAND_CMD_RNDIN		0x85
 #define NAND_CMD_READID		0x90
 #define NAND_CMD_ERASE2		0xd0
+#define NAND_CMD_PARAM		0xec
 #define NAND_CMD_RESET		0xff
 
+#define NAND_CMD_LOCK		0x2a
+#define NAND_CMD_UNLOCK1	0x23
+#define NAND_CMD_UNLOCK2	0x24
+
 /* Extended commands for large page devices */
 #define NAND_CMD_READSTART	0x30
+#define NAND_CMD_RNDOUTSTART	0xE0
 #define NAND_CMD_CACHEDPROG	0x15
 
+/* Extended commands for AG-AND device */
+/*
+ * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
+ *       there is no way to distinguish that from NAND_CMD_READ0
+ *       until the remaining sequence of commands has been completed
+ *       so add a high order bit and mask it off in the command.
+ */
+#define NAND_CMD_DEPLETE1	0x100
+#define NAND_CMD_DEPLETE2	0x38
+#define NAND_CMD_STATUS_MULTI	0x71
+#define NAND_CMD_STATUS_ERROR	0x72
+/* multi-bank error status (banks 0-3) */
+#define NAND_CMD_STATUS_ERROR0	0x73
+#define NAND_CMD_STATUS_ERROR1	0x74
+#define NAND_CMD_STATUS_ERROR2	0x75
+#define NAND_CMD_STATUS_ERROR3	0x76
+#define NAND_CMD_STATUS_RESET	0x7f
+#define NAND_CMD_STATUS_CLEAR	0xff
+
+#define NAND_CMD_NONE		-1
+
 /* Status bits */
 #define NAND_STATUS_FAIL	0x01
 #define NAND_STATUS_FAIL_N1	0x02
@@ -120,25 +124,18 @@
 /*
  * Constants for ECC_MODES
  */
-
-/* No ECC. Usage is not recommended ! */
-#define NAND_ECC_NONE		0
-/* Software ECC 3 byte ECC per 256 Byte data */
-#define NAND_ECC_SOFT		1
-/* Hardware ECC 3 byte ECC per 256 Byte data */
-#define NAND_ECC_HW3_256	2
-/* Hardware ECC 3 byte ECC per 512 Byte data */
-#define NAND_ECC_HW3_512	3
-/* Hardware ECC 3 byte ECC per 512 Byte data */
-#define NAND_ECC_HW6_512	4
-/* Hardware ECC 8 byte ECC per 512 Byte data */
-#define NAND_ECC_HW8_512	6
-/* Hardware ECC 12 byte ECC per 2048 Byte data */
-#define NAND_ECC_HW12_2048	7
+typedef enum {
+	NAND_ECC_NONE,
+	NAND_ECC_SOFT,
+	NAND_ECC_HW,
+	NAND_ECC_HW_SYNDROME,
+	NAND_ECC_HW_OOB_FIRST,
+	NAND_ECC_SOFT_BCH,
+} nand_ecc_modes_t;
 
 /*
  * Constants for Hardware ECC
-*/
+ */
 /* Reset Hardware ECC for read */
 #define NAND_ECC_READ		0
 /* Reset Hardware ECC for write */
@@ -146,9 +143,14 @@
 /* Enable Hardware ECC before syndrom is read back from flash */
 #define NAND_ECC_READSYN	2
 
-/* Option constants for bizarre disfunctionality and real
-*  features
-*/
+/* Bit mask for flags passed to do_nand_read_ecc */
+#define NAND_GET_DEVICE		0x80
+
+
+/*
+ * Option constants for bizarre disfunctionality and real
+ * features.
+ */
 /* Chip can not auto increment pages */
 #define NAND_NO_AUTOINCR	0x00000001
 /* Buswitdh is 16 bit */
@@ -159,12 +161,36 @@
 #define NAND_CACHEPRG		0x00000008
 /* Chip has copy back function */
 #define NAND_COPYBACK		0x00000010
-/* AND Chip which has 4 banks and a confusing page / block
- * assignment. See Renesas datasheet for further information */
+/*
+ * AND Chip which has 4 banks and a confusing page / block
+ * assignment. See Renesas datasheet for further information.
+ */
 #define NAND_IS_AND		0x00000020
-/* Chip has a array of 4 pages which can be read without
- * additional ready /busy waits */
+/*
+ * Chip has a array of 4 pages which can be read without
+ * additional ready /busy waits.
+ */
 #define NAND_4PAGE_ARRAY	0x00000040
+/*
+ * Chip requires that BBT is periodically rewritten to prevent
+ * bits from adjacent blocks from 'leaking' in altering data.
+ * This happens with the Renesas AG-AND chips, possibly others.
+ */
+#define BBT_AUTO_REFRESH	0x00000080
+/*
+ * Chip does not require ready check on read. True
+ * for all large page devices, as they do not support
+ * autoincrement.
+ */
+#define NAND_NO_READRDY		0x00000100
+/* Chip does not allow subpage writes */
+#define NAND_NO_SUBPAGE_WRITE	0x00000200
+
+/* Device is one of 'new' xD cards that expose fake nand command set */
+#define NAND_BROKEN_XD		0x00000400
+
+/* Device behaves just like nand, but is readonly */
+#define NAND_ROM		0x00000800
 
 /* Options valid for Samsung large page devices */
 #define NAND_SAMSUNG_LP_OPTIONS \
@@ -175,168 +201,347 @@
 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
+/* Large page NAND with SOFT_ECC should support subpage reads */
+#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
+					&& (chip->page_shift > 9))
 
 /* Mask to zero out the chip options, which come from the id table */
 #define NAND_CHIPOPTIONS_MSK	(0x0000ffff & ~NAND_NO_AUTOINCR)
 
 /* Non chip related options */
-/* Use a flash based bad block table. This option is passed to the
- * default bad block table function. */
+/*
+ * Use a flash based bad block table. OOB identifier is saved in OOB area.
+ * This option is passed to the default bad block table function.
+ */
 #define NAND_USE_FLASH_BBT	0x00010000
-/* The hw ecc generator provides a syndrome instead a ecc value on read
- * This can only work if we have the ecc bytes directly behind the
- * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
-#define NAND_HWECC_SYNDROME	0x00020000
-
+/* This option skips the bbt scan during initialization. */
+#define NAND_SKIP_BBTSCAN	0x00020000
+/*
+ * This option is defined if the board driver allocates its own buffers
+ * (e.g. because it needs them DMA-coherent).
+ */
+#define NAND_OWN_BUFFERS	0x00040000
+/* Chip may not exist, so silence any errors in scan */
+#define NAND_SCAN_SILENT_NODEV	0x00080000
+/*
+ * If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch
+ * the OOB area.
+ */
+#define NAND_USE_FLASH_BBT_NO_OOB	0x00800000
+/* Create an empty BBT with no vendor information if the BBT is available */
+#define NAND_CREATE_EMPTY_BBT		0x01000000
 
 /* Options set by nand scan */
-/* Nand scan has allocated oob_buf */
-#define NAND_OOBBUF_ALLOC	0x40000000
-/* Nand scan has allocated data_buf */
-#define NAND_DATABUF_ALLOC	0x80000000
+/* bbt has already been read */
+#define NAND_BBT_SCANNED	0x40000000
+/* Nand scan has allocated controller struct */
+#define NAND_CONTROLLER_ALLOC	0x80000000
 
-
-/*
- * nand_state_t - chip states
- * Enumeration for NAND flash chip state
- */
-typedef enum {
-	FL_READY,
-	FL_READING,
-	FL_WRITING,
-	FL_ERASING,
-	FL_SYNCING,
-	FL_CACHEDPRG,
-} nand_state_t;
+/* Cell info constants */
+#define NAND_CI_CHIPNR_MSK	0x03
+#define NAND_CI_CELLTYPE_MSK	0x0C
 
 /* Keep gcc happy */
 struct nand_chip;
 
-#if 0
+struct nand_onfi_params {
+	/* rev info and features block */
+	/* 'O' 'N' 'F' 'I'  */
+	u8 sig[4];
+	__le16 revision;
+	__le16 features;
+	__le16 opt_cmd;
+	u8 reserved[22];
+
+	/* manufacturer information block */
+	char manufacturer[12];
+	char model[20];
+	u8 jedec_id;
+	__le16 date_code;
+	u8 reserved2[13];
+
+	/* memory organization block */
+	__le32 byte_per_page;
+	__le16 spare_bytes_per_page;
+	__le32 data_bytes_per_ppage;
+	__le16 spare_bytes_per_ppage;
+	__le32 pages_per_block;
+	__le32 blocks_per_lun;
+	u8 lun_count;
+	u8 addr_cycles;
+	u8 bits_per_cell;
+	__le16 bb_per_lun;
+	__le16 block_endurance;
+	u8 guaranteed_good_blocks;
+	__le16 guaranteed_block_endurance;
+	u8 programs_per_page;
+	u8 ppage_attr;
+	u8 ecc_bits;
+	u8 interleaved_bits;
+	u8 interleaved_ops;
+	u8 reserved3[13];
+
+	/* electrical parameter block */
+	u8 io_pin_capacitance_max;
+	__le16 async_timing_mode;
+	__le16 program_cache_timing_mode;
+	__le16 t_prog;
+	__le16 t_bers;
+	__le16 t_r;
+	__le16 t_ccs;
+	__le16 src_sync_timing_mode;
+	__le16 src_ssync_features;
+	__le16 clk_pin_capacitance_typ;
+	__le16 io_pin_capacitance_typ;
+	__le16 input_pin_capacitance_typ;
+	u8 input_pin_capacitance_max;
+	u8 driver_strenght_support;
+	__le16 t_int_r;
+	__le16 t_ald;
+	u8 reserved4[7];
+
+	/* vendor */
+	u8 reserved5[90];
+
+	__le16 crc;
+} __attribute__((packed));
+
+#define ONFI_CRC_BASE	0x4F4E
+
 /**
- * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
- * @lock:		protection lock
+ * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
+ * @lock:               protection lock
  * @active:		the mtd device which holds the controller currently
+ * @wq:			wait queue to sleep on if a NAND operation is in
+ *			progress used instead of the per chip wait queue
+ *			when a hw controller is available.
  */
 struct nand_hw_control {
+/* XXX U-BOOT XXX */
+#if 0
 	spinlock_t	 lock;
+	wait_queue_head_t wq;
+#endif
 	struct nand_chip *active;
 };
-#endif
+
+/**
+ * struct nand_ecc_ctrl - Control structure for ecc
+ * @mode:	ecc mode
+ * @steps:	number of ecc steps per page
+ * @size:	data bytes per ecc step
+ * @bytes:	ecc bytes per step
+ * @total:	total number of ecc bytes per page
+ * @prepad:	padding information for syndrome based ecc generators
+ * @postpad:	padding information for syndrome based ecc generators
+ * @layout:	ECC layout control struct pointer
+ * @priv:	pointer to private ecc control data
+ * @hwctl:	function to control hardware ecc generator. Must only
+ *		be provided if an hardware ECC is available
+ * @calculate:	function for ecc calculation or readback from ecc hardware
+ * @correct:	function for ecc correction, matching to ecc generator (sw/hw)
+ * @read_page_raw:	function to read a raw page without ECC
+ * @write_page_raw:	function to write a raw page without ECC
+ * @read_page:	function to read a page according to the ecc generator
+ *		requirements.
+ * @read_subpage:	function to read parts of the page covered by ECC.
+ * @write_page:	function to write a page according to the ecc generator
+ *		requirements.
+ * @read_oob:	function to read chip OOB data
+ * @write_oob:	function to write chip OOB data
+ */
+struct nand_ecc_ctrl {
+	nand_ecc_modes_t mode;
+	int steps;
+	int size;
+	int bytes;
+	int total;
+	int prepad;
+	int postpad;
+	struct nand_ecclayout	*layout;
+	void *priv;
+	void (*hwctl)(struct mtd_info *mtd, int mode);
+	int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
+			uint8_t *ecc_code);
+	int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
+			uint8_t *calc_ecc);
+	int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			uint8_t *buf, int page);
+	void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			const uint8_t *buf);
+	int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
+			uint8_t *buf, int page);
+	int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
+			uint32_t offs, uint32_t len, uint8_t *buf);
+	void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+			const uint8_t *buf);
+	int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page,
+			int sndcmd);
+	int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
+			int page);
+};
+
+/**
+ * struct nand_buffers - buffer structure for read/write
+ * @ecccalc:	buffer for calculated ecc
+ * @ecccode:	buffer for ecc read from flash
+ * @databuf:	buffer for data - dynamically sized
+ *
+ * Do not change the order of buffers. databuf and oobrbuf must be in
+ * consecutive order.
+ */
+struct nand_buffers {
+	uint8_t	ecccalc[NAND_MAX_OOBSIZE];
+	uint8_t	ecccode[NAND_MAX_OOBSIZE];
+	uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
+};
 
 /**
  * struct nand_chip - NAND Private Flash Chip Data
- * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
- * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
+ * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the
+ *			flash device
+ * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the
+ *			flash device.
  * @read_byte:		[REPLACEABLE] read one byte from the chip
- * @write_byte:		[REPLACEABLE] write one byte to the chip
  * @read_word:		[REPLACEABLE] read one word from the chip
- * @write_word:		[REPLACEABLE] write one word to the chip
  * @write_buf:		[REPLACEABLE] write data from the buffer to the chip
  * @read_buf:		[REPLACEABLE] read data from the chip into the buffer
- * @verify_buf:		[REPLACEABLE] verify buffer contents against the chip data
+ * @verify_buf:		[REPLACEABLE] verify buffer contents against the chip
+ *			data.
  * @select_chip:	[REPLACEABLE] select chip nr
  * @block_bad:		[REPLACEABLE] check, if the block is bad
  * @block_markbad:	[REPLACEABLE] mark the block bad
- * @hwcontrol:		[BOARDSPECIFIC] hardwarespecific function for accesing control-lines
- * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
- *			If set to NULL no access to ready/busy is available and the ready/busy information
- *			is read from the chip status register
- * @cmdfunc:		[REPLACEABLE] hardwarespecific function for writing commands to the chip
- * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on ready
- * @calculate_ecc:	[REPLACEABLE] function for ecc calculation or readback from ecc hardware
- * @correct_data:	[REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
- * @enable_hwecc:	[BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
- *			be provided if a hardware ECC is available
- * @erase_cmd:		[INTERN] erase command write function, selectable due to AND support
+ * @cmd_ctrl:		[BOARDSPECIFIC] hardwarespecific function for controlling
+ *			ALE/CLE/nCE. Also used to write command and address
+ * @init_size:		[BOARDSPECIFIC] hardwarespecific function for setting
+ *			mtd->oobsize, mtd->writesize and so on.
+ *			@id_data contains the 8 bytes values of NAND_CMD_READID.
+ *			Return with the bus width.
+ * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accesing
+ *			device ready/busy line. If set to NULL no access to
+ *			ready/busy is available and the ready/busy information
+ *			is read from the chip status register.
+ * @cmdfunc:		[REPLACEABLE] hardwarespecific function for writing
+ *			commands to the chip.
+ * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on
+ *			ready.
+ * @ecc:		[BOARDSPECIFIC] ecc control ctructure
+ * @buffers:		buffer structure for read/write
+ * @hwcontrol:		platform-specific hardware control structure
+ * @ops:		oob operation operands
+ * @erase_cmd:		[INTERN] erase command write function, selectable due
+ *			to AND support.
  * @scan_bbt:		[REPLACEABLE] function to scan bad block table
- * @eccmode:		[BOARDSPECIFIC] mode of ecc, see defines
- * @eccsize:		[INTERN] databytes used per ecc-calculation
- * @eccbytes:		[INTERN] number of ecc bytes per ecc-calculation step
- * @eccsteps:		[INTERN] number of ecc calculation steps per page
- * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
- * @chip_lock:		[INTERN] spinlock used to protect access to this structure and the chip
- * @wq:			[INTERN] wait queue to sleep on if a NAND operation is in progress
+ * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transferring
+ *			data from array to read regs (tR).
  * @state:		[INTERN] the current state of the NAND device
- * @page_shift:		[INTERN] number of address bits in a page (column address bits)
+ * @oob_poi:		poison value buffer
+ * @page_shift:		[INTERN] number of address bits in a page (column
+ *			address bits).
  * @phys_erase_shift:	[INTERN] number of address bits in a physical eraseblock
  * @bbt_erase_shift:	[INTERN] number of address bits in a bbt entry
  * @chip_shift:		[INTERN] number of address bits in one chip
- * @data_buf:		[INTERN] internal buffer for one page + oob
- * @oob_buf:		[INTERN] oob buffer for one eraseblock
- * @oobdirty:		[INTERN] indicates that oob_buf must be reinitialized
- * @data_poi:		[INTERN] pointer to a data buffer
- * @options:		[BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
- *			special functionality. See the defines for further explanation
- * @badblockpos:	[INTERN] position of the bad block marker in the oob area
+ * @options:		[BOARDSPECIFIC] various chip options. They can partly
+ *			be set to inform nand_scan about special functionality.
+ *			See the defines for further explanation.
+ * @badblockpos:	[INTERN] position of the bad block marker in the oob
+ *			area.
+ * @badblockbits:	[INTERN] number of bits to left-shift the bad block
+ *			number
+ * @cellinfo:		[INTERN] MLC/multichip data from chip ident
  * @numchips:		[INTERN] number of physical chips
  * @chipsize:		[INTERN] the size of one chip for multichip arrays
  * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
- * @pagebuf:		[INTERN] holds the pagenumber which is currently in data_buf
- * @autooob:		[REPLACEABLE] the default (auto)placement scheme
+ * @pagebuf:		[INTERN] holds the pagenumber which is currently in
+ *			data_buf.
+ * @subpagesize:	[INTERN] holds the subpagesize
+ * @onfi_version:	[INTERN] holds the chip ONFI version (BCD encoded),
+ *			non 0 if ONFI supported.
+ * @onfi_params:	[INTERN] holds the ONFI page parameter when ONFI is
+ *			supported, 0 otherwise.
+ * @ecclayout:		[REPLACEABLE] the default ecc placement scheme
  * @bbt:		[INTERN] bad block table pointer
- * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash lookup
+ * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
+ *			lookup.
  * @bbt_md:		[REPLACEABLE] bad block table mirror descriptor
- * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for initial bad block scan
- * @controller:		[OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices
+ * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for initial
+ *			bad block scan.
+ * @controller:		[REPLACEABLE] a pointer to a hardware controller
+ *			structure which is shared among multiple independend
+ *			devices.
  * @priv:		[OPTIONAL] pointer to private chip date
+ * @errstat:		[OPTIONAL] hardware specific function to perform
+ *			additional error status checks (determine if errors are
+ *			correctable).
+ * @write_page:		[REPLACEABLE] High-level page write function
  */
 
 struct nand_chip {
-	void  __iomem	*IO_ADDR_R;
-	void  __iomem	*IO_ADDR_W;
+	void __iomem *IO_ADDR_R;
+	void __iomem *IO_ADDR_W;
 
-	u_char		(*read_byte)(struct mtd_info *mtd);
-	void		(*write_byte)(struct mtd_info *mtd, u_char byte);
-	u16		(*read_word)(struct mtd_info *mtd);
-	void		(*write_word)(struct mtd_info *mtd, u16 word);
+	uint8_t (*read_byte)(struct mtd_info *mtd);
+	u16 (*read_word)(struct mtd_info *mtd);
+	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
+	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
+	int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
+	void (*select_chip)(struct mtd_info *mtd, int chip);
+	int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
+	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
+	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
+	int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
+			u8 *id_data);
+	int (*dev_ready)(struct mtd_info *mtd);
+	void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
+			int page_addr);
+	int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
+	void (*erase_cmd)(struct mtd_info *mtd, int page);
+	int (*scan_bbt)(struct mtd_info *mtd);
+	int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
+			int status, int page);
+	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+			const uint8_t *buf, int page, int cached, int raw);
 
-	void		(*write_buf)(struct mtd_info *mtd, const u_char *buf, int len);
-	void		(*read_buf)(struct mtd_info *mtd, u_char *buf, int len);
-	int		(*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len);
-	void		(*select_chip)(struct mtd_info *mtd, int chip);
-	int		(*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
-	int		(*block_markbad)(struct mtd_info *mtd, loff_t ofs);
-	void		(*hwcontrol)(struct mtd_info *mtd, int cmd);
-	int		(*dev_ready)(struct mtd_info *mtd);
-	void		(*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
-	int		(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
-	int		(*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
-	int		(*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
-	void		(*enable_hwecc)(struct mtd_info *mtd, int mode);
-	void		(*erase_cmd)(struct mtd_info *mtd, int page);
-	int		(*scan_bbt)(struct mtd_info *mtd);
-	int		eccmode;
-	int		eccsize;
-	int		eccbytes;
-	int		eccsteps;
-	int		chip_delay;
-#if 0
-	spinlock_t	chip_lock;
-	wait_queue_head_t wq;
-	nand_state_t	state;
+	int chip_delay;
+	unsigned int options;
+
+	int page_shift;
+	int phys_erase_shift;
+	int bbt_erase_shift;
+	int chip_shift;
+	int numchips;
+	uint64_t chipsize;
+	int pagemask;
+	int pagebuf;
+	int subpagesize;
+	uint8_t cellinfo;
+	int badblockpos;
+	int badblockbits;
+
+	int onfi_version;
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+	struct nand_onfi_params onfi_params;
 #endif
-	int		page_shift;
-	int		phys_erase_shift;
-	int		bbt_erase_shift;
-	int		chip_shift;
-	u_char		*data_buf;
-	u_char		*oob_buf;
-	int		oobdirty;
-	u_char		*data_poi;
-	unsigned int	options;
-	int		badblockpos;
-	int		numchips;
-	unsigned long	chipsize;
-	int		pagemask;
-	int		pagebuf;
-	struct nand_oobinfo	*autooob;
-	uint8_t		*bbt;
-	struct nand_bbt_descr	*bbt_td;
-	struct nand_bbt_descr	*bbt_md;
-	struct nand_bbt_descr	*badblock_pattern;
-	struct nand_hw_control	*controller;
-	void		*priv;
+
+	int state;
+
+	uint8_t *oob_poi;
+	struct nand_hw_control *controller;
+	struct nand_ecclayout *ecclayout;
+
+	struct nand_ecc_ctrl ecc;
+	struct nand_buffers *buffers;
+	struct nand_hw_control hwcontrol;
+
+	struct mtd_oob_ops ops;
+
+	uint8_t *bbt;
+	struct nand_bbt_descr *bbt_td;
+	struct nand_bbt_descr *bbt_md;
+
+	struct nand_bbt_descr *badblock_pattern;
+
+	void *priv;
 };
 
 /*
@@ -348,10 +553,12 @@
 #define NAND_MFR_NATIONAL	0x8f
 #define NAND_MFR_RENESAS	0x07
 #define NAND_MFR_STMICRO	0x20
+#define NAND_MFR_HYNIX		0xad
+#define NAND_MFR_MICRON		0x2c
+#define NAND_MFR_AMD		0x01
 
 /**
  * struct nand_flash_dev - NAND Flash Device ID Structure
- *
  * @name:	Identify the device type
  * @id:		device ID code
  * @pagesize:	Pagesize in bytes. Either 256 or 512 or 0
@@ -378,86 +585,20 @@
 */
 struct nand_manufacturers {
 	int id;
-	char * name;
+	char *name;
 };
 
-extern struct nand_flash_dev nand_flash_ids[];
-extern struct nand_manufacturers nand_manuf_ids[];
+extern const struct nand_flash_dev nand_flash_ids[];
+extern const struct nand_manufacturers nand_manuf_ids[];
 
-/**
- * struct nand_bbt_descr - bad block table descriptor
- * @options:	options for this descriptor
- * @pages:	the page(s) where we find the bbt, used with option BBT_ABSPAGE
- *		when bbt is searched, then we store the found bbts pages here.
- *		Its an array and supports up to 8 chips now
- * @offs:	offset of the pattern in the oob area of the page
- * @veroffs:	offset of the bbt version counter in the oob are of the page
- * @version:	version read from the bbt page during scan
- * @len:	length of the pattern, if 0 no pattern check is performed
- * @maxblocks:	maximum number of blocks to search for a bbt. This number of
- *		blocks is reserved at the end of the device where the tables are
- *		written.
- * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
- *		bad) block in the stored bbt
- * @pattern:	pattern to identify bad block table or factory marked good /
- *		bad blocks, can be NULL, if len = 0
- *
- * Descriptor for the bad block table marker and the descriptor for the
- * pattern which identifies good and bad blocks. The assumption is made
- * that the pattern and the version count are always located in the oob area
- * of the first block.
- */
-struct nand_bbt_descr {
-	int	options;
-	int	pages[NAND_MAX_CHIPS];
-	int	offs;
-	int	veroffs;
-	uint8_t version[NAND_MAX_CHIPS];
-	int	len;
-	int	maxblocks;
-	int	reserved_block_code;
-	uint8_t *pattern;
-};
-
-/* Options for the bad block table descriptors */
-
-/* The number of bits used per block in the bbt on the device */
-#define NAND_BBT_NRBITS_MSK	0x0000000F
-#define NAND_BBT_1BIT		0x00000001
-#define NAND_BBT_2BIT		0x00000002
-#define NAND_BBT_4BIT		0x00000004
-#define NAND_BBT_8BIT		0x00000008
-/* The bad block table is in the last good block of the device */
-#define NAND_BBT_LASTBLOCK	0x00000010
-/* The bbt is at the given page, else we must scan for the bbt */
-#define NAND_BBT_ABSPAGE	0x00000020
-/* The bbt is at the given page, else we must scan for the bbt */
-#define NAND_BBT_SEARCH		0x00000040
-/* bbt is stored per chip on multichip devices */
-#define NAND_BBT_PERCHIP	0x00000080
-/* bbt has a version counter at offset veroffs */
-#define NAND_BBT_VERSION	0x00000100
-/* Create a bbt if none axists */
-#define NAND_BBT_CREATE		0x00000200
-/* Search good / bad pattern through all pages of a block */
-#define NAND_BBT_SCANALLPAGES	0x00000400
-/* Scan block empty during good / bad block scan */
-#define NAND_BBT_SCANEMPTY	0x00000800
-/* Write bbt if neccecary */
-#define NAND_BBT_WRITE		0x00001000
-/* Read and write back block contents when writing bbt */
-#define NAND_BBT_SAVECONTENT	0x00002000
-/* Search good / bad pattern on the first and the second page */
-#define NAND_BBT_SCAN2NDPAGE	0x00004000
-
-/* The maximum number of blocks to scan for a bbt */
-#define NAND_BBT_SCAN_MAXBLOCKS 4
-
-extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
-extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
-extern int nand_default_bbt (struct mtd_info *mtd);
-extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt);
-extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
+extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
+extern int nand_default_bbt(struct mtd_info *mtd);
+extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
+extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
+			   int allowbbt);
+extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
+			size_t *retlen, uint8_t *buf);
 
 /*
 * Constants for oob configuration
@@ -465,4 +606,76 @@
 #define NAND_SMALL_BADBLOCK_POS		5
 #define NAND_LARGE_BADBLOCK_POS		0
 
+/**
+ * struct platform_nand_chip - chip level device structure
+ * @nr_chips:		max. number of chips to scan for
+ * @chip_offset:	chip number offset
+ * @nr_partitions:	number of partitions pointed to by partitions (or zero)
+ * @partitions:		mtd partition list
+ * @chip_delay:		R/B delay value in us
+ * @options:		Option flags, e.g. 16bit buswidth
+ * @ecclayout:		ecc layout info structure
+ * @part_probe_types:	NULL-terminated array of probe types
+ * @priv:		hardware controller specific settings
+ */
+struct platform_nand_chip {
+	int nr_chips;
+	int chip_offset;
+	int nr_partitions;
+	struct mtd_partition *partitions;
+	struct nand_ecclayout *ecclayout;
+	int chip_delay;
+	unsigned int options;
+	const char **part_probe_types;
+	void *priv;
+};
+
+/* Keep gcc happy */
+struct platform_device;
+
+/**
+ * struct platform_nand_ctrl - controller level device structure
+ * @hwcontrol:		platform specific hardware control structure
+ * @dev_ready:		platform specific function to read ready/busy pin
+ * @select_chip:	platform specific chip select function
+ * @cmd_ctrl:		platform specific function for controlling
+ *			ALE/CLE/nCE. Also used to write command and address
+ * @priv:		private data to transport driver specific settings
+ *
+ * All fields are optional and depend on the hardware driver requirements
+ */
+struct platform_nand_ctrl {
+	void (*hwcontrol)(struct mtd_info *mtd, int cmd);
+	int (*dev_ready)(struct mtd_info *mtd);
+	void (*select_chip)(struct mtd_info *mtd, int chip);
+	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
+	void *priv;
+};
+
+/**
+ * struct platform_nand_data - container structure for platform-specific data
+ * @chip:		chip level chip structure
+ * @ctrl:		controller level device structure
+ */
+struct platform_nand_data {
+	struct platform_nand_chip chip;
+	struct platform_nand_ctrl ctrl;
+};
+
+/* Some helpers to access the data structures */
+static inline
+struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+
+	return chip->priv;
+}
+
+/* Standard NAND functions from nand_base.c */
+void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
+void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
+void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
+void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
+uint8_t nand_read_byte(struct mtd_info *mtd);
+
 #endif /* __LINUX_MTD_NAND_H */

include/linux/mtd/nand_bch.h

diff --git a/include/linux/mtd/nand_bch.h b/include/linux/mtd/nand_bch.h
new file mode 100644
index 0000000..c0f2247
--- /dev/null
+++ b/include/linux/mtd/nand_bch.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright © 2011 Ivan Djelic <ivan.djelic@parrot.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file is the header for the NAND BCH ECC implementation.
+ */
+
+#ifndef __MTD_NAND_BCH_H__
+#define __MTD_NAND_BCH_H__
+
+struct mtd_info;
+struct nand_bch_control;
+#define CONFIG_NAND_ECC_BCH
+
+#if defined(CONFIG_NAND_ECC_BCH)
+
+static inline int mtd_nand_has_bch(void) { return 1; }
+
+/*
+ * Calculate BCH ecc code
+ */
+int nand_bch_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+			   u_char *ecc_code);
+
+/*
+ * Detect and correct bit errors
+ */
+int nand_bch_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc,
+			  u_char *calc_ecc);
+/*
+ * Initialize BCH encoder/decoder
+ */
+struct nand_bch_control *
+nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
+	      unsigned int eccbytes, struct nand_ecclayout **ecclayout);
+/*
+ * Release BCH encoder/decoder resources
+ */
+void nand_bch_free(struct nand_bch_control *nbc);
+
+#else /* !CONFIG_NAND_ECC_BCH */
+
+static inline int mtd_nand_has_bch(void) { return 0; }
+
+static inline int
+nand_bch_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+		       u_char *ecc_code)
+{
+	return -1;
+}
+
+static inline int
+nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
+		      unsigned char *read_ecc, unsigned char *calc_ecc)
+{
+	return -1;
+}
+
+static inline struct nand_bch_control *
+nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
+	      unsigned int eccbytes, struct nand_ecclayout **ecclayout)
+{
+	return NULL;
+}
+
+static inline void nand_bch_free(struct nand_bch_control *nbc) {}
+
+#endif /* CONFIG_NAND_ECC_BCH */
+
+#endif /* __MTD_NAND_BCH_H__ */

include/linux/types.h

diff --git a/include/linux/types.h b/include/linux/types.h
index df4808f..dcdba14 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -119,6 +119,30 @@
  * Below are truly Linux-specific types that should never collide with
  * any application/library that wants linux/types.h.
  */
+#ifdef __CHECKER__
+#define __bitwise__ __attribute__((bitwise))
+#else
+#define __bitwise__
+#endif
+#ifdef __CHECK_ENDIAN__
+#define __bitwise __bitwise__
+#else
+#define __bitwise
+#endif
+
+typedef __u16 __bitwise __le16;
+typedef __u16 __bitwise __be16;
+typedef __u32 __bitwise __le32;
+typedef __u32 __bitwise __be32;
+#if defined(__GNUC__)
+typedef __u64 __bitwise __le64;
+typedef __u64 __bitwise __be64;
+#endif
+typedef __u16 __bitwise __sum16;
+typedef __u32 __bitwise __wsum;
+
+
+typedef unsigned __bitwise__	gfp_t;
 
 struct ustat {
 	__kernel_daddr_t	f_tfree;
@@ -127,4 +151,5 @@
 	char			f_fpack[6];
 };
 
+
 #endif /* _LINUX_TYPES_H */

include/miiphy.h

diff --git a/include/miiphy.h b/include/miiphy.h
index 71716b0..d5ad6ae 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -47,8 +47,16 @@
 int  miiphy_info(char *devname, unsigned char addr, unsigned int  *oui,
 		unsigned char *model, unsigned char *rev);
 int  miiphy_reset(char *devname, unsigned char addr);
+int miiphy_supports_1000base_t (char *devname, unsigned char addr);
+int miiphy_wait_autonegotiation_complete (char *devname, unsigned char addr);
+int miiphy_speed_duplex (char *devname, unsigned char addr, int *speed, int *duplex);
 int  miiphy_speed(char *devname, unsigned char addr);
 int  miiphy_duplex(char *devname, unsigned char addr);
+
+/****** MSPD Change *******/
+void miiphy_enable_rgmii_rx_delay(char *devname, unsigned char addr);
+void miiphy_enable_rgmii_tx_delay(char *devname, unsigned char addr);
+/*************************/
 #ifdef CFG_FAULT_ECHO_LINK_DOWN
 int  miiphy_link(char *devname, unsigned char addr);
 #endif
@@ -75,7 +83,7 @@
 
 /* phy seed setup */
 #define AUTO			99
-#define _1000BASET              1000
+#define _1000BASET		1000
 #define _100BASET		100
 #define _10BASET		10
 #define HALF			22
@@ -90,9 +98,10 @@
 #define PHY_ANLPAR		0x05
 #define PHY_ANER		0x06
 #define PHY_ANNPTR		0x07
-#define PHY_ANLPNP              0x08
-#define PHY_1000BTCR            0x09
-#define PHY_1000BTSR            0x0A
+#define PHY_ANLPNP		0x08
+#define PHY_1000BTCR		0x09
+#define PHY_1000BTSR		0x0A
+#define PHY_EXSR		0x0F
 #define PHY_PHYSTS		0x10
 #define PHY_MIPSCR		0x11
 #define PHY_MIPGSR		0x12
@@ -104,6 +113,11 @@
 #define PHY_10BTSCR		0x18
 #define PHY_PHYCTRL		0x19
 
+/**** MSPD Change *****/
+#define PHY_DEBUG_PORT_ADDRESS          29
+#define PHY_DEBUG_PORT_DATA             30
+
+
 /* PHY BMCR */
 #define PHY_BMCR_RESET		0x8000
 #define PHY_BMCR_LOOP		0x4000
@@ -115,10 +129,10 @@
 #define PHY_BMCR_DPLX		0x0100
 #define PHY_BMCR_COL_TST	0x0080
 
-#define PHY_BMCR_SPEED_MASK     0x2040
-#define PHY_BMCR_1000_MBPS      0x0040
-#define PHY_BMCR_100_MBPS       0x2000
-#define PHY_BMCR_10_MBPS        0x0000
+#define PHY_BMCR_SPEED_MASK	0x2040
+#define PHY_BMCR_1000_MBPS	0x0040
+#define PHY_BMCR_100_MBPS	0x2000
+#define PHY_BMCR_10_MBPS	0x0000
 
 /* phy BMSR */
 #define PHY_BMSR_100T4		0x8000
@@ -126,6 +140,7 @@
 #define PHY_BMSR_100TXH		0x2000
 #define PHY_BMSR_10TF		0x1000
 #define PHY_BMSR_10TH		0x0800
+#define PHY_BMSR_EXT_STAT	0x0100
 #define PHY_BMSR_PRE_SUP	0x0040
 #define PHY_BMSR_AUTN_COMP	0x0020
 #define PHY_BMSR_RF		0x0010
@@ -134,27 +149,56 @@
 #define PHY_BMSR_JD		0x0002
 #define PHY_BMSR_EXT		0x0001
 
+/*phy ANAR */
+#define PHY_ANAR_NP		0x8000
+#define PHY_ANAR_ACK		0x4000
+#define PHY_ANAR_RF		0x2000
+#define PHY_ANAR_ASYMP		0x0800
+#define PHY_ANAR_PAUSE		0x0400
+#define PHY_ANAR_T4		0x0200
+#define PHY_ANAR_TXFD		0x0100
+#define PHY_ANAR_TX		0x0080
+#define PHY_ANAR_10FD		0x0040
+#define PHY_ANAR_10		0x0020
+#define PHY_ANAR_100		0x0380	/* we can run at 100 */
+
+#define PHY_ANAR_PSB_MASK	0x001f
+#define PHY_ANAR_PSB_802_3	0x0001
+#define PHY_ANAR_PSB_802_9	0x0002
+
 /*phy ANLPAR */
 #define PHY_ANLPAR_NP		0x8000
 #define PHY_ANLPAR_ACK		0x4000
 #define PHY_ANLPAR_RF		0x2000
+#define PHY_ANLPAR_ASYMP	0x0800
+#define PHY_ANLPAR_PAUSE	0x0400
 #define PHY_ANLPAR_T4		0x0200
 #define PHY_ANLPAR_TXFD		0x0100
 #define PHY_ANLPAR_TX		0x0080
 #define PHY_ANLPAR_10FD		0x0040
 #define PHY_ANLPAR_10		0x0020
-#define PHY_ANLPAR_100		0x0380	    /* we can run at 100 */
+#define PHY_ANLPAR_100		0x0380	/* we can run at 100 */
 
-#define PHY_ANLPAR_PSB_MASK     0x001f
-#define PHY_ANLPAR_PSB_802_3    0x0001
-#define PHY_ANLPAR_PSB_802_9    0x0002
+#define PHY_ANLPAR_PSB_MASK	0x001f
+#define PHY_ANLPAR_PSB_802_3	0x0001
+#define PHY_ANLPAR_PSB_802_9	0x0002
 
-/* PHY_1000BTSR */
-#define PHY_1000BTSR_MSCF       0x8000
-#define PHY_1000BTSR_MSCR       0x4000
-#define PHY_1000BTSR_LRS        0x2000
-#define PHY_1000BTSR_RRS        0x1000
-#define PHY_1000BTSR_1000FD     0x0800
-#define PHY_1000BTSR_1000HD     0x0400
+/* phy 1000BTCR */
+#define PHY_1000BTCR_1000FD	0x0200
+#define PHY_1000BTCR_1000HD	0x0100
+
+/* phy 1000BTSR */
+#define PHY_1000BTSR_MSCF	0x8000
+#define PHY_1000BTSR_MSCR	0x4000
+#define PHY_1000BTSR_LRS	0x2000
+#define PHY_1000BTSR_RRS	0x1000
+#define PHY_1000BTSR_1000FD	0x0800
+#define PHY_1000BTSR_1000HD	0x0400
+
+/* phy EXSR */
+#define PHY_EXSR_1000XF		0x8000
+#define PHY_EXSR_1000XH		0x4000
+#define PHY_EXSR_1000TF		0x2000
+#define PHY_EXSR_1000TH		0x1000
 
 #endif

include/nand.h

diff --git a/include/nand.h b/include/nand.h
index 23493f7..5bca4ef 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -24,31 +24,52 @@
 #ifndef _NAND_H_
 #define _NAND_H_
 
-#include <linux/mtd/compat.h>
+#include <config.h>
+
+/*
+ * All boards using a given driver must convert to self-init
+ * at the same time, so do it here.  When all drivers are
+ * converted, this will go away.
+ */
+#if defined(CONFIG_NAND_FSL_ELBC)
+//#define CONFIG_SYS_NAND_SELF_INIT
+#endif
+
+extern void nand_init(void);
+
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 
+#undef CONFIG_SYS_NAND_SELF_INIT
+#ifdef CONFIG_SYS_NAND_SELF_INIT
+void board_nand_init(void);
+int nand_register(int devnum);
+#else
+extern int board_nand_init(struct nand_chip *nand);
+#endif
+
 typedef struct mtd_info nand_info_t;
 
 extern int nand_curr_device;
 extern nand_info_t nand_info[];
 
-static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
+static inline int nand_read(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
 {
 	return info->read(info, ofs, *len, (size_t *)len, buf);
 }
 
-static inline int nand_write(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
+static inline int nand_write(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
 {
 	return info->write(info, ofs, *len, (size_t *)len, buf);
 }
 
-static inline int nand_block_isbad(nand_info_t *info, ulong ofs)
+static inline int nand_block_isbad(nand_info_t *info, loff_t ofs)
 {
 	return info->block_isbad(info, ofs);
 }
 
-static inline int nand_erase(nand_info_t *info, ulong off, ulong size)
+static inline int nand_erase(nand_info_t *info, loff_t off, size_t size)
 {
 	struct erase_info instr;
 
@@ -81,6 +102,7 @@
 };
 
 typedef struct nand_write_options nand_write_options_t;
+typedef struct mtd_oob_ops mtd_oob_ops_t;
 
 struct nand_read_options {
 	u_char *buffer;		/* memory block in which read image is written*/
@@ -93,20 +115,30 @@
 typedef struct nand_read_options nand_read_options_t;
 
 struct nand_erase_options {
-	ulong length;		/* number of bytes to erase */
-	ulong offset;		/* first address in NAND to erase */
+	loff_t length;		/* number of bytes to erase */
+	loff_t offset;		/* first address in NAND to erase */
 	int quiet;		/* don't display progress messages */
 	int jffs2;		/* if true: format for jffs2 usage
 				 * (write appropriate cleanmarker blocks) */
 	int scrub;		/* if true, really clean NAND by erasing
 				 * bad blocks (UNSAFE) */
+
+	/* Don't include skipped bad blocks in size to be erased */
+	int spread;
 };
 
 typedef struct nand_erase_options nand_erase_options_t;
 
-int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts);
+int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
+		       u_char *buffer);
 
-int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts);
+#define WITH_YAFFS_OOB	(1 << 0) /* whether write with yaffs format. This flag
+				  * is a 'mode' meaning it cannot be mixed with
+				  * other flags */
+#define WITH_DROP_FFS	(1 << 1) /* drop trailing all-0xff pages */
+
+int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
+			u_char *buffer, int flags);
 int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
 
 #define NAND_LOCK_STATUS_TIGHT	0x01
@@ -115,10 +147,24 @@
 
 int nand_lock( nand_info_t *meminfo, int tight );
 int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
-int nand_get_lock_status(nand_info_t *meminfo, ulong offset);
+int nand_get_lock_status(nand_info_t *meminfo, loff_t offset);
 
-#ifdef CFG_NAND_SELECT_DEVICE
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
+void nand_deselect(void);
+
+#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
 void board_nand_select_device(struct nand_chip *nand, int chip);
 #endif
 
+__attribute__((noreturn)) void nand_boot(void);
+
+#endif
+
+#ifdef CONFIG_ENV_OFFSET_OOB
+#define ENV_OOB_MARKER 0x30425645 /*"EVB0" in little-endian -- offset is stored
+				    as block number*/
+#define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is
+					stored as byte number */
+#define ENV_OFFSET_SIZE 8
+int get_nand_env_oob(nand_info_t *nand, unsigned long *result);
 #endif

include/types.h

diff --git a/include/types.h b/include/types.h
new file mode 100644
index 0000000..71dc049
--- /dev/null
+++ b/include/types.h
@@ -0,0 +1,53 @@
+#ifndef __ASM_ARM_TYPES_H
+#define __ASM_ARM_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif

lib_arm/Makefile

diff --git a/lib_arm/Makefile b/lib_arm/Makefile
index 037c475..ff103de 100644
--- a/lib_arm/Makefile
+++ b/lib_arm/Makefile
@@ -25,9 +25,10 @@
 
 LIB	= $(obj)lib$(ARCH).a
 
-SOBJS	= _ashldi3.o _ashrdi3.o _divsi3.o _modsi3.o _udivsi3.o _umodsi3.o
+#SOBJS	= _ashldi3.o _ashrdi3.o _divsi3.o _modsi3.o _udivsi3.o _umodsi3.o
+SOBJS	= lib1funcs.o ashldi3.o ashrdi3.o _lshrdi3.o 
 
-COBJS	= armlinux.o board.o \
+COBJS	= interrupts.o armlinux.o board.o \
 	  cache.o div0.o
 
 SRCS 	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)

lib_arm/_divsi3.S

diff --git a/lib_arm/_divsi3.S b/lib_arm/_divsi3.S
deleted file mode 100644
index 9dc15f6..0000000
--- a/lib_arm/_divsi3.S
+++ /dev/null
@@ -1,140 +0,0 @@
-
-.macro ARM_DIV_BODY dividend, divisor, result, curbit
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\curbit, \divisor
-	clz	\result, \dividend
-	sub	\result, \curbit, \result
-	mov	\curbit, #1
-	mov	\divisor, \divisor, lsl \result
-	mov	\curbit, \curbit, lsl \result
-	mov	\result, #0
-
-#else
-
-	@ Initially shift the divisor left 3 bits if possible,
-	@ set curbit accordingly.  This allows for curbit to be located
-	@ at the left end of each 4 bit nibbles in the division loop
-	@ to save one loop in most cases.
-	tst	\divisor, #0xe0000000
-	moveq	\divisor, \divisor, lsl #3
-	moveq	\curbit, #8
-	movne	\curbit, #1
-
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-1:	cmp	\divisor, #0x10000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #4
-	movlo	\curbit, \curbit, lsl #4
-	blo	1b
-
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-1:	cmp	\divisor, #0x80000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #1
-	movlo	\curbit, \curbit, lsl #1
-	blo	1b
-
-	mov	\result, #0
-
-#endif
-
-	@ Division loop
-1:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	orrhs	\result,   \result,   \curbit
-	cmp	\dividend, \divisor,  lsr #1
-	subhs	\dividend, \dividend, \divisor, lsr #1
-	orrhs	\result,   \result,   \curbit,  lsr #1
-	cmp	\dividend, \divisor,  lsr #2
-	subhs	\dividend, \dividend, \divisor, lsr #2
-	orrhs	\result,   \result,   \curbit,  lsr #2
-	cmp	\dividend, \divisor,  lsr #3
-	subhs	\dividend, \dividend, \divisor, lsr #3
-	orrhs	\result,   \result,   \curbit,  lsr #3
-	cmp	\dividend, #0			@ Early termination?
-	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
-	movne	\divisor,  \divisor, lsr #4
-	bne	1b
-
-.endm
-
-.macro ARM_DIV2_ORDER divisor, order
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\order, \divisor
-	rsb	\order, \order, #31
-
-#else
-
-	cmp	\divisor, #(1 << 16)
-	movhs	\divisor, \divisor, lsr #16
-	movhs	\order, #16
-	movlo	\order, #0
-
-	cmp	\divisor, #(1 << 8)
-	movhs	\divisor, \divisor, lsr #8
-	addhs	\order, \order, #8
-
-	cmp	\divisor, #(1 << 4)
-	movhs	\divisor, \divisor, lsr #4
-	addhs	\order, \order, #4
-
-	cmp	\divisor, #(1 << 2)
-	addhi	\order, \order, #3
-	addls	\order, \order, \divisor, lsr #1
-
-#endif
-
-.endm
-
-	.align	5
-.globl __divsi3
-__divsi3:
-	cmp	r1, #0
-	eor	ip, r0, r1			@ save the sign of the result.
-	beq	Ldiv0
-	rsbmi	r1, r1, #0			@ loops below use unsigned.
-	subs	r2, r1, #1			@ division by 1 or -1 ?
-	beq	10f
-	movs	r3, r0
-	rsbmi	r3, r0, #0			@ positive dividend value
-	cmp	r3, r1
-	bls	11f
-	tst	r1, r2				@ divisor is power of 2 ?
-	beq	12f
-
-	ARM_DIV_BODY r3, r1, r0, r2
-
-	cmp	ip, #0
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-10:	teq	ip, r0				@ same sign ?
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-11:	movlo	r0, #0
-	moveq	r0, ip, asr #31
-	orreq	r0, r0, #1
-	mov	pc, lr
-
-12:	ARM_DIV2_ORDER r1, r2
-
-	cmp	ip, #0
-	mov	r0, r3, lsr r2
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-Ldiv0:
-
-	str	lr, [sp, #-4]!
-	bl	__div0
-	mov	r0, #0			@ About as wrong as it could be.
-	ldr	pc, [sp], #4

lib_arm/_lshrdi3.S

diff --git a/lib_arm/_ashrdi3.S b/lib_arm/_lshrdi3.S
similarity index 93%
rename from lib_arm/_ashrdi3.S
rename to lib_arm/_lshrdi3.S
index 5edbcb3..e7fa799 100644
--- a/lib_arm/_ashrdi3.S
+++ b/lib_arm/_lshrdi3.S
@@ -34,13 +34,15 @@
 #define ah r1
 #endif
 
-.globl __ashrdi3
-__ashrdi3:
+.globl __lshrdi3
+.globl __aeabi_llsr
+__lshrdi3:
+__aeabi_llsr:
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
 	movmi	al, al, lsr r2
-	movpl	al, ah, asr r3
+	movpl	al, ah, lsr r3
 	orrmi	al, al, ah, lsl ip
-	mov	ah, ah, asr r2
+	mov	ah, ah, lsr r2
 	mov	pc, lr

lib_arm/_modsi3.S

diff --git a/lib_arm/_modsi3.S b/lib_arm/_modsi3.S
deleted file mode 100644
index 539c584..0000000
--- a/lib_arm/_modsi3.S
+++ /dev/null
@@ -1,99 +0,0 @@
-
-.macro ARM_MOD_BODY dividend, divisor, order, spare
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\order, \divisor
-	clz	\spare, \dividend
-	sub	\order, \order, \spare
-	mov	\divisor, \divisor, lsl \order
-
-#else
-
-	mov	\order, #0
-
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-1:	cmp	\divisor, #0x10000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #4
-	addlo	\order, \order, #4
-	blo	1b
-
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-1:	cmp	\divisor, #0x80000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #1
-	addlo	\order, \order, #1
-	blo	1b
-
-#endif
-
-	@ Perform all needed substractions to keep only the reminder.
-	@ Do comparisons in batch of 4 first.
-	subs	\order, \order, #3		@ yes, 3 is intended here
-	blt	2f
-
-1:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	cmp	\dividend, \divisor,  lsr #1
-	subhs	\dividend, \dividend, \divisor, lsr #1
-	cmp	\dividend, \divisor,  lsr #2
-	subhs	\dividend, \dividend, \divisor, lsr #2
-	cmp	\dividend, \divisor,  lsr #3
-	subhs	\dividend, \dividend, \divisor, lsr #3
-	cmp	\dividend, #1
-	mov	\divisor, \divisor, lsr #4
-	subges	\order, \order, #4
-	bge	1b
-
-	tst	\order, #3
-	teqne	\dividend, #0
-	beq	5f
-
-	@ Either 1, 2 or 3 comparison/substractions are left.
-2:	cmn	\order, #2
-	blt	4f
-	beq	3f
-	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	mov	\divisor,  \divisor,  lsr #1
-3:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	mov	\divisor,  \divisor,  lsr #1
-4:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-5:
-.endm
-
-	.align	5
-.globl __modsi3
-__modsi3:
-	cmp	r1, #0
-	beq	Ldiv0
-	rsbmi	r1, r1, #0			@ loops below use unsigned.
-	movs	ip, r0				@ preserve sign of dividend
-	rsbmi	r0, r0, #0			@ if negative make positive
-	subs	r2, r1, #1			@ compare divisor with 1
-	cmpne	r0, r1				@ compare dividend with divisor
-	moveq	r0, #0
-	tsthi	r1, r2				@ see if divisor is power of 2
-	andeq	r0, r0, r2
-	bls	10f
-
-	ARM_MOD_BODY r0, r1, r2, r3
-
-10:	cmp	ip, #0
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-
-Ldiv0:
-
-	str	lr, [sp, #-4]!
-	bl	__div0
-	mov	r0, #0			@ About as wrong as it could be.
-	ldr	pc, [sp], #4

lib_arm/_udivsi3.S

diff --git a/lib_arm/_udivsi3.S b/lib_arm/_udivsi3.S
deleted file mode 100644
index 2cdcd48..0000000
--- a/lib_arm/_udivsi3.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-dividend	.req	r0
-divisor		.req	r1
-result		.req	r2
-curbit		.req	r3
-/* ip		.req	r12	*/
-/* sp		.req	r13	*/
-/* lr		.req	r14	*/
-/* pc		.req	r15	*/
-	.text
-	.globl	 __udivsi3
-	.type  __udivsi3       ,function
-	.align	0
- __udivsi3      :
-	cmp	divisor, #0
-	beq	Ldiv0
-	mov	curbit, #1
-	mov	result, #0
-	cmp	dividend, divisor
-	bcc	Lgot_result
-Loop1:
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-	cmp	divisor, #0x10000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #4
-	movcc	curbit, curbit, lsl #4
-	bcc	Loop1
-Lbignum:
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-	cmp	divisor, #0x80000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #1
-	movcc	curbit, curbit, lsl #1
-	bcc	Lbignum
-Loop3:
-	@ Test for possible subtractions, and note which bits
-	@ are done in the result.  On the final pass, this may subtract
-	@ too much from the dividend, but the result will be ok, since the
-	@ "bit" will have been shifted out at the bottom.
-	cmp	dividend, divisor
-	subcs	dividend, dividend, divisor
-	orrcs	result, result, curbit
-	cmp	dividend, divisor, lsr #1
-	subcs	dividend, dividend, divisor, lsr #1
-	orrcs	result, result, curbit, lsr #1
-	cmp	dividend, divisor, lsr #2
-	subcs	dividend, dividend, divisor, lsr #2
-	orrcs	result, result, curbit, lsr #2
-	cmp	dividend, divisor, lsr #3
-	subcs	dividend, dividend, divisor, lsr #3
-	orrcs	result, result, curbit, lsr #3
-	cmp	dividend, #0			@ Early termination?
-	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
-	movne	divisor, divisor, lsr #4
-	bne	Loop3
-Lgot_result:
-	mov	r0, result
-	mov 	pc, lr
-Ldiv0:
-	str	lr, [sp, #-4]!
-	bl	 __div0       (PLT)
-	mov	r0, #0			@ about as wrong as it could be
-	ldmia	sp!, {pc}
-	.size  __udivsi3       , . -  __udivsi3
-/* # 235 "libgcc1.S" */
-/* # 320 "libgcc1.S" */
-/* # 421 "libgcc1.S" */
-/* # 433 "libgcc1.S" */
-/* # 456 "libgcc1.S" */
-/* # 500 "libgcc1.S" */
-/* # 580 "libgcc1.S" */

lib_arm/_umodsi3.S

diff --git a/lib_arm/_umodsi3.S b/lib_arm/_umodsi3.S
deleted file mode 100644
index e4aebe8..0000000
--- a/lib_arm/_umodsi3.S
+++ /dev/null
@@ -1,88 +0,0 @@
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-/* # 145 "libgcc1.S" */
-dividend	.req	r0
-divisor		.req	r1
-overdone	.req	r2
-curbit		.req	r3
-/* ip		.req	r12	*/
-/* sp		.req	r13	*/
-/* lr		.req	r14	*/
-/* pc		.req	r15	*/
-	.text
-	.globl	 __umodsi3
-	.type  __umodsi3       ,function
-	.align 0
- __umodsi3      :
-	cmp	divisor, #0
-	beq	Ldiv0
-	mov	curbit, #1
-	cmp	dividend, divisor
-	movcc  	pc, lr
-Loop1:
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-	cmp	divisor, #0x10000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #4
-	movcc	curbit, curbit, lsl #4
-	bcc	Loop1
-Lbignum:
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-	cmp	divisor, #0x80000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #1
-	movcc	curbit, curbit, lsl #1
-	bcc	Lbignum
-Loop3:
-	@ Test for possible subtractions.  On the final pass, this may
-	@ subtract too much from the dividend, so keep track of which
-	@ subtractions are done, we can fix them up afterwards...
-	mov	overdone, #0
-	cmp	dividend, divisor
-	subcs	dividend, dividend, divisor
-	cmp	dividend, divisor, lsr #1
-	subcs	dividend, dividend, divisor, lsr #1
-	orrcs	overdone, overdone, curbit, ror #1
-	cmp	dividend, divisor, lsr #2
-	subcs	dividend, dividend, divisor, lsr #2
-	orrcs	overdone, overdone, curbit, ror #2
-	cmp	dividend, divisor, lsr #3
-	subcs	dividend, dividend, divisor, lsr #3
-	orrcs	overdone, overdone, curbit, ror #3
-	mov	ip, curbit
-	cmp	dividend, #0			@ Early termination?
-	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
-	movne	divisor, divisor, lsr #4
-	bne	Loop3
-	@ Any subtractions that we should not have done will be recorded in
-	@ the top three bits of "overdone".  Exactly which were not needed
-	@ are governed by the position of the bit, stored in ip.
-	@ If we terminated early, because dividend became zero,
-	@ then none of the below will match, since the bit in ip will not be
-	@ in the bottom nibble.
-	ands	overdone, overdone, #0xe0000000
-	moveq  	pc, lr				@ No fixups needed
-	tst	overdone, ip, ror #3
-	addne	dividend, dividend, divisor, lsr #3
-	tst	overdone, ip, ror #2
-	addne	dividend, dividend, divisor, lsr #2
-	tst	overdone, ip, ror #1
-	addne	dividend, dividend, divisor, lsr #1
-	mov 	pc, lr
-Ldiv0:
-	str	lr, [sp, #-4]!
-	bl	 __div0       (PLT)
-	mov	r0, #0			@ about as wrong as it could be
-	ldmia	sp!, {pc}
-	.size  __umodsi3       , . -  __umodsi3
-/* # 320 "libgcc1.S" */
-/* # 421 "libgcc1.S" */
-/* # 433 "libgcc1.S" */
-/* # 456 "libgcc1.S" */
-/* # 500 "libgcc1.S" */
-/* # 580 "libgcc1.S" */

lib_arm/armlinux.c

diff --git a/lib_arm/armlinux.c b/lib_arm/armlinux.c
index 56b7fca..43547b9 100644
--- a/lib_arm/armlinux.c
+++ b/lib_arm/armlinux.c
@@ -265,7 +265,7 @@
 	}
 #endif
 
-	cleanup_before_linux ();
+	//cleanup_before_linux ();
 
 	theKernel (0, bd->bi_arch_number, bd->bi_boot_params);
 }

lib_arm/ashldi3.S

diff --git a/lib_arm/_ashldi3.S b/lib_arm/ashldi3.S
similarity index 93%
rename from lib_arm/_ashldi3.S
rename to lib_arm/ashldi3.S
index de4403d..1410adf 100644
--- a/lib_arm/_ashldi3.S
+++ b/lib_arm/ashldi3.S
@@ -25,6 +25,7 @@
 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
 Boston, MA 02110-1301, USA.  */
 
+#include <linux/linkage.h>
 
 #ifdef __ARMEB__
 #define al r1
@@ -34,8 +35,8 @@
 #define ah r1
 #endif
 
-.globl __ashldi3
-__ashldi3:
+ENTRY(__ashldi3)
+ENTRY(__aeabi_llsl)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -44,3 +45,6 @@
 	orrmi	ah, ah, al, lsr ip
 	mov	al, al, lsl r2
 	mov	pc, lr
+
+ENDPROC(__ashldi3)
+ENDPROC(__aeabi_llsl)

lib_arm/ashrdi3.S

diff --git a/lib_arm/_ashrdi3.S b/lib_arm/ashrdi3.S
similarity index 93%
copy from lib_arm/_ashrdi3.S
copy to lib_arm/ashrdi3.S
index 5edbcb3..6e96280 100644
--- a/lib_arm/_ashrdi3.S
+++ b/lib_arm/ashrdi3.S
@@ -25,6 +25,7 @@
 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
 Boston, MA 02110-1301, USA.  */
 
+#include <linux/linkage.h>
 
 #ifdef __ARMEB__
 #define al r1
@@ -34,8 +35,8 @@
 #define ah r1
 #endif
 
-.globl __ashrdi3
-__ashrdi3:
+ENTRY(__ashrdi3)
+ENTRY(__aeabi_lasr)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
@@ -44,3 +45,6 @@
 	orrmi	al, al, ah, lsl ip
 	mov	ah, ah, asr r2
 	mov	pc, lr
+
+ENDPROC(__ashrdi3)
+ENDPROC(__aeabi_lasr)

lib_arm/board.c

diff --git a/lib_arm/board.c b/lib_arm/board.c
index babc254..010e8cc 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -214,12 +214,16 @@
 int print_cpuinfo (void); /* test-only */
 
 init_fnc_t *init_sequence[] = {
+#if 0
 	cpu_init,		/* basic cpu dependent setup */
+#endif
 	board_init,		/* basic board dependent setup */
 	interrupt_init,		/* set up exceptions */
 	env_init,		/* initialize environment */
+#if 0
 	init_baudrate,		/* initialze baudrate settings */
 	serial_init,		/* serial communications setup */
+#endif
 	console_init_f,		/* stage 1 init of console */
 	display_banner,		/* say that we are here */
 #if defined(CONFIG_DISPLAY_CPUINFO)
@@ -228,11 +232,18 @@
 #if defined(CONFIG_DISPLAY_BOARDINFO)
 	checkboard,		/* display board info */
 #endif
+#if 0
 	dram_init,		/* configure available RAM banks */
 	display_dram_config,
+#endif
 	NULL,
 };
 
+#if defined(CONFIG_M8324XG) || defined(CONFIG_M8325XG) || defined(CONFIG_M8326XG)
+unsigned char comcerto_part_no[8];
+#define COMCERTO_PART_MAGIC 0x4D535044
+#endif
+
 void start_armboot (void)
 {
 	init_fnc_t **init_fnc_ptr;
@@ -253,7 +264,7 @@
 	gd->bd = (bd_t*)((char*)gd - sizeof(bd_t));
 	memset (gd->bd, 0, sizeof (bd_t));
 
-	monitor_flash_len = _bss_start - _armboot_start;
+	//monitor_flash_len = _bss_start - _armboot_start;
 
 	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
 		if ((*init_fnc_ptr)() != 0) {
@@ -261,6 +272,18 @@
 		}
 	}
 
+#if defined(CONFIG_M8324XG) || defined(CONFIG_M8325XG) || defined(CONFIG_M8326XG)
+        /* Check for the magic number if Comcerto Part No is programmed by
+ 	 * eeprom or not */
+	if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  == COMCERTO_PART_MAGIC)
+	{
+		memcpy(comcerto_part_no,(unsigned char*)(ARAM_BASEADDR+0x10100), 8);
+	}
+	else {
+		strcpy(comcerto_part_no,COMCERTO_PART_NO);
+	}
+#endif
+
 #ifndef CFG_NO_FLASH
 	/* configure available FLASH banks */
 	size = flash_init ();
@@ -313,7 +336,7 @@
 	/* must do this after the framebuffer is allocated */
 	drv_vfd_init();
 #endif /* CONFIG_VFD */
-
+#if 0
 	/* IP Address */
 	gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
 
@@ -344,7 +367,7 @@
 		}
 #endif
 	}
-
+#endif
 	devices_init ();	/* get the devices list going. */
 
 #ifdef CONFIG_CMC_PU2
@@ -367,7 +390,7 @@
 #ifdef CONFIG_DRIVER_CS8900
 	cs8900_get_enetaddr (gd->bd->bi_enetaddr);
 #endif
-
+#if 0
 #if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
 	if (getenv ("ethaddr")) {
 		smc_set_mac_addr(gd->bd->bi_enetaddr);
@@ -383,7 +406,7 @@
 		copy_filename (BootFile, s, sizeof (BootFile));
 	}
 #endif	/* CFG_CMD_NET */
-
+#endif
 #ifdef BOARD_LATE_INIT
 	board_late_init ();
 #endif

lib_arm/interrupts.c

diff --git a/lib_arm/interrupts.c b/lib_arm/interrupts.c
new file mode 100644
index 0000000..7746e3b
--- /dev/null
+++ b/lib_arm/interrupts.c
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/proc-armv/ptrace.h>
+
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+
+int interrupt_init (void)
+{
+	/*
+	 * setup up stacks if necessary
+	 */
+	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
+	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+
+	return arch_interrupt_init();
+}
+
+/* enable IRQ interrupts */
+void enable_interrupts (void)
+{
+	unsigned long temp;
+	__asm__ __volatile__("mrs %0, cpsr\n"
+			     "bic %0, %0, #0x80\n"
+			     "msr cpsr_c, %0"
+			     : "=r" (temp)
+			     :
+			     : "memory");
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+	unsigned long old,temp;
+	__asm__ __volatile__("mrs %0, cpsr\n"
+			     "orr %1, %0, #0xc0\n"
+			     "msr cpsr_c, %1"
+			     : "=r" (old), "=r" (temp)
+			     :
+			     : "memory");
+	return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts (void)
+{
+	return;
+}
+int disable_interrupts (void)
+{
+	return 0;
+}
+#endif
+
+
+void bad_mode (void)
+{
+	panic ("Resetting CPU ...\n");
+	//reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+	unsigned long flags;
+	const char *processor_modes[] = {
+	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
+	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
+	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
+	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
+	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
+	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
+	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
+	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
+	};
+
+	flags = condition_codes (regs);
+#if 1 // CHANDU
+	printf ("pc : [<%08lx>]	   lr : [<%08lx>]\n"
+		"sp : %08lx  ip : %08lx	 fp : %08lx\n",
+		instruction_pointer (regs),
+		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+	printf ("r10: %08lx  r9 : %08lx	 r8 : %08lx\n",
+		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+	printf ("r7 : %08lx  r6 : %08lx	 r5 : %08lx  r4 : %08lx\n",
+		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+	printf ("r3 : %08lx  r2 : %08lx	 r1 : %08lx  r0 : %08lx\n",
+		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+	printf ("Flags: %c%c%c%c",
+		flags & CC_N_BIT ? 'N' : 'n',
+		flags & CC_Z_BIT ? 'Z' : 'z',
+		flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
+		interrupts_enabled (regs) ? "on" : "off",
+		fast_interrupts_enabled (regs) ? "on" : "off",
+		processor_modes[processor_mode (regs)],
+		thumb_mode (regs) ? " (T)" : "");
+#endif
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+	printf ("undefined instruction\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+	printf ("software interrupt\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+	printf ("prefetch abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+	printf ("data abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+	printf ("not used\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+	printf ("fast interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+#ifndef CONFIG_USE_IRQ
+void do_irq (struct pt_regs *pt_regs)
+{
+	printf ("interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+#endif

lib_arm/lib1funcs.S

diff --git a/lib_arm/lib1funcs.S b/lib_arm/lib1funcs.S
new file mode 100644
index 0000000..e17b214
--- /dev/null
+++ b/lib_arm/lib1funcs.S
@@ -0,0 +1,344 @@
+/*
+ * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
+ *
+ * Author: Nicolas Pitre <nico at cam.org>
+ *   - contributed to gcc-3.4 on Sep 30, 2003
+ *   - adapted for the Linux kernel on Oct 2, 2003
+ */
+
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file.  (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+
+.macro ARM_DIV_BODY dividend, divisor, result, curbit
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\curbit, \divisor
+	clz	\result, \dividend
+	sub	\result, \curbit, \result
+	mov	\curbit, #1
+	mov	\divisor, \divisor, lsl \result
+	mov	\curbit, \curbit, lsl \result
+	mov	\result, #0
+	
+#else
+
+	@ Initially shift the divisor left 3 bits if possible,
+	@ set curbit accordingly.  This allows for curbit to be located
+	@ at the left end of each 4 bit nibbles in the division loop
+	@ to save one loop in most cases.
+	tst	\divisor, #0xe0000000
+	moveq	\divisor, \divisor, lsl #3
+	moveq	\curbit, #8
+	movne	\curbit, #1
+
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is 
+	@ larger than the dividend.
+1:	cmp	\divisor, #0x10000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #4
+	movlo	\curbit, \curbit, lsl #4
+	blo	1b
+
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+1:	cmp	\divisor, #0x80000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #1
+	movlo	\curbit, \curbit, lsl #1
+	blo	1b
+
+	mov	\result, #0
+
+#endif
+
+	@ Division loop
+1:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	orrhs	\result,   \result,   \curbit
+	cmp	\dividend, \divisor,  lsr #1
+	subhs	\dividend, \dividend, \divisor, lsr #1
+	orrhs	\result,   \result,   \curbit,  lsr #1
+	cmp	\dividend, \divisor,  lsr #2
+	subhs	\dividend, \dividend, \divisor, lsr #2
+	orrhs	\result,   \result,   \curbit,  lsr #2
+	cmp	\dividend, \divisor,  lsr #3
+	subhs	\dividend, \dividend, \divisor, lsr #3
+	orrhs	\result,   \result,   \curbit,  lsr #3
+	cmp	\dividend, #0			@ Early termination?
+	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
+	movne	\divisor,  \divisor, lsr #4
+	bne	1b
+
+.endm
+
+
+.macro ARM_DIV2_ORDER divisor, order
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\order, \divisor
+	rsb	\order, \order, #31
+
+#else
+
+	cmp	\divisor, #(1 << 16)
+	movhs	\divisor, \divisor, lsr #16
+	movhs	\order, #16
+	movlo	\order, #0
+
+	cmp	\divisor, #(1 << 8)
+	movhs	\divisor, \divisor, lsr #8
+	addhs	\order, \order, #8
+
+	cmp	\divisor, #(1 << 4)
+	movhs	\divisor, \divisor, lsr #4
+	addhs	\order, \order, #4
+
+	cmp	\divisor, #(1 << 2)
+	addhi	\order, \order, #3
+	addls	\order, \order, \divisor, lsr #1
+
+#endif
+
+.endm
+
+
+.macro ARM_MOD_BODY dividend, divisor, order, spare
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\order, \divisor
+	clz	\spare, \dividend
+	sub	\order, \order, \spare
+	mov	\divisor, \divisor, lsl \order
+
+#else
+
+	mov	\order, #0
+
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is 
+	@ larger than the dividend.
+1:	cmp	\divisor, #0x10000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #4
+	addlo	\order, \order, #4
+	blo	1b
+
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+1:	cmp	\divisor, #0x80000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #1
+	addlo	\order, \order, #1
+	blo	1b
+
+#endif
+
+	@ Perform all needed substractions to keep only the reminder.
+	@ Do comparisons in batch of 4 first.
+	subs	\order, \order, #3		@ yes, 3 is intended here
+	blt	2f
+
+1:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	cmp	\dividend, \divisor,  lsr #1
+	subhs	\dividend, \dividend, \divisor, lsr #1
+	cmp	\dividend, \divisor,  lsr #2
+	subhs	\dividend, \dividend, \divisor, lsr #2
+	cmp	\dividend, \divisor,  lsr #3
+	subhs	\dividend, \dividend, \divisor, lsr #3
+	cmp	\dividend, #1
+	mov	\divisor, \divisor, lsr #4
+	subges	\order, \order, #4
+	bge	1b
+
+	tst	\order, #3
+	teqne	\dividend, #0
+	beq	5f
+
+	@ Either 1, 2 or 3 comparison/substractions are left.
+2:	cmn	\order, #2
+	blt	4f
+	beq	3f
+	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	mov	\divisor,  \divisor,  lsr #1
+3:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	mov	\divisor,  \divisor,  lsr #1
+4:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+5:
+.endm
+
+
+ENTRY(__udivsi3)
+ENTRY(__aeabi_uidiv)
+
+	subs	r2, r1, #1
+	moveq	pc, lr
+	bcc	Ldiv0
+	cmp	r0, r1
+	bls	11f
+	tst	r1, r2
+	beq	12f
+
+	ARM_DIV_BODY r0, r1, r2, r3
+
+	mov	r0, r2
+	mov	pc, lr
+
+11:	moveq	r0, #1
+	movne	r0, #0
+	mov	pc, lr
+
+12:	ARM_DIV2_ORDER r1, r2
+
+	mov	r0, r0, lsr r2
+	mov	pc, lr
+
+ENDPROC(__udivsi3)
+ENDPROC(__aeabi_uidiv)
+
+ENTRY(__umodsi3)
+
+	subs	r2, r1, #1			@ compare divisor with 1
+	bcc	Ldiv0
+	cmpne	r0, r1				@ compare dividend with divisor
+	moveq   r0, #0
+	tsthi	r1, r2				@ see if divisor is power of 2
+	andeq	r0, r0, r2
+	movls	pc, lr
+
+	ARM_MOD_BODY r0, r1, r2, r3
+
+	mov	pc, lr
+
+ENDPROC(__umodsi3)
+
+ENTRY(__divsi3)
+ENTRY(__aeabi_idiv)
+
+	cmp	r1, #0
+	eor	ip, r0, r1			@ save the sign of the result.
+	beq	Ldiv0
+	rsbmi	r1, r1, #0			@ loops below use unsigned.
+	subs	r2, r1, #1			@ division by 1 or -1 ?
+	beq	10f
+	movs	r3, r0
+	rsbmi	r3, r0, #0			@ positive dividend value
+	cmp	r3, r1
+	bls	11f
+	tst	r1, r2				@ divisor is power of 2 ?
+	beq	12f
+
+	ARM_DIV_BODY r3, r1, r0, r2
+
+	cmp	ip, #0
+	rsbmi	r0, r0, #0
+	mov	pc, lr
+
+10:	teq	ip, r0				@ same sign ?
+	rsbmi	r0, r0, #0
+	mov	pc, lr
+
+11:	movlo	r0, #0
+	moveq	r0, ip, asr #31
+	orreq	r0, r0, #1
+	mov	pc, lr
+
+12:	ARM_DIV2_ORDER r1, r2
+
+	cmp	ip, #0
+	mov	r0, r3, lsr r2
+	rsbmi	r0, r0, #0
+	mov	pc, lr
+
+ENDPROC(__divsi3)
+ENDPROC(__aeabi_idiv)
+
+ENTRY(__modsi3)
+
+	cmp	r1, #0
+	beq	Ldiv0
+	rsbmi	r1, r1, #0			@ loops below use unsigned.
+	movs	ip, r0				@ preserve sign of dividend
+	rsbmi	r0, r0, #0			@ if negative make positive
+	subs	r2, r1, #1			@ compare divisor with 1
+	cmpne	r0, r1				@ compare dividend with divisor
+	moveq	r0, #0
+	tsthi	r1, r2				@ see if divisor is power of 2
+	andeq	r0, r0, r2
+	bls	10f
+
+	ARM_MOD_BODY r0, r1, r2, r3
+
+10:	cmp	ip, #0
+	rsbmi	r0, r0, #0
+	mov	pc, lr
+
+ENDPROC(__modsi3)
+
+ENTRY(__aeabi_uidivmod)
+
+	stmfd	sp!, {r0, r1, ip, lr}
+	bl	__aeabi_uidiv
+	ldmfd	sp!, {r1, r2, ip, lr}
+	mul	r3, r0, r2
+	sub	r1, r1, r3
+	mov	pc, lr
+
+ENDPROC(__aeabi_uidivmod)
+
+ENTRY(__aeabi_idivmod)
+
+	stmfd	sp!, {r0, r1, ip, lr}
+	bl	__aeabi_idiv
+	ldmfd	sp!, {r1, r2, ip, lr}
+	mul	r3, r0, r2
+	sub	r1, r1, r3
+	mov	pc, lr
+
+ENDPROC(__aeabi_idivmod)
+
+Ldiv0:
+
+	str	lr, [sp, #-8]!
+	bl	__div0
+	mov	r0, #0			@ About as wrong as it could be.
+	ldr	pc, [sp], #8
+
+

lib_generic/Makefile

diff --git a/lib_generic/Makefile b/lib_generic/Makefile
index f012cab..285e99a 100644
--- a/lib_generic/Makefile
+++ b/lib_generic/Makefile
@@ -28,7 +28,7 @@
 COBJS	= bzlib.o bzlib_crctable.o bzlib_decompress.o \
 	  bzlib_randtable.o bzlib_huffman.o \
 	  crc32.o ctype.o display_options.o ldiv.o \
-	  string.o vsprintf.o zlib.o
+	  string.o vsprintf.o zlib.o div64.o
 
 SRCS 	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

lib_generic/crc32.c

diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c
index 3d99b69..bdee8e8 100644
--- a/lib_generic/crc32.c
+++ b/lib_generic/crc32.c
@@ -195,4 +195,32 @@
     return crc;
 }
 
+/*
+ * Calculate the crc32 checksum triggering the watchdog every 'chunk_sz' bytes
+ * of input.
+ */
+uint32_t ZEXPORT crc32_wd (uint32_t crc,
+			   const unsigned char *buf,
+			   uInt len, uInt chunk_sz)
+{
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+	const unsigned char *end, *curr;
+	int chunk;
+
+	curr = buf;
+	end = buf + len;
+	while (curr < end) {
+		chunk = end - curr;
+		if (chunk > chunk_sz)
+			chunk = chunk_sz;
+		crc = crc32 (crc, curr, chunk);
+		curr += chunk;
+		WATCHDOG_RESET ();
+	}
+#else
+	crc = crc32 (crc, buf, len);
+#endif
+
+	return crc;
+}
 #endif	/* CFG_CMD_JFFS2 */

lib_generic/div64.c

diff --git a/lib_generic/div64.c b/lib_generic/div64.c
new file mode 100644
index 0000000..e688a91
--- /dev/null
+++ b/lib_generic/div64.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ *
+ * Based on former do_div() implementation from asm-parisc/div64.h:
+ *	Copyright (C) 1999 Hewlett-Packard Co
+ *	Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ *
+ * Generic C version of 64bit/32bit division and modulo, with
+ * 64bit result and 32bit remainder.
+ *
+ * The fast case for (n>>32 == 0) is handled inline by do_div().
+ *
+ * Code generated for this function might be very inefficient
+ * for some CPUs. __div64_32() can be overridden by linking arch-specific
+ * assembly versions such as arch/powerpc/lib/div64.S and arch/sh/lib/div64.S.
+ */
+
+#include <linux/types.h>
+
+uint32_t __div64_32(uint64_t *n, uint32_t base)
+{
+	uint64_t rem = *n;
+	uint64_t b = base;
+	uint64_t res, d = 1;
+	uint32_t high = rem >> 32;
+
+	/* Reduce the thing a bit first */
+	res = 0;
+	if (high >= base) {
+		high /= base;
+		res = (uint64_t) high << 32;
+		rem -= (uint64_t) (high*base) << 32;
+	}
+
+	while ((int64_t)b > 0 && b < rem) {
+		b = b+b;
+		d = d+d;
+	}
+
+	do {
+		if (rem >= b) {
+			rem -= b;
+			res += d;
+		}
+		b >>= 1;
+		d >>= 1;
+	} while (d);
+
+	*n = res;
+	return rem;
+}

lib_generic/string.c

diff --git a/lib_generic/string.c b/lib_generic/string.c
index e0b793a..444c2ea 100644
--- a/lib_generic/string.c
+++ b/lib_generic/string.c
@@ -214,6 +214,45 @@
 }
 #endif
 
+
+/**
+ * skip_spaces - Removes leading whitespace from @str.
+ * @str: The string to be stripped.
+ *
+ * Returns a pointer to the first non-whitespace character in @str.
+ */
+char *skip_spaces(const char *str)
+{
+	while (isspace(*str))
+		++str;
+	return (char *)str;
+}
+
+/**
+ * strim - Removes leading and trailing whitespace from @s.
+ * @s: The string to be stripped.
+ *
+ * Note that the first trailing whitespace is replaced with a %NUL-terminator
+ * in the given string @s. Returns a pointer to the first non-whitespace
+ * character in @s.
+ */
+char *strim(char *s)
+{
+	size_t size;
+	char *end;
+
+	s = skip_spaces(s);
+	size = strlen(s);
+	if (!size)
+		return s;
+
+	end = s + size - 1;
+	while (end >= s && isspace(*end))
+		end--;
+	*(end + 1) = '\0';
+
+	return s;
+}
 #ifndef __HAVE_ARCH_STRLEN
 /**
  * strlen - Find the length of a string

make_release.sh

diff --git a/make_release.sh b/make_release.sh
new file mode 100644
index 0000000..20edefb
--- /dev/null
+++ b/make_release.sh
@@ -0,0 +1,97 @@
+#!/bin/bash
+
+UBOOT_BASE_VERSION=1.1.6
+UBOOT_MAJOR_VERSION=0.04
+UBOOT_MINOR_VERSION=0
+
+CONFIGS='tsavo530 tsavo515 tsavo515_nor megamombasa515 ipots48-800 malindi'
+#CONFIGS='supermombasa910 matisse'
+
+DIFF_FILES_DIRS='Makefile drivers net board/mindspeed cpu/arm920t include/configs include/asm-arm/arch-comcerto'
+#DIFF_FILES_DIRS='Makefile drivers net board/mindspeed cpu/arm1136 include/configs include/asm-arm/arch-comcerto'
+
+CVS_USER=rui.sousa
+
+UBOOT_CVS_TAG=u-boot_`echo ${UBOOT_MAJOR_VERSION} | sed s/\\\./_/g -`_${UBOOT_MINOR_VERSION}
+UBOOT_BASE_CVS_TAG=u-boot_`echo ${UBOOT_BASE_VERSION} | sed s/\\\./_/g -`
+UBOOT_VERSION=${UBOOT_BASE_VERSION}-${UBOOT_MAJOR_VERSION}.${UBOOT_MINOR_VERSION}
+UBOOT_PACKAGE=u-boot-${UBOOT_VERSION}
+
+UBOOT_CVS_DIR=u-boot-${UBOOT_CVS_TAG}-cvs
+CVS_ROOT=/prj/msacvs/enterprise
+CVS_REPOSITORY=u-boot
+CVS_SERVER=cvshost.nb-engr.mindspeed.com
+KERNEL_FTP_DIR=platform_group/enterprise/u-boot/releases/${UBOOT_MAJOR_VERSION}
+
+FTP_SERVER=ftp://sophial1.nice.mindspeed.com
+FTP_USER=user
+FTP_PASSWD='123456'
+
+TOOLCHAIN_PATH=/usr/local/gcc-3.4.5-glibc-2.3.6/arm-softfloat-linux-gnu/bin
+
+set -e
+
+TOP_DIR=`pwd`
+
+export PATH=$PATH:$TOOLCHAIN_PATH
+
+echo "Retrieving u-boot ${UBOOT_VERSION} from CVS (tag ${UBOOT_CVS_TAG})"
+
+rm -fr $UBOOT_CVS_DIR
+cvs -z6 -d:pserver:${CVS_USER}@${CVS_SERVER}:${CVS_ROOT} co -d ${UBOOT_CVS_DIR} -r ${UBOOT_CVS_TAG} ${CVS_REPOSITORY} > make_release.log 2>&1
+
+rm -f ${UBOOT_PACKAGE}.md5sum
+
+for config in $CONFIGS; do
+
+	cd ${TOP_DIR}/${UBOOT_CVS_DIR}
+	echo "Cleaning u-boot source"
+	make distclean >> ${TOP_DIR}/make_release.log 2>&1
+
+	echo "Configuring for ${config}"
+	make ${config}_config >> ${TOP_DIR}/make_release.log 2>&1
+
+	echo "Building binary"
+	make >> ${TOP_DIR}/make_release.log 2>&1
+
+	cd ${TOP_DIR}
+
+	extra=`echo ${config}`
+
+	package=${UBOOT_PACKAGE}${extra}.bin
+	echo "Preparing ${package}"
+	rm -f ${package}
+	cp ${UBOOT_CVS_DIR}/u-boot.bin ${package}
+	md5sum ${package} >> ${UBOOT_PACKAGE}.md5sum 
+
+	package=${UBOOT_PACKAGE}${extra}.elf
+	echo "Preparing ${package}"
+	rm -f ${package}
+	cp ${UBOOT_CVS_DIR}/u-boot ${package}
+	md5sum ${package} >> ${UBOOT_PACKAGE}.md5sum 
+
+done
+
+cd ${TOP_DIR}
+package=${UBOOT_PACKAGE}.patch.bz2
+echo "Preparing ${package}"
+rm -fr ${package} 
+cd ${TOP_DIR}/${UBOOT_CVS_DIR}
+set +e
+cvs -z6 diff -uN -r ${UBOOT_BASE_CVS_TAG} ${DIFF_FILES_DIRS} > ${TOP_DIR}/${UBOOT_PACKAGE}.patch 2>> ${TOP_DIR}/make_release.log
+set -e
+cd ${TOP_DIR} 
+bzip2 -9 ${UBOOT_PACKAGE}.patch
+md5sum ${package} >> ${UBOOT_PACKAGE}.md5sum
+
+echo "Preparing ${UBOOT_PACKAGE}.tar.bz2"
+rm -fr $UBOOT_PACKAGE
+cp -a $UBOOT_CVS_DIR $UBOOT_PACKAGE
+cd $UBOOT_PACKAGE
+rm -fr `find ./ -name CVS`
+make distclean >> ${TOP_DIR}/make_release.log 2>&1
+
+cd ${TOP_DIR}
+rm -f ${UBOOT_PACKAGE}.tar.bz2
+tar -vcjf ${UBOOT_PACKAGE}.tar.bz2 $UBOOT_PACKAGE >> ${TOP_DIR}/make_release.log 2>&1
+md5sum ${UBOOT_PACKAGE}.tar.bz2 >> ${UBOOT_PACKAGE}.md5sum

net/eth.c

diff --git a/net/eth.c b/net/eth.c
index e8ac251..5d15455 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -54,6 +54,8 @@
 extern int skge_initialize(bd_t*);
 extern int tsec_initialize(bd_t*, int, char *);
 extern int npe_initialize(bd_t *);
+extern int comcerto_gemac_initialize(bd_t *bis, int index, char *devname);
+extern int c2000_gemac_initialize(bd_t *bis, int index, char *devname);
 
 static struct eth_device *eth_devices, *eth_current;
 
@@ -141,7 +143,16 @@
 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
 	miiphy_init();
 #endif
-
+#if defined(CONFIG_COMCERTO_900)
+	comcerto_gemac_initialize(bis, 0, "comcerto_gemac0");
+#endif
+#if defined(CONFIG_COMCERTO_100) || defined(CONFIG_COMCERTO_1000)
+	comcerto_gemac_initialize(bis, 0, "comcerto_gemac0");
+	comcerto_gemac_initialize(bis, 1, "comcerto_gemac1");
+#endif
+#if defined(CONFIG_COMCERTO_2000)
+	c2000_gemac_initialize(bis, 0, "c2000_gemac0");
+#endif
 #ifdef CONFIG_DB64360
 	mv6436x_eth_initialize(bis);
 #endif
@@ -464,7 +475,7 @@
 extern int emac4xx_miiphy_initialize(bd_t *bis);
 extern int mcf52x2_miiphy_initialize(bd_t *bis);
 extern int ns7520_miiphy_initialize(bd_t *bis);
-
+extern int comcerto_miiphy_initialize(bd_t *bis);
 int eth_initialize(bd_t *bis)
 {
 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
@@ -474,6 +485,10 @@
 #if defined(CONFIG_AT91RM9200)
 	at91rm9200_miiphy_initialize(bis);
 #endif
+#if defined(CONFIG_COMCERTO_530) || defined(CONFIG_COMCERTO_515) \
+	|| defined(CONFIG_COMCERTO_800) || defined(CONFIG_COMCERTO_900)
+	comcerto_miiphy_initialize(bis);
+#endif
 #if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) \
 	&& !defined(CONFIG_AP1000) && !defined(CONFIG_405)
 	emac4xx_miiphy_initialize(bis);

tools/mkimage.c

diff --git a/tools/mkimage.c b/tools/mkimage.c
index 416e658..1643a67 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -69,12 +69,13 @@
 char *cmdname;
 
 extern unsigned long crc32 (unsigned long crc, const char *buf, unsigned int len);
-
+#if 0
 typedef struct table_entry {
 	int	val;		/* as defined in image.h	*/
 	char	*sname;		/* short (input) name		*/
 	char	*lname;		/* long (output) name		*/
 } table_entry_t;
+#endif
 
 table_entry_t arch_name[] = {
     {	IH_CPU_INVALID,		NULL,		"Invalid CPU",	},