ddr3libv2: fix multi-device support (device number other than 0)
- Add device number as parameter to ADLL read/write functions
- fix PBS training functions to support multi device mode
Change-Id: I61b55d9678acae3d78253eace8572d51a3c5d7df
Signed-off-by: Margarita Granov <margra@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24900
Tested-by: Star_New_DDR <star-new-ddr@marvell.com>
Tested-by: Star_Automation <star@marvell.com>
Reviewed-by: Haim Boot <hayim@marvell.com>
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h
index 0f7b5da..cec7712 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h
@@ -940,11 +940,11 @@
GT_STATUS ddr3TipResetFifoPtr(GT_U32 devNum);
-GT_BOOL readPupValue(GT_32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr, GT_U32 mask);
+GT_BOOL mvHwsDdr3TipReadPupValue(GT_U32 devNum, GT_32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr, GT_U32 mask);
-GT_BOOL readAdllValue(GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr, GT_U32 mask);
+GT_BOOL mvHwsDdr3TipReadAdllValue(GT_U32 devNum,GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr, GT_U32 mask);
-GT_BOOL writeAdllValue(GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr);
+GT_BOOL mvHwsDdr3TipWriteAdllValue(GT_U32 devNum,GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr);
/******************************************************************************
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
index 231643d..09a892f 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
@@ -714,12 +714,11 @@
/*****************************************************************************
Read ADLL Value
******************************************************************************/
-GT_BOOL readAdllValue(GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr, GT_U32 mask)
+GT_BOOL mvHwsDdr3TipReadAdllValue(GT_U32 devNum, GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr, GT_U32 mask)
{
GT_U32 dataValue;
GT_U32 interfaceId = 0, busId = 0;
- GT_U32 devNum = 0;
- GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
/* multi CS support - regAddr is calucalated in calling function with CS offset */
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
@@ -739,10 +738,10 @@
/*****************************************************************************
Write ADLL Value
******************************************************************************/
-GT_BOOL writeAdllValue(GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr)
+GT_BOOL mvHwsDdr3TipWriteAdllValue(GT_U32 devNum, GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr)
{
GT_U32 interfaceId = 0, busId = 0;
- GT_U32 devNum = 0, data;
+ GT_U32 data;
GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
/* multi CS support - regAddr is calucalated in calling function with CS offset */
@@ -765,11 +764,10 @@
/*****************************************************************************
Read Phase Value
******************************************************************************/
-GT_BOOL readPhaseValue(GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr, GT_U32 mask)
+GT_BOOL readPhaseValue(GT_U32 devNum,GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr, GT_U32 mask)
{
GT_U32 dataValue;
GT_U32 interfaceId = 0, busId = 0;
- GT_U32 devNum = 0;
GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
/* multi CS support - regAddr is calucalated in calling function with CS offset */
@@ -790,10 +788,10 @@
/*****************************************************************************
Write Leveling Value
******************************************************************************/
-GT_BOOL writeLevelingValue(GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], GT_U32 PupPhValues[MAX_INTERFACE_NUM*MAX_BUS_NUM],int regAddr)
+GT_BOOL writeLevelingValue(GT_U32 devNum,GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], GT_U32 PupPhValues[MAX_INTERFACE_NUM*MAX_BUS_NUM],int regAddr)
{
GT_U32 interfaceId = 0, busId = 0;
- GT_U32 devNum = 0, data;
+ GT_U32 data;
GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
/* multi CS support - regAddr is calucalated in calling function with CS offset */
@@ -1468,7 +1466,7 @@
ctrlADLL[adll] = 0;
}
/*Save DQS value(after algorithm run)*/
- readAdllValue(ctrlADLL, (reg + (uiCs * CS_REGISTER_ADDR_OFFSET)) , MASK_ALL_BITS );
+ mvHwsDdr3TipReadAdllValue(devNum,ctrlADLL, (reg + (uiCs * CS_REGISTER_ADDR_OFFSET)) , MASK_ALL_BITS );
/*Sweep ADLL from 0:31 on all I/F on all Pup and perform BIST on each stage.*/
for(pup=startPup; pup <=endPup; pup++)
@@ -1529,9 +1527,9 @@
mvPrintf("\n");
}
/*Write back to the phy the Rx DQS value, we store in the begging. */
- writeAdllValue(ctrlADLL, (reg + uiCs * CS_REGISTER_ADDR_OFFSET));
+ mvHwsDdr3TipWriteAdllValue(devNum,ctrlADLL, (reg + uiCs * CS_REGISTER_ADDR_OFFSET));
/* print adll results */
- readAdllValue(ctrlADLL, (reg + uiCs * CS_REGISTER_ADDR_OFFSET), MASK_ALL_BITS);
+ mvHwsDdr3TipReadAdllValue(devNum,ctrlADLL, (reg + uiCs * CS_REGISTER_ADDR_OFFSET), MASK_ALL_BITS);
mvPrintf("%s,DQS,ADLL,,,",(direction==0) ? "Tx":"Rx");
printAdll(devNum, ctrlADLL);
}
@@ -1588,11 +1586,11 @@
ctrlADLL1[adll] = 0;
}
/*Save Leveling value(after algorithm run)*/
- readAdllValue(ctrlADLL, (reg + (uiCs * CS_REGISTER_ADDR_OFFSET)) , 0x1F );
- readPhaseValue(ctrlLevelPhase, (reg + (uiCs * CS_REGISTER_ADDR_OFFSET)) , 0x7<<6 );
+ mvHwsDdr3TipReadAdllValue(devNum,ctrlADLL, (reg + (uiCs * CS_REGISTER_ADDR_OFFSET)) , 0x1F );
+ readPhaseValue(devNum,ctrlLevelPhase, (reg + (uiCs * CS_REGISTER_ADDR_OFFSET)) , 0x7<<6 );
if(direction == 0)
{
- readAdllValue(ctrlADLL1, (0x1 + (uiCs * CS_REGISTER_ADDR_OFFSET)) , MASK_ALL_BITS );
+ mvHwsDdr3TipReadAdllValue(devNum,ctrlADLL1, (0x1 + (uiCs * CS_REGISTER_ADDR_OFFSET)) , MASK_ALL_BITS );
}
/*Sweep ADLL from 0:31 on all I/F on all Pup and perform BIST on each stage.*/
for(pup=startPup; pup <=endPup; pup++)
@@ -1694,13 +1692,13 @@
mvPrintf("\n");
}
/*Write back to the phy the Rx DQS value, we store in the begging. */
- writeLevelingValue(ctrlADLL,ctrlLevelPhase, (reg + uiCs * CS_REGISTER_ADDR_OFFSET));
+ writeLevelingValue(devNum,ctrlADLL,ctrlLevelPhase, (reg + uiCs * CS_REGISTER_ADDR_OFFSET));
if(direction == 0)
{
- writeAdllValue(ctrlADLL1, (0x1 + (uiCs * CS_REGISTER_ADDR_OFFSET)));
+ mvHwsDdr3TipWriteAdllValue(devNum,ctrlADLL1, (0x1 + (uiCs * CS_REGISTER_ADDR_OFFSET)));
}
/* print adll results */
- readAdllValue(ctrlADLL, (reg + uiCs * CS_REGISTER_ADDR_OFFSET), MASK_ALL_BITS);
+ mvHwsDdr3TipReadAdllValue(devNum,ctrlADLL, (reg + uiCs * CS_REGISTER_ADDR_OFFSET), MASK_ALL_BITS);
mvPrintf("%s,DQS,Leveling,,,",(direction==0) ? "Tx":"Rx");
printAdll(devNum, ctrlADLL);
printPh(devNum, ctrlLevelPhase);
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingPbs.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingPbs.c
index 358a674..7be6f05 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingPbs.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingPbs.c
@@ -128,7 +128,7 @@
}
regAddr = (pbsMode == PBS_RX_MODE ) ? (READ_CENTRALIZATION_PHY_REG + (effective_cs * CS_REGISTER_ADDR_OFFSET)) : (WRITE_CENTRALIZATION_PHY_REG + (effective_cs * CS_REGISTER_ADDR_OFFSET));
- readAdllValue(nominalAdll, regAddr , MASK_ALL_BITS );
+ mvHwsDdr3TipReadAdllValue(devNum,nominalAdll, regAddr, MASK_ALL_BITS );
/* stage 1 shift ADLL */
/*ddr3TipIpTrainingPerbitMultiCast( SearchDirection, Direction, InitValue, NumberOfIterations, pbsPattern, SearchEDGE_ , MV_HWS_ControlElement_ADLL);*/
@@ -551,7 +551,7 @@
}
/*Write back to the phy the default values */
regAddr = (pbsMode == PBS_RX_MODE) ? (READ_CENTRALIZATION_PHY_REG + effective_cs * 4) : (WRITE_CENTRALIZATION_PHY_REG + effective_cs * 4);
- writeAdllValue(nominalAdll, regAddr);
+ mvHwsDdr3TipWriteAdllValue(devNum,nominalAdll, regAddr);
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
