diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x.h b/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x.h
old mode 100644
new mode 100755
index 8130cd9..99bdace
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x.h
@@ -104,9 +104,12 @@
 #define MV_TUNE_TRAINING_PARAMS_P_ODT_CTRL	45
 #define MV_TUNE_TRAINING_PARAMS_N_ODT_CTRL	45
 
-#define MV_TUNE_TRAINING_PARAMS_DIC			0x2
-#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG	0x120012
-#define MV_TUNE_TRAINING_PARAMS_RTT_NOM		0x44
+#define MV_TUNE_TRAINING_PARAMS_DIC				0x2
+#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS	0x120012
+#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS	0x10000
+#define MV_TUNE_TRAINING_PARAMS_RTT_NOM			0x44
+#define MV_TUNE_TRAINING_PARAMS_RTT_WR_1CS		0x0
+#define MV_TUNE_TRAINING_PARAMS_RTT_WR_2CS		0x0
 
 #ifdef CONFIG_DDR4
 #define MV_TUNE_TRAINING_PARAMS_P_ODT_DATA_DDR4	0xD
diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_ac3_vars.h b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_ac3_vars.h
old mode 100644
new mode 100755
index f6d3bdf..f8dd185
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_ac3_vars.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_ac3_vars.h
@@ -89,10 +89,12 @@
 #define MV_TUNE_TRAINING_PARAMS_P_ODT_CTRL	45
 #define MV_TUNE_TRAINING_PARAMS_N_ODT_CTRL	45
 
-#define MV_TUNE_TRAINING_PARAMS_DIC			0x2
-#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG	0x120012
-#define MV_TUNE_TRAINING_PARAMS_RTT_NOM		0x44
-#define MV_TUNE_TRAINING_PARAMS_RTT_WR		0x0 /*off*/
+#define MV_TUNE_TRAINING_PARAMS_DIC				0x2
+#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS	0x120012
+#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS	0x10000
+#define MV_TUNE_TRAINING_PARAMS_RTT_NOM			0x44
+#define MV_TUNE_TRAINING_PARAMS_RTT_WR_1CS		0x0 /* off */
+#define MV_TUNE_TRAINING_PARAMS_RTT_WR_2CS		0x0 /* off */
 
 typedef struct __mvDramModes {
     char *mode_name;
diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_vars.h b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_vars.h
old mode 100644
new mode 100755
index 07ff13d..634a671
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_vars.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/msys/ddr3_msys_bc2_vars.h
@@ -82,10 +82,12 @@
 #define MV_TUNE_TRAINING_PARAMS_P_ODT_CTRL	45
 #define MV_TUNE_TRAINING_PARAMS_N_ODT_CTRL	45
 
-#define MV_TUNE_TRAINING_PARAMS_DIC			0x2
-#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG	0x120012
-#define MV_TUNE_TRAINING_PARAMS_RTT_NOM		0x44
-#define MV_TUNE_TRAINING_PARAMS_RTT_WR		0x200 /*RZQ/4*/
+#define MV_TUNE_TRAINING_PARAMS_DIC				0x2
+#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS	0x120012
+#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS	0x10000
+#define MV_TUNE_TRAINING_PARAMS_RTT_NOM			0x44
+#define MV_TUNE_TRAINING_PARAMS_RTT_WR_1CS		0x200 /*RZQ/4*/
+#define MV_TUNE_TRAINING_PARAMS_RTT_WR_2CS		0x200 /*RZQ/4*/
 
 typedef struct __mvDramMcInit {
 	MV_U32 reg_addr;
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c b/tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c
index 30b926f..0255f77 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c
@@ -120,6 +120,20 @@
     MV_HWS_TOPOLOGY_MAP     *topology
 );
 
+extern MV_STATUS ddr3TipGetFirstActiveIf
+(
+    MV_U8   devNum,
+    MV_U32  interfaceMask,
+    MV_U32  *ifId
+);
+
+extern MV_STATUS    mvCalcCsNum
+(
+    MV_U32          devNum,
+	MV_U32          interfaceId,
+	MV_U32          *csNum
+);
+
 extern MV_U32 ddr3TipGetInitFreq();
 
 extern MV_VOID ddr3HwsSetLogLevel(
@@ -137,6 +151,9 @@
 static MV_U32 ddr3GetStaticDdrMode(void);
 #endif
 
+/* global parameter (defined in TIP lib which holds the DDR topology */
+extern MV_HWS_TOPOLOGY_MAP *topologyMap;
+
 /*Set 1 to use dynamic DUNIT configuration,
 	set 0(supported for A380 and AC3) to configure DUNIT in values set by ddr3TipInitSpecificRegConfig*/
 MV_U8 genericInitController = 1;
@@ -823,8 +840,18 @@
 static MV_STATUS ddr3HwsTuneTrainingParams(MV_U8 devNum)
 {
 	MV_TUNE_TRAINING_PARAMS params;
+	MV_U32 interfaceId;
+	MV_U32 csNum;
 	MV_STATUS status;
 
+	/* initilaize the global ddr topology */
+	CHECK_STATUS(ddr3GetTopologyMap(&topologyMap));
+
+	/* get first active interface */
+	CHECK_STATUS(ddr3TipGetFirstActiveIf(devNum, topologyMap->interfaceActiveMask, &interfaceId));
+
+	CHECK_STATUS(mvCalcCsNum(devNum, interfaceId, &csNum));
+
 	/*NOTE: do not remove any field initilization*/
 	params.ckDelay = MV_TUNE_TRAINING_PARAMS_CK_DELAY;
 	params.PhyReg3Val = MV_TUNE_TRAINING_PARAMS_PHYREG3VAL;
@@ -840,14 +867,22 @@
 	params.gZnodtCtrl = MV_TUNE_TRAINING_PARAMS_N_ODT_CTRL;
 
 	params.gDic = MV_TUNE_TRAINING_PARAMS_DIC;
-	params.uiODTConfig = MV_TUNE_TRAINING_PARAMS_ODT_CONFIG;
 	params.gRttNom = MV_TUNE_TRAINING_PARAMS_RTT_NOM;
-	params.gRttWR =  MV_TUNE_TRAINING_PARAMS_RTT_WR;
 
-#ifdef CONFIG_DDR4
+#ifdef CONFIG_DDR3
+	if (csNum == 1) {
+		params.gRttWR = MV_TUNE_TRAINING_PARAMS_RTT_WR_1CS;
+		params.uiODTConfig = MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS;
+	} else {
+		params.gRttWR = MV_TUNE_TRAINING_PARAMS_RTT_WR_2CS;
+		params.uiODTConfig = MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS;
+	}
+#else /* CONFIG_DDR3 */
+	/* DDR4 */
 	params.gZpodtData = MV_TUNE_TRAINING_PARAMS_P_ODT_DATA_DDR4;
 	params.uiODTConfig = MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_DDR4;
 	params.gRttNom = MV_TUNE_TRAINING_PARAMS_RTT_NOM_DDR4;
+	params.gRttWR =  MV_TUNE_TRAINING_PARAMS_RTT_WR;
 	params.gDic = MV_TUNE_TRAINING_PARAMS_DIC_DDR4;
 #endif