commit f1f68ece99f9fdf14afdf6ae4f6e1948bdbac05a
author Margarita Granov <margra@marvell.com> Sun Aug 02 18:59:31 2015 +0300
committer Greg Poist <poist@google.com> Thu Mar 24 11:59:54 2016 -0700
tree 67fda887c10167cd893f4f057935f11880f8e706
parent 2b3a0f0f839bfd3741f071fcb5c3c3ff65fc92c0

fix: ddr3libv2: bobk: WA for init frequency read from SatR.

	Read is done from Device Sample at Reset Override
	(SAR1_OVERRIDE) instead of Sample at Reset (SAR1) Status
	since read from SAR1 register returns wrong value (0).

Change-Id: I99ca1e8b365db765d37abdeafec862303f5f6c24
Signed-off-by: Margarita Granov <margra@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/22426
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24139
Tested-by: Star_Automation <star@marvell.com>

tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c

diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
index c0093d1..3ca8341 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
@@ -1449,7 +1449,9 @@
 	GT_U32 data;
 
     /* calc SAR */
-    CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, REG_DEVICE_SAR1_ADDR,  &data, MASK_ALL_BITS ));
+    CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, REG_DEVICE_SAR1_OVERRIDE_ADDR, /* in BOBK SAR should be read from REG_DEVICE_SAR1_OVERRIDE_ADDR since 
+                                                                                    read from REG_DEVICE_SAR1_ADDR register returns wrong value (0)*/
+                                           &data, MASK_ALL_BITS ));
 	mvPrintf("SAR1 is 0x%X\n", data);
     data = (data >> PLL1_CNFIG_OFFSET) & PLL1_CNFIG_MASK;