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*******************************************************************************
* ddr3_a38x_training_static.h
*
* DESCRIPTION:
*
*
* FILE REVISION NUMBER:
*       $Revision: 7 $
*
*******************************************************************************/

#ifndef __ddr3_msys_ac3_training_static_H
#define __ddr3_msys_ac3_training_static_H

#include <gtGenTypes.h>
#include <mvDdr3TrainingIpStatic.h>
#include <mvDdr3TrainingIp.h>

#ifdef __cplusplus
extern "C" {
#endif

/************************** Globals ******************************/

GT_U8 debugAc3 = 0;

/* this array hold the board round trip delay (DQ and CK) per <interfcae,bus> */
TripDelayElement Ac3BoardRoundTripDelayArray[] =
{
   /* 1st board DB + No ECC*/
   /*interface bus DQS-delay CK-delay */
   { 3486,7164 },
   { 2354,4962 },
   /* 2nd board DB + ECC*/
   /*interface bus DQS-delay CK-delay */
   { 3486,7164 },
   { 2354,4962 },
   { 3410,7754 },/*ECC PUP*/
   /* 3nd board RD + No ECC*/
   /*interface bus DQS-delay CK-delay */
   { 1230,1850 },
   { 740,1850 },
};

/* package trace */
TripDelayElement Ac3PackageRoundTripDelayArray[] =
{
     /*IF BUS DQ_DELYA CK_DELAY */
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 } ,
    {  0,    0 }
};


static GT_32 Ac3SiliconDelayOffset[] =
{
    /* board 0 */
    0,
    /* board 1 */
    0,
    /* board 2 */
    0
};


GT_STATUS ddr3TipInitAc3
(
    GT_U32  devNum,
    GT_U32  boardId
);

#ifdef __cplusplus
}
#endif

#endif /* __ddr3_msys_ac3_training_static_H */