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#ifndef _DDR3_ALP_CONFIG_H
#define _DDR3_ALP_CONFIG_H

#define DDR3_LOG_LEVEL				0
/*DDR3_LOG_LEVEL Information
Level 0: Provides an error code in a case of failure, RL, WL errors and other algorithm failure
Level 1: Provides the D-Unit setup (SPD/Static configuration)
Level 2: Provides the windows margin as a results of DQS centeralization
Level 3: Provides the windows margin of each DQ as a results of DQS centeralization */

#define DDR3_PBS					1
/*	1: Enable Per Bit Skew mechanism
	0: Disable Per Bit Skew mechanism*/

#define DDR3_RUN_SW_WHEN_HW_FAIL	1
/*	1: Enable execution of Software Write/Read leveling upon Hardware Write/Read leveling failures
	0: Disable execution of Software Write/Read leveling upon Hardware Write/Read leveling failures*/

#define DDR3_FAST_PATH_EN			1

/*	1: Open Fast-Path windows after training
	0: Open X-BAR windows after training*/

#undef STATIC_TRAINING
/*	define: Enable static training (not supported)
	undef : Enable Dynamic training*/

#define DUNIT_STATIC
/*	define: Enable static DUNIT configurations
	undef : Enable Dynamic DUNIT configuration using SPD (not supported)*/

#define DDR3_TRAINING_DEBUG			FALSE
/*	TRUE: Enable training debug sequence printing
	FALSE : Disable training debug sequence printing*/

#define REG_DIMM_SKIP_WL			FALSE
/*	TRUE: skip Write leveling stage when using registered DIMM(not supported)
	FALSE : don't skip Write leveling*/


#endif /* _DDR3_ALP_CONFIG_H */