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#ifndef _INC_A38X_DLB_CONFIG_H
#define _INC_A38X_DLB_CONFIG_H

#include "ddr3_hws_hw_training_def.h"

#ifdef CONFIG_DDR4
MV_DRAM_DLB_CONFIG ddr3DlbConfigTable[] =
{
	{REG_STATIC_DRAM_DLB_CONTROL, 	 	0x2000005F},
	{DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 	0x00880000},
	{DLB_AGING_REGISTER, 				0x3F7F007F},
	{DLB_EVICTION_CONTROL_REG, 			0x0000129F},
	{DLB_EVICTION_TIMERS_REGISTER_REG, 	0x00FF0000},
	{DLB_BUS_WEIGHTS_DIFF_CS, 			0x04030803},
	{DLB_BUS_WEIGHTS_DIFF_BG,			0x00000A02},
	{DLB_BUS_WEIGHTS_SAME_BG, 			0x08000901},
	{DLB_BUS_WEIGHTS_RD_WR,  			0x00020005},
	{DLB_BUS_WEIGHTS_ATTR_SYS_PRIO, 	0x00060F10},
	{DLB_MAIN_QUEUE_MAP,				0x00000543},
	{DLB_LINE_SPLIT, 					0x0000000F},
	{DLB_USER_COMMAND_REG,  			0x00000000},
    {0x0, 0x0}
};
#else
MV_DRAM_DLB_CONFIG ddr3DlbConfigTable[] =
{
	{REG_STATIC_DRAM_DLB_CONTROL, 		0x2000005C},
	{DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 	0x00880000},
	{DLB_AGING_REGISTER,				0x0F7F007F},
	{DLB_EVICTION_CONTROL_REG,			0x0000129F},
	{DLB_EVICTION_TIMERS_REGISTER_REG,	0x00FF0000},
	{DLB_BUS_WEIGHTS_DIFF_CS,			0x04030802},
	{DLB_BUS_WEIGHTS_DIFF_BG,			0x00000A02},
	{DLB_BUS_WEIGHTS_SAME_BG,			0x09000A01},
	{DLB_BUS_WEIGHTS_RD_WR,				0x00020005},
	{DLB_BUS_WEIGHTS_ATTR_SYS_PRIO,		0x00060F10},
	{DLB_MAIN_QUEUE_MAP,				0x00000543},
	{DLB_LINE_SPLIT,					0x00000000},
	{DLB_USER_COMMAND_REG,				0x00000000},
	{0x0, 0x0}
};
#endif

#endif /* _INC_A38X_DLB_CONFIG_H */