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*******************************************************************************/
#ifndef _DDR3_A38X_H
#define _DDR3_A38X_H

#define MAX_INTERFACE_NUM  		(1)
#define MAX_BUS_NUM        		(5)

#include "ddr3_hws_hw_training_def.h"

/*Allow topolgy update from board TWSI device*/
#if ( (!defined(CONFIG_CUSTOMER_BOARD_SUPPORT)) && defined(CONFIG_DDR3) )
/*TBD - Currentry 16Bit mode not supported in DDR4, open this define after 16Bit mode validation*/
#define MV_DDR_TOPOLOGY_UPDATE_FROM_TWSI
#endif

#define CONFIG_AVS_FROM_EFUSE /* Read pre-burnt EFUSE values, to derive requested AVS value for current chip */
#define ECC_SUPPORT

/*Controler bus divider 1 for 32 bit, 2 for 64 bit*/
#define MV_DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER		1

/*Tune internal training params values*/
#ifdef CONFIG_CLEARFOG_BOARD
	/* SolidRun Armada 38x MicroSOM has short traces on it's DDR clock.
	   using increased internal delay inside the SoC to compensate for that */
	#define MV_TUNE_TRAINING_PARAMS_CK_DELAY 	260
#else
	#define MV_TUNE_TRAINING_PARAMS_CK_DELAY 	160
#endif
#define MV_TUNE_TRAINING_PARAMS_PHYREG3VAL	0xA

#define MV_TUNE_TRAINING_PARAMS_PRI_DATA	123
#define MV_TUNE_TRAINING_PARAMS_NRI_DATA	123
#define MV_TUNE_TRAINING_PARAMS_PRI_CTRL	74
#define MV_TUNE_TRAINING_PARAMS_NRI_CTRL	74

#define MV_TUNE_TRAINING_PARAMS_P_ODT_DATA	45
#define MV_TUNE_TRAINING_PARAMS_N_ODT_DATA	45
#define MV_TUNE_TRAINING_PARAMS_P_ODT_CTRL	45
#define MV_TUNE_TRAINING_PARAMS_N_ODT_CTRL	45

#define MV_TUNE_TRAINING_PARAMS_DIC				0x2
#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS	0x120012
#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS	0x10000
#define MV_TUNE_TRAINING_PARAMS_RTT_NOM			0x44
#define MV_TUNE_TRAINING_PARAMS_RTT_WR_1CS		0x0
#define MV_TUNE_TRAINING_PARAMS_RTT_WR_2CS		0x0

#ifdef CONFIG_DDR4
#define MV_TUNE_TRAINING_PARAMS_P_ODT_DATA_DDR4	0xD
#define MV_TUNE_TRAINING_PARAMS_DIC_DDR4		0x0
#define MV_TUNE_TRAINING_PARAMS_ODT_CONFIG_DDR4	0x330012
#define MV_TUNE_TRAINING_PARAMS_RTT_NOM_DDR4	0x600 /*RZQ/3 = 0x600*/
#define MV_TUNE_TRAINING_PARAMS_RTT_WR			0x400 /*RZQ/1 = 0x400*/
#else
#define MV_TUNE_TRAINING_PARAMS_RTT_WR		0x0 /*off*/
#endif

#define MARVELL_BOARD MARVELL_BOARD_ID_BASE

#define REG_DEVICE_SAR1_ADDR                        0xE4204
#define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET         17
#define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK           0x1F

/* DRAM Windows */
#define REG_XBAR_WIN_5_CTRL_ADDR					0x20050
#define REG_XBAR_WIN_5_BASE_ADDR					0x20054

/* DRAM Windows */
#define REG_XBAR_WIN_4_CTRL_ADDR                0x20040
#define REG_XBAR_WIN_4_BASE_ADDR                0x20044
#define REG_XBAR_WIN_4_REMAP_ADDR               0x20048
#define REG_XBAR_WIN_7_REMAP_ADDR               0x20078
#define REG_XBAR_WIN_16_CTRL_ADDR               0x200d0
#define REG_XBAR_WIN_16_BASE_ADDR               0x200d4
#define REG_XBAR_WIN_16_REMAP_ADDR              0x200dc
#define REG_XBAR_WIN_19_CTRL_ADDR               0x200e8

#define REG_FASTPATH_WIN_BASE_ADDR(win)         (0x20180 + (0x8 * win))
#define REG_FASTPATH_WIN_CTRL_ADDR(win)         (0x20184 + (0x8 * win))

/*SatR defined too change topology busWidth and ECC configuration*/
#define DDR_SATR_CONFIG_MASK_WIDTH						0x8
#define DDR_SATR_CONFIG_MASK_ECC 						0x10
#define DDR_SATR_CONFIG_MASK_ECC_PUP					0x20

/********************/
/* Registers offset */
/********************/
#define	REG_SAMPLE_RESET_HIGH_ADDR				0x18600

#define MV_BOARD_REFCLK			MV_BOARD_REFCLK_25MHZ

/*Matrix enables DRAM modes(bus width/ECC) per boardId*/
#define MV_TOPOLOGY_UPDATE_32BIT			0
#define MV_TOPOLOGY_UPDATE_32BIT_ECC		1
#define MV_TOPOLOGY_UPDATE_16BIT			2
#define MV_TOPOLOGY_UPDATE_16BIT_ECC		3
#define MV_TOPOLOGY_UPDATE_16BIT_ECC_PUP3	4
/*			 32Bit,		32bit ECC,	16bit, 		16bit ECC PUP4, 16bit ECC PUP3*/
#define MV_TOPOLOGY_UPDATE  {\
/* RD_NAS_68XX_ID */	{1,		1,		1,		1,		1}, \
/* DB_68XX_ID	  */	{1,		1,		1,		1,		1}, \
/* RD_AP_68XX_ID  */	{1,		0,		1,		0,		1}, \
/* DB_AP_68XX_ID  */	{1,		0,		1,		0,		1}, \
/* DB_GP_68XX_ID  */	{1,		0,		1,		0,		1}, \
/* DB_BP_6821_ID  */	{0,		0,		1,		1,		0}, \
/* DB_AMC_6820_ID */	{1,		1,		1,		1,		1}};

/********************/
/* Registers offset */
/********************/
typedef enum
{
    CPU_1066MHz_DDR_400MHz,
    CPU_RESERVED_DDR_RESERVED0,
    CPU_667MHz_DDR_667MHz,
    CPU_800MHz_DDR_800MHz,
    CPU_RESERVED_DDR_RESERVED1,
    CPU_RESERVED_DDR_RESERVED2,
    CPU_RESERVED_DDR_RESERVED3,
    LAST_FREQ
}MSYS_DDR3_CPU_FREQ;

#define ACTIVE_INTERFACE_MASK			  0x1

#endif /* _DDR3_A38X_H */