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#ifndef _INC_A370_VARS_H
#define _INC_A370_VARS_H

#include "ddr3_a370_config.h"
#include "ddr3_a370_mc_static.h"
#include "ddr3_a370_training_static.h"

/* Board/Soc revisions define */
typedef enum  {
	A0,
	A0_PCAC,
	A0_RD,
} MV_SOC_BOARD_REV;

typedef struct __mvDramModes {
	char *mode_name;
	MV_U8 cpuFreq;
	MV_U8 fabFreq;
	MV_U8 chipId;
	MV_SOC_BOARD_REV chipBoardRev;
	MV_DRAM_MC_INIT *regs;
	MV_DRAM_TRAINING_INIT *vals;
} MV_DRAM_MODES;

MV_DRAM_MODES ddr_modes[MV_DDR3_MODES_NUMBER] =
{
	/*	Conf name			CPUFreq		FabFreq		Chip ID		Chip/Board	MC regs		Training Values */
	/* db board values: */
	{"db_1200-300-600",		0x6,		0x5,		0x0,		A0,			ddr3_A0_db_600,		ddr3_db_600	},
	{"pcac_1200-300-600",	0x6,		0x5,		0x0,		A0_PCAC,	ddr3_A0_db_600,		ddr3_pcac_600 },
	{"rd_1200-300-600",		0x6,		0x5,		0x0,		A0_RD,		ddr3_A0_rd_600,		NULL },
};

/* ODT settings - if needed update the following tables: (ODT_OPT - represents the CS configuration bitmap) */

MV_U16 auiODTStatic[ODT_OPT][MAX_CS] =
{
	{ODT60,	0,		0,		0		}, 	/* 0000 */
	{ODT40,	0,		0,		0		}, 	/* 0001 */
	{0,		0,		0,		0		}, 	/* 0010 */
	{ODT40,	0,		0,		0		}, 	/* 0011 */
	{0,		0,		0,		0		}, 	/* 0100 */
	{0,		0,		0,		0		}, 	/* 0101 */
	{0,		0,		0,		0		}, 	/* 0110 */
	{0,		0,		0,		0		}, 	/* 0111 */
	{0,		0,		0,		0		}, 	/* 1000 */
	{0,		0,		0,		0		}, 	/* 1001 */
	{0,		0,		0,		0		}, 	/* 1010 */
	{0,		0,		0,		0		}, 	/* 1011 */
	{0,		0,		0,		0		}, 	/* 1100 */
	{0,		0,		0,		0		}, 	/* 1101 */
	{0,		0,		0,		0		}, 	/* 1110 */
	{0,		0,		0,		0		}, 	/* 1111 */
};

MV_U16 auiODTDynamic[ODT_OPT][MAX_CS] =
{
	{0,		0,		0,		0		}, 	/* 0000 */
	{0,		0,		0,		0		}, 	/* 0001 */
	{0,		0,		0,		0		}, 	/* 0010 */
	{ODT120D,0,		0,		0		}, 	/* 0011 */
	{0,		0,		0,		0		}, 	/* 0100 */
	{0,		0,		0,		0		}, 	/* 0101 */
	{0,		0,		0,		0		}, 	/* 0110 */
	{0,		0,		0,		0		}, 	/* 0111 */
	{0,		0,		0,		0		}, 	/* 1000 */
	{0,		0,		0,		0		}, 	/* 1001 */
	{0,		0,		0,		0		}, 	/* 1010 */
	{0,		0,		0,		0		}, 	/* 1011 */
	{0,		0,		0,		0		}, 	/* 1100 */
	{0,		0,		0,		0		}, 	/* 1101 */
	{0,		0,		0,		0		}, 	/* 1110 */
	{0,		0,		0,		0		} 	/* 1111 */
};

MV_U32 auiODTConfig[ODT_OPT] = {
	0, 0x00010000, 0, 0x00030000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};

/*	User can manually set SPD values (in case SPD is not available on DIMM/System).
	SPD Values can simplify calculating the DUNIT registers values */
MV_U8 ucData[SPD_SIZE] =
{
	/* A370 DB Board DIMM SPD Values - manually set */
/* 2 CS */
	0x92, 0x10, 0x0B, 0x2, 0x3, 0x19, 0x0, 0x9, 0x09, 0x52, 0x1, 0x8, 0x0C, 0x0, 0x7E, 0x0, 0x69, 0x78,
/* 1 CS */
/*	0x92, 0x10, 0x0B, 0x2, 0x3, 0x19, 0x0, 0x1, 0x09, 0x52, 0x1, 0x8, 0x0C, 0x0, 0x7E, 0x0, 0x69, 0x78, */
	0x69, 0x30, 0x69, 0x11, 0x20, 0x89, 0x0, 0x5, 0x3C, 0x3C, 0x0, 0xF0, 0x82, 0x5, 0x80, 0x0, 0x0, 0x0,
	0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
	0x0, 0x0, 0x0, 0x0, 0x0F, 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
	0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
	0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
	0x0, 0x80, 0x2C, 0x1, 0x10, 0x23, 0x35, 0x28, 0xEB, 0xCA, 0x19, 0x8F
};

/*******************************************************************/
/* Controller Specific configurations Starts Here - DO NOT MODIFY  */
/*******************************************************************/

/* Frequency - values are 1/HCLK in ps */
MV_U32 s_auiCpuFabClkToHClk[FAB_OPT][CLK_CPU] =
/* CPU Frequency:
	400		533		667		800		1000	1067	1200	1333	Fabric */
{
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 3330	, 2500	, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
    {0      , 0     , 0     , 0     , 4000  , 3750  , 3000  , 3000  },
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 2500	, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
    {0      , 3750  , 3000  , 0     , 0     , 0     , 0     , 0     },
	{2500	, 0		, 0		, 3750	, 3000	, 0		, 0		, 0		}
};

MV_U32 s_auiCpuDdrRatios[FAB_OPT][CLK_CPU] =
/* CPU Frequency:
	400		533		667		800		1000	1067	1200	1333	Fabric */
{
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, DDR_333, DDR_400, 0	, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		,0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, DDR_500, DDR_533, DDR_600, DDR_666 },
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, DDR_400, 0	},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
	{0		, 0		, 0		, 0		, 0		, 0		, 0		, 0		},
    {0      , DDR_533, DDR_666, 0   , 0     , 0     , 0     , 0     },
	{DDR_400, 0		, 0		, DDR_533, DDR_666, 0	, 0		, 0		}
};

MV_U8 s_auiDivRatio1to1[CLK_VCO][CLK_DDR] =
/* DDR Frequency:
	100		333	400 533	600	666		*/
{ 	{0x4,	0,	1,	0,	0,	0	},	/*	1:1	CLK_CPU_400 = VCO  */
	{0x5,	0,	0,	1,	0,	0	},	/*	1:1	CLK_CPU_533 = VCO   */
	{0x6,	2,	0,	0,	0,	0	},	/*	1:1	CLK_CPU_667 = VCO   */
	{0x8,	0,	2,	0,	0,	0	},	/*	1:1	CLK_CPU_800 = VCO   */
	{0xA,	3,	5,	2,	0,	0	},	/*	1:1	CLK_CPU_1000 = VCO   */
	{0xA,	0,	0,	2,	0,	0	},	/*	1:1	CLK_CPU_1067 = VCO   */
	{0xC,	0,	6,	0,	2,	0	},	/*	1:1	CLK_CPU_1200 = VCO   */
	{0xD,	0,	0,	0,	0,	2	},	/*	1:1	CLK_CPU_1333 = VCO   */
	{0x8,	0,	0,	0,	0,	0	},	/*	1:1	CLK_CPU_400 VCO_800  */
	{0xA,	0,	0,	0,	0,	0	},	/*	1:1	CLK_CPU_533 VCO_1066 */
	{0xC,	0,	0,	0,	0,	0	},	/*	1:1	CLK_CPU_667 VCO_1333 */
	{0x10,	0,	0,	0,	0,	0	},	/*	1:1	CLK_CPU_800 VCO_1600 */
	{0x14,	0,	0,	0,	0,	0	},	/*	1:1	CLK_CPU_1000 VCO_2000  */
	{0x15,	0,	0,	0,	0,	0	},	/*	1:1	CLK_CPU_1067 VCO_2133 */
	{0x18,	0,	6,	0,	0,	0	},	/*	1:1	CLK_CPU_1200 VCO_2400 */
	{0x1A,	0,	0,	0,	0,	0	}	/*	1:1	CLK_CPU_1333 VCO_2666 */
};

MV_U8 s_auiDivRatio2to1[CLK_VCO][CLK_DDR] =
/* DDR Frequency:
	100		333	400	533	600	666		*/
{ 	{0,		0,	0,	0,	0,	0	},	/*	2:1	CLK_CPU_400 = VCO  */
	{0,		0,	0,	1,	0,	0	},	/*	2:1	CLK_CPU_533 = VCO  */
    {0,     2,  0,  0,  0,  1   },  /*  2:1 CLK_CPU_667 = VCO  */
	{0,		0,	2,	3,	0,	0	},	/*	2:1	CLK_CPU_800 = VCO  */
	{0,		0,	5,	2,	0,	0	},	/*	2:1	CLK_CPU_1000 = VCO  */
	{0,		0,	0,	2,	0,	5	},	/*	2:1	CLK_CPU_1067 = VCO  */
	{0,		0,	3,	0,	2,	0	},	/*	2:1	CLK_CPU_1200 = VCO  */
	{0,		0,	0,	5,	0,	2	},	/*	2:1	CLK_CPU_1333 = VCO  */
	{0,		0,	0,	0,	0,	0	},	/*	2:1	CLK_CPU_400 VCO_800  */
	{0,		0,	0,	0,	0,	0	},	/*	2:1	CLK_CPU_533 VCO_1066 */
	{0,		0,	0,	0,	0,	0	},	/*	2:1	CLK_CPU_667 VCO_1333 */
	{0,		0,	0,	3,	0,	0	},	/*	2:1	CLK_CPU_800 VCO_1600 */
	{0,		0,	0,	0,	0,	3	},	/*	2:1	CLK_CPU_1000 VCO_2000  */
	{0,		0,	0,	0,	0,	0	},	/*	2:1	CLK_CPU_1067 VCO_2133 */
	{0,		0,	6,	0,	0,	0	},	/*	2:1	CLK_CPU_1200 VCO_2400 */
	{0,		0,	0,	0,	0,	0	}	/*	2:1	CLK_CPU_1333 VCO_2666 */
};

#endif /* _INC_A370_VARS_H */