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*******************************************************************************/

/*******************************************************************************
* mvXor.h - Header File for :
*
* DESCRIPTION:
*       This file contains Marvell Controller XOR HW library API.
*       NOTE: This HW library API assumes XOR source, destination and
*       descriptors are cache coherent.
*
* DEPENDENCIES:
*       None.
*
*******************************************************************************/

#ifndef __INCMVxorh
#define __INCMVxorh

#ifdef __cplusplus
extern "C" {
#endif

#include "mvCommon.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "mvSysXorConfig.h"

/* typedefs */

/* This enumerator describes the type of functionality the XOR channel      */
/* can have while using the same data structures.                           */
	typedef enum _mvXorType {
		MV_XOR,		/* XOR channel functions as XOR accelerator     */
		MV_DMA,		/* XOR channel functions as IDMA channel        */
		MV_CRC32	/* XOR channel functions as CRC 32 calculator   */
	} MV_XOR_TYPE;

	typedef enum _mvXorBurstLinit {
		MV_XOR_BURST_LIMIT_32_BYTES  = 0x2,
		MV_XOR_BURST_LIMIT_64_BYTES  = 0x3,
		MV_XOR_BURST_LIMIT_128_BYTES = 0x4
	} MV_XOR_BURST_LIMIT;

#if defined(MV_CPU_LE)
	/* This structure describes XOR descriptor size 64bytes                     */
	typedef struct _mvXorDesc {
		MV_U32 status;	/* Successful descriptor execution indication */
		MV_U32 crc32Result;	/* Result of CRC-32 calculation */
		MV_U32 descCommand;	/* type of operation to be carried out on the data */
		MV_U32 phyNextDescPtr;	/* Next descriptor address pointer */
		MV_U32 byteCnt;	/* Size of source and destination blocks in bytes */
		MV_U32 phyDestAdd;	/* Destination Block address pointer */
		MV_U32 srcAdd0;	/* source block #0 address pointer */
		MV_U32 srcAdd1;	/* source block #1 address pointer */
		MV_U32 srcAdd2;	/* source block #2 address pointer */
		MV_U32 srcAdd3;	/* source block #3 address pointer */
		MV_U32 srcAdd4;	/* source block #4 address pointer */
		MV_U32 srcAdd5;	/* source block #6 address pointer */
		MV_U32 srcAdd6;	/* source block #6 address pointer */
		MV_U32 srcAdd7;	/* source block #7 address pointer */
		MV_U32 reserved0;
		MV_U32 reserved1;
	} MV_XOR_DESC;

/* XOR descriptor structure for CRC and DMA descriptor */
	typedef struct _mvCrcDmaDesc {
		MV_U32 status;	/* Successful descriptor execution indication */
		MV_U32 crc32Result;	/* Result of CRC-32 calculation */
		MV_U32 descCommand;	/* type of operation to be carried out on the data */
		MV_U32 nextDescPtr;	/* Next descriptor address pointer */
		MV_U32 byteCnt;	/* Size of source block part represented by the descriptor */
		MV_U32 destAdd;	/* Destination Block address pointer (not used in CRC32 */
		MV_U32 srcAdd0;	/* Mode: Source Block address pointer */
		MV_U32 srcAdd1;	/* Mode: Source Block address pointer */
	} MV_CRC_DMA_DESC;

#elif defined(MV_CPU_BE)
/* This structure describes XOR descriptor size 64bytes                     */
	typedef struct _mvXorDesc {
		MV_U32 crc32Result;	/* Result of CRC-32 calculation */
		MV_U32 status;	/* Successful descriptor execution indication */
		MV_U32 phyNextDescPtr;	/* Next descriptor address pointer */
		MV_U32 descCommand;	/* type of operation to be carried out on the data */
		MV_U32 phyDestAdd;	/* Destination Block address pointer */
		MV_U32 byteCnt;	/* Size of source and destination blocks in bytes */
		MV_U32 srcAdd1;	/* source block #1 address pointer */
		MV_U32 srcAdd0;	/* source block #0 address pointer */
		MV_U32 srcAdd3;	/* source block #3 address pointer */
		MV_U32 srcAdd2;	/* source block #2 address pointer */
		MV_U32 srcAdd5;	/* source block #5 address pointer */
		MV_U32 srcAdd4;	/* source block #4 address pointer */
		MV_U32 srcAdd7;	/* source block #7 address pointer */
		MV_U32 srcAdd6;	/* source block #6 address pointer */
		MV_U32 reserved0;
		MV_U32 reserved1;
	} MV_XOR_DESC;

/* XOR descriptor structure for CRC and DMA descriptor */
	typedef struct _mvCrcDmaDesc {
		MV_U32 crc32Result;	/* Result of CRC-32 calculation */
		MV_U32 status;	/* Successful descriptor execution indication */
		MV_U32 nextDescPtr;	/* Next descriptor address pointer */
		MV_U32 descCommand;	/* type of operation to be carried out on the data */
		MV_U32 destAdd;	/* Destination Block address pointer (not used in CRC32 */
		MV_U32 byteCnt;	/* Size of source block part represented by the descriptor */
		MV_U32 srcAdd1;	/* Mode: Source Block address pointer */
		MV_U32 srcAdd0;	/* Mode: Source Block address pointer */
	} MV_CRC_DMA_DESC;

#endif

#define MV_XOR_DESC_ALIGNMENT       sizeof(MV_XOR_DESC)
	typedef struct _mvXorEcc {
		MV_U32 destPtr;	/* Target block pointer to ECC/MemInit operation */
		MV_U32 blockSize;	/* Block size in bytes for ECC/MemInit operation */
		MV_BOOL periodicEnable;	/* Enable Timer Mode                                                         */
		MV_U32 tClkTicks;	/* ECC timer mode initial count - down value     */
		MV_U32 sectorSize;	/* section size for ECC timer mode operation     */
	} MV_XOR_ECC;

	typedef enum _mvXorOverrideTarget {
		SRC_ADDR0,	/* Source Address #0 Control */
		SRC_ADDR1,	/* Source Address #1 Control */
		SRC_ADDR2,	/* Source Address #2 Control */
		SRC_ADDR3,	/* Source Address #3 Control */
		SRC_ADDR4,	/* Source Address #4 Control */
		SRC_ADDR5,	/* Source Address #5 Control */
		SRC_ADDR6,	/* Source Address #6 Control */
		SRC_ADDR7,	/* Source Address #7 Control */
		XOR_DST_ADDR,	/* Destination Address Control */
		XOR_NEXT_DESC	/* Next Descriptor Address Control */
	} MV_XOR_OVERRIDE_TARGET;

	MV_VOID mvXorHalInit(MV_U32 unit);
	MV_STATUS mvXorCtrlSet(MV_U32 chan, MV_U32 xorCtrl);
	MV_STATUS mvXorEccClean(MV_U32 chan, MV_XOR_ECC *pXorEccConfig);
	MV_U32 mvXorEccCurrTimerGet(MV_U32 chan, MV_U32 tClk);
	MV_STATUS mvXorMemInit(MV_U32 chan, MV_U32 startPtr, MV_U32 blockSize, MV_U32 initValHigh, MV_U32 initValLow);
	MV_STATUS mvXorTransfer(MV_U32 chan, MV_XOR_TYPE xorType, MV_U32 xorChainPtr);
	MV_STATE mvXorStateGet(MV_U32 chan);
	MV_STATUS mvXorCommandSet(MV_U32 chan, MV_COMMAND command);
	MV_STATUS mvXorOverrideSet(MV_U32 chan, MV_XOR_OVERRIDE_TARGET target, MV_U32 winNum, MV_BOOL enable);
	MV_VOID xorSetSrcBurstLimit(MV_U32 chan, MV_XOR_BURST_LIMIT srcBurstLimit);
	MV_VOID mvXorOverrideDisable(MV_U32 chan);

	MV_STATUS mvXorWinInit(MV_UNIT_WIN_INFO *addrWinMap);
	MV_STATUS mvXorTargetWinWrite(MV_U32 unit, MV_U32 winNum,
					MV_UNIT_WIN_INFO *pAddrDecWin);
	MV_STATUS mvXorTargetWinRead(MV_U32 unit, MV_U32 winNum,
					MV_UNIT_WIN_INFO *pAddrDecWin);
	MV_STATUS mvXorTargetWinEnable(MV_U32 unit, MV_U32 winNum, MV_BOOL enable);
	MV_STATUS mvXorProtWinSet(MV_U32 unit, MV_U32 chan, MV_U32 winNum, MV_BOOL access, MV_BOOL write);
	MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh);

#ifdef __cplusplus
}
#endif
#endif