ddr3libv2: Added Leveling Sweep tests and additional patterns
The patterns also may be used for centralization diagnostic run
Change-Id: I1709d75191b9556652d59d28ef64ab421c2eaf79
Signed-off-by: Igor Patrik <igorp@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/19656
Reviewed-on: http://vgitil04.il.marvell.com:8080/24131
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpBist.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpBist.h
index f3d5ffa..db5c8ac 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpBist.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpBist.h
@@ -158,6 +158,13 @@
GT_U32 mode
);
+GT_BOOL ddr3TipRunLevelingSweepTest
+(
+ GT_32 devNum,
+ GT_U32 RepeatNum,
+ GT_U32 direction,
+ GT_U32 mode
+);
/******************************************************************************
* Name: ddr3TipPrintRegs.
* Desc: Print Specified Dunit/Pup Registers
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h
index e2ba6e1..dd7860a 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h
@@ -51,7 +51,10 @@
{
PATTERN_PBS1,
PATTERN_PBS2,
+ PATTERN_PBS3,
+ PATTERN_TEST,
PATTERN_RL,
+ PATTERN_RL2,
PATTERN_STATIC_PBS,
PATTERN_KILLER_DQ0,
PATTERN_KILLER_DQ1,
@@ -61,27 +64,44 @@
PATTERN_KILLER_DQ5,
PATTERN_KILLER_DQ6,
PATTERN_KILLER_DQ7,
- PATTERN_PBS3,
- PATTERN_RL2,
- PATTERN_TEST,
+ PATTERN_VREF,
PATTERN_FULL_SSO0,
PATTERN_FULL_SSO1,
PATTERN_FULL_SSO2,
PATTERN_FULL_SSO3,
- PATTERN_VREF,
+ PATTERN_SSO_FULL_XTALK_DQ0,
+ PATTERN_SSO_FULL_XTALK_DQ1,
+ PATTERN_SSO_FULL_XTALK_DQ2,
+ PATTERN_SSO_FULL_XTALK_DQ3,
+ PATTERN_SSO_FULL_XTALK_DQ4,
+ PATTERN_SSO_FULL_XTALK_DQ5,
+ PATTERN_SSO_FULL_XTALK_DQ6,
+ PATTERN_SSO_FULL_XTALK_DQ7,
+ PATTERN_SSO_XTALK_FREE_DQ0,
+ PATTERN_SSO_XTALK_FREE_DQ1,
+ PATTERN_SSO_XTALK_FREE_DQ2,
+ PATTERN_SSO_XTALK_FREE_DQ3,
+ PATTERN_SSO_XTALK_FREE_DQ4,
+ PATTERN_SSO_XTALK_FREE_DQ5,
+ PATTERN_SSO_XTALK_FREE_DQ6,
+ PATTERN_SSO_XTALK_FREE_DQ7,
+ PATTERN_ISI_XTALK_FREE,
PATTERN_LIMIT
} MV_HWS_PATTERN;
#elif defined(CONFIG_DDR4)
-typedef enum
+typedef enum
{
- PATTERN_PBS1,
+ PATTERN_PBS1,/*0*/
PATTERN_PBS2,
+ PATTERN_PBS3,
+ PATTERN_TEST,
PATTERN_RL,
+ PATTERN_RL2,
PATTERN_STATIC_PBS,
PATTERN_KILLER_DQ0,
PATTERN_KILLER_DQ1,
PATTERN_KILLER_DQ2,
- PATTERN_KILLER_DQ3,
+ PATTERN_KILLER_DQ3,/*10*/
PATTERN_KILLER_DQ4,
PATTERN_KILLER_DQ5,
PATTERN_KILLER_DQ6,
@@ -91,27 +111,41 @@
PATTERN_KILLER_DQ2_INV,
PATTERN_KILLER_DQ3_INV,
PATTERN_KILLER_DQ4_INV,
- PATTERN_KILLER_DQ5_INV,
+ PATTERN_KILLER_DQ5_INV,/*20*/
PATTERN_KILLER_DQ6_INV,
PATTERN_KILLER_DQ7_INV,
PATTERN_VREF,
PATTERN_VREF_INV,
- PATTERN_RESONANCE_1T,
- PATTERN_RESONANCE_2T,
- PATTERN_RESONANCE_3T,
- PATTERN_RESONANCE_4T,
- PATTERN_RESONANCE_5T,
- PATTERN_RESONANCE_6T,
- PATTERN_RESONANCE_7T,
- PATTERN_RESONANCE_8T,
- PATTERN_RESONANCE_9T,
- PATTERN_PBS3,
- PATTERN_RL2,
- PATTERN_TEST,
PATTERN_FULL_SSO0,
PATTERN_FULL_SSO1,
PATTERN_FULL_SSO2,
PATTERN_FULL_SSO3,
+ PATTERN_SSO_FULL_XTALK_DQ0,
+ PATTERN_SSO_FULL_XTALK_DQ1,/*30*/
+ PATTERN_SSO_FULL_XTALK_DQ2,
+ PATTERN_SSO_FULL_XTALK_DQ3,
+ PATTERN_SSO_FULL_XTALK_DQ4,
+ PATTERN_SSO_FULL_XTALK_DQ5,
+ PATTERN_SSO_FULL_XTALK_DQ6,
+ PATTERN_SSO_FULL_XTALK_DQ7,
+ PATTERN_SSO_XTALK_FREE_DQ0,
+ PATTERN_SSO_XTALK_FREE_DQ1,
+ PATTERN_SSO_XTALK_FREE_DQ2,
+ PATTERN_SSO_XTALK_FREE_DQ3,/*40*/
+ PATTERN_SSO_XTALK_FREE_DQ4,
+ PATTERN_SSO_XTALK_FREE_DQ5,
+ PATTERN_SSO_XTALK_FREE_DQ6,
+ PATTERN_SSO_XTALK_FREE_DQ7,
+ PATTERN_ISI_XTALK_FREE,
+ PATTERN_RESONANCE_1T,
+ PATTERN_RESONANCE_2T,
+ PATTERN_RESONANCE_3T,
+ PATTERN_RESONANCE_4T,
+ PATTERN_RESONANCE_5T,/*50*/
+ PATTERN_RESONANCE_6T,
+ PATTERN_RESONANCE_7T,
+ PATTERN_RESONANCE_8T,
+ PATTERN_RESONANCE_9T,
PATTERN_LIMIT
}MV_HWS_PATTERN;
#else
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
index 96017b1..2df6c86 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
@@ -34,11 +34,16 @@
#ifdef DDR_VIEWER_TOOL
GT_STATUS printAdll(GT_U32 devNum, GT_U32 adll[MAX_INTERFACE_NUM*MAX_BUS_NUM]);
+GT_STATUS printPh(GT_U32 devNum, GT_U32 adll[MAX_INTERFACE_NUM*MAX_BUS_NUM]);
+
+GT_U8 sweepPatternIndexStart = PATTERN_KILLER_DQ0, sweepPatternIndexEnd = PATTERN_LIMIT;
static char* ConvertFreq(MV_HWS_DDR_FREQ freq);
#if defined(EXCLUDE_SWITCH_DEBUG)
extern MV_HWS_PATTERN sweepPattern;
GT_U32 ctrlSweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM];
GT_U32 ctrlADLL[MAX_CS_NUM*MAX_INTERFACE_NUM*MAX_BUS_NUM];
+GT_U32 ctrlADLL1[MAX_CS_NUM*MAX_INTERFACE_NUM*MAX_BUS_NUM];
+GT_U32 ctrlLevelPhase[MAX_CS_NUM*MAX_INTERFACE_NUM*MAX_BUS_NUM];
#endif
#endif
@@ -153,7 +158,7 @@
extern GT_U32 maskTuneFunc;
extern GT_U32 freqVal[];
MV_HWS_TIP_CONFIG_FUNC_DB configFuncInfo[HWS_MAX_DEVICE_NUM];
-GT_U8 isDefaultCentralization = 0 , isTuneResult = 0, isValidateWindowPerIf = 0, isValidateWindowPerPup = 0, sweepCnt = 1, isBistResetBit = 1;
+GT_U8 isDefaultCentralization = 0 , isTuneResult = 0, isValidateWindowPerIf = 0, isValidateWindowPerPup = 0, sweepCnt = 1, isBistResetBit = 1, isRunLevelingSweepTests = 0;
static MV_HWS_XSB_INFO xsbInfo[HWS_MAX_DEVICE_NUM];
@@ -436,17 +441,22 @@
freq = topologyMap->interfaceParams[firstActiveIf].memoryFreq;
isPupLog = (isValidateWindowPerPup != 0) ? 1:0;
- mvPrintf("===VALIDATE WINDOW LOG START===\n");
- mvPrintf("DDR Frequency: %s ======\n",ConvertFreq(freq));
+ mvPrintf("===VALIDATE WINDOW LOG START===\n");
+ mvPrintf("DDR Frequency: %s ======\n",ConvertFreq(freq));
/* print sweep windows */
ddr3TipRunSweepTest(devNum, sweepCnt, 1 , isPupLog);
ddr3TipRunSweepTest(devNum, sweepCnt, 0 , isPupLog);
- ddr3TipPrintAllPbsResult(devNum);
- ddr3TipPrintWLSuppResult(devNum);
- mvPrintf("===VALIDATE WINDOW LOG END ===\n");
- CHECK_STATUS(ddr3TipRestoreDunitRegs(devNum));
- ddr3TipRegDump(devNum);
+ if( isRunLevelingSweepTests == 1 ){
+ ddr3TipRunLevelingSweepTest(devNum, sweepCnt, 0 , isPupLog);
+ ddr3TipRunLevelingSweepTest(devNum, sweepCnt, 1 , isPupLog);
+ }
+
+ ddr3TipPrintAllPbsResult(devNum);
+ ddr3TipPrintWLSuppResult(devNum);
+ mvPrintf("===VALIDATE WINDOW LOG END ===\n");
+ CHECK_STATUS(ddr3TipRestoreDunitRegs(devNum));
+ ddr3TipRegDump(devNum);
}
#endif
@@ -750,6 +760,57 @@
return 0;
}
+
+/*****************************************************************************
+Read Phase Value
+******************************************************************************/
+GT_BOOL readPhaseValue(GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], int regAddr, GT_U32 mask)
+{
+ GT_U32 dataValue;
+ GT_U32 interfaceId = 0, busId = 0;
+ GT_U32 devNum = 0;
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+
+ /* multi CS support - regAddr is calucalated in calling function with CS offset */
+ for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
+ {
+ VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
+ for(busId = 0 ; busId < octetsPerInterfaceNum ; busId++)
+ {
+ VALIDATE_BUS_ACTIVE(topologyMap->activeBusMask, busId)
+ CHECK_STATUS(mvHwsDdr3TipBUSRead( devNum, interfaceId, ACCESS_TYPE_UNICAST, busId, DDR_PHY_DATA, regAddr, &dataValue));
+ PupValues[interfaceId*octetsPerInterfaceNum + busId] = dataValue & mask;
+ }
+ }
+
+ return 0;
+}
+
+/*****************************************************************************
+Write Leveling Value
+******************************************************************************/
+GT_BOOL writeLevelingValue(GT_U32 PupValues[MAX_INTERFACE_NUM*MAX_BUS_NUM], GT_U32 PupPhValues[MAX_INTERFACE_NUM*MAX_BUS_NUM],int regAddr)
+{
+ GT_U32 interfaceId = 0, busId = 0;
+ GT_U32 devNum = 0, data;
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+
+ /* multi CS support - regAddr is calucalated in calling function with CS offset */
+
+ for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
+ {
+ VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
+ for(busId = 0 ; busId < octetsPerInterfaceNum ; busId++)
+ {
+ VALIDATE_BUS_ACTIVE(topologyMap->activeBusMask, busId)
+ data = PupValues[interfaceId*octetsPerInterfaceNum+busId] + (PupPhValues[interfaceId*octetsPerInterfaceNum+busId]);
+ CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_UNICAST, interfaceId, ACCESS_TYPE_UNICAST, busId, DDR_PHY_DATA, regAddr, data));
+ }
+
+ }
+ return 0;
+}
+
#ifndef EXCLUDE_SWITCH_DEBUG
extern MV_HWS_DDR_FREQ initFreq;
extern MV_HWS_DDR_FREQ lowFreq;
@@ -1300,6 +1361,25 @@
mvPrintf("\n");
return GT_OK;
}
+GT_STATUS printPh(GT_U32 devNum, GT_U32 adll[MAX_INTERFACE_NUM*MAX_BUS_NUM])
+{
+ GT_U32 i,j;
+ GT_U32 octetsPerInterfaceNum;
+
+ devNum = devNum;
+ octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+
+ for(j=0; j< octetsPerInterfaceNum; j++)
+ {
+ VALIDATE_BUS_ACTIVE(topologyMap->activeBusMask, j)
+ for(i=0;i<MAX_INTERFACE_NUM; i++)
+ {
+ mvPrintf("%d ,",adll[i*octetsPerInterfaceNum+j]>>6);
+ }
+ }
+ mvPrintf("\n");
+ return GT_OK;
+}
#endif
#ifndef EXCLUDE_SWITCH_DEBUG
@@ -1336,65 +1416,6 @@
}
-/*******************************************************/
-/* uiTestType = 0-tx , 1 - rx */
-GT_STATUS ddr3TipSweepTest(GT_U32 devNum, GT_U32 uiTestType, GT_U32 uiMemAddress, GT_U32 isModifyAdll, GT_U32 startIf, GT_U32 endIf, GT_U32 startpup, GT_U32 endpup)
-{
- GT_U32 busCnt = 0, adllVal = 0, interfaceId, uiPrevAdll, uiMaskBit, end_adll, start_adll;
- GT_U32 regAddr = 0, iter = 0;
-
- uiMemAddress = uiMemAddress;
-
- if (uiTestType == 0)
- {
- regAddr = 1;
- uiMaskBit = 0x3f;
- start_adll = 0;
- end_adll = uiMaskBit;
- }
- else
- {
- regAddr = 3;
- uiMaskBit = 0x1f;
- start_adll = 0;
- end_adll = uiMaskBit;
- }
- DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("==============================\n"));
- DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("Test type %d (0-tx, 1-rx) \n",uiTestType));
-
- for(interfaceId = startIf; interfaceId <= endIf; interfaceId++)
- {
- VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
- for(busCnt = startpup; busCnt < endpup; busCnt++)
- {
-
- CHECK_STATUS(mvHwsDdr3TipBUSRead( devNum, interfaceId, ACCESS_TYPE_UNICAST, busCnt, DDR_PHY_DATA, regAddr, &uiPrevAdll));
-
- for(adllVal = start_adll; adllVal <= end_adll; adllVal++)
- {
- if (isModifyAdll == 1)
- {
- CHECK_STATUS(ddr3TipBusReadModifyWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, busCnt, DDR_PHY_DATA, regAddr, adllVal, uiMaskBit));
- }
- for(iter = 0; iter <= debugSweepVal; iter++)
- {
- /*XsbRWTest(devNum, interfaceId, uiMemAddress, testPattern, busCnt, 0);
- CHECK_STATUS(ddr3TipExtWrite(devNum, interfaceId, uiMemAddress, 1, xsbTestTable[seq]));
- CHECK_STATUS(ddr3TipExtRead( devNum, interfaceId, uiMemAddress, 1, dataRead));
- retTmp = ddr3TipCompare(interfaceId, xsbTestTable[seq], dataRead, 0xff);*/
- }
- }
- if (isModifyAdll == 1)
- {
- CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_UNICAST, interfaceId, ACCESS_TYPE_UNICAST, busCnt, DDR_PHY_DATA, regAddr, uiPrevAdll));
- }
- DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("\n"));
- }
- DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("\n"));
- }
-
- return GT_OK;
-}
#endif /* EXCLUDE_SWITCH_DEBUG*/
#if defined(DDR_VIEWER_TOOL)
/*****************************************************************************
@@ -1403,7 +1424,7 @@
GT_BOOL ddr3TipRunSweepTest(GT_32 devNum, GT_U32 RepeatNum, GT_U32 direction, GT_U32 mode)
{
GT_U32 pup = 0, startPup = 0, endPup = 0;
- GT_U32 adll = 0;
+ GT_U32 adll = 0,rep = 0,sweepPatternIndex = 0;
GT_U32 res[MAX_INTERFACE_NUM] = {0};
GT_32 interfaceId = 0;
GT_U32 adllValue = 0;
@@ -1411,10 +1432,10 @@
MV_HWS_ACCESS_TYPE pupAccess;
GT_U32 uiCs;
GT_U32 maxCs = mvHwsDdr3TipMaxCSGet();
- GT_U32 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
RepeatNum = RepeatNum;
-
+ RepeatNum = 2;
if ( mode == 1)
{
/* per pup */
@@ -1434,7 +1455,7 @@
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
- for( pup = startPup ;pup <= endPup ; pup++)
+ for( pup = startPup ;pup <= endPup ; pup++)
{
ctrlSweepres[adll][interfaceId][pup] = 0;
}
@@ -1453,22 +1474,28 @@
{
for(adll = 0 ; adll < ADLL_LENGTH ; adll++)
{
- adllValue = (direction == 0) ? (adll*2):adll;
- CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_MULTICAST, 0, pupAccess, pup, DDR_PHY_DATA, reg + CS_BYTE_GAP(uiCs), adllValue));
- mvHwsDdr3RunBist(devNum, sweepPattern, res ,uiCs);
- /*ddr3TipResetFifoPtr(devNum);*/
- for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
+ for(rep = 0; rep < RepeatNum ; rep++)
{
- VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
- ctrlSweepres[adll][interfaceId][pup] = res[interfaceId];
- if (mode == 1)
+ for(sweepPatternIndex = sweepPatternIndexStart ; sweepPatternIndex < sweepPatternIndexEnd ; sweepPatternIndex++)
{
- CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_UNICAST, interfaceId, ACCESS_TYPE_UNICAST, pup, DDR_PHY_DATA, reg + CS_BYTE_GAP(uiCs), ctrlADLL[interfaceId*uiCs*octetsPerInterfaceNum+pup]));
+ adllValue = (direction == 0) ? (adll*2):adll;
+ CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_MULTICAST, 0, pupAccess, pup, DDR_PHY_DATA, reg + CS_BYTE_GAP(uiCs), adllValue));
+ mvHwsDdr3RunBist(devNum, sweepPattern, res ,uiCs);
+ /*ddr3TipResetFifoPtr(devNum);*/
+ for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
+ {
+ VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
+ ctrlSweepres[adll][interfaceId][pup] += res[interfaceId];
+ if (mode == 1)
+ {
+ CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_UNICAST, interfaceId, ACCESS_TYPE_UNICAST, pup, DDR_PHY_DATA, reg + CS_BYTE_GAP(uiCs), ctrlADLL[interfaceId*uiCs*octetsPerInterfaceNum+pup]));
+ }
+ }
}
}
}
}
- mvPrintf("Final,CS %d,%s,Sweep Result,Adll,", uiCs,((direction==0) ? "TX":"RX"));
+ mvPrintf("Final,CS %d,%s,Sweep,Result,Adll,", uiCs,((direction==0) ? "TX":"RX"));
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
@@ -1489,13 +1516,13 @@
for(adll = 0 ; adll < ADLL_LENGTH ; adll++)
{
adllValue = (direction == 0) ? (adll*2):adll;
- mvPrintf("Final,%s,Sweep Result, %d ,",((direction==0) ? "TX":"RX"),adllValue);
+ mvPrintf("Final,%s,Sweep,Result, %d ,",((direction==0) ? "TX":"RX"),adllValue);
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++){
VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
for( pup=startPup; pup <=endPup; pup++)
{
- mvPrintf("%d , ",ctrlSweepres[adll][interfaceId][pup]);
+ mvPrintf("%8d , ",ctrlSweepres[adll][interfaceId][pup]);
}
}
mvPrintf("\n");
@@ -1512,6 +1539,178 @@
}
+GT_BOOL ddr3TipRunLevelingSweepTest(GT_32 devNum, GT_U32 RepeatNum, GT_U32 direction, GT_U32 mode)
+{
+ GT_U32 pup = 0, startPup = 0, endPup = 0, startAdll = 0;
+ GT_U32 adll = 0,rep = 0,sweepPatternIndex = 0;
+ GT_U32 readData[MAX_INTERFACE_NUM];
+ GT_U32 res[MAX_INTERFACE_NUM] = {0};
+ GT_32 interfaceId = 0,gap = 0;
+ GT_32 adllValue = 0;
+ GT_32 reg = (direction == 0) ? WL_PHY_REG : RL_PHY_REG;
+ MV_HWS_ACCESS_TYPE pupAccess;
+ GT_U32 uiCs;
+ GT_U32 maxCs = mvHwsDdr3TipMaxCSGet();
+ GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ RepeatNum = RepeatNum;
+ RepeatNum = 3;
+ if ( mode == 1)
+ {
+ /* per pup */
+ startPup = 0;
+ endPup = octetsPerInterfaceNum-1;
+ pupAccess = ACCESS_TYPE_UNICAST;
+ }
+ else
+ {
+ startPup = 0;
+ endPup = 0;
+ pupAccess = ACCESS_TYPE_MULTICAST;
+ }
+ for(uiCs=0; uiCs < maxCs; uiCs++){
+ for(adll = 0 ; adll < ADLL_LENGTH ; adll++)
+ {
+ for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
+ {
+ VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
+ for( pup = startPup ;pup <= endPup ; pup++)
+ {
+ ctrlSweepres[adll][interfaceId][pup] = 0;
+ }
+ }
+ }
+
+ for(adll = 0 ; adll < (MAX_INTERFACE_NUM * MAX_BUS_NUM) ; adll++)
+ {
+ ctrlADLL[adll] = 0;
+ ctrlLevelPhase[adll] = 0;
+ ctrlADLL1[adll] = 0;
+ }
+ /*Save Leveling value(after algorithm run)*/
+ readAdllValue(ctrlADLL, (reg + (uiCs * CS_REGISTER_ADDR_OFFSET)) , 0x1F );
+ readPhaseValue(ctrlLevelPhase, (reg + (uiCs * CS_REGISTER_ADDR_OFFSET)) , 0x3<<6 );
+ if(direction == 0)
+ {
+ readAdllValue(ctrlADLL1, (0x1 + (uiCs * CS_REGISTER_ADDR_OFFSET)) , MASK_ALL_BITS );
+ }
+ /*Sweep ADLL from 0:31 on all I/F on all Pup and perform BIST on each stage.*/
+ for(pup=startPup; pup <=endPup; pup++)
+ {
+ for(adll = 0 ; adll < ADLL_LENGTH ; adll++)
+ {
+ for(rep = 0; rep < RepeatNum ; rep++)
+ {
+ adllValue = (direction == 0) ? (adll*2):(adll*3);
+ for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
+ {
+ startAdll = ctrlADLL[interfaceId*uiCs*octetsPerInterfaceNum+pup] + (ctrlLevelPhase[interfaceId*uiCs*octetsPerInterfaceNum+pup]>>6)*32 ;
+ if(direction == 0)
+ {
+ startAdll = (startAdll>32)?(startAdll-32):0;
+ }else
+ {
+ startAdll = (startAdll>48)?(startAdll-48):0;
+ }
+ if(direction == 0)
+ {
+ adllValue = startAdll + adllValue;
+ }else
+ {
+ adllValue = startAdll + adllValue;
+ }
+ gap = ctrlADLL1[interfaceId*uiCs*octetsPerInterfaceNum+pup] - ctrlADLL[interfaceId*uiCs*octetsPerInterfaceNum+pup];
+ gap = (((adllValue%32) + gap)%64);
+ adllValue = ((adllValue%32) + (((adllValue- (adllValue%32))/32)<<6));
+
+ CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_UNICAST, interfaceId, pupAccess, pup, DDR_PHY_DATA, reg + CS_BYTE_GAP(uiCs), adllValue));
+ if(direction == 0)
+ {
+ CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_UNICAST, interfaceId, pupAccess, pup, DDR_PHY_DATA, 0x1 + CS_BYTE_GAP(uiCs), gap));
+ }
+ }
+ for(sweepPatternIndex = sweepPatternIndexStart ; sweepPatternIndex < sweepPatternIndexEnd ; sweepPatternIndex++)
+ {
+ mvHwsDdr3RunBist(devNum, sweepPattern, res ,uiCs);
+ ddr3TipResetFifoPtr(devNum);
+ for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
+ {
+ VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
+ if(pup != 4)
+ {
+ ctrlSweepres[adll][interfaceId][pup] += res[interfaceId];
+ }else
+ {
+ CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0x1458, readData, MASK_ALL_BITS));
+ ctrlSweepres[adll][interfaceId][pup] += readData[interfaceId];
+
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0x1458, 0x0 , 0xFFFFFFFF));
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0x145C, 0x0 , 0xFFFFFFFF));
+ }
+ }
+ }
+ }
+ }
+ for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
+ {
+ startAdll = ctrlADLL[interfaceId*uiCs*octetsPerInterfaceNum+pup] + ctrlLevelPhase[interfaceId*uiCs*octetsPerInterfaceNum+pup] ;
+ CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_UNICAST, interfaceId, pupAccess, pup, DDR_PHY_DATA, reg + CS_BYTE_GAP(uiCs), startAdll));
+ if(direction == 0)
+ {
+ CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_UNICAST, interfaceId, pupAccess, pup, DDR_PHY_DATA, 0x1 + CS_BYTE_GAP(uiCs), ctrlADLL1[interfaceId*uiCs*octetsPerInterfaceNum+pup]));
+ }
+ }
+ }
+ mvPrintf("Final,CS %d,%s,Leveling,Result,Adll,", uiCs,((direction==0) ? "TX":"RX"));
+ for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
+ {
+ VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
+ if (mode == 1)
+ {
+ for(pup=startPup; pup <=endPup; pup++)
+ {
+ VALIDATE_BUS_ACTIVE(topologyMap->activeBusMask, pup)
+ mvPrintf("I/F%d-PHY%d , ",interfaceId,pup);
+ }
+ }
+ else
+ {
+ mvPrintf("I/F%d , ",interfaceId);
+ }
+ }
+ mvPrintf("\n");
+ for(adll = 0 ; adll < ADLL_LENGTH ; adll++)
+ {
+ adllValue = (direction == 0) ? ((adll*2)-32):((adll*3)-48);
+ mvPrintf("Final,%s,LevelingSweep,Result, %d ,",((direction==0) ? "TX":"RX"),adllValue);
+
+ for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++){
+ VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
+ for( pup=startPup; pup <=endPup; pup++)
+ {
+ mvPrintf("%8d , ",ctrlSweepres[adll][interfaceId][pup]);
+ }
+ }
+ mvPrintf("\n");
+ }
+ /*Write back to the phy the Rx DQS value, we store in the begging. */
+ writeLevelingValue(ctrlADLL,ctrlLevelPhase, (reg + uiCs * CS_REGISTER_ADDR_OFFSET));
+ if(direction == 0)
+ {
+ writeAdllValue(ctrlADLL1, (0x1 + (uiCs * CS_REGISTER_ADDR_OFFSET)));
+ }
+ /* print adll results */
+ readAdllValue(ctrlADLL, (reg + uiCs * CS_REGISTER_ADDR_OFFSET), MASK_ALL_BITS);
+ mvPrintf("%s,DQS,Leveling,,,",(direction==0) ? "Tx":"Rx");
+ printAdll(devNum, ctrlADLL);
+ printPh(devNum, ctrlLevelPhase);
+ }/*End of CS*/
+
+ ddr3TipResetFifoPtr(devNum);
+ return 0;
+}
+
+
+
void printTopology(MV_HWS_TOPOLOGY_MAP *pTopologyDB)
{
GT_U32 ui, uj;
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingDb.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingDb.c
index 4f777c9..ad9507d 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingDb.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingDb.c
@@ -442,6 +442,85 @@
}
}
+inline static GT_U32 patternTableGetSsoFullXtalkWord( GT_U8 bit, GT_U8 index)
+{
+ GT_U8 byte = (1 << bit);
+
+ if( 1 == (index&1) ){
+ byte = ~byte;
+ }
+
+ return (byte || (byte<<8) || (byte<<16) || (byte<<24));
+}
+
+inline static GT_U32 patternTableGetSsoXtalkFreeWord( GT_U8 bit, GT_U8 index)
+{
+ GT_U8 byte = (1 << bit);
+
+ if( 1 == (index&1) ){
+ byte = 0;
+ }
+
+ return (byte || (byte<<8) || (byte<<16) || (byte<<24));
+}
+
+inline static GT_U32 patternTableGetISIWord( GT_U8 index)
+{
+ GT_U8 I0 = index%32;
+ GT_U8 I1 = index%8;
+ GT_U32 Word;
+
+ if(I0 > 15)
+ {
+ Word = ((I1 ==5)|(I1==7))?0xFFFFFFFF:0x0;
+ }else{
+ Word = (I1 ==6)?0xFFFFFFFF:0x0;
+ }
+
+ Word = ((I0%16)>7)?~Word:Word;
+ return Word;
+}
+
+inline static GT_U32 patternTableGetSsoFullXtalkWord_16( GT_U8 bit, GT_U8 index)
+{
+ GT_U8 byte = (1 << bit);
+
+ if( 1 == (index&1) ){
+ byte = ~byte;
+ }
+
+ return (byte || (byte<<8) || ((~byte)<<16) || ((~byte)<<24));
+}
+
+inline static GT_U32 patternTableGetSsoXtalkFreeWord_16( GT_U8 bit, GT_U8 index)
+{
+ GT_U8 byte = (1 << bit);
+
+ if( 0 == ((index)&1) ){
+ return ((byte<<16) || (byte<<24));
+ }
+ else{
+ return (byte || (byte<<8));
+ }
+
+}
+inline static GT_U32 patternTableGetISIWord_16( GT_U8 index)
+{
+ GT_U8 I0 = index%16;
+ GT_U8 I1 = index%4;
+ GT_U32 Word;
+
+ if(I0 > 7)
+ {
+ Word = ( I1>1)?0x0000FFFF:0x0;
+ }else{
+ Word = (I1 ==3)?0xFFFF0000:0x0;
+ }
+
+ Word = ((I0%8)>3)?~Word:Word;
+ return Word;
+}
+
INLINE static GT_U32 patternTableGetVrefWord(GT_U8 index)
{
if( 0 == ((patternVrefPatternTableMap[index/8] >> (index%8))&1) ){
@@ -551,13 +630,36 @@
case PATTERN_VREF:
pattern = patternTableGetVrefWord(index);
break;
+ case PATTERN_SSO_FULL_XTALK_DQ0:
+ case PATTERN_SSO_FULL_XTALK_DQ1:
+ case PATTERN_SSO_FULL_XTALK_DQ2:
+ case PATTERN_SSO_FULL_XTALK_DQ3:
+ case PATTERN_SSO_FULL_XTALK_DQ4:
+ case PATTERN_SSO_FULL_XTALK_DQ5:
+ case PATTERN_SSO_FULL_XTALK_DQ6:
+ case PATTERN_SSO_FULL_XTALK_DQ7:
+ pattern = patternTableGetSsoFullXtalkWord(type - PATTERN_SSO_FULL_XTALK_DQ0, index);
+ break;
+ case PATTERN_SSO_XTALK_FREE_DQ0:
+ case PATTERN_SSO_XTALK_FREE_DQ1:
+ case PATTERN_SSO_XTALK_FREE_DQ2:
+ case PATTERN_SSO_XTALK_FREE_DQ3:
+ case PATTERN_SSO_XTALK_FREE_DQ4:
+ case PATTERN_SSO_XTALK_FREE_DQ5:
+ case PATTERN_SSO_XTALK_FREE_DQ6:
+ case PATTERN_SSO_XTALK_FREE_DQ7:
+ pattern = patternTableGetSsoXtalkFreeWord(type - PATTERN_SSO_XTALK_FREE_DQ0, index);
+ break;
+ case PATTERN_ISI_XTALK_FREE:
+ pattern = patternTableGetISIWord( index);
+ break;
default:
pattern = 0;
break;
}
}
else{
- /*16bit patterns*/
+ /*16bit patterns*/
switch(type){
case PATTERN_PBS1:
case PATTERN_PBS2:
@@ -607,6 +709,29 @@
case PATTERN_VREF:
pattern = patternTableGetVrefWord16(index);
break;
+ case PATTERN_SSO_FULL_XTALK_DQ0:
+ case PATTERN_SSO_FULL_XTALK_DQ1:
+ case PATTERN_SSO_FULL_XTALK_DQ2:
+ case PATTERN_SSO_FULL_XTALK_DQ3:
+ case PATTERN_SSO_FULL_XTALK_DQ4:
+ case PATTERN_SSO_FULL_XTALK_DQ5:
+ case PATTERN_SSO_FULL_XTALK_DQ6:
+ case PATTERN_SSO_FULL_XTALK_DQ7:
+ pattern = patternTableGetSsoFullXtalkWord_16(type - PATTERN_SSO_FULL_XTALK_DQ0, index);
+ break;
+ case PATTERN_SSO_XTALK_FREE_DQ0:
+ case PATTERN_SSO_XTALK_FREE_DQ1:
+ case PATTERN_SSO_XTALK_FREE_DQ2:
+ case PATTERN_SSO_XTALK_FREE_DQ3:
+ case PATTERN_SSO_XTALK_FREE_DQ4:
+ case PATTERN_SSO_XTALK_FREE_DQ5:
+ case PATTERN_SSO_XTALK_FREE_DQ6:
+ case PATTERN_SSO_XTALK_FREE_DQ7:
+ pattern = patternTableGetSsoXtalkFreeWord_16(type - PATTERN_SSO_XTALK_FREE_DQ0, index);
+ break;
+ case PATTERN_ISI_XTALK_FREE:
+ pattern = patternTableGetISIWord_16( index);
+ break;
default:
pattern = 0;
break;
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
index ca8c251..2423079 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
@@ -84,7 +84,10 @@
/* num tx phases tx burst delay between rx pattern start_address patternLen*/
{0x1, 1, 2, 1, 0x0080, 2 }, /* PATTERN_PBS1*/
{0x1, 1, 2, 1, 0x00C0, 2 }, /* PATTERN_PBS2*/
+ {0x1, 1, 2, 1, 0x0380, 2 }, /* PATTERN_PBS3*/
+ {0x1, 1, 2, 1, 0x0040, 2 }, /* PATTERN_TEST*/
{0x1, 1, 2, 1, 0x0100, 2 }, /* PATTERN_RL*/
+ {0x1, 1, 2, 1, 0x0000, 2 }, /* PATTERN_RL2*/
{0xf, 7, 2, 7, 0x0140, 16 }, /* PATTERN_STATIC_PBS*/
{0xf, 7, 2, 7, 0x0190, 16 }, /* PATTERN_KILLER_DQ0*/
{0xf, 7, 2, 7, 0x01D0, 16 }, /* PATTERN_KILLER_DQ1*/
@@ -94,129 +97,195 @@
{0xf, 7, 2, 7, 0x02D0, 16 }, /* PATTERN_KILLER_DQ5*/
{0xf, 7, 2, 7, 0x0310, 16 }, /* PATTERN_KILLER_DQ6*/
{0xf, 7, 2, 7, 0x0350, 16 }, /* PATTERN_KILLER_DQ7*/
- {0x1, 1, 2, 1, 0x0380, 2 }, /* PATTERN_PBS3*/
- {0x1, 1, 2, 1, 0x0000, 2 }, /* PATTERN_RL2*/
- {0x1, 1, 2, 1, 0x0040, 2 }, /* PATTERN_TEST*/
+ {0xf, 7, 2, 7, 0x04C0, 16 }, /* PATTERN_VREF*/
{0xf, 7, 2, 7, 0x03C0, 16 }, /* PATTERN_FULL_SSO_1T*/
{0xf, 7, 2, 7, 0x0400, 16 }, /* PATTERN_FULL_SSO_2T*/
{0xf, 7, 2, 7, 0x0440, 16 }, /* PATTERN_FULL_SSO_3T*/
{0xf, 7, 2, 7, 0x0480, 16 }, /* PATTERN_FULL_SSO_4T*/
- {0xf, 7, 2, 7, 0x04C0, 16 } /* PATTERN_VREF*/
+ {0xf, 7, 2, 7, 0x6280, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ0*/
+ {0xf, 7, 2, 7, 0x6680, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ1*/
+ {0xf, 7, 2, 7, 0x6A80, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ2*/
+ {0xf, 7, 2, 7, 0x6E80, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ3*/
+ {0xf, 7, 2, 7, 0x7280, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ4*/
+ {0xf, 7, 2, 7, 0x7680, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ5*/
+ {0xf, 7, 2, 7, 0x7A80, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ6*/
+ {0xf, 7, 2, 7, 0x7E80, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ7*/
+ {0xf, 7, 2, 7, 0x8280, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ0*/
+ {0xf, 7, 2, 7, 0x8680, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ1*/
+ {0xf, 7, 2, 7, 0x8A80, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ2*/
+ {0xf, 7, 2, 7, 0x8E80, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ3*/
+ {0xf, 7, 2, 7, 0x9280, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ4*/
+ {0xf, 7, 2, 7, 0x9680, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ5*/
+ {0xf, 7, 2, 7, 0x9A80, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ6*/
+ {0xf, 7, 2, 7, 0x9E80, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ7*/
+ {0xf, 7, 2, 7, 0xA280, 16 } /* PATTERN_ISI_XTALK_FREE*/
/*Note: actual start_address is <<3 of defined addess*/
};
PatternInfo patternTable_32[] =
{
/* num tx phases tx burst delay between rx pattern start_address patternLen*/
- {0x3, 0x3, 2, 0x3, 0x0080, 4 }, /* PATTERN_PBS1*/
- {0x3, 0x3, 2, 0x3, 0x00C0, 4 }, /* PATTERN_PBS2*/
- {0x3, 0x3, 2, 0x3, 0x0100, 4 }, /* PATTERN_RL*/
- {0x1f, 0xf, 2, 0xf, 0x0140, 32 }, /* PATTERN_STATIC_PBS*/
- {0x1f, 0xf, 2, 0xf, 0x0190, 32 }, /* PATTERN_KILLER_DQ0*/
- {0x1f, 0xf, 2, 0xf, 0x01D0, 32 }, /* PATTERN_KILLER_DQ1*/
- {0x1f, 0xf, 2, 0xf, 0x0210, 32 }, /* PATTERN_KILLER_DQ2*/
- {0x1f, 0xf, 2, 0xf, 0x0250, 32 }, /* PATTERN_KILLER_DQ3*/
- {0x1f, 0xf, 2, 0xf, 0x0290, 32 }, /* PATTERN_KILLER_DQ4*/
- {0x1f, 0xf, 2, 0xf, 0x02D0, 32 }, /* PATTERN_KILLER_DQ5*/
- {0x1f, 0xf, 2, 0xf, 0x0310, 32 }, /* PATTERN_KILLER_DQ6*/
- {0x1f, 0xf, 2, 0xf, 0x0350, 32 }, /* PATTERN_KILLER_DQ7*/
- {0x3, 0x3, 2, 0x3, 0x0380, 4 }, /* PATTERN_PBS3*/
- {0x3, 0x3, 2, 0x3, 0x0000, 4 }, /* PATTERN_RL2*/
- {0x3, 0x3, 2, 0x3, 0x0040, 4 }, /* PATTERN_TEST*/
- {0x1f, 0xf, 2, 0xf, 0x03C0, 32 }, /* PATTERN_FULL_SSO_1T*/
- {0x1f, 0xf, 2, 0xf, 0x0400, 32 }, /* PATTERN_FULL_SSO_2T*/
- {0x1f, 0xf, 2, 0xf, 0x0440, 32 }, /* PATTERN_FULL_SSO_3T*/
- {0x1f, 0xf, 2, 0xf, 0x0480, 32 }, /* PATTERN_FULL_SSO_4T*/
- {0x1f, 0xf, 2, 0xf, 0x04C0, 32 } /* PATTERN_VREF*/
+ {0x3, 0x3, 2, 0x3, 0x0080, 4 }, /* PATTERN_PBS1*/
+ {0x3, 0x3, 2, 0x3, 0x00C0, 4 }, /* PATTERN_PBS2*/
+ {0x3, 0x3, 2, 0x3, 0x0380, 4 }, /* PATTERN_PBS3*/
+ {0x3, 0x3, 2, 0x3, 0x0040, 4 }, /* PATTERN_TEST*/
+ {0x3, 0x3, 2, 0x3, 0x0100, 4 }, /* PATTERN_RL*/
+ {0x3, 0x3, 2, 0x3, 0x0000, 4 }, /* PATTERN_RL2*/
+ {0x1f, 0xF, 2, 0xf, 0x0140, 32 }, /* PATTERN_STATIC_PBS*/
+ {0x1f, 0xF, 2, 0xf, 0x0190, 32 }, /* PATTERN_KILLER_DQ0*/
+ {0x1f, 0xF, 2, 0xf, 0x01D0, 32 }, /* PATTERN_KILLER_DQ1*/
+ {0x1f, 0xF, 2, 0xf, 0x0210, 32 }, /* PATTERN_KILLER_DQ2*/
+ {0x1f, 0xF, 2, 0xf, 0x0250, 32 }, /* PATTERN_KILLER_DQ3*/
+ {0x1f, 0xF, 2, 0xf, 0x0290, 32 }, /* PATTERN_KILLER_DQ4*/
+ {0x1f, 0xF, 2, 0xf, 0x02D0, 32 }, /* PATTERN_KILLER_DQ5*/
+ {0x1f, 0xF, 2, 0xf, 0x0310, 32 }, /* PATTERN_KILLER_DQ6*/
+ {0x1f, 0xF, 2, 0xf, 0x0350, 32 }, /* PATTERN_KILLER_DQ7*/
+ {0x1f, 0xF, 2, 0xf, 0x04C0, 32 }, /* PATTERN_VREF*/
+ {0x1f, 0xF, 2, 0xf, 0x03C0, 32 }, /* PATTERN_FULL_SSO_1T*/
+ {0x1f, 0xF, 2, 0xf, 0x0400, 32 }, /* PATTERN_FULL_SSO_2T*/
+ {0x1f, 0xF, 2, 0xf, 0x0440, 32 }, /* PATTERN_FULL_SSO_3T*/
+ {0x1f, 0xF, 2, 0xf, 0x0480, 32 }, /* PATTERN_FULL_SSO_4T*/
+ {0x1f, 0xF, 2, 0xf, 0x6280, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ0*/
+ {0x1f, 0xF, 2, 0xf, 0x6680, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ1*/
+ {0x1f, 0xF, 2, 0xf, 0x6A80, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ2*/
+ {0x1f, 0xF, 2, 0xf, 0x6E80, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ3*/
+ {0x1f, 0xF, 2, 0xf, 0x7280, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ4*/
+ {0x1f, 0xF, 2, 0xf, 0x7680, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ5*/
+ {0x1f, 0xF, 2, 0xf, 0x7A80, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ6*/
+ {0x1f, 0xF, 2, 0xf, 0x7E80, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ7*/
+ {0x1f, 0xF, 2, 0xf, 0x8280, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ0*/
+ {0x1f, 0xF, 2, 0xf, 0x8680, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ1*/
+ {0x1f, 0xF, 2, 0xf, 0x8A80, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ2*/
+ {0x1f, 0xF, 2, 0xf, 0x8E80, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ3*/
+ {0x1f, 0xF, 2, 0xf, 0x9280, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ4*/
+ {0x1f, 0xF, 2, 0xf, 0x9680, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ5*/
+ {0x1f, 0xF, 2, 0xf, 0x9A80, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ6*/
+ {0x1f, 0xF, 2, 0xf, 0x9E80, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ7*/
+ {0x1f, 0xF, 2, 0xf, 0xA280, 32 } /* PATTERN_ISI_XTALK_FREE*/
+
+
/*Note: actual start_address is <<3 of defined addess*/
};
#else
-
PatternInfo patternTable_16[] =
{
/* num tx phases tx burst delay between rx pattern start_address patternLen*/
- {0x1, 0x1, 2, 0x1, 0x0080, 2 }, /* PATTERN_PBS1*/
- {0x1, 0x1, 2, 0x1, 0x00C0, 2 }, /* PATTERN_PBS2*/
- {0x1, 0x1, 2, 0x1, 0x0100, 2 }, /* PATTERN_RL*/
- {0xf, 0x7, 2, 0x7, 0x0140, 16 }, /* PATTERN_STATIC_PBS*/
- {0xf, 0x7, 2, 0x7, 0x0180, 16 }, /* PATTERN_KILLER_DQ0*/
- {0xf, 0x7, 2, 0x7, 0x01C0, 16 }, /* PATTERN_KILLER_DQ1*/
- {0xf, 0x7, 2, 0x7, 0x0200, 16 }, /* PATTERN_KILLER_DQ2*/
- {0xf, 0x7, 2, 0x7, 0x0240, 16 }, /* PATTERN_KILLER_DQ3*/
- {0xf, 0x7, 2, 0x7, 0x0280, 16 }, /* PATTERN_KILLER_DQ4*/
- {0xf, 0x7, 2, 0x7, 0x02C0, 16 }, /* PATTERN_KILLER_DQ5*/
- {0xf, 0x7, 2, 0x7, 0x0300, 16 }, /* PATTERN_KILLER_DQ6*/
- {0xf, 0x7, 2, 0x7, 0x0340, 16 }, /* PATTERN_KILLER_DQ7*/
- {0xf, 0x7, 2, 0x7, 0x1180, 16 }, /* PATTERN_KILLER_DQ0_EXT*/
- {0xf, 0x7, 2, 0x7, 0x11C0, 16 }, /* PATTERN_KILLER_DQ1_EXT*/
- {0xf, 0x7, 2, 0x7, 0x1200, 16 }, /* PATTERN_KILLER_DQ2_EXT*/
- {0xf, 0x7, 2, 0x7, 0x1240, 16 }, /* PATTERN_KILLER_DQ3_EXT*/
- {0xf, 0x7, 2, 0x7, 0x1280, 16 }, /* PATTERN_KILLER_DQ4_EXT*/
- {0xf, 0x7, 2, 0x7, 0x12C0, 16 }, /* PATTERN_KILLER_DQ5_EXT*/
- {0xf, 0x7, 2, 0x7, 0x1300, 16 }, /* PATTERN_KILLER_DQ6_EXT*/
- {0xf, 0x7, 2, 0x7, 0x1340, 16 }, /* PATTERN_KILLER_DQ7_EXT*/
- {0xf, 0x7, 2, 0x7, 0x04C0, 16 }, /* PATTERN_VREF*/
- {0xf, 0x7, 2, 0x7, 0x14C0, 16 }, /* PATTERN_VREF_INV*/
- {0xf, 0x7, 2, 0x7, 0x1500, 16 }, /* PATTERN_RESONANCE_1T*/
- {0xf, 0x7, 2, 0x7, 0x1540, 16 }, /* PATTERN_RESONANCE_2T*/
- {0xf, 0x7, 2, 0x7, 0x1580, 16 }, /* PATTERN_RESONANCE_3T*/
- {0xf, 0x7, 2, 0x7, 0x15C0, 16 }, /* PATTERN_RESONANCE_4T*/
- {0xf, 0x7, 2, 0x7, 0x1600, 16 }, /* PATTERN_RESONANCE_5T*/
- {0xf, 0x7, 2, 0x7, 0x1640, 16 }, /* PATTERN_RESONANCE_6T*/
- {0xf, 0x7, 2, 0x7, 0x1680, 16 }, /* PATTERN_RESONANCE_7T*/
- {0xf, 0x7, 2, 0x7, 0x16C0, 16 }, /* PATTERN_RESONANCE_8T*/
- {0xf, 0x7, 2, 0x7, 0x1700, 16 }, /* PATTERN_RESONANCE_9T*/
- {0x3, 0x1, 2, 0x1, 0x0380, 2 }, /* PATTERN_PBS3*/
- {0x3, 0x1, 2, 0x1, 0x0000, 2 }, /* PATTERN_RL2*/
- {0x3, 0x1, 2, 0x1, 0x0040, 2 }, /* PATTERN_TEST*/
- {0x1f, 0x7, 2, 0x7, 0x03C0, 16 }, /* PATTERN_FULL_SSO_1T*/
- {0x1f, 0x7, 2, 0x7, 0x0400, 16 }, /* PATTERN_FULL_SSO_2T*/
- {0x1f, 0x7, 2, 0x7, 0x0440, 16 }, /* PATTERN_FULL_SSO_3T*/
- {0x1f, 0x7, 2, 0x7, 0x0480, 16 } /* PATTERN_FULL_SSO_4T*/
+ {0x1, 0x1, 2, 0x1, 0x0000, 2 }, /* PATTERN_PBS1*/
+ {0x1, 0x1, 2, 0x1, 0x0080, 2 }, /* PATTERN_PBS2*/
+ {0x1, 0x1, 2, 0x1, 0x0100, 2 }, /* PATTERN_PBS3*/
+ {0x1, 0x1, 2, 0x1, 0x0180, 2 }, /* PATTERN_TEST*/
+ {0x1, 0x1, 2, 0x1, 0x0200, 2 }, /* PATTERN_RL*/
+ {0x1, 0x1, 2, 0x1, 0x0280, 2 }, /* PATTERN_RL2*/
+ {0xf, 0x7, 2, 0x7, 0x0680, 16 }, /* PATTERN_STATIC_PBS*/
+ {0xf, 0x7, 2, 0x7, 0x0A80, 16 }, /* PATTERN_KILLER_DQ0*/
+ {0xf, 0x7, 2, 0x7, 0x0E80, 16 }, /* PATTERN_KILLER_DQ1*/
+ {0xf, 0x7, 2, 0x7, 0x1280, 16 }, /* PATTERN_KILLER_DQ2*/
+ {0xf, 0x7, 2, 0x7, 0x1680, 16 }, /* PATTERN_KILLER_DQ3*/
+ {0xf, 0x7, 2, 0x7, 0x1A80, 16 }, /* PATTERN_KILLER_DQ4*/
+ {0xf, 0x7, 2, 0x7, 0x1E80, 16 }, /* PATTERN_KILLER_DQ5*/
+ {0xf, 0x7, 2, 0x7, 0x2280, 16 }, /* PATTERN_KILLER_DQ6*/
+ {0xf, 0x7, 2, 0x7, 0x2680, 16 }, /* PATTERN_KILLER_DQ7*/
+ {0xf, 0x7, 2, 0x7, 0x2A80, 16 }, /* PATTERN_KILLER_DQ0_INV*/
+ {0xf, 0x7, 2, 0x7, 0x2E80, 16 }, /* PATTERN_KILLER_DQ1_INV*/
+ {0xf, 0x7, 2, 0x7, 0x3280, 16 }, /* PATTERN_KILLER_DQ2_INV*/
+ {0xf, 0x7, 2, 0x7, 0x3680, 16 }, /* PATTERN_KILLER_DQ3_INV*/
+ {0xf, 0x7, 2, 0x7, 0x3A80, 16 }, /* PATTERN_KILLER_DQ4_INV*/
+ {0xf, 0x7, 2, 0x7, 0x3E80, 16 }, /* PATTERN_KILLER_DQ5_INV*/
+ {0xf, 0x7, 2, 0x7, 0x4280, 16 }, /* PATTERN_KILLER_DQ6_INV*/
+ {0xf, 0x7, 2, 0x7, 0x4680, 16 }, /* PATTERN_KILLER_DQ7_INV*/
+ {0xf, 0x7, 2, 0x7, 0x4A80, 16 }, /* PATTERN_VREF*/
+ {0xf, 0x7, 2, 0x7, 0x4E80, 16 }, /* PATTERN_VREF_INV*/
+ {0xf, 0x7, 2, 0x7, 0x5280, 16 }, /* PATTERN_FULL_SSO_0T*/
+ {0xf, 0x7, 2, 0x7, 0x5680, 16 }, /* PATTERN_FULL_SSO_1T*/
+ {0xf, 0x7, 2, 0x7, 0x5A80, 16 }, /* PATTERN_FULL_SSO_2T*/
+ {0xf, 0x7, 2, 0x7, 0x5E80, 16 }, /* PATTERN_FULL_SSO_3T*/
+ {0xf, 0x7, 2, 0x7, 0x6280, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ0*/
+ {0xf, 0x7, 2, 0x7, 0x6680, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ1*/
+ {0xf, 0x7, 2, 0x7, 0x6A80, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ2*/
+ {0xf, 0x7, 2, 0x7, 0x6E80, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ3*/
+ {0xf, 0x7, 2, 0x7, 0x7280, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ4*/
+ {0xf, 0x7, 2, 0x7, 0x7680, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ5*/
+ {0xf, 0x7, 2, 0x7, 0x7A80, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ6*/
+ {0xf, 0x7, 2, 0x7, 0x7E80, 16 }, /* PATTERN_SSO_FULL_XTALK_DQ7*/
+ {0xf, 0x7, 2, 0x7, 0x8280, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ0*/
+ {0xf, 0x7, 2, 0x7, 0x8680, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ1*/
+ {0xf, 0x7, 2, 0x7, 0x8A80, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ2*/
+ {0xf, 0x7, 2, 0x7, 0x8E80, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ3*/
+ {0xf, 0x7, 2, 0x7, 0x9280, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ4*/
+ {0xf, 0x7, 2, 0x7, 0x9680, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ5*/
+ {0xf, 0x7, 2, 0x7, 0x9A80, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ6*/
+ {0xf, 0x7, 2, 0x7, 0x9E80, 16 }, /* PATTERN_SSO_XTALK_FREE_DQ7*/
+ {0xf, 0x7, 2, 0x7, 0xA280, 16 }, /* PATTERN_ISI_XTALK_FREE*/
+ {0xf, 0x7, 2, 0x7, 0xA680, 16 }, /* PATTERN_RESONANCE_1T*/
+ {0xf, 0x7, 2, 0x7, 0xAA80, 16 }, /* PATTERN_RESONANCE_2T*/
+ {0xf, 0x7, 2, 0x7, 0xAE80, 16 }, /* PATTERN_RESONANCE_3T*/
+ {0xf, 0x7, 2, 0x7, 0xB280, 16 }, /* PATTERN_RESONANCE_4T*/
+ {0xf, 0x7, 2, 0x7, 0xB680, 16 }, /* PATTERN_RESONANCE_5T*/
+ {0xf, 0x7, 2, 0x7, 0xBA80, 16 }, /* PATTERN_RESONANCE_6T*/
+ {0xf, 0x7, 2, 0x7, 0xBE80, 16 }, /* PATTERN_RESONANCE_7T*/
+ {0xf, 0x7, 2, 0x7, 0xC280, 16 }, /* PATTERN_RESONANCE_8T*/
+ {0xf, 0x7, 2, 0x7, 0xC680, 16 } /* PATTERN_RESONANCE_9T*/
/*Note: actual start_address is <<3 of defined addess*/
};
PatternInfo patternTable_32[] =
{
/* num tx phases tx burst delay between rx pattern start_address patternLen*/
- {0x3, 0x3, 2, 0x3, 0x0080, 4 }, /* PATTERN_PBS1*/
- {0x3, 0x3, 2, 0x3, 0x00C0, 4 }, /* PATTERN_PBS2*/
- {0x3, 0x3, 2, 0x3, 0x0100, 4 }, /* PATTERN_RL*/
- {0x1f, 0xf, 2, 0xf, 0x0140, 32 }, /* PATTERN_STATIC_PBS*/
- {0x1f, 0xf, 2, 0xf, 0x0180, 32 }, /* PATTERN_KILLER_DQ0*/
- {0x1f, 0xf, 2, 0xf, 0x01C0, 32 }, /* PATTERN_KILLER_DQ1*/
- {0x1f, 0xf, 2, 0xf, 0x0200, 32 }, /* PATTERN_KILLER_DQ2*/
- {0x1f, 0xf, 2, 0xf, 0x0240, 32 }, /* PATTERN_KILLER_DQ3*/
- {0x1f, 0xf, 2, 0xf, 0x0280, 32 }, /* PATTERN_KILLER_DQ4*/
- {0x1f, 0xf, 2, 0xf, 0x02C0, 32 }, /* PATTERN_KILLER_DQ5*/
- {0x1f, 0xf, 2, 0xf, 0x0300, 32 }, /* PATTERN_KILLER_DQ6*/
- {0x1f, 0xf, 2, 0xf, 0x0340, 32 }, /* PATTERN_KILLER_DQ7*/
- {0x1f, 0xf, 2, 0xf, 0x1180, 32 }, /* PATTERN_KILLER_DQ0_EXT*/
- {0x1f, 0xf, 2, 0xf, 0x11C0, 32 }, /* PATTERN_KILLER_DQ1_EXT*/
- {0x1f, 0xf, 2, 0xf, 0x1200, 32 }, /* PATTERN_KILLER_DQ2_EXT*/
- {0x1f, 0xf, 2, 0xf, 0x1240, 32 }, /* PATTERN_KILLER_DQ3_EXT*/
- {0x1f, 0xf, 2, 0xf, 0x1280, 32 }, /* PATTERN_KILLER_DQ4_EXT*/
- {0x1f, 0xf, 2, 0xf, 0x12C0, 32 }, /* PATTERN_KILLER_DQ5_EXT*/
- {0x1f, 0xf, 2, 0xf, 0x1300, 32 }, /* PATTERN_KILLER_DQ6_EXT*/
- {0x1f, 0xf, 2, 0xf, 0x1340, 32 }, /* PATTERN_KILLER_DQ7_EXT*/
- {0x1f, 0xf, 2, 0xf, 0x04C0, 32 }, /* PATTERN_VREF*/
- {0x1f, 0xf, 2, 0xf, 0x14C0, 32 }, /* PATTERN_VREF_INV*/
- {0x1f, 0xf, 2, 0xf, 0x1500, 32 }, /* PATTERN_RESONANCE_1T*/
- {0x1f, 0xf, 2, 0xf, 0x1540, 32 }, /* PATTERN_RESONANCE_2T*/
- {0x1f, 0xf, 2, 0xf, 0x1580, 32 }, /* PATTERN_RESONANCE_3T*/
- {0x1f, 0xf, 2, 0xf, 0x15C0, 32 }, /* PATTERN_RESONANCE_4T*/
- {0x1f, 0xf, 2, 0xf, 0x1600, 32 }, /* PATTERN_RESONANCE_5T*/
- {0x1f, 0xf, 2, 0xf, 0x1640, 32 }, /* PATTERN_RESONANCE_6T*/
- {0x1f, 0xf, 2, 0xf, 0x1680, 32 }, /* PATTERN_RESONANCE_7T*/
- {0x1f, 0xf, 2, 0xf, 0x16C0, 32 }, /* PATTERN_RESONANCE_8T*/
- {0x1f, 0xf, 2, 0xf, 0x1700, 32 }, /* PATTERN_RESONANCE_9T*/
- {0x3, 0x3, 2, 0x3, 0x0380, 4 }, /* PATTERN_PBS3*/
- {0x3, 0x3, 2, 0x3, 0x0000, 4 }, /* PATTERN_RL2*/
- {0x3, 0x3, 2, 0x3, 0x0040, 4 }, /* PATTERN_TEST*/
- {0x1f, 0xf, 2, 0xf, 0x03C0, 32 }, /* PATTERN_FULL_SSO_1T*/
- {0x1f, 0xf, 2, 0xf, 0x0400, 32 }, /* PATTERN_FULL_SSO_2T*/
- {0x1f, 0xf, 2, 0xf, 0x0440, 32 }, /* PATTERN_FULL_SSO_3T*/
- {0x1f, 0xf, 2, 0xf, 0x0480, 32 } /* PATTERN_FULL_SSO_4T*/
+ {0x3, 0x3, 2, 0x3, 0x0000, 4 }, /* PATTERN_PBS1*/
+ {0x3, 0x3, 2, 0x3, 0x0080, 4 }, /* PATTERN_PBS2*/
+ {0x3, 0x3, 2, 0x3, 0x0100, 4 }, /* PATTERN_PBS3*/
+ {0x3, 0x3, 2, 0x3, 0x0180, 4 }, /* PATTERN_TEST*/
+ {0x3, 0x3, 2, 0x3, 0x0200, 4 }, /* PATTERN_RL*/
+ {0x3, 0x3, 2, 0x3, 0x0280, 4 }, /* PATTERN_RL2*/
+ {0x1f, 0xf, 2, 0xf, 0x0680, 32 }, /* PATTERN_STATIC_PBS*/
+ {0x1f, 0xf, 2, 0xf, 0x0A80, 32 }, /* PATTERN_KILLER_DQ0*/
+ {0x1f, 0xf, 2, 0xf, 0x0E80, 32 }, /* PATTERN_KILLER_DQ1*/
+ {0x1f, 0xf, 2, 0xf, 0x1280, 32 }, /* PATTERN_KILLER_DQ2*/
+ {0x1f, 0xf, 2, 0xf, 0x1680, 32 }, /* PATTERN_KILLER_DQ3*/
+ {0x1f, 0xf, 2, 0xf, 0x1A80, 32 }, /* PATTERN_KILLER_DQ4*/
+ {0x1f, 0xf, 2, 0xf, 0x1E80, 32 }, /* PATTERN_KILLER_DQ5*/
+ {0x1f, 0xf, 2, 0xf, 0x2280, 32 }, /* PATTERN_KILLER_DQ6*/
+ {0x1f, 0xf, 2, 0xf, 0x2680, 32 }, /* PATTERN_KILLER_DQ7*/
+ {0x1f, 0xf, 2, 0xf, 0x2A80, 32 }, /* PATTERN_KILLER_DQ0_INV*/
+ {0x1f, 0xf, 2, 0xf, 0x2E80, 32 }, /* PATTERN_KILLER_DQ1_INV*/
+ {0x1f, 0xf, 2, 0xf, 0x3280, 32 }, /* PATTERN_KILLER_DQ2_INV*/
+ {0x1f, 0xf, 2, 0xf, 0x3680, 32 }, /* PATTERN_KILLER_DQ3_INV*/
+ {0x1f, 0xf, 2, 0xf, 0x3A80, 32 }, /* PATTERN_KILLER_DQ4_INV*/
+ {0x1f, 0xf, 2, 0xf, 0x3E80, 32 }, /* PATTERN_KILLER_DQ5_INV*/
+ {0x1f, 0xf, 2, 0xf, 0x4280, 32 }, /* PATTERN_KILLER_DQ6_INV*/
+ {0x1f, 0xf, 2, 0xf, 0x4680, 32 }, /* PATTERN_KILLER_DQ7_INV*/
+ {0x1f, 0xf, 2, 0xf, 0x4A80, 32 }, /* PATTERN_VREF*/
+ {0x1f, 0xf, 2, 0xf, 0x4E80, 32 }, /* PATTERN_VREF_INV*/
+ {0x1f, 0xf, 2, 0xf, 0x5280, 32 }, /* PATTERN_FULL_SSO_0T*/
+ {0x1f, 0xf, 2, 0xf, 0x5680, 32 }, /* PATTERN_FULL_SSO_1T*/
+ {0x1f, 0xf, 2, 0xf, 0x5A80, 32 }, /* PATTERN_FULL_SSO_2T*/
+ {0x1f, 0xf, 2, 0xf, 0x5E80, 32 }, /* PATTERN_FULL_SSO_3T*/
+ {0x1f, 0xf, 2, 0xf, 0x6280, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ0*/
+ {0x1f, 0xf, 2, 0xf, 0x6680, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ1*/
+ {0x1f, 0xf, 2, 0xf, 0x6A80, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ2*/
+ {0x1f, 0xf, 2, 0xf, 0x6E80, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ3*/
+ {0x1f, 0xf, 2, 0xf, 0x7280, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ4*/
+ {0x1f, 0xf, 2, 0xf, 0x7680, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ5*/
+ {0x1f, 0xf, 2, 0xf, 0x7A80, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ6*/
+ {0x1f, 0xf, 2, 0xf, 0x7E80, 32 }, /* PATTERN_SSO_FULL_XTALK_DQ7*/
+ {0x1f, 0xf, 2, 0xf, 0x8280, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ0*/
+ {0x1f, 0xf, 2, 0xf, 0x8680, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ1*/
+ {0x1f, 0xf, 2, 0xf, 0x8A80, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ2*/
+ {0x1f, 0xf, 2, 0xf, 0x8E80, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ3*/
+ {0x1f, 0xf, 2, 0xf, 0x9280, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ4*/
+ {0x1f, 0xf, 2, 0xf, 0x9680, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ5*/
+ {0x1f, 0xf, 2, 0xf, 0x9A80, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ6*/
+ {0x1f, 0xf, 2, 0xf, 0x9E80, 32 }, /* PATTERN_SSO_XTALK_FREE_DQ7*/
+ {0x1f, 0xf, 2, 0xf, 0xA280, 32 }, /* PATTERN_ISI_XTALK_FREE*/
+ {0x1f, 0xf, 2, 0xf, 0xA680, 32 }, /* PATTERN_RESONANCE_1T*/
+ {0x1f, 0xf, 2, 0xf, 0xAA80, 32 }, /* PATTERN_RESONANCE_2T*/
+ {0x1f, 0xf, 2, 0xf, 0xAE80, 32 }, /* PATTERN_RESONANCE_3T*/
+ {0x1f, 0xf, 2, 0xf, 0xB280, 32 }, /* PATTERN_RESONANCE_4T*/
+ {0x1f, 0xf, 2, 0xf, 0xB680, 32 }, /* PATTERN_RESONANCE_5T*/
+ {0x1f, 0xf, 2, 0xf, 0xBA80, 32 }, /* PATTERN_RESONANCE_6T*/
+ {0x1f, 0xf, 2, 0xf, 0xBE80, 32 }, /* PATTERN_RESONANCE_7T*/
+ {0x1f, 0xf, 2, 0xf, 0xC280, 32 }, /* PATTERN_RESONANCE_8T*/
+ {0x1f, 0xf, 2, 0xf, 0xC680, 32 } /* PATTERN_RESONANCE_9T*/
/*Note: actual start_address is <<3 of defined addess*/
};
