ddr3libv2: bobk: Integration of Caelum DDR training to CPSS

	-Define Caelum topology
	-Define HW DDR IF mask for Caelum and Cetus
	-Define number of busses per interface for MSYS and TM

Change-Id: I06032166841de705bdef0f2ced25cb7a0550ba3d
Signed-off-by: Margarita Granov <margra@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/23756
Tested-by: Star_Automation <star@marvell.com>
Reviewed-by: Haim Boot <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24167
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
1 file changed