msys: bobk: add preliminary support for RD_Lewis

    - Add new definition for Lewis RD board
    - Add deviceID 0xBE10 for RD_Lewis, update BobK device matrix,
     also update for common/15t1,common/15t2,LK2.6 & LK3.4
    - Add Hardware service topology for Lewis

Change-Id:Ifa314942e06f6857efd35b920e87fa20e59b4537
Signed-off-by: Zachary Zhang <zhangzg@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/23599
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
diff --git a/board/mv_ebu/common/common/mvDeviceId.h b/board/mv_ebu/common/common/mvDeviceId.h
index d993ff8..ddcb503 100644
--- a/board/mv_ebu/common/common/mvDeviceId.h
+++ b/board/mv_ebu/common/common/mvDeviceId.h
@@ -448,6 +448,7 @@
 /* BobK deivces matrix */
 #define MV_BOBK_CETUS_98DX4235_DEV_ID		0xBE00
 #define MV_BOBK_CAELUM_98DX4203_DEV_ID		0xBC00
+#define MV_BOBK_LEWIS_98DX8212_DEV_ID		0xBE10
 
 /* BobK  Revisions */
 #define MV_BOBK_A0_ID		0x0
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
index 9ec7405..55721f5 100644
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
@@ -1054,6 +1054,100 @@
 };
 
 /*********************************************************************************/
+/**************************************/
+/* BOBK-LEWIS-RD-LWS-12XG-A BOARD */
+/**************************************/
+
+
+MV_BOARD_TWSI_INFO	rd_dx_bobkLewisInfoBoardTwsiDev[] = {
+/* {{MV_BOARD_DEV_CLASS	devClass, MV_U8	twsiDevAddr, MV_U8 twsiDevAddrType}} */
+	{BOARD_DEV_TWSI_INIT_EPROM, 0x50, ADDR7_BIT},	/* Serial Init EPROM	*/
+};
+
+
+MV_BOARD_MAC_INFO rd_dx_bobkLewisInfoBoardMacInfo[] = {
+/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
+	{BOARD_MAC_SPEED_AUTO, -1, -1, MV_FALSE},
+	{BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+};
+
+MV_BOARD_MODULE_TYPE_INFO rd_dx_bobkLewisInfoBoardModTypeInfo[] = {
+	{
+		.boardMppMod		= MV_BOARD_AUTO,
+	}
+};
+
+/* TO DE */
+MV_DEV_CS_INFO rd_dx_bobkLewisInfoBoardDeCsInfo[] = {
+	/*{deviceCS, params, devType, devWidth, busWidth }*/
+#if defined(MV_INCLUDE_SPI)
+	{SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
+#endif
+#if defined(MV_INCLUDE_NAND)
+	{DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#endif
+};
+
+MV_BOARD_MPP_INFO rd_dx_bobkLewisInfoBoardMppConfigValue[] = {
+	{ {
+	RD_DX_BOBK_LEWIS_MPP0_7,
+	RD_DX_BOBK_LEWIS_MPP8_15,
+	RD_DX_BOBK_LEWIS_MPP16_23,
+	RD_DX_BOBK_LEWIS_MPP24_31,
+	RD_DX_BOBK_LEWIS_MPP32_39,
+	} },
+};
+
+MV_BOARD_INFO rd_dx_bobkLewisInfo = {
+	.boardName			= "RD-LWS-12XG-A",
+	.numBoardMppTypeValue		= ARRSZ(rd_dx_bobkLewisInfoBoardModTypeInfo),
+	.pBoardModTypeValue		= rd_dx_bobkLewisInfoBoardModTypeInfo,
+	.numBoardMppConfigValue		= ARRSZ(rd_dx_bobkLewisInfoBoardMppConfigValue),
+	.pBoardMppConfigValue		= rd_dx_bobkLewisInfoBoardMppConfigValue,
+	.intsGppMaskLow			= 0,
+	.intsGppMaskMid			= 0,
+	.intsGppMaskHigh		= 0,
+	.numBoardDeviceIf		= ARRSZ(rd_dx_bobkLewisInfoBoardDeCsInfo),
+	.pDevCsInfo			= rd_dx_bobkLewisInfoBoardDeCsInfo,
+	.numBoardTwsiDev		= ARRSZ(rd_dx_bobkLewisInfoBoardTwsiDev),
+	.pBoardTwsiDev			= rd_dx_bobkLewisInfoBoardTwsiDev,
+	.numBoardMacInfo		= ARRSZ(rd_dx_bobkLewisInfoBoardMacInfo),
+	.pBoardMacInfo			= rd_dx_bobkLewisInfoBoardMacInfo,
+	.numBoardGppInfo		= 0,
+	.pBoardGppInfo			= NULL,
+	.activeLedsNumber		= 0,
+	.pLedGppPin			= NULL,
+	.ledsPolarity			= 0,
+
+	/* GPP values */
+	.gppOutEnValLow			= RD_DX_BOBK_LEWIS_GPP_OUT_ENA_LOW,
+	.gppOutEnValMid			= RD_DX_BOBK_LEWIS_GPP_OUT_ENA_MID,
+	.gppOutEnValHigh		= 0,
+	.gppOutValLow			= RD_DX_BOBK_LEWIS_GPP_OUT_VAL_LOW,
+	.gppOutValMid			= RD_DX_BOBK_LEWIS_GPP_OUT_VAL_MID,
+	.gppOutValHigh			= 0,
+	.gppPolarityValLow		= RD_DX_BOBK_LEWIS_GPP_POL_LOW,
+	.gppPolarityValMid		= RD_DX_BOBK_LEWIS_GPP_POL_MID,
+	.gppPolarityValHigh		= 0,
+
+	/* External Switch Configuration */
+	.pSwitchInfo = NULL,
+	.switchInfoNum = 0,
+
+	/* NAND init params */
+	.nandFlashReadParams		= DB_DX_BOBK_BOARD_NAND_READ_PARAMS,
+	.nandFlashWriteParams		= DB_DX_BOBK_BOARD_NAND_WRITE_PARAMS,
+	.nandFlashControl		= DB_DX_BOBK_BOARD_NAND_CONTROL,
+	/* NOR init params */
+	.norFlashReadParams		= DB_DX_BOBK_BOARD_NOR_READ_PARAMS,
+	.norFlashWriteParams		= DB_DX_BOBK_BOARD_NOR_WRITE_PARAMS,
+	.isSmiExternalPp		= MV_TRUE,
+	.smiExternalPpIndex		= 0,
+	.modelName			= "BobK Lewis Reference Design Board",
+	.isSdMmcConnected		= MV_TRUE
+};
+
+/*********************************************************************************/
 /***********************/
 /* ALLEYCAT3-DB-DX BOARD */
 /***********************/
@@ -1522,7 +1616,8 @@
 
 MV_BOARD_INFO *marvellBOBKBoardInfoTbl[] = {
 	&db_dx_bobkCetusInfo,
-	&db_dx_bobkCaelumInfo
+	&db_dx_bobkCaelumInfo,
+	&rd_dx_bobkLewisInfo
 };
 
 MV_BOARD_INFO *marvellAC3BoardInfoTbl[] = {
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h
index 2e36929..fba63de 100644
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h
@@ -108,14 +108,15 @@
 #define BOBK_CUSTOMER_BOARD_ID_BASE	0x40
 #define BOBK_CETUS_CUSTOMER_BOARD_ID0		(BOBK_CUSTOMER_BOARD_ID_BASE + 0)
 #define BOBK_CAELUM_CUSTOMER_BOARD_ID1		(BOBK_CUSTOMER_BOARD_ID_BASE + 1)
-#define BOBK_CUSTOMER_MAX_BOARD_ID	(BOBK_CUSTOMER_BOARD_ID_BASE + 2)
-#define BOBK_CUSTOMER_BOARD_NUM		(BOBK_CUSTOMER_MAX_BOARD_ID - BOBK_CUSTOMER_BOARD_ID_BASE)
+#define BOBK_CUSTOMER_MAX_BOARD_ID			(BOBK_CUSTOMER_BOARD_ID_BASE + 2)
+#define BOBK_CUSTOMER_BOARD_NUM			(BOBK_CUSTOMER_MAX_BOARD_ID - BOBK_CUSTOMER_BOARD_ID_BASE)
 
 /* BobK Marvell Boards */
 #define BOBK_MARVELL_BOARD_ID_BASE	0x50
 #define BOBK_CETUS_DB_ID			(BOBK_MARVELL_BOARD_ID_BASE + 0)
 #define BOBK_CAELUM_DB_ID			(BOBK_MARVELL_BOARD_ID_BASE + 1)
-#define BOBK_MARVELL_MAX_BOARD_ID	(BOBK_MARVELL_BOARD_ID_BASE + 2)
+#define BOBK_LEWIS_RD_ID			(BOBK_MARVELL_BOARD_ID_BASE + 2)
+#define BOBK_MARVELL_MAX_BOARD_ID		(BOBK_MARVELL_BOARD_ID_BASE + 3)
 #define BOBK_MARVELL_BOARD_NUM		(BOBK_MARVELL_MAX_BOARD_ID - BOBK_MARVELL_BOARD_ID_BASE)
 
 /* AXP-AMC board: for Linux 2.6/3.4 usage only (AXP family is shared with MSYS in LSP) */
@@ -477,6 +478,68 @@
 #define DB_DX_BOBK_CAELUM_GPP_POL_LOW		0x0
 #define DB_DX_BOBK_CAELUM_GPP_POL_MID		0x0
 
+
+/************************************/
+/*   BOBK-LEWIS-RD-LWS-12XG-A    */
+/************************************/
+#define RD_DX_BOBK_LEWIS_MPP0_7	0x00042222 /* 0-3:SPI, 4:NF_CEn, 5:SFP_Data, 6:DIAG LED, 7:TWSI_SEL1 */
+#define RD_DX_BOBK_LEWIS_MPP8_15	0x11000000 /* 8:TWSI_SEL2,9:SFP_TX,10,TMP_INT,11:INIT_Done,12:MPP12,
+							13:USB_OC,14-15:I2C_[SCLK,SDA] */
+#define RD_DX_BOBK_LEWIS_MPP16_23	0x44444004 /* 16:NF_REn, 17:TWSI_SEL0, 18:NA, 19-23:NF_[Busy,WEn,IO[0,1,2]] */
+#define RD_DX_BOBK_LEWIS_MPP24_31	0x14444444 /* 24-30: NF_IO[3,4,5,6,7],NF_CLE,NF_ALE, 31: SMI_MST_MDC(SMI) */
+#define RD_DX_BOBK_LEWIS_MPP32_39	0x00000001 /* 32: SMI_MST_MDIO(SMI) */
+
+
+/* GPPs
+MPP#	NAME			IN/OUT
+----------------------------------------------
+0	SPI_SI			(in/out)
+1	SPI_SO			(in/out)
+2	SPI_SCK			(in/out)
+3	SPI_CS0n			(in/out)
+4	NF_CEn			(in/out) NAND Flash
+5	SFP_Data			(in)
+6	DIAG LED			(out)
+7	TWSI_SEL1		(out)
+8	TWSI_SEL2		(out)
+9	SFP_TX_DIS		(out)
+10	TMP_INT			(in)
+11	INIT_Done		(in)
+12	MPP12			(N/A)
+13	USB_OC			(in)
+14	I2C_SCLK			(out)
+15	I2C_SDA			(in/out)
+
+16	NF_REn			(in/out)NAND Flash
+17	TWSI_SEL0		(out)
+18	NA			(NA)
+19	NF_Busy			(in/out)NAND Flash
+20	NF_WEn			(in/out)NAND Flash
+21	NF_IO[0]			(in/out)NAND Flash
+22	NF_IO[1]			(in/out)NAND Flash
+23	NF_IO[2]			(in/out)NAND Flash
+24	NF_IO[3]			(in/out)NAND Flash
+25	NF_IO[4]			(in/out)NAND Flash
+26	NF_IO[5]			(in/out)NAND Flash
+27	NF_IO[6]			(in/out)NAND Flash
+28	NF_IO[7]			(in/out)NAND Flash
+29	NF_CLE			(in/out)NAND Flash
+30	NF_ALE			(in/out)NAND Flash
+31	SMI_MST_MDC		(out)
+32	SMI_MST_MDIO		(in/out)
+
+*/
+#define RD_DX_BOBK_LEWIS_GPP_OUT_ENA_LOW	(~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT7 | BIT8\
+					| BIT9 | BIT14 | BIT17 | BIT31))
+#define RD_DX_BOBK_LEWIS_GPP_OUT_ENA_MID	(~(0))
+
+#define RD_DX_BOBK_LEWIS_GPP_OUT_VAL_LOW	(~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT9\
+					| BIT14 | BIT17 | BIT31))
+#define RD_DX_BOBK_LEWIS_GPP_OUT_VAL_MID	0x0
+
+#define RD_DX_BOBK_LEWIS_GPP_POL_LOW		0x0
+#define RD_DX_BOBK_LEWIS_GPP_POL_MID		0x0
+
 /********************************************
 *		AlleyCat3 Boards
 *********************************************/
diff --git a/board/mv_ebu/msys/msys_family/cpu/mvCpu.c b/board/mv_ebu/msys/msys_family/cpu/mvCpu.c
index 0f7a318..a7a143f 100644
--- a/board/mv_ebu/msys/msys_family/cpu/mvCpu.c
+++ b/board/mv_ebu/msys/msys_family/cpu/mvCpu.c
@@ -120,6 +120,8 @@
 	else if (family == MV_BOBK_DEV_ID) {
 		switch (mvCtrlModelGet()) {
 		case MV_BOBK_CETUS_98DX4235_DEV_ID:
+		case MV_BOBK_LEWIS_98DX8212_DEV_ID:
+			/* LEWIS RD board's CPU freq setting is the same as CETUS board */
 			freqMhz = bobkCetusClockRatioTbl[idx].cpuFreq * 1000000;
 			break;
 		case MV_BOBK_CAELUM_98DX4203_DEV_ID:
@@ -170,6 +172,8 @@
 	else if (family == MV_BOBK_DEV_ID) {
 		switch (mvCtrlModelGet()) {
 		case MV_BOBK_CETUS_98DX4235_DEV_ID:
+		case MV_BOBK_LEWIS_98DX8212_DEV_ID:
+			/* LEWIS RD board's CPU freq setting is the same as CETUS board */
 			freqMhz = bobkCetusClockRatioTbl[idx].ddrFreq * 1000000;
 			break;
 		case MV_BOBK_CAELUM_98DX4203_DEV_ID:
@@ -225,6 +229,8 @@
 	else if (family == MV_BOBK_DEV_ID) {
 		switch (mvCtrlModelGet()) {
 		case MV_BOBK_CETUS_98DX4235_DEV_ID:
+		case MV_BOBK_LEWIS_98DX8212_DEV_ID:
+			/* LEWIS RD board's CPU freq setting is the same as CETUS board */
 			freqMhz = bobkCetusClockRatioTbl[idx].pllClk * 1000000;
 			break;
 		case MV_BOBK_CAELUM_98DX4203_DEV_ID:
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
index 2d25242..17cec27 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
@@ -132,11 +132,12 @@
 /* PNC_UNIT_ID		*/ { 0,		0,		1,		0,},
 };
 
-MV_U32  mvDev2CpuMapTable[19][2] = {
+MV_U32  mvDev2CpuMapTable[20][2] = {
 /*	Dev ID			cores#   */
 	{MV_BOBCAT2_DEV_ID,		2},
 	{MV_BOBK_CETUS_98DX4235_DEV_ID,		2},
 	{MV_BOBK_CAELUM_98DX4203_DEV_ID,	2},
+	{MV_BOBK_LEWIS_98DX8212_DEV_ID,	2},
 	{MV_ALLEYCAT3_98DX3336_DEV_ID,	2},
 	{MV_ALLEYCAT3_98DX3335_DEV_ID,	2},
 	{MV_ALLEYCAT3_98DX3334_DEV_ID,	2},