| commit | c86e92c028416025c4490465121bd2a55a74d28c | [log] [tgz] |
|---|---|---|
| author | Margarita Granov <margra@marvell.com> | Wed Oct 14 17:08:50 2015 +0200 |
| committer | Greg Poist <poist@google.com> | Thu Mar 24 11:59:54 2016 -0700 |
| tree | 7a57feb1c9a12277250aa4ed125f1589325ada46 | |
| parent | 9ea0193403a83378b4db5e8a4c92181bae266cf5 [diff] |
fix: ddr3libv2: bobk: Support WM (for CPSS) in TM controller select Initialize devID variable in ASIC_SIMULATION mode. Change-Id: I426372727ad035d5320ee154c544a1d2f3dae8e7 Signed-off-by: Margarita Granov <margra@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/24013 Reviewed-by: Haim Boot <hayim@marvell.com> Tested-by: Haim Boot <hayim@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/24173 Reviewed-by: Omri Itach <omrii@marvell.com> Tested-by: Omri Itach <omrii@marvell.com>
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c index d4388dc..35f614c 100755 --- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c +++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
@@ -481,10 +481,12 @@ ) { GT_U32 interfaceId = 0, dataValue = 0; - +#ifndef ASIC_SIMULATION CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, 0x000F8240 , &devId, MASK_ALL_BITS)); - - if ((devId &0xFFFF) == CETUS_DEV_ID ) +#else + devId = 0xBC00; /* CAELUM_DEV_ID */ +#endif + if ((devId & 0xFFFF) == CETUS_DEV_ID ) { /* IN Cetus TM has only 1 IF #0*/ hwMaxDdrIfNum = 1;