tree edde0033a42ccde40c9da5d544a92264fb22daac
parent 837f4f1a60dc384918307d8c7346619f78f2d4ab
author Igor Patrik <igorp@marvell.com> 1431612530 +0300
committer Greg Poist <poist@google.com> 1458845994 -0700

ddr: Added support for SatR reflck 40Mhz

	Skipped write to PLL, the value not align to 40Mhz.
	Added defines for this SatR field
	Added different freq SatR values depend on reflck SatR
	Added new VCO table with data rigth for 40Mhz

Change-Id: Ia2c1bb2f49ee6dbab61081e5383c7909985a08d9
Signed-off-by: Igor Patrik <igorp@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/19232
Tested-by: Star_Automation <star@marvell.com>
Tested-by: Star_New_DDR <star-new-ddr@marvell.com>
Reviewed-by: Haim Boot <hayim@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24099
Tested-by: Omri Itach <omrii@marvell.com>