)]}' { "commit": "c8692ed60827047330baaf9aa92faaa0acfd6e8f", "tree": "edde0033a42ccde40c9da5d544a92264fb22daac", "parents": [ "837f4f1a60dc384918307d8c7346619f78f2d4ab" ], "author": { "name": "Igor Patrik", "email": "igorp@marvell.com", "time": "Thu May 14 17:08:50 2015 +0300" }, "committer": { "name": "Greg Poist", "email": "poist@google.com", "time": "Thu Mar 24 11:59:54 2016 -0700" }, "message": "ddr: Added support for SatR reflck 40Mhz\n\n\tSkipped write to PLL, the value not align to 40Mhz.\n\tAdded defines for this SatR field\n\tAdded different freq SatR values depend on reflck SatR\n\tAdded new VCO table with data rigth for 40Mhz\n\nChange-Id: Ia2c1bb2f49ee6dbab61081e5383c7909985a08d9\nSigned-off-by: Igor Patrik \u003cigorp@marvell.com\u003e\nReviewed-on: http://vgitil04.il.marvell.com:8080/19232\nTested-by: Star_Automation \u003cstar@marvell.com\u003e\nTested-by: Star_New_DDR \u003cstar-new-ddr@marvell.com\u003e\nReviewed-by: Haim Boot \u003chayim@marvell.com\u003e\nReviewed-by: Omri Itach \u003comrii@marvell.com\u003e\nReviewed-on: http://vgitil04.il.marvell.com:8080/24099\nTested-by: Omri Itach \u003comrii@marvell.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "66f61380260ade73f5227731c2341fcf53050f44", "old_mode": 33261, "old_path": "tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.h", "new_id": "faa3c460ffae8a6ac9484717e4c2ca0b8728f068", "new_mode": 33261, "new_path": "tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.h" }, { "type": "modify", "old_id": "5d4a159aa48ad800e513a78d40ffece874bdb8ac", "old_mode": 33261, "old_path": "tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c", "new_id": "e5efe52f60d6eef3c5653d39f58605ac744e9a69", "new_mode": 33261, "new_path": "tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c" }, { "type": "modify", "old_id": "da5af0aa0caff42f91efd83ae41461838002fb3b", "old_mode": 33188, "old_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/Makefile", "new_id": "8ab899079e57f95cdb5d2bdc900022b5ada6b575", "new_mode": 33188, "new_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/Makefile" }, { "type": "modify", "old_id": "467ea1d6cfe05e329cd0ebc8b3d8cead88c70e45", "old_mode": 33261, "old_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c", "new_id": "330f733f21e510f0193fc57fca578c519baa9606", "new_mode": 33261, "new_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c" }, { "type": "modify", "old_id": "2687275ed4d16b82ae8c3cf01c522b042ba70909", "old_mode": 33261, "old_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c", "new_id": "741a1fa845d8d14edecb09dcd9bb3725e4019eaa", "new_mode": 33261, "new_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c" }, { "type": "modify", "old_id": "81ab0a3dfa0a903c1f3c82965a0b62a16d41288d", "old_mode": 33188, "old_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c", "new_id": "7dced0311bbfc7b03264bf6c4ec8ea3e54bdc17d", "new_mode": 33188, "new_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c" }, { "type": "modify", "old_id": "ca0263e178c68059d9aa9b84ef25a92076984468", "old_mode": 33188, "old_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c", "new_id": "9f04bc0f285bb90e70a4d82382894168faf5eb96", "new_mode": 33188, "new_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c" }, { "type": "modify", "old_id": "30e3b155732f4e17e07227d099b69603e36e5658", "old_mode": 33261, "old_path": "tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedEnvSpec.c", "new_id": "a805e615639e96c85053137776a0113b76ac5971", "new_mode": 33261, "new_path": "tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedEnvSpec.c" } ] }