tools/marvell/bin_hdr/src_init/a370/bin_sramcfg.c

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#include "mv_os.h"
#include "config_marvell.h"     /* Required to identify SOC and Board */
#include "soc_spec.h"
#ifdef MV88F67XX
#include "generalInit.h"

#define REG_XBAR_WIN_19_CTRL_ADDR	0x200e8

MV_VOID sramConfig(void)
{
	MV_U32 *ptr;

	/* disable DRAM Window */
	MV_REG_WRITE(REG_XBAR_WIN_19_CTRL_ADDR, 0x1FFF0E00);	/*Close Mbus Window - 1G */

	/* Fix L2 way 0 size to 256KB */
	MV_REG_WRITE(0x20240,0x40000301);

	/* set L2 way 3 to SRAM at 0 */
	MV_REG_WRITE(0x850C,0x1);
	MV_REG_WRITE(0x20244,0x001);

	ptr = (void*)0x10;
	*ptr = 0xE3A0F02C;		/* mov pc,#0x2C */
	ptr = (void*)0x2C;
	*ptr = 0xE24EE008;		/* sub r14,r14,#0x8 */
	ptr = (void*)0x30;
	*ptr = 0xE1B0F00E;		/* movs pc,r14 */

	changeResetVecBase(0);

	/* remove CPSR bit 8 - don't mask data abort - now we should get data abort */
	setCPSR(0);

	setCPSR(1<<8);

	changeResetVecBase(1<<13);

	/* close L2 way 3 to SRAM at 0 */
	MV_REG_WRITE(0x850C,0x0);
	MV_REG_WRITE(0x20244,0x000);

	/* enable DRAM Window */
	MV_REG_WRITE(REG_XBAR_WIN_19_CTRL_ADDR, 0x1FFF0E01);	/*Close Mbus Window - 1G */
}
#endif /* MV88F67XX */