ddr: Added support for SatR reflck 40Mhz
Skipped write to PLL, the value not align to 40Mhz.
Added defines for this SatR field
Added different freq SatR values depend on reflck SatR
Added new VCO table with data rigth for 40Mhz
Change-Id: Ia2c1bb2f49ee6dbab61081e5383c7909985a08d9
Signed-off-by: Igor Patrik <igorp@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/19232
Tested-by: Star_Automation <star@marvell.com>
Tested-by: Star_New_DDR <star-new-ddr@marvell.com>
Reviewed-by: Haim Boot <hayim@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24099
Tested-by: Omri Itach <omrii@marvell.com>
diff --git a/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.h b/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.h
index 66f6138..faa3c46 100755
--- a/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.h
+++ b/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.h
@@ -86,6 +86,10 @@
#define DEVICE_SAMPLE_AT_RESET2_REG 0x18604
#define DEV_ID_REG 0x18238
+#define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET 0
+#define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ 0
+#define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_40MHZ 1
+
#define CORE_PLL_PARAMETERS_REG 0xE42E0
#define CORE_PLL_CONFIG_REG 0xE42E4
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c b/tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c
index 5d4a159..e5efe52 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3_init_tipv2.c
@@ -411,9 +411,12 @@
/*Set log level for training lib*/
ddr3HwsSetLogLevel(MV_DEBUG_BLOCK_ALL, DEBUG_LEVEL_ERROR);
+ /*ddr3HwsSetLogLevel(MV_DEBUG_TRAINING_MAIN, DEBUG_LEVEL_TRACE);*/
+
#ifdef MV_RUN_WIN_VALIDATION_TEST /* to run DDR viewer tool (to display DDR training results) */
mvHwsDdr3TipSweepTest(MV_TRUE);
#endif
+
/*Start New Training IP*/
status = ddr3HwsHwTraining();
if (MV_OK != status) {
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/Makefile b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/Makefile
index da5af0a..8ab8990 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/Makefile
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/Makefile
@@ -66,10 +66,12 @@
include ../../base.mk
TIP_INC = $(BH_ROOT_DIR)/src_ddr/ddr3libv2/h
-INCLUDE =
-INCLUDE = -I$(TIP_INC)/Os -I$(TIP_INC)/Os/gtOs -I$(TIP_INC)/Os/common/siliconIf -I$(TIP_INC)/SoC -I$(TIP_INC)/Silicon -I$(TIP_INC)/Os/common/configElementDb \
- -I$(TIP_INC)/Driver -I$(TIP_INC)/Driver/ddr3 -I$(BH_ROOT_DIR)/inc/common -I$(BH_ROOT_DIR)/inc/ddr3_soc/$(BOARD) -I$(BH_ROOT_DIR)/inc/ddr3_soc/$(INCNAME) -I$(BH_ROOT_DIR)/src_ddr
+INCLUDE = -I$(TIP_INC)/Os -I$(TIP_INC)/Os/gtOs -I$(TIP_INC)/Os/common/siliconIf \
+ -I$(TIP_INC)/SoC -I$(TIP_INC)/Silicon -I$(TIP_INC)/Os/common/configElementDb \
+ -I$(TIP_INC)/Driver -I$(TIP_INC)/Driver/ddr3 -I$(BH_ROOT_DIR)/inc/common \
+ -I$(BH_ROOT_DIR)/inc/ddr3_soc/$(BOARD) -I$(BH_ROOT_DIR)/inc/ddr3_soc/$(INCNAME) \
+ -I$(BH_ROOT_DIR)/src_ddr -I$(BH_ROOT_DIR)/platform/sysEnv/$(BOARD)
ifeq ($(DDRTYPE),ddr4)
INCLUDE += -I$(BH_ROOT_DIR)/src_ddr/ddr3libv2/src/Driver/ddr4/h
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c
index 467ea1d..330f733 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c
@@ -55,28 +55,10 @@
extern MV_HWS_DDR_FREQ mediumFreq;
extern GT_U8 calibrationUpdateControl; /*2 external only, 1 is internal only*/
extern GT_U32 dfsLowFreq;
+extern GT_U32 freqVal[];
GT_U32 pipeMulticastMask;
-static GT_U16 freqVal[DDR_FREQ_LIMIT] =
-{
- 130, /*DDR_FREQ_LOW_FREQ*/
- 400, /*DDR_FREQ_400,*/
- 533, /*DDR_FREQ_533,*/
- 666, /*DDR_FREQ_667,*/
- 800, /*DDR_FREQ_800,*/
- 933, /*DDR_FREQ_933,*/
- 1066, /*DDR_FREQ_1066,*/
- 311, /*DDR_FREQ_311,*/
- 333, /*DDR_FREQ_333,*/
- 467, /*DDR_FREQ_467,*/
- 850, /*DDR_FREQ_850,*/
- 600, /*DDR_FREQ_600,*/
- 300, /*DDR_FREQ_300,*/
- 900, /*DDR_FREQ_900*/
- 360 /*DDR_FREQ_360*/
-};
-
static GT_U8 Ac3BwPerFreq[DDR_FREQ_LIMIT] =
{
0x3, /*DDR_FREQ_100*/
@@ -464,7 +446,7 @@
delayEnable = 1;
caDelay = 0;
calibrationUpdateControl = 1;
- dfsLowFreq = 130;
+ freqVal[DDR_FREQ_LOW_FREQ] = dfsLowFreq = 130;
initFreq = topologyMap->interfaceParams[interfaceId].memoryFreq;
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
index 2687275..741a1fa 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
@@ -834,7 +834,7 @@
/* frequency and general parameters */
ddr3TipBc2GetMediumFreq(devNum, firstActiveIf, &mediumFreq);
initFreq = topologyMap->interfaceParams[firstActiveIf].memoryFreq;
- dfsLowFreq = 100;
+ freqVal[DDR_FREQ_LOW_FREQ] = dfsLowFreq = 100;
dfsLowPhy1 = PhyReg1Val;
isPllBeforeInit = 0;
useBroadcast = GT_FALSE; /* multicast */
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c
index 81ab0a3..7dced03 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c
@@ -960,7 +960,7 @@
ckDelay = 150;
caDelay = 0;
calibrationUpdateControl = 1;
- dfsLowFreq = 100;
+ freqVal[DDR_FREQ_LOW_FREQ] = dfsLowFreq = 100;
return GT_OK;
}
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
index ca0263e..9f04bc0 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
@@ -25,6 +25,7 @@
#include "ddr3_a38x_tip_training_static.h"
#include "ddr3_hws_sil_training.h"
#include "mvXor.h"
+#include "mvSysEnvLib.h"
#include "mvHwsDdr3A38x.h"
#include "mvSiliconIf.h"
@@ -62,42 +63,12 @@
extern GT_U32 maskTuneFunc;
extern GT_BOOL rlMidFreqWA;
extern GT_U8 calibrationUpdateControl; /*2 external only, 1 is internal only*/
+extern GT_U32 freqVal[];
-
-#ifdef CONFIG_DDR3
-static GT_U16 freqVal[DDR_FREQ_LIMIT] =
-{
- 120, /*DDR_FREQ_LOW_FREQ*/
- 400, /*DDR_FREQ_400,*/
- 533, /*DDR_FREQ_533,*/
- 666, /*DDR_FREQ_667,*/
- 800, /*DDR_FREQ_800,*/
- 933, /*DDR_FREQ_933,*/
- 1066, /*DDR_FREQ_1066,*/
- 311, /*DDR_FREQ_311,*/
- 333, /*DDR_FREQ_333,*/
- 467, /*DDR_FREQ_467,*/
- 850, /*DDR_FREQ_850,*/
- 600, /*DDR_FREQ_600,*/
- 300, /*DDR_FREQ_300,*/
- 900, /*DDR_FREQ_900*/
- 360, /*DDR_FREQ_360*/
- 1000 /*DDR_FREQ_1000*/
-};
-#else /* CONFIG_DDR4 */
-static GT_U16 freqVal[DDR_FREQ_LIMIT] =
-{
- 120, /* DDR_FREQ_LOW_FREQ */
- 666, /* DDR_FREQ_667 */
- 800, /* DDR_FREQ_800 */
- 933, /* DDR_FREQ_933 */
- 1066, /* DDR_FREQ_1066 */
- 900, /*DDR_FREQ_900*/
- 1000 /*DDR_FREQ_1000*/
-};
-
+#ifdef CONFIG_DDR4
extern GT_U8 vrefCalibrationWA; /*1 means SSTL & POD gets the same Vref and a WA is needed*/
#endif
+
extern MV_HWS_DDR_FREQ mediumFreq;
extern GT_STATUS ddr3TipRegWrite
@@ -203,7 +174,6 @@
static GT_U8 A38xRatePerFreq[DDR_FREQ_LIMIT] =
{
-/*TBD*/
0x1, /*DDR_FREQ_100*/
#ifdef CONFIG_DDR3
0x2, /*DDR_FREQ_400*/
@@ -230,7 +200,7 @@
#endif
};
-static GT_U16 A38xVcoFreqPerSar[] =
+static GT_U16 A38xVcoFreqPerSarRefClk25Mhz[] =
{
666, /*0*/
1332,
@@ -265,6 +235,41 @@
800
};
+static GT_U16 A38xVcoFreqPerSarRefClk40Mhz[] =
+{
+ 666, /*0*/
+ 1332,
+ 800,
+ 800, /*0x3*/
+ 1066,
+ 1066, /*0x5*/
+ 1200,
+ 2400,
+ 1332,
+ 1332,
+ 1500,/*10*/
+ 1600, /*0xB*/
+ 1600,
+ 1600,
+ 1700,
+ 1560, /*0xF*/
+ 1866,
+ 1866,
+ 1800,
+ 2000,
+ 2000,/*20*/
+ 4000,
+ 2132,
+ 2132,
+ 2300,
+ 2300,
+ 2400,
+ 2400,
+ 2500,
+ 2500,
+ 1800 /*30 - 0x1E*/
+};
+
GT_U16 A38xODTSlope[] =
{
21443,
@@ -644,7 +649,7 @@
ckDelay = 160;
caDelay = 0;
delayEnable = 1;
- dfsLowFreq = 120;
+ freqVal[DDR_FREQ_LOW_FREQ] = dfsLowFreq = 120;
calibrationUpdateControl = 1;
#ifdef CONFIG_ARMADA_38X
@@ -698,56 +703,82 @@
MV_HWS_DDR_FREQ *freq
)
{
- GT_U32 uiReg;
+ GT_U32 uiReg, refClkSatR;
/* Read sample at reset setting */
uiReg = (MV_REG_READ(REG_DEVICE_SAR1_ADDR)>> RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) & RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
- switch(uiReg) {
-#ifdef CONFIG_DDR3
- case 0x1:
- mvPrintf("Warning: Unsupported freq mode for 333Mhz configured(%d)\n", uiReg);
- case 0x0:
- *freq = DDR_FREQ_333;
- break;
- case 0x3:
- mvPrintf("Warning: Unsupported freq mode for 400Mhz configured(%d)\n", uiReg);
- case 0x2:
- *freq = DDR_FREQ_400;
- break;
- case 0xd:
- mvPrintf("Warning: Unsupported freq mode for 533Mhz configured(%d)\n", uiReg);
- case 0x4:
- *freq = DDR_FREQ_533;
- break;
- case 0x6:
- *freq = DDR_FREQ_600;
- break;
-#endif
- case 0x11:
- case 0x14:
- mvPrintf("Warning: Unsupported freq mode for 667Mhz configured(%d)\n", uiReg);
- case 0x8:
- *freq = DDR_FREQ_667;
- break;
- case 0x15:
- case 0x1b:
- mvPrintf("Warning: Unsupported freq mode for 800Mhz configured(%d)\n", uiReg);
- case 0xC:
- *freq = DDR_FREQ_800;
- break;
- case 0x10:
- *freq = DDR_FREQ_933;
- break;
- case 0x12:
- *freq = DDR_FREQ_900;
- break;
- case 0x13:
- *freq = DDR_FREQ_1000;
- break;
- default:
- *freq = 0;
- return MV_NOT_SUPPORTED;
- }
+
+ refClkSatR = MV_REG_READ(DEVICE_SAMPLE_AT_RESET2_REG);
+ if(((refClkSatR >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ){
+ switch(uiReg) {
+ #ifdef CONFIG_DDR3
+ case 0x1:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Warning: Unsupported freq mode for 333Mhz configured(%d)\n", uiReg));
+ case 0x0:
+ *freq = DDR_FREQ_333;
+ break;
+ case 0x3:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Warning: Unsupported freq mode for 400Mhz configured(%d)\n", uiReg));
+ case 0x2:
+ *freq = DDR_FREQ_400;
+ break;
+ case 0xd:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Warning: Unsupported freq mode for 533Mhz configured(%d)\n", uiReg));
+ case 0x4:
+ *freq = DDR_FREQ_533;
+ break;
+ case 0x6:
+ *freq = DDR_FREQ_600;
+ break;
+ #endif
+ case 0x11:
+ case 0x14:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Warning: Unsupported freq mode for 667Mhz configured(%d)\n", uiReg));
+ case 0x8:
+ *freq = DDR_FREQ_667;
+ break;
+ case 0x15:
+ case 0x1b:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Warning: Unsupported freq mode for 800Mhz configured(%d)\n", uiReg));
+ case 0xC:
+ *freq = DDR_FREQ_800;
+ break;
+ case 0x10:
+ *freq = DDR_FREQ_933;
+ break;
+ case 0x12:
+ *freq = DDR_FREQ_900;
+ break;
+ case 0x13:
+ *freq = DDR_FREQ_1000;
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Warning: Unsupported freq mode for 1000Mhz configured(%d)\n", uiReg));
+ break;
+ default:
+ *freq = 0;
+ return MV_NOT_SUPPORTED;
+ }
+ }
+ else{ /*REFCLK 40 MHZ case*/
+ switch(uiReg) {
+ #ifdef CONFIG_DDR3
+ case 0x3:
+ *freq = DDR_FREQ_400;
+ break;
+ case 0x5:
+ *freq = DDR_FREQ_533;
+ break;
+ #endif
+ case 0xB:
+ *freq = DDR_FREQ_800;
+ break;
+ case 0x1E:
+ *freq = DDR_FREQ_900;
+ break;
+ default:
+ *freq = 0;
+ return MV_NOT_SUPPORTED;
+ }
+ }
return GT_OK;
}
@@ -758,51 +789,75 @@
MV_HWS_DDR_FREQ *freq
)
{
- GT_U32 uiReg;
+ GT_U32 uiReg, refClkSatR;
/* Read sample at reset setting */
uiReg = (MV_REG_READ(REG_DEVICE_SAR1_ADDR)>> RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) & RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
- switch(uiReg) {
- case 0x1:
- case 0x0:
- *freq = DDR_FREQ_333; /*Medium is same as TF to run PBS in this freq*/
- break;
- case 0x3:
- case 0x2:
- *freq = DDR_FREQ_400; /*Medium is same as TF to run PBS in this freq*/
- break;
- case 0xd:
- case 0x4:
- *freq = DDR_FREQ_533;
- break;
- case 0x8:
- case 0x11:
- case 0x14:
- case 0x10:
- *freq = DDR_FREQ_333;
- break;
- case 0x15:
- case 0x1b:
- case 0xC:
- *freq = DDR_FREQ_400;
- break;
- case 0x6:
- *freq = DDR_FREQ_300;
- break;
- case 0x12:
- *freq = DDR_FREQ_360;
- break;
- case 0x13:
- *freq = DDR_FREQ_400;
- break;
- default:
- *freq = 0;
- return MV_NOT_SUPPORTED;
- }
+
+ refClkSatR = MV_REG_READ(DEVICE_SAMPLE_AT_RESET2_REG);
+ if(((refClkSatR >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ){
+ switch(uiReg) {
+ case 0x1:
+ case 0x0:
+ *freq = DDR_FREQ_333; /*Medium is same as TF to run PBS in this freq*/
+ break;
+ case 0x3:
+ case 0x2:
+ *freq = DDR_FREQ_400; /*Medium is same as TF to run PBS in this freq*/
+ break;
+ case 0xd:
+ case 0x4:
+ *freq = DDR_FREQ_533;/*Medium is same as TF to run PBS in this freq*/
+ break;
+ case 0x8:
+ case 0x11:
+ case 0x14:
+ case 0x10:
+ *freq = DDR_FREQ_333;
+ break;
+ case 0x15:
+ case 0x1b:
+ case 0xC:
+ *freq = DDR_FREQ_400;
+ break;
+ case 0x6:
+ *freq = DDR_FREQ_300;
+ break;
+ case 0x12:
+ *freq = DDR_FREQ_360;
+ break;
+ case 0x13:
+ *freq = DDR_FREQ_400;
+ break;
+ default:
+ *freq = 0;
+ return MV_NOT_SUPPORTED;
+ }
+ }
+ else{ /*REFCLK 40 MHZ case*/
+ switch(uiReg) {
+ case 0x3:
+ *freq = DDR_FREQ_400;/*Medium is same as TF to run PBS in this freq*/
+ break;
+ case 0x5:
+ *freq = DDR_FREQ_533;/*Medium is same as TF to run PBS in this freq*/
+ break;
+ case 0xB:
+ *freq = DDR_FREQ_400;
+ break;
+ case 0x1E:
+ *freq = DDR_FREQ_360;
+ break;
+ default:
+ *freq = 0;
+ return MV_NOT_SUPPORTED;
+ }
+ }
return GT_OK;
}
#endif
+
GT_U32 ddr3TipGetInitFreq()
{
MV_HWS_DDR_FREQ freq;
@@ -822,7 +877,7 @@
)
{
GT_U32 divider = 0;
- GT_U32 sarVal;
+ GT_U32 sarVal, refClkSatR;
if (interfaceId != 0) {
DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("A38x does not support interface 0x%x\n", interfaceId));
@@ -832,8 +887,13 @@
/* get VCO freq index */
sarVal = (MV_REG_READ(REG_DEVICE_SAR1_ADDR)>> RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) & RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
- divider = A38xVcoFreqPerSar[sarVal]/freqVal[frequency];
-
+ refClkSatR = MV_REG_READ(DEVICE_SAMPLE_AT_RESET2_REG);
+ if(((refClkSatR >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ){
+ divider = A38xVcoFreqPerSarRefClk25Mhz[sarVal]/freqVal[frequency];
+ }
+ else{
+ divider = A38xVcoFreqPerSarRefClk40Mhz[sarVal]/freqVal[frequency];
+ }
/*Set Sync mode*/
CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0x20220, 0x0, 0x1000));
CHECK_STATUS(ddr3TipA38xIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0xE42F4, 0x0, 0x200));
diff --git a/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedEnvSpec.c b/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedEnvSpec.c
index 30e3b15..a805e61 100755
--- a/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedEnvSpec.c
+++ b/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedEnvSpec.c
@@ -348,7 +348,7 @@
{ G2_SETTINGS_1_REG, 0x800, 0x3FF, { 0x3D2 }, 0, 0 }, /* G2_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI */
{ G3_SETTINGS_0_REG, 0x800, 0xFFFF, { 0xE6E }, 0, 0 }, /* G3_TX SLEW, EMPH1 and AMP */
{ G3_SETTINGS_1_REG, 0x800, 0x47FF, { 0x7D2 }, 0, 0 }, /* G3_RX SELMUFF, SELMUFI, SELMUPF and SELMUPI & DFE_En Gen3, DC wander calibration dis */
- { PCIE_REG0, 0x800, 0x1000, { 0x0 }, 0, 0 }, /* Bit[12]=0x0 idle_sync_en */
+ { PCIE_REG0, 0x800, 0x1000, { 0x0 }, 0, 0 }, /* Bit[12]=0x0 idle_sync_en */
{ RX_REG2, 0x800, 0xF0, { 0x70, }, 0, 0 }, /* Dtl Clamping disable and Dtl clamping Sel(6000ppm) */
{ VTHIMPCAL_CTRL_REG, 0x800, 0xFF00, { 0x3000 }, 0, 0 }, /* tximpcal_th and rximpcal_th */
{ DFE_REG0, 0x800, 0xA00F, { 0x800A }, 0, 0 }, /* DFE_STEP_FINE_FX[3:0] =0xA */
@@ -432,14 +432,14 @@
{ LANE_CFG4_REG, 0x800, 0xC2, { 0xC0 }, 0, 0 }, /* Bit[7]=0x1 - Spread Spectrum Clock Enable,Bit[6]-0x1- CFG_DFE_OVERRIDE,Bit[1]-0x0-PIN_DFE_PAT_DIS, */
{ LANE_CFG5_REG, 0x800, 0x3, { 0x3 }, 0, 0 }, /* Bit[1]=0x1 - CFG_SQ_DET_SEL,Bit[0]=0x1-CFG_RX_INIT_SEL, */
{ G2_SETTINGS_2_REG, 0x800, 0xFE40, { 0x4440 }, 0, 0 }, /* Bits[15:9]= 0x22 -G2_TX_SSC_AMP[6:0]=4.5kPPM,Bits[6] = 0x1 - TX emphasis mode=mV */
- { G2_SETTINGS_3_REG, 0x800, 0xFF, { 0xEF }, 0, 0 }, /* Bit[7] =0x1 FFE Setting Force;Bits[6:4]=0x6 FFE_RES;Bits[3:0] = 0xF FFE_CAP; */
+ { G2_SETTINGS_3_REG, 0x800, 0xFF, { 0xEF }, 0, 0 }, /* Bit[7] =0x1 FFE Setting Force;Bits[6:4]=0x6 FFE_RES;Bits[3:0] = 0xF FFE_CAP; */
{ G2_SETTINGS_4_REG, 0x800, 0x300, { 0x300 }, 0, 0 }, /* Bits[9:8]=0x0 - G2_DFE_RES[1:0]*/
- { PLLINTP_REG1, 0x800, 0x300, { 0x300 }, 0, 0 }, /* Bits[9:8]=0x3 HPF_Bw[1:0] */
+ { PLLINTP_REG1, 0x800, 0x300, { 0x300 }, 0, 0 }, /* Bits[9:8]=0x3 HPF_Bw[1:0] */
{ VTHIMPCAL_CTRL_REG, 0x800, 0xFF00, { 0x3000 }, 0, 0 }, /* Bits[15:12]= 0x3 - tximpcal_th;Bits[11:8] = 0x0 - RXIMPCAL_TH */
{ LANE_CFG5_REG, 0x800, 0x3, { 0x3 }, 0, 0 }, /* Bit[1]=0x1 - CFG_SQ_DET_SEL,Bit[0]=0x1-CFG_RX_INIT_SEL, */
- { MISC_REG, 0x800, 0x42F, { 0x42A }, 0, 0 }, /* Bit[10]=0x1 - REFCLK_SEL(=25Mhz);Bit[5]=0x1 ICP_FORCE_En;Bits[3:0]=0xA ICP=0xA(210uA); */
+ { MISC_REG, 0x800, 0x42F, { 0x42A }, 0, 0 }, /* Bit[10]=0x1 - REFCLK_SEL(=25Mhz);Bit[5]=0x1 ICP_FORCE_En;Bits[3:0]=0xA ICP=0xA(210uA); */
{ POWER_AND_PLL_CTRL_REG, 0x800, 0x1F, { 0x02 }, 0, 0 }, /* Bits[4:0] =0x2 - REF_FREF_SEL(=25Mhz) */
- { G2_SETTINGS_1_REG, 0x800, 0x3FF, { 0x3D2 }, 0, 0 }, /* Bits[9:8]=0x3- G2_RX_SELMUFF;Bits[7:6]=0x3- G2_RX_SELMUFI;Bits[5:3]=0x2 G2_RX_SELMUPF;Bits[2:0]=0x2 - G2_RX_SELMUPI*/
+ { G2_SETTINGS_1_REG, 0x800, 0x3FF, { 0x3D2 }, 0, 0 }, /* Bits[9:8]=0x3- G2_RX_SELMUFF;Bits[7:6]=0x3- G2_RX_SELMUFI;Bits[5:3]=0x2 G2_RX_SELMUPF;Bits[2:0]=0x2 - G2_RX_SELMUPI*/
{ RX_REG2, 0x800, 0xF0, { 0x70 }, 0, 0 }, /* Dtl Clamping disable and Dtl-clamping-Sel(6000ppm) */
{ PCIE_REG1, 0x800, 0xF80, { 0xD00 }, 0, 0 }, /* Bits[11:7]=0x1a - tx_amp_pipe_v0[4:0] */
{ REF_REG0, 0x800, 0x38, { 0x20 }, 0, 0 }, /* vco_cal_vth_sel */
@@ -1144,7 +1144,7 @@
/***************************************************************************/
MV_STATUS mvHwsPreSerdesInitConfig(MV_VOID)
{
- MV_U32 data;
+ MV_U32 data, refClkSatR;
/* configure Core PLL */
/*
@@ -1154,8 +1154,13 @@
bits[24:21]=0x7(Core-PLL VCO Band)
bits[28:25]=0x1(Core-PLL Rlf)
bits[31:29]=0x2(Core-PLL charge-pump adjust)
+ (the configuration valid only for refclk 25Mhz, for 40Mhz better default configuration at this time)
*/
- MV_REG_WRITE(CORE_PLL_PARAMETERS_REG, 0x42E9F003);
+ refClkSatR = MV_REG_READ(DEVICE_SAMPLE_AT_RESET2_REG);
+ if(((refClkSatR >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ){
+ /*Skip the configuration in REFLK 40Mhz mode*/
+ MV_REG_WRITE(CORE_PLL_PARAMETERS_REG, 0x42E9F003);
+ }
/* Enable PLL Configuration */
data = MV_REG_READ(CORE_PLL_CONFIG_REG);
