spi: a38x, a39x: Implement "50MHZ SPI AC timing" Erratum No. FE-9144572
Description:
The device SPI interface supports frequencies of up to 50 MHz.
However, due to this erratum, when the device core clock is 250 MHz
and the SPI interfaces is configured for 50MHz
SPI clock and CPOL=CPHA=1, there might occur data corruption on reads
from the SPI device.
Workaround:
Work in one of the following configurations:
1. Set CPOL=CPHA=0 in "SPI Interface Configuration Register".
2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1 Register"
before setting the interface.
* Selected 2nd option, since Alley-Cat3 share the same solution to avoid timing SPI issues
Change-Id: Ibb8f8fd76de2adeec9846bd7f5df90922dad3910
Signed-off-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/19668
Tested-by: Star_Automation <star@marvell.com>
2 files changed
