fix: msys_ac3: disable PCIe Polarity (via CPLD) for non-DB boards
PCIe connector is not supported on non-DB boards,
for non DB boards, the PCIe is used to connect the internal CPUs.
Thus the PCIe polarity does not have control via CPLD.
- Before, mvCtrlPexPolaritySet was trying to write to i2c CPLD
register that controls the polarity (address: 0x18, reg:0x1A),
and the device does not exist on non-DB boards.
- disable mvCtrlPexPolaritySet for AC3 non-DB boards.
- Fixed JIRA:SYSTEMSW-1689
Change-Id: Ic6cca97547488557607743d58e14c8211f2c9544
Signed-off-by: Bassel Saba <basselsa@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/18052
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
1 file changed
