| commit | b836c7f9cd9d8aac2d6889ae665a2cb5bbd37176 | [log] [tgz] |
|---|---|---|
| author | Igor Petrik <igorp@marvell.com> | Wed May 20 08:49:04 2015 +0300 |
| committer | Greg Poist <poist@google.com> | Thu Mar 24 11:59:54 2016 -0700 |
| tree | b9022a34c306cc79bc21b61e3d0e9ba271fd8606 | |
| parent | 385da43fc5b57a36639a2f0289f1c4f80fdaa0c2 [diff] |
fix: ddr: msys_bc2: Fixed DDR bus width indication - BC2 have 64/32 DDR bus width: fixed U-Boot print of DDR bus width - previous configuration kept, since valid for AC3: 32/16 DDR bus width Change-Id: I74776e1ba154920a5ac64f34dcf055329bfa5acc Signed-off-by: Igor Petrik <igorp@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/19383 Tested-by: Star_Automation <star@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com>